diff -uprN binutils-2.16.91.0.1/bfd/aix5ppc-core.c binutils-2.16.91.0.2/bfd/aix5ppc-core.c --- binutils-2.16.91.0.1/bfd/aix5ppc-core.c 2005-05-10 15:46:40.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/aix5ppc-core.c 2005-07-20 12:27:26.946250254 -0700 @@ -2,7 +2,7 @@ Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc. Written by Tom Rix - Contributed by Redhat. + Contributed by Red Hat Inc. This file is part of BFD, the Binary File Descriptor library. @@ -28,14 +28,10 @@ #include "sysdep.h" #include "libbfd.h" -const bfd_target *xcoff64_core_p - PARAMS ((bfd *)); -bfd_boolean xcoff64_core_file_matches_executable_p - PARAMS ((bfd *, bfd *)); -char *xcoff64_core_file_failing_command - PARAMS ((bfd *)); -int xcoff64_core_file_failing_signal - PARAMS ((bfd *)); +const bfd_target *xcoff64_core_p (bfd *); +bfd_boolean xcoff64_core_file_matches_executable_p (bfd *, bfd *); +char *xcoff64_core_file_failing_command (bfd *); +int xcoff64_core_file_failing_signal (bfd *); /* Aix 5.1 system include file. */ @@ -50,8 +46,7 @@ int xcoff64_core_file_failing_signal ((bfd_signed_vma)(v) < 0 || (bfd_signed_vma)(v) > (bfd_signed_vma)(s).st_size) const bfd_target * -xcoff64_core_p (abfd) - bfd *abfd; +xcoff64_core_p (bfd *abfd) { struct core_dumpxx core, *new_core_hdr; struct stat statbuf; @@ -111,8 +106,7 @@ xcoff64_core_p (abfd) return return_value; } - new_core_hdr = (struct core_dumpxx *) - bfd_zalloc (abfd, sizeof (struct core_dumpxx)); + new_core_hdr = bfd_zalloc (abfd, sizeof (struct core_dumpxx)); if (NULL == new_core_hdr) return return_value; @@ -232,9 +226,7 @@ xcoff64_core_p (abfd) /* Return `TRUE' if given core is from the given executable. */ bfd_boolean -xcoff64_core_file_matches_executable_p (core_bfd, exec_bfd) - bfd *core_bfd; - bfd *exec_bfd; +xcoff64_core_file_matches_executable_p (bfd *core_bfd, bfd *exec_bfd) { struct core_dumpxx core; char *path, *s; @@ -298,8 +290,7 @@ xcoff64_core_file_matches_executable_p ( } char * -xcoff64_core_file_failing_command (abfd) - bfd *abfd; +xcoff64_core_file_failing_command (bfd *abfd) { struct core_dumpxx *c = core_hdr (abfd); char *return_value = 0; @@ -311,8 +302,7 @@ xcoff64_core_file_failing_command (abfd) } int -xcoff64_core_file_failing_signal (abfd) - bfd *abfd; +xcoff64_core_file_failing_signal (bfd *abfd) { struct core_dumpxx *c = core_hdr (abfd); int return_value = 0; @@ -325,41 +315,33 @@ xcoff64_core_file_failing_signal (abfd) #else /* AIX_5_CORE */ -const bfd_target *xcoff64_core_p - PARAMS ((bfd *)); -bfd_boolean xcoff64_core_file_matches_executable_p - PARAMS ((bfd *, bfd *)); -char *xcoff64_core_file_failing_command - PARAMS ((bfd *)); -int xcoff64_core_file_failing_signal - PARAMS ((bfd *)); +const bfd_target *xcoff64_core_p (bfd *); +bfd_boolean xcoff64_core_file_matches_executable_p (bfd *, bfd *); +char *xcoff64_core_file_failing_command (bfd *); +int xcoff64_core_file_failing_signal (bfd *); const bfd_target * -xcoff64_core_p (abfd) - bfd *abfd ATTRIBUTE_UNUSED; +xcoff64_core_p (bfd *abfd ATTRIBUTE_UNUSED) { bfd_set_error (bfd_error_wrong_format); return 0; } bfd_boolean -xcoff64_core_file_matches_executable_p (core_bfd, exec_bfd) - bfd *core_bfd ATTRIBUTE_UNUSED; - bfd *exec_bfd ATTRIBUTE_UNUSED; +xcoff64_core_file_matches_executable_p (bfd *core_bfd ATTRIBUTE_UNUSED, + bfd *exec_bfd ATTRIBUTE_UNUSED) { return FALSE; } char * -xcoff64_core_file_failing_command (abfd) - bfd *abfd ATTRIBUTE_UNUSED; +xcoff64_core_file_failing_command (bfd *abfd ATTRIBUTE_UNUSED) { return 0; } int -xcoff64_core_file_failing_signal (abfd) - bfd *abfd ATTRIBUTE_UNUSED; +xcoff64_core_file_failing_signal (bfd *abfd ATTRIBUTE_UNUSED) { return 0; } diff -uprN binutils-2.16.91.0.1/bfd/archive.c binutils-2.16.91.0.2/bfd/archive.c --- binutils-2.16.91.0.1/bfd/archive.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/archive.c 2005-07-20 12:27:26.948249924 -0700 @@ -182,11 +182,13 @@ _bfd_generic_mkarchive (bfd *abfd) if (bfd_ardata (abfd) == NULL) return FALSE; - bfd_ardata (abfd)->cache = NULL; - bfd_ardata (abfd)->archive_head = NULL; - bfd_ardata (abfd)->symdefs = NULL; - bfd_ardata (abfd)->extended_names = NULL; - bfd_ardata (abfd)->tdata = NULL; + /* Already cleared by bfd_zalloc above. + bfd_ardata (abfd)->cache = NULL; + bfd_ardata (abfd)->archive_head = NULL; + bfd_ardata (abfd)->symdefs = NULL; + bfd_ardata (abfd)->extended_names = NULL; + bfd_ardata (abfd)->extended_names_size = 0; + bfd_ardata (abfd)->tdata = NULL; */ return TRUE; } @@ -335,7 +337,7 @@ get_extended_arelt_filename (bfd *arch, errno = 0; /* Skip first char, which is '/' in SVR4 or ' ' in some other variants. */ index = strtol (name + 1, NULL, 10); - if (errno != 0) + if (errno != 0 || index >= bfd_ardata (arch)->extended_names_size) { bfd_set_error (bfd_error_malformed_archive); return NULL; @@ -405,10 +407,7 @@ _bfd_generic_read_ar_hdr_mag (bfd *abfd, { filename = get_extended_arelt_filename (abfd, hdr.ar_name); if (filename == NULL) - { - bfd_set_error (bfd_error_malformed_archive); - return NULL; - } + return NULL; } /* BSD4.4-style long filename. Only implemented for reading, so far! */ @@ -629,11 +628,13 @@ bfd_generic_archive_p (bfd *abfd) } bfd_ardata (abfd)->first_file_filepos = SARMAG; - bfd_ardata (abfd)->cache = NULL; - bfd_ardata (abfd)->archive_head = NULL; - bfd_ardata (abfd)->symdefs = NULL; - bfd_ardata (abfd)->extended_names = NULL; - bfd_ardata (abfd)->tdata = NULL; + /* Cleared by bfd_zalloc above. + bfd_ardata (abfd)->cache = NULL; + bfd_ardata (abfd)->archive_head = NULL; + bfd_ardata (abfd)->symdefs = NULL; + bfd_ardata (abfd)->extended_names = NULL; + bfd_ardata (abfd)->extended_names_size = 0; + bfd_ardata (abfd)->tdata = NULL; */ if (!BFD_SEND (abfd, _bfd_slurp_armap, (abfd)) || !BFD_SEND (abfd, _bfd_slurp_extended_name_table, (abfd))) @@ -1067,6 +1068,7 @@ _bfd_slurp_extended_name_table (bfd *abf strncmp (nextname, "// ", 16) != 0) { bfd_ardata (abfd)->extended_names = NULL; + bfd_ardata (abfd)->extended_names_size = 0; return TRUE; } @@ -1075,7 +1077,11 @@ _bfd_slurp_extended_name_table (bfd *abf return FALSE; amt = namedata->parsed_size; - bfd_ardata (abfd)->extended_names = bfd_zalloc (abfd, amt); + if (amt + 1 == 0) + goto byebye; + + bfd_ardata (abfd)->extended_names_size = amt; + bfd_ardata (abfd)->extended_names = bfd_zalloc (abfd, amt + 1); if (bfd_ardata (abfd)->extended_names == NULL) { byebye: @@ -1098,15 +1104,17 @@ _bfd_slurp_extended_name_table (bfd *abf trailing '/'. DOS/NT created archive often have \ in them We'll fix all problems here.. */ { - char *temp = bfd_ardata (abfd)->extended_names; + char *ext_names = bfd_ardata (abfd)->extended_names; + char *temp = ext_names; char *limit = temp + namedata->parsed_size; for (; temp < limit; ++temp) { if (*temp == '\012') - temp[temp[-1] == '/' ? -1 : 0] = '\0'; + temp[temp > ext_names && temp[-1] == '/' ? -1 : 0] = '\0'; if (*temp == '\\') *temp = '/'; } + *limit = '\0'; } /* Pad to an even boundary if you have to. */ diff -uprN binutils-2.16.91.0.1/bfd/archures.c binutils-2.16.91.0.2/bfd/archures.c --- binutils-2.16.91.0.1/bfd/archures.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/archures.c 2005-07-20 12:27:26.950249594 -0700 @@ -286,6 +286,9 @@ DESCRIPTION .#define bfd_mach_arc_6 6 .#define bfd_mach_arc_7 7 .#define bfd_mach_arc_8 8 +. bfd_arch_m32c, {* Renesas M16C/M32C. *} +.#define bfd_mach_m16c 0x75 +.#define bfd_mach_m32c 0x78 . bfd_arch_m32r, {* Renesas M32R (formerly Mitsubishi M32R/D) *} .#define bfd_mach_m32r 1 {* For backwards compatibility. *} .#define bfd_mach_m32rx 'x' @@ -422,6 +425,7 @@ extern const bfd_arch_info_type bfd_i960 extern const bfd_arch_info_type bfd_ia64_arch; extern const bfd_arch_info_type bfd_ip2k_arch; extern const bfd_arch_info_type bfd_iq2000_arch; +extern const bfd_arch_info_type bfd_m32c_arch; extern const bfd_arch_info_type bfd_m32r_arch; extern const bfd_arch_info_type bfd_m68hc11_arch; extern const bfd_arch_info_type bfd_m68hc12_arch; @@ -434,6 +438,7 @@ extern const bfd_arch_info_type bfd_mmix extern const bfd_arch_info_type bfd_mn10200_arch; extern const bfd_arch_info_type bfd_mn10300_arch; extern const bfd_arch_info_type bfd_msp430_arch; +extern const bfd_arch_info_type bfd_ms1_arch; extern const bfd_arch_info_type bfd_ns32k_arch; extern const bfd_arch_info_type bfd_openrisc_arch; extern const bfd_arch_info_type bfd_or32_arch; @@ -456,7 +461,6 @@ extern const bfd_arch_info_type bfd_w65_ extern const bfd_arch_info_type bfd_xstormy16_arch; extern const bfd_arch_info_type bfd_xtensa_arch; extern const bfd_arch_info_type bfd_z8k_arch; -extern const bfd_arch_info_type bfd_ms1_arch; static const bfd_arch_info_type * const bfd_archures_list[] = { @@ -486,6 +490,7 @@ static const bfd_arch_info_type * const &bfd_ia64_arch, &bfd_ip2k_arch, &bfd_iq2000_arch, + &bfd_m32c_arch, &bfd_m32r_arch, &bfd_m68hc11_arch, &bfd_m68hc12_arch, diff -uprN binutils-2.16.91.0.1/bfd/bfd-in2.h binutils-2.16.91.0.2/bfd/bfd-in2.h --- binutils-2.16.91.0.1/bfd/bfd-in2.h 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/bfd-in2.h 2005-07-20 12:27:26.972245967 -0700 @@ -143,6 +143,9 @@ typedef unsigned long bfd_size_type; #endif /* not BFD64 */ +#define HALF_BFD_SIZE_TYPE \ + (((bfd_size_type) 1) << (8 * sizeof (bfd_size_type) / 2)) + #ifndef BFD_HOST_64_BIT /* Fall back on a 32 bit type. The idea is to make these types always available for function return types, but in the case that @@ -637,7 +640,7 @@ enum dynamic_lib_link_class { }; extern bfd_boolean bfd_elf_record_link_assignment - (bfd *, struct bfd_link_info *, const char *, bfd_boolean); + (struct bfd_link_info *, const char *, bfd_boolean); extern struct bfd_link_needed_list *bfd_elf_get_needed_list (bfd *, struct bfd_link_info *); extern bfd_boolean bfd_elf_get_bfd_needed_list @@ -705,13 +708,17 @@ extern struct bfd_section *_bfd_elf_tls_ (bfd *, struct bfd_link_info *); extern void _bfd_elf_provide_symbol - (struct bfd_link_info *, const char *, bfd_vma); + (struct bfd_link_info *, const char *, bfd_vma, struct bfd_section *); extern void _bfd_elf_provide_section_bound_symbols - (struct bfd_link_info *, struct bfd_section *sec, const char *, const char *); + (struct bfd_link_info *, struct bfd_section *, const char *, const char *); + +extern void _bfd_elf_fix_excluded_sec_syms + (bfd *, struct bfd_link_info *); extern bfd_boolean bfd_m68k_elf32_create_embedded_relocs - (bfd *, struct bfd_link_info *, struct bfd_section *, struct bfd_section *, char **); + (bfd *, struct bfd_link_info *, struct bfd_section *, struct bfd_section *, + char **); /* SunOS shared library support routines for the linker. */ @@ -720,7 +727,8 @@ extern struct bfd_link_needed_list *bfd_ extern bfd_boolean bfd_sunos_record_link_assignment (bfd *, struct bfd_link_info *, const char *); extern bfd_boolean bfd_sunos_size_dynamic_sections - (bfd *, struct bfd_link_info *, struct bfd_section **, struct bfd_section **, struct bfd_section **); + (bfd *, struct bfd_link_info *, struct bfd_section **, + struct bfd_section **, struct bfd_section **); /* Linux shared library support routines for the linker. */ @@ -1262,8 +1270,9 @@ typedef struct bfd_section output sections that have an input section. */ unsigned int linker_has_input : 1; - /* A mark flag used by some linker backends for garbage collection. */ + /* Mark flags used by some linker backends for garbage collection. */ unsigned int gc_mark : 1; + unsigned int gc_mark_from_eh : 1; /* The following flags are used by the ELF linker. */ @@ -1824,6 +1833,9 @@ enum bfd_architecture #define bfd_mach_arc_6 6 #define bfd_mach_arc_7 7 #define bfd_mach_arc_8 8 + bfd_arch_m32c, /* Renesas M16C/M32C. */ +#define bfd_mach_m16c 0x75 +#define bfd_mach_m32c 0x78 bfd_arch_m32r, /* Renesas M32R (formerly Mitsubishi M32R/D) */ #define bfd_mach_m32r 1 /* For backwards compatibility. */ #define bfd_mach_m32rx 'x' @@ -3023,6 +3035,25 @@ of the container. */ /* DLX relocs */ BFD_RELOC_DLX_JMP26, +/* Renesas M16C/M32C Relocations. */ + BFD_RELOC_M16C_8_PCREL8, + BFD_RELOC_M16C_16_PCREL8, + BFD_RELOC_M16C_8_PCREL16, + BFD_RELOC_M16C_8_ELABEL24, + BFD_RELOC_M16C_8_ABS16, + BFD_RELOC_M16C_16_ABS16, + BFD_RELOC_M16C_16_ABS24, + BFD_RELOC_M16C_16_ABS32, + BFD_RELOC_M16C_24_ABS16, + BFD_RELOC_M16C_24_ABS24, + BFD_RELOC_M16C_24_ABS32, + BFD_RELOC_M16C_32_ABS16, + BFD_RELOC_M16C_32_ABS24, + BFD_RELOC_M16C_32_ABS32, + BFD_RELOC_M16C_40_ABS16, + BFD_RELOC_M16C_40_ABS24, + BFD_RELOC_M16C_40_ABS32, + /* Renesas M32R (formerly Mitsubishi M32R) relocs. This is a 24 bit absolute address. */ BFD_RELOC_M32R_24, @@ -3790,6 +3821,21 @@ This is the 5 bits of a value. */ BFD_RELOC_VAX_JMP_SLOT, BFD_RELOC_VAX_RELATIVE, +/* Morpho MS1 - 16 bit immediate relocation. */ + BFD_RELOC_MS1_PC16, + +/* Morpho MS1 - Hi 16 bits of an address. */ + BFD_RELOC_MS1_HI16, + +/* Morpho MS1 - Low 16 bits of an address. */ + BFD_RELOC_MS1_LO16, + +/* Morpho MS1 - Used to tell the linker which vtable entries are used. */ + BFD_RELOC_MS1_GNU_VTINHERIT, + +/* Morpho MS1 - Used to tell the linker which vtable entries are used. */ + BFD_RELOC_MS1_GNU_VTENTRY, + /* msp430 specific relocation codes */ BFD_RELOC_MSP430_10_PCREL, BFD_RELOC_MSP430_16_PCREL, diff -uprN binutils-2.16.91.0.1/bfd/bfd-in.h binutils-2.16.91.0.2/bfd/bfd-in.h --- binutils-2.16.91.0.1/bfd/bfd-in.h 2005-05-10 15:46:40.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/bfd-in.h 2005-07-20 12:27:26.956248605 -0700 @@ -136,6 +136,9 @@ typedef unsigned long bfd_size_type; #endif /* not BFD64 */ +#define HALF_BFD_SIZE_TYPE \ + (((bfd_size_type) 1) << (8 * sizeof (bfd_size_type) / 2)) + #ifndef BFD_HOST_64_BIT /* Fall back on a 32 bit type. The idea is to make these types always available for function return types, but in the case that @@ -630,7 +633,7 @@ enum dynamic_lib_link_class { }; extern bfd_boolean bfd_elf_record_link_assignment - (bfd *, struct bfd_link_info *, const char *, bfd_boolean); + (struct bfd_link_info *, const char *, bfd_boolean); extern struct bfd_link_needed_list *bfd_elf_get_needed_list (bfd *, struct bfd_link_info *); extern bfd_boolean bfd_elf_get_bfd_needed_list @@ -698,13 +701,17 @@ extern struct bfd_section *_bfd_elf_tls_ (bfd *, struct bfd_link_info *); extern void _bfd_elf_provide_symbol - (struct bfd_link_info *, const char *, bfd_vma); + (struct bfd_link_info *, const char *, bfd_vma, struct bfd_section *); extern void _bfd_elf_provide_section_bound_symbols - (struct bfd_link_info *, struct bfd_section *sec, const char *, const char *); + (struct bfd_link_info *, struct bfd_section *, const char *, const char *); + +extern void _bfd_elf_fix_excluded_sec_syms + (bfd *, struct bfd_link_info *); extern bfd_boolean bfd_m68k_elf32_create_embedded_relocs - (bfd *, struct bfd_link_info *, struct bfd_section *, struct bfd_section *, char **); + (bfd *, struct bfd_link_info *, struct bfd_section *, struct bfd_section *, + char **); /* SunOS shared library support routines for the linker. */ @@ -713,7 +720,8 @@ extern struct bfd_link_needed_list *bfd_ extern bfd_boolean bfd_sunos_record_link_assignment (bfd *, struct bfd_link_info *, const char *); extern bfd_boolean bfd_sunos_size_dynamic_sections - (bfd *, struct bfd_link_info *, struct bfd_section **, struct bfd_section **, struct bfd_section **); + (bfd *, struct bfd_link_info *, struct bfd_section **, + struct bfd_section **, struct bfd_section **); /* Linux shared library support routines for the linker. */ diff -uprN binutils-2.16.91.0.1/bfd/bfd.m4 binutils-2.16.91.0.2/bfd/bfd.m4 --- binutils-2.16.91.0.1/bfd/bfd.m4 2005-04-09 12:02:55.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/bfd.m4 2005-07-20 12:27:26.977245143 -0700 @@ -1,36 +1,6 @@ dnl This file was derived from acinclude.m4. -dnl See whether we need a declaration for a function. - -AC_DEFUN([BFD_NEED_DECLARATION], -[AC_MSG_CHECKING([whether $1 must be declared]) -AC_CACHE_VAL(bfd_cv_decl_needed_$1, -[AC_TRY_COMPILE([ -#include -#ifdef HAVE_STRING_H -#include -#else -#ifdef HAVE_STRINGS_H -#include -#endif -#endif -#ifdef HAVE_STDLIB_H -#include -#endif -#ifdef HAVE_UNISTD_H -#include -#endif], -[char *(*pfn) = (char *(*)) $1], -bfd_cv_decl_needed_$1=no, bfd_cv_decl_needed_$1=yes)]) -AC_MSG_RESULT($bfd_cv_decl_needed_$1) -if test $bfd_cv_decl_needed_$1 = yes; then - AC_DEFINE([NEED_DECLARATION_]translit($1, [a-z], [A-Z]), 1, - [Define if $1 is not declared in system header files.]) -fi -])dnl - - dnl Check for existence of a type $1 in sys/procfs.h AC_DEFUN([BFD_HAVE_SYS_PROCFS_TYPE], diff -uprN binutils-2.16.91.0.1/bfd/cache.c binutils-2.16.91.0.2/bfd/cache.c --- binutils-2.16.91.0.1/bfd/cache.c 2005-05-10 15:46:41.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/cache.c 2005-07-20 12:27:26.978244978 -0700 @@ -177,7 +177,7 @@ DESCRIPTION determine when it can avoid a function call. */ -bfd *bfd_last_cache; +bfd *bfd_last_cache = NULL; /* INTERNAL_FUNCTION diff -uprN binutils-2.16.91.0.1/bfd/ChangeLog binutils-2.16.91.0.2/bfd/ChangeLog --- binutils-2.16.91.0.1/bfd/ChangeLog 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/ChangeLog 2005-07-20 12:27:26.931252727 -0700 @@ -1,3 +1,556 @@ +2005-07-20 Kazuhiro Inaoka + + * elf32-m32r.c (m32r_elf_howto_table): Support R_M32R_REL32. + (m32r_reloc_map): Likewise. + (m32r_elf_relocate_section): Likewise. + (m32r_elf_gc_sweep_hook): Likewise. + (m32r_elf_check_relocs): Likewise. + +2005-07-18 Nick Clifton + + * reloc.c: Add M32C and MS1 relocs. + * bfd-in2.h: Regenerate. + * libbfd.h: Regenerate. + +2005-07-18 Nick Clifton + + * config.bfd: Move m32c entry to correct location. + * archures.c: Likewise. + * configure.in: Likewise. + * configure: Regenerate. + * targets.c: Move ms1 vector to correct location. + +2005-07-18 Jan Beulich + + * elf32-i386.c (elf_howto_table): Adjust overflow complaint handler + for R_386_PC16. + * elf64-x86-64.c (x86_64_elf_howto_table): Adjust overflow complaint + handler for R_X86_64_PC16, R_X86_64_8, and R_X86_64_DTPOFF. + +2005-07-16 Eric Botcazou + + PR ld/1021 + PR ld/1031 + * elflink.c (elf_link_add_object_symbols): Also append the version + name to non-hidden absolute symbols that are functions. + +2005-07-16 Alan Modra + + * elf32-ppc.c (ppc_elf_set_sdata_syms): Return void. Remove hack + for zero size sections. Don't set .sbss syms here. + * elf32-ppc.h (ppc_elf_set_sdata_syms): Adjust prototype. + +2005-07-16 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2005-07-15 Bob Wilson + + * elf32-xtensa.c (vsprint_msg): Add prototype. + (build_encoding_error_message): Delete. Code moved into.... + (elf_xtensa_do_reloc): ....here, and changed to give better + error messages for out of range literals. + +2005-07-15 Alan Modra + + * elflink.c (bfd_elf_record_link_assignment): Remove output_bfd param. + (_bfd_elf_provide_symbol): Allow redefinition of weak syms and those + defined in output sections. Call bfd_elf_record_link_assignment. + * bfd-in.h (bfd_elf_record_link_assignment): Update prototype. + * bfd-in2.h: Regenerate. + +2005-07-14 Jim Blandy + + Add support for m32c-*-elf (Renesas m32c and m16c). + * Makefile.am (ALL_MACHINES): Add cpu-m32c.lo. + (ALL_MACHINES_CFILES): Add cpu-m32c.c. + (BFD32_BACKENDS): Add elf32-m32c.lo. + (BFD32_BACKENDS_CFILES): Add elf32-m32c.c. + (cpu-m32c.lo, elf32-m32c.lo): New rules, generated by 'make dep-am'. + * Makefile.in: Regenerated. + * archures.c (bfd_arch_m32c, bfd_mach_m16c, bfd_mach_m32c): New + arch and mach codes. + (bfd_m32c_arch): New arch info object. + (bfd_archures_list): List bfd_m32c_arch. + * bfd-in2.h: Regenerated. + * config.bfd: Add case for the m32c. + * configure.in: Add case for the m32c. + * configure: Regenerated. + * cpu-m32c.c, elf32-m32c.c: New files. + * libbfd.h: Regenerated. + * targets.c (bfd_elf32_m32c_vec): Declare. + (_bfd_target_vector): List bfd_elf32_m32c_vec. + +2005-07-14 Alan Modra + + * bfd-in.h (_bfd_elf_fix_excluded_sec_syms): Declare. + (_bfd_elf_provide_section_bound_symbols): Remove param name. + Formatting. + * bfd-in2.h: Regenerate. + * elflink.c (bfd_elf_gc_sections): Don't call generic function. + (_bfd_elf_provide_symbol): Formatting. + (_bfd_elf_provide_section_bound_symbols): Remove all hacks, just + create section relative syms. + (fix_syms, _bfd_elf_fix_excluded_sec_syms): New functions. + * elf32-ppc.c (ppc_elf_set_sdata_syms): Use + _bfd_elf_provide_section_bound_symbols. + * reloc.c (bfd_mark_used_section): Delete. + (bfd_generic_gc_sections): Don't call the above. + +2005-07-14 Paul Woegerer + + PR 1063 + * cache.c (bfd_last_cache): Initialise to NULL. + +2005-07-14 Daniel Marques + Nick Clifton + + * coff-alpha.c (alpha_ecoff_bad_format_hook): Detect compressed + Alpha binaries and issue a helpful error message. + (alpha_ecoff_swap_reloc_out): Increase maximum allowed internal + symbol index to 15 to allow for binaries produced by DEC + compilers. + +2005-07-13 Steve Ellcey + + * bfd.m4 (BFD_NEED_DECLARATION): Remove. + +2005-07-12 Alan Modra + + * elf64-ppc.c (ppc64_elf_relocate_section): Don't use a plt stub + when !can_plt_call. + +2005-07-12 Alan Modra + + * elf32-xtensa.c (bfd_elf_xtensa_reloc): Warning fix. + +2005-07-12 Alan Modra + + * elf32-ppc.c (ppc_elf_set_sdata_syms): Correct __sbss_start value. + +2005-07-11 H.J. Lu + + * elflink.c (_bfd_elf_symbol_refs_local_p): Revert the last + change. + +2005-07-08 Paul Koning + + * dwarf2.c (read_address): Check sign_extend_vma to handle targets + where addresses are sign extended. + +2005-07-08 Ralf Corsepius + + * config.bfd: Mark i960-*-rtems*, or32-*-rtems* as obsolete. + Mark a29k-*rtems*, hppa*-*-rtems*, *-go32-rtems*, + i[3-7]86*-*-rtemscoff*, mips*el-*-rtems*, powerpcle-*-rtems*, + sparc*-*-rtemsaout* as removed + +2005-07-08 Alan Modra + + * elf-hppa.h (elf_hppa_final_link): Use gp val of zero when none + of the usual sections are found. + * elf-m10300.c (_bfd_mn10300_elf_size_dynamic_sections): Tidy. + Strip .dynbss if it is zero size. + * elf32-arm.c (elf32_arm_size_dynamic_sections): Likewise. + * elf32-cris.c (elf_cris_size_dynamic_sections): Likewise. + * elf32-hppa.c (elf32_hppa_size_dynamic_sections): Likewise. + * elf32-i370.c (i370_elf_size_dynamic_sections): Likewise, and + .dynsbss. + (i370_elf_finish_dynamic_sections): Don't attempt to write .got + when it is zero size. + * elf32-i386.c (elf_i386_size_dynamic_sections): Correct handling + of .dynbss and zero size sections. + * elf32-m32r.c (m32r_elf_size_dynamic_sections): Strip .dynbss if + it is zero size. + * elf32-m68k.c (elf_m68k_size_dynamic_sections): Tidy. Strip + .dynbss if zero size. + * elf32-ppc.c (ppc_elf_size_dynamic_sections): Likewise, .dynsbss + too. + * elf32-s390.c (elf_s390_size_dynamic_sections): Likewise. + * elf32-sh.c (sh_elf_size_dynamic_sections): Likewise. + * elf32-vax.c (elf_vax_size_dynamic_sections): Likewise. + * elf32-xtensa.c (elf_xtensa_size_dynamic_sections): Tidy. Strip + .plt.* and .got.plt.* if zero size. + * elf64-alpha.c (elf64_alpha_size_dynamic_sections): Tidy. Strip + .got* and .dynbss if zero size. + * elf64-hppa.c (elf64_hppa_size_dynamic_sections): Tidy. Strip + * elf64-ppc.c (create_linkage_sections): Create branch lookup table + in .data.rel.ro.brlt or .rodata.brlt, and similarly for associated + reloc section. + (create_got_section): Always create new .got and .rela.got sections. + (ppc64_elf_size_dynamic_sections): Tidy. Strip .dynbss if zero size. + * elf64-s390.c (elf_s390_size_dynamic_sections): Likewise. + * elf64-sh64.c (sh64_elf64_size_dynamic_sections): Likewise. + * elf64-x86-64.c (elf64_x86_64_size_dynamic_sections): Handle + dynamic bss sections correctly. + * elfxx-mips.c (_bfd_mips_elf_size_dynamic_sections): Tidy. + * elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Tidy. Strip + .dynbss if zero size. + +2005-07-08 Ben Elliston + + * elf32-xtensa.c: Include unconditionally, not only + when ANSI_PROTOTYPES is defined. Remove #ifdef logic. + +2005-07-07 H.J. Lu + + * elf-bfd.h (elf_backend_data): Add special_sections. + + * elf.c (_bfd_elf_get_sec_type_attr): Check special_sections + first. + + * elf32-arm.c (elf_backend_get_sec_type_attr): Removed. + (elf_backend_special_sections): New. Defined. + * elf32-m32r.c: Likewise. + * elf32-m68hc11.c: Likewise. + * elf32-m68hc12.c: Likewise. + * elf32-mcore.c: Likewise. + * elf32-sh64.c: Likewise. + * elf32-v850.c: Likewise. + * elf32-xtensa.c: Likewise. + * elf64-alpha.c: Likewise. + * elf64-hppa.c: Likewise. + * elf64-ppc.c: Likewise. + * elf64-sh64.c: Likewise. + * elfxx-ia64.c: Likewise. + * elfxx-mips.c: Likewise. + * elfxx-mips.h: Likewise. + + * elfxx-target.h (elf_backend_special_sections): New. + (elfNN_bed): Initialize special_sections. + +2005-07-07 Bob Wilson + + * xtensa-modules.c: Update tables with Xtensa MMU features. + +2005-07-07 Kaveh R. Ghazi + + * elf32-xtensa.c (vsprint_msg): Add format attribute. Fix + format bugs. + * vms.h (_bfd_vms_debug): Add format attribute. + (_bfd_vms_debug, _bfd_hexdump): Fix typos. + +2005-07-07 H.J. Lu + + PR 975 + * elflink.c (_bfd_elf_symbol_refs_local_p): Only undefined + symbol with default visibility is local. + +2005-07-07 Ben Elliston + + * config.bfd: Mark m68*-*-rtemscoff as obsolete. + +2005-07-06 H.J. Lu + + * dwarf2.c (varinfo): Add addr. + (lookup_symbol_in_variable_table): Also check addr. + (scan_unit_for_symbols): Set addr for variable. + (comp_unit_find_line): Updated. + +2005-07-06 Nick Clifton + + * coff-alpha.c (alpha_adjust_reloc_in): Issue an informative error + message if an unknown reloc is encountered. + (alpha_relocate_section): Likewise. + + * ecoff.c (_bfd_ecoff_write_object_contents): Cope with a reloc + with a missing howto field. + +2005-07-06 Alan Modra + + * po/SRC-POTFILES.in: Add cpu-ms1.c, elf32-ms1.c, elf-vxworks.c, + elfxx-sparc.c. + +2005-07-05 Paul Brook + + * elf32-ppc.c (ppc_elf_vxworks_special_sections): Remove. + (ppc_elf_vxworks_get_sec_type_attr): New function. + (elf_backend_special_sections): Remove vxwords definition. + (elf_backend_get_sec_type_attr): Define for vxworks. + +2005-07-05 Nick Clifton + + * elf64-ppc.c (ppc64_elf_info_to_howto): Fix typo. + +2005-07-05 Paul Brook + + * config.bfd: Add separate case for ppc-vxworks. + * configure: Regenerate. + * configure.in: Include elf-vxworks.lo on ppc targets. + * elf-vxworks.c (elf_vxworks_final_write_processing): Handle + .rela.plt.unloaded. + * elf32-ppc.c: Add VxWorks target vec. Include elf-vxworks.h. + (PLT_ENTRY_SIZE, PLT_INITIAL_ENTRY_SIZE, PLT_SLOT_SIZE): Remove. + (VXWORKS_PLT_ENTRY_SIZE, ppc_elf_vxworks_plt_entry, + ppc_elf_vxworks_pic_plt_entry, VXWORKS_PLT_INITIAL_ENTRY_SIZE, + ppc_elf_vxworks_plt0_entry, ppc_elf_vxworks_pic_plt0_entry, + VXWORKS_PLT_NON_JMP_SLOT_RELOCS, VXWORKS_PLTRESOLVE_RELOCS, + VXWORKS_PLTRESOLVE_RELOCS_SHLIB): New. + (ppc_elf_link_hash_table): Add srelplt2, sgotplt, hgot, hplt, + is_vxworks, plt_entry_size, plt_slot_size, plt_initial_entry_size. + (ppc_elf_link_hash_table_create): Initialize hadtab plt fields. + (ppc_elf_create_got): Create .got.plt for VxWorks. + (ppc_elf_create_dynamic_sections): Create unloaded plt relocation + section for VxWorks. + (ppc_elf_select_plt_layout): Handle VxWorks plt format. + (allocate_got): VxWorks does not need a got header. + (allocate_dynrelocs): Handle VxWorks plt format. + (ppc_elf_size_dynamic_sections): Save _G_O_T_ and _P_L_T_ symbols for + VxWorks. Handle VxWorks plt/got. + (ppc_elf_finish_dynamic_sections): Fill in VxWorks plt. + (ppc_elf_vxworks_special_sections): New. + (ppc_elf_vxworks_link_hash_table_create, + ppc_elf_vxworks_add_symbol_hook, + elf_i386_vxworks_link_output_symbol_hook, + ppc_elf_vxworks_final_write_processing): New functions. + * targets.c (bfd_elf32_powerpc_vxworks_vec): Declare. + (_bfd_target_vector): Use it. + +2005-07-05 Jakub Jelinek + + * libbfd-in.h (struct artdata): Add extended_names_size field. + * libbfd.h: Rebuilt. + * coff-rs600.c (_bfd_xcoff_archive_p): Don't clear fields in freshly + allocated object by bfd_zalloc. + * coff64-rs6000.c (xcoff64_archive_p): Likewise. + * ecoff.c (_bfd_ecoff_archive_p): Likewise. + * archive.c (_bfd_generic_mkarchive, bfd_generic_archive_p): Likewise. + (get_extended_arelt_filename): Fail if index is bigger or equal to + extended_names_size. + (_bfd_generic_read_ar_hdr_mag): Don't set bfd_error_malformed_archive, + get_extended_arelt_filename already did that. + (_bfd_slurp_extended_name_table): Initialize extended_names_size field. + Allocate one extra byte and clear it, in case extended names table + is not terminated. + + * libbfd-in.h (bfd_malloc2, bfd_realloc2, bfd_zmalloc2, bfd_alloc2, + bfd_zalloc2): New prototypes. + * bfd-in.h (HALF_BFD_SIZE_TYPE): Define. + * libbfd.c (bfd_malloc2, bfd_realloc2, bfd_zmalloc2): New functions. + * opncls.c (bfd_alloc2, bfd_zalloc2): New functions. + * elf.c (bfd_elf_get_elf_syms, setup_group, assign_section_numbers, + elf_map_symbols, map_sections_to_segments, + assign_file_positions_for_segments, copy_private_bfd_data, + swap_out_syms, _bfd_elf_slurp_version_tables): Use bfd_*alloc2 + where appropriate. + * bfd-in2.h: Rebuilt. + * libbfd.h: Rebuilt. + + * elf.c (_bfd_elf_print_private_bfd_data): Don't crash on bogus + verdef or verneed section. + (_bfd_elf_slurp_version_tables): Handle corrupt verdef and/or + verneed sections gracefully. + * elfxx-sparc.c (_bfd_sparc_elf_info_to_howto_ptr): Don't crash on + bogus relocation values. + * elf64-ppc.c (ppc64_elf_info_to_howto): Likewise. + * elf64-s390.c (elf_s390_info_to_howto): Likewise. + * elf32-s390.c (elf_s390_info_to_howto): Likewise. + * elf64-x86-64.c (elf64_x86_64_info_to_howto): Likewise. + * elfxx-ia64.c (lookup_howto): Likewise. + + * elf.c (bfd_elf_get_str_section): Allocate an extra byte after + the end of strtab and clear it. + (elf_read): Remove. + +2005-07-05 Nick Clifton + + * po/vi.po: New Vietnamese translation. + * configure.in (ALL_LINGUAS): Add vi. + * configure: Regenerate. + +2005-07-05 Peter S. Mazinger + + * elf32-arm.c (elf32_arm_size_dynamic_sections): Fix a typo and + touchup logic like i386/ppc. + +2005-07-05 Alan Modra + + * elf.c (special_sections): Move const qualifier. + (special_sections_b..special_sections_t): Likewise. + * elf32-arm.c (elf32_arm_symbian_get_sec_type_attr): Remove duplicate + const. + (elf32_arm_symbian_special_sections): Move const qualifier. + * elf32-m32r.c: Similarly. + * elf32-m68hc11.c: Similarly. + * elf32-m68hc12.c: Similarly. + * elf32-mcore.c: Similarly. + * elf32-ppc.c: Similarly. + * elf32-sh64.c: Similarly. + * elf32-v850.c: Similarly. + * elf32-xtensa.c: Similarly. + * elf64-alpha.c: Similarly. + * elf64-hppa.c: Similarly. + * elf64-ppc.c: Similarly. + * elf64-sh64.c: Similarly. + * elfxx-ia64.c: Similarly. + * elfxx-mips.c: Similarly. + +2005-07-04 Kazuhiro Inaoka + + * elf32-m32r.c (m32r_elf_size_dynamic_sections): Use + info->executable instead of !info->shared where appropriate. + +2005-07-04 Alan Modra + + PR 1042 + * elf.c (assign_file_positions_for_segments): Remove excluded + sections from the segment map. + +2005-07-04 Alan Modra + + PR 1004 + * elf-bfd.h (struct elf_backend_data): Add get_sec_type_attr. Delete + special_sections. + (_bfd_elf_get_special_section): Declare. + (bfd_elf_special_section): Update prototype. + * elf.c (special_sections): Remove unused outer entries. + (get_special_section): Delete. + (_bfd_elf_get_special_section): New function. + (_bfd_elf_get_sec_type_attr): Replace "name" arg with "sec". Update + special_sections indexing. + (_bfd_elf_new_section_hook): Call backend get_sec_type_attr. + * elf32-arm.c (symbian_special_sections_d): Delete. + (symbian_special_sections_g, symbian_special_sections_h): Delete. + (symbian_special_sections_i, symbian_special_sections_f): Delete. + (symbian_special_sections_p): Delete. + (elf32_arm_symbian_special_sections): Merge above to here. + (elf32_arm_symbian_get_sec_type_attr): New function. + (elf_backend_special_sections): Don't define. + (elf_backend_get_sec_type_attr): Define. + * elf32-m32r.c: Similarly to elf32-arm.c. + * elf32-m68hc11.c: Likewise. + * elf32-m68hc12.c: Likewise. + * elf32-mcore.c: Likewise. + * elf32-sh64.c: Likewise. + * elf32-v850.c: Likewise. + * elf32-xtensa.c: Likewise. + * elf64-alpha.c: Likewise. + * elf64-hppa.c: Likewise. + * elf64-ppc.c: Likewise. + * elf64-sh64.c: Likewise. + * elfxx-ia64.c: Likewise. + * elfxx-mips.c: Likewise. + * elf32-ppc.c: Likewise. + (bfd_elf_special_section ppc_alt_plt): New. Use it if .plt loadable. + * elfxx-mips.h (_bfd_mips_elf_get_sec_type_attr): Declare. + (_bfd_mips_elf_special_sections, elf_backend_special_sections): Delete. + (elf_backend_get_sec_type_attr): Define. + * elfxx-target.h (elf_backend_get_sec_type_attr): Define. + (elf_backend_special_sections): Don't define. + (elfNN_bed): Update. + +2005-07-01 Nick Clifton + + * cpu-d10v.c: Update to ISO C90 style function declarations and + fix formatting. + * cpu-d30v.c: Likewsie. + * cpu-i370.c: Likewsie. + * cpu-xstormy16.c: Likewsie. + * elf32-arc.c: Likewsie. + * elf32-d10v.c: Likewsie. + * elf32-d30v.c: Likewsie. + * elf32-dlx.c: Likewsie. + * elf32-i370.c: Likewsie. + * elf32-i960.c: Likewsie. + * elf32-ip2k.c: Likewsie. + * elf32-m32r.c: Likewsie. + * elf32-mcore.c: Likewsie. + * elf32-openrisc.c: Likewsie. + * elf32-or32.c: Likewsie. + * elf32-pj.c: Likewsie. + * elf32-v850.c: Likewsie. + * elf32-xstormy16.c: Likewsie. + +2005-07-01 Alan Modra + + * elf64-alpha.c (elf64_alpha_create_got_section): Always create + a new .got section. + (elf64_alpha_create_dynamic_sections): Always make new sections + by using bfd_make_section_anyway_with_flags. Check that .got not + already created. + (elf64_alpha_check_relocs): Delete "got_created". Use tdata->gotobj + instead. + +2005-06-30 Alan Modra + + * elf32-ppc.c (ppc_elf_adjust_dynamic_symbol): Ignore dynamic + _SDA_BASE_ and _SDA2_BASE_ symbols. + * elflink.c (_bfd_elf_provide_symbol): Correct comment. Define + sym if not def_regular. + (_bfd_elf_provide_section_bound_symbols): Similarly. + +2005-06-30 Ben Elliston + + * config.bfd: Mark as obsolete: + m68*-apollo-* + m68*-apple-aux* + m68*-bull-sysv* + +2005-06-29 Alan Modra + + * elflink.c (_bfd_elf_gc_mark): Mark sections referenced by + .eh_frame specially.. + (bfd_elf_gc_sections): ..rather than totally ignoring .eh_frame. + Don't recheck sections we have already marked. + (elf_gc_sweep): Keep non-code sections referenced from .eh_frame. + * section.c (struct bfd_section): Add gc_mark_from_eh. + (STD_SECTION): Adjust. + * ecoff.c (bfd_debug_section): Adjust. + * bfd-in2.h: Regenerate. + +2005-06-29 Alan Modra + + * elflink.c (elf_gc_sweep): Do not refcount on sections that have + not been processed by check_relocs. + +2005-06-29 Paul Brook + + * bfd-in.h (_bfd_elf_provide_symbol): Update prototype. + * bfd-in2.h: Regenerate. + * elf32-ppc.c (ppc_elf_set_sdata_syms): Make sdata symbols section + relative. + * elflink.c (bfd_elf_set_symbol): Add section argument. + (_bfd_elf_provide_symbol): Ditto. + (_bfd_elf_provide_section_bound_symbols): Pass NULL section argument. + +2005-06-27 Carlos O'Donell + + * bfd/elf32-hppa.c (struct elf32_hppa_stub_hash_entry): + Use bh_root, and hh. + (struct elf32_hppa_link_hash_entry): Use eh, and hsh_cache. + (struct elf32_hppa_dyn_reloc_entry): Use hdh_next. + (struct elf32_hppa_link_hash_table): Use etab and bstab. + (stub_hash_newfunc): Use hh. + (hppa_link_hash_newfunc): Use hsh_cache. + (elf32_hppa_link_hash_table_create): Use etab, and bstab. + (elf32_hppa_link_hash_table_free): Use bstab. + (hppa_stub_name): Use eh. + (hppa_get_stub_entry): Use hh, hsh_entry, and hsh_cache. + (hppa_add_stub): Use bstab. + (hppa_type_of_stub): Use eh. + (hppa_build_one_stub): Use hh and bh_root. + (elf32_hppa_copy_indirect_symbol): Use hdh_next. + (elf32_hppa_check_relocs): Use eh, etab, and hdh_next. + (elf32_hppa_gc_sweep_hook): Use hdh_next. + (elf32_hppa_adjust_dynamic_symbol): Use hdh_next, and etab. + (allocate_plt_static): Use etab. + (allocate_dynrelocs): Use etab, and hdh_next. + (readonly_dynrelocs): Use hdh_next. + (elf32_hppa_size_dynamic_sections): Use etab, and hdh_next. + (get_local_syms): Use eh, bstab, and hh. + (elf32_hppa_size_stubs): Use eh, bstab, and hh. + (elf32_hppa_set_gp): Use etab. + (elf32_hppa_build_stubs): Use bstab. + (final_link_relocate): Use eh, bh_root. + (elf32_hppa_relocate_section): Use elf, etab. + (elf32_hppa_finish_dynamic_sections): Use etab. + +2005-06-27 H.J. Lu + + * elfxx-ia64.c (elfNN_hpux_backend_symbol_processing): Remove + the extra `;'. + 2005-06-21 Carlos O'Donell * bfd/elf32-hppa.c (hppa_elf_hash_entry): Define. diff -uprN binutils-2.16.91.0.1/bfd/coff64-rs6000.c binutils-2.16.91.0.2/bfd/coff64-rs6000.c --- binutils-2.16.91.0.1/bfd/coff64-rs6000.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/coff64-rs6000.c 2005-07-20 12:27:26.998241680 -0700 @@ -1983,10 +1983,12 @@ xcoff64_archive_p (abfd) if (bfd_ardata (abfd) == (struct artdata *) NULL) goto error_ret_restore; - bfd_ardata (abfd)->cache = NULL; - bfd_ardata (abfd)->archive_head = NULL; - bfd_ardata (abfd)->symdefs = NULL; - bfd_ardata (abfd)->extended_names = NULL; + /* Already cleared by bfd_zalloc above. + bfd_ardata (abfd)->cache = NULL; + bfd_ardata (abfd)->archive_head = NULL; + bfd_ardata (abfd)->symdefs = NULL; + bfd_ardata (abfd)->extended_names = NULL; + bfd_ardata (abfd)->extended_names_size = 0; */ bfd_ardata (abfd)->first_file_filepos = bfd_scan_vma (hdr.firstmemoff, (const char **) NULL, 10); diff -uprN binutils-2.16.91.0.1/bfd/coff-alpha.c binutils-2.16.91.0.2/bfd/coff-alpha.c --- binutils-2.16.91.0.1/bfd/coff-alpha.c 2005-05-10 15:46:41.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/coff-alpha.c 2005-07-20 12:27:26.988243329 -0700 @@ -481,10 +481,16 @@ alpha_ecoff_bad_format_hook (abfd, fileh { struct internal_filehdr *internal_f = (struct internal_filehdr *) filehdr; - if (ALPHA_ECOFF_BADMAG (*internal_f)) - return FALSE; + if (! ALPHA_ECOFF_BADMAG (*internal_f)) + return TRUE; - return TRUE; + if (ALPHA_ECOFF_COMPRESSEDMAG (*internal_f)) + (*_bfd_error_handler) + (_("%B: Cannot handle compressed Alpha binaries.\n" + " Use compiler flags, or objZ, to generate uncompressed binaries."), + abfd); + + return FALSE; } /* This is a hook called by coff_real_object_p to create any backend @@ -603,8 +609,11 @@ alpha_ecoff_swap_reloc_out (abfd, intern size = intern->r_size; } + /* XXX FIXME: The maximum symndx value used to be 14 but this + fails with object files produced by DEC's C++ compiler. + Where does the value 14 (or 15) come from anyway ? */ BFD_ASSERT (intern->r_extern - || (intern->r_symndx >= 0 && intern->r_symndx <= 14)); + || (intern->r_symndx >= 0 && intern->r_symndx <= 15)); H_PUT_64 (abfd, intern->r_vaddr, ext->r_vaddr); H_PUT_32 (abfd, symndx, ext->r_symndx); @@ -632,7 +641,15 @@ alpha_adjust_reloc_in (abfd, intern, rpt arelent *rptr; { if (intern->r_type > ALPHA_R_GPVALUE) - abort (); + { + (*_bfd_error_handler) + (_("%B: unknown/unsupported relocation type %d"), + abfd, intern->r_type); + bfd_set_error (bfd_error_bad_value); + rptr->addend = 0; + rptr->howto = NULL; + return; + } switch (intern->r_type) { @@ -1521,8 +1538,26 @@ alpha_relocate_section (output_bfd, info switch (r_type) { + case ALPHA_R_GPRELHIGH: + (*_bfd_error_handler) + (_("%B: unsupported relocation: ALPHA_R_GPRELHIGH"), + input_bfd); + bfd_set_error (bfd_error_bad_value); + continue; + + case ALPHA_R_GPRELLOW: + (*_bfd_error_handler) + (_("%B: unsupported relocation: ALPHA_R_GPRELLOW"), + input_bfd); + bfd_set_error (bfd_error_bad_value); + continue; + default: - abort (); + (*_bfd_error_handler) + (_("%B: unknown relocation type %d"), + input_bfd, (int) r_type); + bfd_set_error (bfd_error_bad_value); + continue; case ALPHA_R_IGNORE: /* This reloc appears after a GPDISP reloc. On earlier diff -uprN binutils-2.16.91.0.1/bfd/coff-rs6000.c binutils-2.16.91.0.2/bfd/coff-rs6000.c --- binutils-2.16.91.0.1/bfd/coff-rs6000.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/coff-rs6000.c 2005-07-20 12:27:26.992242669 -0700 @@ -1294,10 +1294,12 @@ _bfd_xcoff_archive_p (abfd) if (bfd_ardata (abfd) == (struct artdata *) NULL) goto error_ret_restore; - bfd_ardata (abfd)->cache = NULL; - bfd_ardata (abfd)->archive_head = NULL; - bfd_ardata (abfd)->symdefs = NULL; - bfd_ardata (abfd)->extended_names = NULL; + /* Cleared by bfd_zalloc above. + bfd_ardata (abfd)->cache = NULL; + bfd_ardata (abfd)->archive_head = NULL; + bfd_ardata (abfd)->symdefs = NULL; + bfd_ardata (abfd)->extended_names = NULL; + bfd_ardata (abfd)->extended_names_size = 0; */ /* Now handle the two formats. */ if (magic[1] != 'b') diff -uprN binutils-2.16.91.0.1/bfd/config.bfd binutils-2.16.91.0.2/bfd/config.bfd --- binutils-2.16.91.0.1/bfd/config.bfd 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/config.bfd 2005-07-20 12:27:27.003240856 -0700 @@ -31,6 +31,12 @@ targ_underscore=no # Catch obsolete configurations. case $targ in + m68*-apple-aux* | \ + m68*-apollo-* | \ + m68*-bull-sysv* | \ + m68*-*-rtemscoff* | \ + i960-*-rtems* | \ + or32-*-rtems* | \ null) if test "x$enable_obsolete" != xyes; then echo "*** Configuration $targ is obsolete." >&2 @@ -47,6 +53,13 @@ case $targ in vax-*-vms* | \ arm-*-oabi | \ thumb-*-oabi | \ + a29k-*rtems* | \ + hppa*-*-rtems* | \ + *-go32-rtems* | \ + i[3-7]86*-*-rtemscoff* | \ + mips*el-*-rtems* | \ + powerpcle-*-rtems* | \ + sparc*-*-rtemsaout* | \ null) echo "*** Configuration $targ is obsolete." >&2 echo "*** Support has been REMOVED." >&2 @@ -293,7 +306,7 @@ case "${targ}" in ;; a29k-*-ebmon* | a29k-*-udi* | a29k-*-coff* | a29k-*-sym1* | \ - a29k-*-vxworks* | a29k-*-sysv* | a29k-*rtems*) + a29k-*-vxworks* | a29k-*-sysv*) targ_defvec=a29kcoff_big_vec targ_selvecs=sunos_big_vec targ_underscore=yes @@ -409,7 +422,7 @@ case "${targ}" in targ_defvec=bfd_elf32_hppa_nbsd_vec targ_selvecs="bfd_elf32_hppa_vec bfd_elf32_hppa_linux_vec" ;; - hppa*-*-*elf* | hppa*-*-lites* | hppa*-*-sysv4* | hppa*-*-rtems* | hppa*-*-openbsd*) + hppa*-*-*elf* | hppa*-*-lites* | hppa*-*-sysv4* | hppa*-*-openbsd*) targ_defvec=bfd_elf32_hppa_vec targ_selvecs=bfd_elf32_hppa_linux_vec ;; @@ -462,7 +475,7 @@ case "${targ}" in i[3-7]86-*-chorus*) targ_defvec=bfd_elf32_i386_vec ;; - *-*-msdosdjgpp* | *-*-go32* | *-go32-rtems* ) + *-*-msdosdjgpp* | *-*-go32* ) targ_defvec=go32coff_vec targ_selvecs="go32stubbedcoff_vec i386aout_vec" ;; @@ -470,10 +483,6 @@ case "${targ}" in i[3-7]86-*-aix*) targ_defvec=i386coff_vec ;; - i[3-7]86*-*-rtemscoff*) - targ_defvec=i386coff_vec - targ_selvecs="bfd_elf32_i386_vec i386aout_vec" - ;; i[3-7]86-*-rtemself* | i[3-7]86-*-rtems*) targ_defvec=bfd_elf32_i386_vec targ_selvecs="i386coff_vec i386aout_vec" @@ -653,6 +662,10 @@ case "${targ}" in targ_defvec=bfd_elf32_iq2000_vec ;; + m32c-*-elf) + targ_defvec=bfd_elf32_m32c_vec + ;; + m32r*le-*-linux*) targ_defvec=bfd_elf32_m32rlelin_vec targ_selvecs="bfd_elf32_m32rlin_vec bfd_elf32_m32rlelin_vec" @@ -859,7 +872,7 @@ case "${targ}" in targ_defvec=ecoff_big_vec targ_selvecs=ecoff_little_vec ;; - mips*el-*-elf* | mips*el-*-rtems* | mips*el-*-vxworks* | mips*-*-chorus*) + mips*el-*-elf* | mips*el-*-vxworks* | mips*-*-chorus*) targ_defvec=bfd_elf32_littlemips_vec targ_selvecs="bfd_elf32_bigmips_vec bfd_elf64_bigmips_vec bfd_elf64_littlemips_vec" ;; @@ -941,12 +954,12 @@ case "${targ}" in targ_defvec=bfd_elf32_openrisc_vec ;; - or32-*-coff) + or32-*-coff | or32-*-rtems* ) targ_defvec=or32coff_big_vec targ_underscore=yes ;; - or32-*-elf | or32-*-rtems*) + or32-*-elf) targ_defvec=bfd_elf32_or32_big_vec ;; @@ -1019,7 +1032,7 @@ case "${targ}" in #endif powerpc-*-*bsd* | powerpc-*-elf* | powerpc-*-sysv4* | powerpc-*-eabi* | \ powerpc-*-solaris2* | powerpc-*-linux-* | powerpc-*-rtems* | \ - powerpc-*-chorus* | powerpc-*-vxworks* | powerpc-*-windiss*) + powerpc-*-chorus*) targ_defvec=bfd_elf32_powerpc_vec targ_selvecs="rs6000coff_vec bfd_elf32_powerpcle_vec ppcboot_vec" targ64_selvecs="bfd_elf64_powerpc_vec bfd_elf64_powerpcle_vec" @@ -1050,13 +1063,17 @@ case "${targ}" in targ_defvec=bfd_elf32_powerpc_vec targ_selvecs="rs6000coff_vec bfd_elf32_powerpcle_vec ppcboot_vec" ;; + powerpc-*-vxworks* | powerpc-*-windiss*) + targ_defvec=bfd_elf32_powerpc_vxworks_vec + targ_selvecs="rs6000coff_vec bfd_elf32_powerpc_vec bfd_elf32_powerpcle_vec ppcboot_vec" + targ64_selvecs="bfd_elf64_powerpc_vec bfd_elf64_powerpcle_vec" + ;; powerpcle-*-nto*) targ_defvec=bfd_elf32_powerpcle_vec targ_selvecs="rs6000coff_vec bfd_elf32_powerpc_vec ppcboot_vec" ;; powerpcle-*-elf* | powerpcle-*-sysv4* | powerpcle-*-eabi* | \ - powerpcle-*-solaris2* | powerpcle-*-linux-* | powerpcle-*-vxworks* |\ - powerpcle-*-rtems*) + powerpcle-*-solaris2* | powerpcle-*-linux-* | powerpcle-*-vxworks*) targ_defvec=bfd_elf32_powerpcle_vec targ_selvecs="rs6000coff_vec bfd_elf32_powerpc_vec ppcboot_vec" targ64_selvecs="bfd_elf64_powerpc_vec bfd_elf64_powerpcle_vec" @@ -1285,11 +1302,6 @@ case "${targ}" in sparc*-*-coff*) targ_defvec=sparccoff_vec ;; - sparc*-*-rtemsaout*) - targ_defvec=sunos_big_vec - targ_selvecs="bfd_elf32_sparc_vec sparccoff_vec" - targ_underscore=yes - ;; sparc*-*-rtems* | sparc*-*-rtemself*) targ_defvec=bfd_elf32_sparc_vec targ_selvecs="sunos_big_vec sparccoff_vec" diff -uprN binutils-2.16.91.0.1/bfd/configure binutils-2.16.91.0.2/bfd/configure --- binutils-2.16.91.0.1/bfd/configure 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/configure 2005-07-20 12:27:27.022237723 -0700 @@ -2836,7 +2836,7 @@ fi # Define the identity of the package. PACKAGE=bfd - VERSION=2.16.91.0.1 + VERSION=2.16.91.0.2 cat >>confdefs.h <<_ACEOF @@ -5165,7 +5165,7 @@ _ACEOF -ALL_LINGUAS="fr tr ja es sv da zh_CN ro rw" +ALL_LINGUAS="fr tr ja es sv da zh_CN ro rw vi" if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. set dummy ${ac_tool_prefix}ranlib; ac_word=$2 @@ -13003,6 +13003,7 @@ do tb="$tb elf32-arm.lo elf32.lo $elf" ;; bfd_elf32_littlearm_vec) tb="$tb elf32-arm.lo elf32.lo $elf" ;; bfd_elf32_littlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;; + bfd_elf32_m32c_vec) tb="$tb elf32-m32c.lo elf32.lo $elf" ;; bfd_elf32_m32r_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;; bfd_elf32_m32rle_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;; bfd_elf32_m32rlin_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;; @@ -13025,8 +13026,9 @@ do bfd_elf32_or32_big_vec) tb="$tb elf32-or32.lo elf32.lo $elf" ;; bfd_elf32_pj_vec) tb="$tb elf32-pj.lo elf32.lo $elf";; bfd_elf32_pjl_vec) tb="$tb elf32-pj.lo elf32.lo $elf";; - bfd_elf32_powerpc_vec) tb="$tb elf32-ppc.lo elf32.lo $elf" ;; - bfd_elf32_powerpcle_vec) tb="$tb elf32-ppc.lo elf32.lo $elf" ;; + bfd_elf32_powerpc_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; + bfd_elf32_powerpcle_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; + bfd_elf32_powerpc_vxworks_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; bfd_elf32_s390_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;; # FIXME: We include cofflink.lo not because it's needed for # bfd_elf32_sh64[l]_vec, but because we include bfd_elf32_sh[l]_vec diff -uprN binutils-2.16.91.0.1/bfd/configure.in binutils-2.16.91.0.2/bfd/configure.in --- binutils-2.16.91.0.1/bfd/configure.in 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/configure.in 2005-07-20 12:27:27.024237394 -0700 @@ -8,7 +8,7 @@ AC_CONFIG_SRCDIR([libbfd.c]) AC_CANONICAL_TARGET AC_ISC_POSIX -AM_INIT_AUTOMAKE(bfd, 2.16.91.0.1) +AM_INIT_AUTOMAKE(bfd, 2.16.91.0.2) dnl These must be called before AM_PROG_LIBTOOL, because it may want dnl to call AC_CHECK_PROG. @@ -84,7 +84,7 @@ bfd_default_target_size=32 AC_PROG_CC AC_GNU_SOURCE -ALL_LINGUAS="fr tr ja es sv da zh_CN ro rw" +ALL_LINGUAS="fr tr ja es sv da zh_CN ro rw vi" CY_GNU_GETTEXT # Permit host specific settings. @@ -624,6 +624,7 @@ do tb="$tb elf32-arm.lo elf32.lo $elf" ;; bfd_elf32_littlearm_vec) tb="$tb elf32-arm.lo elf32.lo $elf" ;; bfd_elf32_littlemips_vec) tb="$tb elf32-mips.lo elfxx-mips.lo elf32.lo $elf ecofflink.lo" ;; + bfd_elf32_m32c_vec) tb="$tb elf32-m32c.lo elf32.lo $elf" ;; bfd_elf32_m32r_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;; bfd_elf32_m32rle_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;; bfd_elf32_m32rlin_vec) tb="$tb elf32-m32r.lo elf32.lo $elf" ;; @@ -646,8 +647,9 @@ do bfd_elf32_or32_big_vec) tb="$tb elf32-or32.lo elf32.lo $elf" ;; bfd_elf32_pj_vec) tb="$tb elf32-pj.lo elf32.lo $elf";; bfd_elf32_pjl_vec) tb="$tb elf32-pj.lo elf32.lo $elf";; - bfd_elf32_powerpc_vec) tb="$tb elf32-ppc.lo elf32.lo $elf" ;; - bfd_elf32_powerpcle_vec) tb="$tb elf32-ppc.lo elf32.lo $elf" ;; + bfd_elf32_powerpc_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; + bfd_elf32_powerpcle_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; + bfd_elf32_powerpc_vxworks_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;; bfd_elf32_s390_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;; # FIXME: We include cofflink.lo not because it's needed for # bfd_elf32_sh64[l]_vec, but because we include bfd_elf32_sh[l]_vec diff -uprN binutils-2.16.91.0.1/bfd/cpu-d10v.c binutils-2.16.91.0.2/bfd/cpu-d10v.c --- binutils-2.16.91.0.1/bfd/cpu-d10v.c 2005-05-10 15:46:41.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/cpu-d10v.c 2005-07-20 12:27:27.032236075 -0700 @@ -1,22 +1,23 @@ /* BFD support for the D10V processor - Copyright 1996, 1999, 2000, 2002 Free Software Foundation, Inc. + Copyright 1996, 1999, 2000, 2002, 2005 Free Software Foundation, Inc. Contributed by Martin Hunt (hunt@cygnus.com). -This file is part of BFD, the Binary File Descriptor library. + This file is part of BFD, the Binary File Descriptor library. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "bfd.h" #include "sysdep.h" @@ -24,14 +25,14 @@ Foundation, Inc., 51 Franklin Street - F static const bfd_arch_info_type d10v_ts3_info = { - 16, /* 16 bits in a word */ - 16, /* 16 bits in an address */ - 8, /* 8 bits in a byte */ + 16, /* 16 bits in a word. */ + 16, /* 16 bits in an address. */ + 8, /* 8 bits in a byte. */ bfd_arch_d10v, bfd_mach_d10v_ts3, "d10v", "d10v:ts3", - 4, /* section alignment power */ + 4, /* Section alignment power. */ FALSE, bfd_default_compatible, bfd_default_scan, @@ -40,32 +41,32 @@ static const bfd_arch_info_type d10v_ts3 static const bfd_arch_info_type d10v_ts2_info = { - 16, /* 16 bits in a word */ - 16, /* 16 bits in an address */ - 8, /* 8 bits in a byte */ + 16, /* 16 bits in a word. */ + 16, /* 16 bits in an address. */ + 8, /* 8 bits in a byte. */ bfd_arch_d10v, bfd_mach_d10v_ts2, "d10v", "d10v:ts2", - 4, /* section alignment power */ + 4, /* Section alignment power. */ FALSE, bfd_default_compatible, bfd_default_scan, - &d10v_ts3_info, + & d10v_ts3_info, }; const bfd_arch_info_type bfd_d10v_arch = { - 16, /* 16 bits in a word */ - 16, /* 16 bits in an address */ - 8, /* 8 bits in a byte */ + 16, /* 16 bits in a word. */ + 16, /* 16 bits in an address. */ + 8, /* 8 bits in a byte. */ bfd_arch_d10v, bfd_mach_d10v, "d10v", "d10v", - 4, /* section alignment power */ + 4, /* Section alignment power. */ TRUE, bfd_default_compatible, bfd_default_scan, - &d10v_ts2_info, + & d10v_ts2_info, }; diff -uprN binutils-2.16.91.0.1/bfd/cpu-d30v.c binutils-2.16.91.0.2/bfd/cpu-d30v.c --- binutils-2.16.91.0.1/bfd/cpu-d30v.c 2005-05-10 15:46:41.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/cpu-d30v.c 2005-07-20 12:27:27.033235910 -0700 @@ -1,22 +1,23 @@ /* BFD support for the Mitsubishi D30V processor - Copyright 1997, 2002 Free Software Foundation, Inc. + Copyright 1997, 2002, 2005 Free Software Foundation, Inc. Contributed by Martin Hunt (hunt@cygnus.com). -This file is part of BFD, the Binary File Descriptor library. + This file is part of BFD, the Binary File Descriptor library. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "bfd.h" #include "sysdep.h" @@ -24,14 +25,14 @@ Foundation, Inc., 51 Franklin Street - F const bfd_arch_info_type bfd_d30v_arch = { - 32, /* bits in a word */ - 32, /* bits in an address */ - 8, /* bits in a byte */ + 32, /* Bits in a word. */ + 32, /* Bits in an address. */ + 8, /* Bits in a byte. */ bfd_arch_d30v, 0, "d30v", "d30v", - 4, /* section alignment power */ + 4, /* Section alignment power. */ TRUE, bfd_default_compatible, bfd_default_scan, diff -uprN binutils-2.16.91.0.1/bfd/cpu-i370.c binutils-2.16.91.0.2/bfd/cpu-i370.c --- binutils-2.16.91.0.1/bfd/cpu-i370.c 2005-05-10 15:46:41.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/cpu-i370.c 2005-07-20 12:27:27.033235910 -0700 @@ -1,24 +1,25 @@ /* BFD i370 CPU definition - Copyright 1994, 1995, 1996, 1998, 1999, 2000, 2002 + Copyright 1994, 1995, 1996, 1998, 1999, 2000, 2002, 2005 Free Software Foundation, Inc. Contributed by Ian Lance Taylor, Cygnus Support. Hacked by Linas Vepstas in 1998, 1999 -This file is part of BFD, the Binary File Descriptor library. + This file is part of BFD, the Binary File Descriptor library. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "bfd.h" #include "sysdep.h" @@ -26,31 +27,31 @@ Foundation, Inc., 51 Franklin Street - F static const bfd_arch_info_type arch_info_struct[] = { - /* hack alert: old old machines are really 16 and 24 bit arch ... */ + /* Hack alert: old old machines are really 16 and 24 bit arch ... */ { - 32, /* 32 bits in a word */ - 32, /* 32 bits in an address */ - 8, /* 8 bits in a byte */ + 32, /* 32 bits in a word. */ + 32, /* 32 bits in an address. */ + 8, /* 8 bits in a byte. */ bfd_arch_i370, - 360, /* for the 360 */ + 360, /* For the 360. */ "i370", "i370:360", 3, - FALSE, /* not the default */ + FALSE, /* Not the default. */ bfd_default_compatible, bfd_default_scan, &arch_info_struct[1] }, { - 32, /* 32 bits in a word */ - 32, /* 32 bits in an address */ - 8, /* 8 bits in a byte */ + 32, /* 32 bits in a word. */ + 32, /* 32 bits in an address. */ + 8, /* 8 bits in a byte. */ bfd_arch_i370, - 370, /* for the 370 */ + 370, /* For the 370. */ "i370", "i370:370", 3, - FALSE, /* not the default */ + FALSE, /* Not the default. */ bfd_default_compatible, bfd_default_scan, 0 @@ -58,17 +59,17 @@ static const bfd_arch_info_type arch_inf }; const bfd_arch_info_type bfd_i370_arch = - { - 32, /* 32 bits in a word */ - 32, /* 32 bits in an address */ - 8, /* 8 bits in a byte */ - bfd_arch_i370, - 0, /* for the 360/370 common architecture */ - "i370", - "i370:common", - 3, - TRUE, /* the default */ - bfd_default_compatible, - bfd_default_scan, - &arch_info_struct[0] - }; +{ + 32, /* 32 bits in a word. */ + 32, /* 32 bits in an address. */ + 8, /* 8 bits in a byte. */ + bfd_arch_i370, + 0, /* For the 360/370 common architecture. */ + "i370", + "i370:common", + 3, + TRUE, /* The default. */ + bfd_default_compatible, + bfd_default_scan, + & arch_info_struct[0] +}; diff -uprN binutils-2.16.91.0.1/bfd/cpu-m32c.c binutils-2.16.91.0.2/bfd/cpu-m32c.c --- binutils-2.16.91.0.1/bfd/cpu-m32c.c 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/bfd/cpu-m32c.c 2005-07-20 12:27:27.034235745 -0700 @@ -0,0 +1,56 @@ +/* BFD support for the M16C/M32C processors. + Copyright (C) 2004 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" + +static const bfd_arch_info_type arch_info_struct[] = +{ + { + 32, /* bits per word */ + 32, /* bits per address */ + 8, /* bits per byte */ + bfd_arch_m32c, /* architecture */ + bfd_mach_m32c, /* machine */ + "m32c", /* architecture name */ + "m32c", /* printable name */ + 3, /* section align power */ + FALSE, /* the default ? */ + bfd_default_compatible, /* architecture comparison fn */ + bfd_default_scan, /* string to architecture convert fn */ + NULL /* next in list */ + }, +}; + +const bfd_arch_info_type bfd_m32c_arch = +{ + 32, /* Bits per word. */ + 32, /* Bits per address. */ + 8, /* Bits per byte. */ + bfd_arch_m32c, /* Architecture. */ + bfd_mach_m16c, /* Machine. */ + "m32c", /* Architecture name. */ + "m16c", /* Printable name. */ + 4, /* Section align power. */ + TRUE, /* The default ? */ + bfd_default_compatible, /* Architecture comparison fn. */ + bfd_default_scan, /* String to architecture convert fn. */ + &arch_info_struct[0], /* Next in list. */ +}; diff -uprN binutils-2.16.91.0.1/bfd/cpu-xstormy16.c binutils-2.16.91.0.2/bfd/cpu-xstormy16.c --- binutils-2.16.91.0.1/bfd/cpu-xstormy16.c 2005-05-10 15:46:41.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/cpu-xstormy16.c 2005-07-20 12:27:27.037235250 -0700 @@ -1,21 +1,21 @@ /* BFD support for the XSTORMY16 processor. Copyright 2001, 2002 Free Software Foundation, Inc. -This file is part of BFD, the Binary File Descriptor library. + This file is part of BFD, the Binary File Descriptor library. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ #include "bfd.h" #include "sysdep.h" diff -uprN binutils-2.16.91.0.1/bfd/dwarf2.c binutils-2.16.91.0.2/bfd/dwarf2.c --- binutils-2.16.91.0.1/bfd/dwarf2.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/dwarf2.c 2005-07-20 12:27:27.040234756 -0700 @@ -347,16 +347,35 @@ read_indirect_string (struct comp_unit* static bfd_uint64_t read_address (struct comp_unit *unit, bfd_byte *buf) { - switch (unit->addr_size) + int signed_vma = get_elf_backend_data (unit->abfd)->sign_extend_vma; + + if (signed_vma) { - case 8: - return bfd_get_64 (unit->abfd, buf); - case 4: - return bfd_get_32 (unit->abfd, buf); - case 2: - return bfd_get_16 (unit->abfd, buf); - default: - abort (); + switch (unit->addr_size) + { + case 8: + return bfd_get_signed_64 (unit->abfd, buf); + case 4: + return bfd_get_signed_32 (unit->abfd, buf); + case 2: + return bfd_get_signed_16 (unit->abfd, buf); + default: + abort (); + } + } + else + { + switch (unit->addr_size) + { + case 8: + return bfd_get_64 (unit->abfd, buf); + case 4: + return bfd_get_32 (unit->abfd, buf); + case 2: + return bfd_get_16 (unit->abfd, buf); + default: + abort (); + } } } @@ -719,6 +738,7 @@ struct varinfo int line; int tag; char *name; + bfd_vma addr; /* Where the symbol is defined */ asection *sec; /* Is this a stack variable? */ @@ -1495,6 +1515,7 @@ lookup_symbol_in_function_table (struct static bfd_boolean lookup_symbol_in_variable_table (struct comp_unit *unit, asymbol *sym, + bfd_vma addr, const char **filename_ptr, unsigned int *linenumber_ptr) { @@ -1504,6 +1525,9 @@ lookup_symbol_in_variable_table (struct for (each = unit->variable_table; each; each = each->prev_var) if (each->stack == 0 + && each->file != NULL + && each->name != NULL + && each->addr == addr && (!each->sec || each->sec == sec) && strcmp (name, each->name) == 0) break; @@ -1749,21 +1773,23 @@ scan_unit_for_symbols (struct comp_unit break; case DW_AT_location: - if (var->stack) + switch (attr.form) { - switch (attr.form) + case DW_FORM_block: + case DW_FORM_block1: + case DW_FORM_block2: + case DW_FORM_block4: + if (*attr.u.blk->data == DW_OP_addr) { - case DW_FORM_block: - case DW_FORM_block1: - case DW_FORM_block2: - case DW_FORM_block4: - if (*attr.u.blk->data == DW_OP_addr) - var->stack = 0; - break; - - default: - break; + var->stack = 0; + var->addr = bfd_get ((attr.u.blk->size - 1) * 8, + unit->abfd, + attr.u.blk->data + 1); } + break; + + default: + break; } break; @@ -2073,7 +2099,8 @@ comp_unit_find_line (struct comp_unit *u filename_ptr, linenumber_ptr); else - return lookup_symbol_in_variable_table (unit, sym, filename_ptr, + return lookup_symbol_in_variable_table (unit, sym, addr, + filename_ptr, linenumber_ptr); } diff -uprN binutils-2.16.91.0.1/bfd/ecoff.c binutils-2.16.91.0.2/bfd/ecoff.c --- binutils-2.16.91.0.1/bfd/ecoff.c 2005-05-10 15:46:41.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/ecoff.c 2005-07-20 12:27:27.055232283 -0700 @@ -54,12 +54,12 @@ static asection bfd_debug_section = { /* name, id, index, next, prev, flags, user_set_vma, */ "*DEBUG*", 0, 0, NULL, NULL, 0, 0, - /* linker_mark, linker_has_input, gc_mark, segment_mark, */ - 0, 0, 0, 0, - /* sec_info_type, use_rela_p, has_tls_reloc, has_gp_reloc, */ - 0, 0, 0, 0, - /* need_finalize_relax, reloc_done, */ - 0, 0, + /* linker_mark, linker_has_input, gc_mark, gc_mark_from_eh, */ + 0, 0, 1, 0, + /* segment_mark, sec_info_type, use_rela_p, has_tls_reloc, */ + 0, 0, 0, 0, + /* has_gp_reloc, need_finalize_relax, reloc_done, */ + 0, 0, 0, /* vma, lma, size, rawsize, */ 0, 0, 0, 0, /* output_offset, output_section, alignment_power, */ @@ -68,7 +68,7 @@ static asection bfd_debug_section = NULL, NULL, 0, 0, 0, /* line_filepos, userdata, contents, lineno, lineno_count, */ 0, NULL, NULL, NULL, 0, - /* entsize, kept_section, moving_line_filepos, */ + /* entsize, kept_section, moving_line_filepos, */ 0, NULL, 0, /* target_index, used_by_bfd, constructor_chain, owner, */ 0, NULL, NULL, NULL, @@ -2633,6 +2633,7 @@ _bfd_ecoff_write_object_contents (bfd *a reloc_ptr_ptr = current->orelocation; reloc_end = reloc_ptr_ptr + current->reloc_count; out_ptr = (char *) reloc_buff; + for (; reloc_ptr_ptr < reloc_end; reloc_ptr_ptr++, out_ptr += external_reloc_size) @@ -2646,6 +2647,11 @@ _bfd_ecoff_write_object_contents (bfd *a reloc = *reloc_ptr_ptr; sym = *reloc->sym_ptr_ptr; + /* If the howto field has not been initialised then skip this reloc. + This assumes that an error message has been issued elsewhere. */ + if (reloc->howto == NULL) + continue; + in.r_vaddr = (reloc->address + bfd_get_section_vma (abfd, current)); in.r_type = reloc->howto->type; @@ -3182,11 +3188,13 @@ _bfd_ecoff_archive_p (bfd *abfd) } bfd_ardata (abfd)->first_file_filepos = SARMAG; - bfd_ardata (abfd)->cache = NULL; - bfd_ardata (abfd)->archive_head = NULL; - bfd_ardata (abfd)->symdefs = NULL; - bfd_ardata (abfd)->extended_names = NULL; - bfd_ardata (abfd)->tdata = NULL; + /* Already cleared by bfd_zalloc above. + bfd_ardata (abfd)->cache = NULL; + bfd_ardata (abfd)->archive_head = NULL; + bfd_ardata (abfd)->symdefs = NULL; + bfd_ardata (abfd)->extended_names = NULL; + bfd_ardata (abfd)->extended_names_size = 0; + bfd_ardata (abfd)->tdata = NULL; */ if (! _bfd_ecoff_slurp_armap (abfd) || ! _bfd_ecoff_slurp_extended_name_table (abfd)) diff -uprN binutils-2.16.91.0.1/bfd/elf32-arc.c binutils-2.16.91.0.2/bfd/elf32-arc.c --- binutils-2.16.91.0.1/bfd/elf32-arc.c 2005-05-10 15:46:41.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-arc.c 2005-07-20 12:27:27.097225358 -0700 @@ -1,5 +1,5 @@ /* ARC-specific support for 32-bit ELF - Copyright 1994, 1995, 1997, 1999, 2001, 2002 + Copyright 1994, 1995, 1997, 1999, 2001, 2002, 2005 Free Software Foundation, Inc. Contributed by Doug Evans (dje@cygnus.com). @@ -17,7 +17,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "bfd.h" #include "sysdep.h" @@ -26,83 +27,94 @@ #include "elf/arc.h" #include "libiberty.h" -static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup - PARAMS ((bfd *abfd, bfd_reloc_code_real_type code)); -static void arc_info_to_howto_rel - PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); -static bfd_boolean arc_elf_object_p - PARAMS ((bfd *)); -static void arc_elf_final_write_processing - PARAMS ((bfd *, bfd_boolean)); -static bfd_reloc_status_type arc_elf_b22_pcrel - PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); - /* Try to minimize the amount of space occupied by relocation tables on the ROM (not that the ROM won't be swamped by other ELF overhead). */ #define USE_REL 1 +static bfd_reloc_status_type +arc_elf_b22_pcrel (bfd * abfd, + arelent * reloc_entry, + asymbol * symbol, + void * data, + asection * input_section, + bfd * output_bfd, + char ** error_message) +{ + /* If linking, back up the final symbol address by the address of the + reloc. This cannot be accomplished by setting the pcrel_offset + field to TRUE, as bfd_install_relocation will detect this and refuse + to install the offset in the first place, but bfd_perform_relocation + will still insist on removing it. */ + if (output_bfd == NULL) + reloc_entry->addend -= reloc_entry->address; + + /* Fall through to the default elf reloc handler. */ + return bfd_elf_generic_reloc (abfd, reloc_entry, symbol, data, + input_section, output_bfd, error_message); +} + static reloc_howto_type elf_arc_howto_table[] = { /* This reloc does nothing. */ - HOWTO (R_ARC_NONE, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_ARC_NONE", /* name */ - TRUE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE), /* pcrel_offset */ + HOWTO (R_ARC_NONE, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 32, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_bitfield, /* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_ARC_NONE", /* Name. */ + TRUE, /* Partial_inplace. */ + 0, /* Src_mask. */ + 0, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ /* A standard 32 bit relocation. */ - HOWTO (R_ARC_32, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_ARC_32", /* name */ - TRUE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ - FALSE), /* pcrel_offset */ + HOWTO (R_ARC_32, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 32, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_bitfield, /* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_ARC_32", /* Name. */ + TRUE, /* Partial_inplace. */ + 0xffffffff, /* Src_mask. */ + 0xffffffff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ /* A 26 bit absolute branch, right shifted by 2. */ - HOWTO (R_ARC_B26, /* type */ - 2, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 26, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_ARC_B26", /* name */ - TRUE, /* partial_inplace */ - 0x00ffffff, /* src_mask */ - 0x00ffffff, /* dst_mask */ - FALSE), /* pcrel_offset */ + HOWTO (R_ARC_B26, /* Type. */ + 2, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 26, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_bitfield, /* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_ARC_B26", /* Name. */ + TRUE, /* Partial_inplace. */ + 0x00ffffff, /* Src_mask. */ + 0x00ffffff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ /* A relative 22 bit branch; bits 21-2 are stored in bits 26-7. */ - HOWTO (R_ARC_B22_PCREL, /* type */ - 2, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 22, /* bitsize */ - TRUE, /* pc_relative */ - 7, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - arc_elf_b22_pcrel, /* special_function */ - "R_ARC_B22_PCREL", /* name */ - TRUE, /* partial_inplace */ - 0x07ffff80, /* src_mask */ - 0x07ffff80, /* dst_mask */ - FALSE), /* pcrel_offset */ + HOWTO (R_ARC_B22_PCREL, /* Type. */ + 2, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 22, /* Bitsize. */ + TRUE, /* PC_relative. */ + 7, /* Bitpos. */ + complain_overflow_signed, /* Complain_on_overflow. */ + arc_elf_b22_pcrel, /* Special_function. */ + "R_ARC_B22_PCREL", /* Name. */ + TRUE, /* Partial_inplace. */ + 0x07ffff80, /* Src_mask. */ + 0x07ffff80, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ }; /* Map BFD reloc types to ARC ELF reloc types. */ @@ -123,9 +135,8 @@ static const struct arc_reloc_map arc_re }; static reloc_howto_type * -bfd_elf32_bfd_reloc_type_lookup (abfd, code) - bfd *abfd ATTRIBUTE_UNUSED; - bfd_reloc_code_real_type code; +bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) { unsigned int i; @@ -139,10 +150,9 @@ bfd_elf32_bfd_reloc_type_lookup (abfd, c /* Set the howto pointer for an ARC ELF reloc. */ static void -arc_info_to_howto_rel (abfd, cache_ptr, dst) - bfd *abfd ATTRIBUTE_UNUSED; - arelent *cache_ptr; - Elf_Internal_Rela *dst; +arc_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED, + arelent *cache_ptr, + Elf_Internal_Rela *dst) { unsigned int r_type; @@ -154,8 +164,7 @@ arc_info_to_howto_rel (abfd, cache_ptr, /* Set the right machine number for an ARC ELF file. */ static bfd_boolean -arc_elf_object_p (abfd) - bfd *abfd; +arc_elf_object_p (bfd *abfd) { unsigned int mach = bfd_mach_arc_6; @@ -187,9 +196,8 @@ arc_elf_object_p (abfd) This gets the ARC architecture right based on the machine number. */ static void -arc_elf_final_write_processing (abfd, linker) - bfd *abfd; - bfd_boolean linker ATTRIBUTE_UNUSED; +arc_elf_final_write_processing (bfd *abfd, + bfd_boolean linker ATTRIBUTE_UNUSED) { unsigned long val; @@ -213,41 +221,17 @@ arc_elf_final_write_processing (abfd, li elf_elfheader (abfd)->e_flags |= val; } -bfd_reloc_status_type -arc_elf_b22_pcrel (abfd, reloc_entry, symbol, data, input_section, - output_bfd, error_message) - bfd * abfd; - arelent * reloc_entry; - asymbol * symbol; - PTR data; - asection * input_section; - bfd * output_bfd; - char ** error_message; -{ - /* If linking, back up the final symbol address by the address of the - reloc. This cannot be accomplished by setting the pcrel_offset - field to TRUE, as bfd_install_relocation will detect this and refuse - to install the offset in the first place, but bfd_perform_relocation - will still insist on removing it. */ - if (output_bfd == (bfd *) NULL) - reloc_entry->addend -= reloc_entry->address; - - /* Fall through to the default elf reloc handler. */ - return bfd_elf_generic_reloc (abfd, reloc_entry, symbol, data, - input_section, output_bfd, error_message); -} - -#define TARGET_LITTLE_SYM bfd_elf32_littlearc_vec -#define TARGET_LITTLE_NAME "elf32-littlearc" -#define TARGET_BIG_SYM bfd_elf32_bigarc_vec -#define TARGET_BIG_NAME "elf32-bigarc" -#define ELF_ARCH bfd_arch_arc -#define ELF_MACHINE_CODE EM_ARC -#define ELF_MAXPAGESIZE 0x1000 - -#define elf_info_to_howto 0 -#define elf_info_to_howto_rel arc_info_to_howto_rel -#define elf_backend_object_p arc_elf_object_p -#define elf_backend_final_write_processing arc_elf_final_write_processing +#define TARGET_LITTLE_SYM bfd_elf32_littlearc_vec +#define TARGET_LITTLE_NAME "elf32-littlearc" +#define TARGET_BIG_SYM bfd_elf32_bigarc_vec +#define TARGET_BIG_NAME "elf32-bigarc" +#define ELF_ARCH bfd_arch_arc +#define ELF_MACHINE_CODE EM_ARC +#define ELF_MAXPAGESIZE 0x1000 + +#define elf_info_to_howto 0 +#define elf_info_to_howto_rel arc_info_to_howto_rel +#define elf_backend_object_p arc_elf_object_p +#define elf_backend_final_write_processing arc_elf_final_write_processing #include "elf32-target.h" diff -uprN binutils-2.16.91.0.1/bfd/elf32-arm.c binutils-2.16.91.0.2/bfd/elf32-arm.c --- binutils-2.16.91.0.1/bfd/elf32-arm.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-arm.c 2005-07-20 12:27:27.115222390 -0700 @@ -5852,7 +5852,6 @@ elf32_arm_size_dynamic_sections (bfd * o for (s = dynobj->sections; s != NULL; s = s->next) { const char * name; - bfd_boolean strip; if ((s->flags & SEC_LINKER_CREATED) == 0) continue; @@ -5861,38 +5860,14 @@ elf32_arm_size_dynamic_sections (bfd * o of the dynobj section names depend upon the input files. */ name = bfd_get_section_name (dynobj, s); - strip = FALSE; - if (strcmp (name, ".plt") == 0) { - if (s->size == 0) - { - /* Strip this section if we don't need it; see the - comment below. */ - strip = TRUE; - } - else - { - /* Remember whether there is a PLT. */ - plt = TRUE; - } + /* Remember whether there is a PLT. */ + plt = s->size != 0; } else if (strncmp (name, ".rel", 4) == 0) { - if (s->size == 0) - { - /* If we don't need this section, strip it from the - output file. This is mostly to handle .rel.bss and - .rel.plt. We must create both sections in - create_dynamic_sections, because they must be created - before the linker maps input sections to output - sections. The linker does that before - adjust_dynamic_symbol is called, and it is that - function which decides whether anything needs to go - into these sections. */ - strip = TRUE; - } - else + if (s->size != 0) { /* Remember whether there are any reloc sections other than .rel.plt. */ @@ -5904,21 +5879,34 @@ elf32_arm_size_dynamic_sections (bfd * o s->reloc_count = 0; } } - else if (strncmp (name, ".got", 4) != 0) + else if (strncmp (name, ".got", 4) != 0 + && strcmp (name, ".dynbss") != 0) { /* It's not one of our sections, so don't allocate space. */ continue; } - if (strip) + if (s->size == 0) { + /* If we don't need this section, strip it from the + output file. This is mostly to handle .rel.bss and + .rel.plt. We must create both sections in + create_dynamic_sections, because they must be created + before the linker maps input sections to output + sections. The linker does that before + adjust_dynamic_symbol is called, and it is that + function which decides whether anything needs to go + into these sections. */ s->flags |= SEC_EXCLUDE; continue; } + if ((s->flags & SEC_HAS_CONTENTS) == 0) + continue; + /* Allocate memory for the section contents. */ s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); - if (s->contents == NULL && s->size != 0) + if (s->contents == NULL) return FALSE; } @@ -5932,7 +5920,7 @@ elf32_arm_size_dynamic_sections (bfd * o #define add_dynamic_entry(TAG, VAL) \ _bfd_elf_add_dynamic_entry (info, TAG, VAL) - if (!info->shared) + if (info->executable) { if (!add_dynamic_entry (DT_DEBUG, 0)) return FALSE; @@ -5965,10 +5953,9 @@ elf32_arm_size_dynamic_sections (bfd * o { if (!add_dynamic_entry (DT_TEXTREL, 0)) return FALSE; - info->flags |= DF_TEXTREL; } } -#undef add_synamic_entry +#undef add_dynamic_entry return TRUE; } @@ -6942,8 +6929,8 @@ elf32_arm_symbian_link_hash_table_create return ret; } -static struct bfd_elf_special_section const - symbian_special_sections_d[]= +static const struct bfd_elf_special_section +elf32_arm_symbian_special_sections[] = { /* In a BPABI executable, the dynamic linking sections do not go in the loadable read-only segment. The post-linker may wish to @@ -6952,93 +6939,17 @@ static struct bfd_elf_special_section co { ".dynamic", 8, 0, SHT_DYNAMIC, 0 }, { ".dynstr", 7, 0, SHT_STRTAB, 0 }, { ".dynsym", 7, 0, SHT_DYNSYM, 0 }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - symbian_special_sections_g[]= -{ - /* In a BPABI executable, the dynamic linking sections do not go in - the loadable read-only segment. The post-linker may wish to - refer to these sections, but they are not part of the final - program image. */ { ".got", 4, 0, SHT_PROGBITS, 0 }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - symbian_special_sections_h[]= -{ - /* In a BPABI executable, the dynamic linking sections do not go in - the loadable read-only segment. The post-linker may wish to - refer to these sections, but they are not part of the final - program image. */ { ".hash", 5, 0, SHT_HASH, 0 }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - symbian_special_sections_i[]= -{ /* These sections do not need to be writable as the SymbianOS postlinker will arrange things so that no dynamic relocation is required. */ { ".init_array", 11, 0, SHT_INIT_ARRAY, SHF_ALLOC }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - symbian_special_sections_f[]= -{ - /* These sections do not need to be writable as the SymbianOS - postlinker will arrange things so that no dynamic relocation is - required. */ { ".fini_array", 11, 0, SHT_FINI_ARRAY, SHF_ALLOC }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - symbian_special_sections_p[]= -{ - /* These sections do not need to be writable as the SymbianOS - postlinker will arrange things so that no dynamic relocation is - required. */ { ".preinit_array", 14, 0, SHT_PREINIT_ARRAY, SHF_ALLOC }, { NULL, 0, 0, 0, 0 } }; -static struct bfd_elf_special_section const * - elf32_arm_symbian_special_sections[27]= -{ - NULL, /* 'a' */ - NULL, /* 'b' */ - NULL, /* 'c' */ - symbian_special_sections_d, /* 'd' */ - NULL, /* 'e' */ - symbian_special_sections_f, /* 'f' */ - symbian_special_sections_g, /* 'g' */ - symbian_special_sections_h, /* 'h' */ - symbian_special_sections_i, /* 'i' */ - NULL, /* 'j' */ - NULL, /* 'k' */ - NULL, /* 'l' */ - NULL, /* 'm' */ - NULL, /* 'n' */ - NULL, /* 'o' */ - symbian_special_sections_p, /* 'p' */ - NULL, /* 'q' */ - NULL, /* 'r' */ - NULL, /* 's' */ - NULL, /* 't' */ - NULL, /* 'u' */ - NULL, /* 'v' */ - NULL, /* 'w' */ - NULL, /* 'x' */ - NULL, /* 'y' */ - NULL, /* 'z' */ - NULL /* other */ -}; - static void elf32_arm_symbian_begin_write_processing (bfd *abfd, struct bfd_link_info *link_info diff -uprN binutils-2.16.91.0.1/bfd/elf32-cris.c binutils-2.16.91.0.2/bfd/elf32-cris.c --- binutils-2.16.91.0.1/bfd/elf32-cris.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-cris.c 2005-07-20 12:27:27.126220577 -0700 @@ -2935,7 +2935,6 @@ elf_cris_size_dynamic_sections (output_b for (s = dynobj->sections; s != NULL; s = s->next) { const char *name; - bfd_boolean strip; if ((s->flags & SEC_LINKER_CREATED) == 0) continue; @@ -2944,38 +2943,14 @@ elf_cris_size_dynamic_sections (output_b of the dynobj section names depend upon the input files. */ name = bfd_get_section_name (dynobj, s); - strip = FALSE; - if (strcmp (name, ".plt") == 0) { - if (s->size == 0) - { - /* Strip this section if we don't need it; see the - comment below. */ - strip = TRUE; - } - else - { - /* Remember whether there is a PLT. */ - plt = TRUE; - } + /* Remember whether there is a PLT. */ + plt = s->size != 0; } else if (strncmp (name, ".rela", 5) == 0) { - if (s->size == 0) - { - /* If we don't need this section, strip it from the - output file. This is mostly to handle .rela.bss and - .rela.plt. We must create both sections in - create_dynamic_sections, because they must be created - before the linker maps input sections to output - sections. The linker does that before - adjust_dynamic_symbol is called, and it is that - function which decides whether anything needs to go - into these sections. */ - strip = TRUE; - } - else + if (s->size != 0) { /* Remember whether there are any reloc sections other than .rela.plt. */ @@ -2987,25 +2962,38 @@ elf_cris_size_dynamic_sections (output_b s->reloc_count = 0; } } - else if (strncmp (name, ".got", 4) != 0) + else if (strncmp (name, ".got", 4) != 0 + && strcmp (name, ".dynbss") != 0) { /* It's not one of our sections, so don't allocate space. */ continue; } - if (strip) + if (s->size == 0) { + /* If we don't need this section, strip it from the + output file. This is mostly to handle .rela.bss and + .rela.plt. We must create both sections in + create_dynamic_sections, because they must be created + before the linker maps input sections to output + sections. The linker does that before + adjust_dynamic_symbol is called, and it is that + function which decides whether anything needs to go + into these sections. */ s->flags |= SEC_EXCLUDE; continue; } + if ((s->flags & SEC_HAS_CONTENTS) == 0) + continue; + /* Allocate memory for the section contents. We use bfd_zalloc here in case unused entries are not reclaimed before the section's contents are written out. This should not happen, but this way if it does, we will not write out garbage. For reloc sections, this will make entries have the type R_CRIS_NONE. */ s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); - if (s->contents == NULL && s->size != 0) + if (s->contents == NULL) return FALSE; } diff -uprN binutils-2.16.91.0.1/bfd/elf32-d10v.c binutils-2.16.91.0.2/bfd/elf32-d10v.c --- binutils-2.16.91.0.1/bfd/elf32-d10v.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-d10v.c 2005-07-20 12:27:27.128220247 -0700 @@ -1,23 +1,24 @@ /* D10V-specific support for 32-bit ELF - Copyright 1996, 1998, 1999, 2000, 2001, 2002, 2003, 2004 + Copyright 1996, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. Contributed by Martin Hunt (hunt@cygnus.com). -This file is part of BFD, the Binary File Descriptor library. + This file is part of BFD, the Binary File Descriptor library. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "bfd.h" #include "sysdep.h" @@ -25,206 +26,179 @@ Foundation, Inc., 51 Franklin Street - F #include "elf-bfd.h" #include "elf/d10v.h" -static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup - PARAMS ((bfd *abfd, bfd_reloc_code_real_type code)); -static void d10v_info_to_howto_rel - PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); -static asection * elf32_d10v_gc_mark_hook - PARAMS ((asection *, struct bfd_link_info *, Elf_Internal_Rela *, - struct elf_link_hash_entry *, Elf_Internal_Sym *)); -static bfd_boolean elf32_d10v_gc_sweep_hook - PARAMS ((bfd *, struct bfd_link_info *, asection *, - const Elf_Internal_Rela *)); -static bfd_boolean elf32_d10v_check_relocs - PARAMS ((bfd *, struct bfd_link_info *, asection *, - const Elf_Internal_Rela *)); -static bfd_vma extract_rel_addend - PARAMS ((bfd *, bfd_byte *, reloc_howto_type *)); -static void insert_rel_addend - PARAMS ((bfd *, bfd_byte *, reloc_howto_type *, bfd_vma)); -static bfd_boolean elf32_d10v_relocate_section - PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, - bfd_byte *, Elf_Internal_Rela *, Elf_Internal_Sym *, - asection **)); - /* Use REL instead of RELA to save space. */ #define USE_REL 1 static reloc_howto_type elf_d10v_howto_table[] = - { - /* This reloc does nothing. */ - HOWTO (R_D10V_NONE, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_D10V_NONE", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* An PC Relative 10-bit relocation, shifted by 2 */ - /* right container */ - HOWTO (R_D10V_10_PCREL_R, /* type */ - 2, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 7, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_D10V_10_PCREL_R", /* name */ - FALSE, /* partial_inplace */ - 0xff, /* src_mask */ - 0xff, /* dst_mask */ - TRUE), /* pcrel_offset */ - - /* An PC Relative 10-bit relocation, shifted by 2 */ - /* left container */ - HOWTO (R_D10V_10_PCREL_L, /* type */ - 2, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 7, /* bitsize */ - TRUE, /* pc_relative */ - 15, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_D10V_10_PCREL_L", /* name */ - FALSE, /* partial_inplace */ - 0x07f8000, /* src_mask */ - 0x07f8000, /* dst_mask */ - TRUE), /* pcrel_offset */ - - /* A 16 bit absolute relocation */ - HOWTO (R_D10V_16, /* type */ - 0, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_D10V_16", /* name */ - FALSE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* An 18 bit absolute relocation, right shifted 2 */ - HOWTO (R_D10V_18, /* type */ - 2, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_D10V_18", /* name */ - FALSE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* A relative 18 bit relocation, right shifted by 2 */ - HOWTO (R_D10V_18_PCREL, /* type */ - 2, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 15, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_D10V_18_PCREL", /* name */ - FALSE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xffff, /* dst_mask */ - TRUE), /* pcrel_offset */ - - /* A 32 bit absolute relocation */ - HOWTO (R_D10V_32, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_D10V_32", /* name */ - FALSE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* GNU extension to record C++ vtable hierarchy */ - HOWTO (R_D10V_GNU_VTINHERIT, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 0, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - NULL, /* special_function */ - "R_D10V_GNU_VTINHERIT", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* GNU extension to record C++ vtable member usage */ - HOWTO (R_D10V_GNU_VTENTRY, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 0, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - _bfd_elf_rel_vtable_reloc_fn, /* special_function */ - "R_D10V_GNU_VTENTRY", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE), /* pcrel_offset */ - }; +{ + /* This reloc does nothing. */ + HOWTO (R_D10V_NONE, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 32, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont,/* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_D10V_NONE", /* Name. */ + FALSE, /* Partial_inplace. */ + 0, /* Src_mask. */ + 0, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* An PC Relative 10-bit relocation, shifted by 2, right container. */ + HOWTO (R_D10V_10_PCREL_R, /* Type. */ + 2, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 7, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_bitfield, /* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_D10V_10_PCREL_R", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xff, /* Src_mask. */ + 0xff, /* Dst_mask. */ + TRUE), /* PCrel_offset. */ + + /* An PC Relative 10-bit relocation, shifted by 2, left container. */ + HOWTO (R_D10V_10_PCREL_L, /* Type. */ + 2, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 7, /* Bitsize. */ + TRUE, /* PC_relative. */ + 15, /* Bitpos. */ + complain_overflow_bitfield, /* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_D10V_10_PCREL_L", /* Name. */ + FALSE, /* Partial_inplace. */ + 0x07f8000, /* Src_mask. */ + 0x07f8000, /* Dst_mask. */ + TRUE), /* PCrel_offset. */ + + /* A 16 bit absolute relocation. */ + HOWTO (R_D10V_16, /* Type. */ + 0, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont,/* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_D10V_16", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xffff, /* Src_mask. */ + 0xffff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* An 18 bit absolute relocation, right shifted 2. */ + HOWTO (R_D10V_18, /* Type. */ + 2, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_D10V_18", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xffff, /* Src_mask. */ + 0xffff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* A relative 18 bit relocation, right shifted by 2. */ + HOWTO (R_D10V_18_PCREL, /* Type. */ + 2, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 15, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_bitfield, /* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_D10V_18_PCREL", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xffff, /* Src_mask. */ + 0xffff, /* Dst_mask. */ + TRUE), /* PCrel_offset. */ + + /* A 32 bit absolute relocation. */ + HOWTO (R_D10V_32, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 32, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont,/* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_D10V_32", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xffffffff, /* Src_mask. */ + 0xffffffff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* GNU extension to record C++ vtable hierarchy. */ + HOWTO (R_D10V_GNU_VTINHERIT, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 0, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont,/* Complain_on_overflow. */ + NULL, /* Special_function. */ + "R_D10V_GNU_VTINHERIT",/* Name. */ + FALSE, /* Partial_inplace. */ + 0, /* Src_mask. */ + 0, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* GNU extension to record C++ vtable member usage. */ + HOWTO (R_D10V_GNU_VTENTRY, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 0, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont,/* Complain_on_overflow. */ + _bfd_elf_rel_vtable_reloc_fn, /* Special_function. */ + "R_D10V_GNU_VTENTRY", /* Name. */ + FALSE, /* Partial_inplace. */ + 0, /* Src_mask. */ + 0, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ +}; /* Map BFD reloc types to D10V ELF reloc types. */ struct d10v_reloc_map - { - bfd_reloc_code_real_type bfd_reloc_val; - unsigned char elf_reloc_val; - }; +{ + bfd_reloc_code_real_type bfd_reloc_val; + unsigned char elf_reloc_val; +}; static const struct d10v_reloc_map d10v_reloc_map[] = - { - { BFD_RELOC_NONE, R_D10V_NONE, }, - { BFD_RELOC_D10V_10_PCREL_R, R_D10V_10_PCREL_R }, - { BFD_RELOC_D10V_10_PCREL_L, R_D10V_10_PCREL_L }, - { BFD_RELOC_16, R_D10V_16 }, - { BFD_RELOC_D10V_18, R_D10V_18 }, - { BFD_RELOC_D10V_18_PCREL, R_D10V_18_PCREL }, - { BFD_RELOC_32, R_D10V_32 }, - { BFD_RELOC_VTABLE_INHERIT, R_D10V_GNU_VTINHERIT }, - { BFD_RELOC_VTABLE_ENTRY, R_D10V_GNU_VTENTRY }, - }; +{ + { BFD_RELOC_NONE, R_D10V_NONE, }, + { BFD_RELOC_D10V_10_PCREL_R, R_D10V_10_PCREL_R }, + { BFD_RELOC_D10V_10_PCREL_L, R_D10V_10_PCREL_L }, + { BFD_RELOC_16, R_D10V_16 }, + { BFD_RELOC_D10V_18, R_D10V_18 }, + { BFD_RELOC_D10V_18_PCREL, R_D10V_18_PCREL }, + { BFD_RELOC_32, R_D10V_32 }, + { BFD_RELOC_VTABLE_INHERIT, R_D10V_GNU_VTINHERIT }, + { BFD_RELOC_VTABLE_ENTRY, R_D10V_GNU_VTENTRY }, +}; static reloc_howto_type * -bfd_elf32_bfd_reloc_type_lookup (abfd, code) - bfd *abfd ATTRIBUTE_UNUSED; - bfd_reloc_code_real_type code; +bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) { unsigned int i; for (i = 0; i < sizeof (d10v_reloc_map) / sizeof (struct d10v_reloc_map); i++) - { - if (d10v_reloc_map[i].bfd_reloc_val == code) - return &elf_d10v_howto_table[d10v_reloc_map[i].elf_reloc_val]; - } + if (d10v_reloc_map[i].bfd_reloc_val == code) + return &elf_d10v_howto_table[d10v_reloc_map[i].elf_reloc_val]; return NULL; } @@ -232,10 +206,9 @@ bfd_elf32_bfd_reloc_type_lookup (abfd, c /* Set the howto pointer for an D10V ELF reloc. */ static void -d10v_info_to_howto_rel (abfd, cache_ptr, dst) - bfd *abfd ATTRIBUTE_UNUSED; - arelent *cache_ptr; - Elf_Internal_Rela *dst; +d10v_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED, + arelent *cache_ptr, + Elf_Internal_Rela *dst) { unsigned int r_type; @@ -245,12 +218,11 @@ d10v_info_to_howto_rel (abfd, cache_ptr, } static asection * -elf32_d10v_gc_mark_hook (sec, info, rel, h, sym) - asection *sec; - struct bfd_link_info *info ATTRIBUTE_UNUSED; - Elf_Internal_Rela *rel; - struct elf_link_hash_entry *h; - Elf_Internal_Sym *sym; +elf32_d10v_gc_mark_hook (asection *sec, + struct bfd_link_info *info ATTRIBUTE_UNUSED, + Elf_Internal_Rela *rel, + struct elf_link_hash_entry *h, + Elf_Internal_Sym *sym) { if (h != NULL) { @@ -282,13 +254,12 @@ elf32_d10v_gc_mark_hook (sec, info, rel, } static bfd_boolean -elf32_d10v_gc_sweep_hook (abfd, info, sec, relocs) - bfd *abfd ATTRIBUTE_UNUSED; - struct bfd_link_info *info ATTRIBUTE_UNUSED; - asection *sec ATTRIBUTE_UNUSED; - const Elf_Internal_Rela *relocs ATTRIBUTE_UNUSED; +elf32_d10v_gc_sweep_hook (bfd *abfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info ATTRIBUTE_UNUSED, + asection *sec ATTRIBUTE_UNUSED, + const Elf_Internal_Rela *relocs ATTRIBUTE_UNUSED) { - /* we don't use got and plt entries for d10v */ + /* We don't use got and plt entries for d10v. */ return TRUE; } @@ -297,11 +268,10 @@ elf32_d10v_gc_sweep_hook (abfd, info, se virtual table relocs for gc. */ static bfd_boolean -elf32_d10v_check_relocs (abfd, info, sec, relocs) - bfd *abfd; - struct bfd_link_info *info; - asection *sec; - const Elf_Internal_Rela *relocs; +elf32_d10v_check_relocs (bfd *abfd, + struct bfd_link_info *info, + asection *sec, + const Elf_Internal_Rela *relocs) { Elf_Internal_Shdr *symtab_hdr; struct elf_link_hash_entry **sym_hashes, **sym_hashes_end; @@ -356,10 +326,9 @@ elf32_d10v_check_relocs (abfd, info, sec } static bfd_vma -extract_rel_addend (abfd, where, howto) - bfd *abfd; - bfd_byte *where; - reloc_howto_type *howto; +extract_rel_addend (bfd *abfd, + bfd_byte *where, + reloc_howto_type *howto) { bfd_vma insn, val; @@ -392,11 +361,10 @@ extract_rel_addend (abfd, where, howto) } static void -insert_rel_addend (abfd, where, howto, addend) - bfd *abfd; - bfd_byte *where; - reloc_howto_type *howto; - bfd_vma addend; +insert_rel_addend (bfd *abfd, + bfd_byte *where, + reloc_howto_type *howto, + bfd_vma addend) { bfd_vma insn; @@ -425,17 +393,16 @@ insert_rel_addend (abfd, where, howto, a } /* Relocate a D10V ELF section. */ + static bfd_boolean -elf32_d10v_relocate_section (output_bfd, info, input_bfd, input_section, - contents, relocs, local_syms, local_sections) - bfd *output_bfd; - struct bfd_link_info *info; - bfd *input_bfd; - asection *input_section; - bfd_byte *contents; - Elf_Internal_Rela *relocs; - Elf_Internal_Sym *local_syms; - asection **local_sections; +elf32_d10v_relocate_section (bfd *output_bfd, + struct bfd_link_info *info, + bfd *input_bfd, + asection *input_section, + bfd_byte *contents, + Elf_Internal_Rela *relocs, + Elf_Internal_Sym *local_syms, + asection **local_sections) { Elf_Internal_Shdr *symtab_hdr; struct elf_link_hash_entry **sym_hashes; @@ -462,7 +429,7 @@ elf32_d10v_relocate_section (output_bfd, r_type = ELF32_R_TYPE (rel->r_info); if (r_type == R_D10V_GNU_VTENTRY - || r_type == R_D10V_GNU_VTINHERIT ) + || r_type == R_D10V_GNU_VTINHERIT) continue; howto = elf_d10v_howto_table + r_type; @@ -552,7 +519,7 @@ elf32_d10v_relocate_section (output_bfd, { case bfd_reloc_overflow: if (!((*info->callbacks->reloc_overflow) - (info, (h ? &h->root : NULL), name, howto->name, + (info, (h ? &h->root : NULL), name, howto->name, (bfd_vma) 0, input_bfd, input_section, rel->r_offset))) return FALSE; diff -uprN binutils-2.16.91.0.1/bfd/elf32-d30v.c binutils-2.16.91.0.2/bfd/elf32-d30v.c --- binutils-2.16.91.0.1/bfd/elf32-d30v.c 2005-05-10 15:46:41.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-d30v.c 2005-07-20 12:27:27.132219587 -0700 @@ -1,23 +1,24 @@ /* D30V-specific support for 32-bit ELF - Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 + Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. Contributed by Martin Hunt (hunt@cygnus.com). -This file is part of BFD, the Binary File Descriptor library. + This file is part of BFD, the Binary File Descriptor library. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "bfd.h" #include "sysdep.h" @@ -25,240 +26,17 @@ Foundation, Inc., 51 Franklin Street - F #include "elf-bfd.h" #include "elf/d30v.h" -static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup - PARAMS ((bfd *abfd, bfd_reloc_code_real_type code)); -static void d30v_info_to_howto_rel - PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); -static void d30v_info_to_howto_rela - PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); -static bfd_reloc_status_type bfd_elf_d30v_reloc PARAMS (( - bfd *abfd, - arelent *reloc_entry, - asymbol *symbol, - PTR data, - asection *input_section, - bfd *output_bfd, - char **error_message)); -static bfd_reloc_status_type bfd_elf_d30v_reloc_21 PARAMS (( - bfd *abfd, - arelent *reloc_entry, - asymbol *symbol, - PTR data, - asection *input_section, - bfd *output_bfd, - char **error_message)); - -static reloc_howto_type elf_d30v_howto_table[] = -{ - /* This reloc does nothing. */ - HOWTO (R_D30V_NONE, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_D30V_NONE", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* A 6 bit absolute relocation */ - HOWTO (R_D30V_6, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 6, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_D30V_6", /* name */ - FALSE, /* partial_inplace */ - 0x3f, /* src_mask */ - 0x3f, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* A relative 9 bit relocation, right shifted by 3 */ - HOWTO (R_D30V_9_PCREL, /* type */ - 3, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 6, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - bfd_elf_d30v_reloc_21, /* special_function */ - "R_D30V_9_PCREL", /* name */ - FALSE, /* partial_inplace */ - 0x3f, /* src_mask */ - 0x3f, /* dst_mask */ - TRUE), /* pcrel_offset */ - - /* A relative 9 bit relocation, right shifted by 3 */ - HOWTO (R_D30V_9_PCREL_R, /* type */ - 3, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 6, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - bfd_elf_d30v_reloc_21, /* special_function */ - "R_D30V_9_PCREL_R", /* name */ - FALSE, /* partial_inplace */ - 0x3f, /* src_mask */ - 0x3f, /* dst_mask */ - TRUE), /* pcrel_offset */ - - /* An absolute 15 bit relocation, right shifted by 3 */ - HOWTO (R_D30V_15, /* type */ - 3, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 12, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_D30V_15", /* name */ - FALSE, /* partial_inplace */ - 0xfff, /* src_mask */ - 0xfff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* A relative 15 bit relocation, right shifted by 3 */ - HOWTO (R_D30V_15_PCREL, /* type */ - 3, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 12, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - bfd_elf_d30v_reloc_21, /* special_function */ - "R_D30V_15_PCREL", /* name */ - FALSE, /* partial_inplace */ - 0xfff, /* src_mask */ - 0xfff, /* dst_mask */ - TRUE), /* pcrel_offset */ - - /* A relative 15 bit relocation, right shifted by 3 */ - HOWTO (R_D30V_15_PCREL_R, /* type */ - 3, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 12, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - bfd_elf_d30v_reloc_21, /* special_function */ - "R_D30V_15_PCREL_R", /* name */ - FALSE, /* partial_inplace */ - 0xfff, /* src_mask */ - 0xfff, /* dst_mask */ - TRUE), /* pcrel_offset */ - - /* An absolute 21 bit relocation, right shifted by 3 */ - HOWTO (R_D30V_21, /* type */ - 3, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 18, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_D30V_21", /* name */ - FALSE, /* partial_inplace */ - 0x3ffff, /* src_mask */ - 0x3ffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* A relative 21 bit relocation, right shifted by 3 */ - HOWTO (R_D30V_21_PCREL, /* type */ - 3, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 18, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - bfd_elf_d30v_reloc_21, /* special_function */ - "R_D30V_21_PCREL", /* name */ - FALSE, /* partial_inplace */ - 0x3ffff, /* src_mask */ - 0x3ffff, /* dst_mask */ - TRUE), /* pcrel_offset */ - - /* A relative 21 bit relocation, right shifted by 3, in the Right container */ - HOWTO (R_D30V_21_PCREL_R, /* type */ - 3, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 18, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - bfd_elf_d30v_reloc_21, /* special_function */ - "R_D30V_21_PCREL_R", /* name */ - FALSE, /* partial_inplace */ - 0x3ffff, /* src_mask */ - 0x3ffff, /* dst_mask */ - TRUE), /* pcrel_offset */ - - /* A D30V 32 bit absolute relocation */ - HOWTO (R_D30V_32, /* type */ - 0, /* rightshift */ - 4, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_d30v_reloc, /* special_function */ - "R_D30V_32", /* name */ - FALSE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* A relative 32 bit relocation */ - HOWTO (R_D30V_32_PCREL, /* type */ - 0, /* rightshift */ - 4, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - bfd_elf_d30v_reloc, /* special_function */ - "R_D30V_32_PCREL", /* name */ - FALSE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ - TRUE), /* pcrel_offset */ - - /* A regular 32 bit absolute relocation */ - HOWTO (R_D30V_32_NORMAL, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_D30V_32_NORMAL", /* name */ - FALSE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - -}; - #define MAX32 ((bfd_signed_vma) 0x7fffffff) #define MIN32 (- MAX32 - 1) static bfd_reloc_status_type -bfd_elf_d30v_reloc (abfd, reloc_entry, symbol, data, input_section, output_bfd, error_message) - bfd *abfd; - arelent *reloc_entry; - asymbol *symbol; - PTR data; - asection *input_section; - bfd *output_bfd; - char **error_message; +bfd_elf_d30v_reloc (bfd *abfd, + arelent *reloc_entry, + asymbol *symbol, + void * data, + asection *input_section, + bfd *output_bfd, + char **error_message) { bfd_signed_vma relocation; bfd_vma in1, in2, num; @@ -271,7 +49,7 @@ bfd_elf_d30v_reloc (abfd, reloc_entry, s reloc_howto_type *howto = reloc_entry->howto; int make_absolute = 0; - if (output_bfd != (bfd *) NULL) + if (output_bfd != NULL) { /* Partial linking -- do nothing. */ reloc_entry->address += input_section->output_offset; @@ -283,10 +61,10 @@ bfd_elf_d30v_reloc (abfd, reloc_entry, s if (r != bfd_reloc_continue) return r; - /* a hacked-up version of bfd_perform_reloc() follows */ + /* A hacked-up version of bfd_perform_reloc() follows. */ if (bfd_is_und_section (symbol->section) && (symbol->flags & BSF_WEAK) == 0 - && output_bfd == (bfd *) NULL) + && output_bfd == NULL) flag = bfd_reloc_undefined; /* Is the address of the relocation really within the section? */ @@ -313,10 +91,10 @@ bfd_elf_d30v_reloc (abfd, reloc_entry, s /* Here the variable relocation holds the final address of the symbol we are relocating against, plus any addend. */ - if (howto->pc_relative) { - tmp_addr = input_section->output_section->vma + input_section->output_offset + tmp_addr = input_section->output_section->vma + + input_section->output_offset + reloc_entry->address; relocation -= tmp_addr; } @@ -324,7 +102,7 @@ bfd_elf_d30v_reloc (abfd, reloc_entry, s in1 = bfd_get_32 (abfd, (bfd_byte *) data + addr); in2 = bfd_get_32 (abfd, (bfd_byte *) data + addr + 4); - /* extract the addend */ + /* Extract the addend. */ num = ((in2 & 0x3FFFF) | ((in2 & 0xFF00000) >> 2) | ((in1 & 0x3F) << 26)); @@ -345,12 +123,12 @@ bfd_elf_d30v_reloc (abfd, reloc_entry, s } } - in1 |= (relocation >> 26) & 0x3F; /* top 6 bits */ - in2 |= ((relocation & 0x03FC0000) << 2); /* next 8 bits */ - in2 |= relocation & 0x0003FFFF; /* bottom 18 bits */ + in1 |= (relocation >> 26) & 0x3F; /* Top 6 bits. */ + in2 |= ((relocation & 0x03FC0000) << 2); /* Next 8 bits. */ + in2 |= relocation & 0x0003FFFF; /* Bottom 18 bits. */ - /* change a PC-relative instruction to its absolute equivalent */ - /* with this simple hack */ + /* Change a PC-relative instruction to its + absolute equivalent with this simple hack. */ if (make_absolute) in1 |= 0x00100000; @@ -361,14 +139,13 @@ bfd_elf_d30v_reloc (abfd, reloc_entry, s } static bfd_reloc_status_type -bfd_elf_d30v_reloc_21 (abfd, reloc_entry, symbol, data, input_section, output_bfd, error_message) - bfd *abfd; - arelent *reloc_entry; - asymbol *symbol; - PTR data; - asection *input_section; - bfd *output_bfd; - char **error_message; +bfd_elf_d30v_reloc_21 (bfd *abfd, + arelent *reloc_entry, + asymbol *symbol, + void * data, + asection *input_section, + bfd *output_bfd, + char **error_message) { bfd_vma relocation; bfd_vma in1, num; @@ -380,7 +157,7 @@ bfd_elf_d30v_reloc_21 (abfd, reloc_entry reloc_howto_type *howto = reloc_entry->howto; int mask, max; - if (output_bfd != (bfd *) NULL) + if (output_bfd != NULL) { /* Partial linking -- do nothing. */ reloc_entry->address += input_section->output_offset; @@ -392,10 +169,10 @@ bfd_elf_d30v_reloc_21 (abfd, reloc_entry if (r != bfd_reloc_continue) return r; - /* a hacked-up version of bfd_perform_reloc() follows */ - if (bfd_is_und_section (symbol->section) + /* A hacked-up version of bfd_perform_reloc() follows. */ + if (bfd_is_und_section (symbol->section) && (symbol->flags & BSF_WEAK) == 0 - && output_bfd == (bfd *) NULL) + && output_bfd == NULL) flag = bfd_reloc_undefined; /* Is the address of the relocation really within the section? */ @@ -438,30 +215,30 @@ bfd_elf_d30v_reloc_21 (abfd, reloc_entry mask <<= 12; max = (1 << (howto->bitsize + 2)) - 1; - /* extract the addend */ - num = in1 & mask; /* 18 bits */ + /* Extract the addend. */ + num = in1 & mask; /* 18 bits. */ if (howto->bitsize == 6) num >>= 12; - num <<= 3; /* shift left 3 */ - in1 &= ~mask; /* mask out addend */ + num <<= 3; /* shift left 3. */ + in1 &= ~mask; /* Mask out addend. */ relocation += num; - if (howto->type == R_D30V_21_PCREL_R || howto->type == R_D30V_15_PCREL_R || - howto->type == R_D30V_9_PCREL_R ) - { - relocation += 4; - } + if (howto->type == R_D30V_21_PCREL_R + || howto->type == R_D30V_15_PCREL_R + || howto->type == R_D30V_9_PCREL_R) + relocation += 4; - if ((int)relocation < 0 ) + if ((int) relocation < 0) { - if (~(int)relocation > max) + if (~ (int) relocation > max) flag = bfd_reloc_overflow; } else { - if ((int)relocation > max) + if ((int) relocation > max) flag = bfd_reloc_overflow; } + relocation >>= 3; if (howto->bitsize == 6) in1 |= ((relocation & (mask >> 12)) << 12); @@ -473,6 +250,205 @@ bfd_elf_d30v_reloc_21 (abfd, reloc_entry return flag; } +static reloc_howto_type elf_d30v_howto_table[] = +{ + /* This reloc does nothing. */ + HOWTO (R_D30V_NONE, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 32, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_bitfield, /* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_D30V_NONE", /* Name. */ + FALSE, /* Partial_inplace. */ + 0, /* Src_mask. */ + 0, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* A 6 bit absolute relocation. */ + HOWTO (R_D30V_6, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 6, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_bitfield, /* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_D30V_6", /* Name. */ + FALSE, /* Partial_inplace. */ + 0x3f, /* Src_mask. */ + 0x3f, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* A relative 9 bit relocation, right shifted by 3. */ + HOWTO (R_D30V_9_PCREL, /* Type. */ + 3, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 6, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_signed, /* Complain_on_overflow. */ + bfd_elf_d30v_reloc_21, /* Special_function. */ + "R_D30V_9_PCREL", /* Name. */ + FALSE, /* Partial_inplace. */ + 0x3f, /* Src_mask. */ + 0x3f, /* Dst_mask. */ + TRUE), /* PCrel_offset. */ + + /* A relative 9 bit relocation, right shifted by 3. */ + HOWTO (R_D30V_9_PCREL_R, /* Type. */ + 3, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 6, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_signed, /* Complain_on_overflow. */ + bfd_elf_d30v_reloc_21, /* Special_function. */ + "R_D30V_9_PCREL_R", /* Name. */ + FALSE, /* Partial_inplace. */ + 0x3f, /* Src_mask. */ + 0x3f, /* Dst_mask. */ + TRUE), /* PCrel_offset. */ + + /* An absolute 15 bit relocation, right shifted by 3. */ + HOWTO (R_D30V_15, /* Type. */ + 3, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 12, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_signed, /* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_D30V_15", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xfff, /* Src_mask. */ + 0xfff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* A relative 15 bit relocation, right shifted by 3. */ + HOWTO (R_D30V_15_PCREL, /* Type. */ + 3, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 12, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_signed, /* Complain_on_overflow. */ + bfd_elf_d30v_reloc_21, /* Special_function. */ + "R_D30V_15_PCREL", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xfff, /* Src_mask. */ + 0xfff, /* Dst_mask. */ + TRUE), /* PCrel_offset. */ + + /* A relative 15 bit relocation, right shifted by 3. */ + HOWTO (R_D30V_15_PCREL_R, /* Type. */ + 3, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 12, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_signed, /* Complain_on_overflow. */ + bfd_elf_d30v_reloc_21, /* Special_function. */ + "R_D30V_15_PCREL_R", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xfff, /* Src_mask. */ + 0xfff, /* Dst_mask. */ + TRUE), /* PCrel_offset. */ + + /* An absolute 21 bit relocation, right shifted by 3. */ + HOWTO (R_D30V_21, /* Type. */ + 3, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 18, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_signed, /* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_D30V_21", /* Name. */ + FALSE, /* Partial_inplace. */ + 0x3ffff, /* Src_mask. */ + 0x3ffff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* A relative 21 bit relocation, right shifted by 3. */ + HOWTO (R_D30V_21_PCREL, /* Type. */ + 3, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 18, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_signed, /* Complain_on_overflow. */ + bfd_elf_d30v_reloc_21, /* Special_function. */ + "R_D30V_21_PCREL", /* Name. */ + FALSE, /* Partial_inplace. */ + 0x3ffff, /* Src_mask. */ + 0x3ffff, /* Dst_mask. */ + TRUE), /* PCrel_offset. */ + + /* A relative 21 bit relocation, right shifted by 3, in the Right container. */ + HOWTO (R_D30V_21_PCREL_R, /* Type. */ + 3, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 18, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_signed, /* Complain_on_overflow. */ + bfd_elf_d30v_reloc_21, /* Special_function. */ + "R_D30V_21_PCREL_R", /* Name. */ + FALSE, /* Partial_inplace. */ + 0x3ffff, /* Src_mask. */ + 0x3ffff, /* Dst_mask. */ + TRUE), /* PCrel_offset. */ + + /* A D30V 32 bit absolute relocation. */ + HOWTO (R_D30V_32, /* Type. */ + 0, /* Rightshift. */ + 4, /* Size (0 = byte, 1 = short, 2 = long). */ + 32, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_bitfield, /* Complain_on_overflow. */ + bfd_elf_d30v_reloc, /* Special_function. */ + "R_D30V_32", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xffffffff, /* Src_mask. */ + 0xffffffff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* A relative 32 bit relocation. */ + HOWTO (R_D30V_32_PCREL, /* Type. */ + 0, /* Rightshift. */ + 4, /* Size (0 = byte, 1 = short, 2 = long). */ + 32, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_signed, /* Complain_on_overflow. */ + bfd_elf_d30v_reloc, /* Special_function. */ + "R_D30V_32_PCREL", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xffffffff, /* Src_mask. */ + 0xffffffff, /* Dst_mask. */ + TRUE), /* PCrel_offset. */ + + /* A regular 32 bit absolute relocation. */ + HOWTO (R_D30V_32_NORMAL, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 32, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_bitfield, /* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_D30V_32_NORMAL", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xffffffff, /* Src_mask. */ + 0xffffffff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + +}; + /* Map BFD reloc types to D30V ELF reloc types. */ struct d30v_reloc_map @@ -499,9 +475,8 @@ static const struct d30v_reloc_map d30v_ }; static reloc_howto_type * -bfd_elf32_bfd_reloc_type_lookup (abfd, code) - bfd *abfd ATTRIBUTE_UNUSED; - bfd_reloc_code_real_type code; +bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) { unsigned int i; @@ -519,10 +494,9 @@ bfd_elf32_bfd_reloc_type_lookup (abfd, c /* Set the howto pointer for an D30V ELF reloc (type REL). */ static void -d30v_info_to_howto_rel (abfd, cache_ptr, dst) - bfd *abfd ATTRIBUTE_UNUSED; - arelent *cache_ptr; - Elf_Internal_Rela *dst; +d30v_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED, + arelent *cache_ptr, + Elf_Internal_Rela *dst) { unsigned int r_type; @@ -534,10 +508,9 @@ d30v_info_to_howto_rel (abfd, cache_ptr, /* Set the howto pointer for an D30V ELF reloc (type RELA). */ static void -d30v_info_to_howto_rela (abfd, cache_ptr, dst) - bfd *abfd ATTRIBUTE_UNUSED; - arelent *cache_ptr; - Elf_Internal_Rela *dst; +d30v_info_to_howto_rela (bfd *abfd ATTRIBUTE_UNUSED, + arelent *cache_ptr, + Elf_Internal_Rela *dst) { unsigned int r_type; diff -uprN binutils-2.16.91.0.1/bfd/elf32-dlx.c binutils-2.16.91.0.2/bfd/elf32-dlx.c --- binutils-2.16.91.0.1/bfd/elf32-dlx.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-dlx.c 2005-07-20 12:27:27.134219258 -0700 @@ -15,7 +15,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "bfd.h" #include "sysdep.h" @@ -23,27 +24,6 @@ #include "elf-bfd.h" #include "elf/dlx.h" -int set_dlx_skip_hi16_flag PARAMS ((int)); - -static bfd_boolean elf32_dlx_check_relocs - PARAMS ((bfd *, struct bfd_link_info *, asection *, - const Elf_Internal_Rela *)); -static void elf32_dlx_info_to_howto - PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); -static void elf32_dlx_info_to_howto_rel - PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); -static bfd_reloc_status_type elf32_dlx_relocate16 - PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); -static bfd_reloc_status_type elf32_dlx_relocate26 - PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); -static reloc_howto_type *elf32_dlx_reloc_type_lookup - PARAMS ((bfd *, bfd_reloc_code_real_type)); -static bfd_reloc_status_type _bfd_dlx_elf_hi16_reloc - PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); -static reloc_howto_type * dlx_rtype_to_howto - PARAMS ((unsigned int)); - - #define USE_REL 1 #define bfd_elf32_bfd_reloc_type_lookup elf32_dlx_reloc_type_lookup @@ -51,164 +31,6 @@ static reloc_howto_type * dlx_rtype_to_h #define elf_info_to_howto_rel elf32_dlx_info_to_howto_rel #define elf_backend_check_relocs elf32_dlx_check_relocs -static reloc_howto_type dlx_elf_howto_table[]= - { - /* No relocation. */ - HOWTO (R_DLX_NONE, /* type */ - 0, /* rightshift */ - 0, /* size (0 = byte, 1 = short, 2 = long) */ - 0, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont,/* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_DLX_NONE", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* 8 bit relocation. */ - HOWTO (R_DLX_RELOC_8, /* type */ - 0, /* rightshift */ - 0, /* size (0 = byte, 1 = short, 2 = long) */ - 8, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont,/* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_DLX_RELOC_8", /* name */ - TRUE, /* partial_inplace */ - 0xff, /* src_mask */ - 0xff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* 16 bit relocation. */ - HOWTO (R_DLX_RELOC_16, /* type */ - 0, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont,/* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_DLX_RELOC_16", /* name */ - TRUE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* 32 bit relocation. */ - HOWTO (R_DLX_RELOC_32, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont,/* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_DLX_RELOC_32", /* name */ - TRUE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* GNU extension to record C++ vtable hierarchy */ - HOWTO (R_DLX_GNU_VTINHERIT, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 0, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont,/* complain_on_overflow */ - NULL, /* special_function */ - "R_DLX_GNU_VTINHERIT", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* GNU extension to record C++ vtable member usage */ - HOWTO (R_DLX_GNU_VTENTRY, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 0, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont,/* complain_on_overflow */ - _bfd_elf_rel_vtable_reloc_fn,/* special_function */ - "R_DLX_GNU_VTENTRY", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE) /* pcrel_offset */ - }; - -/* 16 bit offset for pc-relative branches. */ -static reloc_howto_type elf_dlx_gnu_rel16_s2 = -HOWTO (R_DLX_RELOC_16_PCREL, /* type */ - 0, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - elf32_dlx_relocate16, /* special_function */ - "R_DLX_RELOC_16_PCREL",/* name */ - TRUE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xffff, /* dst_mask */ - TRUE); /* pcrel_offset */ - -/* 26 bit offset for pc-relative branches. */ -static reloc_howto_type elf_dlx_gnu_rel26_s2 = -HOWTO (R_DLX_RELOC_26_PCREL, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 26, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont,/* complain_on_overflow */ - elf32_dlx_relocate26, /* special_function */ - "R_DLX_RELOC_26_PCREL",/* name */ - TRUE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xffff, /* dst_mask */ - TRUE); /* pcrel_offset */ - -/* High 16 bits of symbol value. */ -static reloc_howto_type elf_dlx_reloc_16_hi = -HOWTO (R_DLX_RELOC_16_HI, /* type */ - 16, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - _bfd_dlx_elf_hi16_reloc,/* special_function */ - "R_DLX_RELOC_16_HI", /* name */ - TRUE, /* partial_inplace */ - 0xFFFF, /* src_mask */ - 0xffff, /* dst_mask */ - FALSE); /* pcrel_offset */ - - /* Low 16 bits of symbol value. */ -static reloc_howto_type elf_dlx_reloc_16_lo = -HOWTO (R_DLX_RELOC_16_LO, /* type */ - 0, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont,/* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_DLX_RELOC_16_LO", /* name */ - TRUE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xffff, /* dst_mask */ - FALSE); /* pcrel_offset */ - - /* The gas default behavior is not to preform the %hi modifier so that the GNU assembler can have the lower 16 bits offset placed in the insn, BUT we do like the gas to indicate it is %hi reloc type so when we in the link @@ -217,24 +39,23 @@ HOWTO (R_DLX_RELOC_16_LO, /* type */ static int skip_dlx_elf_hi16_reloc = 0; +extern int set_dlx_skip_hi16_flag (int); + int -set_dlx_skip_hi16_flag (flag) - int flag; +set_dlx_skip_hi16_flag (int flag) { skip_dlx_elf_hi16_reloc = flag; return flag; } static bfd_reloc_status_type -_bfd_dlx_elf_hi16_reloc (abfd, reloc_entry, symbol, data, - input_section, output_bfd, error_message) - bfd *abfd; - arelent *reloc_entry; - asymbol *symbol; - PTR data; - asection *input_section; - bfd *output_bfd; - char **error_message; +_bfd_dlx_elf_hi16_reloc (bfd *abfd, + arelent *reloc_entry, + asymbol *symbol, + void * data, + asection *input_section, + bfd *output_bfd, + char **error_message) { bfd_reloc_status_type ret; bfd_vma relocation; @@ -288,15 +109,13 @@ _bfd_dlx_elf_hi16_reloc (abfd, reloc_ent relocatable output against an external symbol. */ static bfd_reloc_status_type -elf32_dlx_relocate16 (abfd, reloc_entry, symbol, data, - input_section, output_bfd, error_message) - bfd *abfd; - arelent *reloc_entry; - asymbol *symbol; - PTR data; - asection *input_section; - bfd *output_bfd; - char **error_message ATTRIBUTE_UNUSED; +elf32_dlx_relocate16 (bfd *abfd, + arelent *reloc_entry, + asymbol *symbol, + void * data, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) { unsigned long insn, vallo, allignment; int val; @@ -310,12 +129,12 @@ elf32_dlx_relocate16 (abfd, reloc_entry return bfd_elf_generic_reloc (abfd, reloc_entry, symbol, data, input_section, output_bfd, error_message); - /* Check undefined section and undefined symbols */ + /* Check undefined section and undefined symbols. */ if (bfd_is_und_section (symbol->section) && output_bfd == (bfd *) NULL) return bfd_reloc_undefined; - /* Can not support a long jump to sections other then .text */ + /* Can not support a long jump to sections other then .text. */ if (strcmp (input_section->name, symbol->section->output_section->name) != 0) { fprintf (stderr, @@ -353,15 +172,13 @@ elf32_dlx_relocate16 (abfd, reloc_entry } static bfd_reloc_status_type -elf32_dlx_relocate26 (abfd, reloc_entry, symbol, data, - input_section, output_bfd, error_message) - bfd *abfd; - arelent *reloc_entry; - asymbol *symbol; - PTR data; - asection *input_section; - bfd *output_bfd; - char **error_message ATTRIBUTE_UNUSED; +elf32_dlx_relocate26 (bfd *abfd, + arelent *reloc_entry, + asymbol *symbol, + void * data, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) { unsigned long insn, vallo, allignment; int val; @@ -416,6 +233,163 @@ elf32_dlx_relocate26 (abfd, reloc_entry return bfd_reloc_ok; } +static reloc_howto_type dlx_elf_howto_table[]= +{ + /* No relocation. */ + HOWTO (R_DLX_NONE, /* Type. */ + 0, /* Rightshift. */ + 0, /* size (0 = byte, 1 = short, 2 = long). */ + 0, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont,/* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_DLX_NONE", /* Name. */ + FALSE, /* Partial_inplace. */ + 0, /* Src_mask. */ + 0, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* 8 bit relocation. */ + HOWTO (R_DLX_RELOC_8, /* Type. */ + 0, /* Rightshift. */ + 0, /* Size (0 = byte, 1 = short, 2 = long). */ + 8, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont,/* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_DLX_RELOC_8", /* Name. */ + TRUE, /* Partial_inplace. */ + 0xff, /* Src_mask. */ + 0xff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* 16 bit relocation. */ + HOWTO (R_DLX_RELOC_16, /* Type. */ + 0, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont,/* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_DLX_RELOC_16", /* Name. */ + TRUE, /* Partial_inplace. */ + 0xffff, /* Src_mask. */ + 0xffff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* 32 bit relocation. */ + HOWTO (R_DLX_RELOC_32, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 32, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont,/* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_DLX_RELOC_32", /* Name. */ + TRUE, /* Partial_inplace. */ + 0xffffffff, /* Src_mask. */ + 0xffffffff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* GNU extension to record C++ vtable hierarchy. */ + HOWTO (R_DLX_GNU_VTINHERIT, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 0, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont,/* Complain_on_overflow. */ + NULL, /* Special_function. */ + "R_DLX_GNU_VTINHERIT", /* Name. */ + FALSE, /* Partial_inplace. */ + 0, /* Src_mask. */ + 0, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* GNU extension to record C++ vtable member usage. */ + HOWTO (R_DLX_GNU_VTENTRY, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 0, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont,/* Complain_on_overflow. */ + _bfd_elf_rel_vtable_reloc_fn,/* Special_function. */ + "R_DLX_GNU_VTENTRY", /* Name. */ + FALSE, /* Partial_inplace. */ + 0, /* Src_mask. */ + 0, /* Dst_mask. */ + FALSE) /* PCrel_offset. */ +}; + +/* 16 bit offset for pc-relative branches. */ +static reloc_howto_type elf_dlx_gnu_rel16_s2 = + HOWTO (R_DLX_RELOC_16_PCREL, /* Type. */ + 0, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_signed, /* Complain_on_overflow. */ + elf32_dlx_relocate16, /* Special_function. */ + "R_DLX_RELOC_16_PCREL",/* Name. */ + TRUE, /* Partial_inplace. */ + 0xffff, /* Src_mask. */ + 0xffff, /* Dst_mask. */ + TRUE); /* PCrel_offset. */ + +/* 26 bit offset for pc-relative branches. */ +static reloc_howto_type elf_dlx_gnu_rel26_s2 = + HOWTO (R_DLX_RELOC_26_PCREL, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 26, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont,/* Complain_on_overflow. */ + elf32_dlx_relocate26, /* Special_function. */ + "R_DLX_RELOC_26_PCREL",/* Name. */ + TRUE, /* Partial_inplace. */ + 0xffff, /* Src_mask. */ + 0xffff, /* Dst_mask. */ + TRUE); /* PCrel_offset. */ + +/* High 16 bits of symbol value. */ +static reloc_howto_type elf_dlx_reloc_16_hi = + HOWTO (R_DLX_RELOC_16_HI, /* Type. */ + 16, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 32, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont,/* Complain_on_overflow. */ + _bfd_dlx_elf_hi16_reloc,/* Special_function. */ + "R_DLX_RELOC_16_HI", /* Name. */ + TRUE, /* Partial_inplace. */ + 0xFFFF, /* Src_mask. */ + 0xffff, /* Dst_mask. */ + FALSE); /* PCrel_offset. */ + + /* Low 16 bits of symbol value. */ +static reloc_howto_type elf_dlx_reloc_16_lo = + HOWTO (R_DLX_RELOC_16_LO, /* Type. */ + 0, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont,/* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_DLX_RELOC_16_LO", /* Name. */ + TRUE, /* Partial_inplace. */ + 0xffff, /* Src_mask. */ + 0xffff, /* Dst_mask. */ + FALSE); /* PCrel_offset. */ + /* A mapping from BFD reloc types to DLX ELF reloc types. Stolen from elf32-mips.c. @@ -431,27 +405,25 @@ struct elf_reloc_map }; static const struct elf_reloc_map dlx_reloc_map[] = - { - { BFD_RELOC_NONE, R_DLX_NONE }, - { BFD_RELOC_16, R_DLX_RELOC_16 }, - { BFD_RELOC_32, R_DLX_RELOC_32 }, - { BFD_RELOC_DLX_HI16_S, R_DLX_RELOC_16_HI }, - { BFD_RELOC_DLX_LO16, R_DLX_RELOC_16_LO }, - { BFD_RELOC_VTABLE_INHERIT, R_DLX_GNU_VTINHERIT }, - { BFD_RELOC_VTABLE_ENTRY, R_DLX_GNU_VTENTRY } - }; - +{ + { BFD_RELOC_NONE, R_DLX_NONE }, + { BFD_RELOC_16, R_DLX_RELOC_16 }, + { BFD_RELOC_32, R_DLX_RELOC_32 }, + { BFD_RELOC_DLX_HI16_S, R_DLX_RELOC_16_HI }, + { BFD_RELOC_DLX_LO16, R_DLX_RELOC_16_LO }, + { BFD_RELOC_VTABLE_INHERIT, R_DLX_GNU_VTINHERIT }, + { BFD_RELOC_VTABLE_ENTRY, R_DLX_GNU_VTENTRY } +}; /* Look through the relocs for a section during the first phase. Since we don't do .gots or .plts, we just need to consider the virtual table relocs for gc. */ static bfd_boolean -elf32_dlx_check_relocs (abfd, info, sec, relocs) - bfd *abfd; - struct bfd_link_info *info; - asection *sec; - const Elf_Internal_Rela *relocs; +elf32_dlx_check_relocs (bfd *abfd, + struct bfd_link_info *info, + asection *sec, + const Elf_Internal_Rela *relocs) { Elf_Internal_Shdr *symtab_hdr; struct elf_link_hash_entry **sym_hashes, **sym_hashes_end; @@ -508,9 +480,8 @@ elf32_dlx_check_relocs (abfd, info, sec, /* Given a BFD reloc type, return a howto structure. */ static reloc_howto_type * -elf32_dlx_reloc_type_lookup (abfd, code) - bfd *abfd ATTRIBUTE_UNUSED; - bfd_reloc_code_real_type code; +elf32_dlx_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) { unsigned int i; @@ -535,8 +506,7 @@ elf32_dlx_reloc_type_lookup (abfd, code) } static reloc_howto_type * -dlx_rtype_to_howto (r_type) - unsigned int r_type; +dlx_rtype_to_howto (unsigned int r_type) { switch (r_type) { @@ -561,19 +531,17 @@ dlx_rtype_to_howto (r_type) } static void -elf32_dlx_info_to_howto (abfd, cache_ptr, dst) - bfd * abfd ATTRIBUTE_UNUSED; - arelent * cache_ptr ATTRIBUTE_UNUSED; - Elf_Internal_Rela * dst ATTRIBUTE_UNUSED; +elf32_dlx_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, + arelent * cache_ptr ATTRIBUTE_UNUSED, + Elf_Internal_Rela * dst ATTRIBUTE_UNUSED) { abort (); } static void -elf32_dlx_info_to_howto_rel (abfd, cache_ptr, dst) - bfd *abfd ATTRIBUTE_UNUSED; - arelent *cache_ptr; - Elf_Internal_Rela *dst; +elf32_dlx_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED, + arelent *cache_ptr, + Elf_Internal_Rela *dst) { unsigned int r_type; diff -uprN binutils-2.16.91.0.1/bfd/elf32-hppa.c binutils-2.16.91.0.2/bfd/elf32-hppa.c --- binutils-2.16.91.0.1/bfd/elf32-hppa.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-hppa.c 2005-07-20 12:27:27.154215960 -0700 @@ -180,7 +180,7 @@ enum elf32_hppa_stub_type { struct elf32_hppa_stub_hash_entry { /* Base hash table entry structure. */ - struct bfd_hash_entry root; + struct bfd_hash_entry bh_root; /* The stub section. */ asection *stub_sec; @@ -196,7 +196,7 @@ struct elf32_hppa_stub_hash_entry { enum elf32_hppa_stub_type stub_type; /* The symbol table entry, if any, that this was derived from. */ - struct elf32_hppa_link_hash_entry *h; + struct elf32_hppa_link_hash_entry *hh; /* Where this stub is being called from, or, in the case of combined stub sections, the first input section in the group. */ @@ -205,18 +205,18 @@ struct elf32_hppa_stub_hash_entry { struct elf32_hppa_link_hash_entry { - struct elf_link_hash_entry elf; + struct elf_link_hash_entry eh; /* A pointer to the most recently used stub hash entry against this symbol. */ - struct elf32_hppa_stub_hash_entry *stub_cache; + struct elf32_hppa_stub_hash_entry *hsh_cache; /* Used to count relocations for delayed sizing of relocation sections. */ struct elf32_hppa_dyn_reloc_entry { /* Next relocation in the chain. */ - struct elf32_hppa_dyn_reloc_entry *next; + struct elf32_hppa_dyn_reloc_entry *hdh_next; /* The input section of the reloc. */ asection *sec; @@ -237,10 +237,10 @@ struct elf32_hppa_link_hash_entry { struct elf32_hppa_link_hash_table { /* The main hash table. */ - struct elf_link_hash_table elf; + struct elf_link_hash_table etab; /* The stub hash table. */ - struct bfd_hash_table stub_hash_table; + struct bfd_hash_table bstab; /* Linker stub bfd. */ bfd *stub_bfd; @@ -340,7 +340,7 @@ stub_hash_newfunc (struct bfd_hash_entry hsh->target_value = 0; hsh->target_section = NULL; hsh->stub_type = hppa_stub_long_branch; - hsh->h = NULL; + hsh->hh = NULL; hsh->id_sec = NULL; } @@ -372,7 +372,7 @@ hppa_link_hash_newfunc (struct bfd_hash_ /* Initialize the local fields. */ hh = hppa_elf_hash_entry (entry); - hh->stub_cache = NULL; + hh->hsh_cache = NULL; hh->dyn_relocs = NULL; hh->plabel = 0; } @@ -394,14 +394,14 @@ elf32_hppa_link_hash_table_create (bfd * if (htab == NULL) return NULL; - if (!_bfd_elf_link_hash_table_init (&htab->elf, abfd, hppa_link_hash_newfunc)) + if (!_bfd_elf_link_hash_table_init (&htab->etab, abfd, hppa_link_hash_newfunc)) { free (htab); return NULL; } /* Init the stub hash table too. */ - if (!bfd_hash_table_init (&htab->stub_hash_table, stub_hash_newfunc)) + if (!bfd_hash_table_init (&htab->bstab, stub_hash_newfunc)) return NULL; htab->stub_bfd = NULL; @@ -423,7 +423,7 @@ elf32_hppa_link_hash_table_create (bfd * htab->need_plt_stub = 0; htab->sym_sec.abfd = NULL; - return &htab->elf.root; + return &htab->etab.root; } /* Free the derived linker hash table. */ @@ -434,7 +434,7 @@ elf32_hppa_link_hash_table_free (struct struct elf32_hppa_link_hash_table *htab = (struct elf32_hppa_link_hash_table *) btab; - bfd_hash_table_free (&htab->stub_hash_table); + bfd_hash_table_free (&htab->bstab); _bfd_generic_link_hash_table_free (btab); } @@ -451,13 +451,13 @@ hppa_stub_name (const asection *input_se if (hh) { - len = 8 + 1 + strlen (hh->elf.root.root.string) + 1 + 8 + 1; + len = 8 + 1 + strlen (hh->eh.root.root.string) + 1 + 8 + 1; stub_name = bfd_malloc (len); if (stub_name != NULL) { sprintf (stub_name, "%08x_%s+%x", input_section->id & 0xffffffff, - hh->elf.root.root.string, + hh->eh.root.root.string, (int) rela->r_addend & 0xffffffff); } } @@ -487,7 +487,7 @@ hppa_get_stub_entry (const asection *inp const Elf_Internal_Rela *rela, struct elf32_hppa_link_hash_table *htab) { - struct elf32_hppa_stub_hash_entry *stub_entry; + struct elf32_hppa_stub_hash_entry *hsh_entry; const asection *id_sec; /* If this input section is part of a group of sections sharing one @@ -497,11 +497,11 @@ hppa_get_stub_entry (const asection *inp distinguish between them. */ id_sec = htab->stub_group[input_section->id].link_sec; - if (hh != NULL && hh->stub_cache != NULL - && hh->stub_cache->h == hh - && hh->stub_cache->id_sec == id_sec) + if (hh != NULL && hh->hsh_cache != NULL + && hh->hsh_cache->hh == hh + && hh->hsh_cache->id_sec == id_sec) { - stub_entry = hh->stub_cache; + hsh_entry = hh->hsh_cache; } else { @@ -511,15 +511,15 @@ hppa_get_stub_entry (const asection *inp if (stub_name == NULL) return NULL; - stub_entry = hppa_stub_hash_lookup (&htab->stub_hash_table, + hsh_entry = hppa_stub_hash_lookup (&htab->bstab, stub_name, FALSE, FALSE); if (hh != NULL) - hh->stub_cache = stub_entry; + hh->hsh_cache = hsh_entry; free (stub_name); } - return stub_entry; + return hsh_entry; } /* Add a new stub entry to the stub hash. Not all fields of the new @@ -562,7 +562,7 @@ hppa_add_stub (const char *stub_name, } /* Enter this entry into the linker stub hash table. */ - hsh = hppa_stub_hash_lookup (&htab->stub_hash_table, stub_name, + hsh = hppa_stub_hash_lookup (&htab->bstab, stub_name, TRUE, FALSE); if (hsh == NULL) { @@ -593,12 +593,12 @@ hppa_type_of_stub (asection *input_sec, unsigned int r_type; if (hh != NULL - && hh->elf.plt.offset != (bfd_vma) -1 - && hh->elf.dynindx != -1 + && hh->eh.plt.offset != (bfd_vma) -1 + && hh->eh.dynindx != -1 && !hh->plabel && (info->shared - || !hh->elf.def_regular - || hh->elf.root.type == bfd_link_hash_defweak)) + || !hh->eh.def_regular + || hh->eh.root.type == bfd_link_hash_defweak)) { /* We need an import stub. Decide between hppa_stub_import and hppa_stub_import_shared later. */ @@ -750,7 +750,7 @@ hppa_build_one_stub (struct bfd_hash_ent case hppa_stub_import: case hppa_stub_import_shared: - off = hsh->h->elf.plt.offset; + off = hsh->hh->eh.plt.offset; if (off >= (bfd_vma) -2) abort (); @@ -823,7 +823,7 @@ hppa_build_one_stub (struct bfd_hash_ent hsh->target_section->owner, stub_sec, (long) hsh->stub_offset, - hsh->root.string); + hsh->bh_root.string); bfd_set_error (bfd_error_bad_value); return FALSE; } @@ -842,8 +842,8 @@ hppa_build_one_stub (struct bfd_hash_ent bfd_put_32 (stub_bfd, (bfd_vma) BE_SR0_RP, loc + 20); /* Point the function symbol at the stub. */ - hsh->h->elf.root.u.def.section = stub_sec; - hsh->h->elf.root.u.def.value = stub_sec->size; + hsh->hh->eh.root.u.def.section = stub_sec; + hsh->hh->eh.root.u.def.value = stub_sec->size; size = 24; break; @@ -1029,18 +1029,18 @@ elf32_hppa_copy_indirect_symbol (const s { struct elf32_hppa_dyn_reloc_entry *hdh_q; - for (hdh_q = hh_dir->dyn_relocs; hdh_q != NULL; hdh_q = hdh_q->next) + for (hdh_q = hh_dir->dyn_relocs; hdh_q != NULL; hdh_q = hdh_q->hdh_next) if (hdh_q->sec == hdh_p->sec) { #if RELATIVE_DYNRELOCS hdh_q->relative_count += hdh_p->relative_count; #endif hdh_q->count += hdh_p->count; - *hdh_pp = hdh_p->next; + *hdh_pp = hdh_p->hdh_next; break; } if (hdh_q == NULL) - hdh_pp = &hdh_p->next; + hdh_pp = &hdh_p->hdh_next; } *hdh_pp = hh_dir->dyn_relocs; } @@ -1114,9 +1114,9 @@ elf32_hppa_check_relocs (bfd *abfd, else { hh = hppa_elf_hash_entry (eh_syms[r_symndx - symtab_hdr->sh_info]); - while (hh->elf.root.type == bfd_link_hash_indirect - || hh->elf.root.type == bfd_link_hash_warning) - hh = hppa_elf_hash_entry (hh->elf.root.u.i.link); + while (hh->eh.root.type == bfd_link_hash_indirect + || hh->eh.root.type == bfd_link_hash_warning) + hh = hppa_elf_hash_entry (hh->eh.root.u.i.link); } r_type = ELF32_R_TYPE (rela->r_info); @@ -1188,7 +1188,7 @@ elf32_hppa_check_relocs (bfd *abfd, where a symbol is forced local by versioning, or due to symbolic linking, and we lose the .plt entry. */ need_entry = NEED_PLT; - if (hh->elf.type == STT_PARISC_MILLI) + if (hh->eh.type == STT_PARISC_MILLI) need_entry = 0; } break; @@ -1231,14 +1231,14 @@ elf32_hppa_check_relocs (bfd *abfd, /* This relocation describes the C++ object vtable hierarchy. Reconstruct it for later use during GC. */ case R_PARISC_GNU_VTINHERIT: - if (!bfd_elf_gc_record_vtinherit (abfd, sec, &hh->elf, rela->r_offset)) + if (!bfd_elf_gc_record_vtinherit (abfd, sec, &hh->eh, rela->r_offset)) return FALSE; continue; /* This relocation describes which C++ vtable entries are actually used. Record for later use during GC. */ case R_PARISC_GNU_VTENTRY: - if (!bfd_elf_gc_record_vtentry (abfd, sec, &hh->elf, rela->r_addend)) + if (!bfd_elf_gc_record_vtentry (abfd, sec, &hh->eh, rela->r_addend)) return FALSE; continue; @@ -1253,15 +1253,15 @@ elf32_hppa_check_relocs (bfd *abfd, relocation for this entry. */ if (htab->sgot == NULL) { - if (htab->elf.dynobj == NULL) - htab->elf.dynobj = abfd; - if (!elf32_hppa_create_dynamic_sections (htab->elf.dynobj, info)) + if (htab->etab.dynobj == NULL) + htab->etab.dynobj = abfd; + if (!elf32_hppa_create_dynamic_sections (htab->etab.dynobj, info)) return FALSE; } if (hh != NULL) { - hh->elf.got.refcount += 1; + hh->eh.got.refcount += 1; } else { @@ -1301,8 +1301,8 @@ elf32_hppa_check_relocs (bfd *abfd, { if (hh != NULL) { - hh->elf.needs_plt = 1; - hh->elf.plt.refcount += 1; + hh->eh.needs_plt = 1; + hh->eh.plt.refcount += 1; /* If this .plt entry is for a plabel, mark it so that adjust_dynamic_symbol will keep the entry @@ -1342,7 +1342,7 @@ elf32_hppa_check_relocs (bfd *abfd, so that we generate copy relocs if it turns out to be dynamic. */ if (hh != NULL && !info->shared) - hh->elf.non_got_ref = 1; + hh->eh.non_got_ref = 1; /* If we are creating a shared library then we need to copy the reloc into the shared library. However, if we are @@ -1377,14 +1377,14 @@ elf32_hppa_check_relocs (bfd *abfd, && (IS_ABSOLUTE_RELOC (r_type) || (hh != NULL && (!info->symbolic - || hh->elf.root.type == bfd_link_hash_defweak - || !hh->elf.def_regular)))) + || hh->eh.root.type == bfd_link_hash_defweak + || !hh->eh.def_regular)))) || (ELIMINATE_COPY_RELOCS && !info->shared && (sec->flags & SEC_ALLOC) != 0 && hh != NULL - && (hh->elf.root.type == bfd_link_hash_defweak - || !hh->elf.def_regular))) + && (hh->eh.root.type == bfd_link_hash_defweak + || !hh->eh.def_regular))) { struct elf32_hppa_dyn_reloc_entry *hdh_p; struct elf32_hppa_dyn_reloc_entry **hdh_head; @@ -1409,10 +1409,10 @@ elf32_hppa_check_relocs (bfd *abfd, return FALSE; } - if (htab->elf.dynobj == NULL) - htab->elf.dynobj = abfd; + if (htab->etab.dynobj == NULL) + htab->etab.dynobj = abfd; - dynobj = htab->elf.dynobj; + dynobj = htab->etab.dynobj; sreloc = bfd_get_section_by_name (dynobj, name); if (sreloc == NULL) { @@ -1458,10 +1458,10 @@ elf32_hppa_check_relocs (bfd *abfd, hdh_p = *hdh_head; if (hdh_p == NULL || hdh_p->sec != sec) { - hdh_p = bfd_alloc (htab->elf.dynobj, sizeof *hdh_p); + hdh_p = bfd_alloc (htab->etab.dynobj, sizeof *hdh_p); if (hdh_p == NULL) return FALSE; - hdh_p->next = *hdh_head; + hdh_p->hdh_next = *hdh_head; *hdh_head = hdh_p; hdh_p->sec = sec; hdh_p->count = 0; @@ -1565,11 +1565,11 @@ elf32_hppa_gc_sweep_hook (bfd *abfd, eh = (struct elf_link_hash_entry *) eh->root.u.i.link; hh = hppa_elf_hash_entry (eh); - for (hdh_pp = &hh->dyn_relocs; (hdh_p = *hdh_pp) != NULL; hdh_pp = &hdh_p->next) + for (hdh_pp = &hh->dyn_relocs; (hdh_p = *hdh_pp) != NULL; hdh_pp = &hdh_p->hdh_next) if (hdh_p->sec == sec) { /* Everything must go for SEC. */ - *hdh_pp = hdh_p->next; + *hdh_pp = hdh_p->hdh_next; break; } } @@ -1791,7 +1791,7 @@ elf32_hppa_adjust_dynamic_symbol (struct struct elf32_hppa_dyn_reloc_entry *hdh_p; hh = hppa_elf_hash_entry (eh); - for (hdh_p = hh->dyn_relocs; hdh_p != NULL; hdh_p = hdh_p->next) + for (hdh_p = hh->dyn_relocs; hdh_p != NULL; hdh_p = hdh_p->hdh_next) { sec = hdh_p->sec->output_section; if (sec != NULL && (sec->flags & SEC_READONLY) != 0) @@ -1838,9 +1838,9 @@ elf32_hppa_adjust_dynamic_symbol (struct /* Apply the required alignment. */ sec = htab->sdynbss; sec->size = BFD_ALIGN (sec->size, (bfd_size_type) (1 << power_of_two)); - if (power_of_two > bfd_get_section_alignment (htab->elf.dynobj, sec)) + if (power_of_two > bfd_get_section_alignment (htab->etab.dynobj, sec)) { - if (! bfd_set_section_alignment (htab->elf.dynobj, sec, power_of_two)) + if (! bfd_set_section_alignment (htab->etab.dynobj, sec, power_of_two)) return FALSE; } @@ -1874,7 +1874,7 @@ allocate_plt_static (struct elf_link_has info = (struct bfd_link_info *) inf; hh = hppa_elf_hash_entry(eh); htab = hppa_link_hash_table (info); - if (htab->elf.dynamic_sections_created + if (htab->etab.dynamic_sections_created && eh->plt.refcount > 0) { /* Make sure this symbol is output as a dynamic symbol. @@ -1942,7 +1942,7 @@ allocate_dynrelocs (struct elf_link_hash htab = hppa_link_hash_table (info); hh = hppa_elf_hash_entry (eh); - if (htab->elf.dynamic_sections_created + if (htab->etab.dynamic_sections_created && eh->plt.offset != (bfd_vma) -1 && !hh->plabel && eh->plt.refcount > 0) @@ -1972,7 +1972,7 @@ allocate_dynrelocs (struct elf_link_hash sec = htab->sgot; eh->got.offset = sec->size; sec->size += GOT_ENTRY_SIZE; - if (htab->elf.dynamic_sections_created + if (htab->etab.dynamic_sections_created && (info->shared || (eh->dynindx != -1 && !eh->forced_local))) @@ -2003,9 +2003,9 @@ allocate_dynrelocs (struct elf_link_hash hdh_p->count -= hdh_p->relative_count; hdh_p->relative_count = 0; if (hdh_p->count == 0) - *hdh_pp = hdh_p->next; + *hdh_pp = hdh_p->hdh_next; else - hdh_pp = &hdh_p->next; + hdh_pp = &hdh_p->hdh_next; } } #endif @@ -2026,7 +2026,7 @@ allocate_dynrelocs (struct elf_link_hash && ((ELIMINATE_COPY_RELOCS && eh->def_dynamic && !eh->def_regular) - || (htab->elf.dynamic_sections_created + || (htab->etab.dynamic_sections_created && (eh->root.type == bfd_link_hash_undefweak || eh->root.type == bfd_link_hash_undefined)))) { @@ -2053,7 +2053,7 @@ allocate_dynrelocs (struct elf_link_hash } /* Finally, allocate space. */ - for (hdh_p = hh->dyn_relocs; hdh_p != NULL; hdh_p = hdh_p->next) + for (hdh_p = hh->dyn_relocs; hdh_p != NULL; hdh_p = hdh_p->hdh_next) { asection *sreloc = elf_section_data (hdh_p->sec)->sreloc; sreloc->size += hdh_p->count * sizeof (Elf32_External_Rela); @@ -2096,7 +2096,7 @@ readonly_dynrelocs (struct elf_link_hash eh = (struct elf_link_hash_entry *) eh->root.u.i.link; hh = hppa_elf_hash_entry (eh); - for (hdh_p = hh->dyn_relocs; hdh_p != NULL; hdh_p = hdh_p->next) + for (hdh_p = hh->dyn_relocs; hdh_p != NULL; hdh_p = hdh_p->hdh_next) { asection *sec = hdh_p->sec->output_section; @@ -2126,11 +2126,11 @@ elf32_hppa_size_dynamic_sections (bfd *o bfd_boolean relocs; htab = hppa_link_hash_table (info); - dynobj = htab->elf.dynobj; + dynobj = htab->etab.dynobj; if (dynobj == NULL) abort (); - if (htab->elf.dynamic_sections_created) + if (htab->etab.dynamic_sections_created) { /* Set the contents of the .interp section to the interpreter. */ if (info->executable) @@ -2143,7 +2143,7 @@ elf32_hppa_size_dynamic_sections (bfd *o } /* Force millicode symbols local. */ - elf_link_hash_traverse (&htab->elf, + elf_link_hash_traverse (&htab->etab, clobber_millicode_symbols, info); } @@ -2170,7 +2170,7 @@ elf32_hppa_size_dynamic_sections (bfd *o for (hdh_p = ((struct elf32_hppa_dyn_reloc_entry *) elf_section_data (sec)->local_dynrel); hdh_p != NULL; - hdh_p = hdh_p->next) + hdh_p = hdh_p->hdh_next) { if (!bfd_is_abs_section (hdh_p->sec) && bfd_is_abs_section (hdh_p->sec->output_section)) @@ -2214,7 +2214,7 @@ elf32_hppa_size_dynamic_sections (bfd *o local_plt = end_local_got; end_local_plt = local_plt + locsymcount; - if (! htab->elf.dynamic_sections_created) + if (! htab->etab.dynamic_sections_created) { /* Won't be used, but be safe. */ for (; local_plt < end_local_plt; ++local_plt) @@ -2242,11 +2242,11 @@ elf32_hppa_size_dynamic_sections (bfd *o /* Do all the .plt entries without relocs first. The dynamic linker uses the last .plt reloc to find the end of the .plt (and hence the start of the .got) for lazy linking. */ - elf_link_hash_traverse (&htab->elf, allocate_plt_static, info); + elf_link_hash_traverse (&htab->etab, allocate_plt_static, info); /* Allocate global sym .plt and .got entries, and space for global sym dynamic relocs. */ - elf_link_hash_traverse (&htab->elf, allocate_dynrelocs, info); + elf_link_hash_traverse (&htab->etab, allocate_dynrelocs, info); /* The check_relocs and adjust_dynamic_symbol entry points have determined the sizes of the various dynamic sections. Allocate @@ -2274,7 +2274,8 @@ elf32_hppa_size_dynamic_sections (bfd *o sec->size = (sec->size + sizeof (plt_stub) + mask) & ~mask; } } - else if (sec == htab->sgot) + else if (sec == htab->sgot + || sec == htab->sdynbss) ; else if (strncmp (bfd_get_section_name (dynobj, sec), ".rela", 5) == 0) { @@ -2311,14 +2312,17 @@ elf32_hppa_size_dynamic_sections (bfd *o continue; } + if ((sec->flags & SEC_HAS_CONTENTS) == 0) + continue; + /* Allocate memory for the section contents. Zero it, because we may not fill in all the reloc sections. */ sec->contents = bfd_zalloc (dynobj, sec->size); - if (sec->contents == NULL && sec->size != 0) + if (sec->contents == NULL) return FALSE; } - if (htab->elf.dynamic_sections_created) + if (htab->etab.dynamic_sections_created) { /* Like IA-64 and HPPA64, always create a DT_PLTGOT. It actually has nothing to do with the PLT, it is how we @@ -2359,7 +2363,7 @@ elf32_hppa_size_dynamic_sections (bfd *o /* If any dynamic relocs apply to a read-only section, then we need a DT_TEXTREL entry. */ if ((info->flags & DF_TEXTREL) == 0) - elf_link_hash_traverse (&htab->elf, readonly_dynrelocs, info); + elf_link_hash_traverse (&htab->etab, readonly_dynrelocs, info); if ((info->flags & DF_TEXTREL) != 0) { @@ -2621,31 +2625,31 @@ get_local_syms (bfd *output_bfd, bfd *in hh = hppa_elf_hash_entry (*eh_syms); - while (hh->elf.root.type == bfd_link_hash_indirect - || hh->elf.root.type == bfd_link_hash_warning) - hh = hppa_elf_hash_entry (hh->elf.root.u.i.link); + while (hh->eh.root.type == bfd_link_hash_indirect + || hh->eh.root.type == bfd_link_hash_warning) + hh = hppa_elf_hash_entry (hh->eh.root.u.i.link); /* At this point in the link, undefined syms have been resolved, so we need to check that the symbol was defined in this BFD. */ - if ((hh->elf.root.type == bfd_link_hash_defined - || hh->elf.root.type == bfd_link_hash_defweak) - && hh->elf.type == STT_FUNC - && hh->elf.root.u.def.section->output_section != NULL - && (hh->elf.root.u.def.section->output_section->owner + if ((hh->eh.root.type == bfd_link_hash_defined + || hh->eh.root.type == bfd_link_hash_defweak) + && hh->eh.type == STT_FUNC + && hh->eh.root.u.def.section->output_section != NULL + && (hh->eh.root.u.def.section->output_section->owner == output_bfd) - && hh->elf.root.u.def.section->owner == input_bfd - && hh->elf.def_regular - && !hh->elf.forced_local - && ELF_ST_VISIBILITY (hh->elf.other) == STV_DEFAULT) + && hh->eh.root.u.def.section->owner == input_bfd + && hh->eh.def_regular + && !hh->eh.forced_local + && ELF_ST_VISIBILITY (hh->eh.other) == STV_DEFAULT) { asection *sec; const char *stub_name; struct elf32_hppa_stub_hash_entry *hsh; - sec = hh->elf.root.u.def.section; - stub_name = hh->elf.root.root.string; - hsh = hppa_stub_hash_lookup (&htab->stub_hash_table, + sec = hh->eh.root.u.def.section; + stub_name = hh->eh.root.root.string; + hsh = hppa_stub_hash_lookup (&htab->bstab, stub_name, FALSE, FALSE); if (hsh == NULL) @@ -2654,10 +2658,10 @@ get_local_syms (bfd *output_bfd, bfd *in if (!hsh) return -1; - hsh->target_value = hh->elf.root.u.def.value; - hsh->target_section = hh->elf.root.u.def.section; + hsh->target_value = hh->eh.root.u.def.value; + hsh->target_section = hh->eh.root.u.def.section; hsh->stub_type = hppa_stub_export; - hsh->h = hh; + hsh->hh = hh; stub_changed = 1; } else @@ -2850,31 +2854,31 @@ elf32_hppa_size_stubs e_indx = r_indx - symtab_hdr->sh_info; hh = hppa_elf_hash_entry (elf_sym_hashes (input_bfd)[e_indx]); - while (hh->elf.root.type == bfd_link_hash_indirect - || hh->elf.root.type == bfd_link_hash_warning) - hh = hppa_elf_hash_entry (hh->elf.root.u.i.link); + while (hh->eh.root.type == bfd_link_hash_indirect + || hh->eh.root.type == bfd_link_hash_warning) + hh = hppa_elf_hash_entry (hh->eh.root.u.i.link); - if (hh->elf.root.type == bfd_link_hash_defined - || hh->elf.root.type == bfd_link_hash_defweak) + if (hh->eh.root.type == bfd_link_hash_defined + || hh->eh.root.type == bfd_link_hash_defweak) { - sym_sec = hh->elf.root.u.def.section; - sym_value = hh->elf.root.u.def.value; + sym_sec = hh->eh.root.u.def.section; + sym_value = hh->eh.root.u.def.value; if (sym_sec->output_section != NULL) destination = (sym_value + irela->r_addend + sym_sec->output_offset + sym_sec->output_section->vma); } - else if (hh->elf.root.type == bfd_link_hash_undefweak) + else if (hh->eh.root.type == bfd_link_hash_undefweak) { if (! info->shared) continue; } - else if (hh->elf.root.type == bfd_link_hash_undefined) + else if (hh->eh.root.type == bfd_link_hash_undefined) { if (! (info->unresolved_syms_in_objects == RM_IGNORE - && (ELF_ST_VISIBILITY (hh->elf.other) + && (ELF_ST_VISIBILITY (hh->eh.other) == STV_DEFAULT) - && hh->elf.type != STT_PARISC_MILLI)) + && hh->eh.type != STT_PARISC_MILLI)) continue; } else @@ -2898,7 +2902,7 @@ elf32_hppa_size_stubs if (!stub_name) goto error_ret_free_internal; - hsh = hppa_stub_hash_lookup (&htab->stub_hash_table, + hsh = hppa_stub_hash_lookup (&htab->bstab, stub_name, FALSE, FALSE); if (hsh != NULL) @@ -2925,7 +2929,7 @@ elf32_hppa_size_stubs else if (stub_type == hppa_stub_long_branch) hsh->stub_type = hppa_stub_long_branch_shared; } - hsh->h = hh; + hsh->hh = hh; stub_changed = TRUE; } @@ -2945,7 +2949,7 @@ elf32_hppa_size_stubs stub_sec = stub_sec->next) stub_sec->size = 0; - bfd_hash_traverse (&htab->stub_hash_table, hppa_size_one_stub, htab); + bfd_hash_traverse (&htab->bstab, hppa_size_one_stub, htab); /* Ask the linker to do its stuff. */ (*htab->layout_sections_again) (); @@ -2972,7 +2976,7 @@ elf32_hppa_set_gp (bfd *abfd, struct bfd struct elf32_hppa_link_hash_table *htab; htab = hppa_link_hash_table (info); - h = bfd_link_hash_lookup (&htab->elf.root, "$global$", FALSE, FALSE, FALSE); + h = bfd_link_hash_lookup (&htab->etab.root, "$global$", FALSE, FALSE, FALSE); if (h != NULL && (h->type == bfd_link_hash_defined @@ -3072,7 +3076,7 @@ elf32_hppa_build_stubs (struct bfd_link_ } /* Build the stubs as directed by the stub hash table. */ - table = &htab->stub_hash_table; + table = &htab->bstab; bfd_hash_traverse (table, hppa_build_one_stub, info); return TRUE; @@ -3187,12 +3191,12 @@ final_link_relocate (asection *input_sec if (sym_sec == NULL || sym_sec->output_section == NULL || (hh != NULL - && hh->elf.plt.offset != (bfd_vma) -1 - && hh->elf.dynindx != -1 + && hh->eh.plt.offset != (bfd_vma) -1 + && hh->eh.dynindx != -1 && !hh->plabel && (info->shared - || !hh->elf.def_regular - || hh->elf.root.type == bfd_link_hash_defweak))) + || !hh->eh.def_regular + || hh->eh.root.type == bfd_link_hash_defweak))) { hsh = hppa_get_stub_entry (input_section, sym_sec, hh, rela, htab); @@ -3204,7 +3208,7 @@ final_link_relocate (asection *input_sec addend = 0; } else if (sym_sec == NULL && hh != NULL - && hh->elf.root.type == bfd_link_hash_undefweak) + && hh->eh.root.type == bfd_link_hash_undefweak) { /* It's OK if undefined weak. Calls to undefined weak symbols behave as if the "called" function @@ -3400,7 +3404,7 @@ final_link_relocate (asection *input_sec input_bfd, input_section, offset, - hsh->root.string); + hsh->bh_root.string); bfd_set_error (bfd_error_bad_value); return bfd_reloc_notsupported; } @@ -3548,10 +3552,10 @@ elf32_hppa_relocate_section (bfd *output { bfd_boolean dyn; - off = hh->elf.got.offset; - dyn = htab->elf.dynamic_sections_created; + off = hh->eh.got.offset; + dyn = htab->etab.dynamic_sections_created; if (! WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, info->shared, - &hh->elf)) + &hh->eh)) { /* If we aren't going to call finish_dynamic_symbol, then we need to handle initialisation of the .got @@ -3563,7 +3567,7 @@ elf32_hppa_relocate_section (bfd *output off &= ~1; else { - hh->elf.got.offset |= 1; + hh->eh.got.offset |= 1; do_got = 1; } } @@ -3633,7 +3637,7 @@ elf32_hppa_relocate_section (bfd *output case R_PARISC_PLABEL14R: case R_PARISC_PLABEL21L: case R_PARISC_PLABEL32: - if (htab->elf.dynamic_sections_created) + if (htab->etab.dynamic_sections_created) { bfd_vma off; bfd_boolean do_plt = 0; @@ -3641,9 +3645,9 @@ elf32_hppa_relocate_section (bfd *output redirect this relocation to it. */ if (hh != NULL) { - off = hh->elf.plt.offset; + off = hh->eh.plt.offset; if (! WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, info->shared, - &hh->elf)) + &hh->eh)) { /* In a non-shared link, adjust_dynamic_symbols isn't called for symbols forced local. We @@ -3652,7 +3656,7 @@ elf32_hppa_relocate_section (bfd *output off &= ~1; else { - hh->elf.plt.offset |= 1; + hh->eh.plt.offset |= 1; do_plt = 1; } } @@ -3719,8 +3723,8 @@ elf32_hppa_relocate_section (bfd *output Exception: Undefined PLABELs should have a value of zero. */ if (hh == NULL - || (hh->elf.root.type != bfd_link_hash_undefweak - && hh->elf.root.type != bfd_link_hash_undefined)) + || (hh->eh.root.type != bfd_link_hash_undefweak + && hh->eh.root.type != bfd_link_hash_undefined)) { relocation = (off + htab->splt->output_offset @@ -3761,19 +3765,19 @@ elf32_hppa_relocate_section (bfd *output there all files have not been loaded. */ if ((info->shared && (hh == NULL - || ELF_ST_VISIBILITY (hh->elf.other) == STV_DEFAULT - || hh->elf.root.type != bfd_link_hash_undefweak) + || ELF_ST_VISIBILITY (hh->eh.other) == STV_DEFAULT + || hh->eh.root.type != bfd_link_hash_undefweak) && (IS_ABSOLUTE_RELOC (r_type) - || !SYMBOL_CALLS_LOCAL (info, &hh->elf))) + || !SYMBOL_CALLS_LOCAL (info, &hh->eh))) || (!info->shared && hh != NULL - && hh->elf.dynindx != -1 - && !hh->elf.non_got_ref + && hh->eh.dynindx != -1 + && !hh->eh.non_got_ref && ((ELIMINATE_COPY_RELOCS - && hh->elf.def_dynamic - && !hh->elf.def_regular) - || hh->elf.root.type == bfd_link_hash_undefweak - || hh->elf.root.type == bfd_link_hash_undefined))) + && hh->eh.def_dynamic + && !hh->eh.def_regular) + || hh->eh.root.type == bfd_link_hash_undefweak + || hh->eh.root.type == bfd_link_hash_undefined))) { Elf_Internal_Rela outrel; bfd_boolean skip; @@ -3798,14 +3802,14 @@ elf32_hppa_relocate_section (bfd *output memset (&outrel, 0, sizeof (outrel)); } else if (hh != NULL - && hh->elf.dynindx != -1 + && hh->eh.dynindx != -1 && (plabel || !IS_ABSOLUTE_RELOC (r_type) || !info->shared || !info->symbolic - || !hh->elf.def_regular)) + || !hh->eh.def_regular)) { - outrel.r_info = ELF32_R_INFO (hh->elf.dynindx, r_type); + outrel.r_info = ELF32_R_INFO (hh->eh.dynindx, r_type); } else /* It's a local symbol, or one marked to become local. */ { @@ -3861,7 +3865,7 @@ elf32_hppa_relocate_section (bfd *output continue; if (hh != NULL) - sym_name = hh->elf.root.root.string; + sym_name = hh->eh.root.root.string; else { sym_name = bfd_elf_string_from_elf_section (input_bfd, @@ -3893,7 +3897,7 @@ elf32_hppa_relocate_section (bfd *output else { if (!((*info->callbacks->reloc_overflow) - (info, (hh ? &hh->elf.root : NULL), sym_name, howto->name, + (info, (hh ? &hh->eh.root : NULL), sym_name, howto->name, (bfd_vma) 0, input_bfd, input_section, rela->r_offset))) return FALSE; } @@ -4072,11 +4076,11 @@ elf32_hppa_finish_dynamic_sections (bfd asection *sdyn; htab = hppa_link_hash_table (info); - dynobj = htab->elf.dynobj; + dynobj = htab->etab.dynobj; sdyn = bfd_get_section_by_name (dynobj, ".dynamic"); - if (htab->elf.dynamic_sections_created) + if (htab->etab.dynamic_sections_created) { Elf32_External_Dyn *dyncon, *dynconend; diff -uprN binutils-2.16.91.0.1/bfd/elf32-i370.c binutils-2.16.91.0.2/bfd/elf32-i370.c --- binutils-2.16.91.0.1/bfd/elf32-i370.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-i370.c 2005-07-20 12:27:27.157215466 -0700 @@ -1,31 +1,31 @@ /* i370-specific support for 32-bit ELF - Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004 + Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. Written by Ian Lance Taylor, Cygnus Support. Hacked by Linas Vepstas for i370 linas@linas.org -This file is part of BFD, the Binary File Descriptor library. + This file is part of BFD, the Binary File Descriptor library. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ /* This file is based on a preliminary PowerPC ELF ABI. But its been hacked on for the IBM 360/370 architectures. Basically, the 31bit relocation works, and just about everything else is a wild card. In particular, don't expect shared libs or - dynamic loading to work ... its never been tested ... -*/ + dynamic loading to work ... its never been tested. */ #include "bfd.h" #include "sysdep.h" @@ -98,7 +98,7 @@ static reloc_howto_type i370_elf_howto_r 0xffff, /* dst_mask */ FALSE), /* pcrel_offset */ - /* 31-bit PC relative */ + /* 31-bit PC relative. */ HOWTO (R_I370_REL31, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ @@ -113,7 +113,7 @@ static reloc_howto_type i370_elf_howto_r 0x7fffffff, /* dst_mask */ TRUE), /* pcrel_offset */ - /* 32-bit PC relative */ + /* 32-bit PC relative. */ HOWTO (R_I370_REL32, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ @@ -143,7 +143,7 @@ static reloc_howto_type i370_elf_howto_r 0xfff, /* dst_mask */ FALSE), /* pcrel_offset */ - /* 12-bit PC relative */ + /* 12-bit PC relative. */ HOWTO (R_I370_REL12, /* type */ 0, /* rightshift */ 1, /* size (0 = byte, 1 = short, 2 = long) */ @@ -173,7 +173,7 @@ static reloc_howto_type i370_elf_howto_r 0xff, /* dst_mask */ FALSE), /* pcrel_offset */ - /* 8-bit PC relative */ + /* 8-bit PC relative. */ HOWTO (R_I370_REL8, /* type */ 0, /* rightshift */ 0, /* size (0 = byte, 1 = short, 2 = long) */ @@ -226,19 +226,10 @@ static reloc_howto_type i370_elf_howto_r }; -static void i370_elf_howto_init - PARAMS ((void)); -static reloc_howto_type *i370_elf_reloc_type_lookup - PARAMS ((bfd *, bfd_reloc_code_real_type)); -static void i370_elf_info_to_howto - PARAMS ((bfd *abfd, arelent *cache_ptr, Elf_Internal_Rela *dst)); -static bfd_boolean i370_elf_set_private_flags - PARAMS ((bfd *, flagword)); - /* Initialize the i370_elf_howto_table, so that linear accesses can be done. */ static void -i370_elf_howto_init () +i370_elf_howto_init (void) { unsigned int i, type; @@ -249,21 +240,21 @@ i370_elf_howto_init () i370_elf_howto_table[type] = &i370_elf_howto_raw[i]; } } - + static reloc_howto_type * -i370_elf_reloc_type_lookup (abfd, code) - bfd *abfd ATTRIBUTE_UNUSED; - bfd_reloc_code_real_type code; +i370_elf_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) { enum i370_reloc_type i370_reloc = R_I370_NONE; - if (!i370_elf_howto_table[ R_I370_ADDR31 ]) /* Initialize howto table if needed */ + if (!i370_elf_howto_table[ R_I370_ADDR31 ]) + /* Initialize howto table if needed. */ i370_elf_howto_init (); - switch ((int)code) + switch ((int) code) { default: - return (reloc_howto_type *)NULL; + return NULL; case BFD_RELOC_NONE: i370_reloc = R_I370_NONE; break; case BFD_RELOC_32: i370_reloc = R_I370_ADDR31; break; @@ -276,30 +267,6 @@ i370_elf_reloc_type_lookup (abfd, code) return i370_elf_howto_table[ (int)i370_reloc ]; }; -static bfd_boolean i370_elf_merge_private_bfd_data - PARAMS ((bfd *, bfd *)); -static bfd_boolean i370_elf_relocate_section - PARAMS ((bfd *, struct bfd_link_info *info, bfd *, asection *, bfd_byte *, - Elf_Internal_Rela *relocs, Elf_Internal_Sym *local_syms, - asection **)); -static void i370_elf_post_process_headers - PARAMS ((bfd *, struct bfd_link_info *)); -static bfd_boolean i370_elf_create_dynamic_sections - PARAMS ((bfd *, struct bfd_link_info *)); -static bfd_boolean i370_elf_fake_sections - PARAMS ((bfd *, Elf_Internal_Shdr *, asection *)); -static bfd_boolean i370_elf_check_relocs - PARAMS ((bfd *, struct bfd_link_info *, asection *, - const Elf_Internal_Rela *)); -static bfd_boolean i370_elf_adjust_dynamic_symbol - PARAMS ((struct bfd_link_info *, struct elf_link_hash_entry *)); -static bfd_boolean i370_elf_adjust_dynindx - PARAMS ((struct elf_link_hash_entry *, PTR)); -static bfd_boolean i370_elf_size_dynamic_sections - PARAMS ((bfd *, struct bfd_link_info *)); -static bfd_boolean i370_elf_finish_dynamic_sections - PARAMS ((bfd *, struct bfd_link_info *)); - /* The name of the dynamic interpreter. This is put in the .interp section. */ @@ -308,26 +275,24 @@ static bfd_boolean i370_elf_finish_dynam /* Set the howto pointer for an i370 ELF reloc. */ static void -i370_elf_info_to_howto (abfd, cache_ptr, dst) - bfd *abfd ATTRIBUTE_UNUSED; - arelent *cache_ptr; - Elf_Internal_Rela *dst; +i370_elf_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED, + arelent *cache_ptr, + Elf_Internal_Rela *dst) { - if (!i370_elf_howto_table[ R_I370_ADDR31 ]) /* Initialize howto table */ + if (!i370_elf_howto_table[ R_I370_ADDR31 ]) + /* Initialize howto table. */ i370_elf_howto_init (); BFD_ASSERT (ELF32_R_TYPE (dst->r_info) < (unsigned int) R_I370_max); cache_ptr->howto = i370_elf_howto_table[ELF32_R_TYPE (dst->r_info)]; } -/* hack alert -- the following several routines look generic to me ... - * why are we bothering with them ??? - */ +/* Hack alert -- the following several routines look generic to me ... + why are we bothering with them ? */ /* Function to set whether a module needs the -mrelocatable bit set. */ + static bfd_boolean -i370_elf_set_private_flags (abfd, flags) - bfd *abfd; - flagword flags; +i370_elf_set_private_flags (bfd *abfd, flagword flags) { BFD_ASSERT (!elf_flags_init (abfd) || elf_elfheader (abfd)->e_flags == flags); @@ -338,11 +303,10 @@ i370_elf_set_private_flags (abfd, flags) } /* Merge backend specific data from an object file to the output - object file when linking */ + object file when linking. */ + static bfd_boolean -i370_elf_merge_private_bfd_data (ibfd, obfd) - bfd *ibfd; - bfd *obfd; +i370_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd) { flagword old_flags; flagword new_flags; @@ -353,16 +317,16 @@ i370_elf_merge_private_bfd_data (ibfd, o new_flags = elf_elfheader (ibfd)->e_flags; old_flags = elf_elfheader (obfd)->e_flags; - if (!elf_flags_init (obfd)) /* First call, no flags set */ + if (!elf_flags_init (obfd)) /* First call, no flags set. */ { elf_flags_init (obfd) = TRUE; elf_elfheader (obfd)->e_flags = new_flags; } - else if (new_flags == old_flags) /* Compatible flags are ok */ + else if (new_flags == old_flags) /* Compatible flags are ok. */ ; - else /* Incompatible flags */ + else /* Incompatible flags. */ { (*_bfd_error_handler) ("%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)", @@ -378,9 +342,8 @@ i370_elf_merge_private_bfd_data (ibfd, o /* Handle an i370 specific section when reading an object file. This is called when elfcode.h finds a section with an unknown type. */ /* XXX hack alert bogus This routine is mostly all junk and almost - * certainly does the wrong thing. Its here simply because it does - * just enough to allow glibc-2.1 ld.so to compile & link. - */ + certainly does the wrong thing. Its here simply because it does + just enough to allow glibc-2.1 ld.so to compile & link. */ static bfd_boolean i370_elf_section_from_shdr (bfd *abfd, @@ -408,15 +371,13 @@ i370_elf_section_from_shdr (bfd *abfd, /* Set up any other section flags and such that may be necessary. */ /* XXX hack alert bogus This routine is mostly all junk and almost - * certainly does the wrong thing. Its here simply because it does - * just enough to allow glibc-2.1 ld.so to compile & link. - */ + certainly does the wrong thing. Its here simply because it does + just enough to allow glibc-2.1 ld.so to compile & link. */ static bfd_boolean -i370_elf_fake_sections (abfd, shdr, asect) - bfd *abfd ATTRIBUTE_UNUSED; - Elf_Internal_Shdr *shdr; - asection *asect; +i370_elf_fake_sections (bfd *abfd ATTRIBUTE_UNUSED, + Elf_Internal_Shdr *shdr, + asection *asect) { if ((asect->flags & SEC_EXCLUDE) != 0) shdr->sh_flags |= SHF_EXCLUDE; @@ -431,16 +392,13 @@ i370_elf_fake_sections (abfd, shdr, asec to output sections (just like _bfd_elf_create_dynamic_sections has to create .dynbss and .rela.bss). */ /* XXX hack alert bogus This routine is mostly all junk and almost - * certainly does the wrong thing. Its here simply because it does - * just enough to allow glibc-2.1 ld.so to compile & link. - */ + certainly does the wrong thing. Its here simply because it does + just enough to allow glibc-2.1 ld.so to compile & link. */ static bfd_boolean -i370_elf_create_dynamic_sections (abfd, info) - bfd *abfd; - struct bfd_link_info *info; +i370_elf_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info) { - register asection *s; + asection *s; flagword flags; if (!_bfd_elf_create_dynamic_sections(abfd, info)) @@ -463,7 +421,7 @@ i370_elf_create_dynamic_sections (abfd, return FALSE; } - /* xxx beats me, seem to need a rela.text ... */ + /* XXX beats me, seem to need a rela.text ... */ s = bfd_make_section_with_flags (abfd, ".rela.text", flags | SEC_READONLY); if (s == NULL @@ -478,14 +436,12 @@ i370_elf_create_dynamic_sections (abfd, change the definition to something the rest of the link can understand. */ /* XXX hack alert bogus This routine is mostly all junk and almost - * certainly does the wrong thing. Its here simply because it does - * just enough to allow glibc-2.1 ld.so to compile & link. - */ + certainly does the wrong thing. Its here simply because it does + just enough to allow glibc-2.1 ld.so to compile & link. */ static bfd_boolean -i370_elf_adjust_dynamic_symbol (info, h) - struct bfd_link_info *info; - struct elf_link_hash_entry *h; +i370_elf_adjust_dynamic_symbol (struct bfd_link_info *info, + struct elf_link_hash_entry *h) { bfd *dynobj = elf_hash_table (info)->dynobj; asection *s; @@ -594,14 +550,11 @@ i370_elf_adjust_dynamic_symbol (info, h) /* Increment the index of a dynamic symbol by a given amount. Called via elf_link_hash_traverse. */ /* XXX hack alert bogus This routine is mostly all junk and almost - * certainly does the wrong thing. Its here simply because it does - * just enough to allow glibc-2.1 ld.so to compile & link. - */ + certainly does the wrong thing. Its here simply because it does + just enough to allow glibc-2.1 ld.so to compile & link. */ static bfd_boolean -i370_elf_adjust_dynindx (h, cparg) - struct elf_link_hash_entry *h; - PTR cparg; +i370_elf_adjust_dynindx (struct elf_link_hash_entry *h, void * cparg) { int *cp = (int *) cparg; @@ -622,14 +575,12 @@ i370_elf_adjust_dynindx (h, cparg) /* Set the sizes of the dynamic sections. */ /* XXX hack alert bogus This routine is mostly all junk and almost - * certainly does the wrong thing. Its here simply because it does - * just enough to allow glibc-2.1 ld.so to compile & link. - */ + certainly does the wrong thing. Its here simply because it does + just enough to allow glibc-2.1 ld.so to compile & link. */ static bfd_boolean -i370_elf_size_dynamic_sections (output_bfd, info) - bfd *output_bfd; - struct bfd_link_info *info; +i370_elf_size_dynamic_sections (bfd *output_bfd, + struct bfd_link_info *info) { bfd *dynobj; asection *s; @@ -664,10 +615,10 @@ i370_elf_size_dynamic_sections (output_b stripped from the output file below. */ static char *rela_sections[] = { ".rela.got", ".rela.sdata", ".rela.sdata2", ".rela.sbss", - (char *)0 }; + NULL }; char **p; - for (p = rela_sections; *p != (char *)0; p++) + for (p = rela_sections; *p != NULL; p++) { s = bfd_get_section_by_name (dynobj, *p); if (s != NULL) @@ -684,7 +635,6 @@ i370_elf_size_dynamic_sections (output_b for (s = dynobj->sections; s != NULL; s = s->next) { const char *name; - bfd_boolean strip; if ((s->flags & SEC_LINKER_CREATED) == 0) continue; @@ -692,38 +642,15 @@ i370_elf_size_dynamic_sections (output_b /* It's OK to base decisions on the section name, because none of the dynobj section names depend upon the input files. */ name = bfd_get_section_name (dynobj, s); - strip = FALSE; if (strcmp (name, ".plt") == 0) { - if (s->size == 0) - { - /* Strip this section if we don't need it; see the - comment below. */ - strip = TRUE; - } - else - { - /* Remember whether there is a PLT. */ - plt = TRUE; - } + /* Remember whether there is a PLT. */ + plt = s->size != 0; } else if (strncmp (name, ".rela", 5) == 0) { - if (s->size == 0) - { - /* If we don't need this section, strip it from the - output file. This is mostly to handle .rela.bss and - .rela.plt. We must create both sections in - create_dynamic_sections, because they must be created - before the linker maps input sections to output - sections. The linker does that before - adjust_dynamic_symbol is called, and it is that - function which decides whether anything needs to go - into these sections. */ - strip = TRUE; - } - else + if (s->size != 0) { asection *target; const char *outname; @@ -748,26 +675,35 @@ i370_elf_size_dynamic_sections (output_b } else if (strcmp (name, ".got") != 0 && strcmp (name, ".sdata") != 0 - && strcmp (name, ".sdata2") != 0) + && strcmp (name, ".sdata2") != 0 + && strcmp (name, ".dynbss") != 0 + && strcmp (name, ".dynsbss") != 0) { /* It's not one of our sections, so don't allocate space. */ continue; } - if (strip) + if (s->size == 0) { - if (!bfd_section_removed_from_list (s->output_section->owner, - s->output_section)) - { - bfd_section_list_remove (s->output_section->owner, - s->output_section); - --s->output_section->owner->section_count; - } + /* If we don't need this section, strip it from the + output file. This is mostly to handle .rela.bss and + .rela.plt. We must create both sections in + create_dynamic_sections, because they must be created + before the linker maps input sections to output + sections. The linker does that before + adjust_dynamic_symbol is called, and it is that + function which decides whether anything needs to go + into these sections. */ + s->flags |= SEC_EXCLUDE; continue; } + + if ((s->flags & SEC_HAS_CONTENTS) == 0) + continue; + /* Allocate memory for the section contents. */ - s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); - if (s->contents == NULL && s->size != 0) + s->contents = bfd_zalloc (dynobj, s->size); + if (s->contents == NULL) return FALSE; } @@ -845,8 +781,7 @@ i370_elf_size_dynamic_sections (output_b } elf_link_hash_traverse (elf_hash_table (info), - i370_elf_adjust_dynindx, - (PTR) &c); + i370_elf_adjust_dynindx, & c); elf_hash_table (info)->dynsymcount += c; } @@ -857,16 +792,14 @@ i370_elf_size_dynamic_sections (output_b allocate space in the global offset table or procedure linkage table. */ /* XXX hack alert bogus This routine is mostly all junk and almost - * certainly does the wrong thing. Its here simply because it does - * just enough to allow glibc-2.1 ld.so to compile & link. - */ + certainly does the wrong thing. Its here simply because it does + just enough to allow glibc-2.1 ld.so to compile & link. */ static bfd_boolean -i370_elf_check_relocs (abfd, info, sec, relocs) - bfd *abfd; - struct bfd_link_info *info; - asection *sec; - const Elf_Internal_Rela *relocs; +i370_elf_check_relocs (bfd *abfd, + struct bfd_link_info *info, + asection *sec, + const Elf_Internal_Rela *relocs) { bfd *dynobj; Elf_Internal_Shdr *symtab_hdr; @@ -963,14 +896,12 @@ i370_elf_check_relocs (abfd, info, sec, /* Finish up the dynamic sections. */ /* XXX hack alert bogus This routine is mostly all junk and almost - * certainly does the wrong thing. Its here simply because it does - * just enough to allow glibc-2.1 ld.so to compile & link. - */ + certainly does the wrong thing. Its here simply because it does + just enough to allow glibc-2.1 ld.so to compile & link. */ static bfd_boolean -i370_elf_finish_dynamic_sections (output_bfd, info) - bfd *output_bfd; - struct bfd_link_info *info; +i370_elf_finish_dynamic_sections (bfd *output_bfd, + struct bfd_link_info *info) { asection *sdyn; bfd *dynobj = elf_hash_table (info)->dynobj; @@ -1027,7 +958,7 @@ i370_elf_finish_dynamic_sections (output } } - if (sgot) + if (sgot && sgot->size != 0) { unsigned char *contents = sgot->contents; @@ -1078,7 +1009,7 @@ i370_elf_finish_dynamic_sections (output sym.st_shndx = indx; esym = (Elf32_External_Sym *) sdynsym->contents + dindx; - bfd_elf32_swap_symbol_out (output_bfd, &sym, (PTR) esym, (PTR) 0); + bfd_elf32_swap_symbol_out (output_bfd, &sym, esym, NULL); } } @@ -1121,16 +1052,14 @@ i370_elf_finish_dynamic_sections (output accordingly. */ static bfd_boolean -i370_elf_relocate_section (output_bfd, info, input_bfd, input_section, - contents, relocs, local_syms, local_sections) - bfd *output_bfd; - struct bfd_link_info *info; - bfd *input_bfd; - asection *input_section; - bfd_byte *contents; - Elf_Internal_Rela *relocs; - Elf_Internal_Sym *local_syms; - asection **local_sections; +i370_elf_relocate_section (bfd *output_bfd, + struct bfd_link_info *info, + bfd *input_bfd, + asection *input_section, + bfd_byte *contents, + Elf_Internal_Rela *relocs, + Elf_Internal_Sym *local_syms, + asection **local_sections) { Elf_Internal_Shdr *symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd); @@ -1151,27 +1080,28 @@ i370_elf_relocate_section (output_bfd, i (info->relocatable) ? " (relocatable)" : ""); #endif - if (!i370_elf_howto_table[ R_I370_ADDR31 ]) /* Initialize howto table if needed */ + if (!i370_elf_howto_table[ R_I370_ADDR31 ]) + /* Initialize howto table if needed. */ i370_elf_howto_init (); local_got_offsets = elf_local_got_offsets (input_bfd); for (; rel < relend; rel++) { - enum i370_reloc_type r_type = (enum i370_reloc_type)ELF32_R_TYPE (rel->r_info); - bfd_vma offset = rel->r_offset; - bfd_vma addend = rel->r_addend; - bfd_reloc_status_type r = bfd_reloc_other; - Elf_Internal_Sym *sym = (Elf_Internal_Sym *)0; - asection *sec = (asection *)0; - struct elf_link_hash_entry *h = (struct elf_link_hash_entry *)0; - const char *sym_name = (const char *)0; + enum i370_reloc_type r_type = (enum i370_reloc_type) ELF32_R_TYPE (rel->r_info); + bfd_vma offset = rel->r_offset; + bfd_vma addend = rel->r_addend; + bfd_reloc_status_type r = bfd_reloc_other; + Elf_Internal_Sym *sym = NULL; + asection *sec = NULL; + struct elf_link_hash_entry * h = NULL; + const char *sym_name = NULL; reloc_howto_type *howto; unsigned long r_symndx; bfd_vma relocation; - /* Unknown relocation handling */ - if ((unsigned)r_type >= (unsigned)R_I370_max + /* Unknown relocation handling. */ + if ((unsigned) r_type >= (unsigned) R_I370_max || !i370_elf_howto_table[(int)r_type]) { (*_bfd_error_handler) ("%B: unknown relocation type %d", @@ -1183,7 +1113,7 @@ i370_elf_relocate_section (output_bfd, i continue; } - howto = i370_elf_howto_table[(int)r_type]; + howto = i370_elf_howto_table[(int) r_type]; r_symndx = ELF32_R_SYM (rel->r_info); if (r_symndx < symtab_hdr->sh_info) @@ -1192,7 +1122,7 @@ i370_elf_relocate_section (output_bfd, i sec = local_sections[r_symndx]; sym_name = ""; - relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); + relocation = _bfd_elf_rela_local_sym (output_bfd, sym, & sec, rel); addend = rel->r_addend; } else @@ -1214,12 +1144,10 @@ i370_elf_relocate_section (output_bfd, i || r_type == R_I370_COPY || r_type == R_I370_ADDR16 || r_type == R_I370_RELATIVE)) - { - /* In these cases, we don't need the relocation - value. We check specially because in some - obscure cases sec->output_section will be NULL. */ - relocation = 0; - } + /* In these cases, we don't need the relocation + value. We check specially because in some + obscure cases sec->output_section will be NULL. */ + relocation = 0; else relocation = (h->root.u.def.value + sec->output_section->vma @@ -1256,23 +1184,23 @@ i370_elf_relocate_section (output_bfd, i ret = FALSE; continue; - case (int)R_I370_NONE: + case (int) R_I370_NONE: continue; /* Relocations that may need to be propagated if this is a shared object. */ - case (int)R_I370_REL31: + case (int) R_I370_REL31: /* If these relocations are not to a named symbol, they can be handled right here, no need to bother the dynamic linker. */ if (h == NULL || strcmp (h->root.root.string, "_GLOBAL_OFFSET_TABLE_") == 0) break; - /* fall through */ + /* Fall through. */ /* Relocations that always need to be propagated if this is a shared object. */ - case (int)R_I370_ADDR31: - case (int)R_I370_ADDR16: + case (int) R_I370_ADDR31: + case (int) R_I370_ADDR16: if (info->shared && r_symndx != 0) { @@ -1387,8 +1315,8 @@ i370_elf_relocate_section (output_bfd, i } break; - case (int)R_I370_COPY: - case (int)R_I370_RELATIVE: + case (int) R_I370_COPY: + case (int) R_I370_RELATIVE: (*_bfd_error_handler) ("%B: Relocation %s is not yet supported for symbol %s.", input_bfd, @@ -1406,17 +1334,12 @@ i370_elf_relocate_section (output_bfd, i (int)r_type, sym_name, r_symndx, - (long)offset, - (long)addend); + (long) offset, + (long) addend); #endif - r = _bfd_final_link_relocate (howto, - input_bfd, - input_section, - contents, - offset, - relocation, - addend); + r = _bfd_final_link_relocate (howto, input_bfd, input_section, contents, + offset, relocation, addend); if (r != bfd_reloc_ok) { @@ -1454,7 +1377,6 @@ i370_elf_relocate_section (output_bfd, i offset); } break; - } } } @@ -1467,11 +1389,10 @@ i370_elf_relocate_section (output_bfd, i } static void -i370_elf_post_process_headers (abfd, link_info) - bfd * abfd; - struct bfd_link_info * link_info ATTRIBUTE_UNUSED; +i370_elf_post_process_headers (bfd * abfd, + struct bfd_link_info * link_info ATTRIBUTE_UNUSED) { - Elf_Internal_Ehdr * i_ehdrp; /* Elf file header, internal form */ + Elf_Internal_Ehdr * i_ehdrp; /* Elf file header, internal form. */ i_ehdrp = elf_elfheader (abfd); i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_LINUX; @@ -1488,16 +1409,15 @@ i370_elf_post_process_headers (abfd, lin #define elf_info_to_howto i370_elf_info_to_howto #define elf_backend_plt_not_loaded 1 -#define elf_backend_rela_normal 1 +#define elf_backend_rela_normal 1 #define bfd_elf32_bfd_reloc_type_lookup i370_elf_reloc_type_lookup #define bfd_elf32_bfd_set_private_flags i370_elf_set_private_flags #define bfd_elf32_bfd_merge_private_bfd_data i370_elf_merge_private_bfd_data #define elf_backend_relocate_section i370_elf_relocate_section -/* dynamic loader support is mostly broken; just enough here to be able to - * link glibc's ld.so without errors. - */ +/* Dynamic loader support is mostly broken; just enough here to be able to + link glibc's ld.so without errors. */ #define elf_backend_create_dynamic_sections i370_elf_create_dynamic_sections #define elf_backend_size_dynamic_sections i370_elf_size_dynamic_sections #define elf_backend_finish_dynamic_sections i370_elf_finish_dynamic_sections @@ -1505,37 +1425,27 @@ i370_elf_post_process_headers (abfd, lin #define elf_backend_section_from_shdr i370_elf_section_from_shdr #define elf_backend_adjust_dynamic_symbol i370_elf_adjust_dynamic_symbol #define elf_backend_check_relocs i370_elf_check_relocs - -/* -#define elf_backend_add_symbol_hook i370_elf_add_symbol_hook -#define elf_backend_finish_dynamic_symbol i370_elf_finish_dynamic_symbol -#define elf_backend_additional_program_headers i370_elf_additional_program_headers -#define elf_backend_modify_segment_map i370_elf_modify_segment_map -*/ - #define elf_backend_post_process_headers i370_elf_post_process_headers -static int i370_noop - PARAMS ((void)); - -static int i370_noop () +static int +i370_noop (void) { return 1; } -/* we need to define these at least as no-ops to link glibc ld.so */ +/* We need to define these at least as no-ops to link glibc ld.so. */ #define elf_backend_add_symbol_hook \ (bfd_boolean (*) \ - PARAMS ((bfd *, struct bfd_link_info *, Elf_Internal_Sym *, \ - const char **, flagword *, asection **, bfd_vma *))) i370_noop + (bfd *, struct bfd_link_info *, Elf_Internal_Sym *, \ + const char **, flagword *, asection **, bfd_vma *)) i370_noop #define elf_backend_finish_dynamic_symbol \ (bfd_boolean (*) \ - PARAMS ((bfd *, struct bfd_link_info *, struct elf_link_hash_entry *, \ - Elf_Internal_Sym *))) i370_noop + (bfd *, struct bfd_link_info *, struct elf_link_hash_entry *, \ + Elf_Internal_Sym *)) i370_noop #define elf_backend_additional_program_headers \ - (int (*) PARAMS ((bfd *))) i370_noop + (int (*) (bfd *)) i370_noop #define elf_backend_modify_segment_map \ - (bfd_boolean (*) PARAMS ((bfd *, struct bfd_link_info *))) i370_noop + (bfd_boolean (*) (bfd *, struct bfd_link_info *)) i370_noop #include "elf32-target.h" diff -uprN binutils-2.16.91.0.1/bfd/elf32-i386.c binutils-2.16.91.0.2/bfd/elf32-i386.c --- binutils-2.16.91.0.1/bfd/elf32-i386.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-i386.c 2005-07-20 12:27:27.171213157 -0700 @@ -95,7 +95,7 @@ static reloc_howto_type elf_howto_table[ HOWTO(R_386_16, 0, 1, 16, FALSE, 0, complain_overflow_bitfield, bfd_elf_generic_reloc, "R_386_16", TRUE, 0xffff, 0xffff, FALSE), - HOWTO(R_386_PC16, 0, 1, 16, TRUE, 0, complain_overflow_bitfield, + HOWTO(R_386_PC16, 0, 1, 16, TRUE, 0, complain_overflow_signed, bfd_elf_generic_reloc, "R_386_PC16", TRUE, 0xffff, 0xffff, TRUE), HOWTO(R_386_8, 0, 0, 8, FALSE, 0, complain_overflow_bitfield, @@ -1948,7 +1948,7 @@ elf_i386_size_dynamic_sections (bfd *out continue; } - if (s->size == 0 && strip_section) + if (s->size == 0) { /* If we don't need this section, strip it from the output file. This is mostly to handle .rel.bss and @@ -1959,11 +1959,14 @@ elf_i386_size_dynamic_sections (bfd *out adjust_dynamic_symbol is called, and it is that function which decides whether anything needs to go into these sections. */ - - s->flags |= SEC_EXCLUDE; + if (strip_section) + s->flags |= SEC_EXCLUDE; continue; } + if ((s->flags & SEC_HAS_CONTENTS) == 0) + continue; + /* Allocate memory for the section contents. We use bfd_zalloc here in case unused entries are not reclaimed before the section's contents are written out. This should not happen, diff -uprN binutils-2.16.91.0.1/bfd/elf32-i960.c binutils-2.16.91.0.2/bfd/elf32-i960.c --- binutils-2.16.91.0.1/bfd/elf32-i960.c 2005-05-10 15:46:41.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-i960.c 2005-07-20 12:27:27.192209695 -0700 @@ -1,21 +1,22 @@ /* Intel 960 specific support for 32-bit ELF - Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + Copyright 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. -This file is part of BFD, the Binary File Descriptor library. + This file is part of BFD, the Binary File Descriptor library. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "bfd.h" #include "sysdep.h" @@ -23,33 +24,73 @@ Foundation, Inc., 51 Franklin Street - F #include "elf-bfd.h" #include "elf/i960.h" -static bfd_reloc_status_type elf32_i960_relocate - PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); -static reloc_howto_type *elf32_i960_reloc_type_lookup - PARAMS ((bfd *, bfd_reloc_code_real_type)); -static void elf32_i960_info_to_howto - PARAMS ((bfd *, arelent *cache_ptr, Elf_Internal_Rela *)); -static void elf32_i960_info_to_howto_rel - PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); - #define USE_REL 1 #define bfd_elf32_bfd_reloc_type_lookup elf32_i960_reloc_type_lookup #define elf_info_to_howto elf32_i960_info_to_howto #define elf_info_to_howto_rel elf32_i960_info_to_howto_rel +/* ELF relocs are against symbols. If we are producing relocatable + output, and the reloc is against an external symbol, and nothing + has given us any additional addend, the resulting reloc will also + be against the same symbol. In such a case, we don't want to + change anything about the way the reloc is handled, since it will + all be done at final link time. Rather than put special case code + into bfd_perform_relocation, all the reloc types use this howto + function. It just short circuits the reloc if producing + relocatable output against an external symbol. */ + +static bfd_reloc_status_type +elf32_i960_relocate (bfd *abfd ATTRIBUTE_UNUSED, + arelent *reloc_entry, + asymbol *symbol, + PTR data ATTRIBUTE_UNUSED, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) +{ + /* HACK: I think this first condition is necessary when producing + relocatable output. After the end of HACK, the code is identical + to bfd_elf_generic_reloc(). I would _guess_ the first change + belongs there rather than here. martindo 1998-10-23. */ + if (output_bfd != (bfd *) NULL + && reloc_entry->howto->pc_relative + && !reloc_entry->howto->pcrel_offset) + reloc_entry->addend -= symbol->value; + + /* This is more dubious. */ + else if (output_bfd != (bfd *) NULL + && (symbol->flags & BSF_SECTION_SYM) != 0) + reloc_entry->addend -= symbol->section->output_section->vma; + + else + { + /* ...end of HACK. */ + if (output_bfd != (bfd *) NULL + && (symbol->flags & BSF_SECTION_SYM) == 0 + && (! reloc_entry->howto->partial_inplace + || reloc_entry->addend == 0)) + { + reloc_entry->address += input_section->output_offset; + return bfd_reloc_ok; + } + } + + return bfd_reloc_continue; +} + static reloc_howto_type elf_howto_table[]= { - HOWTO(R_960_NONE, 0, 0, 0, FALSE, 0, complain_overflow_bitfield, - elf32_i960_relocate, "R_960_NONE", TRUE, - 0x00000000, 0x00000000, FALSE), + HOWTO (R_960_NONE, 0, 0, 0, FALSE, 0, complain_overflow_bitfield, + elf32_i960_relocate, "R_960_NONE", TRUE, + 0x00000000, 0x00000000, FALSE), EMPTY_HOWTO (1), HOWTO (R_960_32, 0, 2, 32, FALSE, 0, complain_overflow_bitfield, - elf32_i960_relocate, "R_960_32", TRUE, - 0xffffffff, 0xffffffff, FALSE), + elf32_i960_relocate, "R_960_32", TRUE, + 0xffffffff, 0xffffffff, FALSE), HOWTO (R_960_IP24, 0, 2, 24, TRUE, 0, complain_overflow_signed, - elf32_i960_relocate, "R_960_IP24 ", TRUE, - 0x00ffffff, 0x00ffffff, FALSE), + elf32_i960_relocate, "R_960_IP24 ", TRUE, + 0x00ffffff, 0x00ffffff, FALSE), EMPTY_HOWTO (4), EMPTY_HOWTO (5), EMPTY_HOWTO (6), @@ -74,19 +115,17 @@ elf32_i960_bfd_to_reloc_type (bfd_reloc_ } static void -elf32_i960_info_to_howto (abfd, cache_ptr, dst) - bfd *abfd ATTRIBUTE_UNUSED; - arelent *cache_ptr ATTRIBUTE_UNUSED; - Elf_Internal_Rela *dst ATTRIBUTE_UNUSED; +elf32_i960_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, + arelent * cache_ptr ATTRIBUTE_UNUSED, + Elf_Internal_Rela * dst ATTRIBUTE_UNUSED) { abort (); } static void -elf32_i960_info_to_howto_rel (abfd, cache_ptr, dst) - bfd *abfd ATTRIBUTE_UNUSED; - arelent *cache_ptr; - Elf_Internal_Rela *dst; +elf32_i960_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED, + arelent *cache_ptr, + Elf_Internal_Rela *dst) { enum elf_i960_reloc_type type; @@ -96,63 +135,9 @@ elf32_i960_info_to_howto_rel (abfd, cach cache_ptr->howto = &elf_howto_table[(int) type]; } -/* ELF relocs are against symbols. If we are producing relocatable - output, and the reloc is against an external symbol, and nothing - has given us any additional addend, the resulting reloc will also - be against the same symbol. In such a case, we don't want to - change anything about the way the reloc is handled, since it will - all be done at final link time. Rather than put special case code - into bfd_perform_relocation, all the reloc types use this howto - function. It just short circuits the reloc if producing - relocatable output against an external symbol. */ - -bfd_reloc_status_type -elf32_i960_relocate (abfd, reloc_entry, symbol, data, input_section, - output_bfd, error_message) - bfd *abfd ATTRIBUTE_UNUSED; - arelent *reloc_entry; - asymbol *symbol; - PTR data ATTRIBUTE_UNUSED; - asection *input_section; - bfd *output_bfd; - char **error_message ATTRIBUTE_UNUSED; -{ - /* HACK: I think this first condition is necessary when producing - relocatable output. After the end of HACK, the code is identical - to bfd_elf_generic_reloc(). I would _guess_ the first change - belongs there rather than here. martindo 1998-10-23. */ - if (output_bfd != (bfd *) NULL - && reloc_entry->howto->pc_relative - && !reloc_entry->howto->pcrel_offset) - { - reloc_entry->addend -= symbol->value; - } - /* This is more dubious. */ - else if (output_bfd != (bfd *) NULL - && (symbol->flags & BSF_SECTION_SYM) != 0) - { - reloc_entry->addend -= symbol->section->output_section->vma; - } - else - { - /* end of HACK */ - if (output_bfd != (bfd *) NULL - && (symbol->flags & BSF_SECTION_SYM) == 0 - && (! reloc_entry->howto->partial_inplace - || reloc_entry->addend == 0)) - { - reloc_entry->address += input_section->output_offset; - return bfd_reloc_ok; - } - } - - return bfd_reloc_continue; -} - static reloc_howto_type * -elf32_i960_reloc_type_lookup (abfd, code) - bfd *abfd ATTRIBUTE_UNUSED; - bfd_reloc_code_real_type code; +elf32_i960_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) { return elf_howto_table + elf32_i960_bfd_to_reloc_type (code); } diff -uprN binutils-2.16.91.0.1/bfd/elf32-ip2k.c binutils-2.16.91.0.2/bfd/elf32-ip2k.c --- binutils-2.16.91.0.1/bfd/elf32-ip2k.c 2005-05-10 15:46:41.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-ip2k.c 2005-07-20 12:27:27.197208871 -0700 @@ -16,7 +16,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "bfd.h" #include "sysdep.h" @@ -39,59 +40,12 @@ struct ip2k_opcode unsigned short opcode; unsigned short mask; }; - -/* Prototypes. */ -static reloc_howto_type *ip2k_reloc_type_lookup - PARAMS ((bfd *, bfd_reloc_code_real_type)); -static int ip2k_is_opcode - PARAMS ((bfd_byte *, const struct ip2k_opcode *)); -static bfd_vma symbol_value - PARAMS ((bfd *, Elf_Internal_Shdr *, Elf_Internal_Sym *, - Elf_Internal_Rela *)); -static void ip2k_get_mem - PARAMS ((bfd *, bfd_byte *, int, bfd_byte *)); -static bfd_vma ip2k_nominal_page_bits - PARAMS ((bfd *, asection *, bfd_vma, bfd_byte *)); -static bfd_boolean ip2k_test_page_insn - PARAMS ((bfd *, asection *, Elf_Internal_Rela *, struct misc *)); -static bfd_boolean ip2k_delete_page_insn - PARAMS ((bfd *, asection *, Elf_Internal_Rela *, bfd_boolean *, struct misc *)); -static int ip2k_is_switch_table_128 - PARAMS ((bfd *, asection *, bfd_vma, bfd_byte *)); -static bfd_boolean ip2k_relax_switch_table_128 - PARAMS ((bfd *, asection *, Elf_Internal_Rela *, bfd_boolean *, struct misc *)); -static int ip2k_is_switch_table_256 - PARAMS ((bfd *, asection *, bfd_vma, bfd_byte *)); -static bfd_boolean ip2k_relax_switch_table_256 - PARAMS ((bfd *, asection *, Elf_Internal_Rela *, bfd_boolean *, struct misc *)); -static bfd_boolean ip2k_elf_relax_section - PARAMS ((bfd *, asection *, struct bfd_link_info *, bfd_boolean *)); -static bfd_boolean ip2k_elf_relax_section_page - PARAMS ((bfd *, asection *, bfd_boolean *, struct misc *, unsigned long, unsigned long)); -static void adjust_all_relocations - PARAMS ((bfd *, asection *, bfd_vma, bfd_vma, int, int)); -static bfd_boolean ip2k_elf_relax_delete_bytes - PARAMS ((bfd *, asection *, bfd_vma, int)); -static void ip2k_info_to_howto_rela - PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); -static bfd_reloc_status_type ip2k_final_link_relocate - PARAMS ((reloc_howto_type *, bfd *, asection *, bfd_byte *, - Elf_Internal_Rela *, bfd_vma)); -static bfd_boolean ip2k_elf_relocate_section - PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, - Elf_Internal_Rela *, Elf_Internal_Sym *, asection **)); -static asection *ip2k_elf_gc_mark_hook - PARAMS ((asection *, struct bfd_link_info *, Elf_Internal_Rela *, - struct elf_link_hash_entry *, Elf_Internal_Sym *)); -static bfd_boolean ip2k_elf_gc_sweep_hook - PARAMS ((bfd *, struct bfd_link_info *, asection *, - const Elf_Internal_Rela *)); static bfd_boolean ip2k_relaxed = FALSE; static const struct ip2k_opcode ip2k_page_opcode[] = { - {0x0010, 0xFFF8}, /* page */ + {0x0010, 0xFFF8}, /* Page. */ {0x0000, 0x0000}, }; @@ -100,7 +54,7 @@ static const struct ip2k_opcode ip2k_pag static const struct ip2k_opcode ip2k_jmp_opcode[] = { - {0xE000, 0xE000}, /* jmp */ + {0xE000, 0xE000}, /* Jmp. */ {0x0000, 0x0000}, }; @@ -109,7 +63,7 @@ static const struct ip2k_opcode ip2k_jmp static const struct ip2k_opcode ip2k_snc_opcode[] = { - {0xA00B, 0xFFFF}, /* snc */ + {0xA00B, 0xFFFF}, /* Snc. */ {0x0000, 0x0000}, }; @@ -118,7 +72,7 @@ static const struct ip2k_opcode ip2k_snc static const struct ip2k_opcode ip2k_inc_1sp_opcode[] = { - {0x2B81, 0xFFFF}, /* inc 1(SP) */ + {0x2B81, 0xFFFF}, /* Inc 1(SP). */ {0x0000, 0x0000}, }; @@ -127,7 +81,7 @@ static const struct ip2k_opcode ip2k_inc static const struct ip2k_opcode ip2k_add_2sp_w_opcode[] = { - {0x1F82, 0xFFFF}, /* add 2(SP),w */ + {0x1F82, 0xFFFF}, /* Add 2(SP),w. */ {0x0000, 0x0000}, }; @@ -136,8 +90,8 @@ static const struct ip2k_opcode ip2k_add static const struct ip2k_opcode ip2k_add_w_wreg_opcode[] = { - {0x1C0A, 0xFFFF}, /* add w,wreg */ - {0x1E0A, 0xFFFF}, /* add wreg,w */ + {0x1C0A, 0xFFFF}, /* Add w,wreg. */ + {0x1E0A, 0xFFFF}, /* Add wreg,w. */ {0x0000, 0x0000}, }; @@ -146,7 +100,7 @@ static const struct ip2k_opcode ip2k_add static const struct ip2k_opcode ip2k_add_pcl_w_opcode[] = { - {0x1E09, 0xFFFF}, /* add pcl,w */ + {0x1E09, 0xFFFF}, /* Add pcl,w. */ {0x0000, 0x0000}, }; @@ -220,10 +174,10 @@ static reloc_howto_type ip2k_elf_howto_t /* Map BFD reloc types to IP2K ELF reloc types. */ + static reloc_howto_type * -ip2k_reloc_type_lookup (abfd, code) - bfd * abfd ATTRIBUTE_UNUSED; - bfd_reloc_code_real_type code; +ip2k_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) { /* Note that the ip2k_elf_howto_table is indxed by the R_ constants. Thus, the order that the howto records appear in the @@ -270,20 +224,17 @@ ip2k_reloc_type_lookup (abfd, code) } static void -ip2k_get_mem (abfd, addr, length, ptr) - bfd *abfd ATTRIBUTE_UNUSED; - bfd_byte *addr; - int length; - bfd_byte *ptr; +ip2k_get_mem (bfd *abfd ATTRIBUTE_UNUSED, + bfd_byte *addr, + int length, + bfd_byte *ptr) { while (length --) * ptr ++ = bfd_get_8 (abfd, addr ++); } static bfd_boolean -ip2k_is_opcode (code, opcodes) - bfd_byte *code; - const struct ip2k_opcode *opcodes; +ip2k_is_opcode (bfd_byte *code, const struct ip2k_opcode *opcodes) { unsigned short insn = (code[0] << 8) | code[1]; @@ -306,11 +257,10 @@ ip2k_is_opcode (code, opcodes) /* Return the value of the symbol associated with the relocation IREL. */ static bfd_vma -symbol_value (abfd, symtab_hdr, isymbuf, irel) - bfd *abfd; - Elf_Internal_Shdr *symtab_hdr; - Elf_Internal_Sym *isymbuf; - Elf_Internal_Rela *irel; +symbol_value (bfd *abfd, + Elf_Internal_Shdr *symtab_hdr, + Elf_Internal_Sym *isymbuf, + Elf_Internal_Rela *irel) { if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info) { @@ -346,115 +296,6 @@ symbol_value (abfd, symtab_hdr, isymbuf, } } -/* Returns the expected page state for the given instruction not including - the effect of page instructions. */ - -static bfd_vma -ip2k_nominal_page_bits (abfd, sec, addr, contents) - bfd *abfd ATTRIBUTE_UNUSED; - asection *sec; - bfd_vma addr; - bfd_byte *contents; -{ - bfd_vma page = PAGENO (BASEADDR (sec) + addr); - - /* Check if section flows into this page. If not then the page - bits are assumed to match the PC. This will be true unless - the user has a page instruction without a call/jump, in which - case they are on their own. */ - if (PAGENO (BASEADDR (sec)) == page) - return page; - - /* Section flows across page boundary. The page bits should match - the PC unless there is a possible flow from the previous page, - in which case it is not possible to determine the value of the - page bits. */ - while (PAGENO (BASEADDR (sec) + addr - 2) == page) - { - bfd_byte code[2]; - - addr -= 2; - ip2k_get_mem (abfd, contents + addr, 2, code); - if (!IS_PAGE_OPCODE (code)) - continue; - - /* Found a page instruction, check if jump table. */ - if (ip2k_is_switch_table_128 (abfd, sec, addr, contents) != -1) - /* Jump table => page is conditional. */ - continue; - - if (ip2k_is_switch_table_256 (abfd, sec, addr, contents) != -1) - /* Jump table => page is conditional. */ - continue; - - /* Found a page instruction, check if conditional. */ - if (addr >= 2) - { - ip2k_get_mem (abfd, contents + addr - 2, 2, code); - if (IS_SKIP_OPCODE (code)) - /* Page is conditional. */ - continue; - } - - /* Unconditional page instruction => page bits should be correct. */ - return page; - } - - /* Flow from previous page => page bits are impossible to determine. */ - return 0; -} - -static bfd_boolean -ip2k_test_page_insn (abfd, sec, irel, misc) - bfd *abfd ATTRIBUTE_UNUSED; - asection *sec; - Elf_Internal_Rela *irel; - struct misc *misc; -{ - bfd_vma symval; - - /* Get the value of the symbol referred to by the reloc. */ - symval = symbol_value (abfd, misc->symtab_hdr, misc->isymbuf, irel); - if (symval == UNDEFINED_SYMBOL) - /* This appears to be a reference to an undefined - symbol. Just ignore it--it will be caught by the - regular reloc processing. */ - return FALSE; - - /* Test if we can delete this page instruction. */ - if (PAGENO (symval + irel->r_addend) != - ip2k_nominal_page_bits (abfd, sec, irel->r_offset, misc->contents)) - return FALSE; - - return TRUE; -} - -static bfd_boolean -ip2k_delete_page_insn (abfd, sec, irel, again, misc) - bfd *abfd ATTRIBUTE_UNUSED; - asection *sec; - Elf_Internal_Rela *irel; - bfd_boolean *again; - struct misc *misc; -{ - /* Note that we've changed the relocs, section contents, etc. */ - elf_section_data (sec)->relocs = misc->irelbase; - elf_section_data (sec)->this_hdr.contents = misc->contents; - misc->symtab_hdr->contents = (bfd_byte *) misc->isymbuf; - - /* Fix the relocation's type. */ - irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), R_IP2K_NONE); - - /* Delete the PAGE insn. */ - if (!ip2k_elf_relax_delete_bytes (abfd, sec, irel->r_offset, 2)) - return FALSE; - - /* Modified => will need to iterate relaxation again. */ - *again = TRUE; - - return TRUE; -} - /* Determine if the instruction sequence matches that for the prologue of a switch dispatch table with fewer than 128 entries. @@ -485,11 +326,10 @@ ip2k_delete_page_insn (abfd, sec, irel, jmp $nnnN */ static int -ip2k_is_switch_table_128 (abfd, sec, addr, contents) - bfd *abfd ATTRIBUTE_UNUSED; - asection *sec; - bfd_vma addr; - bfd_byte *contents; +ip2k_is_switch_table_128 (bfd *abfd ATTRIBUTE_UNUSED, + asection *sec, + bfd_vma addr, + bfd_byte *contents) { bfd_byte code[4]; int index = 0; @@ -525,78 +365,6 @@ ip2k_is_switch_table_128 (abfd, sec, add } } -static bfd_boolean -ip2k_relax_switch_table_128 (abfd, sec, irel, again, misc) - bfd *abfd ATTRIBUTE_UNUSED; - asection *sec; - Elf_Internal_Rela *irel; - bfd_boolean *again; - struct misc *misc; -{ - Elf_Internal_Rela *irelend = misc->irelbase + sec->reloc_count; - Elf_Internal_Rela *ireltest = irel; - bfd_byte code[4]; - bfd_vma addr; - - /* Test all page instructions. */ - addr = irel->r_offset; - while (1) - { - if (addr + 4 > sec->size) - break; - - ip2k_get_mem (abfd, misc->contents + addr, 4, code); - if ((! IS_PAGE_OPCODE (code + 0)) - || (! IS_JMP_OPCODE (code + 2))) - break; - - /* Validate relocation entry (every entry should have a matching - relocation entry). */ - if (ireltest >= irelend) - { - _bfd_error_handler (_("ip2k relaxer: switch table without complete matching relocation information.")); - return FALSE; - } - - if (ireltest->r_offset != addr) - { - _bfd_error_handler (_("ip2k relaxer: switch table without complete matching relocation information.")); - return FALSE; - } - - if (! ip2k_test_page_insn (abfd, sec, ireltest, misc)) - /* Un-removable page insn => nothing can be done. */ - return TRUE; - - addr += 4; - ireltest += 2; - } - - /* Relaxable. Adjust table header. */ - ip2k_get_mem (abfd, misc->contents + irel->r_offset - 4, 4, code); - if ((! IS_ADD_W_WREG_OPCODE (code + 0)) - || (! IS_ADD_PCL_W_OPCODE (code + 2))) - { - _bfd_error_handler (_("ip2k relaxer: switch table header corrupt.")); - return FALSE; - } - - if (!ip2k_elf_relax_delete_bytes (abfd, sec, irel->r_offset - 4, 2)) - return FALSE; - - *again = TRUE; - - /* Delete all page instructions in table. */ - while (irel < ireltest) - { - if (!ip2k_delete_page_insn (abfd, sec, irel, again, misc)) - return FALSE; - irel += 2; - } - - return TRUE; -} - /* Determine if the instruction sequence matches that for the prologue switch dispatch table with fewer than 256 entries but more than 127. @@ -638,11 +406,10 @@ ip2k_relax_switch_table_128 (abfd, sec, jmp $nnnN */ static int -ip2k_is_switch_table_256 (abfd, sec, addr, contents) - bfd *abfd ATTRIBUTE_UNUSED; - asection *sec; - bfd_vma addr; - bfd_byte *contents; +ip2k_is_switch_table_256 (bfd *abfd ATTRIBUTE_UNUSED, + asection *sec, + bfd_vma addr, + bfd_byte *contents) { bfd_byte code[16]; int index = 0; @@ -692,297 +459,533 @@ ip2k_is_switch_table_256 (abfd, sec, add } } -static bfd_boolean -ip2k_relax_switch_table_256 (abfd, sec, irel, again, misc) - bfd *abfd ATTRIBUTE_UNUSED; - asection *sec; - Elf_Internal_Rela *irel; - bfd_boolean *again; - struct misc *misc; +/* Returns the expected page state for the given instruction not including + the effect of page instructions. */ + +static bfd_vma +ip2k_nominal_page_bits (bfd *abfd ATTRIBUTE_UNUSED, + asection *sec, + bfd_vma addr, + bfd_byte *contents) { - Elf_Internal_Rela *irelend = misc->irelbase + sec->reloc_count; - Elf_Internal_Rela *ireltest = irel; - bfd_byte code[12]; - bfd_vma addr; - - /* Test all page instructions. */ - addr = irel->r_offset; + bfd_vma page = PAGENO (BASEADDR (sec) + addr); - while (1) + /* Check if section flows into this page. If not then the page + bits are assumed to match the PC. This will be true unless + the user has a page instruction without a call/jump, in which + case they are on their own. */ + if (PAGENO (BASEADDR (sec)) == page) + return page; + + /* Section flows across page boundary. The page bits should match + the PC unless there is a possible flow from the previous page, + in which case it is not possible to determine the value of the + page bits. */ + while (PAGENO (BASEADDR (sec) + addr - 2) == page) { - if (addr + 4 > sec->size) - break; + bfd_byte code[2]; - ip2k_get_mem (abfd, misc->contents + addr, 4, code); + addr -= 2; + ip2k_get_mem (abfd, contents + addr, 2, code); + if (!IS_PAGE_OPCODE (code)) + continue; - if ((! IS_PAGE_OPCODE (code + 0)) - || (! IS_JMP_OPCODE (code + 2))) - break; + /* Found a page instruction, check if jump table. */ + if (ip2k_is_switch_table_128 (abfd, sec, addr, contents) != -1) + /* Jump table => page is conditional. */ + continue; - /* Validate relocation entry (every entry should have a matching - relocation entry). */ - if (ireltest >= irelend) - { - _bfd_error_handler (_("ip2k relaxer: switch table without complete matching relocation information.")); - return FALSE; - } + if (ip2k_is_switch_table_256 (abfd, sec, addr, contents) != -1) + /* Jump table => page is conditional. */ + continue; - if (ireltest->r_offset != addr) + /* Found a page instruction, check if conditional. */ + if (addr >= 2) { - _bfd_error_handler (_("ip2k relaxer: switch table without complete matching relocation information.")); - return FALSE; + ip2k_get_mem (abfd, contents + addr - 2, 2, code); + if (IS_SKIP_OPCODE (code)) + /* Page is conditional. */ + continue; } - if (!ip2k_test_page_insn (abfd, sec, ireltest, misc)) - /* Un-removable page insn => nothing can be done. */ - return TRUE; - - addr += 4; - ireltest += 2; + /* Unconditional page instruction => page bits should be correct. */ + return page; } - /* Relaxable. Adjust table header. */ - ip2k_get_mem (abfd, misc->contents + irel->r_offset - 4, 2, code); - if (IS_PAGE_OPCODE (code)) - addr = irel->r_offset - 16; - else - addr = irel->r_offset - 14; - - ip2k_get_mem (abfd, misc->contents + addr, 12, code); - if ((!IS_ADD_W_WREG_OPCODE (code + 0)) - || (!IS_SNC_OPCODE (code + 2)) - || (!IS_INC_1SP_OPCODE (code + 4)) - || (!IS_ADD_2SP_W_OPCODE (code + 6)) - || (!IS_SNC_OPCODE (code + 8)) - || (!IS_INC_1SP_OPCODE (code + 10))) - { - _bfd_error_handler (_("ip2k relaxer: switch table header corrupt.")); - return FALSE; - } + /* Flow from previous page => page bits are impossible to determine. */ + return 0; +} - /* Delete first 3 opcodes. */ - if (!ip2k_elf_relax_delete_bytes (abfd, sec, addr + 0, 6)) - return FALSE; +static bfd_boolean +ip2k_test_page_insn (bfd *abfd ATTRIBUTE_UNUSED, + asection *sec, + Elf_Internal_Rela *irel, + struct misc *misc) +{ + bfd_vma symval; - *again = TRUE; + /* Get the value of the symbol referred to by the reloc. */ + symval = symbol_value (abfd, misc->symtab_hdr, misc->isymbuf, irel); + if (symval == UNDEFINED_SYMBOL) + /* This appears to be a reference to an undefined + symbol. Just ignore it--it will be caught by the + regular reloc processing. */ + return FALSE; - /* Delete all page instructions in table. */ - while (irel < ireltest) - { - if (!ip2k_delete_page_insn (abfd, sec, irel, again, misc)) - return FALSE; - irel += 2; - } + /* Test if we can delete this page instruction. */ + if (PAGENO (symval + irel->r_addend) != + ip2k_nominal_page_bits (abfd, sec, irel->r_offset, misc->contents)) + return FALSE; return TRUE; } -/* This function handles relaxing for the ip2k. +/* Parts of a Stabs entry. */ - Principle: Start with the first page and remove page instructions that - are not require on this first page. By removing page instructions more - code will fit into this page - repeat until nothing more can be achieved - for this page. Move on to the next page. +#define STRDXOFF 0 +#define TYPEOFF 4 +#define OTHEROFF 5 +#define DESCOFF 6 +#define VALOFF 8 +#define STABSIZE 12 - Processing the pages one at a time from the lowest page allows a removal - only policy to be used - pages can be removed but are never reinserted. */ +/* Adjust all the relocations entries after adding or inserting instructions. */ -static bfd_boolean -ip2k_elf_relax_section (abfd, sec, link_info, again) - bfd *abfd; - asection *sec; - struct bfd_link_info *link_info; - bfd_boolean *again; +static void +adjust_all_relocations (bfd *abfd, + asection *sec, + bfd_vma addr, + bfd_vma endaddr, + int count, + int noadj) { Elf_Internal_Shdr *symtab_hdr; - Elf_Internal_Rela *internal_relocs; - bfd_byte *contents = NULL; - Elf_Internal_Sym *isymbuf = NULL; - static asection * first_section = NULL; - static unsigned long search_addr; - static unsigned long page_start = 0; - static unsigned long page_end = 0; - static unsigned int pass = 0; - static bfd_boolean new_pass = FALSE; - static bfd_boolean changed = FALSE; - struct misc misc; + Elf_Internal_Sym *isymbuf, *isym, *isymend; + unsigned int shndx; + bfd_byte *contents; + Elf_Internal_Rela *irel, *irelend, *irelbase; + struct elf_link_hash_entry **sym_hashes; + struct elf_link_hash_entry **end_hashes; + unsigned int symcount; asection *stab; - /* Assume nothing changes. */ - *again = FALSE; + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; - if (first_section == NULL) - { - ip2k_relaxed = TRUE; - first_section = sec; - } + shndx = _bfd_elf_section_from_bfd_section (abfd, sec); - if (first_section == sec) + contents = elf_section_data (sec)->this_hdr.contents; + + irelbase = elf_section_data (sec)->relocs; + irelend = irelbase + sec->reloc_count; + + for (irel = irelbase; irel < irelend; irel++) { - pass++; - new_pass = TRUE; - } + if (ELF32_R_TYPE (irel->r_info) != R_IP2K_NONE) + { + /* Get the value of the symbol referred to by the reloc. */ + if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info) + { + asection *sym_sec; - /* We don't have to do anything for a relocatable link, - if this section does not have relocs, or if this is - not a code section. */ - if (link_info->relocatable - || (sec->flags & SEC_RELOC) == 0 - || sec->reloc_count == 0 - || (sec->flags & SEC_CODE) == 0) - return TRUE; + /* A local symbol. */ + isym = isymbuf + ELF32_R_SYM (irel->r_info); + sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx); - symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + if (isym->st_shndx == shndx) + { + bfd_vma baseaddr = BASEADDR (sec); + bfd_vma symval = BASEADDR (sym_sec) + isym->st_value + + irel->r_addend; - internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, - (Elf_Internal_Rela *)NULL, - link_info->keep_memory); - if (internal_relocs == NULL) - goto error_return; + if ((baseaddr + addr + noadj) <= symval + && symval < (baseaddr + endaddr)) + irel->r_addend += count; + } + } + } - /* Make sure the stac.rela stuff gets read in. */ - stab = bfd_get_section_by_name (abfd, ".stab"); + /* Do this only for PC space relocations. */ + if (addr <= irel->r_offset && irel->r_offset < endaddr) + irel->r_offset += count; + } + /* Now fix the stab relocations. */ + stab = bfd_get_section_by_name (abfd, ".stab"); if (stab) { - /* So stab does exits. */ - Elf_Internal_Rela * irelbase; + bfd_byte *stabcontents, *stabend, *stabp; + bfd_size_type stab_size = stab->rawsize ? stab->rawsize : stab->size; - irelbase = _bfd_elf_link_read_relocs (abfd, stab, NULL, - (Elf_Internal_Rela *)NULL, - link_info->keep_memory); + irelbase = elf_section_data (stab)->relocs; + irelend = irelbase + stab->reloc_count; + + /* Pull out the contents of the stab section. */ + if (elf_section_data (stab)->this_hdr.contents != NULL) + stabcontents = elf_section_data (stab)->this_hdr.contents; + else + { + if (!bfd_malloc_and_get_section (abfd, stab, &stabcontents)) + { + if (stabcontents != NULL) + free (stabcontents); + return; + } + + /* We need to remember this. */ + elf_section_data (stab)->this_hdr.contents = stabcontents; + } + + stabend = stabcontents + stab_size; + + for (irel = irelbase; irel < irelend; irel++) + { + if (ELF32_R_TYPE (irel->r_info) != R_IP2K_NONE) + { + /* Get the value of the symbol referred to by the reloc. */ + if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info) + { + asection *sym_sec; + + /* A local symbol. */ + isym = isymbuf + ELF32_R_SYM (irel->r_info); + sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx); + + if (sym_sec == sec) + { + const char *name; + unsigned long strx; + unsigned char type, other; + unsigned short desc; + bfd_vma value; + bfd_vma baseaddr = BASEADDR (sec); + bfd_vma symval = BASEADDR (sym_sec) + isym->st_value + + irel->r_addend; + + if ((baseaddr + addr) <= symval + && symval <= (baseaddr + endaddr)) + irel->r_addend += count; + + /* Go hunt up a function and fix its line info if needed. */ + stabp = stabcontents + irel->r_offset - 8; + + /* Go pullout the stab entry. */ + strx = bfd_h_get_32 (abfd, stabp + STRDXOFF); + type = bfd_h_get_8 (abfd, stabp + TYPEOFF); + other = bfd_h_get_8 (abfd, stabp + OTHEROFF); + desc = bfd_h_get_16 (abfd, stabp + DESCOFF); + value = bfd_h_get_32 (abfd, stabp + VALOFF); + + name = bfd_get_stab_name (type); + + if (strcmp (name, "FUN") == 0) + { + int function_adjusted = 0; + + if (symval > (baseaddr + addr)) + /* Not in this function. */ + continue; + + /* Hey we got a function hit. */ + stabp += STABSIZE; + for (;stabp < stabend; stabp += STABSIZE) + { + /* Go pullout the stab entry. */ + strx = bfd_h_get_32 (abfd, stabp + STRDXOFF); + type = bfd_h_get_8 (abfd, stabp + TYPEOFF); + other = bfd_h_get_8 (abfd, stabp + OTHEROFF); + desc = bfd_h_get_16 (abfd, stabp + DESCOFF); + value = bfd_h_get_32 (abfd, stabp + VALOFF); + + name = bfd_get_stab_name (type); + + if (strcmp (name, "FUN") == 0) + { + /* Hit another function entry. */ + if (function_adjusted) + { + /* Adjust the value. */ + value += count; + + /* We need to put it back. */ + bfd_h_put_32 (abfd, value,stabp + VALOFF); + } + + /* And then bale out. */ + break; + } + + if (strcmp (name, "SLINE") == 0) + { + /* Got a line entry. */ + if ((baseaddr + addr) <= (symval + value)) + { + /* Adjust the line entry. */ + value += count; + + /* We need to put it back. */ + bfd_h_put_32 (abfd, value,stabp + VALOFF); + function_adjusted = 1; + } + } + } + } + } + } + } + } } - /* Get section contents cached copy if it exists. */ - if (contents == NULL) + /* When adding an instruction back it is sometimes necessary to move any + global or local symbol that was referencing the first instruction of + the moved block to refer to the first instruction of the inserted block. + + For example adding a PAGE instruction before a CALL or JMP requires + that any label on the CALL or JMP is moved to the PAGE insn. */ + addr += noadj; + + /* Adjust the local symbols defined in this section. */ + isymend = isymbuf + symtab_hdr->sh_info; + for (isym = isymbuf; isym < isymend; isym++) { - /* Get cached copy if it exists. */ - if (elf_section_data (sec)->this_hdr.contents != NULL) - contents = elf_section_data (sec)->this_hdr.contents; - else + if (isym->st_shndx == shndx + && addr <= isym->st_value + && isym->st_value < endaddr) + isym->st_value += count; + } + + /* Now adjust the global symbols defined in this section. */ + symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym) + - symtab_hdr->sh_info); + sym_hashes = elf_sym_hashes (abfd); + end_hashes = sym_hashes + symcount; + for (; sym_hashes < end_hashes; sym_hashes++) + { + struct elf_link_hash_entry *sym_hash = *sym_hashes; + + if ((sym_hash->root.type == bfd_link_hash_defined + || sym_hash->root.type == bfd_link_hash_defweak) + && sym_hash->root.u.def.section == sec) { - /* Go get them off disk. */ - if (!bfd_malloc_and_get_section (abfd, sec, &contents)) - goto error_return; + if (addr <= sym_hash->root.u.def.value + && sym_hash->root.u.def.value < endaddr) + sym_hash->root.u.def.value += count; } } - /* Read this BFD's symbols cached copy if it exists. */ - if (isymbuf == NULL && symtab_hdr->sh_info != 0) + return; +} + +/* Delete some bytes from a section while relaxing. */ + +static bfd_boolean +ip2k_elf_relax_delete_bytes (bfd *abfd, + asection *sec, + bfd_vma addr, + int count) +{ + bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; + bfd_vma endaddr = sec->size; + + /* Actually delete the bytes. */ + memmove (contents + addr, contents + addr + count, + endaddr - addr - count); + + sec->size -= count; + + adjust_all_relocations (abfd, sec, addr + count, endaddr, -count, 0); + return TRUE; +} + +static bfd_boolean +ip2k_delete_page_insn (bfd *abfd ATTRIBUTE_UNUSED, + asection *sec, + Elf_Internal_Rela *irel, + bfd_boolean *again, + struct misc *misc) +{ + /* Note that we've changed the relocs, section contents, etc. */ + elf_section_data (sec)->relocs = misc->irelbase; + elf_section_data (sec)->this_hdr.contents = misc->contents; + misc->symtab_hdr->contents = (bfd_byte *) misc->isymbuf; + + /* Fix the relocation's type. */ + irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), R_IP2K_NONE); + + /* Delete the PAGE insn. */ + if (!ip2k_elf_relax_delete_bytes (abfd, sec, irel->r_offset, 2)) + return FALSE; + + /* Modified => will need to iterate relaxation again. */ + *again = TRUE; + + return TRUE; +} + +static bfd_boolean +ip2k_relax_switch_table_128 (bfd *abfd ATTRIBUTE_UNUSED, + asection *sec, + Elf_Internal_Rela *irel, + bfd_boolean *again, + struct misc *misc) +{ + Elf_Internal_Rela *irelend = misc->irelbase + sec->reloc_count; + Elf_Internal_Rela *ireltest = irel; + bfd_byte code[4]; + bfd_vma addr; + + /* Test all page instructions. */ + addr = irel->r_offset; + while (1) + { + if (addr + 4 > sec->size) + break; + + ip2k_get_mem (abfd, misc->contents + addr, 4, code); + if ((! IS_PAGE_OPCODE (code + 0)) + || (! IS_JMP_OPCODE (code + 2))) + break; + + /* Validate relocation entry (every entry should have a matching + relocation entry). */ + if (ireltest >= irelend) + { + _bfd_error_handler (_("ip2k relaxer: switch table without complete matching relocation information.")); + return FALSE; + } + + if (ireltest->r_offset != addr) + { + _bfd_error_handler (_("ip2k relaxer: switch table without complete matching relocation information.")); + return FALSE; + } + + if (! ip2k_test_page_insn (abfd, sec, ireltest, misc)) + /* Un-removable page insn => nothing can be done. */ + return TRUE; + + addr += 4; + ireltest += 2; + } + + /* Relaxable. Adjust table header. */ + ip2k_get_mem (abfd, misc->contents + irel->r_offset - 4, 4, code); + if ((! IS_ADD_W_WREG_OPCODE (code + 0)) + || (! IS_ADD_PCL_W_OPCODE (code + 2))) + { + _bfd_error_handler (_("ip2k relaxer: switch table header corrupt.")); + return FALSE; + } + + if (!ip2k_elf_relax_delete_bytes (abfd, sec, irel->r_offset - 4, 2)) + return FALSE; + + *again = TRUE; + + /* Delete all page instructions in table. */ + while (irel < ireltest) + { + if (!ip2k_delete_page_insn (abfd, sec, irel, again, misc)) + return FALSE; + irel += 2; + } + + return TRUE; +} + +static bfd_boolean +ip2k_relax_switch_table_256 (bfd *abfd ATTRIBUTE_UNUSED, + asection *sec, + Elf_Internal_Rela *irel, + bfd_boolean *again, + struct misc *misc) +{ + Elf_Internal_Rela *irelend = misc->irelbase + sec->reloc_count; + Elf_Internal_Rela *ireltest = irel; + bfd_byte code[12]; + bfd_vma addr; + + /* Test all page instructions. */ + addr = irel->r_offset; + + while (1) { - isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; - if (isymbuf == NULL) - isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, - symtab_hdr->sh_info, 0, - NULL, NULL, NULL); - if (isymbuf == NULL) - goto error_return; - } + if (addr + 4 > sec->size) + break; - misc.symtab_hdr = symtab_hdr; - misc.isymbuf = isymbuf; - misc.irelbase = internal_relocs; - misc.contents = contents; + ip2k_get_mem (abfd, misc->contents + addr, 4, code); - /* This is where all the relaxation actually get done. */ - if ((pass == 1) || (new_pass && !changed)) - { - /* On the first pass we simply search for the lowest page that - we havn't relaxed yet. Note that the pass count is reset - each time a page is complete in order to move on to the next page. - If we can't find any more pages then we are finished. */ - if (new_pass) - { - pass = 1; - new_pass = FALSE; - changed = TRUE; /* Pre-initialize to break out of pass 1. */ - search_addr = 0xFFFFFFFF; - } + if ((! IS_PAGE_OPCODE (code + 0)) + || (! IS_JMP_OPCODE (code + 2))) + break; - if ((BASEADDR (sec) + sec->size < search_addr) - && (BASEADDR (sec) + sec->size > page_end)) - { - if (BASEADDR (sec) <= page_end) - search_addr = page_end + 1; - else - search_addr = BASEADDR (sec); + /* Validate relocation entry (every entry should have a matching + relocation entry). */ + if (ireltest >= irelend) + { + _bfd_error_handler (_("ip2k relaxer: switch table without complete matching relocation information.")); + return FALSE; + } - /* Found a page => more work to do. */ - *again = TRUE; - } - } - else - { - if (new_pass) - { - new_pass = FALSE; - changed = FALSE; - page_start = PAGENO (search_addr); - page_end = page_start | 0x00003FFF; - } + if (ireltest->r_offset != addr) + { + _bfd_error_handler (_("ip2k relaxer: switch table without complete matching relocation information.")); + return FALSE; + } - /* Only process sections in range. */ - if ((BASEADDR (sec) + sec->size >= page_start) - && (BASEADDR (sec) <= page_end)) - { - if (!ip2k_elf_relax_section_page (abfd, sec, &changed, &misc, page_start, page_end)) - return FALSE; - } - *again = TRUE; + if (!ip2k_test_page_insn (abfd, sec, ireltest, misc)) + /* Un-removable page insn => nothing can be done. */ + return TRUE; + + addr += 4; + ireltest += 2; } - /* Perform some house keeping after relaxing the section. */ + /* Relaxable. Adjust table header. */ + ip2k_get_mem (abfd, misc->contents + irel->r_offset - 4, 2, code); + if (IS_PAGE_OPCODE (code)) + addr = irel->r_offset - 16; + else + addr = irel->r_offset - 14; - if (isymbuf != NULL - && symtab_hdr->contents != (unsigned char *) isymbuf) + ip2k_get_mem (abfd, misc->contents + addr, 12, code); + if ((!IS_ADD_W_WREG_OPCODE (code + 0)) + || (!IS_SNC_OPCODE (code + 2)) + || (!IS_INC_1SP_OPCODE (code + 4)) + || (!IS_ADD_2SP_W_OPCODE (code + 6)) + || (!IS_SNC_OPCODE (code + 8)) + || (!IS_INC_1SP_OPCODE (code + 10))) { - if (! link_info->keep_memory) - free (isymbuf); - else - symtab_hdr->contents = (unsigned char *) isymbuf; + _bfd_error_handler (_("ip2k relaxer: switch table header corrupt.")); + return FALSE; } - if (contents != NULL - && elf_section_data (sec)->this_hdr.contents != contents) + /* Delete first 3 opcodes. */ + if (!ip2k_elf_relax_delete_bytes (abfd, sec, addr + 0, 6)) + return FALSE; + + *again = TRUE; + + /* Delete all page instructions in table. */ + while (irel < ireltest) { - if (! link_info->keep_memory) - free (contents); - else - { - /* Cache the section contents for elf_link_input_bfd. */ - elf_section_data (sec)->this_hdr.contents = contents; - } + if (!ip2k_delete_page_insn (abfd, sec, irel, again, misc)) + return FALSE; + irel += 2; } - if (internal_relocs != NULL - && elf_section_data (sec)->relocs != internal_relocs) - free (internal_relocs); - return TRUE; - - error_return: - if (isymbuf != NULL - && symtab_hdr->contents != (unsigned char *) isymbuf) - free (isymbuf); - if (contents != NULL - && elf_section_data (sec)->this_hdr.contents != contents) - free (contents); - if (internal_relocs != NULL - && elf_section_data (sec)->relocs != internal_relocs) - free (internal_relocs); - return FALSE; } /* This function handles relaxation of a section in a specific page. */ static bfd_boolean -ip2k_elf_relax_section_page (abfd, sec, again, misc, page_start, page_end) - bfd *abfd; - asection *sec; - bfd_boolean *again; - struct misc *misc; - unsigned long page_start; - unsigned long page_end; +ip2k_elf_relax_section_page (bfd *abfd, + asection *sec, + bfd_boolean *again, + struct misc *misc, + unsigned long page_start, + unsigned long page_end) { Elf_Internal_Rela *irelend = misc->irelbase + sec->reloc_count; Elf_Internal_Rela *irel; @@ -1043,301 +1046,222 @@ ip2k_elf_relax_section_page (abfd, sec, return TRUE; } -/* Parts of a Stabs entry. */ - -#define STRDXOFF (0) -#define TYPEOFF (4) -#define OTHEROFF (5) -#define DESCOFF (6) -#define VALOFF (8) -#define STABSIZE (12) - -/* Adjust all the relocations entries after adding or inserting instructions. */ - -static void -adjust_all_relocations (abfd, sec, addr, endaddr, count, noadj) - bfd *abfd; - asection *sec; - bfd_vma addr; - bfd_vma endaddr; - int count; - int noadj; -{ - Elf_Internal_Shdr *symtab_hdr; - Elf_Internal_Sym *isymbuf, *isym, *isymend; - unsigned int shndx; - bfd_byte *contents; - Elf_Internal_Rela *irel, *irelend, *irelbase; - struct elf_link_hash_entry **sym_hashes; - struct elf_link_hash_entry **end_hashes; - unsigned int symcount; - asection *stab; - - symtab_hdr = &elf_tdata (abfd)->symtab_hdr; - isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; - - shndx = _bfd_elf_section_from_bfd_section (abfd, sec); - - contents = elf_section_data (sec)->this_hdr.contents; - - irelbase = elf_section_data (sec)->relocs; - irelend = irelbase + sec->reloc_count; - - for (irel = irelbase; irel < irelend; irel++) - { - if (ELF32_R_TYPE (irel->r_info) != R_IP2K_NONE) - { - /* Get the value of the symbol referred to by the reloc. */ - if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info) - { - asection *sym_sec; - - /* A local symbol. */ - isym = isymbuf + ELF32_R_SYM (irel->r_info); - sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx); - - if (isym->st_shndx == shndx) - { - bfd_vma baseaddr = BASEADDR (sec); - bfd_vma symval = BASEADDR (sym_sec) + isym->st_value - + irel->r_addend; - - if ((baseaddr + addr + noadj) <= symval - && symval < (baseaddr + endaddr)) - irel->r_addend += count; - } - } - } - - /* Do this only for PC space relocations. */ - if (addr <= irel->r_offset && irel->r_offset < endaddr) - irel->r_offset += count; - } - - /* Now fix the stab relocations. */ - stab = bfd_get_section_by_name (abfd, ".stab"); - if (stab) - { - bfd_byte *stabcontents, *stabend, *stabp; - bfd_size_type stab_size = stab->rawsize ? stab->rawsize : stab->size; - - irelbase = elf_section_data (stab)->relocs; - irelend = irelbase + stab->reloc_count; - - /* Pull out the contents of the stab section. */ - if (elf_section_data (stab)->this_hdr.contents != NULL) - stabcontents = elf_section_data (stab)->this_hdr.contents; - else - { - if (!bfd_malloc_and_get_section (abfd, stab, &stabcontents)) - { - if (stabcontents != NULL) - free (stabcontents); - return; - } - - /* We need to remember this. */ - elf_section_data (stab)->this_hdr.contents = stabcontents; - } - - stabend = stabcontents + stab_size; +/* This function handles relaxing for the ip2k. - for (irel = irelbase; irel < irelend; irel++) - { - if (ELF32_R_TYPE (irel->r_info) != R_IP2K_NONE) - { - /* Get the value of the symbol referred to by the reloc. */ - if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info) - { - asection *sym_sec; - - /* A local symbol. */ - isym = isymbuf + ELF32_R_SYM (irel->r_info); - sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx); - - if (sym_sec == sec) - { - const char *name; - unsigned long strx; - unsigned char type, other; - unsigned short desc; - bfd_vma value; - bfd_vma baseaddr = BASEADDR (sec); - bfd_vma symval = BASEADDR (sym_sec) + isym->st_value - + irel->r_addend; - - if ((baseaddr + addr) <= symval - && symval <= (baseaddr + endaddr)) - irel->r_addend += count; + Principle: Start with the first page and remove page instructions that + are not require on this first page. By removing page instructions more + code will fit into this page - repeat until nothing more can be achieved + for this page. Move on to the next page. - /* Go hunt up a function and fix its line info if needed. */ - stabp = stabcontents + irel->r_offset - 8; + Processing the pages one at a time from the lowest page allows a removal + only policy to be used - pages can be removed but are never reinserted. */ - /* Go pullout the stab entry. */ - strx = bfd_h_get_32 (abfd, stabp + STRDXOFF); - type = bfd_h_get_8 (abfd, stabp + TYPEOFF); - other = bfd_h_get_8 (abfd, stabp + OTHEROFF); - desc = bfd_h_get_16 (abfd, stabp + DESCOFF); - value = bfd_h_get_32 (abfd, stabp + VALOFF); - - name = bfd_get_stab_name (type); - - if (strcmp (name, "FUN") == 0) - { - int function_adjusted = 0; +static bfd_boolean +ip2k_elf_relax_section (bfd *abfd, + asection *sec, + struct bfd_link_info *link_info, + bfd_boolean *again) +{ + Elf_Internal_Shdr *symtab_hdr; + Elf_Internal_Rela *internal_relocs; + bfd_byte *contents = NULL; + Elf_Internal_Sym *isymbuf = NULL; + static asection * first_section = NULL; + static unsigned long search_addr; + static unsigned long page_start = 0; + static unsigned long page_end = 0; + static unsigned int pass = 0; + static bfd_boolean new_pass = FALSE; + static bfd_boolean changed = FALSE; + struct misc misc; + asection *stab; - if (symval > (baseaddr + addr)) - /* Not in this function. */ - continue; + /* Assume nothing changes. */ + *again = FALSE; - /* Hey we got a function hit. */ - stabp += STABSIZE; - for (;stabp < stabend; stabp += STABSIZE) - { - /* Go pullout the stab entry. */ - strx = bfd_h_get_32 (abfd, stabp + STRDXOFF); - type = bfd_h_get_8 (abfd, stabp + TYPEOFF); - other = bfd_h_get_8 (abfd, stabp + OTHEROFF); - desc = bfd_h_get_16 (abfd, stabp + DESCOFF); - value = bfd_h_get_32 (abfd, stabp + VALOFF); + if (first_section == NULL) + { + ip2k_relaxed = TRUE; + first_section = sec; + } - name = bfd_get_stab_name (type); + if (first_section == sec) + { + pass++; + new_pass = TRUE; + } - if (strcmp (name, "FUN") == 0) - { - /* Hit another function entry. */ - if (function_adjusted) - { - /* Adjust the value. */ - value += count; - - /* We need to put it back. */ - bfd_h_put_32 (abfd, value,stabp + VALOFF); - } + /* We don't have to do anything for a relocatable link, + if this section does not have relocs, or if this is + not a code section. */ + if (link_info->relocatable + || (sec->flags & SEC_RELOC) == 0 + || sec->reloc_count == 0 + || (sec->flags & SEC_CODE) == 0) + return TRUE; - /* And then bale out. */ - break; - } + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; - if (strcmp (name, "SLINE") == 0) - { - /* Got a line entry. */ - if ((baseaddr + addr) <= (symval + value)) - { - /* Adjust the line entry. */ - value += count; + internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, + link_info->keep_memory); + if (internal_relocs == NULL) + goto error_return; - /* We need to put it back. */ - bfd_h_put_32 (abfd, value,stabp + VALOFF); - function_adjusted = 1; - } - } - } - } - } - } - } - } - } + /* Make sure the stac.rela stuff gets read in. */ + stab = bfd_get_section_by_name (abfd, ".stab"); - /* When adding an instruction back it is sometimes necessary to move any - global or local symbol that was referencing the first instruction of - the moved block to refer to the first instruction of the inserted block. + if (stab) + { + /* So stab does exits. */ + Elf_Internal_Rela * irelbase; - For example adding a PAGE instruction before a CALL or JMP requires - that any label on the CALL or JMP is moved to the PAGE insn. */ - addr += noadj; + irelbase = _bfd_elf_link_read_relocs (abfd, stab, NULL, NULL, + link_info->keep_memory); + } - /* Adjust the local symbols defined in this section. */ - isymend = isymbuf + symtab_hdr->sh_info; - for (isym = isymbuf; isym < isymend; isym++) + /* Get section contents cached copy if it exists. */ + if (contents == NULL) { - if (isym->st_shndx == shndx - && addr <= isym->st_value - && isym->st_value < endaddr) - isym->st_value += count; + /* Get cached copy if it exists. */ + if (elf_section_data (sec)->this_hdr.contents != NULL) + contents = elf_section_data (sec)->this_hdr.contents; + else + { + /* Go get them off disk. */ + if (!bfd_malloc_and_get_section (abfd, sec, &contents)) + goto error_return; + } } - /* Now adjust the global symbols defined in this section. */ - symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym) - - symtab_hdr->sh_info); - sym_hashes = elf_sym_hashes (abfd); - end_hashes = sym_hashes + symcount; - for (; sym_hashes < end_hashes; sym_hashes++) + /* Read this BFD's symbols cached copy if it exists. */ + if (isymbuf == NULL && symtab_hdr->sh_info != 0) { - struct elf_link_hash_entry *sym_hash = *sym_hashes; + isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; + if (isymbuf == NULL) + isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, + symtab_hdr->sh_info, 0, + NULL, NULL, NULL); + if (isymbuf == NULL) + goto error_return; + } - if ((sym_hash->root.type == bfd_link_hash_defined - || sym_hash->root.type == bfd_link_hash_defweak) - && sym_hash->root.u.def.section == sec) + misc.symtab_hdr = symtab_hdr; + misc.isymbuf = isymbuf; + misc.irelbase = internal_relocs; + misc.contents = contents; + + /* This is where all the relaxation actually get done. */ + if ((pass == 1) || (new_pass && !changed)) + { + /* On the first pass we simply search for the lowest page that + we havn't relaxed yet. Note that the pass count is reset + each time a page is complete in order to move on to the next page. + If we can't find any more pages then we are finished. */ + if (new_pass) { - if (addr <= sym_hash->root.u.def.value - && sym_hash->root.u.def.value < endaddr) - sym_hash->root.u.def.value += count; + pass = 1; + new_pass = FALSE; + changed = TRUE; /* Pre-initialize to break out of pass 1. */ + search_addr = 0xFFFFFFFF; + } + + if ((BASEADDR (sec) + sec->size < search_addr) + && (BASEADDR (sec) + sec->size > page_end)) + { + if (BASEADDR (sec) <= page_end) + search_addr = page_end + 1; + else + search_addr = BASEADDR (sec); + + /* Found a page => more work to do. */ + *again = TRUE; } } + else + { + if (new_pass) + { + new_pass = FALSE; + changed = FALSE; + page_start = PAGENO (search_addr); + page_end = page_start | 0x00003FFF; + } - return; -} + /* Only process sections in range. */ + if ((BASEADDR (sec) + sec->size >= page_start) + && (BASEADDR (sec) <= page_end)) + { + if (!ip2k_elf_relax_section_page (abfd, sec, &changed, &misc, page_start, page_end)) + return FALSE; + } + *again = TRUE; + } -/* Delete some bytes from a section while relaxing. */ + /* Perform some house keeping after relaxing the section. */ -static bfd_boolean -ip2k_elf_relax_delete_bytes (abfd, sec, addr, count) - bfd *abfd; - asection *sec; - bfd_vma addr; - int count; -{ - bfd_byte *contents = elf_section_data (sec)->this_hdr.contents; - bfd_vma endaddr = sec->size; + if (isymbuf != NULL + && symtab_hdr->contents != (unsigned char *) isymbuf) + { + if (! link_info->keep_memory) + free (isymbuf); + else + symtab_hdr->contents = (unsigned char *) isymbuf; + } - /* Actually delete the bytes. */ - memmove (contents + addr, contents + addr + count, - endaddr - addr - count); + if (contents != NULL + && elf_section_data (sec)->this_hdr.contents != contents) + { + if (! link_info->keep_memory) + free (contents); + else + { + /* Cache the section contents for elf_link_input_bfd. */ + elf_section_data (sec)->this_hdr.contents = contents; + } + } - sec->size -= count; + if (internal_relocs != NULL + && elf_section_data (sec)->relocs != internal_relocs) + free (internal_relocs); - adjust_all_relocations (abfd, sec, addr + count, endaddr, -count, 0); return TRUE; -} - -/* -------------------------------------------------------------------- */ -/* XXX: The following code is the result of a cut&paste. This unfortunate - practice is very widespread in the various target back-end files. */ + error_return: + if (isymbuf != NULL + && symtab_hdr->contents != (unsigned char *) isymbuf) + free (isymbuf); + if (contents != NULL + && elf_section_data (sec)->this_hdr.contents != contents) + free (contents); + if (internal_relocs != NULL + && elf_section_data (sec)->relocs != internal_relocs) + free (internal_relocs); + return FALSE; +} /* Set the howto pointer for a IP2K ELF reloc. */ static void -ip2k_info_to_howto_rela (abfd, cache_ptr, dst) - bfd * abfd ATTRIBUTE_UNUSED; - arelent * cache_ptr; - Elf_Internal_Rela * dst; +ip2k_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED, + arelent * cache_ptr, + Elf_Internal_Rela * dst) { unsigned int r_type; r_type = ELF32_R_TYPE (dst->r_info); - switch (r_type) - { - default: - cache_ptr->howto = & ip2k_elf_howto_table [r_type]; - break; - } + cache_ptr->howto = & ip2k_elf_howto_table [r_type]; } /* Perform a single relocation. By default we use the standard BFD routines. */ static bfd_reloc_status_type -ip2k_final_link_relocate (howto, input_bfd, input_section, contents, rel, - relocation) - reloc_howto_type * howto; - bfd * input_bfd; - asection * input_section; - bfd_byte * contents; - Elf_Internal_Rela * rel; - bfd_vma relocation; +ip2k_final_link_relocate (reloc_howto_type * howto, + bfd * input_bfd, + asection * input_section, + bfd_byte * contents, + Elf_Internal_Rela * rel, + bfd_vma relocation) { static bfd_vma page_addr = 0; @@ -1383,11 +1307,13 @@ ip2k_final_link_relocate (howto, input_b /* Preceding page instruction. Verify that the page instruction is really needed. One reason for the relaxation to miss a page is if the section is not marked as executable. */ - if (!ip2k_is_switch_table_128 (input_bfd, input_section, rel->r_offset - 2, contents) && - !ip2k_is_switch_table_256 (input_bfd, input_section, rel->r_offset - 2, contents) && - (PAGENO (relocation + rel->r_addend) == - ip2k_nominal_page_bits (input_bfd, input_section, - rel->r_offset - 2, contents))) + if (!ip2k_is_switch_table_128 (input_bfd, input_section, + rel->r_offset - 2, contents) + && !ip2k_is_switch_table_256 (input_bfd, input_section, + rel->r_offset - 2, contents) + && (PAGENO (relocation + rel->r_addend) == + ip2k_nominal_page_bits (input_bfd, input_section, + rel->r_offset - 2, contents))) _bfd_error_handler (_("ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)."), page_addr, relocation + rel->r_addend); @@ -1459,16 +1385,14 @@ ip2k_final_link_relocate (howto, input_b accordingly. */ static bfd_boolean -ip2k_elf_relocate_section (output_bfd, info, input_bfd, input_section, - contents, relocs, local_syms, local_sections) - bfd *output_bfd ATTRIBUTE_UNUSED; - struct bfd_link_info *info; - bfd *input_bfd; - asection *input_section; - bfd_byte *contents; - Elf_Internal_Rela *relocs; - Elf_Internal_Sym *local_syms; - asection **local_sections; +ip2k_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info, + bfd *input_bfd, + asection *input_section, + bfd_byte *contents, + Elf_Internal_Rela *relocs, + Elf_Internal_Sym *local_syms, + asection **local_sections) { Elf_Internal_Shdr *symtab_hdr; struct elf_link_hash_entry **sym_hashes; @@ -1531,7 +1455,7 @@ ip2k_elf_relocate_section (output_bfd, i if (r != bfd_reloc_ok) { - const char * msg = (const char *) NULL; + const char * msg = NULL; switch (r) { @@ -1579,12 +1503,11 @@ ip2k_elf_relocate_section (output_bfd, i } static asection * -ip2k_elf_gc_mark_hook (sec, info, rel, h, sym) - asection *sec; - struct bfd_link_info *info ATTRIBUTE_UNUSED; - Elf_Internal_Rela *rel; - struct elf_link_hash_entry *h; - Elf_Internal_Sym *sym; +ip2k_elf_gc_mark_hook (asection *sec, + struct bfd_link_info *info ATTRIBUTE_UNUSED, + Elf_Internal_Rela *rel, + struct elf_link_hash_entry *h, + Elf_Internal_Sym *sym) { if (h != NULL) { @@ -1617,11 +1540,10 @@ ip2k_elf_gc_mark_hook (sec, info, rel, h } static bfd_boolean -ip2k_elf_gc_sweep_hook (abfd, info, sec, relocs) - bfd *abfd ATTRIBUTE_UNUSED; - struct bfd_link_info *info ATTRIBUTE_UNUSED; - asection *sec ATTRIBUTE_UNUSED; - const Elf_Internal_Rela *relocs ATTRIBUTE_UNUSED; +ip2k_elf_gc_sweep_hook (bfd *abfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info ATTRIBUTE_UNUSED, + asection *sec ATTRIBUTE_UNUSED, + const Elf_Internal_Rela *relocs ATTRIBUTE_UNUSED) { /* We don't use got and plt entries for ip2k. */ return TRUE; diff -uprN binutils-2.16.91.0.1/bfd/elf32-m32c.c binutils-2.16.91.0.2/bfd/elf32-m32c.c --- binutils-2.16.91.0.1/bfd/elf32-m32c.c 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/bfd/elf32-m32c.c 2005-07-20 12:27:27.200208376 -0700 @@ -0,0 +1,1666 @@ +/* M16C/M32C specific support for 32-bit ELF. + Copyright (C) 2005 + Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include "bfd.h" +#include "sysdep.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "elf/m32c.h" +#include "libiberty.h" + +/* Forward declarations. */ +static reloc_howto_type * m32c_reloc_type_lookup + (bfd *, bfd_reloc_code_real_type); +static void m32c_info_to_howto_rela + (bfd *, arelent *, Elf_Internal_Rela *); +static bfd_boolean m32c_elf_relocate_section + (bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, Elf_Internal_Rela *, Elf_Internal_Sym *, asection **); +static bfd_boolean m32c_elf_gc_sweep_hook + (bfd *, struct bfd_link_info *, asection *, const Elf_Internal_Rela *); +static asection * m32c_elf_gc_mark_hook + (asection *, struct bfd_link_info *, Elf_Internal_Rela *, struct elf_link_hash_entry *, Elf_Internal_Sym *); +static bfd_boolean m32c_elf_check_relocs + (bfd *, struct bfd_link_info *, asection *, const Elf_Internal_Rela *); +static bfd_boolean m32c_elf_relax_delete_bytes (bfd *, asection *, bfd_vma, int); +#ifdef DEBUG +static char * m32c_get_reloc (long reloc); +#endif +static bfd_boolean m32c_elf_relax_section +(bfd *abfd, asection *sec, struct bfd_link_info *link_info, bfd_boolean *again); + + +static reloc_howto_type m32c_elf_howto_table [] = +{ + /* This reloc does nothing. */ + HOWTO (R_M32C_NONE, /* type */ + 0, /* rightshift */ + 0, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32C_NONE", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_M32C_16, /* type */ + 0, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32C_16", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0x0000ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_M32C_24, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 24, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32C_24", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0x00ffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_M32C_32, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32C_32", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_M32C_8_PCREL, /* type */ + 0, /* rightshift */ + 0, /* size (0 = byte, 1 = short, 2 = long) */ + 8, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32C_8_PCREL", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0x000000ff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_M32C_16_PCREL, /* type */ + 0, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32C_16_PCREL", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + TRUE), /* pcrel_offset */ +}; + +/* Map BFD reloc types to M32C ELF reloc types. */ + +struct m32c_reloc_map +{ + bfd_reloc_code_real_type bfd_reloc_val; + unsigned int m32c_reloc_val; +}; + +static const struct m32c_reloc_map m32c_reloc_map [] = +{ + { BFD_RELOC_NONE, R_M32C_NONE }, + { BFD_RELOC_16, R_M32C_16 }, + { BFD_RELOC_24, R_M32C_24 }, + { BFD_RELOC_32, R_M32C_32 }, + { BFD_RELOC_8_PCREL, R_M32C_8_PCREL }, + { BFD_RELOC_16_PCREL, R_M32C_16_PCREL } +}; + +static reloc_howto_type * +m32c_reloc_type_lookup + (bfd * abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) +{ + unsigned int i; + + for (i = ARRAY_SIZE (m32c_reloc_map); --i;) + if (m32c_reloc_map [i].bfd_reloc_val == code) + return & m32c_elf_howto_table [m32c_reloc_map[i].m32c_reloc_val]; + + return NULL; +} + +/* Set the howto pointer for an M32C ELF reloc. */ + +static void +m32c_info_to_howto_rela + (bfd * abfd ATTRIBUTE_UNUSED, + arelent * cache_ptr, + Elf_Internal_Rela * dst) +{ + unsigned int r_type; + + r_type = ELF32_R_TYPE (dst->r_info); + BFD_ASSERT (r_type < (unsigned int) R_M32C_max); + cache_ptr->howto = & m32c_elf_howto_table [r_type]; +} + + + +/* Relocate an M32C ELF section. + There is some attempt to make this function usable for many architectures, + both USE_REL and USE_RELA ['twould be nice if such a critter existed], + if only to serve as a learning tool. + + The RELOCATE_SECTION function is called by the new ELF backend linker + to handle the relocations for a section. + + The relocs are always passed as Rela structures; if the section + actually uses Rel structures, the r_addend field will always be + zero. + + This function is responsible for adjusting the section contents as + necessary, and (if using Rela relocs and generating a relocatable + output file) adjusting the reloc addend as necessary. + + This function does not have to worry about setting the reloc + address or the reloc symbol index. + + LOCAL_SYMS is a pointer to the swapped in local symbols. + + LOCAL_SECTIONS is an array giving the section in the input file + corresponding to the st_shndx field of each local symbol. + + The global hash table entry for the global symbols can be found + via elf_sym_hashes (input_bfd). + + When generating relocatable output, this function must handle + STB_LOCAL/STT_SECTION symbols specially. The output symbol is + going to be the section symbol corresponding to the output + section, which means that the addend must be adjusted + accordingly. */ + +static bfd_boolean +m32c_elf_relocate_section + (bfd * output_bfd ATTRIBUTE_UNUSED, + struct bfd_link_info * info, + bfd * input_bfd, + asection * input_section, + bfd_byte * contents, + Elf_Internal_Rela * relocs, + Elf_Internal_Sym * local_syms, + asection ** local_sections) +{ + Elf_Internal_Shdr * symtab_hdr; + struct elf_link_hash_entry ** sym_hashes; + Elf_Internal_Rela * rel; + Elf_Internal_Rela * relend; + bfd *dynobj; + asection *splt; + + symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (input_bfd); + relend = relocs + input_section->reloc_count; + + dynobj = elf_hash_table (info)->dynobj; + splt = NULL; + if (dynobj != NULL) + splt = bfd_get_section_by_name (dynobj, ".plt"); + + for (rel = relocs; rel < relend; rel ++) + { + reloc_howto_type * howto; + unsigned long r_symndx; + Elf_Internal_Sym * sym; + asection * sec; + struct elf_link_hash_entry * h; + bfd_vma relocation; + bfd_reloc_status_type r; + const char * name = NULL; + int r_type; + + r_type = ELF32_R_TYPE (rel->r_info); + + r_symndx = ELF32_R_SYM (rel->r_info); + + if (info->relocatable) + { + /* This is a relocatable link. We don't have to change + anything, unless the reloc is against a section symbol, + in which case we have to adjust according to where the + section symbol winds up in the output section. */ + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + + if (ELF_ST_TYPE (sym->st_info) == STT_SECTION) + { + sec = local_sections [r_symndx]; + rel->r_addend += sec->output_offset + sym->st_value; + } + } + + continue; + } + + /* This is a final link. */ + howto = m32c_elf_howto_table + ELF32_R_TYPE (rel->r_info); + h = NULL; + sym = NULL; + sec = NULL; + + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + sec = local_sections [r_symndx]; + relocation = (sec->output_section->vma + + sec->output_offset + + sym->st_value); + + name = bfd_elf_string_from_elf_section + (input_bfd, symtab_hdr->sh_link, sym->st_name); + name = (name == NULL) ? bfd_section_name (input_bfd, sec) : name; + } + else + { + h = sym_hashes [r_symndx - symtab_hdr->sh_info]; + + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + + name = h->root.root.string; + + if (h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak) + { + sec = h->root.u.def.section; + relocation = (h->root.u.def.value + + sec->output_section->vma + + sec->output_offset); + } + else if (h->root.type == bfd_link_hash_undefweak) + { + relocation = 0; + } + else + { + if (! ((*info->callbacks->undefined_symbol) + (info, h->root.root.string, input_bfd, + input_section, rel->r_offset, TRUE))) + return FALSE; + relocation = 0; + } + } + + switch (ELF32_R_TYPE (rel->r_info)) + { + case R_M32C_16: + { + bfd_vma *plt_offset; + + if (h != NULL) + plt_offset = &h->plt.offset; + else + plt_offset = elf_local_got_offsets (input_bfd) + r_symndx; + + /* printf("%s: rel %x plt %d\n", h ? h->root.root.string : "(none)", + relocation, *plt_offset);*/ + if (relocation <= 0xffff) + { + /* If the symbol is in range for a 16-bit address, we should + have deallocated the plt entry in relax_section. */ + BFD_ASSERT (*plt_offset == (bfd_vma) -1); + } + else + { + /* If the symbol is out of range for a 16-bit address, + we must have allocated a plt entry. */ + BFD_ASSERT (*plt_offset != (bfd_vma) -1); + + /* If this is the first time we've processed this symbol, + fill in the plt entry with the correct symbol address. */ + if ((*plt_offset & 1) == 0) + { + unsigned int x; + + x = 0x000000fc; /* jmpf */ + x |= (relocation << 8) & 0xffffff00; + bfd_put_32 (input_bfd, x, splt->contents + *plt_offset); + *plt_offset |= 1; + } + + relocation = (splt->output_section->vma + + splt->output_offset + + (*plt_offset & -2)); + } + } + break; + } + + r = _bfd_final_link_relocate (howto, input_bfd, input_section, + contents, rel->r_offset, relocation, + rel->r_addend); + + if (r != bfd_reloc_ok) + { + const char * msg = (const char *) NULL; + + switch (r) + { + case bfd_reloc_overflow: + r = info->callbacks->reloc_overflow + (info, (h ? &h->root : NULL), name, howto->name, (bfd_vma) 0, + input_bfd, input_section, rel->r_offset); + break; + + case bfd_reloc_undefined: + r = info->callbacks->undefined_symbol + (info, name, input_bfd, input_section, rel->r_offset, + TRUE); + break; + + case bfd_reloc_outofrange: + msg = _("internal error: out of range error"); + break; + + case bfd_reloc_notsupported: + msg = _("internal error: unsupported relocation error"); + break; + + case bfd_reloc_dangerous: + msg = _("internal error: dangerous relocation"); + break; + + default: + msg = _("internal error: unknown error"); + break; + } + + if (msg) + r = info->callbacks->warning + (info, msg, name, input_bfd, input_section, rel->r_offset); + + if (! r) + return FALSE; + } + } + + return TRUE; +} + +/* Return the section that should be marked against GC for a given + relocation. */ + +static asection * +m32c_elf_gc_mark_hook + (asection * sec, + struct bfd_link_info * info ATTRIBUTE_UNUSED, + Elf_Internal_Rela * rel, + struct elf_link_hash_entry * h, + Elf_Internal_Sym * sym) +{ + if (h != NULL) + { + switch (ELF32_R_TYPE (rel->r_info)) + { + default: + switch (h->root.type) + { + case bfd_link_hash_defined: + case bfd_link_hash_defweak: + return h->root.u.def.section; + + case bfd_link_hash_common: + return h->root.u.c.p->section; + + default: + break; + } + } + } + else + { + if (!(elf_bad_symtab (sec->owner) + && ELF_ST_BIND (sym->st_info) != STB_LOCAL) + && ! ((sym->st_shndx <= 0 || sym->st_shndx >= SHN_LORESERVE) + && sym->st_shndx != SHN_COMMON)) + { + return bfd_section_from_elf_index (sec->owner, sym->st_shndx); + } + } + + return NULL; +} + +/* Update the got entry reference counts for the section being removed. */ + +static bfd_boolean +m32c_elf_gc_sweep_hook + (bfd * abfd ATTRIBUTE_UNUSED, + struct bfd_link_info * info ATTRIBUTE_UNUSED, + asection * sec ATTRIBUTE_UNUSED, + const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED) +{ + return TRUE; +} + +/* We support 16-bit pointers to code above 64k by generating a thunk + below 64k containing a JMP instruction to the final address. */ + +static bfd_boolean +m32c_elf_check_relocs + (bfd * abfd, + struct bfd_link_info * info, + asection * sec, + const Elf_Internal_Rela * relocs) +{ + Elf_Internal_Shdr * symtab_hdr; + struct elf_link_hash_entry ** sym_hashes; + struct elf_link_hash_entry ** sym_hashes_end; + const Elf_Internal_Rela * rel; + const Elf_Internal_Rela * rel_end; + bfd_vma *local_plt_offsets; + asection *splt; + bfd *dynobj; + + if (info->relocatable) + return TRUE; + + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (abfd); + local_plt_offsets = elf_local_got_offsets (abfd); + splt = NULL; + dynobj = elf_hash_table(info)->dynobj; + + sym_hashes_end = sym_hashes + symtab_hdr->sh_size/sizeof (Elf32_External_Sym); + if (!elf_bad_symtab (abfd)) + sym_hashes_end -= symtab_hdr->sh_info; + + rel_end = relocs + sec->reloc_count; + for (rel = relocs; rel < rel_end; rel++) + { + struct elf_link_hash_entry *h; + unsigned long r_symndx; + bfd_vma *offset; + + r_symndx = ELF32_R_SYM (rel->r_info); + if (r_symndx < symtab_hdr->sh_info) + h = NULL; + else + { + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + } + + switch (ELF32_R_TYPE (rel->r_info)) + { + /* This relocation describes a 16-bit pointer to a function. + We may need to allocate a thunk in low memory; reserve memory + for it now. */ + case R_M32C_16: + if (dynobj == NULL) + elf_hash_table (info)->dynobj = dynobj = abfd; + if (splt == NULL) + { + splt = bfd_get_section_by_name (dynobj, ".plt"); + if (splt == NULL) + { + splt = bfd_make_section (dynobj, ".plt"); + if (splt == NULL + || ! bfd_set_section_flags (dynobj, splt, + (SEC_ALLOC + | SEC_LOAD + | SEC_HAS_CONTENTS + | SEC_IN_MEMORY + | SEC_LINKER_CREATED + | SEC_READONLY + | SEC_CODE)) + || ! bfd_set_section_alignment (dynobj, splt, 1)) + return FALSE; + } + } + + if (h != NULL) + offset = &h->plt.offset; + else + { + if (local_plt_offsets == NULL) + { + size_t size; + unsigned int i; + + size = symtab_hdr->sh_info * sizeof (bfd_vma); + local_plt_offsets = (bfd_vma *) bfd_alloc (abfd, size); + if (local_plt_offsets == NULL) + return FALSE; + elf_local_got_offsets (abfd) = local_plt_offsets; + + for (i = 0; i < symtab_hdr->sh_info; i++) + local_plt_offsets[i] = (bfd_vma) -1; + } + offset = &local_plt_offsets[r_symndx]; + } + + if (*offset == (bfd_vma) -1) + { + *offset = splt->size; + splt->size += 4; + } + break; + } + } + + return TRUE; +} + +/* This must exist if dynobj is ever set. */ + +static bfd_boolean +m32c_elf_finish_dynamic_sections (bfd *abfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info) +{ + bfd *dynobj; + asection *splt; + + /* As an extra sanity check, verify that all plt entries have + been filled in. */ + + if ((dynobj = elf_hash_table (info)->dynobj) != NULL + && (splt = bfd_get_section_by_name (dynobj, ".plt")) != NULL) + { + bfd_byte *contents = splt->contents; + unsigned int i, size = splt->size; + for (i = 0; i < size; i += 4) + { + unsigned int x = bfd_get_32 (dynobj, contents + i); + BFD_ASSERT (x != 0); + } + } + + return TRUE; +} + +static bfd_boolean +m32c_elf_always_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info) +{ + bfd *dynobj; + asection *splt; + + if (info->relocatable) + return TRUE; + + dynobj = elf_hash_table (info)->dynobj; + if (dynobj == NULL) + return TRUE; + + splt = bfd_get_section_by_name (dynobj, ".plt"); + BFD_ASSERT (splt != NULL); + + splt->contents = (bfd_byte *) bfd_zalloc (dynobj, splt->size); + if (splt->contents == NULL) + return FALSE; + + return TRUE; +} + +/* Function to set the ELF flag bits. */ + +static bfd_boolean +m32c_elf_set_private_flags (bfd *abfd, flagword flags) +{ + elf_elfheader (abfd)->e_flags = flags; + elf_flags_init (abfd) = TRUE; + return TRUE; +} + +/* Merge backend specific data from an object file to the output + object file when linking. */ + +static bfd_boolean +m32c_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd) +{ + flagword old_flags, old_partial; + flagword new_flags, new_partial; + bfd_boolean error = FALSE; + char new_opt[80]; + char old_opt[80]; + + new_opt[0] = old_opt[0] = '\0'; + new_flags = elf_elfheader (ibfd)->e_flags; + old_flags = elf_elfheader (obfd)->e_flags; + +#ifdef DEBUG + (*_bfd_error_handler) ("old_flags = 0x%.8lx, new_flags = 0x%.8lx, init = %s, filename = %s", + old_flags, new_flags, elf_flags_init (obfd) ? "yes" : "no", + bfd_get_filename (ibfd)); +#endif + + if (!elf_flags_init (obfd)) + { + /* First call, no flags set. */ + elf_flags_init (obfd) = TRUE; + elf_elfheader (obfd)->e_flags = new_flags; + } + + else if (new_flags == old_flags) + /* Compatible flags are ok. */ + ; + + else /* Possibly incompatible flags. */ + { + /* Warn if different cpu is used (allow a specific cpu to override + the generic cpu). */ + new_partial = (new_flags & EF_M32C_CPU_MASK); + old_partial = (old_flags & EF_M32C_CPU_MASK); + if (new_partial == old_partial) + ; + + else + { + switch (new_partial) + { + default: strcat (new_opt, " -m16c"); break; + case EF_M32C_CPU_M16C: strcat (new_opt, " -m16c"); break; + case EF_M32C_CPU_M32C: strcat (new_opt, " -m32c"); break; + } + + switch (old_partial) + { + default: strcat (old_opt, " -m16c"); break; + case EF_M32C_CPU_M16C: strcat (old_opt, " -m16c"); break; + case EF_M32C_CPU_M32C: strcat (old_opt, " -m32c"); break; + } + } + + /* Print out any mismatches from above. */ + if (new_opt[0]) + { + error = TRUE; + (*_bfd_error_handler) + (_("%s: compiled with %s and linked with modules compiled with %s"), + bfd_get_filename (ibfd), new_opt, old_opt); + } + + new_flags &= ~ EF_M32C_ALL_FLAGS; + old_flags &= ~ EF_M32C_ALL_FLAGS; + + /* Warn about any other mismatches. */ + if (new_flags != old_flags) + { + error = TRUE; + (*_bfd_error_handler) + (_("%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"), + bfd_get_filename (ibfd), (long)new_flags, (long)old_flags); + } + } + + if (error) + bfd_set_error (bfd_error_bad_value); + + return !error; +} + + +static bfd_boolean +m32c_elf_print_private_bfd_data (bfd *abfd, PTR ptr) +{ + FILE *file = (FILE *) ptr; + flagword flags; + + BFD_ASSERT (abfd != NULL && ptr != NULL); + + /* Print normal ELF private data. */ + _bfd_elf_print_private_bfd_data (abfd, ptr); + + flags = elf_elfheader (abfd)->e_flags; + fprintf (file, _("private flags = 0x%lx:"), (long)flags); + + switch (flags & EF_M32C_CPU_MASK) + { + default: break; + case EF_M32C_CPU_M16C: fprintf (file, " -m16c"); break; + case EF_M32C_CPU_M32C: fprintf (file, " -m32c"); break; + } + + fputc ('\n', file); + return TRUE; +} + +/* Return the MACH for an e_flags value. */ + +static int +elf32_m32c_machine (bfd *abfd) +{ + switch (elf_elfheader (abfd)->e_flags & EF_M32C_CPU_MASK) + { + case EF_M32C_CPU_M16C: return bfd_mach_m16c; + case EF_M32C_CPU_M32C: return bfd_mach_m32c; + } + + return bfd_mach_m16c; +} + +static bfd_boolean +m32c_elf_object_p (bfd *abfd) +{ + bfd_default_set_arch_mach (abfd, bfd_arch_m32c, + elf32_m32c_machine (abfd)); + return TRUE; +} + + +#ifdef DEBUG +static void +dump_symtab (bfd * abfd, void *internal_syms, void *external_syms) +{ + size_t locsymcount; + Elf_Internal_Sym *isymbuf; + Elf_Internal_Sym *isymend; + Elf_Internal_Sym *isym; + Elf_Internal_Shdr *symtab_hdr; + bfd_boolean free_internal = 0, free_external = 0; + char * st_info_str; + char * st_info_stb_str; + char * st_other_str; + char * st_shndx_str; + + if (! internal_syms) + { + internal_syms = bfd_malloc (1000); + free_internal = 1; + } + if (! external_syms) + { + external_syms = bfd_malloc (1000); + free_external = 1; + } + + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + locsymcount = symtab_hdr->sh_size / get_elf_backend_data(abfd)->s->sizeof_sym; + if (free_internal) + isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, + symtab_hdr->sh_info, 0, + internal_syms, external_syms, NULL); + else + isymbuf = internal_syms; + isymend = isymbuf + locsymcount; + + for (isym = isymbuf ; isym < isymend ; isym++) + { + switch (ELF_ST_TYPE (isym->st_info)) + { + case STT_FUNC: st_info_str = "STT_FUNC"; + case STT_SECTION: st_info_str = "STT_SECTION"; + case STT_SRELC: st_info_str = "STT_SRELC"; + case STT_FILE: st_info_str = "STT_FILE"; + case STT_OBJECT: st_info_str = "STT_OBJECT"; + case STT_TLS: st_info_str = "STT_TLS"; + default: st_info_str = ""; + } + switch (ELF_ST_BIND (isym->st_info)) + { + case STB_LOCAL: st_info_stb_str = "STB_LOCAL"; + case STB_GLOBAL: st_info_stb_str = "STB_GLOBAL"; + default: st_info_stb_str = ""; + } + switch (ELF_ST_VISIBILITY (isym->st_other)) + { + case STV_DEFAULT: st_other_str = "STV_DEFAULT"; + case STV_INTERNAL: st_other_str = "STV_INTERNAL"; + case STV_PROTECTED: st_other_str = "STV_PROTECTED"; + default: st_other_str = ""; + } + switch (isym->st_shndx) + { + case SHN_ABS: st_shndx_str = "SHN_ABS"; + case SHN_COMMON: st_shndx_str = "SHN_COMMON"; + case SHN_UNDEF: st_shndx_str = "SHN_UNDEF"; + default: st_shndx_str = ""; + } + + printf ("isym = %p st_value = %lx st_size = %lx st_name = (%lu) %s " + "st_info = (%d) %s %s st_other = (%d) %s st_shndx = (%d) %s\n", + isym, + (unsigned long) isym->st_value, + (unsigned long) isym->st_size, + isym->st_name, + bfd_elf_string_from_elf_section (abfd, symtab_hdr->sh_link, + isym->st_name), + isym->st_info, st_info_str, st_info_stb_str, + isym->st_other, st_other_str, + isym->st_shndx, st_shndx_str); + } + if (free_internal) + free (internal_syms); + if (free_external) + free (external_syms); +} + +static char * +m32c_get_reloc (long reloc) +{ + if (0 <= reloc && reloc < R_M32C_max) + return m32c_elf_howto_table[reloc].name; + else + return ""; +} +#endif /* DEBUG */ + +/* Handle relaxing. */ + +/* A subroutine of m32c_elf_relax_section. If the global symbol H + is within the low 64k, remove any entry for it in the plt. */ + +struct relax_plt_data +{ + asection *splt; + bfd_boolean *again; +}; + +static bfd_boolean +m32c_relax_plt_check (struct elf_link_hash_entry *h, + PTR xdata) +{ + struct relax_plt_data *data = (struct relax_plt_data *) xdata; + + if (h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + + if (h->plt.offset != (bfd_vma) -1) + { + bfd_vma address; + + if (h->root.type == bfd_link_hash_undefined + || h->root.type == bfd_link_hash_undefweak) + address = 0; + else + address = (h->root.u.def.section->output_section->vma + + h->root.u.def.section->output_offset + + h->root.u.def.value); + + if (address <= 0xffff) + { + h->plt.offset = -1; + data->splt->size -= 4; + *data->again = TRUE; + } + } + + return TRUE; +} + +/* A subroutine of m32c_elf_relax_section. If the global symbol H + previously had a plt entry, give it a new entry offset. */ + +static bfd_boolean +m32c_relax_plt_realloc (struct elf_link_hash_entry *h, + PTR xdata) +{ + bfd_vma *entry = (bfd_vma *) xdata; + + if (h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + + if (h->plt.offset != (bfd_vma) -1) + { + h->plt.offset = *entry; + *entry += 4; + } + + return TRUE; +} + +static bfd_boolean +m32c_elf_relax_plt_section (bfd *dynobj, + asection *splt, + struct bfd_link_info *info, + bfd_boolean *again) +{ + struct relax_plt_data relax_plt_data; + bfd *ibfd; + + /* Assume nothing changes. */ + *again = FALSE; + + if (info->relocatable) + return TRUE; + + /* We only relax the .plt section at the moment. */ + if (dynobj != elf_hash_table (info)->dynobj + || strcmp (splt->name, ".plt") != 0) + return TRUE; + + /* Quick check for an empty plt. */ + if (splt->size == 0) + return TRUE; + + /* Map across all global symbols; see which ones happen to + fall in the low 64k. */ + relax_plt_data.splt = splt; + relax_plt_data.again = again; + elf_link_hash_traverse (elf_hash_table (info), m32c_relax_plt_check, + &relax_plt_data); + + /* Likewise for local symbols, though that's somewhat less convenient + as we have to walk the list of input bfds and swap in symbol data. */ + for (ibfd = info->input_bfds; ibfd ; ibfd = ibfd->link_next) + { + bfd_vma *local_plt_offsets = elf_local_got_offsets (ibfd); + Elf_Internal_Shdr *symtab_hdr; + Elf_Internal_Sym *isymbuf = NULL; + unsigned int idx; + + if (! local_plt_offsets) + continue; + + symtab_hdr = &elf_tdata (ibfd)->symtab_hdr; + if (symtab_hdr->sh_info != 0) + { + isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; + if (isymbuf == NULL) + isymbuf = bfd_elf_get_elf_syms (ibfd, symtab_hdr, + symtab_hdr->sh_info, 0, + NULL, NULL, NULL); + if (isymbuf == NULL) + return FALSE; + } + + for (idx = 0; idx < symtab_hdr->sh_info; ++idx) + { + Elf_Internal_Sym *isym; + asection *tsec; + bfd_vma address; + + if (local_plt_offsets[idx] == (bfd_vma) -1) + continue; + + isym = &isymbuf[idx]; + if (isym->st_shndx == SHN_UNDEF) + continue; + else if (isym->st_shndx == SHN_ABS) + tsec = bfd_abs_section_ptr; + else if (isym->st_shndx == SHN_COMMON) + tsec = bfd_com_section_ptr; + else + tsec = bfd_section_from_elf_index (ibfd, isym->st_shndx); + + address = (tsec->output_section->vma + + tsec->output_offset + + isym->st_value); + if (address <= 0xffff) + { + local_plt_offsets[idx] = -1; + splt->size -= 4; + *again = TRUE; + } + } + + if (isymbuf != NULL + && symtab_hdr->contents != (unsigned char *) isymbuf) + { + if (! info->keep_memory) + free (isymbuf); + else + { + /* Cache the symbols for elf_link_input_bfd. */ + symtab_hdr->contents = (unsigned char *) isymbuf; + } + } + } + + /* If we changed anything, walk the symbols again to reallocate + .plt entry addresses. */ + if (*again && splt->size > 0) + { + bfd_vma entry = 0; + + elf_link_hash_traverse (elf_hash_table (info), + m32c_relax_plt_realloc, &entry); + + for (ibfd = info->input_bfds; ibfd ; ibfd = ibfd->link_next) + { + bfd_vma *local_plt_offsets = elf_local_got_offsets (ibfd); + unsigned int nlocals = elf_tdata (ibfd)->symtab_hdr.sh_info; + unsigned int idx; + + if (! local_plt_offsets) + continue; + + for (idx = 0; idx < nlocals; ++idx) + if (local_plt_offsets[idx] != (bfd_vma) -1) + { + local_plt_offsets[idx] = entry; + entry += 4; + } + } + } + + return TRUE; +} + +struct relax_reloc_s +{ + int machine; + int opcode_mask; + bfd_vma opcode; /* original opcode or insn part */ + int relax_backward; /* lbound */ + int relax_forward; /* hbound */ + int value_shift; + int mask; + int new_opcode; /* new opcode */ + int old_reloc; /* old relocation */ + int new_reloc; /* new relocation */ + int use_pcrel; + int delete_n; /* # bytes differ between original and new */ +}; +static struct relax_reloc_s relax_reloc [] = + { +#if 0 + { + bfd_mach_m16c, + 0xff, + 0xfc, /* jmp.a */ + -32768, + 32767, + 2, + 0xffffff00, + 0xf4, /* jmp.w */ + R_M32C_8_ELABEL24, + R_M32C_8_PCREL16, + 1, + 1, + }, + { + bfd_mach_m32c, + 0xff, + 0xcc, /* jmp.a */ + -32768, + 32767, + 2, + 0xffffff00, + 0xce, /* jmp.w */ + R_M32C_8_ELABEL24, + R_M32C_8_PCREL16, + 1, + 1, + }, + { + bfd_mach_m32c, + 0xff, + 0xcd, /* jsr.a */ + -32768, + 32767, + 2, + 0xffffff00, + 0xcf, /* jsr.w */ + R_M32C_8_ELABEL24, + R_M32C_8_PCREL16, + 1, + 1, + }, + { + bfd_mach_m16c, + 0xff, + 0xf4, /* jmp.w */ + -128, + 127, + 2, + 0xffffff00, + 0xfe, /* jmp.b */ + R_M32C_8_PCREL16, + R_M32C_8_PCREL8, + 1, + 1, + }, + { + bfd_mach_m32c, + 0xff, + 0xce, /* jmp.w */ + -128, + 127, + 2, + 0xffffff00, + 0xbb, /* jmp.b */ + R_M32C_8_PCREL16, + R_M32C_8_PCREL8, + 1, + 1, + }, + { + bfd_mach_m32c, + 0xc0f6, + 0x8096, /* dest */ + 0, + 0xffff, + 3, + 0xffff3fff, + 0xc000, /* abs16 */ + R_M32C_24_ABS24, + R_M32C_24_ABS16, + 0, + 1, + }, + { + bfd_mach_m32c, + 0xc0f6, + 0x80a6, /* dest */ + 0, + 0xffff, + 4, + 0xffff3fff, + 0xc000, /* abs16 */ + R_M32C_32_ABS24, + R_M32C_32_ABS16, + 0, + 1, + }, + { + bfd_mach_m32c, + 0xc0f6, + 0x80b6, /* dest */ + 0, + 0xffff, + 5, + 0xffff3fff, + 0xc000, /* abs16 */ + R_M32C_40_ABS24, + R_M32C_40_ABS16, + 0, + 1, + }, + { + bfd_mach_m32c, + 0x30f0, + 0x20b0, /* src */ + 0, + 0xffff, + 2, + 0xffffcfff, + 0x3000, /* abs16 */ + R_M32C_16_ABS24, + R_M32C_16_ABS16, + 0, + 1, + }, + { + bfd_mach_m32c, + 0xc086, + 0x8086, /* dest */ + 0, + 0xffff, + 2, + 0xffff3fff, + 0xc000, /* abs16 */ + R_M32C_16_ABS24, + R_M32C_16_ABS16, + 0, + 1, + }, +#endif + { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + } + }; +static bfd_boolean +m32c_elf_relax_section + (bfd * abfd, + asection * sec, + struct bfd_link_info * link_info, + bfd_boolean * again) +{ + Elf_Internal_Shdr *symtab_hdr; + Elf_Internal_Shdr *shndx_hdr; + Elf_Internal_Rela *internal_relocs; + Elf_Internal_Rela *free_relocs = NULL; + Elf_Internal_Rela *irel, *irelend; + bfd_byte * contents = NULL; + bfd_byte * free_contents = NULL; + Elf32_External_Sym *extsyms = NULL; + Elf32_External_Sym *free_extsyms = NULL; + Elf_External_Sym_Shndx *shndx_buf = NULL; + int machine; + + if (abfd == elf_hash_table (link_info)->dynobj + && strcmp (sec->name, ".plt") == 0) + return m32c_elf_relax_plt_section (abfd, sec, link_info, again); + + /* Assume nothing changes. */ + *again = FALSE; + + machine = elf32_m32c_machine (abfd); + + /* We don't have to do anything for a relocatable link, if + this section does not have relocs, or if this is not a + code section. */ + if (link_info->relocatable + || (sec->flags & SEC_RELOC) == 0 + || sec->reloc_count == 0 + || (sec->flags & SEC_CODE) == 0) + return TRUE; + + /* Relaxing doesn't quite work right yet. */ + return TRUE; + + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + shndx_hdr = &elf_tdata (abfd)->symtab_shndx_hdr; + + /* Get a copy of the native relocations. */ + internal_relocs = (_bfd_elf_link_read_relocs + (abfd, sec, (PTR) NULL, (Elf_Internal_Rela *) NULL, + link_info->keep_memory)); + if (internal_relocs == NULL) + goto error_return; + if (! link_info->keep_memory) + free_relocs = internal_relocs; + + /* Walk through them looking for relaxing opportunities. */ + irelend = internal_relocs + sec->reloc_count; + + for (irel = internal_relocs; irel < irelend; irel++) + { + bfd_vma symval; + bfd_vma insn; + bfd_vma pc; + bfd_signed_vma pcrel_value; + bfd_vma addend; + int to_delete; + int i; + + /* Get the section contents. */ + if (contents == NULL) + { + if (elf_section_data (sec)->this_hdr.contents != NULL) + contents = elf_section_data (sec)->this_hdr.contents; + /* Go get them off disk. */ + else if (!bfd_malloc_and_get_section (abfd, sec, &contents)) + goto error_return; + } + + /* Read this BFD's symbols if we haven't done so already. */ + if (extsyms == NULL) + { + /* Get cached copy if it exists. */ + if (symtab_hdr->contents != NULL) + extsyms = (Elf32_External_Sym *) symtab_hdr->contents; + else + { + bfd_size_type amt = symtab_hdr->sh_size; + + /* Go get them off disk. */ + extsyms = (Elf32_External_Sym *) bfd_malloc (amt); + if (extsyms == NULL) + goto error_return; + free_extsyms = extsyms; + if (bfd_seek (abfd, symtab_hdr->sh_offset, SEEK_SET) != 0 + || bfd_bread (extsyms, amt, abfd) != amt) + goto error_return; + symtab_hdr->contents = (bfd_byte *) extsyms; + } + + if (shndx_hdr->sh_size != 0) + { + bfd_size_type amt; + + amt = symtab_hdr->sh_info; + amt *= sizeof (Elf_External_Sym_Shndx); + shndx_buf = (Elf_External_Sym_Shndx *) bfd_malloc (amt); + if (shndx_buf == NULL) + goto error_return; + if (bfd_seek (abfd, shndx_hdr->sh_offset, SEEK_SET) != 0 + || bfd_bread ((PTR) shndx_buf, amt, abfd) != amt) + goto error_return; + shndx_hdr->contents = (bfd_byte *) shndx_buf; + } + } + + /* Get the value of the symbol referred to by the reloc. */ + if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info) + { + /* A local symbol. */ + Elf32_External_Sym *esym; + Elf_External_Sym_Shndx *shndx; + Elf_Internal_Sym isym; + + esym = extsyms + ELF32_R_SYM (irel->r_info); + shndx = shndx_buf + (shndx_buf ? ELF32_R_SYM (irel->r_info) : 0); + bfd_elf32_swap_symbol_in (abfd, esym, shndx, &isym); + + symval = (isym.st_value + + sec->output_section->vma + + sec->output_offset); + } + else + { + unsigned long indx; + struct elf_link_hash_entry *h; + + /* An external symbol. */ + indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info; + h = elf_sym_hashes (abfd)[indx]; + BFD_ASSERT (h != NULL); + + if (h->root.type != bfd_link_hash_defined + && h->root.type != bfd_link_hash_defweak) + /* This appears to be a reference to an undefined + symbol. Just ignore it--it will be caught by the + regular reloc processing. */ + continue; + + symval = (h->root.u.def.value + + h->root.u.def.section->output_section->vma + + h->root.u.def.section->output_offset); + } + + /* There will always be room for the relaxed insn, since it is smaller + than the one it would replace. */ + BFD_ASSERT (irel->r_offset <= sec->size - 2); + + insn = bfd_get_16 (abfd, contents + irel->r_offset + 0); + + addend = irel->r_addend; + for (i = 0; relax_reloc[i].machine; i++) + { +#ifdef DEBUG + _bfd_error_handler ("insn %x %d mask %x opcode %x =%x\n", + insn, i, relax_reloc[i].opcode_mask, + relax_reloc[i].opcode, + (insn & relax_reloc[i].opcode_mask) == relax_reloc[i].opcode); +#endif + if (!(machine == relax_reloc[i].machine + && (insn & relax_reloc[i].opcode_mask) == relax_reloc[i].opcode + && (relax_reloc[i].old_reloc + == (int) ELF32_R_TYPE(irel->r_info)))) + continue; + + /* At this point we've confirmed we have a matching insn. Now + ensure the operand is in range. */ + if (relax_reloc[i].use_pcrel) + { + pc = sec->output_section->vma + sec->output_offset + + irel->r_offset; + pcrel_value = symval - pc; +#ifndef USE_REL /* put in for learning purposes */ + pcrel_value += addend; +#else + addend = bfd_get_signed_16 (abfd, contents + irel->r_offset + 2); + pcrel_value += addend; +#endif + } + else + pcrel_value = symval; + + if (pcrel_value >= relax_reloc[i].relax_backward + && pcrel_value < relax_reloc[i].relax_forward + 2) + { + /* We can relax to a shorter operand. */ + insn = (insn & relax_reloc[i].mask) | relax_reloc[i].new_opcode; + + to_delete = relax_reloc[i].delete_n; + + /* Rewrite the insn. */ + bfd_put_16 (abfd, insn, contents + irel->r_offset); + + /* Set the new reloc type. */ + irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), + relax_reloc[i].new_reloc); + irel->r_addend = pcrel_value; + } + else + continue; + +#ifdef DEBUG + _bfd_error_handler ("insn %x pc %x index %d mask %x shift %d delete %d\n" + "old reloc %s new reloc %s", + insn, sec->output_section->vma + + sec->output_offset + irel->r_offset + 2, + i, relax_reloc[i].opcode_mask, + relax_reloc[i].value_shift, to_delete, + m32c_get_reloc (relax_reloc[i].old_reloc), + m32c_get_reloc (relax_reloc[i].new_reloc)); +#endif + + /* Note that we've changed the relocs, section contents, etc. */ + elf_section_data (sec)->relocs = internal_relocs; + free_relocs = NULL; + + elf_section_data (sec)->this_hdr.contents = contents; + free_contents = NULL; + + symtab_hdr->contents = (bfd_byte *) extsyms; + free_extsyms = NULL; + + /* Delete TO_DELETE bytes of data. */ + if (! m32c_elf_relax_delete_bytes + (abfd, sec, irel->r_offset + relax_reloc[i].value_shift, + to_delete)) + goto error_return; + } /* next relax_reloc */ + } /* next relocation */ + + if (free_relocs != NULL) + { + free (free_relocs); + free_relocs = NULL; + } + + if (free_contents != NULL) + { + if (! link_info->keep_memory) + free (free_contents); + /* Cache the section contents for elf_link_input_bfd. */ + else + elf_section_data (sec)->this_hdr.contents = contents; + + free_contents = NULL; + } + + if (shndx_buf != NULL) + { + shndx_hdr->contents = NULL; + free (shndx_buf); + } + + if (free_extsyms != NULL) + { + if (! link_info->keep_memory) + free (free_extsyms); + /* Cache the symbols for elf_link_input_bfd. */ + else + symtab_hdr->contents = NULL /* (unsigned char *) extsyms*/; + + free_extsyms = NULL; + } + /* elf_link_input_bfd expects internal syms. */ + symtab_hdr->contents = NULL; + + return TRUE; + + error_return: + if (free_relocs != NULL) + free (free_relocs); + if (free_contents != NULL) + free (free_contents); + if (shndx_buf != NULL) + { + shndx_hdr->contents = NULL; + free (shndx_buf); + } + if (free_extsyms != NULL) + free (free_extsyms); + return FALSE; +} + +/* Delete some bytes from a section while relaxing. */ + +static bfd_boolean +m32c_elf_relax_delete_bytes + (bfd * abfd, + asection * sec, + bfd_vma addr, + int count) +{ + Elf_Internal_Shdr *symtab_hdr; + Elf_Internal_Shdr *shndx_hdr; + int sec_shndx; + bfd_byte *contents; + Elf_Internal_Rela *irel; + Elf_Internal_Rela *irelend; + Elf_Internal_Rela *irelalign; + bfd_vma toaddr; + Elf32_External_Sym *esym; + Elf32_External_Sym *esymend; + Elf32_External_Sym *extsyms; + Elf_External_Sym_Shndx *shndx_buf; + Elf_External_Sym_Shndx *shndx; + struct elf_link_hash_entry ** sym_hashes; + struct elf_link_hash_entry ** end_hashes; + unsigned int symcount; + + symtab_hdr = & elf_tdata (abfd)->symtab_hdr; + extsyms = (Elf32_External_Sym *) symtab_hdr->contents; + shndx_hdr = & elf_tdata (abfd)->symtab_shndx_hdr; + shndx_buf = (Elf_External_Sym_Shndx *) shndx_hdr->contents; + sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec); + contents = elf_section_data (sec)->this_hdr.contents; + + /* The deletion must stop at the next ALIGN reloc for an aligment + power larger than the number of bytes we are deleting. */ + irelalign = NULL; + toaddr = sec->size; + + irel = elf_section_data (sec)->relocs; + irelend = irel + sec->reloc_count; + + /* Actually delete the bytes. */ + memmove (contents + addr, contents + addr + count, (size_t) (toaddr - addr - count)); + sec->size -= count; + + /* Adjust all the relocs. */ + for (irel = elf_section_data (sec)->relocs; irel < irelend; irel ++) + { + /* Get the new reloc address. */ + if (irel->r_offset > addr && irel->r_offset < toaddr) + irel->r_offset -= count; + if (irel->r_addend > addr && irel->r_addend < toaddr) + irel->r_addend -= count; + } + + /* Adjust the local symbols defined in this section. */ + shndx = shndx_buf; + esym = extsyms; + esymend = esym + symtab_hdr->sh_info; + for (; esym < esymend; esym++, shndx = (shndx ? shndx + 1 : NULL)) + { + Elf_Internal_Sym isym; + Elf_External_Sym_Shndx dummy; + + bfd_elf32_swap_symbol_in (abfd, esym, shndx, &isym); + + if ((int) isym.st_shndx == sec_shndx + && isym.st_value > addr + && isym.st_value < toaddr) + { + isym.st_value -= count; + bfd_elf32_swap_symbol_out (abfd, &isym, (PTR) esym, (PTR) & dummy); + } + } + + /* Now adjust the global symbols defined in this section. */ + symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym) + - symtab_hdr->sh_info); + sym_hashes = elf_sym_hashes (abfd); + // sym_hashes += symtab_hdr->sh_info; + end_hashes = sym_hashes + symcount; + + for (; sym_hashes < end_hashes; sym_hashes ++) + { + struct elf_link_hash_entry * sym_hash = * sym_hashes; + + if (sym_hash && + ( sym_hash->root.type == bfd_link_hash_defined + || sym_hash->root.type == bfd_link_hash_defweak) + && sym_hash->root.u.def.section == sec + && sym_hash->root.u.def.value > addr + && sym_hash->root.u.def.value < toaddr) + sym_hash->root.u.def.value -= count; + } + + return TRUE; +} + + +#define ELF_ARCH bfd_arch_m32c +#define ELF_MACHINE_CODE EM_M32C +#define ELF_MAXPAGESIZE 0x1000 + +#if 0 +#define TARGET_BIG_SYM bfd_elf32_m32c_vec +#define TARGET_BIG_NAME "elf32-m32c" +#else +#define TARGET_LITTLE_SYM bfd_elf32_m32c_vec +#define TARGET_LITTLE_NAME "elf32-m32c" +#endif + +#define elf_info_to_howto_rel NULL +#define elf_info_to_howto m32c_info_to_howto_rela +#define elf_backend_object_p m32c_elf_object_p +#define elf_backend_relocate_section m32c_elf_relocate_section +#define elf_backend_gc_mark_hook m32c_elf_gc_mark_hook +#define elf_backend_gc_sweep_hook m32c_elf_gc_sweep_hook +#define elf_backend_check_relocs m32c_elf_check_relocs +#define elf_backend_object_p m32c_elf_object_p +#define elf_symbol_leading_char ('_') +#define elf_backend_always_size_sections \ + m32c_elf_always_size_sections +#define elf_backend_finish_dynamic_sections \ + m32c_elf_finish_dynamic_sections + +#define elf_backend_can_gc_sections 1 + +#define bfd_elf32_bfd_reloc_type_lookup m32c_reloc_type_lookup +#define bfd_elf32_bfd_relax_section m32c_elf_relax_section +#define bfd_elf32_bfd_set_private_flags m32c_elf_set_private_flags +#define bfd_elf32_bfd_merge_private_bfd_data m32c_elf_merge_private_bfd_data +#define bfd_elf32_bfd_print_private_bfd_data m32c_elf_print_private_bfd_data + +#include "elf32-target.h" diff -uprN binutils-2.16.91.0.1/bfd/elf32-m32r.c binutils-2.16.91.0.2/bfd/elf32-m32r.c --- binutils-2.16.91.0.1/bfd/elf32-m32r.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-m32r.c 2005-07-20 12:27:27.210206727 -0700 @@ -24,85 +24,6 @@ #include "elf-bfd.h" #include "elf/m32r.h" -static bfd_reloc_status_type m32r_elf_10_pcrel_reloc - PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); -static bfd_reloc_status_type m32r_elf_do_10_pcrel_reloc - PARAMS ((bfd *, reloc_howto_type *, asection *, - bfd_byte *, bfd_vma, asection *, bfd_vma, bfd_vma)); -static bfd_reloc_status_type m32r_elf_hi16_reloc - PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); -static void m32r_elf_relocate_hi16 - PARAMS ((bfd *, int, Elf_Internal_Rela *, Elf_Internal_Rela *, - bfd_byte *, bfd_vma)); -bfd_reloc_status_type m32r_elf_lo16_reloc - PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); -bfd_reloc_status_type m32r_elf_generic_reloc - PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); -static bfd_reloc_status_type m32r_elf_sda16_reloc - PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); -static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup - PARAMS ((bfd *abfd, bfd_reloc_code_real_type code)); -static void m32r_info_to_howto_rel - PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); -static void m32r_info_to_howto - PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); -bfd_boolean _bfd_m32r_elf_section_from_bfd_section - PARAMS ((bfd *, asection *, int *)); -void _bfd_m32r_elf_symbol_processing - PARAMS ((bfd *, asymbol *)); -static bfd_boolean m32r_elf_add_symbol_hook - PARAMS ((bfd *, struct bfd_link_info *, Elf_Internal_Sym *, - const char **, flagword *, asection **, bfd_vma *)); -static bfd_boolean m32r_elf_relocate_section - PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, - Elf_Internal_Rela *, Elf_Internal_Sym *, asection **)); -static bfd_reloc_status_type m32r_elf_final_sda_base - PARAMS ((bfd *, struct bfd_link_info *, const char **, bfd_vma *)); -static bfd_boolean m32r_elf_object_p - PARAMS ((bfd *)); -static void m32r_elf_final_write_processing - PARAMS ((bfd *, bfd_boolean)); -static bfd_boolean m32r_elf_set_private_flags - PARAMS ((bfd *, flagword)); -static bfd_boolean m32r_elf_merge_private_bfd_data - PARAMS ((bfd *, bfd *)); -static bfd_boolean m32r_elf_print_private_bfd_data - PARAMS ((bfd *, PTR)); -static bfd_boolean m32r_elf_gc_sweep_hook - PARAMS ((bfd *, struct bfd_link_info *, asection *, - const Elf_Internal_Rela *)); -static bfd_boolean m32r_elf_check_relocs - PARAMS ((bfd *, struct bfd_link_info *, asection *, - const Elf_Internal_Rela *)); - -static bfd_boolean m32r_elf_adjust_dynamic_symbol - PARAMS ((struct bfd_link_info *, struct elf_link_hash_entry *)); -static bfd_boolean m32r_elf_size_dynamic_sections - PARAMS ((bfd *, struct bfd_link_info *)); - -asection * m32r_elf_gc_mark_hook - PARAMS ((asection *, struct bfd_link_info *, Elf_Internal_Rela *, - struct elf_link_hash_entry *, Elf_Internal_Sym *)); - -static bfd_boolean m32r_elf_create_dynamic_sections - PARAMS ((bfd *, struct bfd_link_info *)); - -static bfd_boolean m32r_elf_finish_dynamic_sections - PARAMS ((bfd *, struct bfd_link_info *)); - -static bfd_boolean m32r_elf_finish_dynamic_symbol - PARAMS ((bfd *, struct bfd_link_info *, struct elf_link_hash_entry *, - Elf_Internal_Sym *)); - -static bfd_boolean allocate_dynrelocs - PARAMS ((struct elf_link_hash_entry *, PTR)); -static bfd_boolean readonly_dynrelocs - PARAMS ((struct elf_link_hash_entry *, PTR)); -static enum elf_reloc_type_class m32r_elf_reloc_type_class - PARAMS ((const Elf_Internal_Rela *)); -static bfd_boolean m32r_elf_fake_sections - PARAMS ((bfd *, Elf_Internal_Shdr *, asection *)); - #define NOP_INSN 0x7000 #define MAKE_PARALLEL(insn) ((insn) | 0x8000) @@ -115,7 +36,7 @@ static bfd_boolean m32r_elf_fake_section #ifndef USE_REL #define USE_REL 0 #endif */ -/* Use RELA. But use REL to link old objects for backwords compatibility. */ +/* Use RELA. But use REL to link old objects for backwords compatibility. */ /* Functions for the M32R ELF linker. */ @@ -160,1092 +81,1091 @@ static bfd_boolean m32r_elf_fake_section #define PLT_ENTRY_WORD4 0xff000000 /* bra .plt0. */ -static reloc_howto_type m32r_elf_howto_table[] = -{ - /* This reloc does nothing. */ - HOWTO (R_M32R_NONE, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_NONE", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE), /* pcrel_offset */ +/* Utility to actually perform an R_M32R_10_PCREL reloc. */ - /* A 16 bit absolute relocation. */ - HOWTO (R_M32R_16, /* type */ - 0, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - m32r_elf_generic_reloc,/* special_function */ - "R_M32R_16", /* name */ - TRUE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xffff, /* dst_mask */ - FALSE), /* pcrel_offset */ +static bfd_reloc_status_type +m32r_elf_do_10_pcrel_reloc (bfd *abfd, + reloc_howto_type *howto, + asection *input_section, + bfd_byte *data, + bfd_vma offset, + asection *symbol_section ATTRIBUTE_UNUSED, + bfd_vma symbol_value, + bfd_vma addend) +{ + bfd_signed_vma relocation; + unsigned long x; + bfd_reloc_status_type status; - /* A 32 bit absolute relocation. */ - HOWTO (R_M32R_32, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - m32r_elf_generic_reloc,/* special_function */ - "R_M32R_32", /* name */ - TRUE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ - FALSE), /* pcrel_offset */ + /* Sanity check the address (offset in section). */ + if (offset > bfd_get_section_limit (abfd, input_section)) + return bfd_reloc_outofrange; - /* A 24 bit address. */ - HOWTO (R_M32R_24, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 24, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_unsigned, /* complain_on_overflow */ - m32r_elf_generic_reloc,/* special_function */ - "R_M32R_24", /* name */ - TRUE, /* partial_inplace */ - 0xffffff, /* src_mask */ - 0xffffff, /* dst_mask */ - FALSE), /* pcrel_offset */ + relocation = symbol_value + addend; + /* Make it pc relative. */ + relocation -= (input_section->output_section->vma + + input_section->output_offset); + /* These jumps mask off the lower two bits of the current address + before doing pcrel calculations. */ + relocation -= (offset & -(bfd_vma) 4); - /* An PC Relative 10-bit relocation, shifted by 2. - This reloc is complicated because relocations are relative to pc & -4. - i.e. branches in the right insn slot use the address of the left insn - slot for pc. */ - /* ??? It's not clear whether this should have partial_inplace set or not. - Branch relaxing in the assembler can store the addend in the insn, - and if bfd_install_relocation gets called the addend may get added - again. */ - HOWTO (R_M32R_10_PCREL, /* type */ - 2, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 10, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - m32r_elf_10_pcrel_reloc, /* special_function */ - "R_M32R_10_PCREL", /* name */ - FALSE, /* partial_inplace */ - 0xff, /* src_mask */ - 0xff, /* dst_mask */ - TRUE), /* pcrel_offset */ + if (relocation < -0x200 || relocation > 0x1ff) + status = bfd_reloc_overflow; + else + status = bfd_reloc_ok; - /* A relative 18 bit relocation, right shifted by 2. */ - HOWTO (R_M32R_18_PCREL, /* type */ - 2, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_18_PCREL", /* name */ - FALSE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xffff, /* dst_mask */ - TRUE), /* pcrel_offset */ + x = bfd_get_16 (abfd, data + offset); + relocation >>= howto->rightshift; + relocation <<= howto->bitpos; + x = (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask); + bfd_put_16 (abfd, (bfd_vma) x, data + offset); - /* A relative 26 bit relocation, right shifted by 2. */ - /* ??? It's not clear whether this should have partial_inplace set or not. - Branch relaxing in the assembler can store the addend in the insn, - and if bfd_install_relocation gets called the addend may get added - again. */ - HOWTO (R_M32R_26_PCREL, /* type */ - 2, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 26, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_26_PCREL", /* name */ - FALSE, /* partial_inplace */ - 0xffffff, /* src_mask */ - 0xffffff, /* dst_mask */ - TRUE), /* pcrel_offset */ + return status; +} - /* High 16 bits of address when lower 16 is or'd in. */ - HOWTO (R_M32R_HI16_ULO, /* type */ - 16, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - m32r_elf_hi16_reloc, /* special_function */ - "R_M32R_HI16_ULO", /* name */ - TRUE, /* partial_inplace */ - 0x0000ffff, /* src_mask */ - 0x0000ffff, /* dst_mask */ - FALSE), /* pcrel_offset */ +/* Handle the R_M32R_10_PCREL reloc. */ - /* High 16 bits of address when lower 16 is added in. */ - HOWTO (R_M32R_HI16_SLO, /* type */ - 16, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - m32r_elf_hi16_reloc, /* special_function */ - "R_M32R_HI16_SLO", /* name */ - TRUE, /* partial_inplace */ - 0x0000ffff, /* src_mask */ - 0x0000ffff, /* dst_mask */ - FALSE), /* pcrel_offset */ +static bfd_reloc_status_type +m32r_elf_10_pcrel_reloc (bfd * abfd, + arelent * reloc_entry, + asymbol * symbol, + void * data, + asection * input_section, + bfd * output_bfd, + char ** error_message ATTRIBUTE_UNUSED) +{ + /* This part is from bfd_elf_generic_reloc. */ + if (output_bfd != NULL + && (symbol->flags & BSF_SECTION_SYM) == 0 + && (! reloc_entry->howto->partial_inplace + || reloc_entry->addend == 0)) + { + reloc_entry->address += input_section->output_offset; + return bfd_reloc_ok; + } - /* Lower 16 bits of address. */ - HOWTO (R_M32R_LO16, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - m32r_elf_lo16_reloc, /* special_function */ - "R_M32R_LO16", /* name */ - TRUE, /* partial_inplace */ - 0x0000ffff, /* src_mask */ - 0x0000ffff, /* dst_mask */ - FALSE), /* pcrel_offset */ + if (output_bfd != NULL) + /* FIXME: See bfd_perform_relocation. Is this right? */ + return bfd_reloc_continue; - /* Small data area 16 bits offset. */ - HOWTO (R_M32R_SDA16, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - m32r_elf_sda16_reloc, /* special_function */ - "R_M32R_SDA16", /* name */ - TRUE, /* partial_inplace */ /* FIXME: correct? */ - 0x0000ffff, /* src_mask */ - 0x0000ffff, /* dst_mask */ - FALSE), /* pcrel_offset */ + return m32r_elf_do_10_pcrel_reloc (abfd, reloc_entry->howto, + input_section, + data, reloc_entry->address, + symbol->section, + (symbol->value + + symbol->section->output_section->vma + + symbol->section->output_offset), + reloc_entry->addend); +} - /* GNU extension to record C++ vtable hierarchy */ - HOWTO (R_M32R_GNU_VTINHERIT, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 0, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - NULL, /* special_function */ - "R_M32R_GNU_VTINHERIT", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE), /* pcrel_offset */ +/* Do generic partial_inplace relocation. + This is a local replacement for bfd_elf_generic_reloc. */ - /* GNU extension to record C++ vtable member usage */ - HOWTO (R_M32R_GNU_VTENTRY, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 0, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - _bfd_elf_rel_vtable_reloc_fn, /* special_function */ - "R_M32R_GNU_VTENTRY", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE), /* pcrel_offset */ +static bfd_reloc_status_type +m32r_elf_generic_reloc (bfd *input_bfd, + arelent *reloc_entry, + asymbol *symbol, + void * data, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) +{ + bfd_reloc_status_type ret; + bfd_vma relocation; + bfd_byte *inplace_address; - EMPTY_HOWTO (13), - EMPTY_HOWTO (14), - EMPTY_HOWTO (15), - EMPTY_HOWTO (16), - EMPTY_HOWTO (17), - EMPTY_HOWTO (18), - EMPTY_HOWTO (19), - EMPTY_HOWTO (20), - EMPTY_HOWTO (21), - EMPTY_HOWTO (22), - EMPTY_HOWTO (23), - EMPTY_HOWTO (24), - EMPTY_HOWTO (25), - EMPTY_HOWTO (26), - EMPTY_HOWTO (27), - EMPTY_HOWTO (28), - EMPTY_HOWTO (29), - EMPTY_HOWTO (30), - EMPTY_HOWTO (31), - EMPTY_HOWTO (32), + /* This part is from bfd_elf_generic_reloc. + If we're relocating, and this an external symbol, we don't want + to change anything. */ + if (output_bfd != NULL + && (symbol->flags & BSF_SECTION_SYM) == 0 + && reloc_entry->addend == 0) + { + reloc_entry->address += input_section->output_offset; + return bfd_reloc_ok; + } - /* A 16 bit absolute relocation. */ - HOWTO (R_M32R_16_RELA, /* type */ - 0, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_16_RELA", /* name */ - FALSE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xffff, /* dst_mask */ - FALSE), /* pcrel_offset */ + /* Now do the reloc in the usual way. + ??? It would be nice to call bfd_elf_generic_reloc here, + but we have partial_inplace set. bfd_elf_generic_reloc will + pass the handling back to bfd_install_relocation which will install + a section relative addend which is wrong. */ - /* A 32 bit absolute relocation. */ - HOWTO (R_M32R_32_RELA, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc,/* special_function */ - "R_M32R_32_RELA", /* name */ - FALSE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ - FALSE), /* pcrel_offset */ + /* Sanity check the address (offset in section). */ + if (reloc_entry->address > bfd_get_section_limit (input_bfd, input_section)) + return bfd_reloc_outofrange; - /* A 24 bit address. */ - HOWTO (R_M32R_24_RELA, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 24, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_unsigned, /* complain_on_overflow */ - bfd_elf_generic_reloc,/* special_function */ - "R_M32R_24_RELA", /* name */ - FALSE, /* partial_inplace */ - 0xffffff, /* src_mask */ - 0xffffff, /* dst_mask */ - FALSE), /* pcrel_offset */ + ret = bfd_reloc_ok; + if (bfd_is_und_section (symbol->section) + && output_bfd == NULL) + ret = bfd_reloc_undefined; - HOWTO (R_M32R_10_PCREL_RELA, /* type */ - 2, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 10, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - m32r_elf_10_pcrel_reloc, /* special_function */ - "R_M32R_10_PCREL_RELA",/* name */ - FALSE, /* partial_inplace */ - 0xff, /* src_mask */ - 0xff, /* dst_mask */ - TRUE), /* pcrel_offset */ + if (bfd_is_com_section (symbol->section) + || output_bfd != NULL) + relocation = 0; + else + relocation = symbol->value; - /* A relative 18 bit relocation, right shifted by 2. */ - HOWTO (R_M32R_18_PCREL_RELA, /* type */ - 2, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_18_PCREL_RELA",/* name */ - FALSE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xffff, /* dst_mask */ - TRUE), /* pcrel_offset */ + /* Only do this for a final link. */ + if (output_bfd == NULL) + { + relocation += symbol->section->output_section->vma; + relocation += symbol->section->output_offset; + } - /* A relative 26 bit relocation, right shifted by 2. */ - HOWTO (R_M32R_26_PCREL_RELA, /* type */ - 2, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 26, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_26_PCREL_RELA",/* name */ - FALSE, /* partial_inplace */ - 0xffffff, /* src_mask */ - 0xffffff, /* dst_mask */ - TRUE), /* pcrel_offset */ + relocation += reloc_entry->addend; + inplace_address = (bfd_byte *) data + reloc_entry->address; - /* High 16 bits of address when lower 16 is or'd in. */ - HOWTO (R_M32R_HI16_ULO_RELA, /* type */ - 16, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_HI16_ULO_RELA",/* name */ - FALSE, /* partial_inplace */ - 0x0000ffff, /* src_mask */ - 0x0000ffff, /* dst_mask */ - FALSE), /* pcrel_offset */ +#define DOIT(x) \ + x = ( (x & ~reloc_entry->howto->dst_mask) | \ + (((x & reloc_entry->howto->src_mask) + relocation) & \ + reloc_entry->howto->dst_mask)) - /* High 16 bits of address when lower 16 is added in. */ - HOWTO (R_M32R_HI16_SLO_RELA, /* type */ - 16, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_HI16_SLO_RELA",/* name */ - FALSE, /* partial_inplace */ - 0x0000ffff, /* src_mask */ - 0x0000ffff, /* dst_mask */ - FALSE), /* pcrel_offset */ + switch (reloc_entry->howto->size) + { + case 1: + { + short x = bfd_get_16 (input_bfd, inplace_address); + DOIT (x); + bfd_put_16 (input_bfd, (bfd_vma) x, inplace_address); + } + break; + case 2: + { + unsigned long x = bfd_get_32 (input_bfd, inplace_address); + DOIT (x); + bfd_put_32 (input_bfd, (bfd_vma)x , inplace_address); + } + break; + default: + BFD_ASSERT (0); + } - /* Lower 16 bits of address. */ - HOWTO (R_M32R_LO16_RELA, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_LO16_RELA", /* name */ - FALSE, /* partial_inplace */ - 0x0000ffff, /* src_mask */ - 0x0000ffff, /* dst_mask */ - FALSE), /* pcrel_offset */ + if (output_bfd != NULL) + reloc_entry->address += input_section->output_offset; - /* Small data area 16 bits offset. */ - HOWTO (R_M32R_SDA16_RELA, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_SDA16_RELA", /* name */ - TRUE, /* partial_inplace */ /* FIXME: correct? */ - 0x0000ffff, /* src_mask */ - 0x0000ffff, /* dst_mask */ - FALSE), /* pcrel_offset */ + return ret; +} - /* GNU extension to record C++ vtable hierarchy */ - HOWTO (R_M32R_RELA_GNU_VTINHERIT, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 0, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - NULL, /* special_function */ - "R_M32R_RELA_GNU_VTINHERIT", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE), /* pcrel_offset */ +/* Handle the R_M32R_SDA16 reloc. + This reloc is used to compute the address of objects in the small data area + and to perform loads and stores from that area. + The lower 16 bits are sign extended and added to the register specified + in the instruction, which is assumed to point to _SDA_BASE_. */ - /* GNU extension to record C++ vtable member usage */ - HOWTO (R_M32R_RELA_GNU_VTENTRY, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 0, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - _bfd_elf_rel_vtable_reloc_fn, /* special_function */ - "R_M32R_RELA_GNU_VTENTRY", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE), /* pcrel_offset */ +static bfd_reloc_status_type +m32r_elf_sda16_reloc (bfd *abfd ATTRIBUTE_UNUSED, + arelent *reloc_entry, + asymbol *symbol, + void * data ATTRIBUTE_UNUSED, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) +{ + /* This part is from bfd_elf_generic_reloc. */ + if (output_bfd != NULL + && (symbol->flags & BSF_SECTION_SYM) == 0 + && (! reloc_entry->howto->partial_inplace + || reloc_entry->addend == 0)) + { + reloc_entry->address += input_section->output_offset; + return bfd_reloc_ok; + } - EMPTY_HOWTO (45), - EMPTY_HOWTO (46), - EMPTY_HOWTO (47), + if (output_bfd != NULL) + /* FIXME: See bfd_perform_relocation. Is this right? */ + return bfd_reloc_continue; - /* Like R_M32R_24, but referring to the GOT table entry for - the symbol. */ - HOWTO (R_M32R_GOT24, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 24, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_unsigned, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_GOT24", /* name */ - FALSE, /* partial_inplace */ - 0xffffff, /* src_mask */ - 0xffffff, /* dst_mask */ - FALSE), /* pcrel_offset */ + /* FIXME: not sure what to do here yet. But then again, the linker + may never call us. */ + abort (); +} - /* Like R_M32R_PCREL, but referring to the procedure linkage table - entry for the symbol. */ - HOWTO (R_M32R_26_PLTREL, /* type */ - 2, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 24, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_26_PLTREL", /* name */ - FALSE, /* partial_inplace */ - 0xffffff, /* src_mask */ - 0xffffff, /* dst_mask */ - TRUE), /* pcrel_offset */ + +/* Handle the R_M32R_HI16_[SU]LO relocs. + HI16_SLO is for the add3 and load/store with displacement instructions. + HI16_ULO is for the or3 instruction. + For R_M32R_HI16_SLO, the lower 16 bits are sign extended when added to + the high 16 bytes so if the lower 16 bits are negative (bit 15 == 1) then + we must add one to the high 16 bytes (which will get subtracted off when + the low 16 bits are added). + These relocs have to be done in combination with an R_M32R_LO16 reloc + because there is a carry from the LO16 to the HI16. Here we just save + the information we need; we do the actual relocation when we see the LO16. + This code is copied from the elf32-mips.c. We also support an arbitrary + number of HI16 relocs to be associated with a single LO16 reloc. The + assembler sorts the relocs to ensure each HI16 immediately precedes its + LO16. However if there are multiple copies, the assembler may not find + the real LO16 so it picks the first one it finds. */ - /* This is used only by the dynamic linker. The symbol should exist - both in the object being run and in some shared library. The - dynamic linker copies the data addressed by the symbol from the - shared library into the object, because the object being - run has to have the data at some particular address. */ - HOWTO (R_M32R_COPY, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_COPY", /* name */ - FALSE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ - FALSE), /* pcrel_offset */ +struct m32r_hi16 +{ + struct m32r_hi16 *next; + bfd_byte *addr; + bfd_vma addend; +}; + +/* FIXME: This should not be a static variable. */ + +static struct m32r_hi16 *m32r_hi16_list; + +static bfd_reloc_status_type +m32r_elf_hi16_reloc (bfd *abfd ATTRIBUTE_UNUSED, + arelent *reloc_entry, + asymbol *symbol, + void * data, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) +{ + bfd_reloc_status_type ret; + bfd_vma relocation; + struct m32r_hi16 *n; + + /* This part is from bfd_elf_generic_reloc. + If we're relocating, and this an external symbol, we don't want + to change anything. */ + if (output_bfd != NULL + && (symbol->flags & BSF_SECTION_SYM) == 0 + && reloc_entry->addend == 0) + { + reloc_entry->address += input_section->output_offset; + return bfd_reloc_ok; + } + + /* Sanity check the address (offset in section). */ + if (reloc_entry->address > bfd_get_section_limit (abfd, input_section)) + return bfd_reloc_outofrange; + + ret = bfd_reloc_ok; + if (bfd_is_und_section (symbol->section) + && output_bfd == NULL) + ret = bfd_reloc_undefined; + + if (bfd_is_com_section (symbol->section)) + relocation = 0; + else + relocation = symbol->value; + + relocation += symbol->section->output_section->vma; + relocation += symbol->section->output_offset; + relocation += reloc_entry->addend; + + /* Save the information, and let LO16 do the actual relocation. */ + n = bfd_malloc ((bfd_size_type) sizeof *n); + if (n == NULL) + return bfd_reloc_outofrange; + n->addr = (bfd_byte *) data + reloc_entry->address; + n->addend = relocation; + n->next = m32r_hi16_list; + m32r_hi16_list = n; + + if (output_bfd != NULL) + reloc_entry->address += input_section->output_offset; + + return ret; +} + +/* Handle an M32R ELF HI16 reloc. */ + +static void +m32r_elf_relocate_hi16 (bfd *input_bfd, + int type, + Elf_Internal_Rela *relhi, + Elf_Internal_Rela *rello, + bfd_byte *contents, + bfd_vma addend) +{ + unsigned long insn; + bfd_vma addlo; + + insn = bfd_get_32 (input_bfd, contents + relhi->r_offset); + + addlo = bfd_get_32 (input_bfd, contents + rello->r_offset); + if (type == R_M32R_HI16_SLO) + addlo = ((addlo & 0xffff) ^ 0x8000) - 0x8000; + else + addlo &= 0xffff; + + addend += ((insn & 0xffff) << 16) + addlo; + + /* Reaccount for sign extension of low part. */ + if (type == R_M32R_HI16_SLO + && (addend & 0x8000) != 0) + addend += 0x10000; + + bfd_put_32 (input_bfd, + (insn & 0xffff0000) | ((addend >> 16) & 0xffff), + contents + relhi->r_offset); +} + +/* Do an R_M32R_LO16 relocation. This is a straightforward 16 bit + inplace relocation; this function exists in order to do the + R_M32R_HI16_[SU]LO relocation described above. */ + +static bfd_reloc_status_type +m32r_elf_lo16_reloc (bfd *input_bfd, + arelent *reloc_entry, + asymbol *symbol, + void * data, + asection *input_section, + bfd *output_bfd, + char **error_message) +{ + /* This part is from bfd_elf_generic_reloc. + If we're relocating, and this an external symbol, we don't want + to change anything. */ + if (output_bfd != NULL + && (symbol->flags & BSF_SECTION_SYM) == 0 + && reloc_entry->addend == 0) + { + reloc_entry->address += input_section->output_offset; + return bfd_reloc_ok; + } + + if (m32r_hi16_list != NULL) + { + struct m32r_hi16 *l; + + l = m32r_hi16_list; + while (l != NULL) + { + unsigned long insn; + unsigned long val; + unsigned long vallo; + struct m32r_hi16 *next; + + /* Do the HI16 relocation. Note that we actually don't need + to know anything about the LO16 itself, except where to + find the low 16 bits of the addend needed by the LO16. */ + insn = bfd_get_32 (input_bfd, l->addr); + vallo = ((bfd_get_32 (input_bfd, (bfd_byte *) data + reloc_entry->address) + & 0xffff) ^ 0x8000) - 0x8000; + val = ((insn & 0xffff) << 16) + vallo; + val += l->addend; + + /* Reaccount for sign extension of low part. */ + if ((val & 0x8000) != 0) + val += 0x10000; + + insn = (insn &~ (bfd_vma) 0xffff) | ((val >> 16) & 0xffff); + bfd_put_32 (input_bfd, (bfd_vma) insn, l->addr); + + next = l->next; + free (l); + l = next; + } - /* Like R_M32R_24, but used when setting global offset table - entries. */ - HOWTO (R_M32R_GLOB_DAT, /* type */ + m32r_hi16_list = NULL; + } + + /* Now do the LO16 reloc in the usual way. + ??? It would be nice to call bfd_elf_generic_reloc here, + but we have partial_inplace set. bfd_elf_generic_reloc will + pass the handling back to bfd_install_relocation which will install + a section relative addend which is wrong. */ + return m32r_elf_generic_reloc (input_bfd, reloc_entry, symbol, data, + input_section, output_bfd, error_message); +} + + +static reloc_howto_type m32r_elf_howto_table[] = +{ + /* This reloc does nothing. */ + HOWTO (R_M32R_NONE, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 32, /* bitsize */ FALSE, /* pc_relative */ 0, /* bitpos */ complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_GLOB_DAT", /* name */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_NONE", /* name */ FALSE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ + 0, /* src_mask */ + 0, /* dst_mask */ FALSE), /* pcrel_offset */ - /* Marks a procedure linkage table entry for a symbol. */ - HOWTO (R_M32R_JMP_SLOT, /* type */ + /* A 16 bit absolute relocation. */ + HOWTO (R_M32R_16, /* type */ 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ FALSE, /* pc_relative */ 0, /* bitpos */ complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_JMP_SLOT", /* name */ - FALSE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ + m32r_elf_generic_reloc,/* special_function */ + "R_M32R_16", /* name */ + TRUE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ FALSE), /* pcrel_offset */ - /* Used only by the dynamic linker. When the object is run, this - longword is set to the load address of the object, plus the - addend. */ - HOWTO (R_M32R_RELATIVE, /* type */ + /* A 32 bit absolute relocation. */ + HOWTO (R_M32R_32, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 32, /* bitsize */ FALSE, /* pc_relative */ 0, /* bitpos */ complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_RELATIVE", /* name */ - FALSE, /* partial_inplace */ + m32r_elf_generic_reloc,/* special_function */ + "R_M32R_32", /* name */ + TRUE, /* partial_inplace */ 0xffffffff, /* src_mask */ 0xffffffff, /* dst_mask */ FALSE), /* pcrel_offset */ - HOWTO (R_M32R_GOTOFF, /* type */ + /* A 24 bit address. */ + HOWTO (R_M32R_24, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 24, /* bitsize */ FALSE, /* pc_relative */ 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_GOTOFF", /* name */ - FALSE, /* partial_inplace */ + complain_overflow_unsigned, /* complain_on_overflow */ + m32r_elf_generic_reloc,/* special_function */ + "R_M32R_24", /* name */ + TRUE, /* partial_inplace */ 0xffffff, /* src_mask */ 0xffffff, /* dst_mask */ FALSE), /* pcrel_offset */ - /* An PC Relative 24-bit relocation used when setting PIC offset - table register. */ - HOWTO (R_M32R_GOTPC24, /* type */ - 0, /* rightshift */ + /* An PC Relative 10-bit relocation, shifted by 2. + This reloc is complicated because relocations are relative to pc & -4. + i.e. branches in the right insn slot use the address of the left insn + slot for pc. */ + /* ??? It's not clear whether this should have partial_inplace set or not. + Branch relaxing in the assembler can store the addend in the insn, + and if bfd_install_relocation gets called the addend may get added + again. */ + HOWTO (R_M32R_10_PCREL, /* type */ + 2, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 10, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + m32r_elf_10_pcrel_reloc, /* special_function */ + "R_M32R_10_PCREL", /* name */ + FALSE, /* partial_inplace */ + 0xff, /* src_mask */ + 0xff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* A relative 18 bit relocation, right shifted by 2. */ + HOWTO (R_M32R_18_PCREL, /* type */ + 2, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ - 24, /* bitsize */ + 16, /* bitsize */ TRUE, /* pc_relative */ 0, /* bitpos */ - complain_overflow_unsigned, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_GOTPC24", /* name */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_18_PCREL", /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* A relative 26 bit relocation, right shifted by 2. */ + /* ??? It's not clear whether this should have partial_inplace set or not. + Branch relaxing in the assembler can store the addend in the insn, + and if bfd_install_relocation gets called the addend may get added + again. */ + HOWTO (R_M32R_26_PCREL, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 26, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_26_PCREL", /* name */ FALSE, /* partial_inplace */ 0xffffff, /* src_mask */ 0xffffff, /* dst_mask */ TRUE), /* pcrel_offset */ - /* Like R_M32R_HI16_ULO, but referring to the GOT table entry for - the symbol. */ - HOWTO (R_M32R_GOT16_HI_ULO, /* type */ + /* High 16 bits of address when lower 16 is or'd in. */ + HOWTO (R_M32R_HI16_ULO, /* type */ 16, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 16, /* bitsize */ FALSE, /* pc_relative */ 0, /* bitpos */ complain_overflow_dont, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_GOT16_HI_ULO", /* name */ - FALSE, /* partial_inplace */ + m32r_elf_hi16_reloc, /* special_function */ + "R_M32R_HI16_ULO", /* name */ + TRUE, /* partial_inplace */ 0x0000ffff, /* src_mask */ 0x0000ffff, /* dst_mask */ FALSE), /* pcrel_offset */ - /* Like R_M32R_HI16_SLO, but referring to the GOT table entry for - the symbol. */ - HOWTO (R_M32R_GOT16_HI_SLO, /* type */ + /* High 16 bits of address when lower 16 is added in. */ + HOWTO (R_M32R_HI16_SLO, /* type */ 16, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 16, /* bitsize */ FALSE, /* pc_relative */ 0, /* bitpos */ complain_overflow_dont, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_GOT16_HI_SLO", /* name */ - FALSE, /* partial_inplace */ + m32r_elf_hi16_reloc, /* special_function */ + "R_M32R_HI16_SLO", /* name */ + TRUE, /* partial_inplace */ 0x0000ffff, /* src_mask */ 0x0000ffff, /* dst_mask */ FALSE), /* pcrel_offset */ - /* Like R_M32R_LO16, but referring to the GOT table entry for - the symbol. */ - HOWTO (R_M32R_GOT16_LO, /* type */ + /* Lower 16 bits of address. */ + HOWTO (R_M32R_LO16, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 16, /* bitsize */ FALSE, /* pc_relative */ 0, /* bitpos */ complain_overflow_dont, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_GOT16_LO", /* name */ - FALSE, /* partial_inplace */ + m32r_elf_lo16_reloc, /* special_function */ + "R_M32R_LO16", /* name */ + TRUE, /* partial_inplace */ 0x0000ffff, /* src_mask */ 0x0000ffff, /* dst_mask */ FALSE), /* pcrel_offset */ - /* An PC Relative relocation used when setting PIC offset table register. - Like R_M32R_HI16_ULO, but referring to the GOT table entry for - the symbol. */ - HOWTO (R_M32R_GOTPC_HI_ULO, /* type */ - 16, /* rightshift */ + /* Small data area 16 bits offset. */ + HOWTO (R_M32R_SDA16, /* type */ + 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 16, /* bitsize */ FALSE, /* pc_relative */ 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_GOTPC_HI_ULO", /* name */ - FALSE, /* partial_inplace */ + complain_overflow_signed, /* complain_on_overflow */ + m32r_elf_sda16_reloc, /* special_function */ + "R_M32R_SDA16", /* name */ + TRUE, /* partial_inplace */ /* FIXME: correct? */ 0x0000ffff, /* src_mask */ 0x0000ffff, /* dst_mask */ - TRUE), /* pcrel_offset */ + FALSE), /* pcrel_offset */ - /* An PC Relative relocation used when setting PIC offset table register. - Like R_M32R_HI16_SLO, but referring to the GOT table entry for - the symbol. */ - HOWTO (R_M32R_GOTPC_HI_SLO, /* type */ - 16, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ + /* GNU extension to record C++ vtable hierarchy. */ + HOWTO (R_M32R_GNU_VTINHERIT, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 0, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + NULL, /* special_function */ + "R_M32R_GNU_VTINHERIT", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* GNU extension to record C++ vtable member usage. */ + HOWTO (R_M32R_GNU_VTENTRY, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 0, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_elf_rel_vtable_reloc_fn, /* special_function */ + "R_M32R_GNU_VTENTRY", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + FALSE), /* pcrel_offset */ + + EMPTY_HOWTO (13), + EMPTY_HOWTO (14), + EMPTY_HOWTO (15), + EMPTY_HOWTO (16), + EMPTY_HOWTO (17), + EMPTY_HOWTO (18), + EMPTY_HOWTO (19), + EMPTY_HOWTO (20), + EMPTY_HOWTO (21), + EMPTY_HOWTO (22), + EMPTY_HOWTO (23), + EMPTY_HOWTO (24), + EMPTY_HOWTO (25), + EMPTY_HOWTO (26), + EMPTY_HOWTO (27), + EMPTY_HOWTO (28), + EMPTY_HOWTO (29), + EMPTY_HOWTO (30), + EMPTY_HOWTO (31), + EMPTY_HOWTO (32), + + /* A 16 bit absolute relocation. */ + HOWTO (R_M32R_16_RELA, /* type */ + 0, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ 16, /* bitsize */ FALSE, /* pc_relative */ 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ + complain_overflow_bitfield, /* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ - "R_M32R_GOTPC_HI_SLO", /* name */ + "R_M32R_16_RELA", /* name */ FALSE, /* partial_inplace */ - 0x0000ffff, /* src_mask */ - 0x0000ffff, /* dst_mask */ - TRUE), /* pcrel_offset */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* A 32 bit absolute relocation. */ + HOWTO (R_M32R_32_RELA, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc,/* special_function */ + "R_M32R_32_RELA", /* name */ + FALSE, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ - /* An PC Relative relocation used when setting PIC offset table register. - Like R_M32R_LO16, but referring to the GOT table entry for - the symbol. */ - HOWTO (R_M32R_GOTPC_LO, /* type */ + /* A 24 bit address. */ + HOWTO (R_M32R_24_RELA, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ + 24, /* bitsize */ FALSE, /* pc_relative */ 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_M32R_GOTPC_LO", /* name */ + complain_overflow_unsigned, /* complain_on_overflow */ + bfd_elf_generic_reloc,/* special_function */ + "R_M32R_24_RELA", /* name */ FALSE, /* partial_inplace */ - 0x0000ffff, /* src_mask */ - 0x0000ffff, /* dst_mask */ + 0xffffff, /* src_mask */ + 0xffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + HOWTO (R_M32R_10_PCREL_RELA, /* type */ + 2, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 10, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + m32r_elf_10_pcrel_reloc, /* special_function */ + "R_M32R_10_PCREL_RELA",/* name */ + FALSE, /* partial_inplace */ + 0xff, /* src_mask */ + 0xff, /* dst_mask */ TRUE), /* pcrel_offset */ - HOWTO (R_M32R_GOTOFF_HI_ULO, /* type */ - 16, /* rightshift */ + /* A relative 18 bit relocation, right shifted by 2. */ + HOWTO (R_M32R_18_PCREL_RELA, /* type */ + 2, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 16, /* bitsize */ - FALSE, /* pc_relative */ + TRUE, /* pc_relative */ 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ + complain_overflow_signed, /* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ - "R_M32R_GOTOFF_HI_ULO",/* name */ + "R_M32R_18_PCREL_RELA",/* name */ FALSE, /* partial_inplace */ - 0x0000ffff, /* src_mask */ - 0x0000ffff, /* dst_mask */ - FALSE), /* pcrel_offset */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE), /* pcrel_offset */ - HOWTO (R_M32R_GOTOFF_HI_SLO, /* type */ - 16, /* rightshift */ + /* A relative 26 bit relocation, right shifted by 2. */ + HOWTO (R_M32R_26_PCREL_RELA, /* type */ + 2, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ + 26, /* bitsize */ + TRUE, /* pc_relative */ 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ + complain_overflow_signed, /* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ - "R_M32R_GOTOFF_HI_SLO",/* name */ + "R_M32R_26_PCREL_RELA",/* name */ FALSE, /* partial_inplace */ - 0x0000ffff, /* src_mask */ - 0x0000ffff, /* dst_mask */ - FALSE), /* pcrel_offset */ + 0xffffff, /* src_mask */ + 0xffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ - HOWTO (R_M32R_GOTOFF_LO, /* type */ - 0, /* rightshift */ + /* High 16 bits of address when lower 16 is or'd in. */ + HOWTO (R_M32R_HI16_ULO_RELA, /* type */ + 16, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 16, /* bitsize */ FALSE, /* pc_relative */ 0, /* bitpos */ complain_overflow_dont, /* complain_on_overflow */ bfd_elf_generic_reloc, /* special_function */ - "R_M32R_GOTOFF_LO", /* name */ + "R_M32R_HI16_ULO_RELA",/* name */ FALSE, /* partial_inplace */ 0x0000ffff, /* src_mask */ 0x0000ffff, /* dst_mask */ - FALSE), /* pcrel_offset */ -}; - -/* Handle the R_M32R_10_PCREL reloc. */ - -static bfd_reloc_status_type -m32r_elf_10_pcrel_reloc (abfd, reloc_entry, symbol, data, - input_section, output_bfd, error_message) - bfd * abfd; - arelent * reloc_entry; - asymbol * symbol; - PTR data; - asection * input_section; - bfd * output_bfd; - char ** error_message ATTRIBUTE_UNUSED; -{ - /* This part is from bfd_elf_generic_reloc. */ - if (output_bfd != (bfd *) NULL - && (symbol->flags & BSF_SECTION_SYM) == 0 - && (! reloc_entry->howto->partial_inplace - || reloc_entry->addend == 0)) - { - reloc_entry->address += input_section->output_offset; - return bfd_reloc_ok; - } - - if (output_bfd != NULL) - { - /* FIXME: See bfd_perform_relocation. Is this right? */ - return bfd_reloc_continue; - } - - return m32r_elf_do_10_pcrel_reloc (abfd, reloc_entry->howto, - input_section, - data, reloc_entry->address, - symbol->section, - (symbol->value - + symbol->section->output_section->vma - + symbol->section->output_offset), - reloc_entry->addend); -} - -/* Utility to actually perform an R_M32R_10_PCREL reloc. */ - -static bfd_reloc_status_type -m32r_elf_do_10_pcrel_reloc (abfd, howto, input_section, data, offset, - symbol_section, symbol_value, addend) - bfd *abfd; - reloc_howto_type *howto; - asection *input_section; - bfd_byte *data; - bfd_vma offset; - asection *symbol_section ATTRIBUTE_UNUSED; - bfd_vma symbol_value; - bfd_vma addend; -{ - bfd_signed_vma relocation; - unsigned long x; - bfd_reloc_status_type status; - - /* Sanity check the address (offset in section). */ - if (offset > bfd_get_section_limit (abfd, input_section)) - return bfd_reloc_outofrange; - - relocation = symbol_value + addend; - /* Make it pc relative. */ - relocation -= (input_section->output_section->vma - + input_section->output_offset); - /* These jumps mask off the lower two bits of the current address - before doing pcrel calculations. */ - relocation -= (offset & -(bfd_vma) 4); - - if (relocation < -0x200 || relocation > 0x1ff) - status = bfd_reloc_overflow; - else - status = bfd_reloc_ok; - - x = bfd_get_16 (abfd, data + offset); - relocation >>= howto->rightshift; - relocation <<= howto->bitpos; - x = (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask); - bfd_put_16 (abfd, (bfd_vma) x, data + offset); - - return status; -} - -/* Handle the R_M32R_HI16_[SU]LO relocs. - HI16_SLO is for the add3 and load/store with displacement instructions. - HI16_ULO is for the or3 instruction. - For R_M32R_HI16_SLO, the lower 16 bits are sign extended when added to - the high 16 bytes so if the lower 16 bits are negative (bit 15 == 1) then - we must add one to the high 16 bytes (which will get subtracted off when - the low 16 bits are added). - These relocs have to be done in combination with an R_M32R_LO16 reloc - because there is a carry from the LO16 to the HI16. Here we just save - the information we need; we do the actual relocation when we see the LO16. - This code is copied from the elf32-mips.c. We also support an arbitrary - number of HI16 relocs to be associated with a single LO16 reloc. The - assembler sorts the relocs to ensure each HI16 immediately precedes its - LO16. However if there are multiple copies, the assembler may not find - the real LO16 so it picks the first one it finds. */ - -struct m32r_hi16 -{ - struct m32r_hi16 *next; - bfd_byte *addr; - bfd_vma addend; -}; - -/* FIXME: This should not be a static variable. */ - -static struct m32r_hi16 *m32r_hi16_list; - -static bfd_reloc_status_type -m32r_elf_hi16_reloc (abfd, reloc_entry, symbol, data, - input_section, output_bfd, error_message) - bfd *abfd ATTRIBUTE_UNUSED; - arelent *reloc_entry; - asymbol *symbol; - PTR data; - asection *input_section; - bfd *output_bfd; - char **error_message ATTRIBUTE_UNUSED; -{ - bfd_reloc_status_type ret; - bfd_vma relocation; - struct m32r_hi16 *n; - - /* This part is from bfd_elf_generic_reloc. - If we're relocating, and this an external symbol, we don't want - to change anything. */ - if (output_bfd != (bfd *) NULL - && (symbol->flags & BSF_SECTION_SYM) == 0 - && reloc_entry->addend == 0) - { - reloc_entry->address += input_section->output_offset; - return bfd_reloc_ok; - } - - /* Sanity check the address (offset in section). */ - if (reloc_entry->address > bfd_get_section_limit (abfd, input_section)) - return bfd_reloc_outofrange; - - ret = bfd_reloc_ok; - if (bfd_is_und_section (symbol->section) - && output_bfd == (bfd *) NULL) - ret = bfd_reloc_undefined; - - if (bfd_is_com_section (symbol->section)) - relocation = 0; - else - relocation = symbol->value; - - relocation += symbol->section->output_section->vma; - relocation += symbol->section->output_offset; - relocation += reloc_entry->addend; - - /* Save the information, and let LO16 do the actual relocation. */ - n = (struct m32r_hi16 *) bfd_malloc ((bfd_size_type) sizeof *n); - if (n == NULL) - return bfd_reloc_outofrange; - n->addr = (bfd_byte *) data + reloc_entry->address; - n->addend = relocation; - n->next = m32r_hi16_list; - m32r_hi16_list = n; - - if (output_bfd != (bfd *) NULL) - reloc_entry->address += input_section->output_offset; - - return ret; -} - -/* Handle an M32R ELF HI16 reloc. */ - -static void -m32r_elf_relocate_hi16 (input_bfd, type, relhi, rello, contents, addend) - bfd *input_bfd; - int type; - Elf_Internal_Rela *relhi; - Elf_Internal_Rela *rello; - bfd_byte *contents; - bfd_vma addend; -{ - unsigned long insn; - bfd_vma addlo; - - insn = bfd_get_32 (input_bfd, contents + relhi->r_offset); - - addlo = bfd_get_32 (input_bfd, contents + rello->r_offset); - if (type == R_M32R_HI16_SLO) - addlo = ((addlo & 0xffff) ^ 0x8000) - 0x8000; - else - addlo &= 0xffff; - - addend += ((insn & 0xffff) << 16) + addlo; - - /* Reaccount for sign extension of low part. */ - if (type == R_M32R_HI16_SLO - && (addend & 0x8000) != 0) - addend += 0x10000; - - bfd_put_32 (input_bfd, - (insn & 0xffff0000) | ((addend >> 16) & 0xffff), - contents + relhi->r_offset); -} - -/* Do an R_M32R_LO16 relocation. This is a straightforward 16 bit - inplace relocation; this function exists in order to do the - R_M32R_HI16_[SU]LO relocation described above. */ - -bfd_reloc_status_type -m32r_elf_lo16_reloc (input_bfd, reloc_entry, symbol, data, - input_section, output_bfd, error_message) - bfd *input_bfd; - arelent *reloc_entry; - asymbol *symbol; - PTR data; - asection *input_section; - bfd *output_bfd; - char **error_message; -{ - /* This part is from bfd_elf_generic_reloc. - If we're relocating, and this an external symbol, we don't want - to change anything. */ - if (output_bfd != (bfd *) NULL - && (symbol->flags & BSF_SECTION_SYM) == 0 - && reloc_entry->addend == 0) - { - reloc_entry->address += input_section->output_offset; - return bfd_reloc_ok; - } + FALSE), /* pcrel_offset */ - if (m32r_hi16_list != NULL) - { - struct m32r_hi16 *l; + /* High 16 bits of address when lower 16 is added in. */ + HOWTO (R_M32R_HI16_SLO_RELA, /* type */ + 16, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_HI16_SLO_RELA",/* name */ + FALSE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ - l = m32r_hi16_list; - while (l != NULL) - { - unsigned long insn; - unsigned long val; - unsigned long vallo; - struct m32r_hi16 *next; + /* Lower 16 bits of address. */ + HOWTO (R_M32R_LO16_RELA, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_LO16_RELA", /* name */ + FALSE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ - /* Do the HI16 relocation. Note that we actually don't need - to know anything about the LO16 itself, except where to - find the low 16 bits of the addend needed by the LO16. */ - insn = bfd_get_32 (input_bfd, l->addr); - vallo = ((bfd_get_32 (input_bfd, (bfd_byte *) data + reloc_entry->address) - & 0xffff) ^ 0x8000) - 0x8000; - val = ((insn & 0xffff) << 16) + vallo; - val += l->addend; + /* Small data area 16 bits offset. */ + HOWTO (R_M32R_SDA16_RELA, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_SDA16_RELA", /* name */ + TRUE, /* partial_inplace */ /* FIXME: correct? */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ - /* Reaccount for sign extension of low part. */ - if ((val & 0x8000) != 0) - val += 0x10000; + /* GNU extension to record C++ vtable hierarchy. */ + HOWTO (R_M32R_RELA_GNU_VTINHERIT, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 0, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + NULL, /* special_function */ + "R_M32R_RELA_GNU_VTINHERIT", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + FALSE), /* pcrel_offset */ - insn = (insn &~ (bfd_vma) 0xffff) | ((val >> 16) & 0xffff); - bfd_put_32 (input_bfd, (bfd_vma) insn, l->addr); + /* GNU extension to record C++ vtable member usage. */ + HOWTO (R_M32R_RELA_GNU_VTENTRY, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 0, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_elf_rel_vtable_reloc_fn, /* special_function */ + "R_M32R_RELA_GNU_VTENTRY", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + FALSE), /* pcrel_offset */ - next = l->next; - free (l); - l = next; - } + /* A 32 bit PC relative relocation. */ + HOWTO (R_M32R_REL32, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc,/* special_function */ + "R_M32R_REL32", /* name */ + FALSE, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ - m32r_hi16_list = NULL; - } + EMPTY_HOWTO (46), + EMPTY_HOWTO (47), - /* Now do the LO16 reloc in the usual way. - ??? It would be nice to call bfd_elf_generic_reloc here, - but we have partial_inplace set. bfd_elf_generic_reloc will - pass the handling back to bfd_install_relocation which will install - a section relative addend which is wrong. */ - return m32r_elf_generic_reloc (input_bfd, reloc_entry, symbol, data, - input_section, output_bfd, error_message); -} + /* Like R_M32R_24, but referring to the GOT table entry for + the symbol. */ + HOWTO (R_M32R_GOT24, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 24, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_GOT24", /* name */ + FALSE, /* partial_inplace */ + 0xffffff, /* src_mask */ + 0xffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ -/* Do generic partial_inplace relocation. - This is a local replacement for bfd_elf_generic_reloc. */ + /* Like R_M32R_PCREL, but referring to the procedure linkage table + entry for the symbol. */ + HOWTO (R_M32R_26_PLTREL, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 24, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_26_PLTREL", /* name */ + FALSE, /* partial_inplace */ + 0xffffff, /* src_mask */ + 0xffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ -bfd_reloc_status_type -m32r_elf_generic_reloc (input_bfd, reloc_entry, symbol, data, - input_section, output_bfd, error_message) - bfd *input_bfd; - arelent *reloc_entry; - asymbol *symbol; - PTR data; - asection *input_section; - bfd *output_bfd; - char **error_message ATTRIBUTE_UNUSED; -{ - bfd_reloc_status_type ret; - bfd_vma relocation; - bfd_byte *inplace_address; + /* This is used only by the dynamic linker. The symbol should exist + both in the object being run and in some shared library. The + dynamic linker copies the data addressed by the symbol from the + shared library into the object, because the object being + run has to have the data at some particular address. */ + HOWTO (R_M32R_COPY, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_COPY", /* name */ + FALSE, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ - /* This part is from bfd_elf_generic_reloc. - If we're relocating, and this an external symbol, we don't want - to change anything. */ - if (output_bfd != (bfd *) NULL - && (symbol->flags & BSF_SECTION_SYM) == 0 - && reloc_entry->addend == 0) - { - reloc_entry->address += input_section->output_offset; - return bfd_reloc_ok; - } + /* Like R_M32R_24, but used when setting global offset table + entries. */ + HOWTO (R_M32R_GLOB_DAT, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_GLOB_DAT", /* name */ + FALSE, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ - /* Now do the reloc in the usual way. - ??? It would be nice to call bfd_elf_generic_reloc here, - but we have partial_inplace set. bfd_elf_generic_reloc will - pass the handling back to bfd_install_relocation which will install - a section relative addend which is wrong. */ + /* Marks a procedure linkage table entry for a symbol. */ + HOWTO (R_M32R_JMP_SLOT, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_JMP_SLOT", /* name */ + FALSE, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ - /* Sanity check the address (offset in section). */ - if (reloc_entry->address > bfd_get_section_limit (input_bfd, input_section)) - return bfd_reloc_outofrange; + /* Used only by the dynamic linker. When the object is run, this + longword is set to the load address of the object, plus the + addend. */ + HOWTO (R_M32R_RELATIVE, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_RELATIVE", /* name */ + FALSE, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ - ret = bfd_reloc_ok; - if (bfd_is_und_section (symbol->section) - && output_bfd == (bfd *) NULL) - ret = bfd_reloc_undefined; + HOWTO (R_M32R_GOTOFF, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 24, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_GOTOFF", /* name */ + FALSE, /* partial_inplace */ + 0xffffff, /* src_mask */ + 0xffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ - if (bfd_is_com_section (symbol->section) - || output_bfd != (bfd *) NULL) - relocation = 0; - else - relocation = symbol->value; + /* An PC Relative 24-bit relocation used when setting PIC offset + table register. */ + HOWTO (R_M32R_GOTPC24, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 24, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_GOTPC24", /* name */ + FALSE, /* partial_inplace */ + 0xffffff, /* src_mask */ + 0xffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ - /* Only do this for a final link. */ - if (output_bfd == (bfd *) NULL) - { - relocation += symbol->section->output_section->vma; - relocation += symbol->section->output_offset; - } + /* Like R_M32R_HI16_ULO, but referring to the GOT table entry for + the symbol. */ + HOWTO (R_M32R_GOT16_HI_ULO, /* type */ + 16, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_GOT16_HI_ULO", /* name */ + FALSE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ - relocation += reloc_entry->addend; - inplace_address = (bfd_byte *) data + reloc_entry->address; + /* Like R_M32R_HI16_SLO, but referring to the GOT table entry for + the symbol. */ + HOWTO (R_M32R_GOT16_HI_SLO, /* type */ + 16, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_GOT16_HI_SLO", /* name */ + FALSE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ -#define DOIT(x) \ - x = ( (x & ~reloc_entry->howto->dst_mask) | \ - (((x & reloc_entry->howto->src_mask) + relocation) & \ - reloc_entry->howto->dst_mask)) + /* Like R_M32R_LO16, but referring to the GOT table entry for + the symbol. */ + HOWTO (R_M32R_GOT16_LO, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_GOT16_LO", /* name */ + FALSE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ - switch (reloc_entry->howto->size) - { - case 1: - { - short x = bfd_get_16 (input_bfd, inplace_address); - DOIT (x); - bfd_put_16 (input_bfd, (bfd_vma) x, inplace_address); - } - break; - case 2: - { - unsigned long x = bfd_get_32 (input_bfd, inplace_address); - DOIT (x); - bfd_put_32 (input_bfd, (bfd_vma)x , inplace_address); - } - break; - default: - BFD_ASSERT (0); - } + /* An PC Relative relocation used when setting PIC offset table register. + Like R_M32R_HI16_ULO, but referring to the GOT table entry for + the symbol. */ + HOWTO (R_M32R_GOTPC_HI_ULO, /* type */ + 16, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_GOTPC_HI_ULO", /* name */ + FALSE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ - if (output_bfd != (bfd *) NULL) - reloc_entry->address += input_section->output_offset; + /* An PC Relative relocation used when setting PIC offset table register. + Like R_M32R_HI16_SLO, but referring to the GOT table entry for + the symbol. */ + HOWTO (R_M32R_GOTPC_HI_SLO, /* type */ + 16, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_GOTPC_HI_SLO", /* name */ + FALSE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ - return ret; -} + /* An PC Relative relocation used when setting PIC offset table register. + Like R_M32R_LO16, but referring to the GOT table entry for + the symbol. */ + HOWTO (R_M32R_GOTPC_LO, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_GOTPC_LO", /* name */ + FALSE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ -/* Handle the R_M32R_SDA16 reloc. - This reloc is used to compute the address of objects in the small data area - and to perform loads and stores from that area. - The lower 16 bits are sign extended and added to the register specified - in the instruction, which is assumed to point to _SDA_BASE_. */ + HOWTO (R_M32R_GOTOFF_HI_ULO, /* type */ + 16, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_GOTOFF_HI_ULO",/* name */ + FALSE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ -static bfd_reloc_status_type -m32r_elf_sda16_reloc (abfd, reloc_entry, symbol, data, - input_section, output_bfd, error_message) - bfd *abfd ATTRIBUTE_UNUSED; - arelent *reloc_entry; - asymbol *symbol; - PTR data ATTRIBUTE_UNUSED; - asection *input_section; - bfd *output_bfd; - char **error_message ATTRIBUTE_UNUSED; -{ - /* This part is from bfd_elf_generic_reloc. */ - if (output_bfd != (bfd *) NULL - && (symbol->flags & BSF_SECTION_SYM) == 0 - && (! reloc_entry->howto->partial_inplace - || reloc_entry->addend == 0)) - { - reloc_entry->address += input_section->output_offset; - return bfd_reloc_ok; - } + HOWTO (R_M32R_GOTOFF_HI_SLO, /* type */ + 16, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_GOTOFF_HI_SLO",/* name */ + FALSE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ - if (output_bfd != NULL) - { - /* FIXME: See bfd_perform_relocation. Is this right? */ - return bfd_reloc_continue; - } + HOWTO (R_M32R_GOTOFF_LO, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_M32R_GOTOFF_LO", /* name */ + FALSE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ +}; - /* FIXME: not sure what to do here yet. But then again, the linker - may never call us. */ - abort (); -} - /* Map BFD reloc types to M32R ELF reloc types. */ struct m32r_reloc_map @@ -1287,6 +1207,7 @@ static const struct m32r_reloc_map m32r_ { BFD_RELOC_M32R_SDA16, R_M32R_SDA16_RELA }, { BFD_RELOC_VTABLE_INHERIT, R_M32R_RELA_GNU_VTINHERIT }, { BFD_RELOC_VTABLE_ENTRY, R_M32R_RELA_GNU_VTENTRY }, + { BFD_RELOC_32_PCREL, R_M32R_REL32 }, { BFD_RELOC_M32R_GOT24, R_M32R_GOT24 }, { BFD_RELOC_M32R_26_PLTREL, R_M32R_26_PLTREL }, @@ -1309,9 +1230,8 @@ static const struct m32r_reloc_map m32r_ #endif static reloc_howto_type * -bfd_elf32_bfd_reloc_type_lookup (abfd, code) - bfd *abfd ATTRIBUTE_UNUSED; - bfd_reloc_code_real_type code; +bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) { unsigned int i; @@ -1319,19 +1239,16 @@ bfd_elf32_bfd_reloc_type_lookup (abfd, c for (i = 0; i < sizeof (m32r_reloc_map_old) / sizeof (struct m32r_reloc_map); i++) - { - if (m32r_reloc_map_old[i].bfd_reloc_val == code) - return &m32r_elf_howto_table[m32r_reloc_map_old[i].elf_reloc_val]; - } + if (m32r_reloc_map_old[i].bfd_reloc_val == code) + return &m32r_elf_howto_table[m32r_reloc_map_old[i].elf_reloc_val]; + #else /* ! USE_M32R_OLD_RELOC */ for (i = 0; i < sizeof (m32r_reloc_map) / sizeof (struct m32r_reloc_map); i++) - { - if (m32r_reloc_map[i].bfd_reloc_val == code) - return &m32r_elf_howto_table[m32r_reloc_map[i].elf_reloc_val]; - } + if (m32r_reloc_map[i].bfd_reloc_val == code) + return &m32r_elf_howto_table[m32r_reloc_map[i].elf_reloc_val]; #endif return NULL; @@ -1340,10 +1257,9 @@ bfd_elf32_bfd_reloc_type_lookup (abfd, c /* Set the howto pointer for an M32R ELF reloc. */ static void -m32r_info_to_howto_rel (abfd, cache_ptr, dst) - bfd *abfd ATTRIBUTE_UNUSED; - arelent *cache_ptr; - Elf_Internal_Rela *dst; +m32r_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED, + arelent *cache_ptr, + Elf_Internal_Rela *dst) { unsigned int r_type; @@ -1353,10 +1269,9 @@ m32r_info_to_howto_rel (abfd, cache_ptr, } static void -m32r_info_to_howto (abfd, cache_ptr, dst) - bfd *abfd ATTRIBUTE_UNUSED; - arelent *cache_ptr; - Elf_Internal_Rela *dst; +m32r_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED, + arelent *cache_ptr, + Elf_Internal_Rela *dst) { BFD_ASSERT ((ELF32_R_TYPE(dst->r_info) == (unsigned int) R_M32R_NONE) || ((ELF32_R_TYPE(dst->r_info) > (unsigned int) R_M32R_GNU_VTENTRY) @@ -1368,11 +1283,10 @@ m32r_info_to_howto (abfd, cache_ptr, dst /* Given a BFD section, try to locate the corresponding ELF section index. */ -bfd_boolean -_bfd_m32r_elf_section_from_bfd_section (abfd, sec, retval) - bfd *abfd ATTRIBUTE_UNUSED; - asection *sec; - int *retval; +static bfd_boolean +_bfd_m32r_elf_section_from_bfd_section (bfd *abfd ATTRIBUTE_UNUSED, + asection *sec, + int *retval) { if (strcmp (bfd_get_section_name (abfd, sec), ".scommon") == 0) { @@ -1394,14 +1308,10 @@ static asymbol *m32r_elf_scom_symbol_ptr /* Handle the special M32R section numbers that a symbol may use. */ -void -_bfd_m32r_elf_symbol_processing (abfd, asym) - bfd *abfd ATTRIBUTE_UNUSED; - asymbol *asym; +static void +_bfd_m32r_elf_symbol_processing (bfd *abfd ATTRIBUTE_UNUSED, asymbol *asym) { - elf_symbol_type *elfsym; - - elfsym = (elf_symbol_type *) asym; + elf_symbol_type *elfsym = (elf_symbol_type *) asym; switch (elfsym->internal_elf_sym.st_shndx) { @@ -1431,14 +1341,13 @@ _bfd_m32r_elf_symbol_processing (abfd, a linker sections. */ static bfd_boolean -m32r_elf_add_symbol_hook (abfd, info, sym, namep, flagsp, secp, valp) - bfd *abfd; - struct bfd_link_info *info; - Elf_Internal_Sym *sym; - const char **namep; - flagword *flagsp ATTRIBUTE_UNUSED; - asection **secp; - bfd_vma *valp; +m32r_elf_add_symbol_hook (bfd *abfd, + struct bfd_link_info *info, + Elf_Internal_Sym *sym, + const char **namep, + flagword *flagsp ATTRIBUTE_UNUSED, + asection **secp, + bfd_vma *valp) { if (! info->relocatable && (*namep)[0] == '_' && (*namep)[1] == 'S' @@ -1455,7 +1364,6 @@ m32r_elf_add_symbol_hook (abfd, info, sy asection *s = bfd_get_section_by_name (abfd, ".sdata"); /* The following code was cobbled from elf32-ppc.c and elflink.c. */ - if (s == NULL) { flagword flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS @@ -1478,7 +1386,7 @@ m32r_elf_add_symbol_hook (abfd, info, sy BSF_GLOBAL, s, (bfd_vma) 32768, - (const char *) NULL, + NULL, FALSE, get_elf_backend_data (abfd)->collect, &bh))) @@ -1506,19 +1414,17 @@ m32r_elf_add_symbol_hook (abfd, info, sy external symbol if we are producing relocatable output. */ static bfd_reloc_status_type -m32r_elf_final_sda_base (output_bfd, info, error_message, psb) - bfd *output_bfd; - struct bfd_link_info *info; - const char **error_message; - bfd_vma *psb; +m32r_elf_final_sda_base (bfd *output_bfd, + struct bfd_link_info *info, + const char **error_message, + bfd_vma *psb) { if (elf_gp (output_bfd) == 0) { struct bfd_link_hash_entry *h; h = bfd_link_hash_lookup (info->hash, "_SDA_BASE_", FALSE, FALSE, TRUE); - if (h != (struct bfd_link_hash_entry *) NULL - && h->type == bfd_link_hash_defined) + if (h != NULL && h->type == bfd_link_hash_defined) elf_gp (output_bfd) = (h->u.def.value + h->u.def.section->output_section->vma + h->u.def.section->output_offset); @@ -1586,11 +1492,6 @@ struct elf_m32r_link_hash_entry /* Track dynamic relocs copied for this symbol. */ struct elf_m32r_dyn_relocs *dyn_relocs; - -// bfd_signed_vma gotplt_refcount; - - /* Number of PC relative relocs copied for this symbol. */ - /* struct elf_m32r_pcrel_relocs_copied *pcrel_relocs_copied; FIXME */ }; /* m32r ELF linker hash table. */ @@ -1617,7 +1518,7 @@ struct elf_m32r_link_hash_table #define m32r_elf_link_hash_traverse(table, func, info) \ (elf_link_hash_traverse \ (&(table)->root, \ - (bfd_boolean (*) PARAMS ((struct elf_link_hash_entry *, PTR))) (func), \ + (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \ (info))) /* Get the m32r ELF linker hash table from a link_info structure. */ @@ -1627,57 +1528,48 @@ struct elf_m32r_link_hash_table ((struct elf_m32r_link_hash_table *) ((p)->hash)) /* Create an entry in an m32r ELF linker hash table. */ -static struct bfd_hash_entry * -m32r_elf_link_hash_newfunc (struct bfd_hash_entry *, struct bfd_hash_table *, - const char * ); static struct bfd_hash_entry * -m32r_elf_link_hash_newfunc (entry, table, string) - struct bfd_hash_entry *entry; - struct bfd_hash_table *table; - const char *string; +m32r_elf_link_hash_newfunc (struct bfd_hash_entry *entry, + struct bfd_hash_table *table, + const char *string) { struct elf_m32r_link_hash_entry *ret = (struct elf_m32r_link_hash_entry *) entry; /* Allocate the structure if it has not already been allocated by a subclass. */ - if (ret == (struct elf_m32r_link_hash_entry *) NULL) - ret = ((struct elf_m32r_link_hash_entry *) - bfd_hash_allocate (table, - sizeof (struct elf_m32r_link_hash_entry))); - if (ret == (struct elf_m32r_link_hash_entry *) NULL) - return (struct bfd_hash_entry *) ret; + if (ret == NULL) + ret = bfd_hash_allocate (table, + sizeof (struct elf_m32r_link_hash_entry)); + if (ret == NULL) + return NULL; /* Call the allocation method of the superclass. */ ret = ((struct elf_m32r_link_hash_entry *) _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret, table, string)); - if (ret != (struct elf_m32r_link_hash_entry *) NULL) + if (ret != NULL) { struct elf_m32r_link_hash_entry *eh; eh = (struct elf_m32r_link_hash_entry *) ret; eh->dyn_relocs = NULL; -// eh->gotplt_refcount = 0; - /* eh->pcrel_relocs_copied = NULL; FIXME */ } return (struct bfd_hash_entry *) ret; } /* Create an m32r ELF linker hash table. */ -static struct bfd_link_hash_table *m32r_elf_link_hash_table_create (bfd *); static struct bfd_link_hash_table * -m32r_elf_link_hash_table_create (abfd) - bfd *abfd; +m32r_elf_link_hash_table_create (bfd *abfd) { struct elf_m32r_link_hash_table *ret; bfd_size_type amt = sizeof (struct elf_m32r_link_hash_table); - ret = (struct elf_m32r_link_hash_table *) bfd_malloc (amt); - if (ret == (struct elf_m32r_link_hash_table *) NULL) + ret = bfd_malloc (amt); + if (ret == NULL) return NULL; if (! _bfd_elf_link_hash_table_init (&ret->root, abfd, @@ -1701,12 +1593,9 @@ m32r_elf_link_hash_table_create (abfd) /* Create .got, .gotplt, and .rela.got sections in DYNOBJ, and set up shortcuts to them in our hash table. */ -static bfd_boolean create_got_section (bfd *, struct bfd_link_info *); static bfd_boolean -create_got_section (dynobj, info) - bfd *dynobj; - struct bfd_link_info *info; +create_got_section (bfd *dynobj, struct bfd_link_info *info) { struct elf_m32r_link_hash_table *htab; @@ -1736,13 +1625,11 @@ create_got_section (dynobj, info) /* Create dynamic sections when linking against a dynamic object. */ static bfd_boolean -m32r_elf_create_dynamic_sections (abfd, info) - bfd *abfd; - struct bfd_link_info *info; +m32r_elf_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info) { struct elf_m32r_link_hash_table *htab; flagword flags, pltflags; - register asection *s; + asection *s; const struct elf_backend_data *bed = get_elf_backend_data (abfd); int ptralign = 2; /* 32bit */ @@ -1750,7 +1637,6 @@ m32r_elf_create_dynamic_sections (abfd, /* We need to create .plt, .rel[a].plt, .got, .got.plt, .dynbss, and .rel[a].bss sections. */ - flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED); @@ -1773,9 +1659,10 @@ m32r_elf_create_dynamic_sections (abfd, .plt section. */ struct bfd_link_hash_entry *bh = NULL; struct elf_link_hash_entry *h; + if (! (_bfd_generic_link_add_one_symbol (info, abfd, "_PROCEDURE_LINKAGE_TABLE_", BSF_GLOBAL, s, - (bfd_vma) 0, (const char *) NULL, FALSE, + (bfd_vma) 0, NULL, FALSE, get_elf_backend_data (abfd)->collect, &bh))) return FALSE; h = (struct elf_link_hash_entry *) bh; @@ -1812,7 +1699,7 @@ m32r_elf_create_dynamic_sections (abfd, || ((secflags & SEC_HAS_CONTENTS) != SEC_HAS_CONTENTS)) continue; secname = bfd_get_section_name (abfd, sec); - relname = (char *) bfd_malloc ((bfd_size_type) strlen (secname) + 6); + relname = bfd_malloc ((bfd_size_type) strlen (secname) + 6); strcpy (relname, ".rela"); strcat (relname, secname); if (bfd_get_section_by_name (abfd, secname)) @@ -1866,16 +1753,14 @@ m32r_elf_create_dynamic_sections (abfd, } /* Copy the extra info we tack onto an elf_link_hash_entry. */ -static void m32r_elf_copy_indirect_symbol (const struct elf_backend_data *, - struct elf_link_hash_entry *, - struct elf_link_hash_entry *); static void m32r_elf_copy_indirect_symbol (const struct elf_backend_data *bed, struct elf_link_hash_entry *dir, struct elf_link_hash_entry *ind) { - struct elf_m32r_link_hash_entry *edir, *eind; + struct elf_m32r_link_hash_entry * edir; + struct elf_m32r_link_hash_entry * eind; edir = (struct elf_m32r_link_hash_entry *) dir; eind = (struct elf_m32r_link_hash_entry *) ind; @@ -1892,7 +1777,7 @@ m32r_elf_copy_indirect_symbol (const str /* Add reloc counts against the weak sym to the strong sym list. Merge any entries against the same section. */ - for (pp = &eind->dyn_relocs; (p = *pp) != NULL; ) + for (pp = &eind->dyn_relocs; (p = *pp) != NULL;) { struct elf_m32r_dyn_relocs *q; @@ -1914,12 +1799,6 @@ m32r_elf_copy_indirect_symbol (const str eind->dyn_relocs = NULL; } -// if (ind->root.type == bfd_link_hash_indirect -// && dir->got.refcount <= 0) -// { -// edir->tls_type = eind->tls_type; -// eind->tls_type = GOT_UNKNOWN; -// } _bfd_elf_link_hash_copy_indirect (bed, dir, ind); } @@ -1931,9 +1810,8 @@ m32r_elf_copy_indirect_symbol (const str understand. */ static bfd_boolean -m32r_elf_adjust_dynamic_symbol (info, h) - struct bfd_link_info *info; - struct elf_link_hash_entry *h; +m32r_elf_adjust_dynamic_symbol (struct bfd_link_info *info, + struct elf_link_hash_entry *h) { struct elf_m32r_link_hash_table *htab; struct elf_m32r_link_hash_entry *eh; @@ -1943,7 +1821,7 @@ m32r_elf_adjust_dynamic_symbol (info, h) unsigned int power_of_two; #ifdef DEBUG_PIC -printf("m32r_elf_adjust_dynamic_symbol()\n"); + printf ("m32r_elf_adjust_dynamic_symbol()\n"); #endif dynobj = elf_hash_table (info)->dynobj; @@ -1956,7 +1834,6 @@ printf("m32r_elf_adjust_dynamic_symbol() && h->ref_regular && !h->def_regular))); - /* If this is a function, put it in the procedure linkage table. We will fill in the contents of the procedure linkage table later, when we know the address of the .got section. */ @@ -2090,9 +1967,7 @@ printf("m32r_elf_adjust_dynamic_symbol() dynamic relocs. */ static bfd_boolean -allocate_dynrelocs (h, inf) - struct elf_link_hash_entry *h; - PTR inf; +allocate_dynrelocs (struct elf_link_hash_entry *h, void * inf) { struct bfd_link_info *info; struct elf_m32r_link_hash_table *htab; @@ -2112,16 +1987,6 @@ allocate_dynrelocs (h, inf) htab = m32r_elf_hash_table (info); eh = (struct elf_m32r_link_hash_entry *) h; -// if ((h->got.refcount > 0 -// || h->forced_local) -// && eh->gotplt_refcount > 0) -// { -// /* The symbol has been forced local, or we have some direct got refs, -// so treat all the gotplt refs as got refs. */ -// h->got.refcount += eh->gotplt_refcount; -// if (h->plt.refcount >= eh->gotplt_refcount) -// h->plt.refcount -= eh->gotplt_refcount; -// } if (htab->root.dynamic_sections_created && h->plt.refcount > 0) @@ -2221,7 +2086,8 @@ allocate_dynrelocs (h, inf) || info->symbolic)) { struct elf_m32r_dyn_relocs **pp; - for (pp = &eh->dyn_relocs; (p = *pp) != NULL; ) + + for (pp = &eh->dyn_relocs; (p = *pp) != NULL;) { p->count -= p->pc_count; p->pc_count = 0; @@ -2274,12 +2140,11 @@ allocate_dynrelocs (h, inf) return TRUE; } + /* Find any dynamic relocs that apply to read-only sections. */ static bfd_boolean -readonly_dynrelocs (h, inf) - struct elf_link_hash_entry *h; - PTR inf; +readonly_dynrelocs (struct elf_link_hash_entry *h, void * inf) { struct elf_m32r_link_hash_entry *eh; struct elf_m32r_dyn_relocs *p; @@ -2308,9 +2173,8 @@ readonly_dynrelocs (h, inf) /* Set the sizes of the dynamic sections. */ static bfd_boolean -m32r_elf_size_dynamic_sections (output_bfd, info) - bfd *output_bfd ATTRIBUTE_UNUSED; - struct bfd_link_info *info; +m32r_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info) { struct elf_m32r_link_hash_table *htab; bfd *dynobj; @@ -2319,7 +2183,7 @@ m32r_elf_size_dynamic_sections (output_b bfd *ibfd; #ifdef DEBUG_PIC -printf("m32r_elf_size_dynamic_sections()\n"); + printf ("m32r_elf_size_dynamic_sections()\n"); #endif htab = m32r_elf_hash_table (info); @@ -2329,7 +2193,7 @@ printf("m32r_elf_size_dynamic_sections() if (htab->root.dynamic_sections_created) { /* Set the contents of the .interp section to the interpreter. */ - if (! info->shared) + if (info->executable) { s = bfd_get_section_by_name (dynobj, ".interp"); BFD_ASSERT (s != NULL); @@ -2403,7 +2267,7 @@ printf("m32r_elf_size_dynamic_sections() /* Allocate global sym .plt and .got entries, and space for global sym dynamic relocs. */ - elf_link_hash_traverse (&htab->root, allocate_dynrelocs, (PTR) info); + elf_link_hash_traverse (&htab->root, allocate_dynrelocs, info); /* We now have determined the sizes of the various dynamic sections. Allocate memory for them. */ @@ -2415,7 +2279,8 @@ printf("m32r_elf_size_dynamic_sections() if (s == htab->splt || s == htab->sgot - || s == htab->sgotplt) + || s == htab->sgotplt + || s == htab->sdynbss) { /* Strip this section if we don't need it; see the comment below. */ @@ -2430,10 +2295,8 @@ printf("m32r_elf_size_dynamic_sections() s->reloc_count = 0; } else - { - /* It's not one of our sections, so don't allocate space. */ - continue; - } + /* It's not one of our sections, so don't allocate space. */ + continue; if (s->size == 0) { @@ -2450,12 +2313,15 @@ printf("m32r_elf_size_dynamic_sections() continue; } + if ((s->flags & SEC_HAS_CONTENTS) == 0) + continue; + /* Allocate memory for the section contents. We use bfd_zalloc here in case unused entries are not reclaimed before the section's contents are written out. This should not happen, but this way if it does, we get a R_M32R_NONE reloc instead of garbage. */ - s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); + s->contents = bfd_zalloc (dynobj, s->size); if (s->contents == NULL) return FALSE; } @@ -2470,7 +2336,7 @@ printf("m32r_elf_size_dynamic_sections() #define add_dynamic_entry(TAG, VAL) \ _bfd_elf_add_dynamic_entry (info, TAG, VAL) - if (! info->shared) + if (info->executable) { if (! add_dynamic_entry (DT_DEBUG, 0)) return FALSE; @@ -2497,7 +2363,7 @@ printf("m32r_elf_size_dynamic_sections() then we need a DT_TEXTREL entry. */ if ((info->flags & DF_TEXTREL) == 0) elf_link_hash_traverse (&htab->root, readonly_dynrelocs, - (PTR) info); + info); if ((info->flags & DF_TEXTREL) != 0) { @@ -2510,6 +2376,7 @@ printf("m32r_elf_size_dynamic_sections() return TRUE; } + /* Relocate an M32R/D ELF section. There is some attempt to make this function usable for many architectures, both for RELA and REL type relocs, if only to serve as a learning tool. @@ -2544,16 +2411,14 @@ printf("m32r_elf_size_dynamic_sections() accordingly. */ static bfd_boolean -m32r_elf_relocate_section (output_bfd, info, input_bfd, input_section, - contents, relocs, local_syms, local_sections) - bfd *output_bfd ATTRIBUTE_UNUSED; - struct bfd_link_info *info; - bfd *input_bfd; - asection *input_section; - bfd_byte *contents; - Elf_Internal_Rela *relocs; - Elf_Internal_Sym *local_syms; - asection **local_sections; +m32r_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info, + bfd *input_bfd, + asection *input_section, + bfd_byte *contents, + Elf_Internal_Rela *relocs, + Elf_Internal_Sym *local_syms, + asection **local_sections) { Elf_Internal_Shdr *symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd); @@ -2607,7 +2472,7 @@ m32r_elf_relocate_section (output_bfd, i continue; } - if (r_type == R_M32R_GNU_VTENTRY + if ( r_type == R_M32R_GNU_VTENTRY || r_type == R_M32R_GNU_VTINHERIT || r_type == R_M32R_NONE || r_type == R_M32R_RELA_GNU_VTENTRY @@ -2628,20 +2493,16 @@ m32r_elf_relocate_section (output_bfd, i section symbol winds up in the output section. */ sec = NULL; if (r_symndx >= symtab_hdr->sh_info) - { - /* External symbol. */ - continue; - } + /* External symbol. */ + continue; /* Local symbol. */ sym = local_syms + r_symndx; sym_name = ""; /* STT_SECTION: symbol is associated with a section. */ if (ELF_ST_TYPE (sym->st_info) != STT_SECTION) - { - /* Symbol isn't associated with a section. Nothing to do. */ - continue; - } + /* Symbol isn't associated with a section. Nothing to do. */ + continue; sec = local_sections[r_symndx]; addend += sec->output_offset + sym->st_value; @@ -2765,6 +2626,7 @@ m32r_elf_relocate_section (output_bfd, i || r_type == R_M32R_HI16_SLO_RELA || r_type == R_M32R_LO16_RELA) && !h->forced_local) + || r_type == R_M32R_REL32 || r_type == R_M32R_10_PCREL_RELA || r_type == R_M32R_18_PCREL_RELA || r_type == R_M32R_26_PCREL_RELA) @@ -2960,7 +2822,7 @@ m32r_elf_relocate_section (output_bfd, i outrel.r_info = ELF32_R_INFO (0, R_M32R_RELATIVE); outrel.r_addend = relocation; loc = srelgot->contents; - loc += srelgot->reloc_count * sizeof(Elf32_External_Rela); + loc += srelgot->reloc_count * sizeof (Elf32_External_Rela); bfd_elf32_swap_reloca_out (output_bfd, &outrel,loc); ++srelgot->reloc_count; } @@ -2986,19 +2848,14 @@ m32r_elf_relocate_section (output_bfd, i if (h == NULL) break; - //if (ELF_ST_VISIBILITY (h->other) == STV_INTERNAL - // || ELF_ST_VISIBILITY (h->other) == STV_HIDDEN) - // break; if (h->forced_local) break; if (h->plt.offset == (bfd_vma) -1) - { - /* We didn't make a PLT entry for this symbol. This - happens when statically linking PIC code, or when - using -Bsymbolic. */ - break; - } + /* We didn't make a PLT entry for this symbol. This + happens when statically linking PIC code, or when + using -Bsymbolic. */ + break; relocation = (splt->output_section->vma + splt->output_offset @@ -3006,16 +2863,14 @@ m32r_elf_relocate_section (output_bfd, i break; case R_M32R_HI16_SLO_RELA: - { - if ((relocation + rel->r_addend) & 0x8000) - { - rel->r_addend += 0x10000; - } - } + if ((relocation + rel->r_addend) & 0x8000) + rel->r_addend += 0x10000; /* Fall through. */ + case R_M32R_16_RELA: case R_M32R_24_RELA: case R_M32R_32_RELA: + case R_M32R_REL32: case R_M32R_18_PCREL_RELA: case R_M32R_26_PCREL_RELA: case R_M32R_HI16_ULO_RELA: @@ -3024,7 +2879,8 @@ m32r_elf_relocate_section (output_bfd, i && r_symndx != 0 && (input_section->flags & SEC_ALLOC) != 0 && ((r_type != R_M32R_18_PCREL_RELA - && r_type != R_M32R_26_PCREL_RELA) + && r_type != R_M32R_26_PCREL_RELA + && r_type != R_M32R_REL32) || (h != NULL && h->dynindx != -1 && (! info->symbolic @@ -3037,7 +2893,6 @@ m32r_elf_relocate_section (output_bfd, i /* When generating a shared object, these relocations are copied into the output file to be resolved at run time. */ - if (sreloc == NULL) { const char *name; @@ -3068,14 +2923,15 @@ m32r_elf_relocate_section (output_bfd, i if (outrel.r_offset == (bfd_vma) -1) skip = TRUE; else if (outrel.r_offset == (bfd_vma) -2) - skip = TRUE, relocate = TRUE; + skip = relocate = TRUE; outrel.r_offset += (input_section->output_section->vma + input_section->output_offset); if (skip) memset (&outrel, 0, sizeof outrel); else if (r_type == R_M32R_18_PCREL_RELA - || r_type == R_M32R_26_PCREL_RELA) + || r_type == R_M32R_26_PCREL_RELA + || r_type == R_M32R_REL32) { BFD_ASSERT (h != NULL && h->dynindx != -1); outrel.r_info = ELF32_R_INFO (h->dynindx, r_type); @@ -3102,7 +2958,7 @@ m32r_elf_relocate_section (output_bfd, i } loc = sreloc->contents; - loc += sreloc->reloc_count * sizeof(Elf32_External_Rela); + loc += sreloc->reloc_count * sizeof (Elf32_External_Rela); bfd_elf32_swap_reloca_out (output_bfd, &outrel,loc); ++sreloc->reloc_count; @@ -3158,7 +3014,7 @@ m32r_elf_relocate_section (output_bfd, i BFD_ASSERT (sec != NULL); name = bfd_get_section_name (abfd, sec); - if (strcmp (name, ".sdata") == 0 + if ( strcmp (name, ".sdata") == 0 || strcmp (name, ".sbss") == 0 || strcmp (name, ".scommon") == 0) { @@ -3192,7 +3048,7 @@ m32r_elf_relocate_section (output_bfd, i continue; } } - /* fall through */ + /* Fall through. */ default : /* OLD_M32R_RELOC */ @@ -3275,19 +3131,19 @@ m32r_elf_relocate_section (output_bfd, i /* Finish up dynamic symbol handling. We set the contents of various dynamic sections here. */ + static bfd_boolean -m32r_elf_finish_dynamic_symbol (output_bfd, info, h, sym) - bfd *output_bfd; - struct bfd_link_info *info; - struct elf_link_hash_entry *h; - Elf_Internal_Sym *sym; +m32r_elf_finish_dynamic_symbol (bfd *output_bfd, + struct bfd_link_info *info, + struct elf_link_hash_entry *h, + Elf_Internal_Sym *sym) { struct elf_m32r_link_hash_table *htab; bfd *dynobj; bfd_byte *loc; #ifdef DEBUG_PIC -printf("m32r_elf_finish_dynamic_symbol()\n"); + printf ("m32r_elf_finish_dynamic_symbol()\n"); #endif htab = m32r_elf_hash_table (info); @@ -3384,7 +3240,7 @@ printf("m32r_elf_finish_dynamic_symbol() rela.r_info = ELF32_R_INFO (h->dynindx, R_M32R_JMP_SLOT); rela.r_addend = 0; loc = srela->contents; - loc += plt_index * sizeof(Elf32_External_Rela); + loc += plt_index * sizeof (Elf32_External_Rela); bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); if (!h->def_regular) @@ -3430,14 +3286,14 @@ printf("m32r_elf_finish_dynamic_symbol() } else { - BFD_ASSERT((h->got.offset & 1) == 0); + BFD_ASSERT ((h->got.offset & 1) == 0); bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + h->got.offset); rela.r_info = ELF32_R_INFO (h->dynindx, R_M32R_GLOB_DAT); rela.r_addend = 0; } loc = srela->contents; - loc += srela->reloc_count * sizeof(Elf32_External_Rela); + loc += srela->reloc_count * sizeof (Elf32_External_Rela); bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); ++srela->reloc_count; } @@ -3463,7 +3319,7 @@ printf("m32r_elf_finish_dynamic_symbol() rela.r_info = ELF32_R_INFO (h->dynindx, R_M32R_COPY); rela.r_addend = 0; loc = s->contents; - loc += s->reloc_count * sizeof(Elf32_External_Rela); + loc += s->reloc_count * sizeof (Elf32_External_Rela); bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); ++s->reloc_count; } @@ -3480,9 +3336,8 @@ printf("m32r_elf_finish_dynamic_symbol() /* Finish up the dynamic sections. */ static bfd_boolean -m32r_elf_finish_dynamic_sections (output_bfd, info) - bfd *output_bfd; - struct bfd_link_info *info; +m32r_elf_finish_dynamic_sections (bfd *output_bfd, + struct bfd_link_info *info) { struct elf_m32r_link_hash_table *htab; bfd *dynobj; @@ -3490,7 +3345,7 @@ m32r_elf_finish_dynamic_sections (output asection *sgot; #ifdef DEBUG_PIC -printf("m32r_elf_finish_dynamic_sections()\n"); + printf ("m32r_elf_finish_dynamic_sections()\n"); #endif htab = m32r_elf_hash_table (info); @@ -3615,9 +3470,9 @@ printf("m32r_elf_finish_dynamic_sections /* Set the right machine number. */ + static bfd_boolean -m32r_elf_object_p (abfd) - bfd *abfd; +m32r_elf_object_p (bfd *abfd) { switch (elf_elfheader (abfd)->e_flags & EF_M32R_ARCH) { @@ -3630,10 +3485,10 @@ m32r_elf_object_p (abfd) } /* Store the machine number in the flags field. */ + static void -m32r_elf_final_write_processing (abfd, linker) - bfd *abfd; - bfd_boolean linker ATTRIBUTE_UNUSED; +m32r_elf_final_write_processing (bfd *abfd, + bfd_boolean linker ATTRIBUTE_UNUSED) { unsigned long val; @@ -3650,10 +3505,9 @@ m32r_elf_final_write_processing (abfd, l } /* Function to keep M32R specific file flags. */ + static bfd_boolean -m32r_elf_set_private_flags (abfd, flags) - bfd *abfd; - flagword flags; +m32r_elf_set_private_flags (bfd *abfd, flagword flags) { BFD_ASSERT (!elf_flags_init (abfd) || elf_elfheader (abfd)->e_flags == flags); @@ -3665,10 +3519,9 @@ m32r_elf_set_private_flags (abfd, flags) /* Merge backend specific data from an object file to the output object file when linking. */ + static bfd_boolean -m32r_elf_merge_private_bfd_data (ibfd, obfd) - bfd *ibfd; - bfd *obfd; +m32r_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd) { flagword out_flags; flagword in_flags; @@ -3696,9 +3549,8 @@ m32r_elf_merge_private_bfd_data (ibfd, o if (bfd_get_arch (obfd) == bfd_get_arch (ibfd) && bfd_get_arch_info (obfd)->the_default) - { - return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd)); - } + return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), + bfd_get_mach (ibfd)); return TRUE; } @@ -3724,11 +3576,10 @@ m32r_elf_merge_private_bfd_data (ibfd, o return TRUE; } -/* Display the flags field */ +/* Display the flags field. */ + static bfd_boolean -m32r_elf_print_private_bfd_data (abfd, ptr) - bfd *abfd; - PTR ptr; +m32r_elf_print_private_bfd_data (bfd *abfd, void * ptr) { FILE * file = (FILE *) ptr; @@ -3751,13 +3602,12 @@ m32r_elf_print_private_bfd_data (abfd, p return TRUE; } -asection * -m32r_elf_gc_mark_hook (sec, info, rel, h, sym) - asection *sec; - struct bfd_link_info *info ATTRIBUTE_UNUSED; - Elf_Internal_Rela *rel; - struct elf_link_hash_entry *h; - Elf_Internal_Sym *sym; +static asection * +m32r_elf_gc_mark_hook (asection *sec, + struct bfd_link_info *info ATTRIBUTE_UNUSED, + Elf_Internal_Rela *rel, + struct elf_link_hash_entry *h, + Elf_Internal_Sym *sym) { if (h != NULL) { @@ -3791,11 +3641,10 @@ m32r_elf_gc_mark_hook (sec, info, rel, h } static bfd_boolean -m32r_elf_gc_sweep_hook (abfd, info, sec, relocs) - bfd *abfd ATTRIBUTE_UNUSED; - struct bfd_link_info *info ATTRIBUTE_UNUSED; - asection *sec ATTRIBUTE_UNUSED; - const Elf_Internal_Rela *relocs ATTRIBUTE_UNUSED; +m32r_elf_gc_sweep_hook (bfd *abfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info ATTRIBUTE_UNUSED, + asection *sec ATTRIBUTE_UNUSED, + const Elf_Internal_Rela *relocs ATTRIBUTE_UNUSED) { /* Update the got entry reference counts for the section being removed. */ Elf_Internal_Shdr *symtab_hdr; @@ -3853,6 +3702,7 @@ m32r_elf_gc_sweep_hook (abfd, info, sec, case R_M32R_16_RELA: case R_M32R_24_RELA: case R_M32R_32_RELA: + case R_M32R_REL32: case R_M32R_HI16_ULO_RELA: case R_M32R_HI16_SLO_RELA: case R_M32R_LO16_RELA: @@ -3874,7 +3724,8 @@ m32r_elf_gc_sweep_hook (abfd, info, sec, if (p->sec == sec) { if (ELF32_R_TYPE (rel->r_info) == R_M32R_26_PCREL_RELA - || ELF32_R_TYPE (rel->r_info) == R_M32R_26_PCREL_RELA) + || ELF32_R_TYPE (rel->r_info) == R_M32R_26_PCREL_RELA + || ELF32_R_TYPE (rel->r_info) == R_M32R_REL32) p->pc_count -= 1; p->count -= 1; if (p->count == 0) @@ -3905,11 +3756,10 @@ m32r_elf_gc_sweep_hook (abfd, info, sec, virtual table relocs for gc. */ static bfd_boolean -m32r_elf_check_relocs (abfd, info, sec, relocs) - bfd *abfd; - struct bfd_link_info *info; - asection *sec; - const Elf_Internal_Rela *relocs; +m32r_elf_check_relocs (bfd *abfd, + struct bfd_link_info *info, + asection *sec, + const Elf_Internal_Rela *relocs) { Elf_Internal_Shdr *symtab_hdr; struct elf_link_hash_entry **sym_hashes, **sym_hashes_end; @@ -4004,8 +3854,7 @@ m32r_elf_check_relocs (abfd, info, sec, size = symtab_hdr->sh_info; size *= sizeof (bfd_signed_vma); - local_got_refcounts = ((bfd_signed_vma *) - bfd_zalloc (abfd, size)); + local_got_refcounts = bfd_zalloc (abfd, size); if (local_got_refcounts == NULL) return FALSE; elf_local_got_refcounts (abfd) = local_got_refcounts; @@ -4036,6 +3885,7 @@ m32r_elf_check_relocs (abfd, info, sec, case R_M32R_16_RELA: case R_M32R_24_RELA: case R_M32R_32_RELA: + case R_M32R_REL32: case R_M32R_HI16_ULO_RELA: case R_M32R_HI16_SLO_RELA: case R_M32R_LO16_RELA: @@ -4071,7 +3921,8 @@ m32r_elf_check_relocs (abfd, info, sec, if ((info->shared && (sec->flags & SEC_ALLOC) != 0 && ((r_type != R_M32R_26_PCREL_RELA - && r_type != R_M32R_18_PCREL_RELA) + && r_type != R_M32R_18_PCREL_RELA + && r_type != R_M32R_REL32) || (h != NULL && (! info->symbolic || h->root.type == bfd_link_hash_defweak @@ -4147,7 +3998,8 @@ m32r_elf_check_relocs (abfd, info, sec, if (p == NULL || p->sec != sec) { bfd_size_type amt = sizeof (*p); - p = ((struct elf_m32r_dyn_relocs *) bfd_alloc (dynobj, amt)); + + p = bfd_alloc (dynobj, amt); if (p == NULL) return FALSE; p->next = *head; @@ -4188,53 +4040,19 @@ m32r_elf_check_relocs (abfd, info, sec, return TRUE; } -static struct bfd_elf_special_section const - m32r_elf_special_sections_s[] = +static const struct bfd_elf_special_section m32r_elf_special_sections[] = { - { ".sdata", 6, -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, { ".sbss", 5, -2, SHT_NOBITS, SHF_ALLOC + SHF_WRITE }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const * - m32r_elf_special_sections[27] = -{ - NULL, /* 'a' */ - NULL, /* 'b' */ - NULL, /* 'c' */ - NULL, /* 'd' */ - NULL, /* 'e' */ - NULL, /* 'f' */ - NULL, /* 'g' */ - NULL, /* 'h' */ - NULL, /* 'i' */ - NULL, /* 'j' */ - NULL, /* 'k' */ - NULL, /* 'l' */ - NULL, /* 'm' */ - NULL, /* 'n' */ - NULL, /* 'o' */ - NULL, /* 'p' */ - NULL, /* 'q' */ - NULL, /* 'r' */ - m32r_elf_special_sections_s, /* 's' */ - NULL, /* 't' */ - NULL, /* 'u' */ - NULL, /* 'v' */ - NULL, /* 'w' */ - NULL, /* 'x' */ - NULL, /* 'y' */ - NULL, /* 'z' */ - NULL /* other */ + { ".sdata", 6, -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, + { NULL, 0, 0, 0, 0 } }; static bfd_boolean -m32r_elf_fake_sections (abfd, hdr, sec) - bfd *abfd; - Elf_Internal_Shdr *hdr ATTRIBUTE_UNUSED; - asection *sec; +m32r_elf_fake_sections (bfd *abfd, + Elf_Internal_Shdr *hdr ATTRIBUTE_UNUSED, + asection *sec) { - register const char *name; + const char *name; name = bfd_get_section_name (abfd, sec); @@ -4256,7 +4074,7 @@ m32r_elf_fake_sections (abfd, hdr, sec) esd = elf_section_data (sec); BFD_ASSERT (esd->rel_hdr2 == NULL); - esd->rel_hdr2 = (Elf_Internal_Shdr *) bfd_zalloc (abfd, amt); + esd->rel_hdr2 = bfd_zalloc (abfd, amt); if (!esd->rel_hdr2) return FALSE; _bfd_elf_init_reloc_shdr (abfd, esd->rel_hdr2, sec, @@ -4267,19 +4085,14 @@ m32r_elf_fake_sections (abfd, hdr, sec) } static enum elf_reloc_type_class -m32r_elf_reloc_type_class (rela) - const Elf_Internal_Rela *rela; +m32r_elf_reloc_type_class (const Elf_Internal_Rela *rela) { switch ((int) ELF32_R_TYPE (rela->r_info)) { - case R_M32R_RELATIVE: - return reloc_class_relative; - case R_M32R_JMP_SLOT: - return reloc_class_plt; - case R_M32R_COPY: - return reloc_class_copy; - default: - return reloc_class_normal; + case R_M32R_RELATIVE: return reloc_class_relative; + case R_M32R_JMP_SLOT: return reloc_class_plt; + case R_M32R_COPY: return reloc_class_copy; + default: return reloc_class_normal; } } @@ -4341,18 +4154,18 @@ m32r_elf_reloc_type_class (rela) #include "elf32-target.h" -#undef ELF_MAXPAGESIZE +#undef ELF_MAXPAGESIZE #define ELF_MAXPAGESIZE 0x1000 -#undef TARGET_BIG_SYM +#undef TARGET_BIG_SYM #define TARGET_BIG_SYM bfd_elf32_m32rlin_vec -#undef TARGET_BIG_NAME +#undef TARGET_BIG_NAME #define TARGET_BIG_NAME "elf32-m32r-linux" -#undef TARGET_LITTLE_SYM +#undef TARGET_LITTLE_SYM #define TARGET_LITTLE_SYM bfd_elf32_m32rlelin_vec -#undef TARGET_LITTLE_NAME +#undef TARGET_LITTLE_NAME #define TARGET_LITTLE_NAME "elf32-m32rle-linux" -#undef elf32_bed +#undef elf32_bed #define elf32_bed elf32_m32r_lin_bed #include "elf32-target.h" diff -uprN binutils-2.16.91.0.1/bfd/elf32-m68hc11.c binutils-2.16.91.0.2/bfd/elf32-m68hc11.c --- binutils-2.16.91.0.1/bfd/elf32-m68hc11.c 2005-05-10 15:46:42.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-m68hc11.c 2005-07-20 12:27:27.214206068 -0700 @@ -1257,65 +1257,14 @@ m68hc11_elf_relax_delete_bytes (bfd *abf are located in .page0. - The .vectors is the section that represents the interrupt vectors. */ -static struct bfd_elf_special_section const - m68hc11_special_sections_e[] = +static const struct bfd_elf_special_section elf32_m68hc11_special_sections[] = { { ".eeprom", 7, 0, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - m68hc11_special_sections_s[]= -{ - { ".softregs", 9, 0, SHT_NOBITS, SHF_ALLOC + SHF_WRITE }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - m68hc11_special_sections_p[]= -{ { ".page0", 6, 0, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - m68hc11_special_sections_v[]= -{ + { ".softregs", 9, 0, SHT_NOBITS, SHF_ALLOC + SHF_WRITE }, { ".vectors", 8, 0, SHT_PROGBITS, SHF_ALLOC }, { NULL, 0, 0, 0, 0 } }; - -static struct bfd_elf_special_section const * - elf32_m68hc11_special_sections[27] = -{ - NULL, /* 'a' */ - NULL, /* 'b' */ - NULL, /* 'c' */ - NULL, /* 'd' */ - m68hc11_special_sections_e, /* 'e' */ - NULL, /* 'f' */ - NULL, /* 'g' */ - NULL, /* 'h' */ - NULL, /* 'i' */ - NULL, /* 'j' */ - NULL, /* 'k' */ - NULL, /* 'l' */ - NULL, /* 'm' */ - NULL, /* 'n' */ - NULL, /* 'o' */ - m68hc11_special_sections_p, /* 'p' */ - NULL, /* 'q' */ - NULL, /* 'r' */ - m68hc11_special_sections_s, /* 's' */ - NULL, /* 't' */ - NULL, /* 'u' */ - m68hc11_special_sections_v, /* 'v' */ - NULL, /* 'w' */ - NULL, /* 'x' */ - NULL, /* 'y' */ - NULL, /* 'z' */ - NULL /* other */ -}; #define ELF_ARCH bfd_arch_m68hc11 #define ELF_MACHINE_CODE EM_68HC11 @@ -1335,7 +1284,7 @@ static struct bfd_elf_special_section co #define elf_backend_object_p 0 #define elf_backend_final_write_processing 0 #define elf_backend_can_gc_sections 1 -#define elf_backend_special_sections elf32_m68hc11_special_sections +#define elf_backend_special_sections elf32_m68hc11_special_sections #define bfd_elf32_bfd_link_hash_table_create \ m68hc11_elf_bfd_link_hash_table_create diff -uprN binutils-2.16.91.0.1/bfd/elf32-m68hc12.c binutils-2.16.91.0.2/bfd/elf32-m68hc12.c --- binutils-2.16.91.0.1/bfd/elf32-m68hc12.c 2005-05-10 15:46:42.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-m68hc12.c 2005-07-20 12:27:27.215205903 -0700 @@ -535,65 +535,14 @@ m68hc12_elf_set_mach_from_flags (bfd *ab Page0 accesses are faster on the M68HC12. - The .vectors is the section that represents the interrupt vectors. */ -static struct bfd_elf_special_section const - m68hc12_special_sections_e[] = +static const struct bfd_elf_special_section elf32_m68hc12_special_sections[] = { { ".eeprom", 7, 0, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - m68hc12_special_sections_s[]= -{ - { ".softregs", 9, 0, SHT_NOBITS, SHF_ALLOC + SHF_WRITE }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - m68hc12_special_sections_p[]= -{ { ".page0", 6, 0, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - m68hc12_special_sections_v[]= -{ + { ".softregs", 9, 0, SHT_NOBITS, SHF_ALLOC + SHF_WRITE }, { ".vectors", 8, 0, SHT_PROGBITS, SHF_ALLOC }, { NULL, 0, 0, 0, 0 } }; - -static struct bfd_elf_special_section const * - elf32_m68hc12_special_sections[27] = -{ - NULL, /* 'a' */ - NULL, /* 'b' */ - NULL, /* 'c' */ - NULL, /* 'd' */ - m68hc12_special_sections_e, /* 'e' */ - NULL, /* 'f' */ - NULL, /* 'g' */ - NULL, /* 'h' */ - NULL, /* 'i' */ - NULL, /* 'j' */ - NULL, /* 'k' */ - NULL, /* 'l' */ - NULL, /* 'm' */ - NULL, /* 'n' */ - NULL, /* 'o' */ - m68hc12_special_sections_p, /* 'p' */ - NULL, /* 'q' */ - NULL, /* 'r' */ - m68hc12_special_sections_s, /* 's' */ - NULL, /* 't' */ - NULL, /* 'u' */ - m68hc12_special_sections_v, /* 'v' */ - NULL, /* 'w' */ - NULL, /* 'x' */ - NULL, /* 'y' */ - NULL, /* 'z' */ - NULL /* other */ -}; #define ELF_ARCH bfd_arch_m68hc12 #define ELF_MACHINE_CODE EM_68HC12 diff -uprN binutils-2.16.91.0.1/bfd/elf32-m68k.c binutils-2.16.91.0.2/bfd/elf32-m68k.c --- binutils-2.16.91.0.1/bfd/elf32-m68k.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-m68k.c 2005-07-20 12:27:27.225204254 -0700 @@ -1189,7 +1189,6 @@ elf_m68k_size_dynamic_sections (output_b for (s = dynobj->sections; s != NULL; s = s->next) { const char *name; - bfd_boolean strip; if ((s->flags & SEC_LINKER_CREATED) == 0) continue; @@ -1198,38 +1197,14 @@ elf_m68k_size_dynamic_sections (output_b of the dynobj section names depend upon the input files. */ name = bfd_get_section_name (dynobj, s); - strip = FALSE; - if (strcmp (name, ".plt") == 0) { - if (s->size == 0) - { - /* Strip this section if we don't need it; see the - comment below. */ - strip = TRUE; - } - else - { - /* Remember whether there is a PLT. */ - plt = TRUE; - } + /* Remember whether there is a PLT. */ + plt = s->size != 0; } else if (strncmp (name, ".rela", 5) == 0) { - if (s->size == 0) - { - /* If we don't need this section, strip it from the - output file. This is mostly to handle .rela.bss and - .rela.plt. We must create both sections in - create_dynamic_sections, because they must be created - before the linker maps input sections to output - sections. The linker does that before - adjust_dynamic_symbol is called, and it is that - function which decides whether anything needs to go - into these sections. */ - strip = TRUE; - } - else + if (s->size != 0) { relocs = TRUE; @@ -1238,18 +1213,31 @@ elf_m68k_size_dynamic_sections (output_b s->reloc_count = 0; } } - else if (strncmp (name, ".got", 4) != 0) + else if (strncmp (name, ".got", 4) != 0 + && strcmp (name, ".dynbss") != 0) { /* It's not one of our sections, so don't allocate space. */ continue; } - if (strip) + if (s->size == 0) { + /* If we don't need this section, strip it from the + output file. This is mostly to handle .rela.bss and + .rela.plt. We must create both sections in + create_dynamic_sections, because they must be created + before the linker maps input sections to output + sections. The linker does that before + adjust_dynamic_symbol is called, and it is that + function which decides whether anything needs to go + into these sections. */ s->flags |= SEC_EXCLUDE; continue; } + if ((s->flags & SEC_HAS_CONTENTS) == 0) + continue; + /* Allocate memory for the section contents. */ /* FIXME: This should be a call to bfd_alloc not bfd_zalloc. Unused entries should be reclaimed before the section's contents @@ -1257,7 +1245,7 @@ elf_m68k_size_dynamic_sections (output_b order to prevent writing out garbage, we initialise the section's contents to zero. */ s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); - if (s->contents == NULL && s->size != 0) + if (s->contents == NULL) return FALSE; } diff -uprN binutils-2.16.91.0.1/bfd/elf32-mcore.c binutils-2.16.91.0.2/bfd/elf32-mcore.c --- binutils-2.16.91.0.1/bfd/elf32-mcore.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-mcore.c 2005-07-20 12:27:27.227203925 -0700 @@ -1,22 +1,23 @@ /* Motorola MCore specific support for 32-bit ELF - Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004 + Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. -This file is part of BFD, the Binary File Descriptor library. + This file is part of BFD, the Binary File Descriptor library. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, + USA. */ /* This file is based on a preliminary RCE ELF ABI. The information may not match the final RCE ELF ABI. */ @@ -31,30 +32,76 @@ Foundation, Inc., 51 Franklin Street - F /* RELA relocs are used here... */ -static void mcore_elf_howto_init - PARAMS ((void)); -static reloc_howto_type * mcore_elf_reloc_type_lookup - PARAMS ((bfd *, bfd_reloc_code_real_type)); -static void mcore_elf_info_to_howto - PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); -static bfd_boolean mcore_elf_set_private_flags - PARAMS ((bfd *, flagword)); -static bfd_boolean mcore_elf_merge_private_bfd_data - PARAMS ((bfd *, bfd *)); -static bfd_reloc_status_type mcore_elf_unsupported_reloc - PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); -static bfd_boolean mcore_elf_relocate_section - PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, - Elf_Internal_Rela *, Elf_Internal_Sym *, asection **)); -static asection * mcore_elf_gc_mark_hook - PARAMS ((asection *, struct bfd_link_info *, Elf_Internal_Rela *, - struct elf_link_hash_entry *, Elf_Internal_Sym *)); -static bfd_boolean mcore_elf_gc_sweep_hook - PARAMS ((bfd *, struct bfd_link_info *, asection *, - const Elf_Internal_Rela *)); -static bfd_boolean mcore_elf_check_relocs - PARAMS ((bfd *, struct bfd_link_info *, asection *, - const Elf_Internal_Rela *)); +/* Function to set whether a module needs the -mrelocatable bit set. */ + +static bfd_boolean +mcore_elf_set_private_flags (bfd * abfd, flagword flags) +{ + BFD_ASSERT (! elf_flags_init (abfd) + || elf_elfheader (abfd)->e_flags == flags); + + elf_elfheader (abfd)->e_flags = flags; + elf_flags_init (abfd) = TRUE; + return TRUE; +} + +/* Merge backend specific data from an object file to the output + object file when linking. */ + +static bfd_boolean +mcore_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd) +{ + flagword old_flags; + flagword new_flags; + + /* Check if we have the same endianess. */ + if (! _bfd_generic_verify_endian_match (ibfd, obfd)) + return FALSE; + + if ( bfd_get_flavour (ibfd) != bfd_target_elf_flavour + || bfd_get_flavour (obfd) != bfd_target_elf_flavour) + return TRUE; + + new_flags = elf_elfheader (ibfd)->e_flags; + old_flags = elf_elfheader (obfd)->e_flags; + + if (! elf_flags_init (obfd)) + { + /* First call, no flags set. */ + elf_flags_init (obfd) = TRUE; + elf_elfheader (obfd)->e_flags = new_flags; + } + else if (new_flags == old_flags) + /* Compatible flags are OK. */ + ; + else + { + /* FIXME */ + } + + return TRUE; +} + +/* Don't pretend we can deal with unsupported relocs. */ + +static bfd_reloc_status_type +mcore_elf_unsupported_reloc (bfd * abfd, + arelent * reloc_entry, + asymbol * symbol ATTRIBUTE_UNUSED, + PTR data ATTRIBUTE_UNUSED, + asection * input_section ATTRIBUTE_UNUSED, + bfd * output_bfd ATTRIBUTE_UNUSED, + char ** error_message ATTRIBUTE_UNUSED) +{ + BFD_ASSERT (reloc_entry->howto != (reloc_howto_type *)0); + + _bfd_error_handler (_("%B: Relocation %s (%d) is not currently supported.\n"), + abfd, + reloc_entry->howto->name, + reloc_entry->howto->type); + + return bfd_reloc_notsupported; +} static reloc_howto_type * mcore_elf_howto_table [(int) R_MCORE_max]; @@ -174,7 +221,7 @@ static reloc_howto_type mcore_elf_howto_ 0x7ff, /* dst_mask */ TRUE), /* pcrel_offset */ - /* GNU extension to record C++ vtable hierarchy */ + /* GNU extension to record C++ vtable hierarchy. */ HOWTO (R_MCORE_GNU_VTINHERIT, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ @@ -189,7 +236,7 @@ static reloc_howto_type mcore_elf_howto_ 0, /* dst_mask */ FALSE), /* pcrel_offset */ - /* GNU extension to record C++ vtable member usage */ + /* GNU extension to record C++ vtable member usage. */ HOWTO (R_MCORE_GNU_VTENTRY, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ @@ -225,7 +272,7 @@ static reloc_howto_type mcore_elf_howto_ /* Initialize the mcore_elf_howto_table, so that linear accesses can be done. */ static void -mcore_elf_howto_init () +mcore_elf_howto_init (void) { unsigned int i; @@ -242,9 +289,8 @@ mcore_elf_howto_init () } static reloc_howto_type * -mcore_elf_reloc_type_lookup (abfd, code) - bfd * abfd ATTRIBUTE_UNUSED; - bfd_reloc_code_real_type code; +mcore_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) { enum elf_mcore_reloc_type mcore_reloc = R_MCORE_NONE; @@ -261,102 +307,31 @@ mcore_elf_reloc_type_lookup (abfd, code) case BFD_RELOC_VTABLE_ENTRY: mcore_reloc = R_MCORE_GNU_VTENTRY; break; case BFD_RELOC_RVA: mcore_reloc = R_MCORE_RELATIVE; break; default: - return (reloc_howto_type *)NULL; + return NULL; } - if (! mcore_elf_howto_table [R_MCORE_PCRELIMM8BY4]) /* Initialize howto table if needed */ + if (! mcore_elf_howto_table [R_MCORE_PCRELIMM8BY4]) + /* Initialize howto table if needed. */ mcore_elf_howto_init (); return mcore_elf_howto_table [(int) mcore_reloc]; }; /* Set the howto pointer for a RCE ELF reloc. */ + static void -mcore_elf_info_to_howto (abfd, cache_ptr, dst) - bfd * abfd ATTRIBUTE_UNUSED; - arelent * cache_ptr; - Elf_Internal_Rela * dst; +mcore_elf_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, + arelent * cache_ptr, + Elf_Internal_Rela * dst) { - if (! mcore_elf_howto_table [R_MCORE_PCRELIMM8BY4]) /* Initialize howto table if needed */ + if (! mcore_elf_howto_table [R_MCORE_PCRELIMM8BY4]) + /* Initialize howto table if needed. */ mcore_elf_howto_init (); BFD_ASSERT (ELF32_R_TYPE (dst->r_info) < (unsigned int) R_MCORE_max); cache_ptr->howto = mcore_elf_howto_table [ELF32_R_TYPE (dst->r_info)]; } - -/* Function to set whether a module needs the -mrelocatable bit set. */ -static bfd_boolean -mcore_elf_set_private_flags (abfd, flags) - bfd * abfd; - flagword flags; -{ - BFD_ASSERT (! elf_flags_init (abfd) - || elf_elfheader (abfd)->e_flags == flags); - - elf_elfheader (abfd)->e_flags = flags; - elf_flags_init (abfd) = TRUE; - return TRUE; -} - -/* Merge backend specific data from an object file to the output - object file when linking. */ -static bfd_boolean -mcore_elf_merge_private_bfd_data (ibfd, obfd) - bfd * ibfd; - bfd * obfd; -{ - flagword old_flags; - flagword new_flags; - - /* Check if we have the same endianess */ - if (! _bfd_generic_verify_endian_match (ibfd, obfd)) - return FALSE; - - if ( bfd_get_flavour (ibfd) != bfd_target_elf_flavour - || bfd_get_flavour (obfd) != bfd_target_elf_flavour) - return TRUE; - - new_flags = elf_elfheader (ibfd)->e_flags; - old_flags = elf_elfheader (obfd)->e_flags; - - if (! elf_flags_init (obfd)) /* First call, no flags set */ - { - elf_flags_init (obfd) = TRUE; - elf_elfheader (obfd)->e_flags = new_flags; - } - else if (new_flags == old_flags) /* Compatible flags are ok */ - ; - else - { - /* FIXME */ - } - - return TRUE; -} - -/* Don't pretend we can deal with unsupported relocs. */ - -static bfd_reloc_status_type -mcore_elf_unsupported_reloc (abfd, reloc_entry, symbol, data, input_section, - output_bfd, error_message) - bfd * abfd; - arelent * reloc_entry; - asymbol * symbol ATTRIBUTE_UNUSED; - PTR data ATTRIBUTE_UNUSED; - asection * input_section ATTRIBUTE_UNUSED; - bfd * output_bfd ATTRIBUTE_UNUSED; - char ** error_message ATTRIBUTE_UNUSED; -{ - BFD_ASSERT (reloc_entry->howto != (reloc_howto_type *)0); - - _bfd_error_handler (_("%B: Relocation %s (%d) is not currently supported.\n"), - abfd, - reloc_entry->howto->name, - reloc_entry->howto->type); - - return bfd_reloc_notsupported; -} /* The RELOCATE_SECTION function is called by the ELF backend linker to handle the relocations for a section. @@ -388,16 +363,14 @@ mcore_elf_unsupported_reloc (abfd, reloc accordingly. */ static bfd_boolean -mcore_elf_relocate_section (output_bfd, info, input_bfd, input_section, - contents, relocs, local_syms, local_sections) - bfd * output_bfd; - struct bfd_link_info * info; - bfd * input_bfd; - asection * input_section; - bfd_byte * contents; - Elf_Internal_Rela * relocs; - Elf_Internal_Sym * local_syms; - asection ** local_sections; +mcore_elf_relocate_section (bfd * output_bfd, + struct bfd_link_info * info, + bfd * input_bfd, + asection * input_section, + bfd_byte * contents, + Elf_Internal_Rela * relocs, + Elf_Internal_Sym * local_syms, + asection ** local_sections) { Elf_Internal_Shdr * symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr; struct elf_link_hash_entry ** sym_hashes = elf_sym_hashes (input_bfd); @@ -426,15 +399,15 @@ mcore_elf_relocate_section (output_bfd, bfd_vma offset = rel->r_offset; bfd_vma addend = rel->r_addend; bfd_reloc_status_type r = bfd_reloc_other; - asection * sec = (asection *) 0; + asection * sec = NULL; reloc_howto_type * howto; bfd_vma relocation; - Elf_Internal_Sym * sym = (Elf_Internal_Sym *) 0; + Elf_Internal_Sym * sym = NULL; unsigned long r_symndx; - struct elf_link_hash_entry * h = (struct elf_link_hash_entry *) 0; + struct elf_link_hash_entry * h = NULL; unsigned short oldinst = 0; - /* Unknown relocation handling */ + /* Unknown relocation handling. */ if ((unsigned) r_type >= (unsigned) R_MCORE_max || ! mcore_elf_howto_table [(int)r_type]) { @@ -553,38 +526,35 @@ mcore_elf_relocate_section (output_bfd, relocation. */ static asection * -mcore_elf_gc_mark_hook (sec, info, rel, h, sym) - asection * sec; - struct bfd_link_info * info ATTRIBUTE_UNUSED; - Elf_Internal_Rela * rel; - struct elf_link_hash_entry * h; - Elf_Internal_Sym * sym; +mcore_elf_gc_mark_hook (asection * sec, + struct bfd_link_info * info ATTRIBUTE_UNUSED, + Elf_Internal_Rela * rel, + struct elf_link_hash_entry * h, + Elf_Internal_Sym * sym) { - if (h != NULL) + if (h == NULL) + return bfd_section_from_elf_index (sec->owner, sym->st_shndx); + + switch (ELF32_R_TYPE (rel->r_info)) { - switch (ELF32_R_TYPE (rel->r_info)) - { - case R_MCORE_GNU_VTINHERIT: - case R_MCORE_GNU_VTENTRY: - break; + case R_MCORE_GNU_VTINHERIT: + case R_MCORE_GNU_VTENTRY: + break; - default: - switch (h->root.type) - { - case bfd_link_hash_defined: - case bfd_link_hash_defweak: - return h->root.u.def.section; + default: + switch (h->root.type) + { + case bfd_link_hash_defined: + case bfd_link_hash_defweak: + return h->root.u.def.section; - case bfd_link_hash_common: - return h->root.u.c.p->section; + case bfd_link_hash_common: + return h->root.u.c.p->section; - default: - break; - } + default: + break; } } - else - return bfd_section_from_elf_index (sec->owner, sym->st_shndx); return NULL; } @@ -592,11 +562,10 @@ mcore_elf_gc_mark_hook (sec, info, rel, /* Update the got entry reference counts for the section being removed. */ static bfd_boolean -mcore_elf_gc_sweep_hook (abfd, info, sec, relocs) - bfd * abfd ATTRIBUTE_UNUSED; - struct bfd_link_info * info ATTRIBUTE_UNUSED; - asection * sec ATTRIBUTE_UNUSED; - const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED; +mcore_elf_gc_sweep_hook (bfd * abfd ATTRIBUTE_UNUSED, + struct bfd_link_info * info ATTRIBUTE_UNUSED, + asection * sec ATTRIBUTE_UNUSED, + const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED) { return TRUE; } @@ -606,11 +575,10 @@ mcore_elf_gc_sweep_hook (abfd, info, sec virtual table relocs for gc. */ static bfd_boolean -mcore_elf_check_relocs (abfd, info, sec, relocs) - bfd * abfd; - struct bfd_link_info * info; - asection * sec; - const Elf_Internal_Rela * relocs; +mcore_elf_check_relocs (bfd * abfd, + struct bfd_link_info * info, + asection * sec, + const Elf_Internal_Rela * relocs) { Elf_Internal_Shdr * symtab_hdr; struct elf_link_hash_entry ** sym_hashes; @@ -667,52 +635,13 @@ mcore_elf_check_relocs (abfd, info, sec, return TRUE; } -static struct bfd_elf_special_section const - mcore_special_sections_c [] = +static const struct bfd_elf_special_section mcore_elf_special_sections[]= { { ".ctors", 6, -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - mcore_special_sections_d[]= -{ { ".dtors", 6, -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, { NULL, 0, 0, 0, 0 } }; -static struct bfd_elf_special_section const * - mcore_elf_special_sections[27]= -{ - NULL, /* 'a' */ - NULL, /* 'b' */ - mcore_special_sections_c, /* 'c' */ - mcore_special_sections_d, /* 'd' */ - NULL, /* 'e' */ - NULL, /* 'f' */ - NULL, /* 'g' */ - NULL, /* 'h' */ - NULL, /* 'i' */ - NULL, /* 'j' */ - NULL, /* 'k' */ - NULL, /* 'l' */ - NULL, /* 'm' */ - NULL, /* 'n' */ - NULL, /* 'o' */ - NULL, /* 'p' */ - NULL, /* 'q' */ - NULL, /* 'r' */ - NULL, /* 's' */ - NULL, /* 't' */ - NULL, /* 'u' */ - NULL, /* 'v' */ - NULL, /* 'w' */ - NULL, /* 'x' */ - NULL, /* 'y' */ - NULL, /* 'z' */ - NULL /* other */ -}; - #define TARGET_BIG_SYM bfd_elf32_mcore_big_vec #define TARGET_BIG_NAME "elf32-mcore-big" #define TARGET_LITTLE_SYM bfd_elf32_mcore_little_vec diff -uprN binutils-2.16.91.0.1/bfd/elf32-openrisc.c binutils-2.16.91.0.2/bfd/elf32-openrisc.c --- binutils-2.16.91.0.1/bfd/elf32-openrisc.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-openrisc.c 2005-07-20 12:27:27.229203595 -0700 @@ -1,22 +1,23 @@ /* OpenRISC-specific support for 32-bit ELF. - Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc. + Copyright 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. Contributed by Johan Rydberg, jrydberg@opencores.org -This file is part of BFD, the Binary File Descriptor library. + This file is part of BFD, the Binary File Descriptor library. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, + USA. */ #include "bfd.h" #include "sysdep.h" @@ -25,35 +26,8 @@ Foundation, Inc., 51 Franklin Street - F #include "elf/openrisc.h" #include "libiberty.h" -/* Forward declarations. */ - -static reloc_howto_type *openrisc_reloc_type_lookup - PARAMS ((bfd * , bfd_reloc_code_real_type)); -static void openrisc_info_to_howto_rela - PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); -static bfd_boolean openrisc_elf_relocate_section - PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, - Elf_Internal_Rela *, Elf_Internal_Sym *, asection **)); -static bfd_reloc_status_type openrisc_final_link_relocate - PARAMS ((reloc_howto_type *, bfd *, asection *, bfd_byte *, - Elf_Internal_Rela *, bfd_vma)); -static bfd_boolean openrisc_elf_gc_sweep_hook - PARAMS ((bfd *, struct bfd_link_info *, asection *, - const Elf_Internal_Rela *)); -static asection * openrisc_elf_gc_mark_hook - PARAMS ((asection *, struct bfd_link_info *, Elf_Internal_Rela *, - struct elf_link_hash_entry *, Elf_Internal_Sym *)); -static bfd_boolean openrisc_elf_check_relocs - PARAMS ((bfd *, struct bfd_link_info *, asection *, - const Elf_Internal_Rela *)); -static bfd_boolean openrisc_elf_object_p - PARAMS ((bfd *)); -static void openrisc_elf_final_write_processing - PARAMS ((bfd *, bfd_boolean)); - - static reloc_howto_type openrisc_elf_howto_table[] = - { +{ /* This reloc does nothing. */ HOWTO (R_OPENRISC_NONE, /* type */ 0, /* rightshift */ @@ -172,7 +146,7 @@ static reloc_howto_type openrisc_elf_how 0xffffffff, /* dst_mask */ FALSE), /* pcrel_offset */ - /* GNU extension to record C++ vtable hierarchy */ + /* GNU extension to record C++ vtable hierarchy. */ HOWTO (R_OPENRISC_GNU_VTINHERIT, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ @@ -187,7 +161,7 @@ static reloc_howto_type openrisc_elf_how 0, /* dst_mask */ FALSE), /* pcrel_offset */ - /* GNU extension to record C++ vtable member usage */ + /* GNU extension to record C++ vtable member usage. */ HOWTO (R_OPENRISC_GNU_VTENTRY, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ @@ -206,29 +180,28 @@ static reloc_howto_type openrisc_elf_how /* Map BFD reloc types to OpenRISC ELF reloc types. */ struct openrisc_reloc_map - { - bfd_reloc_code_real_type bfd_reloc_val; - unsigned int openrisc_reloc_val; - }; +{ + bfd_reloc_code_real_type bfd_reloc_val; + unsigned int openrisc_reloc_val; +}; static const struct openrisc_reloc_map openrisc_reloc_map[] = - { - { BFD_RELOC_NONE, R_OPENRISC_NONE }, - { BFD_RELOC_32, R_OPENRISC_32 }, - { BFD_RELOC_16, R_OPENRISC_16 }, - { BFD_RELOC_8, R_OPENRISC_8 }, - { BFD_RELOC_OPENRISC_REL_26,R_OPENRISC_INSN_REL_26 }, - { BFD_RELOC_OPENRISC_ABS_26,R_OPENRISC_INSN_ABS_26 }, +{ + { BFD_RELOC_NONE, R_OPENRISC_NONE }, + { BFD_RELOC_32, R_OPENRISC_32 }, + { BFD_RELOC_16, R_OPENRISC_16 }, + { BFD_RELOC_8, R_OPENRISC_8 }, + { BFD_RELOC_OPENRISC_REL_26,R_OPENRISC_INSN_REL_26 }, + { BFD_RELOC_OPENRISC_ABS_26,R_OPENRISC_INSN_ABS_26 }, { BFD_RELOC_HI16, R_OPENRISC_HI_16_IN_INSN }, - { BFD_RELOC_LO16, R_OPENRISC_LO_16_IN_INSN }, - { BFD_RELOC_VTABLE_INHERIT, R_OPENRISC_GNU_VTINHERIT }, - { BFD_RELOC_VTABLE_ENTRY, R_OPENRISC_GNU_VTENTRY } - }; + { BFD_RELOC_LO16, R_OPENRISC_LO_16_IN_INSN }, + { BFD_RELOC_VTABLE_INHERIT, R_OPENRISC_GNU_VTINHERIT }, + { BFD_RELOC_VTABLE_ENTRY, R_OPENRISC_GNU_VTENTRY } +}; static reloc_howto_type * -openrisc_reloc_type_lookup (abfd, code) - bfd * abfd ATTRIBUTE_UNUSED; - bfd_reloc_code_real_type code; +openrisc_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) { unsigned int i; @@ -243,10 +216,9 @@ openrisc_reloc_type_lookup (abfd, code) /* Set the howto pointer for an OpenRISC ELF reloc. */ static void -openrisc_info_to_howto_rela (abfd, cache_ptr, dst) - bfd * abfd ATTRIBUTE_UNUSED; - arelent * cache_ptr; - Elf_Internal_Rela * dst; +openrisc_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED, + arelent * cache_ptr, + Elf_Internal_Rela * dst) { unsigned int r_type; @@ -259,14 +231,12 @@ openrisc_info_to_howto_rela (abfd, cache routines, but a few relocs, we have to do them ourselves. */ static bfd_reloc_status_type -openrisc_final_link_relocate (howto, input_bfd, input_section, contents, rel, - relocation) - reloc_howto_type *howto; - bfd *input_bfd; - asection *input_section; - bfd_byte *contents; - Elf_Internal_Rela *rel; - bfd_vma relocation; +openrisc_final_link_relocate (reloc_howto_type *howto, + bfd *input_bfd, + asection *input_section, + bfd_byte *contents, + Elf_Internal_Rela *rel, + bfd_vma relocation) { bfd_reloc_status_type r = bfd_reloc_ok; @@ -319,16 +289,14 @@ openrisc_final_link_relocate (howto, inp accordingly. */ static bfd_boolean -openrisc_elf_relocate_section (output_bfd, info, input_bfd, input_section, - contents, relocs, local_syms, local_sections) - bfd *output_bfd; - struct bfd_link_info *info; - bfd *input_bfd; - asection *input_section; - bfd_byte *contents; - Elf_Internal_Rela *relocs; - Elf_Internal_Sym *local_syms; - asection **local_sections; +openrisc_elf_relocate_section (bfd *output_bfd, + struct bfd_link_info *info, + bfd *input_bfd, + asection *input_section, + bfd_byte *contents, + Elf_Internal_Rela *relocs, + Elf_Internal_Sym *local_syms, + asection **local_sections) { Elf_Internal_Shdr *symtab_hdr; struct elf_link_hash_entry **sym_hashes; @@ -396,7 +364,7 @@ openrisc_elf_relocate_section (output_bf if (r != bfd_reloc_ok) { - const char *msg = (const char *) NULL; + const char *msg = NULL; switch (r) { @@ -444,38 +412,35 @@ openrisc_elf_relocate_section (output_bf relocation. */ static asection * -openrisc_elf_gc_mark_hook (sec, info, rel, h, sym) - asection *sec; - struct bfd_link_info *info ATTRIBUTE_UNUSED; - Elf_Internal_Rela *rel; - struct elf_link_hash_entry *h; - Elf_Internal_Sym *sym; +openrisc_elf_gc_mark_hook (asection *sec, + struct bfd_link_info *info ATTRIBUTE_UNUSED, + Elf_Internal_Rela *rel, + struct elf_link_hash_entry *h, + Elf_Internal_Sym *sym) { - if (h != NULL) + if (h == NULL) + return bfd_section_from_elf_index (sec->owner, sym->st_shndx); + + switch (ELF32_R_TYPE (rel->r_info)) { - switch (ELF32_R_TYPE (rel->r_info)) - { - case R_OPENRISC_GNU_VTINHERIT: - case R_OPENRISC_GNU_VTENTRY: - break; + case R_OPENRISC_GNU_VTINHERIT: + case R_OPENRISC_GNU_VTENTRY: + break; - default: - switch (h->root.type) - { - case bfd_link_hash_defined: - case bfd_link_hash_defweak: - return h->root.u.def.section; + default: + switch (h->root.type) + { + case bfd_link_hash_defined: + case bfd_link_hash_defweak: + return h->root.u.def.section; - case bfd_link_hash_common: - return h->root.u.c.p->section; + case bfd_link_hash_common: + return h->root.u.c.p->section; - default: - break; - } + default: + break; } } - else - return bfd_section_from_elf_index (sec->owner, sym->st_shndx); return NULL; } @@ -483,11 +448,10 @@ openrisc_elf_gc_mark_hook (sec, info, re /* Update the got entry reference counts for the section being removed. */ static bfd_boolean -openrisc_elf_gc_sweep_hook (abfd, info, sec, relocs) - bfd *abfd ATTRIBUTE_UNUSED; - struct bfd_link_info *info ATTRIBUTE_UNUSED; - asection *sec ATTRIBUTE_UNUSED; - const Elf_Internal_Rela *relocs ATTRIBUTE_UNUSED; +openrisc_elf_gc_sweep_hook (bfd *abfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info ATTRIBUTE_UNUSED, + asection *sec ATTRIBUTE_UNUSED, + const Elf_Internal_Rela *relocs ATTRIBUTE_UNUSED) { return TRUE; } @@ -497,11 +461,10 @@ openrisc_elf_gc_sweep_hook (abfd, info, virtual table relocs for gc. */ static bfd_boolean -openrisc_elf_check_relocs (abfd, info, sec, relocs) - bfd *abfd; - struct bfd_link_info *info; - asection *sec; - const Elf_Internal_Rela *relocs; +openrisc_elf_check_relocs (bfd *abfd, + struct bfd_link_info *info, + asection *sec, + const Elf_Internal_Rela *relocs) { Elf_Internal_Shdr *symtab_hdr; struct elf_link_hash_entry **sym_hashes, **sym_hashes_end; @@ -559,24 +522,17 @@ openrisc_elf_check_relocs (abfd, info, s /* Set the right machine number. */ static bfd_boolean -openrisc_elf_object_p (abfd) - bfd *abfd; +openrisc_elf_object_p (bfd *abfd) { - switch (elf_elfheader (abfd)->e_flags & 0xf) - { - default: - (void) bfd_default_set_arch_mach (abfd, bfd_arch_openrisc, 0); - break; - } + bfd_default_set_arch_mach (abfd, bfd_arch_openrisc, 0); return TRUE; } /* Store the machine number in the flags field. */ static void -openrisc_elf_final_write_processing (abfd, linker) - bfd *abfd; - bfd_boolean linker ATTRIBUTE_UNUSED; +openrisc_elf_final_write_processing (bfd *abfd, + bfd_boolean linker ATTRIBUTE_UNUSED) { unsigned long val; diff -uprN binutils-2.16.91.0.1/bfd/elf32-or32.c binutils-2.16.91.0.2/bfd/elf32-or32.c --- binutils-2.16.91.0.1/bfd/elf32-or32.c 2005-05-10 15:46:42.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-or32.c 2005-07-20 12:27:27.237202276 -0700 @@ -1,5 +1,5 @@ /* OR32-specific support for 32-bit ELF - Copyright 2002, 2004 Free Software Foundation, Inc. + Copyright 2002, 2004, 2005 Free Software Foundation, Inc. Contributed by Ivan Guzvinec This file is part of BFD, the Binary File Descriptor library. @@ -25,226 +25,14 @@ #include "elf/or32.h" #include "libiberty.h" -static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup - PARAMS ((bfd *, bfd_reloc_code_real_type)); -static void or32_info_to_howto_rel - PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); -static bfd_boolean or32_elf_object_p - PARAMS ((bfd *)); -static void or32_elf_final_write_processing - PARAMS ((bfd *, bfd_boolean)); -static bfd_reloc_status_type or32_elf_32_reloc - PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); -static bfd_reloc_status_type or32_elf_16_reloc - PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); -static bfd_reloc_status_type or32_elf_8_reloc - PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); -static bfd_reloc_status_type or32_elf_const_reloc - PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); -static bfd_reloc_status_type or32_elf_consth_reloc - PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); -static bfd_reloc_status_type or32_elf_jumptarg_reloc - PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); - /* Try to minimize the amount of space occupied by relocation tables on the ROM (not that the ROM won't be swamped by other ELF overhead). */ #define USE_REL 1 -static reloc_howto_type elf_or32_howto_table[] = -{ - /* This reloc does nothing. */ - HOWTO (R_OR32_NONE, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_OR32_NONE", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* A standard 32 bit relocation. */ - HOWTO (R_OR32_32, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - or32_elf_32_reloc, /* special_function */ - "R_OR32_32", /* name */ - FALSE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* A standard 16 bit relocation. */ - HOWTO (R_OR32_16, /* type */ - 0, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - or32_elf_16_reloc, /* special_function */ - "R_OR32_16", /* name */ - FALSE, /* partial_inplace */ - 0x0000ffff, /* src_mask */ - 0x0000ffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* A standard 8 bit relocation. */ - HOWTO (R_OR32_8, /* type */ - 0, /* rightshift */ - 0, /* size (0 = byte, 1 = short, 2 = long) */ - 8, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - or32_elf_8_reloc, /* special_function */ - "R_OR32_8", /* name */ - FALSE, /* partial_inplace */ - 0x000000ff, /* src_mask */ - 0x000000ff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* A standard low 16 bit relocation. */ - HOWTO (R_OR32_CONST, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - or32_elf_const_reloc, /* special_function */ - "R_OR32_CONST", /* name */ - FALSE, /* partial_inplace */ - 0x0000ffff, /* src_mask */ - 0x0000ffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* A standard high 16 bit relocation. */ - HOWTO (R_OR32_CONSTH, /* type */ - 16, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - or32_elf_consth_reloc, /* special_function */ - "R_OR32_CONSTH", /* name */ - FALSE, /* partial_inplace */ - 0xffff0000, /* src_mask */ - 0x0000ffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* A standard branch relocation. */ - HOWTO (R_OR32_JUMPTARG, /* type */ - 2, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 28, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - or32_elf_jumptarg_reloc,/* special_function */ - "R_OR32_JUMPTARG", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0x03ffffff, /* dst_mask */ - TRUE), /* pcrel_offset */ - - /* GNU extension to record C++ vtable hierarchy. */ - HOWTO (R_OR32_GNU_VTINHERIT, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 0, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - NULL, /* special_function */ - "R_OR32_GNU_VTINHERIT", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* GNU extension to record C++ vtable member usage. */ - HOWTO (R_OR32_GNU_VTENTRY, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 0, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - _bfd_elf_rel_vtable_reloc_fn, /* special_function */ - "R_OR32_GNU_VTENTRY", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE), /* pcrel_offset */ -}; - -/* Map BFD reloc types to OR32 ELF reloc types. */ - -struct or32_reloc_map -{ - bfd_reloc_code_real_type bfd_reloc_val; - unsigned char elf_reloc_val; -}; - -static const struct or32_reloc_map or32_reloc_map[] = -{ - { BFD_RELOC_NONE, R_OR32_NONE }, - { BFD_RELOC_32, R_OR32_32 }, - { BFD_RELOC_16, R_OR32_16 }, - { BFD_RELOC_8, R_OR32_8 }, - { BFD_RELOC_LO16, R_OR32_CONST }, - { BFD_RELOC_HI16, R_OR32_CONSTH }, - { BFD_RELOC_32_GOT_PCREL, R_OR32_JUMPTARG }, - { BFD_RELOC_VTABLE_INHERIT, R_OR32_GNU_VTINHERIT }, - { BFD_RELOC_VTABLE_ENTRY, R_OR32_GNU_VTENTRY }, -}; - -static reloc_howto_type * -bfd_elf32_bfd_reloc_type_lookup (abfd, code) - bfd *abfd ATTRIBUTE_UNUSED; - bfd_reloc_code_real_type code; -{ - unsigned int i; - - for (i = ARRAY_SIZE (or32_reloc_map); i--;) - { - if (or32_reloc_map[i].bfd_reloc_val == code) - return &elf_or32_howto_table[or32_reloc_map[i].elf_reloc_val]; - } - - return NULL; -} - -/* Set the howto pointer for an OR32 ELF reloc. */ - -static void -or32_info_to_howto_rel (abfd, cache_ptr, dst) - bfd *abfd ATTRIBUTE_UNUSED; - arelent *cache_ptr; - Elf_Internal_Rela *dst; -{ - unsigned int r_type; - - r_type = ELF32_R_TYPE (dst->r_info); - BFD_ASSERT (r_type < (unsigned int) R_OR32_max); - cache_ptr->howto = &elf_or32_howto_table[r_type]; -} - /* Set the right machine number for an OR32 ELF file. */ static bfd_boolean -or32_elf_object_p (abfd) - bfd *abfd; +or32_elf_object_p (bfd *abfd) { (void) bfd_default_set_arch_mach (abfd, bfd_arch_or32, 0); return TRUE; @@ -254,41 +42,22 @@ or32_elf_object_p (abfd) This gets the OR32 architecture right based on the machine number. */ static void -or32_elf_final_write_processing (abfd, linker) - bfd *abfd; - bfd_boolean linker ATTRIBUTE_UNUSED; +or32_elf_final_write_processing (bfd *abfd, + bfd_boolean linker ATTRIBUTE_UNUSED) { - int mach; - unsigned long val; - - switch (mach = bfd_get_mach (abfd)) - { - /* - case bfd_mach_arc_base: - val = E_OR32_MACH_BASE; - break; - */ - default: - val = 0; - return; - } - elf_elfheader (abfd)->e_flags &=~ EF_OR32_MACH; - elf_elfheader (abfd)->e_flags |= val; } -bfd_reloc_status_type -or32_elf_32_reloc (abfd, reloc_entry, symbol, data, input_section, - output_bfd, error_message) - bfd *abfd; - arelent *reloc_entry; - asymbol *symbol; - PTR data; - asection *input_section; - bfd *output_bfd; - char **error_message ATTRIBUTE_UNUSED; +static bfd_reloc_status_type +or32_elf_32_reloc (bfd *abfd, + arelent *reloc_entry, + asymbol *symbol, + void * data, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) { - if (output_bfd != (bfd *) NULL) + if (output_bfd != NULL) { unsigned long insn; bfd_size_type addr = reloc_entry->address; @@ -307,18 +76,16 @@ or32_elf_32_reloc (abfd, reloc_entry, sy return bfd_reloc_continue; } -bfd_reloc_status_type -or32_elf_16_reloc (abfd, reloc_entry, symbol, data, input_section, - output_bfd, error_message) - bfd *abfd; - arelent *reloc_entry; - asymbol *symbol; - PTR data; - asection *input_section; - bfd *output_bfd; - char **error_message ATTRIBUTE_UNUSED; +static bfd_reloc_status_type +or32_elf_16_reloc (bfd *abfd, + arelent *reloc_entry, + asymbol *symbol, + void * data, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) { - if (output_bfd != (bfd *) NULL) + if (output_bfd != NULL) { unsigned short insn; bfd_size_type addr = reloc_entry->address; @@ -337,18 +104,16 @@ or32_elf_16_reloc (abfd, reloc_entry, sy return bfd_reloc_continue; } -bfd_reloc_status_type -or32_elf_8_reloc (abfd, reloc_entry, symbol, data, input_section, - output_bfd, error_message) - bfd *abfd ATTRIBUTE_UNUSED; - arelent *reloc_entry; - asymbol *symbol; - PTR data; - asection *input_section; - bfd *output_bfd; - char **error_message ATTRIBUTE_UNUSED; +static bfd_reloc_status_type +or32_elf_8_reloc (bfd *abfd ATTRIBUTE_UNUSED, + arelent *reloc_entry, + asymbol *symbol, + void * data, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) { - if (output_bfd != (bfd *) NULL) + if (output_bfd != NULL) { unsigned char insn; bfd_size_type addr = reloc_entry->address; @@ -387,16 +152,14 @@ struct or32_consth static struct or32_consth *or32_consth_list; -bfd_reloc_status_type -or32_elf_consth_reloc (abfd, reloc_entry, symbol, data, input_section, - output_bfd, error_message) - bfd *abfd ATTRIBUTE_UNUSED; - arelent *reloc_entry; - asymbol *symbol; - PTR data; - asection *input_section; - bfd *output_bfd; - char **error_message ATTRIBUTE_UNUSED; +static bfd_reloc_status_type +or32_elf_consth_reloc (bfd *abfd ATTRIBUTE_UNUSED, + arelent *reloc_entry, + asymbol *symbol, + void * data, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) { bfd_reloc_status_type ret; bfd_vma relocation; @@ -405,7 +168,7 @@ or32_elf_consth_reloc (abfd, reloc_entry ret = bfd_reloc_ok; if (bfd_is_und_section (symbol->section) - && output_bfd == (bfd *) NULL) + && output_bfd == NULL) ret = bfd_reloc_undefined; if (bfd_is_com_section (symbol->section)) @@ -421,7 +184,7 @@ or32_elf_consth_reloc (abfd, reloc_entry return bfd_reloc_outofrange; /* Save the information, and let LO16 do the actual relocation. */ - n = (struct or32_consth *) bfd_malloc (sizeof *n); + n = bfd_malloc (sizeof *n); if (n == NULL) return bfd_reloc_outofrange; n->addr = (bfd_byte *) data + reloc_entry->address; @@ -429,7 +192,7 @@ or32_elf_consth_reloc (abfd, reloc_entry n->next = or32_consth_list; or32_consth_list = n; - if (output_bfd != (bfd *) NULL) + if (output_bfd != NULL) reloc_entry->address += input_section->output_offset; return ret; @@ -439,16 +202,14 @@ or32_elf_consth_reloc (abfd, reloc_entry inplace relocation; this function exists in order to do the R_OR32_CONSTH relocation described above. */ -bfd_reloc_status_type -or32_elf_const_reloc (abfd, reloc_entry, symbol, data, input_section, - output_bfd, error_message) - bfd *abfd; - arelent *reloc_entry; - asymbol *symbol; - PTR data; - asection *input_section; - bfd *output_bfd; - char **error_message; +static bfd_reloc_status_type +or32_elf_const_reloc (bfd *abfd, + arelent *reloc_entry, + asymbol *symbol, + void * data, + asection *input_section, + bfd *output_bfd, + char **error_message) { if (or32_consth_list != NULL) { @@ -482,7 +243,7 @@ or32_elf_const_reloc (abfd, reloc_entry, or32_consth_list = NULL; } - if (output_bfd != (bfd *) NULL) + if (output_bfd != NULL) { unsigned long insn, tmp; bfd_size_type addr = reloc_entry->address; @@ -505,18 +266,16 @@ or32_elf_const_reloc (abfd, reloc_entry, input_section, output_bfd, error_message); } -bfd_reloc_status_type -or32_elf_jumptarg_reloc (abfd, reloc_entry, symbol, data, input_section, - output_bfd, error_message) - bfd *abfd; - arelent *reloc_entry; - asymbol *symbol ATTRIBUTE_UNUSED; - PTR data; - asection *input_section; - bfd *output_bfd; - char **error_message ATTRIBUTE_UNUSED; +static bfd_reloc_status_type +or32_elf_jumptarg_reloc (bfd *abfd, + arelent *reloc_entry, + asymbol *symbol ATTRIBUTE_UNUSED, + void * data, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) { - if (output_bfd != (bfd *) NULL) + if (output_bfd != NULL) { unsigned long insn, tmp; bfd_size_type addr = reloc_entry->address; @@ -535,6 +294,192 @@ or32_elf_jumptarg_reloc (abfd, reloc_ent return bfd_reloc_continue; } +static reloc_howto_type elf_or32_howto_table[] = +{ + /* This reloc does nothing. */ + HOWTO (R_OR32_NONE, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_OR32_NONE", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* A standard 32 bit relocation. */ + HOWTO (R_OR32_32, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + or32_elf_32_reloc, /* special_function */ + "R_OR32_32", /* name */ + FALSE, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* A standard 16 bit relocation. */ + HOWTO (R_OR32_16, /* type */ + 0, /* rightshift */ + 1, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + or32_elf_16_reloc, /* special_function */ + "R_OR32_16", /* name */ + FALSE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* A standard 8 bit relocation. */ + HOWTO (R_OR32_8, /* type */ + 0, /* rightshift */ + 0, /* size (0 = byte, 1 = short, 2 = long) */ + 8, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + or32_elf_8_reloc, /* special_function */ + "R_OR32_8", /* name */ + FALSE, /* partial_inplace */ + 0x000000ff, /* src_mask */ + 0x000000ff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* A standard low 16 bit relocation. */ + HOWTO (R_OR32_CONST, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + or32_elf_const_reloc, /* special_function */ + "R_OR32_CONST", /* name */ + FALSE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* A standard high 16 bit relocation. */ + HOWTO (R_OR32_CONSTH, /* type */ + 16, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + or32_elf_consth_reloc, /* special_function */ + "R_OR32_CONSTH", /* name */ + FALSE, /* partial_inplace */ + 0xffff0000, /* src_mask */ + 0x0000ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* A standard branch relocation. */ + HOWTO (R_OR32_JUMPTARG, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 28, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + or32_elf_jumptarg_reloc,/* special_function */ + "R_OR32_JUMPTARG", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0x03ffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* GNU extension to record C++ vtable hierarchy. */ + HOWTO (R_OR32_GNU_VTINHERIT, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 0, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + NULL, /* special_function */ + "R_OR32_GNU_VTINHERIT", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* GNU extension to record C++ vtable member usage. */ + HOWTO (R_OR32_GNU_VTENTRY, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 0, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_elf_rel_vtable_reloc_fn, /* special_function */ + "R_OR32_GNU_VTENTRY", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + FALSE), /* pcrel_offset */ +}; + +/* Map BFD reloc types to OR32 ELF reloc types. */ + +struct or32_reloc_map +{ + bfd_reloc_code_real_type bfd_reloc_val; + unsigned char elf_reloc_val; +}; + +static const struct or32_reloc_map or32_reloc_map[] = +{ + { BFD_RELOC_NONE, R_OR32_NONE }, + { BFD_RELOC_32, R_OR32_32 }, + { BFD_RELOC_16, R_OR32_16 }, + { BFD_RELOC_8, R_OR32_8 }, + { BFD_RELOC_LO16, R_OR32_CONST }, + { BFD_RELOC_HI16, R_OR32_CONSTH }, + { BFD_RELOC_32_GOT_PCREL, R_OR32_JUMPTARG }, + { BFD_RELOC_VTABLE_INHERIT, R_OR32_GNU_VTINHERIT }, + { BFD_RELOC_VTABLE_ENTRY, R_OR32_GNU_VTENTRY }, +}; + +static reloc_howto_type * +bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) +{ + unsigned int i; + + for (i = ARRAY_SIZE (or32_reloc_map); i--;) + if (or32_reloc_map[i].bfd_reloc_val == code) + return &elf_or32_howto_table[or32_reloc_map[i].elf_reloc_val]; + + return NULL; +} + +/* Set the howto pointer for an OR32 ELF reloc. */ + +static void +or32_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED, + arelent *cache_ptr, + Elf_Internal_Rela *dst) +{ + unsigned int r_type; + + r_type = ELF32_R_TYPE (dst->r_info); + BFD_ASSERT (r_type < (unsigned int) R_OR32_max); + cache_ptr->howto = &elf_or32_howto_table[r_type]; +} + #define TARGET_LITTLE_SYM bfd_elf32_or32_little_vec #define TARGET_LITTLE_NAME "elf32-littleor32" #define TARGET_BIG_SYM bfd_elf32_or32_big_vec diff -uprN binutils-2.16.91.0.1/bfd/elf32-pj.c binutils-2.16.91.0.2/bfd/elf32-pj.c --- binutils-2.16.91.0.1/bfd/elf32-pj.c 2005-05-10 15:46:42.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-pj.c 2005-07-20 12:27:27.242201451 -0700 @@ -1,22 +1,22 @@ /* picoJava specific support for 32-bit ELF - Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + Copyright 1999, 2000, 2001, 2002, 2005 Free Software Foundation, Inc. Contributed by Steve Chamberlan of Transmeta (sac@pobox.com). -This file is part of BFD, the Binary File Descriptor library. + This file is part of BFD, the Binary File Descriptor library. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ #include "bfd.h" #include "sysdep.h" @@ -25,14 +25,87 @@ Foundation, Inc., 51 Franklin Street - F #include "elf-bfd.h" #include "elf/pj.h" -static bfd_reloc_status_type pj_elf_reloc - PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); -static reloc_howto_type *pj_elf_reloc_type_lookup - PARAMS ((bfd *, bfd_reloc_code_real_type)); -static void pj_elf_info_to_howto - PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); -static void pj_elf_final_write_processing - PARAMS ((bfd *, bfd_boolean)); +/* This function is used for normal relocs. This is like the COFF + function, and is almost certainly incorrect for other ELF targets. */ + +static bfd_reloc_status_type +pj_elf_reloc (bfd *abfd, + arelent *reloc_entry, + asymbol *symbol_in, + void * data, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) +{ + unsigned long insn; + bfd_vma sym_value; + enum elf_pj_reloc_type r_type; + bfd_vma addr = reloc_entry->address; + bfd_byte *hit_data = addr + (bfd_byte *) data; + + r_type = (enum elf_pj_reloc_type) reloc_entry->howto->type; + + if (output_bfd != NULL) + { + /* Partial linking--do nothing. */ + reloc_entry->address += input_section->output_offset; + return bfd_reloc_ok; + } + + if (symbol_in != NULL + && bfd_is_und_section (symbol_in->section)) + return bfd_reloc_undefined; + + if (bfd_is_com_section (symbol_in->section)) + sym_value = 0; + else + sym_value = (symbol_in->value + + symbol_in->section->output_section->vma + + symbol_in->section->output_offset); + + switch (r_type) + { + case R_PJ_DATA_DIR32: + insn = bfd_get_32 (abfd, hit_data); + insn += sym_value + reloc_entry->addend; + bfd_put_32 (abfd, (bfd_vma) insn, hit_data); + break; + + /* Relocations in code are always bigendian, no matter what the + data endianness is. */ + + case R_PJ_CODE_DIR32: + insn = bfd_getb32 (hit_data); + insn += sym_value + reloc_entry->addend; + bfd_putb32 ((bfd_vma) insn, hit_data); + break; + + case R_PJ_CODE_REL16: + insn = bfd_getb16 (hit_data); + insn += sym_value + reloc_entry->addend + - (input_section->output_section->vma + + input_section->output_offset); + bfd_putb16 ((bfd_vma) insn, hit_data); + break; + case R_PJ_CODE_LO16: + insn = bfd_getb16 (hit_data); + insn += sym_value + reloc_entry->addend; + bfd_putb16 ((bfd_vma) insn, hit_data); + break; + + case R_PJ_CODE_HI16: + insn = bfd_getb16 (hit_data); + insn += (sym_value + reloc_entry->addend) >> 16; + bfd_putb16 ((bfd_vma) insn, hit_data); + break; + + default: + abort (); + break; + } + + return bfd_reloc_ok; +} static reloc_howto_type pj_elf_howto_table[] = { @@ -53,7 +126,7 @@ static reloc_howto_type pj_elf_howto_tab /* 32 bit absolute relocation. Setting partial_inplace to TRUE and src_mask to a non-zero value is similar to the COFF toolchain. */ - HOWTO (R_PJ_DATA_DIR32, /* type */ + HOWTO (R_PJ_DATA_DIR32, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 32, /* bitsize */ @@ -68,7 +141,7 @@ static reloc_howto_type pj_elf_howto_tab FALSE), /* pcrel_offset */ /* 32 bit PC relative relocation. */ - HOWTO (R_PJ_CODE_REL32, /* type */ + HOWTO (R_PJ_CODE_REL32, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ 32, /* bitsize */ @@ -83,7 +156,7 @@ static reloc_howto_type pj_elf_howto_tab TRUE), /* pcrel_offset */ /* 16 bit PC relative relocation. */ - HOWTO (R_PJ_CODE_REL16, /* type */ + HOWTO (R_PJ_CODE_REL16, /* type */ 0, /* rightshift */ 1, /* size (0 = byte, 1 = short, 2 = long) */ 16, /* bitsize */ @@ -147,7 +220,7 @@ static reloc_howto_type pj_elf_howto_tab 0xffff, /* dst_mask */ TRUE), /* pcrel_offset */ - /* GNU extension to record C++ vtable hierarchy */ + /* GNU extension to record C++ vtable hierarchy. */ HOWTO (R_PJ_GNU_VTINHERIT, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ @@ -162,7 +235,7 @@ static reloc_howto_type pj_elf_howto_tab 0, /* dst_mask */ FALSE), /* pcrel_offset */ - /* GNU extension to record C++ vtable member usage */ + /* GNU extension to record C++ vtable member usage. */ HOWTO (R_PJ_GNU_VTENTRY, /* type */ 0, /* rightshift */ 2, /* size (0 = byte, 1 = short, 2 = long) */ @@ -178,90 +251,6 @@ static reloc_howto_type pj_elf_howto_tab FALSE), /* pcrel_offset */ }; -/* This function is used for normal relocs. This is like the COFF - function, and is almost certainly incorrect for other ELF targets. */ - -static bfd_reloc_status_type -pj_elf_reloc (abfd, reloc_entry, symbol_in, data, input_section, output_bfd, - error_message) - bfd *abfd; - arelent *reloc_entry; - asymbol *symbol_in; - PTR data; - asection *input_section; - bfd *output_bfd; - char **error_message ATTRIBUTE_UNUSED; -{ - unsigned long insn; - bfd_vma sym_value; - enum elf_pj_reloc_type r_type; - bfd_vma addr = reloc_entry->address; - bfd_byte *hit_data = addr + (bfd_byte *) data; - - r_type = (enum elf_pj_reloc_type) reloc_entry->howto->type; - - if (output_bfd != NULL) - { - /* Partial linking--do nothing. */ - reloc_entry->address += input_section->output_offset; - return bfd_reloc_ok; - } - - if (symbol_in != NULL - && bfd_is_und_section (symbol_in->section)) - return bfd_reloc_undefined; - - if (bfd_is_com_section (symbol_in->section)) - sym_value = 0; - else - sym_value = (symbol_in->value + - symbol_in->section->output_section->vma + - symbol_in->section->output_offset); - - switch (r_type) - { - case R_PJ_DATA_DIR32: - insn = bfd_get_32 (abfd, hit_data); - insn += sym_value + reloc_entry->addend; - bfd_put_32 (abfd, (bfd_vma) insn, hit_data); - break; - - /* Relocations in code are always bigendian, no matter what the - data endianness is. */ - - case R_PJ_CODE_DIR32: - insn = bfd_getb32 (hit_data); - insn += sym_value + reloc_entry->addend; - bfd_putb32 ((bfd_vma) insn, hit_data); - break; - - case R_PJ_CODE_REL16: - insn = bfd_getb16 (hit_data); - insn += sym_value + reloc_entry->addend - - (input_section->output_section->vma - + input_section->output_offset); - bfd_putb16 ((bfd_vma) insn, hit_data); - break; - case R_PJ_CODE_LO16: - insn = bfd_getb16 (hit_data); - insn += sym_value + reloc_entry->addend; - bfd_putb16 ((bfd_vma) insn, hit_data); - break; - - case R_PJ_CODE_HI16: - insn = bfd_getb16 (hit_data); - insn += (sym_value + reloc_entry->addend) >> 16; - bfd_putb16 ((bfd_vma) insn, hit_data); - break; - - default: - abort (); - break; - } - - return bfd_reloc_ok; -} - /* This structure is used to map BFD reloc codes to PJ ELF relocs. */ struct elf_reloc_map @@ -290,17 +279,14 @@ static const struct elf_reloc_map pj_rel corresponding PJ ELf reloc. */ static reloc_howto_type * -pj_elf_reloc_type_lookup (abfd, code) - bfd *abfd ATTRIBUTE_UNUSED; - bfd_reloc_code_real_type code; +pj_elf_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) { unsigned int i; for (i = 0; i < sizeof (pj_reloc_map) / sizeof (struct elf_reloc_map); i++) - { - if (pj_reloc_map[i].bfd_reloc_val == code) - return &pj_elf_howto_table[(int) pj_reloc_map[i].elf_reloc_val]; - } + if (pj_reloc_map[i].bfd_reloc_val == code) + return & pj_elf_howto_table[(int) pj_reloc_map[i].elf_reloc_val]; return NULL; } @@ -308,10 +294,9 @@ pj_elf_reloc_type_lookup (abfd, code) /* Given an ELF reloc, fill in the howto field of a relent. */ static void -pj_elf_info_to_howto (abfd, cache_ptr, dst) - bfd *abfd ATTRIBUTE_UNUSED; - arelent *cache_ptr; - Elf_Internal_Rela *dst; +pj_elf_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED, + arelent *cache_ptr, + Elf_Internal_Rela *dst) { unsigned int r; @@ -326,12 +311,11 @@ pj_elf_info_to_howto (abfd, cache_ptr, d e_flags field. */ static void -pj_elf_final_write_processing (abfd, linker) - bfd *abfd; - bfd_boolean linker ATTRIBUTE_UNUSED; +pj_elf_final_write_processing (bfd *abfd, + bfd_boolean linker ATTRIBUTE_UNUSED) { - elf_elfheader (abfd)->e_flags |= EF_PICOJAVA_ARCH; - elf_elfheader (abfd)->e_flags |= EF_PICOJAVA_GNUCALLS; + elf_elfheader (abfd)->e_flags |= EF_PICOJAVA_ARCH; + elf_elfheader (abfd)->e_flags |= EF_PICOJAVA_GNUCALLS; } #define TARGET_BIG_SYM bfd_elf32_pj_vec diff -uprN binutils-2.16.91.0.1/bfd/elf32-ppc.c binutils-2.16.91.0.2/bfd/elf32-ppc.c --- binutils-2.16.91.0.1/bfd/elf32-ppc.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-ppc.c 2005-07-20 12:27:27.261198319 -0700 @@ -32,6 +32,7 @@ #include "elf-bfd.h" #include "elf/ppc.h" #include "elf32-ppc.h" +#include "elf-vxworks.h" /* RELA relocations are used here. */ @@ -52,12 +53,6 @@ static bfd_reloc_status_type ppc_elf_unh #define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1" /* For old-style PLT. */ -/* The size in bytes of an entry in the procedure linkage table. */ -#define PLT_ENTRY_SIZE 12 -/* The initial size of the plt reserved for the dynamic linker. */ -#define PLT_INITIAL_ENTRY_SIZE 72 -/* The size of the gap between entries in the PLT. */ -#define PLT_SLOT_SIZE 8 /* The number of single-slot PLT entries (the rest use two slots). */ #define PLT_NUM_SINGLE_ENTRIES 8192 @@ -65,6 +60,73 @@ static bfd_reloc_status_type ppc_elf_unh #define GLINK_PLTRESOLVE 16*4 #define GLINK_ENTRY_SIZE 4*4 +/* VxWorks uses its own plt layout, filled in by the static linker. */ + +/* The standard VxWorks PLT entry. */ +#define VXWORKS_PLT_ENTRY_SIZE 32 +static const bfd_vma ppc_elf_vxworks_plt_entry + [VXWORKS_PLT_ENTRY_SIZE / 4] = + { + 0x3d800000, /* lis r12,0 */ + 0x818c0000, /* lwz r12,0(r12) */ + 0x7d8903a6, /* mtctr r12 */ + 0x4e800420, /* bctr */ + 0x39600000, /* li r11,0 */ + 0x48000000, /* b 14 <.PLT0resolve+0x4> */ + 0x60000000, /* nop */ + 0x60000000, /* nop */ + }; +static const bfd_vma ppc_elf_vxworks_pic_plt_entry + [VXWORKS_PLT_ENTRY_SIZE / 4] = + { + 0x3d9e0000, /* addis r12,r30,0 */ + 0x818c0000, /* lwz r12,0(r12) */ + 0x7d8903a6, /* mtctr r12 */ + 0x4e800420, /* bctr */ + 0x39600000, /* li r11,0 */ + 0x48000000, /* b 14 <.PLT0resolve+0x4> 14: R_PPC_REL24 .PLTresolve */ + 0x60000000, /* nop */ + 0x60000000, /* nop */ + }; + +/* The initial VxWorks PLT entry. */ +#define VXWORKS_PLT_INITIAL_ENTRY_SIZE 32 +static const bfd_vma ppc_elf_vxworks_plt0_entry + [VXWORKS_PLT_INITIAL_ENTRY_SIZE / 4] = + { + 0x3d800000, /* lis r12,0 */ + 0x398c0000, /* addi r12,r12,0 */ + 0x800c0008, /* lwz r0,8(r12) */ + 0x7c0903a6, /* mtctr r0 */ + 0x818c0004, /* lwz r12,4(r12) */ + 0x4e800420, /* bctr */ + 0x60000000, /* nop */ + 0x60000000, /* nop */ + }; +static const bfd_vma ppc_elf_vxworks_pic_plt0_entry + [VXWORKS_PLT_INITIAL_ENTRY_SIZE / 4] = + { + 0x819e0008, /* lwz r12,8(r30) */ + 0x7d8903a6, /* mtctr r12 */ + 0x819e0004, /* lwz r12,4(r30) */ + 0x4e800420, /* bctr */ + 0x60000000, /* nop */ + 0x60000000, /* nop */ + 0x60000000, /* nop */ + 0x60000000, /* nop */ + }; + +/* For executables, we have some additional relocations in + .rela.plt.unloaded, for the kernel loader. */ + +/* The number of non-JMP_SLOT relocations per PLT0 slot. */ +#define VXWORKS_PLT_NON_JMP_SLOT_RELOCS 3 +/* The number of relocations in the PLTResolve slot. */ +#define VXWORKS_PLTRESOLVE_RELOCS 2 +/* The number of relocations in the PLTResolve slot when when creating + a shared library. */ +#define VXWORKS_PLTRESOLVE_RELOCS_SHLIB 0 + /* Some instructions. */ #define ADDIS_11_11 0x3d6b0000 #define ADDIS_11_30 0x3d7e0000 @@ -1828,70 +1890,44 @@ ppc_elf_additional_program_headers (bfd that the linker doesn't crater when trying to make more than 2 sections. */ -static struct bfd_elf_special_section const - ppc_special_sections_p[] = +static const struct bfd_elf_special_section ppc_elf_special_sections[] = { { ".plt", 4, 0, SHT_NOBITS, SHF_ALLOC + SHF_EXECINSTR }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - ppc_special_sections_s[] = -{ - { ".sdata", 6, -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, { ".sbss", 5, -2, SHT_NOBITS, SHF_ALLOC + SHF_WRITE }, - { ".sdata2", 7, -2, SHT_PROGBITS, SHF_ALLOC }, { ".sbss2", 6, -2, SHT_PROGBITS, SHF_ALLOC }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - ppc_special_sections_t[] = -{ + { ".sdata", 6, -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, + { ".sdata2", 7, -2, SHT_PROGBITS, SHF_ALLOC }, { ".tags", 5, 0, SHT_ORDERED, SHF_ALLOC }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - ppc_special_sections_other[]= -{ { ".PPC.EMB.apuinfo", 16, 0, SHT_NOTE, 0 }, - { ".PPC.EMB.sdata0", 15, 0, SHT_PROGBITS, SHF_ALLOC }, { ".PPC.EMB.sbss0", 14, 0, SHT_PROGBITS, SHF_ALLOC }, - { NULL, 0, 0, 0, 0 } + { ".PPC.EMB.sdata0", 15, 0, SHT_PROGBITS, SHF_ALLOC }, + { NULL, 0, 0, 0, 0 } }; -static struct bfd_elf_special_section const * - ppc_elf_special_sections[27]= +/* This is what we want for new plt/got. */ +static struct bfd_elf_special_section ppc_alt_plt = + { ".plt", 4, 0, SHT_PROGBITS, SHF_ALLOC }; + +static const struct bfd_elf_special_section * +ppc_elf_get_sec_type_attr (bfd *abfd ATTRIBUTE_UNUSED, asection *sec) { - NULL, /* 'a' */ - NULL, /* 'b' */ - NULL, /* 'c' */ - NULL, /* 'd' */ - NULL, /* 'e' */ - NULL, /* 'f' */ - NULL, /* 'g' */ - NULL, /* 'h' */ - NULL, /* 'i' */ - NULL, /* 'j' */ - NULL, /* 'k' */ - NULL, /* 'l' */ - NULL, /* 'm' */ - NULL, /* 'n' */ - NULL, /* 'o' */ - ppc_special_sections_p, /* 'p' */ - NULL, /* 'q' */ - NULL, /* 'r' */ - ppc_special_sections_s, /* 's' */ - ppc_special_sections_t, /* 's' */ - NULL, /* 'u' */ - NULL, /* 'v' */ - NULL, /* 'w' */ - NULL, /* 'x' */ - NULL, /* 'y' */ - NULL, /* 'z' */ - ppc_special_sections_other, /* other */ -}; + const struct bfd_elf_special_section *ssect; + + /* See if this is one of the special sections. */ + if (sec->name == NULL) + return NULL; + + ssect = _bfd_elf_get_special_section (sec->name, ppc_elf_special_sections, + sec->use_rela_p); + if (ssect != NULL) + { + if (ssect == ppc_elf_special_sections && (sec->flags & SEC_LOAD) != 0) + ssect = &ppc_alt_plt; + return ssect; + } + + return _bfd_elf_get_sec_type_attr (abfd, sec); +} /* Very simple linked list structure for recording apuinfo values. */ typedef struct apuinfo_list @@ -2319,6 +2355,25 @@ struct ppc_elf_link_hash_table /* Small local sym to section mapping cache. */ struct sym_sec_cache sym_sec; + + /* The (unloaded but important) .rela.plt.unloaded on VxWorks. */ + asection *srelplt2; + + /* The .got.plt section (VxWorks only)*/ + asection *sgotplt; + + /* Short-cuts to frequently used symbols on VxWorks targets. */ + struct elf_link_hash_entry *hgot, *hplt; + + /* True if the target system is VxWorks. */ + int is_vxworks; + + /* The size of PLT entries. */ + int plt_entry_size; + /* The distance between adjacent PLT slots. */ + int plt_slot_size; + /* The size of the first PLT entry. */ + int plt_initial_entry_size; }; /* Get the PPC ELF linker hash table from a link_info structure. */ @@ -2386,10 +2441,16 @@ ppc_elf_link_hash_table_create (bfd *abf ret->sdata[1].sym_name = "_SDA2_BASE_"; ret->sdata[1].bss_name = ".sbss2"; + ret->plt_entry_size = 12; + ret->plt_slot_size = 8; + ret->plt_initial_entry_size = 72; + + ret->is_vxworks = 0; + return &ret->elf.root; } -/* The powerpc .got has a blrl instruction in it. Mark it executable. */ +/* Create .got and the related sections. */ static bfd_boolean ppc_elf_create_got (bfd *abfd, struct bfd_link_info *info) @@ -2406,10 +2467,21 @@ ppc_elf_create_got (bfd *abfd, struct bf if (s == NULL) abort (); - flags = (SEC_ALLOC | SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS | SEC_IN_MEMORY - | SEC_LINKER_CREATED); - if (!bfd_set_section_flags (abfd, s, flags)) - return FALSE; + if (htab->is_vxworks) + { + htab->sgotplt = bfd_get_section_by_name (abfd, ".got.plt"); + if (!htab->sgotplt) + abort (); + } + else + { + /* The powerpc .got has a blrl instruction in it. Mark it + executable. */ + flags = (SEC_ALLOC | SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS + | SEC_IN_MEMORY | SEC_LINKER_CREATED); + if (!bfd_set_section_flags (abfd, s, flags)) + return FALSE; + } flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY); @@ -2467,6 +2539,20 @@ ppc_elf_create_dynamic_sections (bfd *ab return FALSE; } + /* Create the section for VxWorks static plt relocations. */ + if (htab->is_vxworks && !info->shared) + { + s = bfd_make_section (abfd, ".rela.plt.unloaded"); + flags = (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_READONLY + | SEC_LINKER_CREATED); + if (s == NULL + || ! bfd_set_section_flags (abfd, s, flags) + || ! bfd_set_section_alignment (abfd, s, + get_elf_backend_data (abfd)->s->log_file_align)) + return FALSE; + htab->srelplt2 = s; + } + htab->relplt = bfd_get_section_by_name (abfd, ".rela.plt"); htab->plt = s = bfd_get_section_by_name (abfd, ".plt"); if (s == NULL) @@ -3449,15 +3535,26 @@ ppc_elf_select_plt_layout (bfd *output_b int force_old_plt) { struct ppc_elf_link_hash_table *htab; + flagword flags; htab = ppc_elf_hash_table (info); if (force_old_plt || !htab->new_plt) htab->old_plt = 1; - if (!htab->old_plt) + if (htab->is_vxworks) { - flagword flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS - | SEC_IN_MEMORY | SEC_LINKER_CREATED); + /* The VxWorks PLT is a loaded section with contents. */ + flags = SEC_ALLOC | SEC_CODE | SEC_IN_MEMORY | SEC_LINKER_CREATED + | SEC_HAS_CONTENTS | SEC_LOAD | SEC_READONLY; + + if (htab->plt != NULL + && !bfd_set_section_flags (htab->elf.dynobj, htab->plt, flags)) + return -1; + } + else if (!htab->old_plt) + { + flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS + | SEC_IN_MEMORY | SEC_LINKER_CREATED); /* The new PLT is a loaded section. */ if (htab->plt != NULL @@ -3945,6 +4042,24 @@ ppc_elf_adjust_dynamic_symbol (struct bf /* This is a reference to a symbol defined by a dynamic object which is not a function. */ + /* First, a fudge for old shared libs that export some symbols they + should not. */ + if (!h->def_regular + && (strcmp (h->root.root.string, "_SDA_BASE_") == 0 + || strcmp (h->root.root.string, "_SDA2_BASE_") == 0)) + { + /* These symbols will be defined later, as if they were defined in + a linker script. We don't want to use a definition in a shared + object. */ + const struct elf_backend_data *bed; + + bed = get_elf_backend_data (htab->elf.dynobj); + (*bed->elf_backend_hide_symbol) (info, h, TRUE); + h->root.type = bfd_link_hash_undefined; + h->root.u.undef.abfd = htab->elf.dynobj; + return TRUE; + } + /* If we are creating a shared library, we must presume that the only references to the symbol are via the global offset table. For such cases we need not do anything here; the relocations will @@ -4050,7 +4165,12 @@ allocate_got (struct ppc_elf_link_hash_t if (htab->old_plt) max_before_header = 32764; - if (need <= htab->got_gap) + if (htab->is_vxworks) + { + where = htab->got->size; + htab->got->size += need; + } + else if (need <= htab->got_gap) { where = max_before_header - htab->got_gap; htab->got_gap -= need; @@ -4111,7 +4231,7 @@ allocate_dynrelocs (struct elf_link_hash { asection *s = htab->plt; - if (!htab->old_plt) + if (!(htab->old_plt || htab->is_vxworks)) { if (!doneone) { @@ -4142,16 +4262,17 @@ allocate_dynrelocs (struct elf_link_hash /* If this is the first .plt entry, make room for the special first entry. */ if (s->size == 0) - s->size += PLT_INITIAL_ENTRY_SIZE; + s->size += htab->plt_initial_entry_size; /* The PowerPC PLT is actually composed of two parts, the first part is 2 words (for a load and a jump), and then there is a remaining word available at the end. */ - plt_offset = (PLT_INITIAL_ENTRY_SIZE - + (PLT_SLOT_SIZE - * ((s->size - PLT_INITIAL_ENTRY_SIZE) - / PLT_ENTRY_SIZE))); + plt_offset = (htab->plt_initial_entry_size + + (htab->plt_slot_size + * ((s->size + - htab->plt_initial_entry_size) + / htab->plt_entry_size))); /* If this symbol is not defined in a regular file, and we are not generating a shared @@ -4166,12 +4287,15 @@ allocate_dynrelocs (struct elf_link_hash h->root.u.def.value = plt_offset; } - /* Make room for this entry. After the 8192nd - entry, room for two entries is allocated. */ - s->size += PLT_ENTRY_SIZE; - if ((s->size - PLT_INITIAL_ENTRY_SIZE) / PLT_ENTRY_SIZE - > PLT_NUM_SINGLE_ENTRIES) - s->size += PLT_ENTRY_SIZE; + /* Make room for this entry. */ + s->size += htab->plt_entry_size; + /* After the 8192nd entry, room for two entries + is allocated. */ + if (!htab->is_vxworks + && (s->size - htab->plt_initial_entry_size) + / htab->plt_entry_size + > PLT_NUM_SINGLE_ENTRIES) + s->size += htab->plt_entry_size; } ent->plt.offset = plt_offset; } @@ -4180,6 +4304,29 @@ allocate_dynrelocs (struct elf_link_hash if (!doneone) { htab->relplt->size += sizeof (Elf32_External_Rela); + + if (htab->is_vxworks) + { + /* Allocate space for the unloaded relocations. */ + if (!info->shared) + { + if (ent->plt.offset + == (bfd_vma) htab->plt_initial_entry_size) + { + htab->srelplt2->size + += sizeof (Elf32_External_Rela) + * VXWORKS_PLTRESOLVE_RELOCS; + } + + htab->srelplt2->size + += sizeof (Elf32_External_Rela) + * VXWORKS_PLT_NON_JMP_SLOT_RELOCS; + } + + /* Every PLT entry has an associated GOT entry in + .got.plt. */ + htab->sgotplt->size += 4; + } doneone = TRUE; } } @@ -4497,10 +4644,31 @@ ppc_elf_size_dynamic_sections (bfd *outp else htab->tlsld_got.offset = (bfd_vma) -1; + if (htab->is_vxworks) + { + /* Save the GOT and PLT symbols in the hash table for easy access. + Mark them as having relocations; they might not, but we won't + know for sure until we build the GOT in finish_dynamic_symbol. */ + + htab->hgot = elf_link_hash_lookup (elf_hash_table (info), + "_GLOBAL_OFFSET_TABLE_", + FALSE, FALSE, FALSE); + if (htab->hgot) + htab->hgot->indx = -2; + htab->hplt = elf_link_hash_lookup (elf_hash_table (info), + "_PROCEDURE_LINKAGE_TABLE_", + FALSE, FALSE, FALSE); + if (htab->hplt) + htab->hplt->indx = -2; + /* If the PLT is executable then give the symbol function type. */ + if (htab->hplt && htab->plt->flags & SEC_CODE) + htab->hplt->type = STT_FUNC; + } + /* Allocate space for global sym dynamic relocs. */ elf_link_hash_traverse (elf_hash_table (info), allocate_dynrelocs, info); - if (htab->got != NULL) + if (htab->got != NULL && !htab->is_vxworks) { unsigned int g_o_t = 32768; @@ -4510,7 +4678,7 @@ ppc_elf_size_dynamic_sections (bfd *outp g_o_t = htab->got->size; htab->got->size += htab->got_header_size; } - if (htab->old_plt) + if (htab->old_plt && !htab->is_vxworks) g_o_t += 4; htab->elf.hgot->root.u.def.value = g_o_t; @@ -4531,14 +4699,24 @@ ppc_elf_size_dynamic_sections (bfd *outp relocs = FALSE; for (s = htab->elf.dynobj->sections; s != NULL; s = s->next) { + bfd_boolean strip_section = TRUE; + if ((s->flags & SEC_LINKER_CREATED) == 0) continue; if (s == htab->plt || s == htab->glink || s == htab->got - || s == htab->sbss) - { + || s == htab->sgotplt + || s == htab->sbss + || s == htab->dynbss + || s == htab->dynsbss) + { + /* We'd like to strip these sections if they aren't needed, but if + we've exported dynamic symbols from them we must leave them. + It's too late to tell BFD to get rid of the symbols. */ + if ((s == htab->plt || s == htab->got) && htab->hplt != NULL) + strip_section = FALSE; /* Strip this section if we don't need it; see the comment below. */ } @@ -4549,19 +4727,7 @@ ppc_elf_size_dynamic_sections (bfd *outp } else if (strncmp (bfd_get_section_name (dynobj, s), ".rela", 5) == 0) { - if (s->size == 0) - { - /* If we don't need this section, strip it from the - output file. This is mostly to handle .rela.bss and - .rela.plt. We must create both sections in - create_dynamic_sections, because they must be created - before the linker maps input sections to output - sections. The linker does that before - adjust_dynamic_symbol is called, and it is that - function which decides whether anything needs to go - into these sections. */ - } - else + if (s->size != 0) { /* Remember whether there are any relocation sections. */ relocs = TRUE; @@ -4577,8 +4743,17 @@ ppc_elf_size_dynamic_sections (bfd *outp continue; } - if (s->size == 0) + if (s->size == 0 && strip_section) { + /* If we don't need this section, strip it from the + output file. This is mostly to handle .rela.bss and + .rela.plt. We must create both sections in + create_dynamic_sections, because they must be created + before the linker maps input sections to output + sections. The linker does that before + adjust_dynamic_symbol is called, and it is that + function which decides whether anything needs to go + into these sections. */ s->flags |= SEC_EXCLUDE; continue; } @@ -5086,7 +5261,7 @@ ppc_elf_relax_section (bfd *abfd, statement runs the risk of section alignment affecting where the section starts. */ -bfd_boolean +void ppc_elf_set_sdata_syms (bfd *obfd, struct bfd_link_info *info) { struct ppc_elf_link_hash_table *htab; @@ -5108,25 +5283,21 @@ ppc_elf_set_sdata_syms (bfd *obfd, struc if (s == NULL) s = bfd_get_section_by_name (obfd, lsect->bss_name); - val = 0; - if (s != NULL) - val = s->vma + 32768; - lsect->sym_val = val; + if (s) + { + /* VxWorks executables are relocatable, so the sdata base symbols + must be section-relative. */ + val = 32768; + lsect->sym_val = val + s->vma; + } + else + { + val = 0; + lsect->sym_val = 0; + } - _bfd_elf_provide_symbol (info, lsect->sym_name, val); + _bfd_elf_provide_symbol (info, lsect->sym_name, val, s); } - - s = bfd_get_section_by_name (obfd, ".sbss"); - val = 0; - if (s != NULL) - val = s->vma; - _bfd_elf_provide_symbol (info, "__sbss_start", val); - _bfd_elf_provide_symbol (info, "___sbss_start", val); - if (s != NULL) - val += s->size; - _bfd_elf_provide_symbol (info, "__sbss_end", val); - _bfd_elf_provide_symbol (info, "___sbss_end", val); - return TRUE; } /* Fill in the address for a pointer generated in a linker section. */ @@ -6447,38 +6618,171 @@ ppc_elf_finish_dynamic_symbol (bfd *outp bfd_byte *loc; bfd_vma reloc_index; + if (!(htab->old_plt || htab->is_vxworks)) + reloc_index = ent->plt.offset / 4; + else + { + reloc_index = ((ent->plt.offset - htab->plt_initial_entry_size) + / htab->plt_slot_size); + if (reloc_index > PLT_NUM_SINGLE_ENTRIES + && !htab->is_vxworks) + reloc_index -= (reloc_index - PLT_NUM_SINGLE_ENTRIES) / 2; + } + /* This symbol has an entry in the procedure linkage table. Set it up. */ - if (htab->old_plt) + if (htab->is_vxworks) { - /* We don't need to fill in the .plt. The ppc dynamic - linker will fill it in. */ + bfd_vma got_offset; + const bfd_vma *plt_entry; + + /* The first three entries in .got.plt are reserved. */ + got_offset = (reloc_index + 3) * 4; + + /* Use the right PLT. */ + plt_entry = info->shared ? ppc_elf_vxworks_pic_plt_entry + : ppc_elf_vxworks_plt_entry; + + /* Fill in the .plt on VxWorks. */ + if (info->shared) + { + bfd_vma got_offset_hi = (got_offset >> 16) + + ((got_offset & 0x8000) >> 15); + + bfd_put_32 (output_bfd, + plt_entry[0] | (got_offset_hi & 0xffff), + htab->plt->contents + ent->plt.offset + 0); + bfd_put_32 (output_bfd, + plt_entry[1] | (got_offset & 0xffff), + htab->plt->contents + ent->plt.offset + 4); + } + else + { + bfd_vma got_loc = (got_offset + + htab->hgot->root.u.def.value + + htab->hgot->root.u.def.section->output_offset + + htab->hgot->root.u.def.section->output_section->vma); + bfd_vma got_loc_hi = (got_loc >> 16) + + ((got_loc & 0x8000) >> 15); + + bfd_put_32 (output_bfd, + plt_entry[0] | (got_loc_hi & 0xffff), + htab->plt->contents + ent->plt.offset + 0); + bfd_put_32 (output_bfd, + plt_entry[1] | (got_loc & 0xffff), + htab->plt->contents + ent->plt.offset + 4); + } + + bfd_put_32 (output_bfd, plt_entry[2], + htab->plt->contents + ent->plt.offset + 8); + bfd_put_32 (output_bfd, plt_entry[3], + htab->plt->contents + ent->plt.offset + 12); + + /* This instruction is an immediate load. The value loaded is + the byte offset of the R_PPC_JMP_SLOT relocation from the + start of the .rela.plt section. The value is stored in the + low-order 16 bits of the load instruction. */ + /* NOTE: It appears that this is now an index rather than a + prescaled offset. */ + bfd_put_32 (output_bfd, + plt_entry[4] | reloc_index, + htab->plt->contents + ent->plt.offset + 16); + /* This instruction is a PC-relative branch whose target is + the start of the PLT section. The address of this branch + instruction is 20 bytes beyond the start of this PLT entry. + The address is encoded in bits 6-29, inclusive. The value + stored is right-shifted by two bits, permitting a 26-bit + offset. */ + bfd_put_32 (output_bfd, + (plt_entry[5] + | (-(ent->plt.offset + 20) & 0x03fffffc)), + htab->plt->contents + ent->plt.offset + 20); + bfd_put_32 (output_bfd, plt_entry[6], + htab->plt->contents + ent->plt.offset + 24); + bfd_put_32 (output_bfd, plt_entry[7], + htab->plt->contents + ent->plt.offset + 28); + + /* Fill in the GOT entry corresponding to this PLT slot with + the address immediately after the the "bctr" instruction + in this PLT entry. */ + bfd_put_32 (output_bfd, (htab->plt->output_section->vma + + htab->plt->output_offset + + ent->plt.offset + 16), + htab->sgotplt->contents + got_offset); + + if (!info->shared) + { + /* Fill in a couple of entries in .rela.plt.unloaded. */ + loc = htab->srelplt2->contents + + ((VXWORKS_PLTRESOLVE_RELOCS + reloc_index + * VXWORKS_PLT_NON_JMP_SLOT_RELOCS) + * sizeof (Elf32_External_Rela)); + + /* Provide the @ha relocation for the first instruction. */ + rela.r_offset = (htab->plt->output_section->vma + + htab->plt->output_offset + + ent->plt.offset + 2); + rela.r_info = ELF32_R_INFO (htab->hgot->indx, + R_PPC_ADDR16_HA); + rela.r_addend = got_offset; + bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); + loc += sizeof (Elf32_External_Rela); + + /* Provide the @l relocation for the second instruction. */ + rela.r_offset = (htab->plt->output_section->vma + + htab->plt->output_offset + + ent->plt.offset + 6); + rela.r_info = ELF32_R_INFO (htab->hgot->indx, + R_PPC_ADDR16_LO); + rela.r_addend = got_offset; + bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); + loc += sizeof (Elf32_External_Rela); + + /* Provide a relocation for the GOT entry corresponding to this + PLT slot. Point it at the middle of the .plt entry. */ + rela.r_offset = (htab->sgotplt->output_section->vma + + htab->sgotplt->output_offset + + got_offset); + rela.r_info = ELF32_R_INFO (htab->hplt->indx, + R_PPC_ADDR32); + rela.r_addend = ent->plt.offset + 16; + bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); + } + + /* VxWorks uses non-standard semantics for R_PPC_JMP_SLOT. + In particular, the offset for the relocation is not the + address of the PLT entry for this function, as specified + by the ABI. Instead, the offset is set to the address of + the GOT slot for this function. See EABI 4.4.4.1. */ + rela.r_offset = (htab->sgotplt->output_section->vma + + htab->sgotplt->output_offset + + got_offset); + } else { - bfd_vma val = (htab->glink_pltresolve + ent->plt.offset - + htab->glink->output_section->vma - + htab->glink->output_offset); - bfd_put_32 (output_bfd, val, - htab->plt->contents + ent->plt.offset); + rela.r_offset = (htab->plt->output_section->vma + + htab->plt->output_offset + + ent->plt.offset); + if (htab->old_plt) + { + /* We don't need to fill in the .plt. The ppc dynamic + linker will fill it in. */ + } + else + { + bfd_vma val = (htab->glink_pltresolve + ent->plt.offset + + htab->glink->output_section->vma + + htab->glink->output_offset); + bfd_put_32 (output_bfd, val, + htab->plt->contents + ent->plt.offset); + } } /* Fill in the entry in the .rela.plt section. */ - rela.r_offset = (htab->plt->output_section->vma - + htab->plt->output_offset - + ent->plt.offset); rela.r_info = ELF32_R_INFO (h->dynindx, R_PPC_JMP_SLOT); rela.r_addend = 0; - if (!htab->old_plt) - reloc_index = ent->plt.offset / 4; - else - { - reloc_index = ((ent->plt.offset - PLT_INITIAL_ENTRY_SIZE) - / PLT_SLOT_SIZE); - if (reloc_index > PLT_NUM_SINGLE_ENTRIES) - reloc_index -= (reloc_index - PLT_NUM_SINGLE_ENTRIES) / 2; - } loc = (htab->relplt->contents + reloc_index * sizeof (Elf32_External_Rela)); bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); @@ -6599,9 +6903,11 @@ ppc_elf_finish_dynamic_symbol (bfd *outp #endif /* Mark some specially defined symbols as absolute. */ - if (h == htab->elf.hgot - || strcmp (h->root.root.string, "_DYNAMIC") == 0 - || strcmp (h->root.root.string, "_PROCEDURE_LINKAGE_TABLE_") == 0) + if (strcmp (h->root.root.string, "_DYNAMIC") == 0 + || (!htab->is_vxworks + && (h == htab->elf.hgot + || strcmp (h->root.root.string, + "_PROCEDURE_LINKAGE_TABLE_") == 0))) sym->st_shndx = SHN_ABS; return TRUE; @@ -6632,15 +6938,22 @@ ppc_elf_finish_dynamic_sections (bfd *ou struct bfd_link_info *info) { asection *sdyn; + asection *splt; struct ppc_elf_link_hash_table *htab; bfd_vma got; + bfd * dynobj; #ifdef DEBUG fprintf (stderr, "ppc_elf_finish_dynamic_sections called\n"); #endif htab = ppc_elf_hash_table (info); - sdyn = bfd_get_section_by_name (htab->elf.dynobj, ".dynamic"); + dynobj = elf_hash_table (info)->dynobj; + sdyn = bfd_get_section_by_name (dynobj, ".dynamic"); + if (htab->is_vxworks) + splt = bfd_get_section_by_name (dynobj, ".plt"); + else + splt = NULL; got = 0; if (htab->elf.hgot != NULL) @@ -6661,12 +6974,15 @@ ppc_elf_finish_dynamic_sections (bfd *ou Elf_Internal_Dyn dyn; asection *s; - bfd_elf32_swap_dyn_in (htab->elf.dynobj, dyncon, &dyn); + bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn); switch (dyn.d_tag) { case DT_PLTGOT: - s = htab->plt; + if (htab->is_vxworks) + s = htab->sgotplt; + else + s = htab->plt; dyn.d_un.d_ptr = s->output_section->vma + s->output_offset; break; @@ -6683,6 +6999,15 @@ ppc_elf_finish_dynamic_sections (bfd *ou dyn.d_un.d_ptr = got; break; + case DT_RELASZ: + if (htab->is_vxworks) + { + if (htab->relplt) + dyn.d_un.d_ptr -= htab->relplt->size; + break; + } + continue; + default: continue; } @@ -6699,7 +7024,7 @@ ppc_elf_finish_dynamic_sections (bfd *ou bfd_vma val; p += elf_hash_table (info)->hgot->root.u.def.value; - if (htab->old_plt) + if (htab->old_plt && !htab->is_vxworks) bfd_put_32 (output_bfd, 0x4e800021 /* blrl */, p - 4); val = 0; @@ -6710,6 +7035,89 @@ ppc_elf_finish_dynamic_sections (bfd *ou elf_section_data (htab->got->output_section)->this_hdr.sh_entsize = 4; } + /* Fill in the first entry in the VxWorks procedure linkage table. */ + if (splt && splt->size > 0) + { + /* Use the right PLT. */ + static const bfd_vma *plt_entry = NULL; + plt_entry = info->shared ? + ppc_elf_vxworks_pic_plt0_entry : ppc_elf_vxworks_plt0_entry; + + if (!info->shared) + { + bfd_vma got_value = + (htab->hgot->root.u.def.section->output_section->vma + + htab->hgot->root.u.def.section->output_offset + + htab->hgot->root.u.def.value); + bfd_vma got_hi = (got_value >> 16) + ((got_value & 0x8000) >> 15); + + bfd_put_32 (output_bfd, plt_entry[0] | (got_hi & 0xffff), + splt->contents + 0); + bfd_put_32 (output_bfd, plt_entry[1] | (got_value & 0xffff), + splt->contents + 4); + } + else + { + bfd_put_32 (output_bfd, plt_entry[0], splt->contents + 0); + bfd_put_32 (output_bfd, plt_entry[1], splt->contents + 4); + } + bfd_put_32 (output_bfd, plt_entry[2], splt->contents + 8); + bfd_put_32 (output_bfd, plt_entry[3], splt->contents + 12); + bfd_put_32 (output_bfd, plt_entry[4], splt->contents + 16); + bfd_put_32 (output_bfd, plt_entry[5], splt->contents + 20); + bfd_put_32 (output_bfd, plt_entry[6], splt->contents + 24); + bfd_put_32 (output_bfd, plt_entry[7], splt->contents + 28); + + if (! info->shared) + { + Elf_Internal_Rela rela; + bfd_byte *loc; + + loc = htab->srelplt2->contents; + + /* Output the @ha relocation for the first instruction. */ + rela.r_offset = (htab->plt->output_section->vma + + htab->plt->output_offset + + 2); + rela.r_info = ELF32_R_INFO (htab->hgot->indx, R_PPC_ADDR16_HA); + rela.r_addend = 0; + bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); + loc += sizeof (Elf32_External_Rela); + + /* Output the @l relocation for the second instruction. */ + rela.r_offset = (htab->plt->output_section->vma + + htab->plt->output_offset + + 6); + rela.r_info = ELF32_R_INFO (htab->hgot->indx, R_PPC_ADDR16_LO); + rela.r_addend = 0; + bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); + loc += sizeof (Elf32_External_Rela); + + /* Fix up the remaining relocations. They may have the wrong + symbol index for _G_O_T_ or _P_L_T_ depending on the order + in which symbols were output. */ + while (loc < htab->srelplt2->contents + htab->srelplt2->size) + { + Elf_Internal_Rela rel; + + bfd_elf32_swap_reloc_in (output_bfd, loc, &rel); + rel.r_info = ELF32_R_INFO (htab->hgot->indx, R_PPC_ADDR16_HA); + bfd_elf32_swap_reloc_out (output_bfd, &rel, loc); + loc += sizeof (Elf32_External_Rela); + + bfd_elf32_swap_reloc_in (output_bfd, loc, &rel); + rel.r_info = ELF32_R_INFO (htab->hgot->indx, R_PPC_ADDR16_LO); + bfd_elf32_swap_reloc_out (output_bfd, &rel, loc); + loc += sizeof (Elf32_External_Rela); + + bfd_elf32_swap_reloc_in (output_bfd, loc, &rel); + rel.r_info = ELF32_R_INFO (htab->hplt->indx, R_PPC_ADDR32); + bfd_elf32_swap_reloc_out (output_bfd, &rel, loc); + loc += sizeof (Elf32_External_Rela); + } + } + } + if (htab->glink != NULL && htab->glink->contents != NULL) { unsigned char *p; @@ -6946,7 +7354,130 @@ ppc_elf_finish_dynamic_sections (bfd *ou #define elf_backend_begin_write_processing ppc_elf_begin_write_processing #define elf_backend_final_write_processing ppc_elf_final_write_processing #define elf_backend_write_section ppc_elf_write_section -#define elf_backend_special_sections ppc_elf_special_sections +#define elf_backend_get_sec_type_attr ppc_elf_get_sec_type_attr #define elf_backend_plt_sym_val ppc_elf_plt_sym_val #include "elf32-target.h" + +/* VxWorks Target */ + +#undef TARGET_LITTLE_SYM +#undef TARGET_LITTLE_NAME + +#undef TARGET_BIG_SYM +#define TARGET_BIG_SYM bfd_elf32_powerpc_vxworks_vec +#undef TARGET_BIG_NAME +#define TARGET_BIG_NAME "elf32-powerpc-vxworks" + +/* VxWorks uses the elf default section flags for .plt. */ +static const struct bfd_elf_special_section * +ppc_elf_vxworks_get_sec_type_attr (bfd *abfd ATTRIBUTE_UNUSED, asection *sec) +{ + if (sec->name == NULL) + return NULL; + + if (strcmp (sec->name, ".plt") == 0) + return _bfd_elf_get_sec_type_attr (abfd, sec); + + return ppc_elf_get_sec_type_attr (abfd, sec); +} + +/* Like ppc_elf_link_hash_table_create, but overrides + appropriately for VxWorks. */ +static struct bfd_link_hash_table * +ppc_elf_vxworks_link_hash_table_create (bfd *abfd) +{ + struct bfd_link_hash_table *ret; + + ret = ppc_elf_link_hash_table_create (abfd); + if (ret) + { + struct ppc_elf_link_hash_table *htab + = (struct ppc_elf_link_hash_table *)ret; + htab->is_vxworks = 1; + htab->plt_entry_size = VXWORKS_PLT_ENTRY_SIZE; + htab->plt_slot_size = VXWORKS_PLT_ENTRY_SIZE; + htab->plt_initial_entry_size = VXWORKS_PLT_INITIAL_ENTRY_SIZE; + } + return ret; +} + +/* Tweak magic VxWorks symbols as they are loaded. */ +static bfd_boolean +ppc_elf_vxworks_add_symbol_hook (bfd *abfd, + struct bfd_link_info *info, + Elf_Internal_Sym *sym, + const char **namep ATTRIBUTE_UNUSED, + flagword *flagsp ATTRIBUTE_UNUSED, + asection **secp, + bfd_vma *valp) +{ + if (!elf_vxworks_add_symbol_hook(abfd, info, sym,namep, flagsp, secp, + valp)) + return FALSE; + + return ppc_elf_add_symbol_hook(abfd, info, sym,namep, flagsp, secp, valp); +} + +/* Tweak magic VxWorks symbols as they are written to the output file. */ +static bfd_boolean +elf_i386_vxworks_link_output_symbol_hook (struct bfd_link_info *info + ATTRIBUTE_UNUSED, + const char *name, + Elf_Internal_Sym *sym, + asection *input_sec ATTRIBUTE_UNUSED, + struct elf_link_hash_entry *h + ATTRIBUTE_UNUSED) +{ + /* Ignore the first dummy symbol. */ + if (!name) + return TRUE; + + return elf_vxworks_link_output_symbol_hook (name, sym); +} + +static void +ppc_elf_vxworks_final_write_processing (bfd *abfd, bfd_boolean linker) +{ + ppc_elf_final_write_processing(abfd, linker); + elf_vxworks_final_write_processing(abfd, linker); +} + +/* On VxWorks, we emit relocations against _PROCEDURE_LINKAGE_TABLE_, so + define it. */ +#undef elf_backend_want_plt_sym +#define elf_backend_want_plt_sym 1 +#undef elf_backend_want_got_plt +#define elf_backend_want_got_plt 1 +#undef elf_backend_got_symbol_offset +#define elf_backend_got_symbol_offset 0 +#undef elf_backend_plt_not_loaded +#define elf_backend_plt_not_loaded 0 +#undef elf_backend_plt_readonly +#define elf_backend_plt_readonly 1 +#undef elf_backend_got_header_size +#define elf_backend_got_header_size 12 + +#undef bfd_elf32_bfd_link_hash_table_create +#define bfd_elf32_bfd_link_hash_table_create \ + ppc_elf_vxworks_link_hash_table_create +#undef elf_backend_add_symbol_hook +#define elf_backend_add_symbol_hook \ + ppc_elf_vxworks_add_symbol_hook +#undef elf_backend_link_output_symbol_hook +#define elf_backend_link_output_symbol_hook \ + elf_i386_vxworks_link_output_symbol_hook +#undef elf_backend_final_write_processing +#define elf_backend_final_write_processing \ + ppc_elf_vxworks_final_write_processing +#undef elf_backend_get_sec_type_attr +#define elf_backend_get_sec_type_attr \ + ppc_elf_vxworks_get_sec_type_attr +#undef elf_backend_emit_relocs +#define elf_backend_emit_relocs \ + elf_vxworks_emit_relocs + +#undef elf32_bed +#define elf32_bed ppc_elf_vxworks_bed + +#include "elf32-target.h" diff -uprN binutils-2.16.91.0.1/bfd/elf32-ppc.h binutils-2.16.91.0.2/bfd/elf32-ppc.h --- binutils-2.16.91.0.1/bfd/elf32-ppc.h 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-ppc.h 2005-07-20 12:27:27.262198154 -0700 @@ -20,4 +20,4 @@ Foundation, Inc., 51 Franklin Street - F int ppc_elf_select_plt_layout (bfd *, struct bfd_link_info *, int); asection *ppc_elf_tls_setup (bfd *, struct bfd_link_info *); bfd_boolean ppc_elf_tls_optimize (bfd *, struct bfd_link_info *); -bfd_boolean ppc_elf_set_sdata_syms (bfd *, struct bfd_link_info *); +void ppc_elf_set_sdata_syms (bfd *, struct bfd_link_info *); diff -uprN binutils-2.16.91.0.1/bfd/elf32-s390.c binutils-2.16.91.0.2/bfd/elf32-s390.c --- binutils-2.16.91.0.1/bfd/elf32-s390.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-s390.c 2005-07-20 12:27:27.265197659 -0700 @@ -351,7 +351,8 @@ elf_s390_info_to_howto (abfd, cache_ptr, arelent *cache_ptr; Elf_Internal_Rela *dst; { - switch (ELF32_R_TYPE(dst->r_info)) + unsigned int r_type = ELF32_R_TYPE(dst->r_info); + switch (r_type) { case R_390_GNU_VTINHERIT: cache_ptr->howto = &elf32_s390_vtinherit_howto; @@ -362,8 +363,13 @@ elf_s390_info_to_howto (abfd, cache_ptr, break; default: - BFD_ASSERT (ELF32_R_TYPE(dst->r_info) < (unsigned int) R_390_max); - cache_ptr->howto = &elf_howto_table[ELF32_R_TYPE(dst->r_info)]; + if (r_type >= sizeof (elf_howto_table) / sizeof (elf_howto_table[0])) + { + (*_bfd_error_handler) (_("%B: invalid relocation type %d"), + abfd, (int) r_type); + r_type = R_390_NONE; + } + cache_ptr->howto = &elf_howto_table[r_type]; } } @@ -2099,7 +2105,8 @@ elf_s390_size_dynamic_sections (output_b if (s == htab->splt || s == htab->sgot - || s == htab->sgotplt) + || s == htab->sgotplt + || s == htab->sdynbss) { /* Strip this section if we don't need it; see the comment below. */ @@ -2135,6 +2142,9 @@ elf_s390_size_dynamic_sections (output_b continue; } + if ((s->flags & SEC_HAS_CONTENTS) == 0) + continue; + /* Allocate memory for the section contents. We use bfd_zalloc here in case unused entries are not reclaimed before the section's contents are written out. This should not happen, diff -uprN binutils-2.16.91.0.1/bfd/elf32-sh64.c binutils-2.16.91.0.2/bfd/elf32-sh64.c --- binutils-2.16.91.0.1/bfd/elf32-sh64.c 2005-05-10 15:46:42.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-sh64.c 2005-07-20 12:27:27.282194857 -0700 @@ -754,43 +754,10 @@ sh64_elf_merge_symbol_attribute (struct return; } -static struct bfd_elf_special_section const - sh64_special_sections_c[] = +static const struct bfd_elf_special_section sh64_elf_special_sections[] = { { ".cranges", 8, 0, SHT_PROGBITS, 0 }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const * - sh64_elf_special_sections[27]= -{ - NULL, /* 'a' */ - NULL, /* 'b' */ - sh64_special_sections_c, /* 'c' */ - NULL, /* 'd' */ - NULL, /* 'e' */ - NULL, /* 'f' */ - NULL, /* 'g' */ - NULL, /* 'h' */ - NULL, /* 'i' */ - NULL, /* 'j' */ - NULL, /* 'k' */ - NULL, /* 'l' */ - NULL, /* 'm' */ - NULL, /* 'n' */ - NULL, /* 'o' */ - NULL, /* 'p' */ - NULL, /* 'q' */ - NULL, /* 'r' */ - NULL, /* 's' */ - NULL, /* 't' */ - NULL, /* 'u' */ - NULL, /* 'v' */ - NULL, /* 'w' */ - NULL, /* 'x' */ - NULL, /* 'y' */ - NULL, /* 'z' */ - NULL /* other */ + { NULL, 0, 0, 0, 0 } }; #undef TARGET_BIG_SYM diff -uprN binutils-2.16.91.0.1/bfd/elf32-sh.c binutils-2.16.91.0.2/bfd/elf32-sh.c --- binutils-2.16.91.0.1/bfd/elf32-sh.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-sh.c 2005-07-20 12:27:27.273196340 -0700 @@ -4354,7 +4354,8 @@ sh_elf_size_dynamic_sections (bfd *outpu if (s == htab->splt || s == htab->sgot - || s == htab->sgotplt) + || s == htab->sgotplt + || s == htab->sdynbss) { /* Strip this section if we don't need it; see the comment below. */ @@ -4390,6 +4391,9 @@ sh_elf_size_dynamic_sections (bfd *outpu continue; } + if ((s->flags & SEC_HAS_CONTENTS) == 0) + continue; + /* Allocate memory for the section contents. We use bfd_zalloc here in case unused entries are not reclaimed before the section's contents are written out. This should not happen, diff -uprN binutils-2.16.91.0.1/bfd/elf32-v850.c binutils-2.16.91.0.2/bfd/elf32-v850.c --- binutils-2.16.91.0.1/bfd/elf32-v850.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-v850.c 2005-07-20 12:27:27.288193867 -0700 @@ -16,7 +16,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ /* XXX FIXME: This code is littered with 32bit int, 16bit short, 8bit char dependencies. As is the gas & simulator code for the v850. */ @@ -32,628 +33,15 @@ /* Sign-extend a 24-bit number. */ #define SEXT24(x) ((((x) & 0xffffff) ^ 0x800000) - 0x800000) -static reloc_howto_type *v850_elf_reloc_type_lookup - PARAMS ((bfd *abfd, bfd_reloc_code_real_type code)); -static void v850_elf_info_to_howto_rel - PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); -static void v850_elf_info_to_howto_rela - PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); -static bfd_reloc_status_type v850_elf_reloc - PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); -static bfd_boolean v850_elf_is_local_label_name - PARAMS ((bfd *, const char *)); -static bfd_boolean v850_elf_relocate_section - PARAMS((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, - Elf_Internal_Rela *, Elf_Internal_Sym *, asection **)); -static bfd_reloc_status_type v850_elf_perform_relocation - PARAMS ((bfd *, unsigned int, bfd_vma, bfd_byte *)); -static bfd_boolean v850_elf_check_relocs - PARAMS ((bfd *, struct bfd_link_info *, asection *, const Elf_Internal_Rela *)); -static void remember_hi16s_reloc - PARAMS ((bfd *, bfd_vma, bfd_byte *)); -static bfd_byte * find_remembered_hi16s_reloc - PARAMS ((bfd_vma, bfd_boolean *)); -static bfd_reloc_status_type v850_elf_final_link_relocate - PARAMS ((reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *, bfd_vma, - bfd_vma, bfd_vma, struct bfd_link_info *, asection *, int)); -static bfd_boolean v850_elf_object_p - PARAMS ((bfd *)); -static bfd_boolean v850_elf_fake_sections - PARAMS ((bfd *, Elf_Internal_Shdr *, asection *)); -static void v850_elf_final_write_processing - PARAMS ((bfd *, bfd_boolean)); -static bfd_boolean v850_elf_set_private_flags - PARAMS ((bfd *, flagword)); -static bfd_boolean v850_elf_merge_private_bfd_data - PARAMS ((bfd *, bfd *)); -static bfd_boolean v850_elf_print_private_bfd_data - PARAMS ((bfd *, PTR)); -static bfd_boolean v850_elf_section_from_bfd_section - PARAMS ((bfd *, asection *, int *)); -static void v850_elf_symbol_processing - PARAMS ((bfd *, asymbol *)); -static bfd_boolean v850_elf_add_symbol_hook - PARAMS ((bfd *, struct bfd_link_info *, Elf_Internal_Sym *, - const char **, flagword *, asection **, bfd_vma *)); -static bfd_boolean v850_elf_link_output_symbol_hook - PARAMS ((struct bfd_link_info *, const char *, Elf_Internal_Sym *, - asection *, struct elf_link_hash_entry *)); -static bfd_boolean v850_elf_gc_sweep_hook - PARAMS ((bfd *, struct bfd_link_info *, asection *, - const Elf_Internal_Rela *)); -static asection * v850_elf_gc_mark_hook - PARAMS ((asection *, struct bfd_link_info *, - Elf_Internal_Rela *, struct elf_link_hash_entry *, - Elf_Internal_Sym *)); -static bfd_reloc_status_type v850_elf_ignore_reloc - PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)); -static bfd_boolean v850_elf_relax_delete_bytes - PARAMS ((bfd *, asection *, bfd_vma, bfd_vma, int)); -static bfd_boolean v850_elf_relax_section - PARAMS ((bfd *, asection *, struct bfd_link_info *, bfd_boolean *)); - -/* Note: It is REQUIRED that the 'type' value of each entry - in this array match the index of the entry in the array. */ -static reloc_howto_type v850_elf_howto_table[] = -{ - /* This reloc does nothing. */ - HOWTO (R_V850_NONE, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_V850_NONE", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* A PC relative 9 bit branch. */ - HOWTO (R_V850_9_PCREL, /* type */ - 2, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 26, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_bitfield, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_9_PCREL", /* name */ - FALSE, /* partial_inplace */ - 0x00ffffff, /* src_mask */ - 0x00ffffff, /* dst_mask */ - TRUE), /* pcrel_offset */ - - /* A PC relative 22 bit branch. */ - HOWTO (R_V850_22_PCREL, /* type */ - 2, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 22, /* bitsize */ - TRUE, /* pc_relative */ - 7, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_22_PCREL", /* name */ - FALSE, /* partial_inplace */ - 0x07ffff80, /* src_mask */ - 0x07ffff80, /* dst_mask */ - TRUE), /* pcrel_offset */ - - /* High 16 bits of symbol value. */ - HOWTO (R_V850_HI16_S, /* type */ - 0, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_HI16_S", /* name */ - FALSE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* High 16 bits of symbol value. */ - HOWTO (R_V850_HI16, /* type */ - 0, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_HI16", /* name */ - FALSE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* Low 16 bits of symbol value. */ - HOWTO (R_V850_LO16, /* type */ - 0, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_LO16", /* name */ - FALSE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* Simple 32bit reloc. */ - HOWTO (R_V850_ABS32, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_ABS32", /* name */ - FALSE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* Simple 16bit reloc. */ - HOWTO (R_V850_16, /* type */ - 0, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_V850_16", /* name */ - FALSE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* Simple 8bit reloc. */ - HOWTO (R_V850_8, /* type */ - 0, /* rightshift */ - 0, /* size (0 = byte, 1 = short, 2 = long) */ - 8, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - bfd_elf_generic_reloc, /* special_function */ - "R_V850_8", /* name */ - FALSE, /* partial_inplace */ - 0xff, /* src_mask */ - 0xff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* 16 bit offset from the short data area pointer. */ - HOWTO (R_V850_SDA_16_16_OFFSET, /* type */ - 0, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_SDA_16_16_OFFSET", /* name */ - FALSE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* 15 bit offset from the short data area pointer. */ - HOWTO (R_V850_SDA_15_16_OFFSET, /* type */ - 1, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 1, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_SDA_15_16_OFFSET", /* name */ - FALSE, /* partial_inplace */ - 0xfffe, /* src_mask */ - 0xfffe, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* 16 bit offset from the zero data area pointer. */ - HOWTO (R_V850_ZDA_16_16_OFFSET, /* type */ - 0, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_ZDA_16_16_OFFSET", /* name */ - FALSE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* 15 bit offset from the zero data area pointer. */ - HOWTO (R_V850_ZDA_15_16_OFFSET, /* type */ - 1, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 1, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_ZDA_15_16_OFFSET", /* name */ - FALSE, /* partial_inplace */ - 0xfffe, /* src_mask */ - 0xfffe, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* 6 bit offset from the tiny data area pointer. */ - HOWTO (R_V850_TDA_6_8_OFFSET, /* type */ - 2, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 8, /* bitsize */ - FALSE, /* pc_relative */ - 1, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_TDA_6_8_OFFSET", /* name */ - FALSE, /* partial_inplace */ - 0x7e, /* src_mask */ - 0x7e, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* 8 bit offset from the tiny data area pointer. */ - HOWTO (R_V850_TDA_7_8_OFFSET, /* type */ - 1, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 8, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_TDA_7_8_OFFSET", /* name */ - FALSE, /* partial_inplace */ - 0x7f, /* src_mask */ - 0x7f, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* 7 bit offset from the tiny data area pointer. */ - HOWTO (R_V850_TDA_7_7_OFFSET, /* type */ - 0, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 7, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_TDA_7_7_OFFSET", /* name */ - FALSE, /* partial_inplace */ - 0x7f, /* src_mask */ - 0x7f, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* 16 bit offset from the tiny data area pointer! */ - HOWTO (R_V850_TDA_16_16_OFFSET, /* type */ - 0, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_TDA_16_16_OFFSET", /* name */ - FALSE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xfff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* 5 bit offset from the tiny data area pointer. */ - HOWTO (R_V850_TDA_4_5_OFFSET, /* type */ - 1, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 5, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_TDA_4_5_OFFSET", /* name */ - FALSE, /* partial_inplace */ - 0x0f, /* src_mask */ - 0x0f, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* 4 bit offset from the tiny data area pointer. */ - HOWTO (R_V850_TDA_4_4_OFFSET, /* type */ - 0, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 4, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_TDA_4_4_OFFSET", /* name */ - FALSE, /* partial_inplace */ - 0x0f, /* src_mask */ - 0x0f, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* 16 bit offset from the short data area pointer. */ - HOWTO (R_V850_SDA_16_16_SPLIT_OFFSET, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_SDA_16_16_SPLIT_OFFSET",/* name */ - FALSE, /* partial_inplace */ - 0xfffe0020, /* src_mask */ - 0xfffe0020, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* 16 bit offset from the zero data area pointer. */ - HOWTO (R_V850_ZDA_16_16_SPLIT_OFFSET, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_ZDA_16_16_SPLIT_OFFSET",/* name */ - FALSE, /* partial_inplace */ - 0xfffe0020, /* src_mask */ - 0xfffe0020, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* 6 bit offset from the call table base pointer. */ - HOWTO (R_V850_CALLT_6_7_OFFSET, /* type */ - 0, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 7, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_CALLT_6_7_OFFSET", /* name */ - FALSE, /* partial_inplace */ - 0x3f, /* src_mask */ - 0x3f, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* 16 bit offset from the call table base pointer. */ - HOWTO (R_V850_CALLT_16_16_OFFSET, /* type */ - 0, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_CALLT_16_16_OFFSET", /* name */ - FALSE, /* partial_inplace */ - 0xffff, /* src_mask */ - 0xffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* GNU extension to record C++ vtable hierarchy */ - HOWTO (R_V850_GNU_VTINHERIT, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 0, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - NULL, /* special_function */ - "R_V850_GNU_VTINHERIT", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* GNU extension to record C++ vtable member usage */ - HOWTO (R_V850_GNU_VTENTRY, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 0, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - _bfd_elf_rel_vtable_reloc_fn, /* special_function */ - "R_V850_GNU_VTENTRY", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* Indicates a .longcall pseudo-op. The compiler will generate a .longcall - pseudo-op when it finds a function call which can be relaxed. */ - HOWTO (R_V850_LONGCALL, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - v850_elf_ignore_reloc, /* special_function */ - "R_V850_LONGCALL", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - TRUE), /* pcrel_offset */ - - /* Indicates a .longjump pseudo-op. The compiler will generate a - .longjump pseudo-op when it finds a branch which can be relaxed. */ - HOWTO (R_V850_LONGJUMP, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_signed, /* complain_on_overflow */ - v850_elf_ignore_reloc, /* special_function */ - "R_V850_LONGJUMP", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - TRUE), /* pcrel_offset */ - - HOWTO (R_V850_ALIGN, /* type */ - 0, /* rightshift */ - 1, /* size (0 = byte, 1 = short, 2 = long) */ - 0, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_unsigned, /* complain_on_overflow */ - v850_elf_ignore_reloc, /* special_function */ - "R_V850_ALIGN", /* name */ - FALSE, /* partial_inplace */ - 0, /* src_mask */ - 0, /* dst_mask */ - TRUE), /* pcrel_offset */ - - /* Simple pc-relative 32bit reloc. */ - HOWTO (R_V850_REL32, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 32, /* bitsize */ - TRUE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_REL32", /* name */ - FALSE, /* partial_inplace */ - 0xffffffff, /* src_mask */ - 0xffffffff, /* dst_mask */ - FALSE), /* pcrel_offset */ - - /* An ld.bu version of R_V850_LO16. */ - HOWTO (R_V850_LO16_SPLIT_OFFSET, /* type */ - 0, /* rightshift */ - 2, /* size (0 = byte, 1 = short, 2 = long) */ - 16, /* bitsize */ - FALSE, /* pc_relative */ - 0, /* bitpos */ - complain_overflow_dont, /* complain_on_overflow */ - v850_elf_reloc, /* special_function */ - "R_V850_LO16_SPLIT_OFFSET", /* name */ - FALSE, /* partial_inplace */ - 0xfffe0020, /* src_mask */ - 0xfffe0020, /* dst_mask */ - FALSE), /* pcrel_offset */ -}; - -/* Map BFD reloc types to V850 ELF reloc types. */ - -struct v850_elf_reloc_map -{ - /* BFD_RELOC_V850_CALLT_16_16_OFFSET is 258, which will not fix in an - unsigned char. */ - bfd_reloc_code_real_type bfd_reloc_val; - unsigned int elf_reloc_val; -}; - -static const struct v850_elf_reloc_map v850_elf_reloc_map[] = -{ - { BFD_RELOC_NONE, R_V850_NONE }, - { BFD_RELOC_V850_9_PCREL, R_V850_9_PCREL }, - { BFD_RELOC_V850_22_PCREL, R_V850_22_PCREL }, - { BFD_RELOC_HI16_S, R_V850_HI16_S }, - { BFD_RELOC_HI16, R_V850_HI16 }, - { BFD_RELOC_LO16, R_V850_LO16 }, - { BFD_RELOC_32, R_V850_ABS32 }, - { BFD_RELOC_32_PCREL, R_V850_REL32 }, - { BFD_RELOC_16, R_V850_16 }, - { BFD_RELOC_8, R_V850_8 }, - { BFD_RELOC_V850_SDA_16_16_OFFSET, R_V850_SDA_16_16_OFFSET }, - { BFD_RELOC_V850_SDA_15_16_OFFSET, R_V850_SDA_15_16_OFFSET }, - { BFD_RELOC_V850_ZDA_16_16_OFFSET, R_V850_ZDA_16_16_OFFSET }, - { BFD_RELOC_V850_ZDA_15_16_OFFSET, R_V850_ZDA_15_16_OFFSET }, - { BFD_RELOC_V850_TDA_6_8_OFFSET, R_V850_TDA_6_8_OFFSET }, - { BFD_RELOC_V850_TDA_7_8_OFFSET, R_V850_TDA_7_8_OFFSET }, - { BFD_RELOC_V850_TDA_7_7_OFFSET, R_V850_TDA_7_7_OFFSET }, - { BFD_RELOC_V850_TDA_16_16_OFFSET, R_V850_TDA_16_16_OFFSET }, - { BFD_RELOC_V850_TDA_4_5_OFFSET, R_V850_TDA_4_5_OFFSET }, - { BFD_RELOC_V850_TDA_4_4_OFFSET, R_V850_TDA_4_4_OFFSET }, - { BFD_RELOC_V850_LO16_SPLIT_OFFSET, R_V850_LO16_SPLIT_OFFSET }, - { BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET, R_V850_SDA_16_16_SPLIT_OFFSET }, - { BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET, R_V850_ZDA_16_16_SPLIT_OFFSET }, - { BFD_RELOC_V850_CALLT_6_7_OFFSET, R_V850_CALLT_6_7_OFFSET }, - { BFD_RELOC_V850_CALLT_16_16_OFFSET, R_V850_CALLT_16_16_OFFSET }, - { BFD_RELOC_VTABLE_INHERIT, R_V850_GNU_VTINHERIT }, - { BFD_RELOC_VTABLE_ENTRY, R_V850_GNU_VTENTRY }, - { BFD_RELOC_V850_LONGCALL, R_V850_LONGCALL }, - { BFD_RELOC_V850_LONGJUMP, R_V850_LONGJUMP }, - { BFD_RELOC_V850_ALIGN, R_V850_ALIGN }, - -}; - -/* Map a bfd relocation into the appropriate howto structure. */ - -static reloc_howto_type * -v850_elf_reloc_type_lookup (abfd, code) - bfd *abfd ATTRIBUTE_UNUSED; - bfd_reloc_code_real_type code; -{ - unsigned int i; - - for (i = ARRAY_SIZE (v850_elf_reloc_map); i --;) - if (v850_elf_reloc_map[i].bfd_reloc_val == code) - { - unsigned int elf_reloc_val = v850_elf_reloc_map[i].elf_reloc_val; - - BFD_ASSERT (v850_elf_howto_table[elf_reloc_val].type == elf_reloc_val); - - return v850_elf_howto_table + elf_reloc_val; - } - - return NULL; -} - -/* Set the howto pointer for an V850 ELF reloc. */ - -static void -v850_elf_info_to_howto_rel (abfd, cache_ptr, dst) - bfd *abfd ATTRIBUTE_UNUSED; - arelent *cache_ptr; - Elf_Internal_Rela *dst; -{ - unsigned int r_type; - - r_type = ELF32_R_TYPE (dst->r_info); - BFD_ASSERT (r_type < (unsigned int) R_V850_max); - cache_ptr->howto = &v850_elf_howto_table[r_type]; -} - -/* Set the howto pointer for a V850 ELF reloc (type RELA). */ -static void -v850_elf_info_to_howto_rela (abfd, cache_ptr, dst) - bfd *abfd ATTRIBUTE_UNUSED; - arelent * cache_ptr; - Elf_Internal_Rela *dst; -{ - unsigned int r_type; - - r_type = ELF32_R_TYPE (dst->r_info); - BFD_ASSERT (r_type < (unsigned int) R_V850_max); - cache_ptr->howto = &v850_elf_howto_table[r_type]; -} - /* Look through the relocs for a section during the first phase, and allocate space in the global offset table or procedure linkage table. */ static bfd_boolean -v850_elf_check_relocs (abfd, info, sec, relocs) - bfd *abfd; - struct bfd_link_info *info; - asection *sec; - const Elf_Internal_Rela *relocs; +v850_elf_check_relocs (bfd *abfd, + struct bfd_link_info *info, + asection *sec, + const Elf_Internal_Rela *relocs) { bfd_boolean ret = TRUE; bfd *dynobj; @@ -664,7 +52,7 @@ v850_elf_check_relocs (abfd, info, sec, asection *sreloc; enum v850_reloc_type r_type; int other = 0; - const char *common = (const char *)0; + const char *common = NULL; if (info->relocatable) return TRUE; @@ -834,30 +222,27 @@ v850_elf_check_relocs (abfd, info, sec, typedef struct hi16s_location { - bfd_vma addend; - bfd_byte *address; - unsigned long counter; - bfd_boolean found; - struct hi16s_location *next; + bfd_vma addend; + bfd_byte * address; + unsigned long counter; + bfd_boolean found; + struct hi16s_location * next; } hi16s_location; -static hi16s_location *previous_hi16s; -static hi16s_location *free_hi16s; -static unsigned long hi16s_counter; +static hi16s_location * previous_hi16s; +static hi16s_location * free_hi16s; +static unsigned long hi16s_counter; static void -remember_hi16s_reloc (abfd, addend, address) - bfd *abfd; - bfd_vma addend; - bfd_byte *address; +remember_hi16s_reloc (bfd *abfd, bfd_vma addend, bfd_byte *address) { hi16s_location * entry = NULL; bfd_size_type amt = sizeof (* free_hi16s); /* Find a free structure. */ if (free_hi16s == NULL) - free_hi16s = (hi16s_location *) bfd_zalloc (abfd, amt); + free_hi16s = bfd_zalloc (abfd, amt); entry = free_hi16s; free_hi16s = free_hi16s->next; @@ -872,20 +257,16 @@ remember_hi16s_reloc (abfd, addend, addr /* Cope with wrap around of our counter. */ if (hi16s_counter == 0) { - /* XXX - Assume that all counter entries differ only in their low 16 bits. */ + /* XXX: Assume that all counter entries differ only in their low 16 bits. */ for (entry = previous_hi16s; entry != NULL; entry = entry->next) entry->counter &= 0xffff; hi16s_counter = 0x10000; } - - return; } static bfd_byte * -find_remembered_hi16s_reloc (addend, already_found) - bfd_vma addend; - bfd_boolean *already_found; +find_remembered_hi16s_reloc (bfd_vma addend, bfd_boolean *already_found) { hi16s_location *match = NULL; hi16s_location *entry; @@ -1070,6 +451,7 @@ v850_elf_perform_lo16_relocation (bfd *a { #define BIT15_SET(x) ((x) & 0x8000) #define OVERFLOWS(a,i) ((((a) & 0xffff) + (i)) > 0xffff) + if ((BIT15_SET (*insn + addend) && ! BIT15_SET (addend)) || (OVERFLOWS (addend, *insn) && ((! BIT15_SET (*insn)) || (BIT15_SET (addend))))) @@ -1107,11 +489,10 @@ v850_elf_perform_lo16_relocation (bfd *a allowed to do its stuff instead. At least for most of the relocs, anyway. */ static bfd_reloc_status_type -v850_elf_perform_relocation (abfd, r_type, addend, address) - bfd *abfd; - unsigned int r_type; - bfd_vma addend; - bfd_byte *address; +v850_elf_perform_relocation (bfd *abfd, + unsigned int r_type, + bfd_vma addend, + bfd_byte *address) { unsigned long insn; unsigned long result; @@ -1120,7 +501,6 @@ v850_elf_perform_relocation (abfd, r_typ switch (r_type) { default: - /* fprintf (stderr, "reloc type %d not SUPPORTED\n", r_type ); */ return bfd_reloc_notsupported; case R_V850_REL32: @@ -1202,8 +582,6 @@ v850_elf_perform_relocation (abfd, r_typ break; case R_V850_16: - - /* drop through */ case R_V850_SDA_16_16_OFFSET: case R_V850_ZDA_16_16_OFFSET: case R_V850_TDA_16_16_OFFSET: @@ -1364,14 +742,13 @@ v850_elf_perform_relocation (abfd, r_typ /* Insert the addend into the instruction. */ static bfd_reloc_status_type -v850_elf_reloc (abfd, reloc, symbol, data, isection, obfd, err) - bfd *abfd ATTRIBUTE_UNUSED; - arelent *reloc; - asymbol *symbol; - PTR data ATTRIBUTE_UNUSED; - asection *isection; - bfd *obfd; - char **err ATTRIBUTE_UNUSED; +v850_elf_reloc (bfd *abfd ATTRIBUTE_UNUSED, + arelent *reloc, + asymbol *symbol, + void * data ATTRIBUTE_UNUSED, + asection *isection, + bfd *obfd, + char **err ATTRIBUTE_UNUSED) { long relocation; @@ -1380,7 +757,7 @@ v850_elf_reloc (abfd, reloc, symbol, dat and either we are not putting the addend into the instruction or the addend is zero, so there is nothing to add into the instruction then just fixup the address and return. */ - if (obfd != (bfd *) NULL + if (obfd != NULL && (symbol->flags & BSF_SECTION_SYM) == 0 && (! reloc->howto->partial_inplace || reloc->addend == 0)) @@ -1426,26 +803,571 @@ v850_elf_reloc (abfd, reloc, symbol, dat for relaxing, which the linker should otherwise ignore. */ static bfd_reloc_status_type -v850_elf_ignore_reloc (abfd, reloc_entry, symbol, data, input_section, - output_bfd, error_message) - bfd *abfd ATTRIBUTE_UNUSED; - arelent *reloc_entry; - asymbol *symbol ATTRIBUTE_UNUSED; - PTR data ATTRIBUTE_UNUSED; - asection *input_section; - bfd *output_bfd; - char **error_message ATTRIBUTE_UNUSED; +v850_elf_ignore_reloc (bfd *abfd ATTRIBUTE_UNUSED, + arelent *reloc_entry, + asymbol *symbol ATTRIBUTE_UNUSED, + void * data ATTRIBUTE_UNUSED, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) { if (output_bfd != NULL) reloc_entry->address += input_section->output_offset; return bfd_reloc_ok; } +/* Note: It is REQUIRED that the 'type' value of each entry + in this array match the index of the entry in the array. */ +static reloc_howto_type v850_elf_howto_table[] = +{ + /* This reloc does nothing. */ + HOWTO (R_V850_NONE, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 32, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_bitfield, /* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_V850_NONE", /* Name. */ + FALSE, /* Partial_inplace. */ + 0, /* Src_mask. */ + 0, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* A PC relative 9 bit branch. */ + HOWTO (R_V850_9_PCREL, /* Type. */ + 2, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 26, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_bitfield, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_9_PCREL", /* Name. */ + FALSE, /* Partial_inplace. */ + 0x00ffffff, /* Src_mask. */ + 0x00ffffff, /* Dst_mask. */ + TRUE), /* PCrel_offset. */ + + /* A PC relative 22 bit branch. */ + HOWTO (R_V850_22_PCREL, /* Type. */ + 2, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 22, /* Bitsize. */ + TRUE, /* PC_relative. */ + 7, /* Bitpos. */ + complain_overflow_signed, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_22_PCREL", /* Name. */ + FALSE, /* Partial_inplace. */ + 0x07ffff80, /* Src_mask. */ + 0x07ffff80, /* Dst_mask. */ + TRUE), /* PCrel_offset. */ + + /* High 16 bits of symbol value. */ + HOWTO (R_V850_HI16_S, /* Type. */ + 0, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_HI16_S", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xffff, /* Src_mask. */ + 0xffff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* High 16 bits of symbol value. */ + HOWTO (R_V850_HI16, /* Type. */ + 0, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_HI16", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xffff, /* Src_mask. */ + 0xffff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* Low 16 bits of symbol value. */ + HOWTO (R_V850_LO16, /* Type. */ + 0, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_LO16", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xffff, /* Src_mask. */ + 0xffff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* Simple 32bit reloc. */ + HOWTO (R_V850_ABS32, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 32, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_ABS32", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xffffffff, /* Src_mask. */ + 0xffffffff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* Simple 16bit reloc. */ + HOWTO (R_V850_16, /* Type. */ + 0, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_V850_16", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xffff, /* Src_mask. */ + 0xffff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* Simple 8bit reloc. */ + HOWTO (R_V850_8, /* Type. */ + 0, /* Rightshift. */ + 0, /* Size (0 = byte, 1 = short, 2 = long). */ + 8, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + bfd_elf_generic_reloc, /* Special_function. */ + "R_V850_8", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xff, /* Src_mask. */ + 0xff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* 16 bit offset from the short data area pointer. */ + HOWTO (R_V850_SDA_16_16_OFFSET, /* Type. */ + 0, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_SDA_16_16_OFFSET", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xffff, /* Src_mask. */ + 0xffff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* 15 bit offset from the short data area pointer. */ + HOWTO (R_V850_SDA_15_16_OFFSET, /* Type. */ + 1, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 1, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_SDA_15_16_OFFSET", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xfffe, /* Src_mask. */ + 0xfffe, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* 16 bit offset from the zero data area pointer. */ + HOWTO (R_V850_ZDA_16_16_OFFSET, /* Type. */ + 0, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_ZDA_16_16_OFFSET", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xffff, /* Src_mask. */ + 0xffff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* 15 bit offset from the zero data area pointer. */ + HOWTO (R_V850_ZDA_15_16_OFFSET, /* Type. */ + 1, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 1, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_ZDA_15_16_OFFSET", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xfffe, /* Src_mask. */ + 0xfffe, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* 6 bit offset from the tiny data area pointer. */ + HOWTO (R_V850_TDA_6_8_OFFSET, /* Type. */ + 2, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 8, /* Bitsize. */ + FALSE, /* PC_relative. */ + 1, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_TDA_6_8_OFFSET", /* Name. */ + FALSE, /* Partial_inplace. */ + 0x7e, /* Src_mask. */ + 0x7e, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* 8 bit offset from the tiny data area pointer. */ + HOWTO (R_V850_TDA_7_8_OFFSET, /* Type. */ + 1, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 8, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_TDA_7_8_OFFSET", /* Name. */ + FALSE, /* Partial_inplace. */ + 0x7f, /* Src_mask. */ + 0x7f, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* 7 bit offset from the tiny data area pointer. */ + HOWTO (R_V850_TDA_7_7_OFFSET, /* Type. */ + 0, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 7, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_TDA_7_7_OFFSET", /* Name. */ + FALSE, /* Partial_inplace. */ + 0x7f, /* Src_mask. */ + 0x7f, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* 16 bit offset from the tiny data area pointer! */ + HOWTO (R_V850_TDA_16_16_OFFSET, /* Type. */ + 0, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_TDA_16_16_OFFSET", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xffff, /* Src_mask. */ + 0xfff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* 5 bit offset from the tiny data area pointer. */ + HOWTO (R_V850_TDA_4_5_OFFSET, /* Type. */ + 1, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 5, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_TDA_4_5_OFFSET", /* Name. */ + FALSE, /* Partial_inplace. */ + 0x0f, /* Src_mask. */ + 0x0f, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* 4 bit offset from the tiny data area pointer. */ + HOWTO (R_V850_TDA_4_4_OFFSET, /* Type. */ + 0, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 4, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_TDA_4_4_OFFSET", /* Name. */ + FALSE, /* Partial_inplace. */ + 0x0f, /* Src_mask. */ + 0x0f, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* 16 bit offset from the short data area pointer. */ + HOWTO (R_V850_SDA_16_16_SPLIT_OFFSET, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_SDA_16_16_SPLIT_OFFSET",/* Name. */ + FALSE, /* Partial_inplace. */ + 0xfffe0020, /* Src_mask. */ + 0xfffe0020, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* 16 bit offset from the zero data area pointer. */ + HOWTO (R_V850_ZDA_16_16_SPLIT_OFFSET, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_ZDA_16_16_SPLIT_OFFSET",/* Name. */ + FALSE, /* Partial_inplace. */ + 0xfffe0020, /* Src_mask. */ + 0xfffe0020, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* 6 bit offset from the call table base pointer. */ + HOWTO (R_V850_CALLT_6_7_OFFSET, /* Type. */ + 0, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 7, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_CALLT_6_7_OFFSET", /* Name. */ + FALSE, /* Partial_inplace. */ + 0x3f, /* Src_mask. */ + 0x3f, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* 16 bit offset from the call table base pointer. */ + HOWTO (R_V850_CALLT_16_16_OFFSET, /* Type. */ + 0, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_CALLT_16_16_OFFSET", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xffff, /* Src_mask. */ + 0xffff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* GNU extension to record C++ vtable hierarchy */ + HOWTO (R_V850_GNU_VTINHERIT, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 0, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + NULL, /* Special_function. */ + "R_V850_GNU_VTINHERIT", /* Name. */ + FALSE, /* Partial_inplace. */ + 0, /* Src_mask. */ + 0, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* GNU extension to record C++ vtable member usage */ + HOWTO (R_V850_GNU_VTENTRY, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 0, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + _bfd_elf_rel_vtable_reloc_fn, /* Special_function. */ + "R_V850_GNU_VTENTRY", /* Name. */ + FALSE, /* Partial_inplace. */ + 0, /* Src_mask. */ + 0, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* Indicates a .longcall pseudo-op. The compiler will generate a .longcall + pseudo-op when it finds a function call which can be relaxed. */ + HOWTO (R_V850_LONGCALL, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 32, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_signed, /* Complain_on_overflow. */ + v850_elf_ignore_reloc, /* Special_function. */ + "R_V850_LONGCALL", /* Name. */ + FALSE, /* Partial_inplace. */ + 0, /* Src_mask. */ + 0, /* Dst_mask. */ + TRUE), /* PCrel_offset. */ + + /* Indicates a .longjump pseudo-op. The compiler will generate a + .longjump pseudo-op when it finds a branch which can be relaxed. */ + HOWTO (R_V850_LONGJUMP, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 32, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_signed, /* Complain_on_overflow. */ + v850_elf_ignore_reloc, /* Special_function. */ + "R_V850_LONGJUMP", /* Name. */ + FALSE, /* Partial_inplace. */ + 0, /* Src_mask. */ + 0, /* Dst_mask. */ + TRUE), /* PCrel_offset. */ + + HOWTO (R_V850_ALIGN, /* Type. */ + 0, /* Rightshift. */ + 1, /* Size (0 = byte, 1 = short, 2 = long). */ + 0, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_unsigned, /* Complain_on_overflow. */ + v850_elf_ignore_reloc, /* Special_function. */ + "R_V850_ALIGN", /* Name. */ + FALSE, /* Partial_inplace. */ + 0, /* Src_mask. */ + 0, /* Dst_mask. */ + TRUE), /* PCrel_offset. */ + + /* Simple pc-relative 32bit reloc. */ + HOWTO (R_V850_REL32, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 32, /* Bitsize. */ + TRUE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_REL32", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xffffffff, /* Src_mask. */ + 0xffffffff, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ + + /* An ld.bu version of R_V850_LO16. */ + HOWTO (R_V850_LO16_SPLIT_OFFSET, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ + 16, /* Bitsize. */ + FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain_on_overflow. */ + v850_elf_reloc, /* Special_function. */ + "R_V850_LO16_SPLIT_OFFSET", /* Name. */ + FALSE, /* Partial_inplace. */ + 0xfffe0020, /* Src_mask. */ + 0xfffe0020, /* Dst_mask. */ + FALSE), /* PCrel_offset. */ +}; + +/* Map BFD reloc types to V850 ELF reloc types. */ + +struct v850_elf_reloc_map +{ + /* BFD_RELOC_V850_CALLT_16_16_OFFSET is 258, which will not fix in an + unsigned char. */ + bfd_reloc_code_real_type bfd_reloc_val; + unsigned int elf_reloc_val; +}; + +static const struct v850_elf_reloc_map v850_elf_reloc_map[] = +{ + { BFD_RELOC_NONE, R_V850_NONE }, + { BFD_RELOC_V850_9_PCREL, R_V850_9_PCREL }, + { BFD_RELOC_V850_22_PCREL, R_V850_22_PCREL }, + { BFD_RELOC_HI16_S, R_V850_HI16_S }, + { BFD_RELOC_HI16, R_V850_HI16 }, + { BFD_RELOC_LO16, R_V850_LO16 }, + { BFD_RELOC_32, R_V850_ABS32 }, + { BFD_RELOC_32_PCREL, R_V850_REL32 }, + { BFD_RELOC_16, R_V850_16 }, + { BFD_RELOC_8, R_V850_8 }, + { BFD_RELOC_V850_SDA_16_16_OFFSET, R_V850_SDA_16_16_OFFSET }, + { BFD_RELOC_V850_SDA_15_16_OFFSET, R_V850_SDA_15_16_OFFSET }, + { BFD_RELOC_V850_ZDA_16_16_OFFSET, R_V850_ZDA_16_16_OFFSET }, + { BFD_RELOC_V850_ZDA_15_16_OFFSET, R_V850_ZDA_15_16_OFFSET }, + { BFD_RELOC_V850_TDA_6_8_OFFSET, R_V850_TDA_6_8_OFFSET }, + { BFD_RELOC_V850_TDA_7_8_OFFSET, R_V850_TDA_7_8_OFFSET }, + { BFD_RELOC_V850_TDA_7_7_OFFSET, R_V850_TDA_7_7_OFFSET }, + { BFD_RELOC_V850_TDA_16_16_OFFSET, R_V850_TDA_16_16_OFFSET }, + { BFD_RELOC_V850_TDA_4_5_OFFSET, R_V850_TDA_4_5_OFFSET }, + { BFD_RELOC_V850_TDA_4_4_OFFSET, R_V850_TDA_4_4_OFFSET }, + { BFD_RELOC_V850_LO16_SPLIT_OFFSET, R_V850_LO16_SPLIT_OFFSET }, + { BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET, R_V850_SDA_16_16_SPLIT_OFFSET }, + { BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET, R_V850_ZDA_16_16_SPLIT_OFFSET }, + { BFD_RELOC_V850_CALLT_6_7_OFFSET, R_V850_CALLT_6_7_OFFSET }, + { BFD_RELOC_V850_CALLT_16_16_OFFSET, R_V850_CALLT_16_16_OFFSET }, + { BFD_RELOC_VTABLE_INHERIT, R_V850_GNU_VTINHERIT }, + { BFD_RELOC_VTABLE_ENTRY, R_V850_GNU_VTENTRY }, + { BFD_RELOC_V850_LONGCALL, R_V850_LONGCALL }, + { BFD_RELOC_V850_LONGJUMP, R_V850_LONGJUMP }, + { BFD_RELOC_V850_ALIGN, R_V850_ALIGN }, + +}; + +/* Map a bfd relocation into the appropriate howto structure. */ + +static reloc_howto_type * +v850_elf_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) +{ + unsigned int i; + + for (i = ARRAY_SIZE (v850_elf_reloc_map); i --;) + if (v850_elf_reloc_map[i].bfd_reloc_val == code) + { + unsigned int elf_reloc_val = v850_elf_reloc_map[i].elf_reloc_val; + + BFD_ASSERT (v850_elf_howto_table[elf_reloc_val].type == elf_reloc_val); + + return v850_elf_howto_table + elf_reloc_val; + } + + return NULL; +} + +/* Set the howto pointer for an V850 ELF reloc. */ + +static void +v850_elf_info_to_howto_rel (bfd *abfd ATTRIBUTE_UNUSED, + arelent *cache_ptr, + Elf_Internal_Rela *dst) +{ + unsigned int r_type; + + r_type = ELF32_R_TYPE (dst->r_info); + BFD_ASSERT (r_type < (unsigned int) R_V850_max); + cache_ptr->howto = &v850_elf_howto_table[r_type]; +} + +/* Set the howto pointer for a V850 ELF reloc (type RELA). */ + +static void +v850_elf_info_to_howto_rela (bfd *abfd ATTRIBUTE_UNUSED, + arelent * cache_ptr, + Elf_Internal_Rela *dst) +{ + unsigned int r_type; + + r_type = ELF32_R_TYPE (dst->r_info); + BFD_ASSERT (r_type < (unsigned int) R_V850_max); + cache_ptr->howto = &v850_elf_howto_table[r_type]; +} static bfd_boolean -v850_elf_is_local_label_name (abfd, name) - bfd *abfd ATTRIBUTE_UNUSED; - const char *name; +v850_elf_is_local_label_name (bfd *abfd ATTRIBUTE_UNUSED, const char *name) { return ( (name[0] == '.' && (name[1] == 'L' || name[1] == '.')) || (name[0] == '_' && name[1] == '.' && name[2] == 'L' && name[3] == '_')); @@ -1459,20 +1381,17 @@ v850_elf_is_local_label_name (abfd, name /* Perform a relocation as part of a final link. */ static bfd_reloc_status_type -v850_elf_final_link_relocate (howto, input_bfd, output_bfd, - input_section, contents, offset, value, - addend, info, sym_sec, is_local) - reloc_howto_type *howto; - bfd *input_bfd; - bfd *output_bfd ATTRIBUTE_UNUSED; - asection *input_section; - bfd_byte *contents; - bfd_vma offset; - bfd_vma value; - bfd_vma addend; - struct bfd_link_info *info; - asection *sym_sec; - int is_local ATTRIBUTE_UNUSED; +v850_elf_final_link_relocate (reloc_howto_type *howto, + bfd *input_bfd, + bfd *output_bfd ATTRIBUTE_UNUSED, + asection *input_section, + bfd_byte *contents, + bfd_vma offset, + bfd_vma value, + bfd_vma addend, + struct bfd_link_info *info, + asection *sym_sec, + int is_local ATTRIBUTE_UNUSED) { unsigned int r_type = howto->type; bfd_byte *hit_data = contents + offset; @@ -1495,7 +1414,7 @@ v850_elf_final_link_relocate (howto, inp if (((value & 0xff000000) != 0x0) && ((value & 0xff000000) != 0xff000000)) return bfd_reloc_overflow; - /* Only the bottom 24 bits of the PC are valid */ + /* Only the bottom 24 bits of the PC are valid. */ value = SEXT24 (value); break; @@ -1535,7 +1454,7 @@ v850_elf_final_link_relocate (howto, inp /* Get the value of __gp. */ h = bfd_link_hash_lookup (info->hash, "__gp", FALSE, FALSE, TRUE); - if (h == (struct bfd_link_hash_entry *) NULL + if (h == NULL || h->type != bfd_link_hash_defined) return bfd_reloc_gp_not_found; @@ -1560,7 +1479,7 @@ v850_elf_final_link_relocate (howto, inp /* Get the value of __ep. */ h = bfd_link_hash_lookup (info->hash, "__ep", FALSE, FALSE, TRUE); - if (h == (struct bfd_link_hash_entry *) NULL + if (h == NULL || h->type != bfd_link_hash_defined) return bfd_reloc_ep_not_found; @@ -1579,7 +1498,7 @@ v850_elf_final_link_relocate (howto, inp /* Get the value of __ctbp. */ h = bfd_link_hash_lookup (info->hash, "__ctbp", FALSE, FALSE, TRUE); - if (h == (struct bfd_link_hash_entry *) NULL + if (h == NULL || h->type != bfd_link_hash_defined) return bfd_reloc_ctbp_not_found; @@ -1600,7 +1519,7 @@ v850_elf_final_link_relocate (howto, inp /* Get the value of __ctbp. */ h = bfd_link_hash_lookup (info->hash, "__ctbp", FALSE, FALSE, TRUE); - if (h == (struct bfd_link_hash_entry *) NULL + if (h == NULL || h->type != bfd_link_hash_defined) return bfd_reloc_ctbp_not_found; @@ -1632,16 +1551,14 @@ v850_elf_final_link_relocate (howto, inp /* Relocate an V850 ELF section. */ static bfd_boolean -v850_elf_relocate_section (output_bfd, info, input_bfd, input_section, - contents, relocs, local_syms, local_sections) - bfd *output_bfd; - struct bfd_link_info *info; - bfd *input_bfd; - asection *input_section; - bfd_byte *contents; - Elf_Internal_Rela *relocs; - Elf_Internal_Sym *local_syms; - asection **local_sections; +v850_elf_relocate_section (bfd *output_bfd, + struct bfd_link_info *info, + bfd *input_bfd, + asection *input_section, + bfd_byte *contents, + Elf_Internal_Rela *relocs, + Elf_Internal_Sym *local_syms, + asection **local_sections) { Elf_Internal_Shdr *symtab_hdr; struct elf_link_hash_entry **sym_hashes; @@ -1694,9 +1611,9 @@ v850_elf_relocate_section (output_bfd, i { bfd_boolean unresolved_reloc, warned; - /* Note - this check is delayed until now as it is possible and valid - to have a file without any symbols but with relocs that can be - processed. */ + /* Note - this check is delayed until now as it is possible and + valid to have a file without any symbols but with relocs that + can be processed. */ if (sym_hashes == NULL) { info->callbacks->warning @@ -1722,7 +1639,7 @@ v850_elf_relocate_section (output_bfd, i if (r != bfd_reloc_ok) { const char * name; - const char * msg = (const char *)0; + const char * msg = NULL; if (h != NULL) name = h->root.root.string; @@ -1793,23 +1710,21 @@ v850_elf_relocate_section (output_bfd, i } static bfd_boolean -v850_elf_gc_sweep_hook (abfd, info, sec, relocs) - bfd *abfd ATTRIBUTE_UNUSED; - struct bfd_link_info *info ATTRIBUTE_UNUSED; - asection *sec ATTRIBUTE_UNUSED; - const Elf_Internal_Rela *relocs ATTRIBUTE_UNUSED; +v850_elf_gc_sweep_hook (bfd *abfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info ATTRIBUTE_UNUSED, + asection *sec ATTRIBUTE_UNUSED, + const Elf_Internal_Rela *relocs ATTRIBUTE_UNUSED) { /* No got and plt entries for v850-elf. */ return TRUE; } static asection * -v850_elf_gc_mark_hook (sec, info, rel, h, sym) - asection *sec; - struct bfd_link_info *info ATTRIBUTE_UNUSED; - Elf_Internal_Rela *rel; - struct elf_link_hash_entry *h; - Elf_Internal_Sym *sym; +v850_elf_gc_mark_hook (asection *sec, + struct bfd_link_info *info ATTRIBUTE_UNUSED, + Elf_Internal_Rela *rel, + struct elf_link_hash_entry *h, + Elf_Internal_Sym *sym) { if (h != NULL) { @@ -1843,8 +1758,7 @@ v850_elf_gc_mark_hook (sec, info, rel, h /* Set the right machine number. */ static bfd_boolean -v850_elf_object_p (abfd) - bfd *abfd; +v850_elf_object_p (bfd *abfd) { switch (elf_elfheader (abfd)->e_flags & EF_V850_ARCH) { @@ -1865,18 +1779,17 @@ v850_elf_object_p (abfd) /* Store the machine number in the flags field. */ static void -v850_elf_final_write_processing (abfd, linker) - bfd *abfd; - bfd_boolean linker ATTRIBUTE_UNUSED; +v850_elf_final_write_processing (bfd *abfd, + bfd_boolean linker ATTRIBUTE_UNUSED) { unsigned long val; switch (bfd_get_mach (abfd)) { default: - case bfd_mach_v850: val = E_V850_ARCH; break; - case bfd_mach_v850e: val = E_V850E_ARCH; break; - case bfd_mach_v850e1: val = E_V850E1_ARCH; break; + case bfd_mach_v850: val = E_V850_ARCH; break; + case bfd_mach_v850e: val = E_V850E_ARCH; break; + case bfd_mach_v850e1: val = E_V850E1_ARCH; break; } elf_elfheader (abfd)->e_flags &=~ EF_V850_ARCH; @@ -1886,9 +1799,7 @@ v850_elf_final_write_processing (abfd, l /* Function to keep V850 specific file flags. */ static bfd_boolean -v850_elf_set_private_flags (abfd, flags) - bfd *abfd; - flagword flags; +v850_elf_set_private_flags (bfd *abfd, flagword flags) { BFD_ASSERT (!elf_flags_init (abfd) || elf_elfheader (abfd)->e_flags == flags); @@ -1900,10 +1811,9 @@ v850_elf_set_private_flags (abfd, flags) /* Merge backend specific data from an object file to the output object file when linking. */ + static bfd_boolean -v850_elf_merge_private_bfd_data (ibfd, obfd) - bfd *ibfd; - bfd *obfd; +v850_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd) { flagword out_flags; flagword in_flags; @@ -1967,9 +1877,7 @@ v850_elf_merge_private_bfd_data (ibfd, o /* Display the flags field. */ static bfd_boolean -v850_elf_print_private_bfd_data (abfd, ptr) - bfd *abfd; - PTR ptr; +v850_elf_print_private_bfd_data (bfd *abfd, void * ptr) { FILE * file = (FILE *) ptr; @@ -1984,7 +1892,7 @@ v850_elf_print_private_bfd_data (abfd, p { default: case E_V850_ARCH: fprintf (file, _("v850 architecture")); break; - case E_V850E_ARCH: fprintf (file, _("v850e architecture")); break; + case E_V850E_ARCH: fprintf (file, _("v850e architecture")); break; case E_V850E1_ARCH: fprintf (file, _("v850e1 architecture")); break; } @@ -2014,10 +1922,9 @@ static asymbol * v850_elf_zcom_symbol_pt corresponding ELF section index. */ static bfd_boolean -v850_elf_section_from_bfd_section (abfd, sec, retval) - bfd *abfd ATTRIBUTE_UNUSED; - asection *sec; - int *retval; +v850_elf_section_from_bfd_section (bfd *abfd ATTRIBUTE_UNUSED, + asection *sec, + int *retval) { if (strcmp (bfd_get_section_name (abfd, sec), ".scommon") == 0) *retval = SHN_V850_SCOMMON; @@ -2034,9 +1941,7 @@ v850_elf_section_from_bfd_section (abfd, /* Handle the special V850 section numbers that a symbol may use. */ static void -v850_elf_symbol_processing (abfd, asym) - bfd *abfd; - asymbol *asym; +v850_elf_symbol_processing (bfd *abfd, asymbol *asym) { elf_symbol_type * elfsym = (elf_symbol_type *) asym; unsigned int indx; @@ -2130,14 +2035,13 @@ v850_elf_symbol_processing (abfd, asym) file. We must handle the special v850 section numbers here. */ static bfd_boolean -v850_elf_add_symbol_hook (abfd, info, sym, namep, flagsp, secp, valp) - bfd *abfd; - struct bfd_link_info *info ATTRIBUTE_UNUSED; - Elf_Internal_Sym *sym; - const char **namep ATTRIBUTE_UNUSED; - flagword *flagsp ATTRIBUTE_UNUSED; - asection **secp; - bfd_vma *valp; +v850_elf_add_symbol_hook (bfd *abfd, + struct bfd_link_info *info ATTRIBUTE_UNUSED, + Elf_Internal_Sym *sym, + const char **namep ATTRIBUTE_UNUSED, + flagword *flagsp ATTRIBUTE_UNUSED, + asection **secp, + bfd_vma *valp) { unsigned int indx = sym->st_shndx; @@ -2191,12 +2095,11 @@ v850_elf_add_symbol_hook (abfd, info, sy } static bfd_boolean -v850_elf_link_output_symbol_hook (info, name, sym, input_sec, h) - struct bfd_link_info *info ATTRIBUTE_UNUSED; - const char *name ATTRIBUTE_UNUSED; - Elf_Internal_Sym *sym; - asection *input_sec; - struct elf_link_hash_entry *h ATTRIBUTE_UNUSED; +v850_elf_link_output_symbol_hook (struct bfd_link_info *info ATTRIBUTE_UNUSED, + const char *name ATTRIBUTE_UNUSED, + Elf_Internal_Sym *sym, + asection *input_sec, + struct elf_link_hash_entry *h ATTRIBUTE_UNUSED) { /* If we see a common symbol, which implies a relocatable link, then if a symbol was in a special common section in an input file, mark @@ -2247,23 +2150,18 @@ v850_elf_section_from_shdr (bfd *abfd, by the section name, which is a hack, but ought to work. */ static bfd_boolean -v850_elf_fake_sections (abfd, hdr, sec) - bfd *abfd ATTRIBUTE_UNUSED; - Elf_Internal_Shdr *hdr; - asection *sec; +v850_elf_fake_sections (bfd *abfd ATTRIBUTE_UNUSED, + Elf_Internal_Shdr *hdr, + asection *sec) { - register const char * name; + const char * name; name = bfd_get_section_name (abfd, sec); if (strcmp (name, ".scommon") == 0) - { - hdr->sh_type = SHT_V850_SCOMMON; - } + hdr->sh_type = SHT_V850_SCOMMON; else if (strcmp (name, ".tcommon") == 0) - { - hdr->sh_type = SHT_V850_TCOMMON; - } + hdr->sh_type = SHT_V850_TCOMMON; else if (strcmp (name, ".zcommon") == 0) hdr->sh_type = SHT_V850_ZCOMMON; @@ -2273,12 +2171,11 @@ v850_elf_fake_sections (abfd, hdr, sec) /* Delete some bytes from a section while relaxing. */ static bfd_boolean -v850_elf_relax_delete_bytes (abfd, sec, addr, toaddr, count) - bfd *abfd; - asection *sec; - bfd_vma addr; - bfd_vma toaddr; - int count; +v850_elf_relax_delete_bytes (bfd *abfd, + asection *sec, + bfd_vma addr, + bfd_vma toaddr, + int count) { Elf_Internal_Shdr *symtab_hdr; Elf32_External_Sym *extsyms; @@ -2499,11 +2396,10 @@ v850_elf_relax_delete_bytes (abfd, sec, #define JMP_R1(insn) ((insn) & 0x1f) static bfd_boolean -v850_elf_relax_section (abfd, sec, link_info, again) - bfd *abfd; - asection *sec; - struct bfd_link_info *link_info; - bfd_boolean *again; +v850_elf_relax_section (bfd *abfd, + asection *sec, + struct bfd_link_info *link_info, + bfd_boolean *again) { Elf_Internal_Shdr *symtab_hdr; Elf_Internal_Rela *internal_relocs; @@ -2527,8 +2423,7 @@ v850_elf_relax_section (abfd, sec, link_ symtab_hdr = & elf_tdata (abfd)->symtab_hdr; internal_relocs = (_bfd_elf_link_read_relocs - (abfd, sec, (PTR) NULL, (Elf_Internal_Rela *) NULL, - link_info->keep_memory)); + (abfd, sec, NULL, NULL, link_info->keep_memory)); if (internal_relocs == NULL) goto error_return; @@ -2610,7 +2505,7 @@ v850_elf_relax_section (abfd, sec, link_ contents = elf_section_data (sec)->this_hdr.contents; else { - if (!bfd_malloc_and_get_section (abfd, sec, &contents)) + if (! bfd_malloc_and_get_section (abfd, sec, &contents)) goto error_return; } } @@ -3129,93 +3024,36 @@ v850_elf_relax_section (abfd, sec, link_ goto finish; } -static struct bfd_elf_special_section const - v850_special_sections_c[]= +static const struct bfd_elf_special_section v850_elf_special_sections[] = { { ".call_table_data", 16, 0, SHT_PROGBITS, (SHF_ALLOC + SHF_WRITE) }, { ".call_table_text", 16, 0, SHT_PROGBITS, (SHF_ALLOC + SHF_WRITE + SHF_EXECINSTR) }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - v850_special_sections_r[]= -{ { ".rosdata", 8, -2, SHT_PROGBITS, (SHF_ALLOC + SHF_V850_GPREL) }, { ".rozdata", 8, -2, SHT_PROGBITS, (SHF_ALLOC + SHF_V850_R0REL) }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - v850_special_sections_s[]= -{ - { ".sdata", 6, -2, SHT_PROGBITS, (SHF_ALLOC + SHF_WRITE - + SHF_V850_GPREL) }, { ".sbss", 5, -2, SHT_NOBITS, (SHF_ALLOC + SHF_WRITE + SHF_V850_GPREL) }, { ".scommon", 8, -2, SHT_V850_SCOMMON, (SHF_ALLOC + SHF_WRITE + SHF_V850_GPREL) }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - v850_special_sections_t[]= -{ - { ".tdata", 6, -2, SHT_PROGBITS, (SHF_ALLOC + SHF_WRITE - + SHF_V850_EPREL) }, + { ".sdata", 6, -2, SHT_PROGBITS, (SHF_ALLOC + SHF_WRITE + + SHF_V850_GPREL) }, { ".tbss", 5, -2, SHT_NOBITS, (SHF_ALLOC + SHF_WRITE + SHF_V850_EPREL) }, { ".tcommon", 8, -2, SHT_V850_TCOMMON, (SHF_ALLOC + SHF_WRITE + SHF_V850_R0REL) }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - v850_special_sections_z[]= -{ - { ".zdata", 6, -2, SHT_PROGBITS, (SHF_ALLOC + SHF_WRITE - + SHF_V850_R0REL) }, + { ".tdata", 6, -2, SHT_PROGBITS, (SHF_ALLOC + SHF_WRITE + + SHF_V850_EPREL) }, { ".zbss", 5, -2, SHT_NOBITS, (SHF_ALLOC + SHF_WRITE + SHF_V850_R0REL) }, { ".zcommon", 8, -2, SHT_V850_ZCOMMON, (SHF_ALLOC + SHF_WRITE + SHF_V850_R0REL) }, + { ".zdata", 6, -2, SHT_PROGBITS, (SHF_ALLOC + SHF_WRITE + + SHF_V850_R0REL) }, { NULL, 0, 0, 0, 0 } }; - -static struct bfd_elf_special_section const * - v850_elf_special_sections[27] = -{ - NULL, /* 'a' */ - NULL, /* 'b' */ - v850_special_sections_c, /* 'c' */ - NULL, /* 'd' */ - NULL, /* 'e' */ - NULL, /* 'f' */ - NULL, /* 'g' */ - NULL, /* 'h' */ - NULL, /* 'i' */ - NULL, /* 'j' */ - NULL, /* 'k' */ - NULL, /* 'l' */ - NULL, /* 'm' */ - NULL, /* 'n' */ - NULL, /* 'o' */ - NULL, /* 'p' */ - NULL, /* 'q' */ - v850_special_sections_r, /* 'r' */ - v850_special_sections_s, /* 's' */ - v850_special_sections_t, /* 't' */ - NULL, /* 'u' */ - NULL, /* 'v' */ - NULL, /* 'w' */ - NULL, /* 'x' */ - NULL, /* 'y' */ - v850_special_sections_z, /* 'z' */ - NULL /* other */ -}; #define TARGET_LITTLE_SYM bfd_elf32_v850_vec #define TARGET_LITTLE_NAME "elf32-v850" diff -uprN binutils-2.16.91.0.1/bfd/elf32-vax.c binutils-2.16.91.0.2/bfd/elf32-vax.c --- binutils-2.16.91.0.1/bfd/elf32-vax.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-vax.c 2005-07-20 12:27:27.290193538 -0700 @@ -1173,7 +1173,6 @@ elf_vax_size_dynamic_sections (bfd *outp for (s = dynobj->sections; s != NULL; s = s->next) { const char *name; - bfd_boolean strip; if ((s->flags & SEC_LINKER_CREATED) == 0) continue; @@ -1182,38 +1181,14 @@ elf_vax_size_dynamic_sections (bfd *outp of the dynobj section names depend upon the input files. */ name = bfd_get_section_name (dynobj, s); - strip = FALSE; - if (strcmp (name, ".plt") == 0) { - if (s->size == 0) - { - /* Strip this section if we don't need it; see the - comment below. */ - strip = TRUE; - } - else - { - /* Remember whether there is a PLT. */ - plt = TRUE; - } + /* Remember whether there is a PLT. */ + plt = s->size != 0; } else if (strncmp (name, ".rela", 5) == 0) { - if (s->size == 0) - { - /* If we don't need this section, strip it from the - output file. This is mostly to handle .rela.bss and - .rela.plt. We must create both sections in - create_dynamic_sections, because they must be created - before the linker maps input sections to output - sections. The linker does that before - adjust_dynamic_symbol is called, and it is that - function which decides whether anything needs to go - into these sections. */ - strip = TRUE; - } - else + if (s->size != 0) { asection *target; @@ -1243,21 +1218,34 @@ elf_vax_size_dynamic_sections (bfd *outp s->reloc_count = 0; } } - else if (strncmp (name, ".got", 4) != 0) + else if (strncmp (name, ".got", 4) != 0 + && strcmp (name, ".dynbss") != 0) { /* It's not one of our sections, so don't allocate space. */ continue; } - if (strip) + if (s->size == 0) { + /* If we don't need this section, strip it from the + output file. This is mostly to handle .rela.bss and + .rela.plt. We must create both sections in + create_dynamic_sections, because they must be created + before the linker maps input sections to output + sections. The linker does that before + adjust_dynamic_symbol is called, and it is that + function which decides whether anything needs to go + into these sections. */ s->flags |= SEC_EXCLUDE; continue; } + if ((s->flags & SEC_HAS_CONTENTS) == 0) + continue; + /* Allocate memory for the section contents. */ s->contents = (bfd_byte *) bfd_alloc (dynobj, s->size); - if (s->contents == NULL && s->size != 0) + if (s->contents == NULL) return FALSE; } diff -uprN binutils-2.16.91.0.1/bfd/elf32-xstormy16.c binutils-2.16.91.0.2/bfd/elf32-xstormy16.c --- binutils-2.16.91.0.1/bfd/elf32-xstormy16.c 2005-05-10 15:46:42.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-xstormy16.c 2005-07-20 12:27:27.294192878 -0700 @@ -1,21 +1,22 @@ -/* XSTORMY16-specific support for 32-bit ELF. - Copyright 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. +/* Xstormy16-specific support for 32-bit ELF. + Copyright 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. -This file is part of BFD, the Binary File Descriptor library. + This file is part of BFD, the Binary File Descriptor library. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, + USA. */ #include "bfd.h" #include "sysdep.h" @@ -24,38 +25,48 @@ Foundation, Inc., 51 Franklin Street - F #include "elf/xstormy16.h" #include "libiberty.h" -/* Forward declarations. */ -static reloc_howto_type * xstormy16_reloc_type_lookup - PARAMS ((bfd *abfd, bfd_reloc_code_real_type code)); -static void xstormy16_info_to_howto_rela - PARAMS ((bfd *, arelent *, Elf_Internal_Rela *)); -static bfd_reloc_status_type xstormy16_elf_24_reloc - PARAMS ((bfd *abfd, arelent *reloc_entry, asymbol *symbol, - PTR data, asection *input_section, bfd *output_bfd, - char **error_message)); -static bfd_boolean xstormy16_elf_check_relocs - PARAMS ((bfd *, struct bfd_link_info *, asection *, - const Elf_Internal_Rela *)); -static bfd_boolean xstormy16_relax_plt_check - PARAMS ((struct elf_link_hash_entry *, PTR)); -static bfd_boolean xstormy16_relax_plt_realloc - PARAMS ((struct elf_link_hash_entry *, PTR)); -static bfd_boolean xstormy16_elf_relax_section - PARAMS ((bfd *abfd, asection *sec, struct bfd_link_info *link_info, - bfd_boolean *again)); -static bfd_boolean xstormy16_elf_always_size_sections - PARAMS ((bfd *, struct bfd_link_info *)); -static bfd_boolean xstormy16_elf_relocate_section - PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, - Elf_Internal_Rela *, Elf_Internal_Sym *, asection **)); -static bfd_boolean xstormy16_elf_finish_dynamic_sections - PARAMS((bfd *, struct bfd_link_info *)); -static bfd_boolean xstormy16_elf_gc_sweep_hook - PARAMS ((bfd *, struct bfd_link_info *, asection *, - const Elf_Internal_Rela *)); -static asection * xstormy16_elf_gc_mark_hook - PARAMS ((asection *, struct bfd_link_info *, Elf_Internal_Rela *, - struct elf_link_hash_entry *, Elf_Internal_Sym *)); +/* Handle the R_XSTORMY16_24 reloc, which has an odd bit arrangement. */ + +static bfd_reloc_status_type +xstormy16_elf_24_reloc (bfd *abfd, + arelent *reloc_entry, + asymbol *symbol, + void * data, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) +{ + bfd_vma relocation, x; + + if (output_bfd != NULL) + { + reloc_entry->address += input_section->output_offset; + return bfd_reloc_ok; + } + + if (reloc_entry->address > bfd_get_section_limit (abfd, input_section)) + return bfd_reloc_outofrange; + + if (bfd_is_com_section (symbol->section)) + relocation = 0; + else + relocation = symbol->value; + + relocation += symbol->section->output_section->vma; + relocation += symbol->section->output_offset; + relocation += reloc_entry->addend; + + x = bfd_get_32 (abfd, (bfd_byte *) data + reloc_entry->address); + x &= 0x0000ff00; + x |= relocation & 0xff; + x |= (relocation << 8) & 0xffff0000; + bfd_put_32 (abfd, x, (bfd_byte *) data + reloc_entry->address); + + if (relocation & ~ (bfd_vma) 0xffffff) + return bfd_reloc_overflow; + + return bfd_reloc_ok; +} static reloc_howto_type xstormy16_elf_howto_table [] = { @@ -238,7 +249,7 @@ static reloc_howto_type xstormy16_elf_ho 0, /* src_mask */ 0xffff, /* dst_mask */ FALSE), /* pcrel_offset */ - + /* A 12 bit absolute relocation. */ HOWTO (R_XSTORMY16_12, /* type */ 0, /* rightshift */ @@ -318,9 +329,8 @@ static const reloc_map xstormy16_reloc_m }; static reloc_howto_type * -xstormy16_reloc_type_lookup (abfd, code) - bfd * abfd ATTRIBUTE_UNUSED; - bfd_reloc_code_real_type code; +xstormy16_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) { unsigned int i; @@ -341,10 +351,9 @@ xstormy16_reloc_type_lookup (abfd, code) /* Set the howto pointer for an XSTORMY16 ELF reloc. */ static void -xstormy16_info_to_howto_rela (abfd, cache_ptr, dst) - bfd * abfd ATTRIBUTE_UNUSED; - arelent * cache_ptr; - Elf_Internal_Rela * dst; +xstormy16_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED, + arelent * cache_ptr, + Elf_Internal_Rela * dst) { unsigned int r_type = ELF32_R_TYPE (dst->r_info); @@ -357,51 +366,6 @@ xstormy16_info_to_howto_rela (abfd, cach else abort (); } - -/* Handle the R_XSTORMY16_24 reloc, which has an odd bit arrangement. */ - -static bfd_reloc_status_type -xstormy16_elf_24_reloc (abfd, reloc_entry, symbol, data, input_section, - output_bfd, error_message) - bfd *abfd; - arelent *reloc_entry; - asymbol *symbol; - PTR data; - asection *input_section; - bfd *output_bfd; - char **error_message ATTRIBUTE_UNUSED; -{ - bfd_vma relocation, x; - - if (output_bfd != NULL) - { - reloc_entry->address += input_section->output_offset; - return bfd_reloc_ok; - } - - if (reloc_entry->address > bfd_get_section_limit (abfd, input_section)) - return bfd_reloc_outofrange; - - if (bfd_is_com_section (symbol->section)) - relocation = 0; - else - relocation = symbol->value; - - relocation += symbol->section->output_section->vma; - relocation += symbol->section->output_offset; - relocation += reloc_entry->addend; - - x = bfd_get_32 (abfd, (bfd_byte *) data + reloc_entry->address); - x &= 0x0000ff00; - x |= relocation & 0xff; - x |= (relocation << 8) & 0xffff0000; - bfd_put_32 (abfd, x, (bfd_byte *) data + reloc_entry->address); - - if (relocation & ~ (bfd_vma) 0xffffff) - return bfd_reloc_overflow; - - return bfd_reloc_ok; -} /* We support 16-bit pointers to code above 64k by generating a thunk below 64k containing a JMPF instruction to the final address. We @@ -410,11 +374,10 @@ xstormy16_elf_24_reloc (abfd, reloc_entr sections will fall in the address space. */ static bfd_boolean -xstormy16_elf_check_relocs (abfd, info, sec, relocs) - bfd *abfd; - struct bfd_link_info *info; - asection *sec; - const Elf_Internal_Rela *relocs; +xstormy16_elf_check_relocs (bfd *abfd, + struct bfd_link_info *info, + asection *sec, + const Elf_Internal_Rela *relocs) { const Elf_Internal_Rela *rel, *relend; struct elf_link_hash_entry **sym_hashes; @@ -495,7 +458,7 @@ xstormy16_elf_check_relocs (abfd, info, unsigned int i; size = symtab_hdr->sh_info * sizeof (bfd_vma); - local_plt_offsets = (bfd_vma *) bfd_alloc (abfd, size); + local_plt_offsets = bfd_alloc (abfd, size); if (local_plt_offsets == NULL) return FALSE; elf_local_got_offsets (abfd) = local_plt_offsets; @@ -542,9 +505,7 @@ struct relax_plt_data }; static bfd_boolean -xstormy16_relax_plt_check (h, xdata) - struct elf_link_hash_entry *h; - PTR xdata; +xstormy16_relax_plt_check (struct elf_link_hash_entry *h, void * xdata) { struct relax_plt_data *data = (struct relax_plt_data *) xdata; @@ -578,9 +539,7 @@ xstormy16_relax_plt_check (h, xdata) previously had a plt entry, give it a new entry offset. */ static bfd_boolean -xstormy16_relax_plt_realloc (h, xdata) - struct elf_link_hash_entry *h; - PTR xdata; +xstormy16_relax_plt_realloc (struct elf_link_hash_entry *h, void * xdata) { bfd_vma *entry = (bfd_vma *) xdata; @@ -597,11 +556,10 @@ xstormy16_relax_plt_realloc (h, xdata) } static bfd_boolean -xstormy16_elf_relax_section (dynobj, splt, info, again) - bfd *dynobj; - asection *splt; - struct bfd_link_info *info; - bfd_boolean *again; +xstormy16_elf_relax_section (bfd *dynobj, + asection *splt, + struct bfd_link_info *info, + bfd_boolean *again) { struct relax_plt_data relax_plt_data; bfd *ibfd; @@ -726,9 +684,8 @@ xstormy16_elf_relax_section (dynobj, spl } static bfd_boolean -xstormy16_elf_always_size_sections (output_bfd, info) - bfd *output_bfd ATTRIBUTE_UNUSED; - struct bfd_link_info *info; +xstormy16_elf_always_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info) { bfd *dynobj; asection *splt; @@ -743,7 +700,7 @@ xstormy16_elf_always_size_sections (outp splt = bfd_get_section_by_name (dynobj, ".plt"); BFD_ASSERT (splt != NULL); - splt->contents = (bfd_byte *) bfd_zalloc (dynobj, splt->size); + splt->contents = bfd_zalloc (dynobj, splt->size); if (splt->contents == NULL) return FALSE; @@ -781,16 +738,14 @@ xstormy16_elf_always_size_sections (outp accordingly. */ static bfd_boolean -xstormy16_elf_relocate_section (output_bfd, info, input_bfd, input_section, - contents, relocs, local_syms, local_sections) - bfd * output_bfd ATTRIBUTE_UNUSED; - struct bfd_link_info * info; - bfd * input_bfd; - asection * input_section; - bfd_byte * contents; - Elf_Internal_Rela * relocs; - Elf_Internal_Sym * local_syms; - asection ** local_sections; +xstormy16_elf_relocate_section (bfd * output_bfd ATTRIBUTE_UNUSED, + struct bfd_link_info * info, + bfd * input_bfd, + asection * input_section, + bfd_byte * contents, + Elf_Internal_Rela * relocs, + Elf_Internal_Sym * local_syms, + asection ** local_sections) { Elf_Internal_Shdr * symtab_hdr; struct elf_link_hash_entry ** sym_hashes; @@ -934,7 +889,7 @@ xstormy16_elf_relocate_section (output_b if (r != bfd_reloc_ok) { - const char * msg = (const char *) NULL; + const char * msg = NULL; switch (r) { @@ -982,9 +937,8 @@ xstormy16_elf_relocate_section (output_b /* This must exist if dynobj is ever set. */ static bfd_boolean -xstormy16_elf_finish_dynamic_sections (abfd, info) - bfd *abfd ATTRIBUTE_UNUSED; - struct bfd_link_info *info; +xstormy16_elf_finish_dynamic_sections (bfd *abfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info) { bfd *dynobj; asection *splt; @@ -997,9 +951,11 @@ xstormy16_elf_finish_dynamic_sections (a { bfd_byte *contents = splt->contents; unsigned int i, size = splt->size; + for (i = 0; i < size; i += 4) { unsigned int x = bfd_get_32 (dynobj, contents + i); + BFD_ASSERT (x != 0); } } @@ -1011,12 +967,11 @@ xstormy16_elf_finish_dynamic_sections (a relocation. */ static asection * -xstormy16_elf_gc_mark_hook (sec, info, rel, h, sym) - asection * sec; - struct bfd_link_info * info ATTRIBUTE_UNUSED; - Elf_Internal_Rela * rel; - struct elf_link_hash_entry * h; - Elf_Internal_Sym * sym; +xstormy16_elf_gc_mark_hook (asection * sec, + struct bfd_link_info * info ATTRIBUTE_UNUSED, + Elf_Internal_Rela * rel, + struct elf_link_hash_entry * h, + Elf_Internal_Sym * sym) { if (h != NULL) { @@ -1050,11 +1005,10 @@ xstormy16_elf_gc_mark_hook (sec, info, r /* Update the got entry reference counts for the section being removed. */ static bfd_boolean -xstormy16_elf_gc_sweep_hook (abfd, info, sec, relocs) - bfd * abfd ATTRIBUTE_UNUSED; - struct bfd_link_info * info ATTRIBUTE_UNUSED; - asection * sec ATTRIBUTE_UNUSED; - const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED; +xstormy16_elf_gc_sweep_hook (bfd * abfd ATTRIBUTE_UNUSED, + struct bfd_link_info * info ATTRIBUTE_UNUSED, + asection * sec ATTRIBUTE_UNUSED, + const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED) { return TRUE; } diff -uprN binutils-2.16.91.0.1/bfd/elf32-xtensa.c binutils-2.16.91.0.2/bfd/elf32-xtensa.c --- binutils-2.16.91.0.1/bfd/elf32-xtensa.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf32-xtensa.c 2005-07-20 12:27:27.312189910 -0700 @@ -21,11 +21,7 @@ #include "bfd.h" #include "sysdep.h" -#ifdef ANSI_PROTOTYPES #include -#else -#include -#endif #include #include "bfdlink.h" @@ -40,7 +36,7 @@ /* Local helper functions. */ static bfd_boolean add_extra_plt_sections (bfd *, int); -static char *build_encoding_error_message (xtensa_opcode, bfd_vma); +static char *vsprint_msg (const char *, const char *, int, ...) ATTRIBUTE_PRINTF(2,4); static bfd_reloc_status_type bfd_elf_xtensa_reloc (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **); static bfd_boolean do_fix_for_relocatable_link @@ -1409,7 +1405,6 @@ elf_xtensa_size_dynamic_sections (bfd *o for (s = dynobj->sections; s != NULL; s = s->next) { const char *name; - bfd_boolean strip; if ((s->flags & SEC_LINKER_CREATED) == 0) continue; @@ -1418,37 +1413,23 @@ elf_xtensa_size_dynamic_sections (bfd *o of the dynobj section names depend upon the input files. */ name = bfd_get_section_name (dynobj, s); - strip = FALSE; - if (strncmp (name, ".rela", 5) == 0) { - if (strcmp (name, ".rela.plt") == 0) - relplt = TRUE; - else if (strcmp (name, ".rela.got") == 0) - relgot = TRUE; - - /* We use the reloc_count field as a counter if we need - to copy relocs into the output file. */ - s->reloc_count = 0; - } - else if (strncmp (name, ".plt.", 5) == 0 - || strncmp (name, ".got.plt.", 9) == 0) - { - if (s->size == 0) - { - /* If we don't need this section, strip it from the output - file. We must create the ".plt*" and ".got.plt*" - sections in create_dynamic_sections and/or check_relocs - based on a conservative estimate of the PLT relocation - count, because the sections must be created before the - linker maps input sections to output sections. The - linker does that before size_dynamic_sections, where we - compute the exact size of the PLT, so there may be more - of these sections than are actually needed. */ - strip = TRUE; + if (s->size != 0) + { + if (strcmp (name, ".rela.plt") == 0) + relplt = TRUE; + else if (strcmp (name, ".rela.got") == 0) + relgot = TRUE; + + /* We use the reloc_count field as a counter if we need + to copy relocs into the output file. */ + s->reloc_count = 0; } } - else if (strcmp (name, ".got") != 0 + else if (strncmp (name, ".plt.", 5) != 0 + && strncmp (name, ".got.plt.", 9) != 0 + && strcmp (name, ".got") != 0 && strcmp (name, ".plt") != 0 && strcmp (name, ".got.plt") != 0 && strcmp (name, ".xt.lit.plt") != 0 @@ -1458,13 +1439,24 @@ elf_xtensa_size_dynamic_sections (bfd *o continue; } - if (strip) - s->flags |= SEC_EXCLUDE; - else + if (s->size == 0) + { + /* If we don't need this section, strip it from the output + file. We must create the ".plt*" and ".got.plt*" + sections in create_dynamic_sections and/or check_relocs + based on a conservative estimate of the PLT relocation + count, because the sections must be created before the + linker maps input sections to output sections. The + linker does that before size_dynamic_sections, where we + compute the exact size of the PLT, so there may be more + of these sections than are actually needed. */ + s->flags |= SEC_EXCLUDE; + } + else if ((s->flags & SEC_HAS_CONTENTS) != 0) { /* Allocate memory for the section contents. */ s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); - if (s->contents == NULL && s->size != 0) + if (s->contents == NULL) return FALSE; } } @@ -1750,7 +1742,30 @@ elf_xtensa_do_reloc (reloc_howto_type *h || xtensa_operand_set_field (isa, opcode, opnd, fmt, slot, sbuff, newval)) { - *error_message = build_encoding_error_message (opcode, relocation); + const char *opname = xtensa_opcode_name (isa, opcode); + const char *msg; + + msg = "cannot encode"; + if (is_direct_call_opcode (opcode)) + { + if ((relocation & 0x3) != 0) + msg = "misaligned call target"; + else + msg = "call target out of range"; + } + else if (opcode == get_l32r_opcode ()) + { + if ((relocation & 0x3) != 0) + msg = "misaligned literal target"; + else if (is_alt_relocation (howto->type)) + msg = "literal target out of range (too many literals)"; + else if (self_address > relocation) + msg = "literal target out of range (try using text-section-literals)"; + else + msg = "literal placed after use"; + } + + *error_message = vsprint_msg (opname, ": %s", strlen (msg) + 2, msg); return bfd_reloc_dangerous; } @@ -1805,32 +1820,6 @@ vsprint_msg (const char *origmsg, const } -static char * -build_encoding_error_message (xtensa_opcode opcode, bfd_vma target_address) -{ - const char *opname = xtensa_opcode_name (xtensa_default_isa, opcode); - const char *msg; - - msg = "cannot encode"; - if (is_direct_call_opcode (opcode)) - { - if ((target_address & 0x3) != 0) - msg = "misaligned call target"; - else - msg = "call target out of range"; - } - else if (opcode == get_l32r_opcode ()) - { - if ((target_address & 0x3) != 0) - msg = "misaligned literal target"; - else - msg = "literal target out of range"; - } - - return vsprint_msg (opname, ": %s", strlen (msg) + 2, msg); -} - - /* This function is registered as the "special_function" in the Xtensa howto for handling simplify operations. bfd_perform_relocation / bfd_install_relocation use it to @@ -1938,7 +1927,8 @@ bfd_elf_xtensa_reloc (bfd *abfd, *error_message = ""; *error_message = vsprint_msg (*error_message, ": (%s + 0x%lx)", strlen (symbol->name) + 17, - symbol->name, reloc_entry->addend); + symbol->name, + (unsigned long) reloc_entry->addend); } return flag; @@ -2355,7 +2345,7 @@ elf_xtensa_relocate_section (bfd *output else error_message = vsprint_msg (error_message, ": (%s+0x%x)", strlen (name) + 22, - name, rel->r_addend); + name, (int)rel->r_addend); } if (!((*info->callbacks->reloc_dangerous) @@ -9482,58 +9472,13 @@ xtensa_callback_required_dependence (bfd /* The default literal sections should always be marked as "code" (i.e., SHF_EXECINSTR). This is particularly important for the Linux kernel module loader so that the literals are not placed after the text. */ -static struct bfd_elf_special_section const - xtensa_special_sections_f[]= +static const struct bfd_elf_special_section elf_xtensa_special_sections[] = { { ".fini.literal", 13, 0, SHT_PROGBITS, SHF_ALLOC + SHF_EXECINSTR }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - xtensa_special_sections_i[]= -{ { ".init.literal", 13, 0, SHT_PROGBITS, SHF_ALLOC + SHF_EXECINSTR }, - { NULL, 0, 0, 0, 0 } -}; -static struct bfd_elf_special_section const - xtensa_special_sections_l[]= -{ { ".literal", 8, 0, SHT_PROGBITS, SHF_ALLOC + SHF_EXECINSTR }, { NULL, 0, 0, 0, 0 } }; - -static struct bfd_elf_special_section const * - elf_xtensa_special_sections[27] = -{ - NULL, /* 'a' */ - NULL, /* 'b' */ - NULL, /* 'c' */ - NULL, /* 'd' */ - NULL, /* 'e' */ - xtensa_special_sections_f, /* 'f' */ - NULL, /* 'g' */ - NULL, /* 'h' */ - xtensa_special_sections_i, /* 'i' */ - NULL, /* 'j' */ - NULL, /* 'k' */ - xtensa_special_sections_l, /* 'l' */ - NULL, /* 'm' */ - NULL, /* 'n' */ - NULL, /* 'o' */ - NULL, /* 'p' */ - NULL, /* 'q' */ - NULL, /* 'r' */ - NULL, /* 's' */ - NULL, /* 't' */ - NULL, /* 'u' */ - NULL, /* 'v' */ - NULL, /* 'w' */ - NULL, /* 'x' */ - NULL, /* 'y' */ - NULL, /* 'z' */ - NULL /* other */ -}; - #ifndef ELF_ARCH #define TARGET_LITTLE_SYM bfd_elf32_xtensa_le_vec diff -uprN binutils-2.16.91.0.1/bfd/elf64-alpha.c binutils-2.16.91.0.2/bfd/elf64-alpha.c --- binutils-2.16.91.0.1/bfd/elf64-alpha.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf64-alpha.c 2005-07-20 12:27:27.330186943 -0700 @@ -1204,26 +1204,23 @@ static bfd_boolean elf64_alpha_create_got_section (bfd *abfd, struct bfd_link_info *info ATTRIBUTE_UNUSED) { + flagword flags; asection *s; - if ((s = bfd_get_section_by_name (abfd, ".got"))) - { - /* Check for a non-linker created .got? */ - if (alpha_elf_tdata (abfd)->got == NULL) - alpha_elf_tdata (abfd)->got = s; - return TRUE; - } - - s = bfd_make_section_with_flags (abfd, ".got", (SEC_ALLOC | SEC_LOAD - | SEC_HAS_CONTENTS - | SEC_IN_MEMORY - | SEC_LINKER_CREATED)); + flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY + | SEC_LINKER_CREATED); + s = bfd_make_section_anyway_with_flags (abfd, ".got", flags); if (s == NULL || !bfd_set_section_alignment (abfd, s, 3)) return FALSE; alpha_elf_tdata (abfd)->got = s; + /* Make sure the object's gotobj is set to itself so that we default + to every object with its own .got. We'll merge .gots later once + we've collected each object's info. */ + alpha_elf_tdata (abfd)->gotobj = abfd; + return TRUE; } @@ -1233,18 +1230,16 @@ static bfd_boolean elf64_alpha_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info) { asection *s; + flagword flags; struct elf_link_hash_entry *h; struct bfd_link_hash_entry *bh; /* We need to create .plt, .rela.plt, .got, and .rela.got sections. */ - s = bfd_make_section_with_flags (abfd, ".plt", - (SEC_ALLOC | SEC_LOAD | SEC_CODE - | SEC_HAS_CONTENTS - | SEC_IN_MEMORY - | SEC_LINKER_CREATED - | (elf64_alpha_use_secureplt - ? SEC_READONLY : 0))); + flags = (SEC_ALLOC | SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS | SEC_IN_MEMORY + | SEC_LINKER_CREATED + | (elf64_alpha_use_secureplt ? SEC_READONLY : 0)); + s = bfd_make_section_anyway_with_flags (abfd, ".plt", flags); if (s == NULL || ! bfd_set_section_alignment (abfd, s, 4)) return FALSE; @@ -1263,19 +1258,16 @@ elf64_alpha_create_dynamic_sections (bfd if (info->shared && ! bfd_elf_link_record_dynamic_symbol (info, h)) return FALSE; - s = bfd_make_section_with_flags (abfd, ".rela.plt", - (SEC_ALLOC | SEC_LOAD - | SEC_HAS_CONTENTS - | SEC_IN_MEMORY - | SEC_LINKER_CREATED - | SEC_READONLY)); + flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY + | SEC_LINKER_CREATED | SEC_READONLY); + s = bfd_make_section_anyway_with_flags (abfd, ".rela.plt", flags); if (s == NULL || ! bfd_set_section_alignment (abfd, s, 3)) return FALSE; if (elf64_alpha_use_secureplt) { - s = bfd_make_section_with_flags (abfd, ".got.plt", - SEC_ALLOC | SEC_LINKER_CREATED); + flags = SEC_ALLOC | SEC_LINKER_CREATED; + s = bfd_make_section_anyway_with_flags (abfd, ".got.plt", flags); if (s == NULL || ! bfd_set_section_alignment (abfd, s, 3)) return FALSE; } @@ -1283,15 +1275,15 @@ elf64_alpha_create_dynamic_sections (bfd /* We may or may not have created a .got section for this object, but we definitely havn't done the rest of the work. */ - if (!elf64_alpha_create_got_section (abfd, info)) - return FALSE; + if (alpha_elf_tdata(abfd)->gotobj == NULL) + { + if (!elf64_alpha_create_got_section (abfd, info)) + return FALSE; + } - s = bfd_make_section_with_flags (abfd, ".rela.got", - (SEC_ALLOC | SEC_LOAD - | SEC_HAS_CONTENTS - | SEC_IN_MEMORY - | SEC_LINKER_CREATED - | SEC_READONLY)); + flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY + | SEC_LINKER_CREATED | SEC_READONLY); + s = bfd_make_section_anyway_with_flags (abfd, ".rela.got", flags); if (s == NULL || !bfd_set_section_alignment (abfd, s, 3)) return FALSE; @@ -1746,7 +1738,6 @@ elf64_alpha_check_relocs (bfd *abfd, str Elf_Internal_Shdr *symtab_hdr; struct alpha_elf_link_hash_entry **sym_hashes; const Elf_Internal_Rela *rel, *relend; - bfd_boolean got_created; bfd_size_type amt; if (info->relocatable) @@ -1769,7 +1760,6 @@ elf64_alpha_check_relocs (bfd *abfd, str rel_sec_name = NULL; symtab_hdr = &elf_tdata(abfd)->symtab_hdr; sym_hashes = alpha_elf_sym_hashes(abfd); - got_created = FALSE; relend = relocs + sec->reloc_count; for (rel = relocs; rel < relend; ++rel) @@ -1881,18 +1871,10 @@ elf64_alpha_check_relocs (bfd *abfd, str if (need & NEED_GOT) { - if (!got_created) + if (alpha_elf_tdata(abfd)->gotobj == NULL) { if (!elf64_alpha_create_got_section (abfd, info)) return FALSE; - - /* Make sure the object's gotobj is set to itself so - that we default to every object with its own .got. - We'll merge .gots later once we've collected each - object's info. */ - alpha_elf_tdata(abfd)->gotobj = abfd; - - got_created = 1; } } @@ -2785,7 +2767,6 @@ elf64_alpha_size_dynamic_sections (bfd * for (s = dynobj->sections; s != NULL; s = s->next) { const char *name; - bfd_boolean strip; if (!(s->flags & SEC_LINKER_CREATED)) continue; @@ -2794,23 +2775,11 @@ elf64_alpha_size_dynamic_sections (bfd * of the dynobj section names depend upon the input files. */ name = bfd_get_section_name (dynobj, s); - /* If we don't need this section, strip it from the output file. - This is to handle .rela.bss and .rela.plt. We must create it - in create_dynamic_sections, because it must be created before - the linker maps input sections to output sections. The - linker does that before adjust_dynamic_symbol is called, and - it is that function which decides whether anything needs to - go into these sections. */ - - strip = FALSE; - if (strncmp (name, ".rela", 5) == 0) { - strip = (s->size == 0); - - if (!strip) + if (s->size != 0) { - if (strcmp(name, ".rela.plt") == 0) + if (strcmp (name, ".rela.plt") == 0) relplt = TRUE; /* We use the reloc_count field as a counter if we need @@ -2818,19 +2787,30 @@ elf64_alpha_size_dynamic_sections (bfd * s->reloc_count = 0; } } - else if (strcmp (name, ".plt") != 0) + else if (strncmp (name, ".got", 4) != 0 + && strcmp (name, ".plt") != 0 + && strcmp (name, ".dynbss") != 0) { /* It's not one of our dynamic sections, so don't allocate space. */ continue; } - if (strip) - s->flags |= SEC_EXCLUDE; - else + if (s->size == 0) + { + /* If we don't need this section, strip it from the output file. + This is to handle .rela.bss and .rela.plt. We must create it + in create_dynamic_sections, because it must be created before + the linker maps input sections to output sections. The + linker does that before adjust_dynamic_symbol is called, and + it is that function which decides whether anything needs to + go into these sections. */ + s->flags |= SEC_EXCLUDE; + } + else if ((s->flags & SEC_HAS_CONTENTS) != 0) { /* Allocate memory for the section contents. */ s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); - if (s->contents == NULL && s->size != 0) + if (s->contents == NULL) return FALSE; } } @@ -5180,46 +5160,13 @@ elf64_alpha_reloc_type_class (const Elf_ } } -static struct bfd_elf_special_section const - alpha_special_sections_s[]= +static const struct bfd_elf_special_section elf64_alpha_special_sections[] = { - { ".sdata", 6, -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE + SHF_ALPHA_GPREL }, { ".sbss", 5, -2, SHT_NOBITS, SHF_ALLOC + SHF_WRITE + SHF_ALPHA_GPREL }, + { ".sdata", 6, -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE + SHF_ALPHA_GPREL }, { NULL, 0, 0, 0, 0 } }; -static struct bfd_elf_special_section const * - elf64_alpha_special_sections[27] = -{ - NULL, /* 'a' */ - NULL, /* 'b' */ - NULL, /* 'c' */ - NULL, /* 'd' */ - NULL, /* 'e' */ - NULL, /* 'f' */ - NULL, /* 'g' */ - NULL, /* 'h' */ - NULL, /* 'i' */ - NULL, /* 'j' */ - NULL, /* 'k' */ - NULL, /* 'l' */ - NULL, /* 'm' */ - NULL, /* 'n' */ - NULL, /* 'o' */ - NULL, /* 'p' */ - NULL, /* 'q' */ - NULL, /* 'r' */ - alpha_special_sections_s, /* 's' */ - NULL, /* 't' */ - NULL, /* 'u' */ - NULL, /* 'v' */ - NULL, /* 'w' */ - NULL, /* 'x' */ - NULL, /* 'y' */ - NULL, /* 'z' */ - NULL /* other */ -}; - /* ECOFF swapping routines. These are used when dealing with the .mdebug section, which is in the ECOFF debugging format. Copied from elf32-mips.c. */ diff -uprN binutils-2.16.91.0.1/bfd/elf64-hppa.c binutils-2.16.91.0.2/bfd/elf64-hppa.c --- binutils-2.16.91.0.1/bfd/elf64-hppa.c 2005-05-10 15:46:42.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf64-hppa.c 2005-07-20 12:27:27.336185954 -0700 @@ -1699,7 +1699,6 @@ elf64_hppa_size_dynamic_sections (output for (s = dynobj->sections; s != NULL; s = s->next) { const char *name; - bfd_boolean strip; if ((s->flags & SEC_LINKER_CREATED) == 0) continue; @@ -1708,60 +1707,21 @@ elf64_hppa_size_dynamic_sections (output of the dynobj section names depend upon the input files. */ name = bfd_get_section_name (dynobj, s); - strip = 0; - if (strcmp (name, ".plt") == 0) { - /* Strip this section if we don't need it; see the comment below. */ - if (s->size == 0) - { - strip = TRUE; - } - else - { - /* Remember whether there is a PLT. */ - plt = TRUE; - } + /* Remember whether there is a PLT. */ + plt = s->size != 0; } - else if (strcmp (name, ".dlt") == 0) + else if (strcmp (name, ".opd") == 0 + || strncmp (name, ".dlt", 4) == 0 + || strcmp (name, ".stub") == 0 + || strcmp (name, ".got") == 0) { /* Strip this section if we don't need it; see the comment below. */ - if (s->size == 0) - { - strip = TRUE; - } - } - else if (strcmp (name, ".opd") == 0) - { - /* Strip this section if we don't need it; see the comment below. */ - if (s->size == 0) - { - strip = TRUE; - } } else if (strncmp (name, ".rela", 5) == 0) { - /* If we don't need this section, strip it from the output file. - This is mostly to handle .rela.bss and .rela.plt. We must - create both sections in create_dynamic_sections, because they - must be created before the linker maps input sections to output - sections. The linker does that before adjust_dynamic_symbol - is called, and it is that function which decides whether - anything needs to go into these sections. */ - if (s->size == 0) - { - /* If we don't need this section, strip it from the - output file. This is mostly to handle .rela.bss and - .rela.plt. We must create both sections in - create_dynamic_sections, because they must be created - before the linker maps input sections to output - sections. The linker does that before - adjust_dynamic_symbol is called, and it is that - function which decides whether anything needs to go - into these sections. */ - strip = TRUE; - } - else + if (s->size != 0) { asection *target; @@ -1792,20 +1752,30 @@ elf64_hppa_size_dynamic_sections (output s->reloc_count = 0; } } - else if (strncmp (name, ".dlt", 4) != 0 - && strcmp (name, ".stub") != 0 - && strcmp (name, ".got") != 0) + else { /* It's not one of our sections, so don't allocate space. */ continue; } - if (strip) + if (s->size == 0) { + /* If we don't need this section, strip it from the + output file. This is mostly to handle .rela.bss and + .rela.plt. We must create both sections in + create_dynamic_sections, because they must be created + before the linker maps input sections to output + sections. The linker does that before + adjust_dynamic_symbol is called, and it is that + function which decides whether anything needs to go + into these sections. */ s->flags |= SEC_EXCLUDE; continue; } + if ((s->flags & SEC_HAS_CONTENTS) == 0) + continue; + /* Allocate memory for the section contents if it has not been allocated already. We use bfd_zalloc here in case unused entries are not reclaimed before the section's @@ -1815,7 +1785,7 @@ elf64_hppa_size_dynamic_sections (output if (s->contents == NULL) { s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); - if (s->contents == NULL && s->size != 0) + if (s->contents == NULL) return FALSE; } } @@ -2671,52 +2641,13 @@ elf64_hppa_elf_get_symbol_type (elf_sym, return type; } -static struct bfd_elf_special_section const - hppa_special_sections_f[]= +static const struct bfd_elf_special_section elf64_hppa_special_sections[] = { { ".fini", 5, 0, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - hppa_special_sections_i[]= -{ { ".init", 5, 0, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, { NULL, 0, 0, 0, 0 } }; -static struct bfd_elf_special_section const * - elf64_hppa_special_sections[27] = -{ - NULL, /* 'a' */ - NULL, /* 'b' */ - NULL, /* 'c' */ - NULL, /* 'd' */ - NULL, /* 'e' */ - hppa_special_sections_f, /* 'f' */ - NULL, /* 'g' */ - NULL, /* 'h' */ - hppa_special_sections_i, /* 'i' */ - NULL, /* 'j' */ - NULL, /* 'k' */ - NULL, /* 'l' */ - NULL, /* 'm' */ - NULL, /* 'n' */ - NULL, /* 'o' */ - NULL, /* 'f' */ - NULL, /* 'q' */ - NULL, /* 'r' */ - NULL, /* 's' */ - NULL, /* 't' */ - NULL, /* 'u' */ - NULL, /* 'v' */ - NULL, /* 'w' */ - NULL, /* 'x' */ - NULL, /* 'y' */ - NULL, /* 'z' */ - NULL /* other */ -}; - /* The hash bucket size is the standard one, namely 4. */ const struct elf_size_info hppa64_elf_size_info = diff -uprN binutils-2.16.91.0.1/bfd/elf64-ppc.c binutils-2.16.91.0.2/bfd/elf64-ppc.c --- binutils-2.16.91.0.1/bfd/elf64-ppc.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf64-ppc.c 2005-07-20 12:27:27.356182656 -0700 @@ -2117,8 +2117,13 @@ ppc64_elf_info_to_howto (bfd *abfd ATTRI ppc_howto_init (); type = ELF64_R_TYPE (dst->r_info); - BFD_ASSERT (type < (sizeof (ppc64_elf_howto_table) - / sizeof (ppc64_elf_howto_table[0]))); + if (type >= (sizeof (ppc64_elf_howto_table) + / sizeof (ppc64_elf_howto_table[0]))) + { + (*_bfd_error_handler) (_("%B: invalid relocation type %d"), + abfd, (int) type); + type = R_PPC64_NONE; + } cache_ptr->howto = ppc64_elf_howto_table[type]; } @@ -2508,62 +2513,17 @@ ppc64_elf_merge_private_bfd_data (bfd *i /* Add extra PPC sections. */ -static struct bfd_elf_special_section const - ppc64_special_sections_p[]= +static const struct bfd_elf_special_section ppc64_elf_special_sections[]= { { ".plt", 4, 0, SHT_NOBITS, 0 }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - ppc64_special_sections_s[]= -{ - { ".sdata", 6, -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, { ".sbss", 5, -2, SHT_NOBITS, SHF_ALLOC + SHF_WRITE }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - ppc64_special_sections_t[]= -{ + { ".sdata", 6, -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, { ".toc", 4, 0, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, { ".toc1", 5, 0, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, { ".tocbss", 7, 0, SHT_NOBITS, SHF_ALLOC + SHF_WRITE }, { NULL, 0, 0, 0, 0 } }; -static struct bfd_elf_special_section const * - ppc64_elf_special_sections[27]= -{ - NULL, /* 'a' */ - NULL, /* 'b' */ - NULL, /* 'c' */ - NULL, /* 'd' */ - NULL, /* 'e' */ - NULL, /* 'f' */ - NULL, /* 'g' */ - NULL, /* 'h' */ - NULL, /* 'i' */ - NULL, /* 'j' */ - NULL, /* 'k' */ - NULL, /* 'l' */ - NULL, /* 'm' */ - NULL, /* 'n' */ - NULL, /* 'o' */ - ppc64_special_sections_p, /* 'p' */ - NULL, /* 'q' */ - NULL, /* 'r' */ - ppc64_special_sections_s, /* 's' */ - ppc64_special_sections_t, /* 't' */ - NULL, /* 'u' */ - NULL, /* 'v' */ - NULL, /* 'w' */ - NULL, /* 'x' */ - NULL, /* 'y' */ - NULL, /* 'z' */ - NULL /* other */ -}; - struct _ppc64_elf_section_data { struct bfd_elf_section_data elf; @@ -3235,7 +3195,7 @@ struct ppc_branch_hash_entry { /* Base hash table entry structure. */ struct bfd_hash_entry root; - /* Offset within .branch_lt. */ + /* Offset within branch lookup table. */ unsigned int offset; /* Generation marker. */ @@ -3733,26 +3693,50 @@ create_linkage_sections (bfd *dynobj, st || ! bfd_set_section_alignment (dynobj, htab->glink, 2)) return FALSE; - /* Create .branch_lt for plt_branch stubs. */ - flags = (SEC_ALLOC | SEC_LOAD - | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED); - htab->brlt = bfd_make_section_anyway_with_flags (dynobj, ".branch_lt", - flags); + /* Create branch lookup table for plt_branch stubs. */ + if (info->shared) + { + flags = (SEC_ALLOC | SEC_LOAD + | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED); + htab->brlt + = bfd_make_section_anyway_with_flags (dynobj, ".data.rel.ro.brlt", + flags); + } + else + { + flags = (SEC_ALLOC | SEC_LOAD | SEC_READONLY + | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED); + htab->brlt + = bfd_make_section_anyway_with_flags (dynobj, ".rodata.brlt", flags); + } + if (htab->brlt == NULL || ! bfd_set_section_alignment (dynobj, htab->brlt, 3)) return FALSE; - if (info->shared || info->emitrelocations) + if (info->shared) { flags = (SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED); - htab->relbrlt = bfd_make_section_anyway_with_flags (dynobj, - ".rela.branch_lt", - flags); - if (!htab->relbrlt - || ! bfd_set_section_alignment (dynobj, htab->relbrlt, 3)) - return FALSE; + htab->relbrlt + = bfd_make_section_anyway_with_flags (dynobj, ".rela.data.rel.ro.brlt", + flags); + } + else if (info->emitrelocations) + { + flags = (SEC_ALLOC | SEC_LOAD | SEC_READONLY + | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED); + htab->relbrlt + = bfd_make_section_anyway_with_flags (dynobj, ".rela.rodata.brlt", + flags); } + else + return TRUE; + + if (!htab->relbrlt + || ! bfd_set_section_alignment (dynobj, htab->relbrlt, 3)) + return FALSE; + return TRUE; } @@ -3779,13 +3763,13 @@ create_got_section (bfd *abfd, struct bf flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED); - got = bfd_make_section_with_flags (abfd, ".got", flags); + got = bfd_make_section_anyway_with_flags (abfd, ".got", flags); if (!got || !bfd_set_section_alignment (abfd, got, 3)) return FALSE; - relgot = bfd_make_section_with_flags (abfd, ".rela.got", - flags | SEC_READONLY); + relgot = bfd_make_section_anyway_with_flags (abfd, ".rela.got", + flags | SEC_READONLY); if (!relgot || ! bfd_set_section_alignment (abfd, relgot, 3)) return FALSE; @@ -7736,26 +7720,15 @@ ppc64_elf_size_dynamic_sections (bfd *ou continue; else if (s == htab->got || s == htab->plt - || s == htab->glink) + || s == htab->glink + || s == htab->dynbss) { /* Strip this section if we don't need it; see the comment below. */ } else if (strncmp (bfd_get_section_name (dynobj, s), ".rela", 5) == 0) { - if (s->size == 0) - { - /* If we don't need this section, strip it from the - output file. This is mostly to handle .rela.bss and - .rela.plt. We must create both sections in - create_dynamic_sections, because they must be created - before the linker maps input sections to output - sections. The linker does that before - adjust_dynamic_symbol is called, and it is that - function which decides whether anything needs to go - into these sections. */ - } - else + if (s->size != 0) { if (s != htab->relplt) relocs = TRUE; @@ -7773,12 +7746,20 @@ ppc64_elf_size_dynamic_sections (bfd *ou if (s->size == 0) { + /* If we don't need this section, strip it from the + output file. This is mostly to handle .rela.bss and + .rela.plt. We must create both sections in + create_dynamic_sections, because they must be created + before the linker maps input sections to output + sections. The linker does that before + adjust_dynamic_symbol is called, and it is that + function which decides whether anything needs to go + into these sections. */ s->flags |= SEC_EXCLUDE; continue; } - /* .plt is in the bss section. We don't initialise it. */ - if (s == htab->plt) + if ((s->flags & SEC_HAS_CONTENTS) == 0) continue; /* Allocate memory for the section contents. We use bfd_zalloc @@ -9160,7 +9141,7 @@ ppc64_elf_size_stubs (bfd *output_bfd, (*htab->layout_sections_again) (); } - /* It would be nice to strip .branch_lt from the output if the + /* It would be nice to strip htab->brlt from the output if the section is empty, but it's too late. If we strip sections here, the dynamic symbol table is corrupted since the section symbol for the stripped section isn't written. */ @@ -10017,6 +9998,8 @@ ppc64_elf_relocate_section (bfd *output_ br = bfd_get_32 (input_bfd, contents + rel->r_offset); if ((br & 1) == 0) can_plt_call = TRUE; + else + stub_entry = NULL; } else if (h != NULL && strcmp (h->elf.root.root.string, diff -uprN binutils-2.16.91.0.1/bfd/elf64-s390.c binutils-2.16.91.0.2/bfd/elf64-s390.c --- binutils-2.16.91.0.1/bfd/elf64-s390.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf64-s390.c 2005-07-20 12:27:27.360181997 -0700 @@ -373,7 +373,8 @@ elf_s390_info_to_howto (abfd, cache_ptr, arelent *cache_ptr; Elf_Internal_Rela *dst; { - switch (ELF64_R_TYPE(dst->r_info)) + unsigned int r_type = ELF64_R_TYPE(dst->r_info); + switch (r_type) { case R_390_GNU_VTINHERIT: cache_ptr->howto = &elf64_s390_vtinherit_howto; @@ -384,8 +385,13 @@ elf_s390_info_to_howto (abfd, cache_ptr, break; default: - BFD_ASSERT (ELF64_R_TYPE(dst->r_info) < (unsigned int) R_390_max); - cache_ptr->howto = &elf_howto_table[ELF64_R_TYPE(dst->r_info)]; + if (r_type >= sizeof (elf_howto_table) / sizeof (elf_howto_table[0])) + { + (*_bfd_error_handler) (_("%B: invalid relocation type %d"), + abfd, (int) r_type); + r_type = R_390_NONE; + } + cache_ptr->howto = &elf_howto_table[r_type]; } } @@ -2070,7 +2076,8 @@ elf_s390_size_dynamic_sections (output_b if (s == htab->splt || s == htab->sgot - || s == htab->sgotplt) + || s == htab->sgotplt + || s == htab->sdynbss) { /* Strip this section if we don't need it; see the comment below. */ @@ -2106,6 +2113,9 @@ elf_s390_size_dynamic_sections (output_b continue; } + if ((s->flags & SEC_HAS_CONTENTS) == 0) + continue; + /* Allocate memory for the section contents. We use bfd_zalloc here in case unused entries are not reclaimed before the section's contents are written out. This should not happen, diff -uprN binutils-2.16.91.0.1/bfd/elf64-sh64.c binutils-2.16.91.0.2/bfd/elf64-sh64.c --- binutils-2.16.91.0.1/bfd/elf64-sh64.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf64-sh64.c 2005-07-20 12:27:27.370180348 -0700 @@ -3566,7 +3566,6 @@ sh64_elf64_size_dynamic_sections (bfd *o for (s = dynobj->sections; s != NULL; s = s->next) { const char *name; - bfd_boolean strip; if ((s->flags & SEC_LINKER_CREATED) == 0) continue; @@ -3575,38 +3574,14 @@ sh64_elf64_size_dynamic_sections (bfd *o of the dynobj section names depend upon the input files. */ name = bfd_get_section_name (dynobj, s); - strip = FALSE; - if (strcmp (name, ".plt") == 0) { - if (s->size == 0) - { - /* Strip this section if we don't need it; see the - comment below. */ - strip = TRUE; - } - else - { - /* Remember whether there is a PLT. */ - plt = TRUE; - } + /* Remember whether there is a PLT. */ + plt = s->size != 0; } else if (strncmp (name, ".rela", 5) == 0) { - if (s->size == 0) - { - /* If we don't need this section, strip it from the - output file. This is mostly to handle .rela.bss and - .rela.plt. We must create both sections in - create_dynamic_sections, because they must be created - before the linker maps input sections to output - sections. The linker does that before - adjust_dynamic_symbol is called, and it is that - function which decides whether anything needs to go - into these sections. */ - strip = TRUE; - } - else + if (s->size != 0) { asection *target; @@ -3637,21 +3612,34 @@ sh64_elf64_size_dynamic_sections (bfd *o s->reloc_count = 0; } } - else if (strncmp (name, ".got", 4) != 0) + else if (strncmp (name, ".got", 4) != 0 + && strcmp (name, ".dynbss") != 0) { /* It's not one of our sections, so don't allocate space. */ continue; } - if (strip) + if (s->size == 0) { + /* If we don't need this section, strip it from the + output file. This is mostly to handle .rela.bss and + .rela.plt. We must create both sections in + create_dynamic_sections, because they must be created + before the linker maps input sections to output + sections. The linker does that before + adjust_dynamic_symbol is called, and it is that + function which decides whether anything needs to go + into these sections. */ s->flags |= SEC_EXCLUDE; continue; } + if ((s->flags & SEC_HAS_CONTENTS) == 0) + continue; + /* Allocate memory for the section contents. */ s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); - if (s->contents == NULL && s->size != 0) + if (s->contents == NULL) return FALSE; } @@ -4068,43 +4056,10 @@ sh64_elf64_merge_symbol_attribute (struc return; } -static struct bfd_elf_special_section const - sh64_special_sections_c[] = +static const struct bfd_elf_special_section sh64_elf64_special_sections[]= { { ".cranges", 8, 0, SHT_PROGBITS, 0 }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const * - sh64_elf64_special_sections[27]= -{ - NULL, /* 'a' */ - NULL, /* 'b' */ - sh64_special_sections_c, /* 'c' */ - NULL, /* 'd' */ - NULL, /* 'e' */ - NULL, /* 'f' */ - NULL, /* 'g' */ - NULL, /* 'h' */ - NULL, /* 'i' */ - NULL, /* 'j' */ - NULL, /* 'k' */ - NULL, /* 'l' */ - NULL, /* 'm' */ - NULL, /* 'n' */ - NULL, /* 'o' */ - NULL, /* 'p' */ - NULL, /* 'q' */ - NULL, /* 'r' */ - NULL, /* 's' */ - NULL, /* 't' */ - NULL, /* 'u' */ - NULL, /* 'v' */ - NULL, /* 'w' */ - NULL, /* 'x' */ - NULL, /* 'y' */ - NULL, /* 'z' */ - NULL /* other */ + { NULL, 0, 0, 0, 0 } }; #define TARGET_BIG_SYM bfd_elf64_sh64_vec diff -uprN binutils-2.16.91.0.1/bfd/elf64-x86-64.c binutils-2.16.91.0.2/bfd/elf64-x86-64.c --- binutils-2.16.91.0.1/bfd/elf64-x86-64.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf64-x86-64.c 2005-07-20 12:27:27.373179853 -0700 @@ -73,9 +73,9 @@ static reloc_howto_type x86_64_elf_howto FALSE), HOWTO(R_X86_64_16, 0, 1, 16, FALSE, 0, complain_overflow_bitfield, bfd_elf_generic_reloc, "R_X86_64_16", FALSE, 0xffff, 0xffff, FALSE), - HOWTO(R_X86_64_PC16,0, 1, 16, TRUE, 0, complain_overflow_bitfield, + HOWTO(R_X86_64_PC16,0, 1, 16, TRUE, 0, complain_overflow_signed, bfd_elf_generic_reloc, "R_X86_64_PC16", FALSE, 0xffff, 0xffff, TRUE), - HOWTO(R_X86_64_8, 0, 0, 8, FALSE, 0, complain_overflow_signed, + HOWTO(R_X86_64_8, 0, 0, 8, FALSE, 0, complain_overflow_bitfield, bfd_elf_generic_reloc, "R_X86_64_8", FALSE, 0xff, 0xff, FALSE), HOWTO(R_X86_64_PC8, 0, 0, 8, TRUE, 0, complain_overflow_signed, bfd_elf_generic_reloc, "R_X86_64_PC8", FALSE, 0xff, 0xff, TRUE), @@ -94,7 +94,7 @@ static reloc_howto_type x86_64_elf_howto HOWTO(R_X86_64_TLSLD, 0, 2, 32, TRUE, 0, complain_overflow_signed, bfd_elf_generic_reloc, "R_X86_64_TLSLD", FALSE, 0xffffffff, 0xffffffff, TRUE), - HOWTO(R_X86_64_DTPOFF32, 0, 2, 32, FALSE, 0, complain_overflow_bitfield, + HOWTO(R_X86_64_DTPOFF32, 0, 2, 32, FALSE, 0, complain_overflow_signed, bfd_elf_generic_reloc, "R_X86_64_DTPOFF32", FALSE, 0xffffffff, 0xffffffff, FALSE), HOWTO(R_X86_64_GOTTPOFF, 0, 2, 32, TRUE, 0, complain_overflow_signed, @@ -189,16 +189,19 @@ elf64_x86_64_info_to_howto (bfd *abfd AT unsigned r_type, i; r_type = ELF64_R_TYPE (dst->r_info); - if (r_type < (unsigned int) R_X86_64_GNU_VTINHERIT) + if (r_type < (unsigned int) R_X86_64_GNU_VTINHERIT + || r_type >= (unsigned int) R_X86_64_max) { - BFD_ASSERT (r_type <= (unsigned int) R_X86_64_GOTPC32); + if (r_type > (unsigned int) R_X86_64_GOTPC32) + { + (*_bfd_error_handler) (_("%B: invalid relocation type %d"), + abfd, (int) r_type); + r_type = R_X86_64_NONE; + } i = r_type; } else - { - BFD_ASSERT (r_type < (unsigned int) R_X86_64_max); - i = r_type - ((unsigned int) R_X86_64_GNU_VTINHERIT - R_X86_64_GOTPC32 - 1); - } + i = r_type - ((unsigned int) R_X86_64_GNU_VTINHERIT - R_X86_64_GOTPC32 - 1); cache_ptr->howto = &x86_64_elf_howto_table[i]; BFD_ASSERT (r_type == cache_ptr->howto->type); } @@ -1683,6 +1686,9 @@ elf64_x86_64_size_dynamic_sections (bfd continue; } + if ((s->flags & SEC_HAS_CONTENTS) == 0) + continue; + /* Allocate memory for the section contents. We use bfd_zalloc here in case unused entries are not reclaimed before the section's contents are written out. This should not happen, diff -uprN binutils-2.16.91.0.1/bfd/elf-bfd.h binutils-2.16.91.0.2/bfd/elf-bfd.h --- binutils-2.16.91.0.1/bfd/elf-bfd.h 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf-bfd.h 2005-07-20 12:27:27.058231788 -0700 @@ -633,11 +633,16 @@ struct elf_backend_data bfd_boolean (*elf_backend_section_from_shdr) (bfd *, Elf_Internal_Shdr *, const char *, int); - /* A function to convert machine dependent section header flags to + /* A function to convert machine dependent ELF section header flags to BFD internal section header flags. */ bfd_boolean (*elf_backend_section_flags) (flagword *, const Elf_Internal_Shdr *); + /* A function that returns a struct containing ELF section flags and + type for the given BFD section. */ + const struct bfd_elf_special_section * (*get_sec_type_attr) + (bfd *, asection *); + /* A function to handle unusual program segment types when creating BFD sections from ELF program segments. */ bfd_boolean (*elf_backend_section_from_phdr) @@ -976,9 +981,8 @@ struct elf_backend_data const struct elf_size_info *s; - /* An array of 27 target specific special section map arrays, - covering 'a' to 'z', plus other. */ - const struct bfd_elf_special_section **special_sections; + /* An array of target specific special sections. */ + const struct bfd_elf_special_section *special_sections; /* The size in bytes of the header for the GOT. This includes the so-called reserved entries on some systems. */ @@ -1501,8 +1505,10 @@ extern bfd_boolean _bfd_elf_new_section_ (bfd *, asection *); extern bfd_boolean _bfd_elf_init_reloc_shdr (bfd *, Elf_Internal_Shdr *, asection *, bfd_boolean); +extern const struct bfd_elf_special_section *_bfd_elf_get_special_section + (const char *, const struct bfd_elf_special_section *, unsigned int); extern const struct bfd_elf_special_section *_bfd_elf_get_sec_type_attr - (bfd *, const char *); + (bfd *, asection *); /* If the target doesn't have reloc handling written yet: */ extern void _bfd_elf_no_info_to_howto diff -uprN binutils-2.16.91.0.1/bfd/elf.c binutils-2.16.91.0.2/bfd/elf.c --- binutils-2.16.91.0.1/bfd/elf.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf.c 2005-07-20 12:27:27.088226842 -0700 @@ -206,28 +206,6 @@ bfd_elf_hash (const char *namearg) return h & 0xffffffff; } -/* Read a specified number of bytes at a specified offset in an ELF - file, into a newly allocated buffer, and return a pointer to the - buffer. */ - -static bfd_byte * -elf_read (bfd *abfd, file_ptr offset, bfd_size_type size) -{ - bfd_byte *buf; - - if ((buf = bfd_alloc (abfd, size)) == NULL) - return NULL; - if (bfd_seek (abfd, offset, SEEK_SET) != 0) - return NULL; - if (bfd_bread (buf, size, abfd) != size) - { - if (bfd_get_error () != bfd_error_system_call) - bfd_set_error (bfd_error_file_truncated); - return NULL; - } - return buf; -} - bfd_boolean bfd_elf_mkobject (bfd *abfd) { @@ -267,7 +245,21 @@ bfd_elf_get_str_section (bfd *abfd, unsi /* No cached one, attempt to read, and cache what we read. */ offset = i_shdrp[shindex]->sh_offset; shstrtabsize = i_shdrp[shindex]->sh_size; - shstrtab = elf_read (abfd, offset, shstrtabsize); + + /* Allocate and clear an extra byte at the end, to prevent crashes + in case the string table is not terminated. */ + if (shstrtabsize + 1 == 0 + || (shstrtab = bfd_alloc (abfd, shstrtabsize + 1)) == NULL + || bfd_seek (abfd, offset, SEEK_SET) != 0) + shstrtab = NULL; + else if (bfd_bread (shstrtab, shstrtabsize, abfd) != shstrtabsize) + { + if (bfd_get_error () != bfd_error_system_call) + bfd_set_error (bfd_error_file_truncated); + shstrtab = NULL; + } + else + shstrtab[shstrtabsize] = '\0'; i_shdrp[shindex]->contents = shstrtab; } return (char *) shstrtab; @@ -348,7 +340,7 @@ bfd_elf_get_elf_syms (bfd *ibfd, pos = symtab_hdr->sh_offset + symoffset * extsym_size; if (extsym_buf == NULL) { - alloc_ext = bfd_malloc (amt); + alloc_ext = bfd_malloc2 (symcount, extsym_size); extsym_buf = alloc_ext; } if (extsym_buf == NULL @@ -367,7 +359,8 @@ bfd_elf_get_elf_syms (bfd *ibfd, pos = shndx_hdr->sh_offset + symoffset * sizeof (Elf_External_Sym_Shndx); if (extshndx_buf == NULL) { - alloc_extshndx = bfd_malloc (amt); + alloc_extshndx = bfd_malloc2 (symcount, + sizeof (Elf_External_Sym_Shndx)); extshndx_buf = alloc_extshndx; } if (extshndx_buf == NULL @@ -381,8 +374,7 @@ bfd_elf_get_elf_syms (bfd *ibfd, if (intsym_buf == NULL) { - bfd_size_type amt = symcount * sizeof (Elf_Internal_Sym); - intsym_buf = bfd_malloc (amt); + intsym_buf = bfd_malloc2 (symcount, sizeof (Elf_Internal_Sym)); if (intsym_buf == NULL) goto out; } @@ -502,10 +494,10 @@ setup_group (bfd *abfd, Elf_Internal_Shd /* We keep a list of elf section headers for group sections, so we can find them quickly. */ bfd_size_type amt; - + elf_tdata (abfd)->num_group = num_group; - amt = num_group * sizeof (Elf_Internal_Shdr *); - elf_tdata (abfd)->group_sect_ptr = bfd_alloc (abfd, amt); + elf_tdata (abfd)->group_sect_ptr + = bfd_alloc2 (abfd, num_group, sizeof (Elf_Internal_Shdr *)); if (elf_tdata (abfd)->group_sect_ptr == NULL) return FALSE; @@ -525,7 +517,8 @@ setup_group (bfd *abfd, Elf_Internal_Shd /* Read the raw contents. */ BFD_ASSERT (sizeof (*dest) >= 4); amt = shdr->sh_size * sizeof (*dest) / 4; - shdr->contents = bfd_alloc (abfd, amt); + shdr->contents = bfd_alloc2 (abfd, shdr->sh_size, + sizeof (*dest) / 4); if (shdr->contents == NULL || bfd_seek (abfd, shdr->sh_offset, SEEK_SET) != 0 || (bfd_bread (shdr->contents, shdr->sh_size, abfd) @@ -1227,8 +1220,9 @@ _bfd_elf_print_private_bfd_data (bfd *ab for (t = elf_tdata (abfd)->verdef; t != NULL; t = t->vd_nextdef) { fprintf (f, "%d 0x%2.2x 0x%8.8lx %s\n", t->vd_ndx, - t->vd_flags, t->vd_hash, t->vd_nodename); - if (t->vd_auxptr->vda_nextptr != NULL) + t->vd_flags, t->vd_hash, + t->vd_nodename ? t->vd_nodename : ""); + if (t->vd_auxptr != NULL && t->vd_auxptr->vda_nextptr != NULL) { Elf_Internal_Verdaux *a; @@ -1236,7 +1230,8 @@ _bfd_elf_print_private_bfd_data (bfd *ab for (a = t->vd_auxptr->vda_nextptr; a != NULL; a = a->vda_nextptr) - fprintf (f, "%s ", a->vda_nodename); + fprintf (f, "%s ", + a->vda_nodename ? a->vda_nodename : ""); fprintf (f, "\n"); } } @@ -1251,10 +1246,12 @@ _bfd_elf_print_private_bfd_data (bfd *ab { Elf_Internal_Vernaux *a; - fprintf (f, _(" required from %s:\n"), t->vn_filename); + fprintf (f, _(" required from %s:\n"), + t->vn_filename ? t->vn_filename : ""); for (a = t->vn_auxptr; a != NULL; a = a->vna_nextptr) fprintf (f, " 0x%8.8lx 0x%2.2x %2.2d %s\n", a->vna_hash, - a->vna_flags, a->vna_other, a->vna_nodename); + a->vna_flags, a->vna_other, + a->vna_nodename ? a->vna_nodename : ""); } } @@ -2164,19 +2161,19 @@ bfd_section_from_elf_index (bfd *abfd, u return elf_elfsections (abfd)[index]->bfd_section; } -static struct bfd_elf_special_section const special_sections_b[] = +static const struct bfd_elf_special_section special_sections_b[] = { { ".bss", 4, -2, SHT_NOBITS, SHF_ALLOC + SHF_WRITE }, { NULL, 0, 0, 0, 0 } }; -static struct bfd_elf_special_section const special_sections_c[] = +static const struct bfd_elf_special_section special_sections_c[] = { { ".comment", 8, 0, SHT_PROGBITS, 0 }, { NULL, 0, 0, 0, 0 } }; -static struct bfd_elf_special_section const special_sections_d[] = +static const struct bfd_elf_special_section special_sections_d[] = { { ".data", 5, -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, { ".data1", 6, 0, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, @@ -2191,14 +2188,14 @@ static struct bfd_elf_special_section co { NULL, 0, 0, 0, 0 } }; -static struct bfd_elf_special_section const special_sections_f[] = +static const struct bfd_elf_special_section special_sections_f[] = { { ".fini", 5, 0, SHT_PROGBITS, SHF_ALLOC + SHF_EXECINSTR }, { ".fini_array", 11, 0, SHT_FINI_ARRAY, SHF_ALLOC + SHF_WRITE }, { NULL, 0, 0, 0, 0 } }; -static struct bfd_elf_special_section const special_sections_g[] = +static const struct bfd_elf_special_section special_sections_g[] = { { ".gnu.linkonce.b",15, -2, SHT_NOBITS, SHF_ALLOC + SHF_WRITE }, { ".got", 4, 0, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, @@ -2210,13 +2207,13 @@ static struct bfd_elf_special_section co { NULL, 0, 0, 0, 0 } }; -static struct bfd_elf_special_section const special_sections_h[] = +static const struct bfd_elf_special_section special_sections_h[] = { { ".hash", 5, 0, SHT_HASH, SHF_ALLOC }, { NULL, 0, 0, 0, 0 } }; -static struct bfd_elf_special_section const special_sections_i[] = +static const struct bfd_elf_special_section special_sections_i[] = { { ".init", 5, 0, SHT_PROGBITS, SHF_ALLOC + SHF_EXECINSTR }, { ".init_array", 11, 0, SHT_INIT_ARRAY, SHF_ALLOC + SHF_WRITE }, @@ -2224,27 +2221,27 @@ static struct bfd_elf_special_section co { NULL, 0, 0, 0, 0 } }; -static struct bfd_elf_special_section const special_sections_l[] = +static const struct bfd_elf_special_section special_sections_l[] = { { ".line", 5, 0, SHT_PROGBITS, 0 }, { NULL, 0, 0, 0, 0 } }; -static struct bfd_elf_special_section const special_sections_n[] = +static const struct bfd_elf_special_section special_sections_n[] = { { ".note.GNU-stack",15, 0, SHT_PROGBITS, 0 }, { ".note", 5, -1, SHT_NOTE, 0 }, { NULL, 0, 0, 0, 0 } }; -static struct bfd_elf_special_section const special_sections_p[] = +static const struct bfd_elf_special_section special_sections_p[] = { { ".preinit_array", 14, 0, SHT_PREINIT_ARRAY, SHF_ALLOC + SHF_WRITE }, { ".plt", 4, 0, SHT_PROGBITS, SHF_ALLOC + SHF_EXECINSTR }, { NULL, 0, 0, 0, 0 } }; -static struct bfd_elf_special_section const special_sections_r[] = +static const struct bfd_elf_special_section special_sections_r[] = { { ".rodata", 7, -2, SHT_PROGBITS, SHF_ALLOC }, { ".rodata1", 8, 0, SHT_PROGBITS, SHF_ALLOC }, @@ -2253,7 +2250,7 @@ static struct bfd_elf_special_section co { NULL, 0, 0, 0, 0 } }; -static struct bfd_elf_special_section const special_sections_s[] = +static const struct bfd_elf_special_section special_sections_s[] = { { ".shstrtab", 9, 0, SHT_STRTAB, 0 }, { ".strtab", 7, 0, SHT_STRTAB, 0 }, @@ -2262,7 +2259,7 @@ static struct bfd_elf_special_section co { NULL, 0, 0, 0, 0 } }; -static struct bfd_elf_special_section const special_sections_t[] = +static const struct bfd_elf_special_section special_sections_t[] = { { ".text", 5, -2, SHT_PROGBITS, SHF_ALLOC + SHF_EXECINSTR }, { ".tbss", 5, -2, SHT_NOBITS, SHF_ALLOC + SHF_WRITE + SHF_TLS }, @@ -2270,9 +2267,8 @@ static struct bfd_elf_special_section co { NULL, 0, 0, 0, 0 } }; -static struct bfd_elf_special_section const *special_sections [27] = +static const struct bfd_elf_special_section *special_sections[] = { - NULL, /* 'a' */ special_sections_b, /* 'b' */ special_sections_c, /* 'b' */ special_sections_d, /* 'd' */ @@ -2292,51 +2288,29 @@ static struct bfd_elf_special_section co special_sections_r, /* 'r' */ special_sections_s, /* 's' */ special_sections_t, /* 't' */ - NULL, /* 'u' */ - NULL, /* 'v' */ - NULL, /* 'w' */ - NULL, /* 'x' */ - NULL, /* 'y' */ - NULL, /* 'z' */ - NULL /* other */ }; -static const struct bfd_elf_special_section * -get_special_section (const char *name, - const struct bfd_elf_special_section **special_sections_p, - unsigned int rela) +const struct bfd_elf_special_section * +_bfd_elf_get_special_section (const char *name, + const struct bfd_elf_special_section *spec, + unsigned int rela) { int i; int len; - const struct bfd_elf_special_section *special_sections; - - if (name [0] == '.') - { - i = name [1] - 'a'; - if (i < 0 || i > 25) - i = 26; - } - else - i = 26; - - special_sections = special_sections_p [i]; - if (!special_sections) - return special_sections; + len = strlen (name); - len= strlen (name); - - for (i = 0; special_sections[i].prefix != NULL; i++) + for (i = 0; spec[i].prefix != NULL; i++) { int suffix_len; - int prefix_len = special_sections[i].prefix_length; + int prefix_len = spec[i].prefix_length; if (len < prefix_len) continue; - if (memcmp (name, special_sections[i].prefix, prefix_len) != 0) + if (memcmp (name, spec[i].prefix, prefix_len) != 0) continue; - suffix_len = special_sections[i].suffix_length; + suffix_len = spec[i].suffix_length; if (suffix_len <= 0) { if (name[prefix_len] != 0) @@ -2345,7 +2319,7 @@ get_special_section (const char *name, continue; if (name[prefix_len] != '.' && (suffix_len == -2 - || (rela && special_sections[i].type == SHT_REL))) + || (rela && spec[i].type == SHT_REL))) continue; } } @@ -2354,41 +2328,58 @@ get_special_section (const char *name, if (len < prefix_len + suffix_len) continue; if (memcmp (name + len - suffix_len, - special_sections[i].prefix + prefix_len, + spec[i].prefix + prefix_len, suffix_len) != 0) continue; } - return &special_sections[i]; + return &spec[i]; } return NULL; } const struct bfd_elf_special_section * -_bfd_elf_get_sec_type_attr (bfd *abfd, const char *name) +_bfd_elf_get_sec_type_attr (bfd *abfd, asection *sec) { - const struct elf_backend_data *bed = get_elf_backend_data (abfd); - const struct bfd_elf_special_section *ssect = NULL; + int i; + const struct bfd_elf_special_section *spec; + const struct elf_backend_data *bed; /* See if this is one of the special sections. */ - if (name) + if (sec->name == NULL) + return NULL; + + bed = get_elf_backend_data (abfd); + spec = bed->special_sections; + if (spec) { - unsigned int rela = bed->default_use_rela_p; + spec = _bfd_elf_get_special_section (sec->name, + bed->special_sections, + sec->use_rela_p); + if (spec != NULL) + return spec; + } - if (bed->special_sections) - ssect = get_special_section (name, bed->special_sections, rela); + if (sec->name[0] != '.') + return NULL; - if (! ssect) - ssect = get_special_section (name, special_sections, rela); - } + i = sec->name[1] - 'b'; + if (i < 0 || i > 't' - 'b') + return NULL; + + spec = special_sections[i]; - return ssect; + if (spec == NULL) + return NULL; + + return _bfd_elf_get_special_section (sec->name, spec, sec->use_rela_p); } bfd_boolean _bfd_elf_new_section_hook (bfd *abfd, asection *sec) { struct bfd_elf_section_data *sdata; + const struct elf_backend_data *bed; const struct bfd_elf_special_section *ssect; sdata = (struct bfd_elf_section_data *) sec->used_by_bfd; @@ -2400,13 +2391,17 @@ _bfd_elf_new_section_hook (bfd *abfd, as sec->used_by_bfd = sdata; } + /* Indicate whether or not this section should use RELA relocations. */ + bed = get_elf_backend_data (abfd); + sec->use_rela_p = bed->default_use_rela_p; + /* When we read a file, we don't need section type and flags unless it is a linker created section. They will be overridden in _bfd_elf_make_section_from_shdr anyway. */ if (abfd->direction != read_direction || (sec->flags & SEC_LINKER_CREATED) != 0) { - ssect = _bfd_elf_get_sec_type_attr (abfd, sec->name); + ssect = (*bed->get_sec_type_attr) (abfd, sec); if (ssect != NULL) { elf_section_type (sec) = ssect->type; @@ -2414,9 +2409,6 @@ _bfd_elf_new_section_hook (bfd *abfd, as } } - /* Indicate whether or not this section should use RELA relocations. */ - sec->use_rela_p = get_elf_backend_data (abfd)->default_use_rela_p; - return TRUE; } @@ -2908,7 +2900,6 @@ assign_section_numbers (bfd *abfd, struc asection *sec; unsigned int section_number, secn; Elf_Internal_Shdr **i_shdrp; - bfd_size_type amt; struct bfd_elf_section_data *d; section_number = 1; @@ -3012,13 +3003,11 @@ assign_section_numbers (bfd *abfd, struc /* Set up the list of section header pointers, in agreement with the indices. */ - amt = section_number * sizeof (Elf_Internal_Shdr *); - i_shdrp = bfd_zalloc (abfd, amt); + i_shdrp = bfd_zalloc2 (abfd, section_number, sizeof (Elf_Internal_Shdr *)); if (i_shdrp == NULL) return FALSE; - amt = sizeof (Elf_Internal_Shdr); - i_shdrp[0] = bfd_zalloc (abfd, amt); + i_shdrp[0] = bfd_zalloc (abfd, sizeof (Elf_Internal_Shdr)); if (i_shdrp[0] == NULL) { bfd_release (abfd, i_shdrp); @@ -3269,7 +3258,6 @@ elf_map_symbols (bfd *abfd) unsigned int idx; asection *asect; asymbol **new_syms; - bfd_size_type amt; #ifdef DEBUG fprintf (stderr, "elf_map_symbols\n"); @@ -3283,8 +3271,7 @@ elf_map_symbols (bfd *abfd) } max_index++; - amt = max_index * sizeof (asymbol *); - sect_syms = bfd_zalloc (abfd, amt); + sect_syms = bfd_zalloc2 (abfd, max_index, sizeof (asymbol *)); if (sect_syms == NULL) return FALSE; elf_section_syms (abfd) = sect_syms; @@ -3357,8 +3344,7 @@ elf_map_symbols (bfd *abfd) } /* Now sort the symbols so the local symbols are first. */ - amt = (num_locals + num_globals) * sizeof (asymbol *); - new_syms = bfd_alloc (abfd, amt); + new_syms = bfd_alloc2 (abfd, num_locals + num_globals, sizeof (asymbol *)); if (new_syms == NULL) return FALSE; @@ -3617,8 +3603,7 @@ map_sections_to_segments (bfd *abfd) /* Select the allocated sections, and sort them. */ - amt = bfd_count_sections (abfd) * sizeof (asection *); - sections = bfd_malloc (amt); + sections = bfd_malloc2 (bfd_count_sections (abfd), sizeof (asection *)); if (sections == NULL) goto error_return; @@ -4050,7 +4035,6 @@ assign_file_positions_for_segments (bfd bfd_vma filehdr_vaddr, filehdr_paddr; bfd_vma phdrs_vaddr, phdrs_paddr; Elf_Internal_Phdr *p; - bfd_size_type amt; if (elf_tdata (abfd)->segment_map == NULL) { @@ -4061,7 +4045,8 @@ assign_file_positions_for_segments (bfd { /* The placement algorithm assumes that non allocated sections are not in PT_LOAD segments. We ensure this here by removing such - sections from the segment map. */ + sections from the segment map. We also remove excluded + sections. */ for (m = elf_tdata (abfd)->segment_map; m != NULL; m = m->next) @@ -4069,13 +4054,12 @@ assign_file_positions_for_segments (bfd unsigned int new_count; unsigned int i; - if (m->p_type != PT_LOAD) - continue; - new_count = 0; for (i = 0; i < m->count; i ++) { - if ((m->sections[i]->flags & SEC_ALLOC) != 0) + if ((m->sections[i]->flags & SEC_EXCLUDE) == 0 + && ((m->sections[i]->flags & SEC_ALLOC) != 0 + || m->p_type != PT_LOAD)) { if (i != new_count) m->sections[new_count] = m->sections[i]; @@ -4125,8 +4109,7 @@ assign_file_positions_for_segments (bfd if (alloc == 0) alloc = count; - amt = alloc * sizeof (Elf_Internal_Phdr); - phdrs = bfd_alloc (abfd, amt); + phdrs = bfd_alloc2 (abfd, alloc, sizeof (Elf_Internal_Phdr)); if (phdrs == NULL) return FALSE; @@ -5386,8 +5369,7 @@ copy_private_bfd_data (bfd *ibfd, bfd *o /* Gcc 2.96 miscompiles this code on mips. Don't do casting here to work around this long long bug. */ - amt = section_count * sizeof (asection *); - sections = bfd_malloc (amt); + sections = bfd_malloc2 (section_count, sizeof (asection *)); if (sections == NULL) return FALSE; @@ -5809,8 +5791,7 @@ swap_out_syms (bfd *abfd, symstrtab_hdr = &elf_tdata (abfd)->strtab_hdr; symstrtab_hdr->sh_type = SHT_STRTAB; - amt = (bfd_size_type) (1 + symcount) * bed->s->sizeof_sym; - outbound_syms = bfd_alloc (abfd, amt); + outbound_syms = bfd_alloc2 (abfd, 1 + symcount, bed->s->sizeof_sym); if (outbound_syms == NULL) { _bfd_stringtab_free (stt); @@ -5823,7 +5804,8 @@ swap_out_syms (bfd *abfd, if (symtab_shndx_hdr->sh_name != 0) { amt = (bfd_size_type) (1 + symcount) * sizeof (Elf_External_Sym_Shndx); - outbound_shndx = bfd_zalloc (abfd, amt); + outbound_shndx = bfd_zalloc2 (abfd, 1 + symcount, + sizeof (Elf_External_Sym_Shndx)); if (outbound_shndx == NULL) { _bfd_stringtab_free (stt); @@ -6236,7 +6218,6 @@ bfd_boolean _bfd_elf_slurp_version_tables (bfd *abfd, bfd_boolean default_imported_symver) { bfd_byte *contents = NULL; - bfd_size_type amt; unsigned int freeidx = 0; if (elf_dynverref (abfd) != 0) @@ -6245,11 +6226,12 @@ _bfd_elf_slurp_version_tables (bfd *abfd Elf_External_Verneed *everneed; Elf_Internal_Verneed *iverneed; unsigned int i; + bfd_byte *contents_end; hdr = &elf_tdata (abfd)->dynverref_hdr; - amt = (bfd_size_type) hdr->sh_info * sizeof (Elf_Internal_Verneed); - elf_tdata (abfd)->verref = bfd_zalloc (abfd, amt); + elf_tdata (abfd)->verref = bfd_zalloc2 (abfd, hdr->sh_info, + sizeof (Elf_Internal_Verneed)); if (elf_tdata (abfd)->verref == NULL) goto error_return; @@ -6257,11 +6239,22 @@ _bfd_elf_slurp_version_tables (bfd *abfd contents = bfd_malloc (hdr->sh_size); if (contents == NULL) - goto error_return; + { +error_return_verref: + elf_tdata (abfd)->verref = NULL; + elf_tdata (abfd)->cverrefs = 0; + goto error_return; + } if (bfd_seek (abfd, hdr->sh_offset, SEEK_SET) != 0 || bfd_bread (contents, hdr->sh_size, abfd) != hdr->sh_size) - goto error_return; + goto error_return_verref; + if (hdr->sh_info && hdr->sh_size < sizeof (Elf_External_Verneed)) + goto error_return_verref; + + BFD_ASSERT (sizeof (Elf_External_Verneed) + == sizeof (Elf_External_Vernaux)); + contents_end = contents + hdr->sh_size - sizeof (Elf_External_Verneed); everneed = (Elf_External_Verneed *) contents; iverneed = elf_tdata (abfd)->verref; for (i = 0; i < hdr->sh_info; i++, iverneed++) @@ -6278,11 +6271,21 @@ _bfd_elf_slurp_version_tables (bfd *abfd bfd_elf_string_from_elf_section (abfd, hdr->sh_link, iverneed->vn_file); if (iverneed->vn_filename == NULL) - goto error_return; + goto error_return_verref; - amt = iverneed->vn_cnt; - amt *= sizeof (Elf_Internal_Vernaux); - iverneed->vn_auxptr = bfd_alloc (abfd, amt); + if (iverneed->vn_cnt == 0) + iverneed->vn_auxptr = NULL; + else + { + iverneed->vn_auxptr = bfd_alloc2 (abfd, iverneed->vn_cnt, + sizeof (Elf_Internal_Vernaux)); + if (iverneed->vn_auxptr == NULL) + goto error_return_verref; + } + + if (iverneed->vn_aux + > (size_t) (contents_end - (bfd_byte *) everneed)) + goto error_return_verref; evernaux = ((Elf_External_Vernaux *) ((bfd_byte *) everneed + iverneed->vn_aux)); @@ -6295,13 +6298,17 @@ _bfd_elf_slurp_version_tables (bfd *abfd bfd_elf_string_from_elf_section (abfd, hdr->sh_link, ivernaux->vna_name); if (ivernaux->vna_nodename == NULL) - goto error_return; + goto error_return_verref; if (j + 1 < iverneed->vn_cnt) ivernaux->vna_nextptr = ivernaux + 1; else ivernaux->vna_nextptr = NULL; + if (ivernaux->vna_next + > (size_t) (contents_end - (bfd_byte *) evernaux)) + goto error_return_verref; + evernaux = ((Elf_External_Vernaux *) ((bfd_byte *) evernaux + ivernaux->vna_next)); @@ -6314,6 +6321,10 @@ _bfd_elf_slurp_version_tables (bfd *abfd else iverneed->vn_nextref = NULL; + if (iverneed->vn_next + > (size_t) (contents_end - (bfd_byte *) everneed)) + goto error_return_verref; + everneed = ((Elf_External_Verneed *) ((bfd_byte *) everneed + iverneed->vn_next)); } @@ -6331,6 +6342,7 @@ _bfd_elf_slurp_version_tables (bfd *abfd Elf_Internal_Verdef iverdefmem; unsigned int i; unsigned int maxidx; + bfd_byte *contents_end_def, *contents_end_aux; hdr = &elf_tdata (abfd)->dynverdef_hdr; @@ -6341,6 +6353,16 @@ _bfd_elf_slurp_version_tables (bfd *abfd || bfd_bread (contents, hdr->sh_size, abfd) != hdr->sh_size) goto error_return; + if (hdr->sh_info && hdr->sh_size < sizeof (Elf_External_Verdef)) + goto error_return; + + BFD_ASSERT (sizeof (Elf_External_Verdef) + >= sizeof (Elf_External_Verdaux)); + contents_end_def = contents + hdr->sh_size + - sizeof (Elf_External_Verdef); + contents_end_aux = contents + hdr->sh_size + - sizeof (Elf_External_Verdaux); + /* We know the number of entries in the section but not the maximum index. Therefore we have to run through all entries and find the maximum. */ @@ -6353,6 +6375,10 @@ _bfd_elf_slurp_version_tables (bfd *abfd if ((iverdefmem.vd_ndx & ((unsigned) VERSYM_VERSION)) > maxidx) maxidx = iverdefmem.vd_ndx & ((unsigned) VERSYM_VERSION); + if (iverdefmem.vd_next + > (size_t) (contents_end_def - (bfd_byte *) everdef)) + goto error_return; + everdef = ((Elf_External_Verdef *) ((bfd_byte *) everdef + iverdefmem.vd_next)); } @@ -6364,8 +6390,8 @@ _bfd_elf_slurp_version_tables (bfd *abfd else freeidx = ++maxidx; } - amt = (bfd_size_type) maxidx * sizeof (Elf_Internal_Verdef); - elf_tdata (abfd)->verdef = bfd_zalloc (abfd, amt); + elf_tdata (abfd)->verdef = bfd_zalloc2 (abfd, maxidx, + sizeof (Elf_Internal_Verdef)); if (elf_tdata (abfd)->verdef == NULL) goto error_return; @@ -6381,15 +6407,32 @@ _bfd_elf_slurp_version_tables (bfd *abfd _bfd_elf_swap_verdef_in (abfd, everdef, &iverdefmem); + if ((iverdefmem.vd_ndx & VERSYM_VERSION) == 0) + { +error_return_verdef: + elf_tdata (abfd)->verdef = NULL; + elf_tdata (abfd)->cverdefs = 0; + goto error_return; + } + iverdef = &iverdefarr[(iverdefmem.vd_ndx & VERSYM_VERSION) - 1]; memcpy (iverdef, &iverdefmem, sizeof (Elf_Internal_Verdef)); iverdef->vd_bfd = abfd; - amt = (bfd_size_type) iverdef->vd_cnt * sizeof (Elf_Internal_Verdaux); - iverdef->vd_auxptr = bfd_alloc (abfd, amt); - if (iverdef->vd_auxptr == NULL) - goto error_return; + if (iverdef->vd_cnt == 0) + iverdef->vd_auxptr = NULL; + else + { + iverdef->vd_auxptr = bfd_alloc2 (abfd, iverdef->vd_cnt, + sizeof (Elf_Internal_Verdaux)); + if (iverdef->vd_auxptr == NULL) + goto error_return_verdef; + } + + if (iverdef->vd_aux + > (size_t) (contents_end_aux - (bfd_byte *) everdef)) + goto error_return_verdef; everdaux = ((Elf_External_Verdaux *) ((bfd_byte *) everdef + iverdef->vd_aux)); @@ -6402,20 +6445,25 @@ _bfd_elf_slurp_version_tables (bfd *abfd bfd_elf_string_from_elf_section (abfd, hdr->sh_link, iverdaux->vda_name); if (iverdaux->vda_nodename == NULL) - goto error_return; + goto error_return_verdef; if (j + 1 < iverdef->vd_cnt) iverdaux->vda_nextptr = iverdaux + 1; else iverdaux->vda_nextptr = NULL; + if (iverdaux->vda_next + > (size_t) (contents_end_aux - (bfd_byte *) everdaux)) + goto error_return_verdef; + everdaux = ((Elf_External_Verdaux *) ((bfd_byte *) everdaux + iverdaux->vda_next)); } - iverdef->vd_nodename = iverdef->vd_auxptr->vda_nodename; + if (iverdef->vd_cnt) + iverdef->vd_nodename = iverdef->vd_auxptr->vda_nodename; - if (i + 1 < hdr->sh_info) + if ((size_t) (iverdef - iverdefarr) + 1 < maxidx) iverdef->vd_nextdef = iverdef + 1; else iverdef->vd_nextdef = NULL; @@ -6434,8 +6482,8 @@ _bfd_elf_slurp_version_tables (bfd *abfd else freeidx++; - amt = (bfd_size_type) freeidx * sizeof (Elf_Internal_Verdef); - elf_tdata (abfd)->verdef = bfd_zalloc (abfd, amt); + elf_tdata (abfd)->verdef = bfd_zalloc2 (abfd, freeidx, + sizeof (Elf_Internal_Verdef)); if (elf_tdata (abfd)->verdef == NULL) goto error_return; @@ -6459,10 +6507,11 @@ _bfd_elf_slurp_version_tables (bfd *abfd iverdef->vd_nodename = bfd_elf_get_dt_soname (abfd); if (iverdef->vd_nodename == NULL) - goto error_return; + goto error_return_verdef; iverdef->vd_nextdef = NULL; - amt = (bfd_size_type) sizeof (Elf_Internal_Verdaux); - iverdef->vd_auxptr = bfd_alloc (abfd, amt); + iverdef->vd_auxptr = bfd_alloc (abfd, sizeof (Elf_Internal_Verdaux)); + if (iverdef->vd_auxptr == NULL) + goto error_return_verdef; iverdaux = iverdef->vd_auxptr; iverdaux->vda_nodename = iverdef->vd_nodename; diff -uprN binutils-2.16.91.0.1/bfd/elf-hppa.h binutils-2.16.91.0.2/bfd/elf-hppa.h --- binutils-2.16.91.0.1/bfd/elf-hppa.h 2005-05-10 15:46:41.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf-hppa.h 2005-07-20 12:27:27.066230469 -0700 @@ -1259,9 +1259,9 @@ elf_hppa_final_link (bfd *abfd, struct b if (!sec || (sec->flags & SEC_EXCLUDE)) sec = bfd_get_section_by_name (abfd, ".data"); if (!sec || (sec->flags & SEC_EXCLUDE)) - return FALSE; - - gp_val = sec->output_offset + sec->output_section->vma; + gp_val = 0; + else + gp_val = sec->output_offset + sec->output_section->vma; } } diff -uprN binutils-2.16.91.0.1/bfd/elflink.c binutils-2.16.91.0.2/bfd/elflink.c --- binutils-2.16.91.0.1/bfd/elflink.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elflink.c 2005-07-20 12:27:27.391176886 -0700 @@ -433,8 +433,7 @@ bfd_elf_link_record_dynamic_symbol (stru this in case some dynamic object refers to this symbol. */ bfd_boolean -bfd_elf_record_link_assignment (bfd *output_bfd ATTRIBUTE_UNUSED, - struct bfd_link_info *info, +bfd_elf_record_link_assignment (struct bfd_link_info *info, const char *name, bfd_boolean provide) { @@ -3688,11 +3687,12 @@ elf_link_add_object_symbols (bfd *abfd, /* If this is a hidden symbol, or if it is not version 1, we append the version name to the symbol name. - However, we do not modify a non-hidden absolute - symbol, because it might be the version symbol - itself. FIXME: What if it isn't? */ + However, we do not modify a non-hidden absolute symbol + if it is not a function, because it might be the version + symbol itself. FIXME: What if it isn't? */ if ((iver.vs_vers & VERSYM_HIDDEN) != 0 - || (vernum > 1 && ! bfd_is_abs_section (sec))) + || (vernum > 1 && (! bfd_is_abs_section (sec) + || ELF_ST_TYPE (isym->st_info) == STT_FUNC))) { const char *verstr; size_t namelen, verlen, newlen; @@ -8733,6 +8733,7 @@ _bfd_elf_gc_mark (struct bfd_link_info * gc_mark_hook_fn gc_mark_hook) { bfd_boolean ret; + bfd_boolean is_eh; asection *group_sec; sec->gc_mark = 1; @@ -8745,6 +8746,7 @@ _bfd_elf_gc_mark (struct bfd_link_info * /* Look through the section relocs. */ ret = TRUE; + is_eh = strcmp (sec->name, ".eh_frame") == 0; if ((sec->flags & SEC_RELOC) != 0 && sec->reloc_count > 0) { Elf_Internal_Rela *relstart, *rel, *relend; @@ -8821,6 +8823,8 @@ _bfd_elf_gc_mark (struct bfd_link_info * { if (bfd_get_flavour (rsec->owner) != bfd_target_elf_flavour) rsec->gc_mark = 1; + else if (is_eh) + rsec->gc_mark_from_eh = 1; else if (!_bfd_elf_gc_mark (info, rsec, gc_mark_hook)) { ret = FALSE; @@ -8891,6 +8895,41 @@ elf_gc_sweep (struct bfd_link_info *info if (o->gc_mark) continue; + /* Keep .gcc_except_table.* if the associated .text.* is + marked. This isn't very nice, but the proper solution, + splitting .eh_frame up and using comdat doesn't pan out + easily due to needing special relocs to handle the + difference of two symbols in separate sections. + Don't keep code sections referenced by .eh_frame. */ + if (o->gc_mark_from_eh && (o->flags & SEC_CODE) == 0) + { + if (strncmp (o->name, ".gcc_except_table.", 18) == 0) + { + unsigned long len; + char *fn_name; + asection *fn_text; + + len = strlen (o->name + 18) + 1; + fn_name = bfd_malloc (len + 6); + if (fn_name == NULL) + return FALSE; + memcpy (fn_name, ".text.", 6); + memcpy (fn_name + 6, o->name + 18, len); + fn_text = bfd_get_section_by_name (sub, fn_name); + free (fn_name); + if (fn_text != NULL && fn_text->gc_mark) + o->gc_mark = 1; + } + + /* If not using specially named exception table section, + then keep whatever we are using. */ + else + o->gc_mark = 1; + + if (o->gc_mark) + continue; + } + /* Skip sweeping sections already excluded. */ if (o->flags & SEC_EXCLUDE) continue; @@ -8902,7 +8941,9 @@ elf_gc_sweep (struct bfd_link_info *info /* But we also have to update some of the relocation info we collected before. */ if (gc_sweep_hook - && (o->flags & SEC_RELOC) && o->reloc_count > 0) + && (o->flags & SEC_RELOC) != 0 + && o->reloc_count > 0 + && !bfd_is_abs_section (o->output_section)) { Elf_Internal_Rela *internal_relocs; bfd_boolean r; @@ -9078,9 +9119,6 @@ bfd_elf_gc_sections (bfd *abfd, struct b (asection *, struct bfd_link_info *, Elf_Internal_Rela *, struct elf_link_hash_entry *h, Elf_Internal_Sym *); - if (!info->gc_sections) - return bfd_generic_gc_sections (abfd, info); - if (!get_elf_backend_data (abfd)->can_gc_sections || info->relocatable || info->emitrelocations @@ -9123,18 +9161,9 @@ bfd_elf_gc_sections (bfd *abfd, struct b continue; for (o = sub->sections; o != NULL; o = o->next) - { - if (o->flags & SEC_KEEP) - { - /* _bfd_elf_discard_section_eh_frame knows how to discard - orphaned FDEs so don't mark sections referenced by the - EH frame section. */ - if (strcmp (o->name, ".eh_frame") == 0) - o->gc_mark = 1; - else if (!_bfd_elf_gc_mark (info, o, gc_mark_hook)) - return FALSE; - } - } + if ((o->flags & SEC_KEEP) != 0 && !o->gc_mark) + if (!_bfd_elf_gc_mark (info, o, gc_mark_hook)) + return FALSE; } /* ... and mark SEC_EXCLUDE for those that go. */ @@ -9792,10 +9821,11 @@ _bfd_elf_section_already_linked (bfd *ab } static void -bfd_elf_set_symbol (struct elf_link_hash_entry *h, bfd_vma val) +bfd_elf_set_symbol (struct elf_link_hash_entry *h, bfd_vma val, + struct bfd_section *s) { h->root.type = bfd_link_hash_defined; - h->root.u.def.section = bfd_abs_section_ptr; + h->root.u.def.section = s ? s : bfd_abs_section_ptr; h->root.u.def.value = val; h->def_regular = 1; h->type = STT_OBJECT; @@ -9803,23 +9833,28 @@ bfd_elf_set_symbol (struct elf_link_hash h->forced_local = 1; } -/* Set NAME to VAL if the symbol exists and is undefined. */ +/* Set NAME to VAL if the symbol exists and is not defined in a regular + object file. If S is NULL it is an absolute symbol, otherwise it is + relative to that section. */ void _bfd_elf_provide_symbol (struct bfd_link_info *info, const char *name, - bfd_vma val) + bfd_vma val, struct bfd_section *s) { struct elf_link_hash_entry *h; - h = elf_link_hash_lookup (elf_hash_table (info), name, FALSE, FALSE, - FALSE); - if (h != NULL && (h->root.type == bfd_link_hash_undefined - || h->root.type == bfd_link_hash_undefweak)) - bfd_elf_set_symbol (h, val); + bfd_elf_record_link_assignment (info, name, TRUE); + + h = elf_link_hash_lookup (elf_hash_table (info), name, FALSE, FALSE, FALSE); + if (h != NULL + && !(h->root.type == bfd_link_hash_defined + && h->root.u.def.section != NULL + && h->root.u.def.section != h->root.u.def.section->output_section)) + bfd_elf_set_symbol (h, val, s); } -/* Set START and END to boundaries of SEC if they exist and are - undefined. */ +/* Set START and END to boundaries of SEC if they exist and are not + defined in regular object files. */ void _bfd_elf_provide_section_bound_symbols (struct bfd_link_info *info, @@ -9827,49 +9862,41 @@ _bfd_elf_provide_section_bound_symbols ( const char *start, const char *end) { - struct elf_link_hash_entry *hs, *he; - bfd_vma start_val, end_val; - bfd_boolean do_start, do_end; - - /* Check if we need them or not first. */ - hs = elf_link_hash_lookup (elf_hash_table (info), start, FALSE, - FALSE, FALSE); - do_start = (hs != NULL - && (hs->root.type == bfd_link_hash_undefined - || hs->root.type == bfd_link_hash_undefweak)); - - he = elf_link_hash_lookup (elf_hash_table (info), end, FALSE, - FALSE, FALSE); - do_end = (he != NULL - && (he->root.type == bfd_link_hash_undefined - || he->root.type == bfd_link_hash_undefweak)); + bfd_vma val = 0; + _bfd_elf_provide_symbol (info, start, val, sec); + if (sec != NULL) + val = sec->size; + _bfd_elf_provide_symbol (info, end, val, sec); +} - if (!do_start && !do_end) - return; +/* Convert symbols in excluded output sections to absolute. */ - if (sec != NULL) - { - start_val = sec->vma; - end_val = start_val + sec->size; - } - else +static bfd_boolean +fix_syms (struct bfd_link_hash_entry *h, void *data) +{ + bfd *obfd = (bfd *) data; + + if (h->type == bfd_link_hash_warning) + h = h->u.i.link; + + if (h->type == bfd_link_hash_defined + || h->type == bfd_link_hash_defweak) { - /* We have to choose those values very carefully. Some targets, - like alpha, may have relocation overflow with 0. "__bss_start" - should be defined in all cases. */ - struct elf_link_hash_entry *h - = elf_link_hash_lookup (elf_hash_table (info), "__bss_start", - FALSE, FALSE, FALSE); - if (h != NULL && h->root.type == bfd_link_hash_defined) - start_val = h->root.u.def.value; - else - start_val = 0; - end_val = start_val; + asection *s = h->u.def.section; + if (s != NULL + && s == s->output_section + && bfd_section_removed_from_list (obfd, s)) + { + h->u.def.value += s->vma; + h->u.def.section = bfd_abs_section_ptr; + } } - if (do_start) - bfd_elf_set_symbol (hs, start_val); + return TRUE; +} - if (do_end) - bfd_elf_set_symbol (he, end_val); +void +_bfd_elf_fix_excluded_sec_syms (bfd *obfd, struct bfd_link_info *info) +{ + bfd_link_hash_traverse (info->hash, fix_syms, obfd); } diff -uprN binutils-2.16.91.0.1/bfd/elf-m10300.c binutils-2.16.91.0.2/bfd/elf-m10300.c --- binutils-2.16.91.0.1/bfd/elf-m10300.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf-m10300.c 2005-07-20 12:27:27.071229645 -0700 @@ -4221,7 +4221,6 @@ _bfd_mn10300_elf_size_dynamic_sections ( for (s = dynobj->sections; s != NULL; s = s->next) { const char * name; - bfd_boolean strip; if ((s->flags & SEC_LINKER_CREATED) == 0) continue; @@ -4230,34 +4229,14 @@ _bfd_mn10300_elf_size_dynamic_sections ( of the dynobj section names depend upon the input files. */ name = bfd_get_section_name (dynobj, s); - strip = FALSE; - if (strcmp (name, ".plt") == 0) { - if (s->size == 0) - /* Strip this section if we don't need it; see the - comment below. */ - strip = TRUE; - else - /* Remember whether there is a PLT. */ - plt = TRUE; + /* Remember whether there is a PLT. */ + plt = s->size != 0; } else if (strncmp (name, ".rela", 5) == 0) { - if (s->size == 0) - { - /* If we don't need this section, strip it from the - output file. This is mostly to handle .rela.bss and - .rela.plt. We must create both sections in - create_dynamic_sections, because they must be created - before the linker maps input sections to output - sections. The linker does that before - adjust_dynamic_symbol is called, and it is that - function which decides whether anything needs to go - into these sections. */ - strip = TRUE; - } - else + if (s->size != 0) { asection * target; @@ -4288,23 +4267,36 @@ _bfd_mn10300_elf_size_dynamic_sections ( s->reloc_count = 0; } } - else if (strncmp (name, ".got", 4) != 0) + else if (strncmp (name, ".got", 4) != 0 + && strcmp (name, ".dynbss") != 0) /* It's not one of our sections, so don't allocate space. */ continue; - if (strip) + if (s->size == 0) { + /* If we don't need this section, strip it from the + output file. This is mostly to handle .rela.bss and + .rela.plt. We must create both sections in + create_dynamic_sections, because they must be created + before the linker maps input sections to output + sections. The linker does that before + adjust_dynamic_symbol is called, and it is that + function which decides whether anything needs to go + into these sections. */ s->flags |= SEC_EXCLUDE; continue; } + if ((s->flags & SEC_HAS_CONTENTS) == 0) + continue; + /* Allocate memory for the section contents. We use bfd_zalloc here in case unused entries are not reclaimed before the section's contents are written out. This should not happen, but this way if it does, we get a R_MN10300_NONE reloc instead of garbage. */ s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); - if (s->contents == NULL && s->size != 0) + if (s->contents == NULL) return FALSE; } diff -uprN binutils-2.16.91.0.1/bfd/elf-vxworks.c binutils-2.16.91.0.2/bfd/elf-vxworks.c --- binutils-2.16.91.0.1/bfd/elf-vxworks.c 2005-05-10 15:46:41.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elf-vxworks.c 2005-07-20 12:27:27.072229480 -0700 @@ -142,6 +142,8 @@ elf_vxworks_final_write_processing (bfd sec = bfd_get_section_by_name (abfd, ".rel.plt.unloaded"); if (!sec) + sec = bfd_get_section_by_name (abfd, ".rela.plt.unloaded"); + if (!sec) return; d = elf_section_data (sec); d->this_hdr.sh_link = elf_tdata (abfd)->symtab_section; diff -uprN binutils-2.16.91.0.1/bfd/elfxx-ia64.c binutils-2.16.91.0.2/bfd/elfxx-ia64.c --- binutils-2.16.91.0.1/bfd/elfxx-ia64.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elfxx-ia64.c 2005-07-20 12:27:27.397175896 -0700 @@ -487,7 +487,8 @@ lookup_howto (rtype) elf_code_to_howto_index[ia64_howto_table[i].type] = i; } - BFD_ASSERT (rtype <= R_IA64_MAX_RELOC_CODE); + if (rtype > R_IA64_MAX_RELOC_CODE) + return 0; i = elf_code_to_howto_index[rtype]; if (i >= NELEMS (ia64_howto_table)) return 0; @@ -5050,46 +5051,13 @@ elfNN_ia64_reloc_type_class (rela) } } -static struct bfd_elf_special_section const - ia64_special_sections_s[]= +static const struct bfd_elf_special_section elfNN_ia64_special_sections[] = { { ".sbss", 5, -1, SHT_NOBITS, SHF_ALLOC + SHF_WRITE + SHF_IA_64_SHORT }, { ".sdata", 6, -1, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE + SHF_IA_64_SHORT }, { NULL, 0, 0, 0, 0 } }; -static struct bfd_elf_special_section const * - elfNN_ia64_special_sections[27] = -{ - NULL, /* 'a' */ - NULL, /* 'b' */ - NULL, /* 'c' */ - NULL, /* 'd' */ - NULL, /* 'e' */ - NULL, /* 'f' */ - NULL, /* 'g' */ - NULL, /* 'h' */ - NULL, /* 'i' */ - NULL, /* 'j' */ - NULL, /* 'k' */ - NULL, /* 'l' */ - NULL, /* 'm' */ - NULL, /* 'n' */ - NULL, /* 'o' */ - NULL, /* 'p' */ - NULL, /* 'q' */ - NULL, /* 'r' */ - ia64_special_sections_s, /* 's' */ - NULL, /* 't' */ - NULL, /* 'u' */ - NULL, /* 'v' */ - NULL, /* 'w' */ - NULL, /* 'x' */ - NULL, /* 'y' */ - NULL, /* 'z' */ - NULL /* other */ -}; - static bfd_boolean elfNN_ia64_object_p (bfd *abfd) { @@ -5219,7 +5187,7 @@ static void elfNN_hpux_backend_symbol_processing (bfd *abfd ATTRIBUTE_UNUSED, asymbol *asym) { - elf_symbol_type *elfsym = (elf_symbol_type *) asym;; + elf_symbol_type *elfsym = (elf_symbol_type *) asym; switch (elfsym->internal_elf_sym.st_shndx) { diff -uprN binutils-2.16.91.0.1/bfd/elfxx-mips.c binutils-2.16.91.0.2/bfd/elfxx-mips.c --- binutils-2.16.91.0.1/bfd/elfxx-mips.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elfxx-mips.c 2005-07-20 12:27:27.413173258 -0700 @@ -6668,7 +6668,6 @@ _bfd_mips_elf_size_dynamic_sections (bfd for (s = dynobj->sections; s != NULL; s = s->next) { const char *name; - bfd_boolean strip; /* It's OK to base decisions on the section name, because none of the dynobj section names depend upon the input files. */ @@ -6677,24 +6676,9 @@ _bfd_mips_elf_size_dynamic_sections (bfd if ((s->flags & SEC_LINKER_CREATED) == 0) continue; - strip = FALSE; - if (strncmp (name, ".rel", 4) == 0) { - if (s->size == 0) - { - /* We only strip the section if the output section name - has the same name. Otherwise, there might be several - input sections for this output section. FIXME: This - code is probably not needed these days anyhow, since - the linker now does not create empty output sections. */ - if (s->output_section != NULL - && strcmp (name, - bfd_get_section_name (s->output_section->owner, - s->output_section)) == 0) - strip = TRUE; - } - else + if (s->size != 0) { const char *outname; asection *target; @@ -6818,15 +6802,18 @@ _bfd_mips_elf_size_dynamic_sections (bfd continue; } - if (strip) + if (s->size == 0) { s->flags |= SEC_EXCLUDE; continue; } + if ((s->flags & SEC_HAS_CONTENTS) == 0) + continue; + /* Allocate memory for the section contents. */ s->contents = bfd_zalloc (dynobj, s->size); - if (s->contents == NULL && s->size != 0) + if (s->contents == NULL) { bfd_set_error (bfd_error_no_memory); return FALSE; @@ -9969,63 +9956,13 @@ _bfd_mips_elf_print_private_bfd_data (bf return TRUE; } -static struct bfd_elf_special_section const - mips_special_sections_l[]= +const struct bfd_elf_special_section _bfd_mips_elf_special_sections[] = { { ".lit4", 5, 0, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE + SHF_MIPS_GPREL }, { ".lit8", 5, 0, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE + SHF_MIPS_GPREL }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - mips_special_sections_m[]= -{ { ".mdebug", 7, 0, SHT_MIPS_DEBUG, 0 }, - { NULL, 0, 0, 0, 0 } -}; - -static struct bfd_elf_special_section const - mips_special_sections_s[]= -{ - { ".sdata", 6, -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE + SHF_MIPS_GPREL }, { ".sbss", 5, -2, SHT_NOBITS, SHF_ALLOC + SHF_WRITE + SHF_MIPS_GPREL }, -}; - -static struct bfd_elf_special_section const - mips_special_sections_u[]= -{ + { ".sdata", 6, -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE + SHF_MIPS_GPREL }, { ".ucode", 6, 0, SHT_MIPS_UCODE, 0 }, { NULL, 0, 0, 0, 0 } }; - -struct bfd_elf_special_section const * - _bfd_mips_elf_special_sections[27] = -{ - NULL, /* 'a' */ - NULL, /* 'b' */ - NULL, /* 'c' */ - NULL, /* 'd' */ - NULL, /* 'e' */ - NULL, /* 'f' */ - NULL, /* 'g' */ - NULL, /* 'h' */ - NULL, /* 'i' */ - NULL, /* 'j' */ - NULL, /* 'k' */ - mips_special_sections_l, /* 'l' */ - mips_special_sections_m, /* 'm' */ - NULL, /* 'n' */ - NULL, /* 'o' */ - NULL, /* 'p' */ - NULL, /* 'q' */ - NULL, /* 'r' */ - mips_special_sections_s, /* 'm' */ - NULL, /* 't' */ - mips_special_sections_u, /* 'u' */ - NULL, /* 'v' */ - NULL, /* 'w' */ - NULL, /* 'x' */ - NULL, /* 'y' */ - NULL, /* 'z' */ - NULL /* other */ -}; diff -uprN binutils-2.16.91.0.1/bfd/elfxx-mips.h binutils-2.16.91.0.2/bfd/elfxx-mips.h --- binutils-2.16.91.0.1/bfd/elfxx-mips.h 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elfxx-mips.h 2005-07-20 12:27:27.414173094 -0700 @@ -128,7 +128,8 @@ extern bfd_boolean _bfd_mips_relax_secti extern bfd_vma _bfd_mips_elf_sign_extend (bfd_vma, int); -extern struct bfd_elf_special_section const *_bfd_mips_elf_special_sections[]; +extern const struct bfd_elf_special_section _bfd_mips_elf_special_sections []; + #define elf_backend_name_local_section_symbols \ _bfd_mips_elf_name_local_section_symbols #define elf_backend_special_sections _bfd_mips_elf_special_sections diff -uprN binutils-2.16.91.0.1/bfd/elfxx-sparc.c binutils-2.16.91.0.2/bfd/elfxx-sparc.c --- binutils-2.16.91.0.1/bfd/elfxx-sparc.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elfxx-sparc.c 2005-07-20 12:27:27.418172434 -0700 @@ -397,7 +397,12 @@ _bfd_sparc_elf_info_to_howto_ptr (unsign return &sparc_rev32_howto; default: - BFD_ASSERT (r_type < (unsigned int) R_SPARC_max_std); + if (r_type >= (unsigned int) R_SPARC_max_std) + { + (*_bfd_error_handler) (_("invalid relocation type %d"), + (int) r_type); + r_type = R_SPARC_NONE; + } return &_bfd_sparc_elf_howto_table[r_type]; } } @@ -2147,55 +2152,54 @@ _bfd_sparc_elf_size_dynamic_sections (bf memory for them. */ for (s = dynobj->sections; s != NULL; s = s->next) { - const char *name; - bfd_boolean strip = FALSE; - if ((s->flags & SEC_LINKER_CREATED) == 0) continue; - /* It's OK to base decisions on the section name, because none - of the dynobj section names depend upon the input files. */ - name = bfd_get_section_name (dynobj, s); - - if (strncmp (name, ".rela", 5) == 0) + if (s == htab->splt + || s == htab->sgot + || s == htab->sdynbss) { - if (s->size == 0) - { - /* If we don't need this section, strip it from the - output file. This is to handle .rela.bss and - .rel.plt. We must create it in - create_dynamic_sections, because it must be created - before the linker maps input sections to output - sections. The linker does that before - adjust_dynamic_symbol is called, and it is that - function which decides whether anything needs to go - into these sections. */ - strip = TRUE; - } - else + /* Strip this section if we don't need it; see the + comment below. */ + } + else if (strncmp (s->name, ".rela", 5) == 0) + { + if (s->size != 0) { /* We use the reloc_count field as a counter if we need to copy relocs into the output file. */ s->reloc_count = 0; } } - else if (s != htab->splt && s != htab->sgot) + else { - /* It's not one of our sections, so don't allocate space. */ + /* It's not one of our sections. */ continue; } - if (strip) + if (s->size == 0) { + /* If we don't need this section, strip it from the + output file. This is mostly to handle .rela.bss and + .rela.plt. We must create both sections in + create_dynamic_sections, because they must be created + before the linker maps input sections to output + sections. The linker does that before + adjust_dynamic_symbol is called, and it is that + function which decides whether anything needs to go + into these sections. */ s->flags |= SEC_EXCLUDE; continue; } + if ((s->flags & SEC_HAS_CONTENTS) == 0) + continue; + /* Allocate memory for the section contents. Zero the memory for the benefit of .rela.plt, which has 4 unused entries at the beginning, and we don't want garbage. */ s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); - if (s->contents == NULL && s->size != 0) + if (s->contents == NULL) return FALSE; } diff -uprN binutils-2.16.91.0.1/bfd/elfxx-target.h binutils-2.16.91.0.2/bfd/elfxx-target.h --- binutils-2.16.91.0.1/bfd/elfxx-target.h 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/elfxx-target.h 2005-07-20 12:27:27.419172269 -0700 @@ -331,6 +331,9 @@ #ifndef elf_backend_section_flags #define elf_backend_section_flags 0 #endif +#ifndef elf_backend_get_sec_type_attr +#define elf_backend_get_sec_type_attr _bfd_elf_get_sec_type_attr +#endif #ifndef elf_backend_section_from_phdr #define elf_backend_section_from_phdr _bfd_elf_make_section_from_phdr #endif @@ -540,6 +543,7 @@ static const struct elf_backend_data elf elf_backend_section_processing, elf_backend_section_from_shdr, elf_backend_section_flags, + elf_backend_get_sec_type_attr, elf_backend_section_from_phdr, elf_backend_fake_sections, elf_backend_section_from_bfd_section, diff -uprN binutils-2.16.91.0.1/bfd/libbfd.c binutils-2.16.91.0.2/bfd/libbfd.c --- binutils-2.16.91.0.1/bfd/libbfd.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/libbfd.c 2005-07-20 12:27:27.425171280 -0700 @@ -156,6 +156,36 @@ bfd_malloc (bfd_size_type size) return ptr; } +/* Allocate memory using malloc, nmemb * size with overflow checking. */ + +void * +bfd_malloc2 (bfd_size_type nmemb, bfd_size_type size) +{ + void *ptr; + + if ((nmemb | size) >= HALF_BFD_SIZE_TYPE + && size != 0 + && nmemb > ~(bfd_size_type) 0 / size) + { + bfd_set_error (bfd_error_no_memory); + return NULL; + } + + size *= nmemb; + + if (size != (size_t) size) + { + bfd_set_error (bfd_error_no_memory); + return NULL; + } + + ptr = malloc ((size_t) size); + if (ptr == NULL && (size_t) size != 0) + bfd_set_error (bfd_error_no_memory); + + return ptr; +} + /* Reallocate memory using realloc. */ void * @@ -180,6 +210,40 @@ bfd_realloc (void *ptr, bfd_size_type si return ret; } +/* Reallocate memory using realloc, nmemb * size with overflow checking. */ + +void * +bfd_realloc2 (void *ptr, bfd_size_type nmemb, bfd_size_type size) +{ + void *ret; + + if ((nmemb | size) >= HALF_BFD_SIZE_TYPE + && size != 0 + && nmemb > ~(bfd_size_type) 0 / size) + { + bfd_set_error (bfd_error_no_memory); + return NULL; + } + + size *= nmemb; + + if (size != (size_t) size) + { + bfd_set_error (bfd_error_no_memory); + return NULL; + } + + if (ptr == NULL) + ret = malloc ((size_t) size); + else + ret = realloc (ptr, (size_t) size); + + if (ret == NULL && (size_t) size != 0) + bfd_set_error (bfd_error_no_memory); + + return ret; +} + /* Allocate memory using malloc and clear it. */ void * @@ -205,6 +269,44 @@ bfd_zmalloc (bfd_size_type size) return ptr; } + +/* Allocate memory using malloc (nmemb * size) with overflow checking + and clear it. */ + +void * +bfd_zmalloc2 (bfd_size_type nmemb, bfd_size_type size) +{ + void *ptr; + + if ((nmemb | size) >= HALF_BFD_SIZE_TYPE + && size != 0 + && nmemb > ~(bfd_size_type) 0 / size) + { + bfd_set_error (bfd_error_no_memory); + return NULL; + } + + size *= nmemb; + + if (size != (size_t) size) + { + bfd_set_error (bfd_error_no_memory); + return NULL; + } + + ptr = malloc ((size_t) size); + + if ((size_t) size != 0) + { + if (ptr == NULL) + bfd_set_error (bfd_error_no_memory); + else + memset (ptr, 0, (size_t) size); + } + + return ptr; +} + /* INTERNAL_FUNCTION bfd_write_bigendian_4byte_int diff -uprN binutils-2.16.91.0.1/bfd/libbfd.h binutils-2.16.91.0.2/bfd/libbfd.h --- binutils-2.16.91.0.1/bfd/libbfd.h 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/libbfd.h 2005-07-20 12:27:27.428170785 -0700 @@ -69,6 +69,7 @@ struct artdata { carsym *symdefs; /* the symdef entries */ symindex symdef_count; /* how many there are */ char *extended_names; /* clever intel extension */ + bfd_size_type extended_names_size; /* Size of extended names */ /* when more compilers are standard C, this can be a time_t */ long armap_timestamp; /* Timestamp value written into armap. This is used for BSD archives to check @@ -98,6 +99,12 @@ extern void *bfd_realloc (void *, bfd_size_type); extern void *bfd_zmalloc (bfd_size_type); +extern void *bfd_malloc2 + (bfd_size_type, bfd_size_type); +extern void *bfd_realloc2 + (void *, bfd_size_type, bfd_size_type); +extern void *bfd_zmalloc2 + (bfd_size_type, bfd_size_type); extern void _bfd_default_error_handler (const char *s, ...); extern bfd_error_handler_type _bfd_error_handler; @@ -108,6 +115,10 @@ extern void *bfd_alloc (bfd *, bfd_size_type); extern void *bfd_zalloc (bfd *, bfd_size_type); +extern void *bfd_alloc2 + (bfd *, bfd_size_type, bfd_size_type); +extern void *bfd_zalloc2 + (bfd *, bfd_size_type, bfd_size_type); extern void bfd_release (bfd *, void *); @@ -1327,6 +1338,23 @@ static const char *const bfd_reloc_code_ "BFD_RELOC_DLX_HI16_S", "BFD_RELOC_DLX_LO16", "BFD_RELOC_DLX_JMP26", + "BFD_RELOC_M16C_8_PCREL8", + "BFD_RELOC_M16C_16_PCREL8", + "BFD_RELOC_M16C_8_PCREL16", + "BFD_RELOC_M16C_8_ELABEL24", + "BFD_RELOC_M16C_8_ABS16", + "BFD_RELOC_M16C_16_ABS16", + "BFD_RELOC_M16C_16_ABS24", + "BFD_RELOC_M16C_16_ABS32", + "BFD_RELOC_M16C_24_ABS16", + "BFD_RELOC_M16C_24_ABS24", + "BFD_RELOC_M16C_24_ABS32", + "BFD_RELOC_M16C_32_ABS16", + "BFD_RELOC_M16C_32_ABS24", + "BFD_RELOC_M16C_32_ABS32", + "BFD_RELOC_M16C_40_ABS16", + "BFD_RELOC_M16C_40_ABS24", + "BFD_RELOC_M16C_40_ABS32", "BFD_RELOC_M32R_24", "BFD_RELOC_M32R_10_PCREL", "BFD_RELOC_M32R_18_PCREL", @@ -1718,6 +1746,11 @@ static const char *const bfd_reloc_code_ "BFD_RELOC_VAX_GLOB_DAT", "BFD_RELOC_VAX_JMP_SLOT", "BFD_RELOC_VAX_RELATIVE", + "BFD_RELOC_MS1_PC16", + "BFD_RELOC_MS1_HI16", + "BFD_RELOC_MS1_LO16", + "BFD_RELOC_MS1_GNU_VTINHERIT", + "BFD_RELOC_MS1_GNU_VTENTRY", "BFD_RELOC_MSP430_10_PCREL", "BFD_RELOC_MSP430_16_PCREL", "BFD_RELOC_MSP430_16", diff -uprN binutils-2.16.91.0.1/bfd/libbfd-in.h binutils-2.16.91.0.2/bfd/libbfd-in.h --- binutils-2.16.91.0.1/bfd/libbfd-in.h 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/libbfd-in.h 2005-07-20 12:27:27.420172104 -0700 @@ -64,6 +64,7 @@ struct artdata { carsym *symdefs; /* the symdef entries */ symindex symdef_count; /* how many there are */ char *extended_names; /* clever intel extension */ + bfd_size_type extended_names_size; /* Size of extended names */ /* when more compilers are standard C, this can be a time_t */ long armap_timestamp; /* Timestamp value written into armap. This is used for BSD archives to check @@ -93,6 +94,12 @@ extern void *bfd_realloc (void *, bfd_size_type); extern void *bfd_zmalloc (bfd_size_type); +extern void *bfd_malloc2 + (bfd_size_type, bfd_size_type); +extern void *bfd_realloc2 + (void *, bfd_size_type, bfd_size_type); +extern void *bfd_zmalloc2 + (bfd_size_type, bfd_size_type); extern void _bfd_default_error_handler (const char *s, ...); extern bfd_error_handler_type _bfd_error_handler; @@ -103,6 +110,10 @@ extern void *bfd_alloc (bfd *, bfd_size_type); extern void *bfd_zalloc (bfd *, bfd_size_type); +extern void *bfd_alloc2 + (bfd *, bfd_size_type, bfd_size_type); +extern void *bfd_zalloc2 + (bfd *, bfd_size_type, bfd_size_type); extern void bfd_release (bfd *, void *); diff -uprN binutils-2.16.91.0.1/bfd/Makefile.am binutils-2.16.91.0.2/bfd/Makefile.am --- binutils-2.16.91.0.1/bfd/Makefile.am 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/Makefile.am 2005-07-20 12:27:26.934252232 -0700 @@ -77,6 +77,7 @@ ALL_MACHINES = \ cpu-i960.lo \ cpu-ip2k.lo \ cpu-iq2000.lo \ + cpu-m32c.lo \ cpu-m32r.lo \ cpu-m68hc11.lo \ cpu-m68hc12.lo \ @@ -136,6 +137,7 @@ ALL_MACHINES_CFILES = \ cpu-i960.c \ cpu-ip2k.c \ cpu-iq2000.c \ + cpu-m32c.c \ cpu-m32r.c \ cpu-m68hc11.c \ cpu-m68hc12.c \ @@ -242,6 +244,7 @@ BFD32_BACKENDS = \ elf32-i960.lo \ elf32-ip2k.lo \ elf32-iq2000.lo \ + elf32-m32c.lo \ elf32-m32r.lo \ elf32-m68hc11.lo \ elf32-m68hc12.lo \ @@ -413,6 +416,7 @@ BFD32_BACKENDS_CFILES = \ elf32-i960.c \ elf32-ip2k.c \ elf32-iq2000.c \ + elf32-m32c.c \ elf32-m32r.c \ elf32-m68k.c \ elf32-m68hc11.c \ @@ -904,8 +908,9 @@ bfdver.h: $(srcdir)/version.h $(srcdir)/ # DO NOT DELETE THIS LINE -- mkdep uses it. # DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY. -archive.lo: archive.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \ - $(INCDIR)/aout/ar.h $(INCDIR)/aout/ranlib.h $(INCDIR)/safe-ctype.h +archive.lo: archive.c $(INCDIR)/filenames.h $(INCDIR)/libiberty.h \ + $(INCDIR)/hashtab.h $(INCDIR)/aout/ar.h $(INCDIR)/aout/ranlib.h \ + $(INCDIR)/safe-ctype.h archures.lo: archures.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \ $(INCDIR)/safe-ctype.h bfd.lo: bfd.c bfdver.h $(INCDIR)/filenames.h $(INCDIR)/libiberty.h \ @@ -985,6 +990,7 @@ cpu-i860.lo: cpu-i860.c $(INCDIR)/filena cpu-i960.lo: cpu-i960.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h cpu-ip2k.lo: cpu-ip2k.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h cpu-iq2000.lo: cpu-iq2000.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h +cpu-m32c.lo: cpu-m32c.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h cpu-m32r.lo: cpu-m32r.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h cpu-m68hc11.lo: cpu-m68hc11.c $(INCDIR)/filenames.h \ $(INCDIR)/hashtab.h @@ -998,6 +1004,7 @@ cpu-maxq.lo: cpu-maxq.c $(INCDIR)/filena cpu-mcore.lo: cpu-mcore.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h cpu-mips.lo: cpu-mips.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h cpu-mmix.lo: cpu-mmix.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h +cpu-ms1.lo: cpu-ms1.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h cpu-msp430.lo: cpu-msp430.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h cpu-or32.lo: cpu-or32.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h cpu-ns32k.lo: cpu-ns32k.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \ @@ -1287,6 +1294,11 @@ elf32-iq2000.lo: elf32-iq2000.c $(INCDIR $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \ $(INCDIR)/elf/iq2000.h $(INCDIR)/elf/reloc-macros.h \ elf32-target.h +elf32-m32c.lo: elf32-m32c.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \ + elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/m32c.h \ + $(INCDIR)/elf/reloc-macros.h $(INCDIR)/libiberty.h \ + elf32-target.h elf32-m32r.lo: elf32-m32r.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \ elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/m32r.h \ @@ -1337,10 +1349,10 @@ elf32-mips.lo: elf32-mips.c $(INCDIR)/fi $(INCDIR)/coff/symconst.h $(INCDIR)/coff/internal.h \ $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/mips.h $(INCDIR)/coff/external.h \ ecoffswap.h elf32-target.h -elf32-ms1.lo: elf32-ms1.c elf-bfd.h $(INCDIR)/elf/common.h \ - $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \ - $(INCDIR)/elf/ms1.h $(INCDIR)/elf/reloc-macros.h \ - elf32-target.h +elf32-ms1.lo: elf32-ms1.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \ + elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/ms1.h \ + $(INCDIR)/elf/reloc-macros.h elf32-target.h elf32-msp430.lo: elf32-msp430.c $(INCDIR)/filenames.h \ $(INCDIR)/libiberty.h $(INCDIR)/hashtab.h elf-bfd.h \ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ @@ -1363,7 +1375,8 @@ elf32-pj.lo: elf32-pj.c $(INCDIR)/filena elf32-ppc.lo: elf32-ppc.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \ $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \ $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/ppc.h \ - $(INCDIR)/elf/reloc-macros.h elf32-ppc.h elf32-target.h + $(INCDIR)/elf/reloc-macros.h elf32-ppc.h elf-vxworks.h \ + elf32-target.h elf32-sh64.lo: elf32-sh64.c $(INCDIR)/filenames.h elf-bfd.h \ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ $(INCDIR)/bfdlink.h $(srcdir)/../opcodes/sh64-opc.h \ diff -uprN binutils-2.16.91.0.1/bfd/Makefile.in binutils-2.16.91.0.2/bfd/Makefile.in --- binutils-2.16.91.0.1/bfd/Makefile.in 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/Makefile.in 2005-07-20 12:27:26.938251573 -0700 @@ -314,6 +314,7 @@ ALL_MACHINES = \ cpu-i960.lo \ cpu-ip2k.lo \ cpu-iq2000.lo \ + cpu-m32c.lo \ cpu-m32r.lo \ cpu-m68hc11.lo \ cpu-m68hc12.lo \ @@ -373,6 +374,7 @@ ALL_MACHINES_CFILES = \ cpu-i960.c \ cpu-ip2k.c \ cpu-iq2000.c \ + cpu-m32c.c \ cpu-m32r.c \ cpu-m68hc11.c \ cpu-m68hc12.c \ @@ -480,6 +482,7 @@ BFD32_BACKENDS = \ elf32-i960.lo \ elf32-ip2k.lo \ elf32-iq2000.lo \ + elf32-m32c.lo \ elf32-m32r.lo \ elf32-m68hc11.lo \ elf32-m68hc12.lo \ @@ -651,6 +654,7 @@ BFD32_BACKENDS_CFILES = \ elf32-i960.c \ elf32-ip2k.c \ elf32-iq2000.c \ + elf32-m32c.c \ elf32-m32r.c \ elf32-m68k.c \ elf32-m68hc11.c \ @@ -1473,8 +1477,9 @@ bfdver.h: $(srcdir)/version.h $(srcdir)/ # DO NOT DELETE THIS LINE -- mkdep uses it. # DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY. -archive.lo: archive.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \ - $(INCDIR)/aout/ar.h $(INCDIR)/aout/ranlib.h $(INCDIR)/safe-ctype.h +archive.lo: archive.c $(INCDIR)/filenames.h $(INCDIR)/libiberty.h \ + $(INCDIR)/hashtab.h $(INCDIR)/aout/ar.h $(INCDIR)/aout/ranlib.h \ + $(INCDIR)/safe-ctype.h archures.lo: archures.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \ $(INCDIR)/safe-ctype.h bfd.lo: bfd.c bfdver.h $(INCDIR)/filenames.h $(INCDIR)/libiberty.h \ @@ -1554,6 +1559,7 @@ cpu-i860.lo: cpu-i860.c $(INCDIR)/filena cpu-i960.lo: cpu-i960.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h cpu-ip2k.lo: cpu-ip2k.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h cpu-iq2000.lo: cpu-iq2000.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h +cpu-m32c.lo: cpu-m32c.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h cpu-m32r.lo: cpu-m32r.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h cpu-m68hc11.lo: cpu-m68hc11.c $(INCDIR)/filenames.h \ $(INCDIR)/hashtab.h @@ -1567,6 +1573,7 @@ cpu-maxq.lo: cpu-maxq.c $(INCDIR)/filena cpu-mcore.lo: cpu-mcore.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h cpu-mips.lo: cpu-mips.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h cpu-mmix.lo: cpu-mmix.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h +cpu-ms1.lo: cpu-ms1.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h cpu-msp430.lo: cpu-msp430.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h cpu-or32.lo: cpu-or32.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h cpu-ns32k.lo: cpu-ns32k.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \ @@ -1856,6 +1863,11 @@ elf32-iq2000.lo: elf32-iq2000.c $(INCDIR $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \ $(INCDIR)/elf/iq2000.h $(INCDIR)/elf/reloc-macros.h \ elf32-target.h +elf32-m32c.lo: elf32-m32c.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \ + elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/m32c.h \ + $(INCDIR)/elf/reloc-macros.h $(INCDIR)/libiberty.h \ + elf32-target.h elf32-m32r.lo: elf32-m32r.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \ elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/m32r.h \ @@ -1906,10 +1918,10 @@ elf32-mips.lo: elf32-mips.c $(INCDIR)/fi $(INCDIR)/coff/symconst.h $(INCDIR)/coff/internal.h \ $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/mips.h $(INCDIR)/coff/external.h \ ecoffswap.h elf32-target.h -elf32-ms1.lo: elf32-ms1.c elf-bfd.h $(INCDIR)/elf/common.h \ - $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \ - $(INCDIR)/elf/ms1.h $(INCDIR)/elf/reloc-macros.h \ - elf32-target.h +elf32-ms1.lo: elf32-ms1.c $(INCDIR)/filenames.h $(INCDIR)/hashtab.h \ + elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/ms1.h \ + $(INCDIR)/elf/reloc-macros.h elf32-target.h elf32-msp430.lo: elf32-msp430.c $(INCDIR)/filenames.h \ $(INCDIR)/libiberty.h $(INCDIR)/hashtab.h elf-bfd.h \ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ @@ -1932,7 +1944,8 @@ elf32-pj.lo: elf32-pj.c $(INCDIR)/filena elf32-ppc.lo: elf32-ppc.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \ $(INCDIR)/hashtab.h elf-bfd.h $(INCDIR)/elf/common.h \ $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/ppc.h \ - $(INCDIR)/elf/reloc-macros.h elf32-ppc.h elf32-target.h + $(INCDIR)/elf/reloc-macros.h elf32-ppc.h elf-vxworks.h \ + elf32-target.h elf32-sh64.lo: elf32-sh64.c $(INCDIR)/filenames.h elf-bfd.h \ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ $(INCDIR)/bfdlink.h $(srcdir)/../opcodes/sh64-opc.h \ diff -uprN binutils-2.16.91.0.1/bfd/opncls.c binutils-2.16.91.0.2/bfd/opncls.c --- binutils-2.16.91.0.1/bfd/opncls.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/opncls.c 2005-07-20 12:27:27.432170126 -0700 @@ -858,6 +858,45 @@ bfd_alloc (bfd *abfd, bfd_size_type size /* INTERNAL_FUNCTION + bfd_alloc2 + +SYNOPSIS + void *bfd_alloc2 (bfd *abfd, bfd_size_type nmemb, bfd_size_type size); + +DESCRIPTION + Allocate a block of @var{nmemb} elements of @var{size} bytes each + of memory attached to <> and return a pointer to it. +*/ + +void * +bfd_alloc2 (bfd *abfd, bfd_size_type nmemb, bfd_size_type size) +{ + void *ret; + + if ((nmemb | size) >= HALF_BFD_SIZE_TYPE + && size != 0 + && nmemb > ~(bfd_size_type) 0 / size) + { + bfd_set_error (bfd_error_no_memory); + return NULL; + } + + size *= nmemb; + + if (size != (unsigned long) size) + { + bfd_set_error (bfd_error_no_memory); + return NULL; + } + + ret = objalloc_alloc (abfd->memory, (unsigned long) size); + if (ret == NULL) + bfd_set_error (bfd_error_no_memory); + return ret; +} + +/* +INTERNAL_FUNCTION bfd_zalloc SYNOPSIS @@ -879,6 +918,39 @@ bfd_zalloc (bfd *abfd, bfd_size_type siz return res; } +/* +INTERNAL_FUNCTION + bfd_zalloc2 + +SYNOPSIS + void *bfd_zalloc2 (bfd *abfd, bfd_size_type nmemb, bfd_size_type size); + +DESCRIPTION + Allocate a block of @var{nmemb} elements of @var{size} bytes each + of zeroed memory attached to <> and return a pointer to it. +*/ + +void * +bfd_zalloc2 (bfd *abfd, bfd_size_type nmemb, bfd_size_type size) +{ + void *res; + + if ((nmemb | size) >= HALF_BFD_SIZE_TYPE + && size != 0 + && nmemb > ~(bfd_size_type) 0 / size) + { + bfd_set_error (bfd_error_no_memory); + return NULL; + } + + size *= nmemb; + + res = bfd_alloc (abfd, size); + if (res) + memset (res, 0, (size_t) size); + return res; +} + /* Free a block allocated for a BFD. Note: Also frees all more recently allocated blocks! */ diff -uprN binutils-2.16.91.0.1/bfd/po/bfd.pot binutils-2.16.91.0.2/bfd/po/bfd.pot --- binutils-2.16.91.0.1/bfd/po/bfd.pot 2005-04-09 12:03:01.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/po/bfd.pot 2005-07-20 12:27:27.486161223 -0700 @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2005-03-05 22:14+1030\n" +"POT-Creation-Date: 2005-07-14 17:27-0500\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -16,52 +16,52 @@ msgstr "" "Content-Type: text/plain; charset=CHARSET\n" "Content-Transfer-Encoding: 8bit\n" -#: aout-adobe.c:204 +#: aout-adobe.c:127 msgid "%B: Unknown section type in a.out.adobe file: %x\n" msgstr "" -#: aout-cris.c:207 +#: aout-cris.c:202 #, c-format msgid "%s: Invalid relocation type exported: %d" msgstr "" -#: aout-cris.c:251 +#: aout-cris.c:245 msgid "%B: Invalid relocation type imported: %d" msgstr "" -#: aout-cris.c:262 +#: aout-cris.c:256 msgid "%B: Bad relocation record imported: %d" msgstr "" -#: aoutx.h:1287 aoutx.h:1626 +#: aoutx.h:1250 aoutx.h:1584 #, c-format msgid "%s: can not represent section `%s' in a.out object file format" msgstr "" -#: aoutx.h:1592 +#: aoutx.h:1550 #, c-format msgid "" "%s: can not represent section for symbol `%s' in a.out object file format" msgstr "" -#: aoutx.h:1594 +#: aoutx.h:1552 msgid "*unknown*" msgstr "" -#: aoutx.h:3682 +#: aoutx.h:5287 #, c-format msgid "%s: relocatable link from %s to %s not supported" msgstr "" -#: archive.c:1729 +#: archive.c:1758 msgid "Warning: writing archive was slow: rewriting timestamp\n" msgstr "" -#: archive.c:1992 +#: archive.c:2017 msgid "Reading archive file mod timestamp" msgstr "" -#: archive.c:2018 +#: archive.c:2041 msgid "Writing updated armap timestamp" msgstr "" @@ -174,12 +174,12 @@ msgstr "" msgid "not mapping: env var not set\n" msgstr "" -#: binary.c:309 +#: binary.c:285 #, c-format msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx." msgstr "" -#: coff64-rs6000.c:2107 coff-rs6000.c:3608 +#: coff64-rs6000.c:2109 coff-rs6000.c:3610 msgid "%B: symbol `%s' has unrecognized smclas %d" msgstr "" @@ -203,32 +203,55 @@ msgstr "" msgid "missing IHIHALF reloc" msgstr "" -#: coff-alpha.c:881 coff-alpha.c:918 coff-alpha.c:1972 coff-mips.c:985 +#: coff-alpha.c:489 +msgid "" +"%B: Cannot handle compressed Alpha binaries.\n" +" Use compiler flags, or objZ, to generate uncompressed binaries." +msgstr "" + +#: coff-alpha.c:646 +msgid "%B: unknown/unsupported relocation type %d" +msgstr "" + +#: coff-alpha.c:898 coff-alpha.c:935 coff-alpha.c:2007 coff-mips.c:985 msgid "GP relative relocation used when GP not defined" msgstr "" -#: coff-alpha.c:1467 +#: coff-alpha.c:1484 msgid "using multiple gp values" msgstr "" -#: coff-arm.c:1066 elf32-arm.c:1425 +#: coff-alpha.c:1543 +msgid "%B: unsupported relocation: ALPHA_R_GPRELHIGH" +msgstr "" + +#: coff-alpha.c:1550 +msgid "%B: unsupported relocation: ALPHA_R_GPRELLOW" +msgstr "" + +#: coff-alpha.c:1557 elf32-m32r.c:2452 elf64-alpha.c:3932 elf64-alpha.c:4058 +#: elf32-ia64.c:4085 elf64-ia64.c:4085 +msgid "%B: unknown relocation type %d" +msgstr "" + +#: coff-arm.c:990 elf32-arm.c:1916 #, c-format msgid "%B: unable to find THUMB glue '%s' for `%s'" msgstr "" -#: coff-arm.c:1096 elf32-arm.c:1459 +#: coff-arm.c:1019 elf32-arm.c:1950 #, c-format msgid "%B: unable to find ARM glue '%s' for `%s'" msgstr "" -#: coff-arm.c:1394 elf32-arm.c:2165 +#: coff-arm.c:1319 elf32-arm.c:2673 #, c-format msgid "" "%B(%s): warning: interworking not enabled.\n" " first occurrence: %B: arm call to thumb" msgstr "" -#: coff-arm.c:1484 +#: coff-arm.c:1409 #, c-format msgid "" "%B(%s): warning: interworking not enabled.\n" @@ -236,159 +259,159 @@ msgid "" " consider relinking with --support-old-code enabled" msgstr "" -#: coff-arm.c:1776 cofflink.c:3013 coff-tic80.c:687 +#: coff-arm.c:1702 cofflink.c:3013 coff-tic80.c:695 msgid "%B: bad reloc address 0x%lx in section `%A'" msgstr "" -#: coff-arm.c:2110 +#: coff-arm.c:2028 msgid "%B: illegal symbol index in reloc: %d" msgstr "" -#: coff-arm.c:2243 +#: coff-arm.c:2158 #, c-format msgid "ERROR: %B is compiled for APCS-%d, whereas %B is compiled for APCS-%d" msgstr "" -#: coff-arm.c:2259 elf32-arm.c:3583 +#: coff-arm.c:2174 elf32-arm.c:4464 #, c-format msgid "" "ERROR: %B passes floats in float registers, whereas %B passes them in " "integer registers" msgstr "" -#: coff-arm.c:2262 elf32-arm.c:3587 +#: coff-arm.c:2177 elf32-arm.c:4468 #, c-format msgid "" "ERROR: %B passes floats in integer registers, whereas %B passes them in " "float registers" msgstr "" -#: coff-arm.c:2276 +#: coff-arm.c:2191 #, c-format msgid "" "ERROR: %B is compiled as position independent code, whereas target %B is " "absolute position" msgstr "" -#: coff-arm.c:2279 +#: coff-arm.c:2194 #, c-format msgid "" "ERROR: %B is compiled as absolute position code, whereas target %B is " "position independent" msgstr "" -#: coff-arm.c:2307 elf32-arm.c:3652 +#: coff-arm.c:2222 elf32-arm.c:4533 #, c-format msgid "Warning: %B supports interworking, whereas %B does not" msgstr "" -#: coff-arm.c:2310 elf32-arm.c:3658 +#: coff-arm.c:2225 elf32-arm.c:4539 #, c-format msgid "Warning: %B does not support interworking, whereas %B does" msgstr "" -#: coff-arm.c:2336 +#: coff-arm.c:2249 #, c-format msgid "private flags = %x:" msgstr "" -#: coff-arm.c:2344 elf32-arm.c:3709 +#: coff-arm.c:2257 elf32-arm.c:4590 #, c-format msgid " [floats passed in float registers]" msgstr "" -#: coff-arm.c:2346 +#: coff-arm.c:2259 #, c-format msgid " [floats passed in integer registers]" msgstr "" -#: coff-arm.c:2349 elf32-arm.c:3712 +#: coff-arm.c:2262 elf32-arm.c:4593 #, c-format msgid " [position independent]" msgstr "" -#: coff-arm.c:2351 +#: coff-arm.c:2264 #, c-format msgid " [absolute position]" msgstr "" -#: coff-arm.c:2355 +#: coff-arm.c:2268 #, c-format msgid " [interworking flag not initialised]" msgstr "" -#: coff-arm.c:2357 +#: coff-arm.c:2270 #, c-format msgid " [interworking supported]" msgstr "" -#: coff-arm.c:2359 +#: coff-arm.c:2272 #, c-format msgid " [interworking not supported]" msgstr "" -#: coff-arm.c:2407 elf32-arm.c:3390 +#: coff-arm.c:2318 elf32-arm.c:4271 #, c-format msgid "" "Warning: Not setting interworking flag of %B since it has already been " "specified as non-interworking" msgstr "" -#: coff-arm.c:2411 elf32-arm.c:3394 +#: coff-arm.c:2322 elf32-arm.c:4275 #, c-format msgid "Warning: Clearing the interworking flag of %B due to outside request" msgstr "" -#: coffcode.h:859 +#: coffcode.h:849 msgid "%B: warning: COMDAT symbol '%s' does not match section name '%s'" msgstr "" #. Generate a warning message rather using the 'unhandled' #. variable as this will allow some .sys files generate by #. other toolchains to be processed. See bugzilla issue 196. -#: coffcode.h:1072 +#: coffcode.h:1061 msgid "" "%B: Warning: Ignoring section flag IMAGE_SCN_MEM_NOT_PAGED in section %s" msgstr "" -#: coffcode.h:1127 +#: coffcode.h:1116 msgid "%B (%s): Section flag %s (0x%x) ignored" msgstr "" -#: coffcode.h:2255 +#: coffcode.h:2210 #, c-format msgid "Unrecognized TI COFF target id '0x%x'" msgstr "" -#: coffcode.h:4375 +#: coffcode.h:4238 msgid "%B: warning: line number table read failed" msgstr "" -#: coffcode.h:4407 +#: coffcode.h:4270 msgid "%B: warning: illegal symbol index %ld in line numbers" msgstr "" -#: coffcode.h:4421 +#: coffcode.h:4284 msgid "%B: warning: duplicate line number information for `%s'" msgstr "" -#: coffcode.h:4771 +#: coffcode.h:4629 msgid "%B: Unrecognized storage class %d for %s symbol `%s'" msgstr "" -#: coffcode.h:4904 +#: coffcode.h:4755 msgid "warning: %B: local symbol `%s' has no section" msgstr "" -#: coffcode.h:5010 coff-i860.c:586 coff-tic54x.c:376 +#: coffcode.h:4859 coff-i860.c:586 coff-tic54x.c:376 msgid "%B: warning: illegal symbol index %ld in relocs" msgstr "" -#: coffcode.h:5048 +#: coffcode.h:4897 msgid "%B: illegal relocation type %d at address 0x%lx" msgstr "" -#: coffgen.c:1594 +#: coffgen.c:1511 msgid "%B: bad string table size %lu" msgstr "" @@ -406,7 +429,7 @@ msgstr "" msgid "uncertain calling convention for non-COFF symbol" msgstr "" -#: cofflink.c:507 elflink.c:3955 +#: cofflink.c:507 elflink.c:3967 msgid "Warning: type of symbol `%s' changed from %d to %d in %B" msgstr "" @@ -414,17 +437,17 @@ msgstr "" msgid "%B: relocs in section `%A', but it has no contents" msgstr "" -#: cofflink.c:2624 coffswap.h:890 +#: cofflink.c:2624 coffswap.h:823 #, c-format msgid "%s: %s: reloc overflow: 0x%lx > 0xffff" msgstr "" -#: cofflink.c:2633 coffswap.h:876 +#: cofflink.c:2633 coffswap.h:809 #, c-format msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff" msgstr "" -#: coff-m68k.c:482 elf32-m68k.c:2128 +#: coff-m68k.c:482 elf32-m68k.c:2183 msgid "unsupported reloc type" msgstr "" @@ -452,17 +475,17 @@ msgstr "" msgid "GP relative relocation when _gp not defined" msgstr "" -#: coff-rs6000.c:2783 +#: coff-rs6000.c:2785 #, c-format msgid "%s: unsupported relocation type 0x%02x" msgstr "" -#: coff-rs6000.c:2876 +#: coff-rs6000.c:2878 #, c-format msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry" msgstr "" -#: coff-tic4x.c:174 coff-tic54x.c:282 coff-tic80.c:450 +#: coff-tic4x.c:174 coff-tic54x.c:282 coff-tic80.c:458 #, c-format msgid "Unrecognized reloc type 0x%x" msgstr "" @@ -486,359 +509,380 @@ msgstr "" msgid "warning: unable to update contents of %s section in %s" msgstr "" -#: dwarf2.c:296 +#: dwarf2.c:315 msgid "Dwarf Error: Can't find .debug_str section." msgstr "" -#: dwarf2.c:314 +#: dwarf2.c:333 #, c-format msgid "" "Dwarf Error: DW_FORM_strp offset (%lu) greater than or equal to .debug_str " "size (%lu)." msgstr "" -#: dwarf2.c:388 +#: dwarf2.c:426 msgid "Dwarf Error: Can't find .debug_abbrev section." msgstr "" -#: dwarf2.c:403 +#: dwarf2.c:441 #, c-format msgid "" "Dwarf Error: Abbrev offset (%lu) greater than or equal to .debug_abbrev size " "(%lu)." msgstr "" -#: dwarf2.c:601 +#: dwarf2.c:656 #, c-format msgid "Dwarf Error: Invalid or unhandled FORM value: %u." msgstr "" -#: dwarf2.c:773 +#: dwarf2.c:857 msgid "Dwarf Error: mangled line number section (bad file number)." msgstr "" -#: dwarf2.c:866 +#: dwarf2.c:948 msgid "Dwarf Error: Can't find .debug_line section." msgstr "" -#: dwarf2.c:883 +#: dwarf2.c:965 #, c-format msgid "" "Dwarf Error: Line offset (%lu) greater than or equal to .debug_line size (%" "lu)." msgstr "" -#: dwarf2.c:1088 +#: dwarf2.c:1193 msgid "Dwarf Error: mangled line number section." msgstr "" -#: dwarf2.c:1285 dwarf2.c:1343 dwarf2.c:1498 +#: dwarf2.c:1383 +msgid "Dwarf Error: Can't find .debug_ranges section." +msgstr "" + +#: dwarf2.c:1565 dwarf2.c:1666 dwarf2.c:1896 #, c-format msgid "Dwarf Error: Could not find abbrev number %u." msgstr "" -#: dwarf2.c:1459 +#: dwarf2.c:1857 #, c-format msgid "" "Dwarf Error: found dwarf version '%u', this reader only handles version 2 " "information." msgstr "" -#: dwarf2.c:1466 +#: dwarf2.c:1864 #, c-format msgid "" "Dwarf Error: found address size '%u', this reader can not handle sizes " "greater than '%u'." msgstr "" -#: dwarf2.c:1489 +#: dwarf2.c:1887 #, c-format msgid "Dwarf Error: Bad abbrev number: %u." msgstr "" -#: ecoff.c:1269 +#: ecoff.c:1227 #, c-format msgid "Unknown basic type %d" msgstr "" -#: ecoff.c:1529 +#: ecoff.c:1484 #, c-format msgid "" "\n" " End+1 symbol: %ld" msgstr "" -#: ecoff.c:1536 ecoff.c:1539 +#: ecoff.c:1491 ecoff.c:1494 #, c-format msgid "" "\n" " First symbol: %ld" msgstr "" -#: ecoff.c:1551 +#: ecoff.c:1506 #, c-format msgid "" "\n" " End+1 symbol: %-7ld Type: %s" msgstr "" -#: ecoff.c:1558 +#: ecoff.c:1513 #, c-format msgid "" "\n" " Local symbol: %ld" msgstr "" -#: ecoff.c:1566 +#: ecoff.c:1521 #, c-format msgid "" "\n" " struct; End+1 symbol: %ld" msgstr "" -#: ecoff.c:1571 +#: ecoff.c:1526 #, c-format msgid "" "\n" " union; End+1 symbol: %ld" msgstr "" -#: ecoff.c:1576 +#: ecoff.c:1531 #, c-format msgid "" "\n" " enum; End+1 symbol: %ld" msgstr "" -#: ecoff.c:1582 +#: ecoff.c:1537 #, c-format msgid "" "\n" " Type: %s" msgstr "" -#: elf32-arm.c:1794 +#: elf32-arm.c:2305 msgid "%B: BE8 images only valid in big-endian mode." msgstr "" -#: elf32-arm.c:1953 +#: elf32-arm.c:2461 #, c-format msgid "Invalid TARGET2 relocation type '%s'." msgstr "" -#: elf32-arm.c:2060 +#: elf32-arm.c:2568 msgid "" "%B(%s): warning: interworking not enabled.\n" " first occurrence: %B: thumb call to arm" msgstr "" -#: elf32-arm.c:2476 +#: elf32-arm.c:3034 msgid "\\%B: Warning: Arm BLX instruction targets Arm function '%s'." msgstr "" -#: elf32-arm.c:2665 +#: elf32-arm.c:3217 msgid "%B: Warning: Thumb BLX instruction targets thumb function '%s'." msgstr "" -#: elf32-arm.c:3185 elf32-sh.c:4610 elf64-sh64.c:1537 +#: elf32-arm.c:3879 +msgid "%B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object" +msgstr "" + +#: elf32-arm.c:4092 elf32-sh.c:4611 elf64-sh64.c:1537 msgid "%B(%A+0x%lx): %s relocation against SEC_MERGE section" msgstr "" -#: elf32-arm.c:3277 -msgid "%B(%A): warning: unresolvable relocation %d against symbol `%s'" +#: elf32-arm.c:4153 elf64-ppc.c:9615 +msgid "%B(%A+0x%lx): %s used with TLS symbol %s" +msgstr "" + +#: elf32-arm.c:4154 elf64-ppc.c:9616 +msgid "%B(%A+0x%lx): %s used with non-TLS symbol %s" +msgstr "" + +#: elf32-arm.c:4177 +msgid "%B(%A+0x%lx): warning: unresolvable relocation %d against symbol `%s'" msgstr "" -#: elf32-arm.c:3329 elf32-avr.c:875 elf32-cr16c.c:773 elf32-cris.c:1502 -#: elf32-crx.c:911 elf32-d10v.c:564 elf32-fr30.c:595 elf32-frv.c:4107 -#: elf32-h8300.c:494 elf32-i860.c:1189 elf32-ip2k.c:1550 elf32-iq2000.c:611 -#: elf32-m32r.c:3250 elf32-m68hc1x.c:1189 elf32-msp430.c:503 -#: elf32-openrisc.c:415 elf32-v850.c:1749 elf32-xstormy16.c:954 -#: elf64-mmix.c:1517 elf-m10200.c:427 elf-m10300.c:1527 +#: elf32-arm.c:4210 elf32-avr.c:880 elf32-cr16c.c:773 elf32-cris.c:1502 +#: elf32-crx.c:911 elf32-d10v.c:536 elf32-fr30.c:595 elf32-frv.c:4107 +#: elf32-h8300.c:494 elf32-i860.c:1189 elf32-ip2k.c:1474 elf32-iq2000.c:616 +#: elf32-m32c.c:400 elf32-m32r.c:3085 elf32-m68hc1x.c:1194 elf32-ms1.c:373 +#: elf32-msp430.c:508 elf32-openrisc.c:383 elf32-v850.c:1672 +#: elf32-xstormy16.c:909 elf64-mmix.c:1517 elf-m10200.c:427 elf-m10300.c:1529 msgid "internal error: out of range error" msgstr "" -#: elf32-arm.c:3333 elf32-avr.c:879 elf32-cr16c.c:777 elf32-cris.c:1506 -#: elf32-crx.c:915 elf32-d10v.c:568 elf32-fr30.c:599 elf32-frv.c:4111 -#: elf32-h8300.c:498 elf32-i860.c:1193 elf32-iq2000.c:615 elf32-m32r.c:3254 -#: elf32-m68hc1x.c:1193 elf32-msp430.c:507 elf32-openrisc.c:419 -#: elf32-v850.c:1753 elf32-xstormy16.c:958 elf64-mmix.c:1521 elf-m10200.c:431 -#: elf-m10300.c:1531 elfxx-mips.c:7179 +#: elf32-arm.c:4214 elf32-avr.c:884 elf32-cr16c.c:777 elf32-cris.c:1506 +#: elf32-crx.c:915 elf32-d10v.c:540 elf32-fr30.c:599 elf32-frv.c:4111 +#: elf32-h8300.c:498 elf32-i860.c:1193 elf32-iq2000.c:620 elf32-m32c.c:404 +#: elf32-m32r.c:3089 elf32-m68hc1x.c:1198 elf32-msp430.c:512 +#: elf32-openrisc.c:387 elf32-v850.c:1676 elf32-xstormy16.c:913 +#: elf64-mmix.c:1521 elf-m10200.c:431 elf-m10300.c:1533 elfxx-mips.c:7198 msgid "internal error: unsupported relocation error" msgstr "" -#: elf32-arm.c:3337 elf32-cr16c.c:781 elf32-crx.c:919 elf32-d10v.c:572 -#: elf32-h8300.c:502 elf32-m32r.c:3258 elf32-m68hc1x.c:1197 elf-m10200.c:435 -#: elf-m10300.c:1535 +#: elf32-arm.c:4218 elf32-cr16c.c:781 elf32-crx.c:919 elf32-d10v.c:544 +#: elf32-h8300.c:502 elf32-m32r.c:3093 elf32-m68hc1x.c:1202 elf-m10200.c:435 +#: elf-m10300.c:1537 msgid "internal error: dangerous error" msgstr "" -#: elf32-arm.c:3341 elf32-avr.c:887 elf32-cr16c.c:785 elf32-cris.c:1514 -#: elf32-crx.c:923 elf32-d10v.c:576 elf32-fr30.c:607 elf32-frv.c:4119 -#: elf32-h8300.c:506 elf32-i860.c:1201 elf32-ip2k.c:1565 elf32-iq2000.c:623 -#: elf32-m32r.c:3262 elf32-m68hc1x.c:1201 elf32-msp430.c:515 -#: elf32-openrisc.c:427 elf32-v850.c:1773 elf32-xstormy16.c:966 -#: elf64-mmix.c:1529 elf-m10200.c:439 elf-m10300.c:1539 +#: elf32-arm.c:4222 elf32-avr.c:892 elf32-cr16c.c:785 elf32-cris.c:1514 +#: elf32-crx.c:923 elf32-d10v.c:548 elf32-fr30.c:607 elf32-frv.c:4119 +#: elf32-h8300.c:506 elf32-i860.c:1201 elf32-ip2k.c:1489 elf32-iq2000.c:628 +#: elf32-m32c.c:412 elf32-m32r.c:3097 elf32-m68hc1x.c:1206 elf32-ms1.c:381 +#: elf32-msp430.c:520 elf32-openrisc.c:395 elf32-v850.c:1696 +#: elf32-xstormy16.c:921 elf64-mmix.c:1529 elf-m10200.c:439 elf-m10300.c:1541 msgid "internal error: unknown error" msgstr "" -#: elf32-arm.c:3440 +#: elf32-arm.c:4321 msgid "" "Warning: Clearing the interworking flag of %B because non-interworking code " "in %B has been linked with it" msgstr "" -#: elf32-arm.c:3559 +#: elf32-arm.c:4440 msgid "" "ERROR: Source object %B has EABI version %d, but target %B has EABI version %" "d" msgstr "" -#: elf32-arm.c:3572 +#: elf32-arm.c:4453 msgid "ERROR: %B is compiled for APCS-%d, whereas target %B uses APCS-%d" msgstr "" -#: elf32-arm.c:3597 +#: elf32-arm.c:4478 msgid "ERROR: %B uses VFP instructions, whereas %B does not" msgstr "" -#: elf32-arm.c:3601 +#: elf32-arm.c:4482 msgid "ERROR: %B uses FPA instructions, whereas %B does not" msgstr "" -#: elf32-arm.c:3611 +#: elf32-arm.c:4492 msgid "ERROR: %B uses Maverick instructions, whereas %B does not" msgstr "" -#: elf32-arm.c:3615 +#: elf32-arm.c:4496 msgid "ERROR: %B does not use Maverick instructions, whereas %B does" msgstr "" -#: elf32-arm.c:3634 +#: elf32-arm.c:4515 msgid "ERROR: %B uses software FP, whereas %B uses hardware FP" msgstr "" -#: elf32-arm.c:3638 +#: elf32-arm.c:4519 msgid "ERROR: %B uses hardware FP, whereas %B uses software FP" msgstr "" #. Ignore init flag - it may not be set, despite the flags field #. containing valid data. #. Ignore init flag - it may not be set, despite the flags field containing valid data. -#: elf32-arm.c:3685 elf32-cris.c:3243 elf32-m68hc1x.c:1333 elf32-m68k.c:397 -#: elf32-vax.c:546 elfxx-mips.c:9846 +#: elf32-arm.c:4566 elf32-cris.c:3235 elf32-m68hc1x.c:1338 elf32-m68k.c:428 +#: elf32-vax.c:528 elfxx-mips.c:9903 #, c-format msgid "private flags = %lx:" msgstr "" -#: elf32-arm.c:3694 +#: elf32-arm.c:4575 #, c-format msgid " [interworking enabled]" msgstr "" -#: elf32-arm.c:3702 +#: elf32-arm.c:4583 #, c-format msgid " [VFP float format]" msgstr "" -#: elf32-arm.c:3704 +#: elf32-arm.c:4585 #, c-format msgid " [Maverick float format]" msgstr "" -#: elf32-arm.c:3706 +#: elf32-arm.c:4587 #, c-format msgid " [FPA float format]" msgstr "" -#: elf32-arm.c:3715 +#: elf32-arm.c:4596 #, c-format msgid " [new ABI]" msgstr "" -#: elf32-arm.c:3718 +#: elf32-arm.c:4599 #, c-format msgid " [old ABI]" msgstr "" -#: elf32-arm.c:3721 +#: elf32-arm.c:4602 #, c-format msgid " [software FP]" msgstr "" -#: elf32-arm.c:3730 +#: elf32-arm.c:4611 #, c-format msgid " [Version1 EABI]" msgstr "" -#: elf32-arm.c:3733 elf32-arm.c:3744 +#: elf32-arm.c:4614 elf32-arm.c:4625 #, c-format msgid " [sorted symbol table]" msgstr "" -#: elf32-arm.c:3735 elf32-arm.c:3746 +#: elf32-arm.c:4616 elf32-arm.c:4627 #, c-format msgid " [unsorted symbol table]" msgstr "" -#: elf32-arm.c:3741 +#: elf32-arm.c:4622 #, c-format msgid " [Version2 EABI]" msgstr "" -#: elf32-arm.c:3749 +#: elf32-arm.c:4630 #, c-format msgid " [dynamic symbols use segment index]" msgstr "" -#: elf32-arm.c:3752 +#: elf32-arm.c:4633 #, c-format msgid " [mapping symbols precede others]" msgstr "" -#: elf32-arm.c:3759 +#: elf32-arm.c:4640 #, c-format msgid " [Version3 EABI]" msgstr "" -#: elf32-arm.c:3763 +#: elf32-arm.c:4644 #, c-format msgid " [Version4 EABI]" msgstr "" -#: elf32-arm.c:3766 +#: elf32-arm.c:4647 #, c-format msgid " [BE8]" msgstr "" -#: elf32-arm.c:3769 +#: elf32-arm.c:4650 #, c-format msgid " [LE8]" msgstr "" -#: elf32-arm.c:3775 +#: elf32-arm.c:4656 #, c-format msgid " " msgstr "" -#: elf32-arm.c:3782 +#: elf32-arm.c:4663 #, c-format msgid " [relocatable executable]" msgstr "" -#: elf32-arm.c:3785 +#: elf32-arm.c:4666 #, c-format msgid " [has entry point]" msgstr "" -#: elf32-arm.c:3790 +#: elf32-arm.c:4671 #, c-format msgid "" msgstr "" -#: elf32-avr.c:883 elf32-cris.c:1510 elf32-fr30.c:603 elf32-frv.c:4115 -#: elf32-i860.c:1197 elf32-ip2k.c:1561 elf32-iq2000.c:619 elf32-msp430.c:511 -#: elf32-openrisc.c:423 elf32-v850.c:1757 elf32-xstormy16.c:962 -#: elf64-mmix.c:1525 +#: elf32-arm.c:4907 elf32-i386.c:905 elf32-s390.c:992 elf32-xtensa.c:784 +#: elf64-s390.c:945 elf64-x86-64.c:662 elfxx-sparc.c:1019 +msgid "%B: bad symbol index: %d" +msgstr "" + +#: elf32-avr.c:888 elf32-cris.c:1510 elf32-fr30.c:603 elf32-frv.c:4115 +#: elf32-i860.c:1197 elf32-ip2k.c:1485 elf32-iq2000.c:624 elf32-m32c.c:408 +#: elf32-ms1.c:377 elf32-msp430.c:516 elf32-openrisc.c:391 elf32-v850.c:1680 +#: elf32-xstormy16.c:917 elf64-mmix.c:1525 msgid "internal error: dangerous relocation" msgstr "" @@ -880,50 +924,50 @@ msgstr "" msgid "%B: Internal inconsistency; no relocation section %s" msgstr "" -#: elf32-cris.c:2507 +#: elf32-cris.c:2512 msgid "" "%B, section %A:\n" " v10/v32 compatible object %s must not contain a PIC relocation" msgstr "" -#: elf32-cris.c:2694 elf32-cris.c:2762 +#: elf32-cris.c:2699 elf32-cris.c:2767 msgid "" "%B, section %A:\n" " relocation %s should not be used in a shared object; recompile with -fPIC" msgstr "" -#: elf32-cris.c:3192 +#: elf32-cris.c:3184 msgid "Unexpected machine number" msgstr "" -#: elf32-cris.c:3246 +#: elf32-cris.c:3238 #, c-format msgid " [symbols have a _ prefix]" msgstr "" -#: elf32-cris.c:3249 +#: elf32-cris.c:3241 #, c-format msgid " [v10 and v32]" msgstr "" -#: elf32-cris.c:3252 +#: elf32-cris.c:3244 #, c-format msgid " [v32]" msgstr "" -#: elf32-cris.c:3297 +#: elf32-cris.c:3289 msgid "%B: uses _-prefixed symbols, but writing file with non-prefixed symbols" msgstr "" -#: elf32-cris.c:3298 +#: elf32-cris.c:3290 msgid "%B: uses non-prefixed symbols, but writing file with _-prefixed symbols" msgstr "" -#: elf32-cris.c:3317 +#: elf32-cris.c:3309 msgid "%B contains CRIS v32 code, incompatible with previous objects" msgstr "" -#: elf32-cris.c:3319 +#: elf32-cris.c:3311 msgid "%B contains non-CRIS-v32 code, incompatible with previous objects" msgstr "" @@ -1011,296 +1055,286 @@ msgstr "" msgid "relocation references a different segment" msgstr "" -#: elf32-frv.c:6344 +#: elf32-frv.c:6345 msgid "%B: unsupported relocation type %i" msgstr "" -#: elf32-frv.c:6662 +#: elf32-frv.c:6663 #, c-format msgid "" "%s: compiled with %s and linked with modules that use non-pic relocations" msgstr "" -#: elf32-frv.c:6715 elf32-iq2000.c:796 +#: elf32-frv.c:6716 elf32-iq2000.c:801 elf32-m32c.c:720 #, c-format msgid "%s: compiled with %s and linked with modules compiled with %s" msgstr "" -#: elf32-frv.c:6727 +#: elf32-frv.c:6728 #, c-format msgid "" "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%" "lx)" msgstr "" -#: elf32-frv.c:6748 +#: elf32-frv.c:6749 #, c-format msgid "%s: cannot link non-fdpic object file into fdpic executable" msgstr "" -#: elf32-frv.c:6752 +#: elf32-frv.c:6753 #, c-format msgid "%s: cannot link fdpic object file into non-fdpic executable" msgstr "" -#: elf32-frv.c:6777 elf32-iq2000.c:833 +#: elf32-frv.c:6778 elf32-iq2000.c:838 elf32-m32c.c:756 elf32-ms1.c:596 #, c-format msgid "private flags = 0x%lx:" msgstr "" -#: elf32-gen.c:83 elf64-gen.c:83 +#: elf32-gen.c:68 elf64-gen.c:68 msgid "%B: Relocations in generic ELF (EM: %d)" msgstr "" -#: elf32-hppa.c:542 elf32-m68hc1x.c:161 elf64-ppc.c:3644 +#: elf32-hppa.c:569 elf32-m68hc1x.c:161 elf64-ppc.c:3659 msgid "%B: cannot create stub entry %s" msgstr "" -#: elf32-hppa.c:795 elf32-hppa.c:3359 +#: elf32-hppa.c:822 elf32-hppa.c:3403 msgid "%B(%A+0x%lx): cannot reach %s, recompile with -ffunction-sections" msgstr "" -#: elf32-hppa.c:1176 +#: elf32-hppa.c:1213 msgid "" "%B: relocation %s can not be used when making a shared object; recompile " "with -fPIC" msgstr "" -#: elf32-hppa.c:1370 +#: elf32-hppa.c:1406 #, c-format msgid "Could not find relocation section for %s" msgstr "" -#: elf32-hppa.c:2623 +#: elf32-hppa.c:2669 msgid "%B: duplicate export stub %s" msgstr "" -#: elf32-hppa.c:3214 +#: elf32-hppa.c:3258 msgid "" "%B(%A+0x%lx): %s fixup for insn 0x%x is not supported in a non-shared link" msgstr "" -#: elf32-hppa.c:3844 +#: elf32-hppa.c:3887 msgid "%B(%A+0x%lx): cannot handle %s for %s" msgstr "" -#: elf32-hppa.c:4137 +#: elf32-hppa.c:4181 msgid ".got section not immediately after .plt section" msgstr "" -#: elf32-i386.c:326 +#: elf32-i386.c:327 elf32-s390.c:368 elf64-ppc.c:2123 elf64-s390.c:390 +#: elf64-x86-64.c:197 msgid "%B: invalid relocation type %d" msgstr "" -#: elf32-i386.c:865 elf32-s390.c:985 elf32-sparc.c:910 elf32-xtensa.c:788 -#: elf64-s390.c:938 elf64-x86-64.c:646 -msgid "%B: bad symbol index: %d" -msgstr "" - -#: elf32-i386.c:973 elf32-s390.c:1162 elf32-sh.c:6388 elf32-sparc.c:1033 -#: elf64-s390.c:1124 +#: elf32-i386.c:1018 elf32-s390.c:1174 elf32-sh.c:6389 elf64-s390.c:1136 +#: elfxx-sparc.c:1147 msgid "%B: `%s' accessed both as normal and thread local symbol" msgstr "" -#: elf32-i386.c:1088 elf32-s390.c:1271 elf64-ppc.c:4676 elf64-s390.c:1236 -#: elf64-x86-64.c:882 +#: elf32-i386.c:1133 elf32-s390.c:1283 elf64-ppc.c:4733 elf64-s390.c:1248 +#: elf64-x86-64.c:906 msgid "%B: bad relocation section name `%s'" msgstr "" -#: elf32-i386.c:2043 +#: elf32-i386.c:2144 msgid "%B: unrecognized relocation (0x%x) in section `%A'" msgstr "" -#: elf32-i386.c:2287 +#: elf32-i386.c:2404 msgid "" "%B: relocation R_386_GOTOFF against protected function `%s' can not be used " "when making a shared object" msgstr "" -#: elf32-i386.c:2931 elf32-m68k.c:1700 elf32-s390.c:2993 elf32-sparc.c:2859 -#: elf32-xtensa.c:2321 elf64-s390.c:2990 elf64-sparc.c:2684 -#: elf64-x86-64.c:2438 +#: elf32-i386.c:3033 elf32-m68k.c:1728 elf32-s390.c:3010 elf32-xtensa.c:2314 +#: elf64-s390.c:3007 elf64-x86-64.c:2508 elfxx-sparc.c:3134 msgid "%B(%A+0x%lx): unresolvable relocation against symbol `%s'" msgstr "" -#: elf32-i386.c:2971 elf32-m68k.c:1740 elf32-s390.c:3044 elf64-s390.c:3041 -#: elf64-x86-64.c:2482 +#: elf32-i386.c:3073 elf32-m68k.c:1768 elf32-s390.c:3061 elf64-s390.c:3058 +#: elf64-x86-64.c:2552 msgid "%B(%A+0x%lx): reloc against `%s': error %d" msgstr "" -#: elf32-ip2k.c:557 elf32-ip2k.c:563 elf32-ip2k.c:726 elf32-ip2k.c:732 +#: elf32-ip2k.c:853 elf32-ip2k.c:859 elf32-ip2k.c:926 elf32-ip2k.c:932 msgid "" "ip2k relaxer: switch table without complete matching relocation information." msgstr "" -#: elf32-ip2k.c:580 elf32-ip2k.c:759 +#: elf32-ip2k.c:876 elf32-ip2k.c:959 msgid "ip2k relaxer: switch table header corrupt." msgstr "" -#: elf32-ip2k.c:1377 +#: elf32-ip2k.c:1301 #, c-format msgid "ip2k linker: missing page instruction at 0x%08lx (dest = 0x%08lx)." msgstr "" -#: elf32-ip2k.c:1391 +#: elf32-ip2k.c:1317 #, c-format msgid "ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)." msgstr "" #. Only if it's not an unresolved symbol. -#: elf32-ip2k.c:1557 +#: elf32-ip2k.c:1481 msgid "unsupported relocation between data/insn address spaces" msgstr "" -#: elf32-iq2000.c:809 +#: elf32-iq2000.c:814 elf32-m32c.c:732 #, c-format msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" msgstr "" -#: elf32-m32r.c:1530 +#: elf32-m32r.c:1421 msgid "SDA relocation when _SDA_BASE_ not defined" msgstr "" -#: elf32-m32r.c:2604 elf64-alpha.c:4181 elf64-alpha.c:4307 elf32-ia64.c:3910 -#: elf64-ia64.c:3910 -msgid "%B: unknown relocation type %d" -msgstr "" - -#: elf32-m32r.c:2789 elf64-sh64.c:1626 elf-m10300.c:1481 +#: elf32-m32r.c:2633 elf64-sh64.c:1626 elf-m10300.c:1483 #, c-format msgid "" "%s: warning: unresolvable relocation against symbol `%s' from %s section" msgstr "" -#: elf32-m32r.c:3187 +#: elf32-m32r.c:3022 msgid "%B: The target (%s) of an %s relocation is in the wrong section (%A)" msgstr "" -#: elf32-m32r.c:3719 +#: elf32-m32r.c:3550 msgid "%B: Instruction set mismatch with previous modules" msgstr "" -#: elf32-m32r.c:3741 +#: elf32-m32r.c:3571 #, c-format msgid "private flags = %lx" msgstr "" -#: elf32-m32r.c:3746 +#: elf32-m32r.c:3576 #, c-format msgid ": m32r instructions" msgstr "" -#: elf32-m32r.c:3747 +#: elf32-m32r.c:3577 #, c-format msgid ": m32rx instructions" msgstr "" -#: elf32-m32r.c:3748 +#: elf32-m32r.c:3578 #, c-format msgid ": m32r2 instructions" msgstr "" -#: elf32-m68hc1x.c:1101 +#: elf32-m68hc1x.c:1106 #, c-format msgid "" "Reference to the far symbol `%s' using a wrong relocation may result in " "incorrect execution" msgstr "" -#: elf32-m68hc1x.c:1124 +#: elf32-m68hc1x.c:1129 #, c-format msgid "" "banked address [%lx:%04lx] (%lx) is not in the same bank as current banked " "address [%lx:%04lx] (%lx)" msgstr "" -#: elf32-m68hc1x.c:1143 +#: elf32-m68hc1x.c:1148 #, c-format msgid "" "reference to a banked address [%lx:%04lx] in the normal address space at %" "04lx" msgstr "" -#: elf32-m68hc1x.c:1276 +#: elf32-m68hc1x.c:1281 msgid "" "%B: linking files compiled for 16-bit integers (-mshort) and others for 32-" "bit integers" msgstr "" -#: elf32-m68hc1x.c:1283 +#: elf32-m68hc1x.c:1288 msgid "" "%B: linking files compiled for 32-bit double (-fshort-double) and others for " "64-bit double" msgstr "" -#: elf32-m68hc1x.c:1292 +#: elf32-m68hc1x.c:1297 msgid "%B: linking files compiled for HCS12 with others compiled for HC12" msgstr "" -#: elf32-m68hc1x.c:1308 elf32-ppc.c:2298 elf64-sparc.c:3090 elfxx-mips.c:9807 +#: elf32-m68hc1x.c:1313 elf32-ppc.c:3515 elf64-sparc.c:696 elfxx-mips.c:9864 msgid "%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" msgstr "" -#: elf32-m68hc1x.c:1336 +#: elf32-m68hc1x.c:1341 #, c-format msgid "[abi=32-bit int, " msgstr "" -#: elf32-m68hc1x.c:1338 +#: elf32-m68hc1x.c:1343 #, c-format msgid "[abi=16-bit int, " msgstr "" -#: elf32-m68hc1x.c:1341 +#: elf32-m68hc1x.c:1346 #, c-format msgid "64-bit double, " msgstr "" -#: elf32-m68hc1x.c:1343 +#: elf32-m68hc1x.c:1348 #, c-format msgid "32-bit double, " msgstr "" -#: elf32-m68hc1x.c:1346 +#: elf32-m68hc1x.c:1351 #, c-format msgid "cpu=HC11]" msgstr "" -#: elf32-m68hc1x.c:1348 +#: elf32-m68hc1x.c:1353 #, c-format msgid "cpu=HCS12]" msgstr "" -#: elf32-m68hc1x.c:1350 +#: elf32-m68hc1x.c:1355 #, c-format msgid "cpu=HC12]" msgstr "" -#: elf32-m68hc1x.c:1353 +#: elf32-m68hc1x.c:1358 #, c-format msgid " [memory=bank-model]" msgstr "" -#: elf32-m68hc1x.c:1355 +#: elf32-m68hc1x.c:1360 #, c-format msgid " [memory=flat]" msgstr "" -#: elf32-m68k.c:400 +#: elf32-m68k.c:431 #, c-format msgid " [cpu32]" msgstr "" -#: elf32-m68k.c:403 +#: elf32-m68k.c:434 #, c-format msgid " [m68000]" msgstr "" -#: elf32-mcore.c:353 elf32-mcore.c:455 +#: elf32-mcore.c:98 elf32-mcore.c:428 msgid "%B: Relocation %s (%d) is not currently supported.\n" msgstr "" -#: elf32-mcore.c:441 +#: elf32-mcore.c:414 msgid "%B: Unknown relocation type %d\n" msgstr "" @@ -1317,85 +1351,85 @@ msgstr "" msgid "Linking mips16 objects into %s format is not supported" msgstr "" -#: elf32-ppc.c:2181 +#: elf32-ppc.c:1652 #, c-format msgid "generic linker can't handle %s" msgstr "" -#: elf32-ppc.c:2263 -msgid "" -"%B: compiled with -mrelocatable and linked with modules compiled normally" +#: elf32-ppc.c:2080 +msgid "corrupt or empty %s section in %B" msgstr "" -#: elf32-ppc.c:2271 -msgid "" -"%B: compiled normally and linked with modules compiled with -mrelocatable" +#: elf32-ppc.c:2087 +msgid "unable to read in %s section from %B" msgstr "" -#: elf32-ppc.c:3526 -msgid "%B: relocation %s cannot be used when making a shared object" +#: elf32-ppc.c:2093 +msgid "corrupt %s section in %B" msgstr "" -#. It does not make sense to have a procedure linkage -#. table entry for a local symbol. -#: elf32-ppc.c:3731 -msgid "%B(%A+0x%lx): %s reloc against local symbol" +#: elf32-ppc.c:2136 +msgid "warning: unable to set size of %s section in %B" msgstr "" -#: elf32-ppc.c:4935 elf64-ppc.c:9967 -msgid "%B: unknown relocation type %d for symbol %s" +#: elf32-ppc.c:2183 +msgid "failed to allocate space for new APUinfo section." msgstr "" -#: elf32-ppc.c:5184 -msgid "%B(%A+0x%lx): non-zero addend on %s reloc against `%s'" +#: elf32-ppc.c:2202 +msgid "failed to compute new APUinfo section." msgstr "" -#: elf32-ppc.c:5510 elf32-ppc.c:5536 elf32-ppc.c:5595 -msgid "" -"%B: the target (%s) of a %s relocation is in the wrong output section (%s)" +#: elf32-ppc.c:2205 +msgid "failed to install new APUinfo section." msgstr "" -#: elf32-ppc.c:5650 -msgid "%B: relocation %s is not yet supported for symbol %s." +#: elf32-ppc.c:2936 +msgid "%B: relocation %s cannot be used when making a shared object" msgstr "" -#: elf32-ppc.c:5705 elf64-ppc.c:10606 -msgid "%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'" +#. It does not make sense to have a procedure linkage +#. table entry for a local symbol. +#: elf32-ppc.c:3152 +msgid "%B(%A+0x%lx): %s reloc against local symbol" msgstr "" -#: elf32-ppc.c:5756 elf64-ppc.c:10653 -msgid "%B(%A+0x%lx): %s reloc against `%s': error %d" +#: elf32-ppc.c:3480 +msgid "" +"%B: compiled with -mrelocatable and linked with modules compiled normally" msgstr "" -#: elf32-ppc.c:5999 -msgid "corrupt or empty %s section in %B" +#: elf32-ppc.c:3488 +msgid "" +"%B: compiled normally and linked with modules compiled with -mrelocatable" msgstr "" -#: elf32-ppc.c:6006 -msgid "unable to read in %s section from %B" +#: elf32-ppc.c:5758 elf64-ppc.c:10129 +msgid "%B: unknown relocation type %d for symbol %s" msgstr "" -#: elf32-ppc.c:6012 -msgid "corrupt %s section in %B" +#: elf32-ppc.c:6008 +msgid "%B(%A+0x%lx): non-zero addend on %s reloc against `%s'" msgstr "" -#: elf32-ppc.c:6055 -msgid "warning: unable to set size of %s section in %B" +#: elf32-ppc.c:6354 elf32-ppc.c:6376 elf32-ppc.c:6425 +msgid "" +"%B: the target (%s) of a %s relocation is in the wrong output section (%s)" msgstr "" -#: elf32-ppc.c:6104 -msgid "failed to allocate space for new APUinfo section." +#: elf32-ppc.c:6480 +msgid "%B: relocation %s is not yet supported for symbol %s." msgstr "" -#: elf32-ppc.c:6123 -msgid "failed to compute new APUinfo section." +#: elf32-ppc.c:6536 elf64-ppc.c:10768 +msgid "%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'" msgstr "" -#: elf32-ppc.c:6126 -msgid "failed to install new APUinfo section." +#: elf32-ppc.c:6585 elf64-ppc.c:10815 +msgid "%B(%A+0x%lx): %s reloc against `%s': error %d" msgstr "" -#: elf32-s390.c:2234 elf64-s390.c:2205 +#: elf32-s390.c:2251 elf64-s390.c:2222 msgid "%B(%A+0x%lx): invalid instruction for TLS relocation %s" msgstr "" @@ -1414,34 +1448,34 @@ msgstr "" msgid "%s: object size does not match that of target %s" msgstr "" -#: elf32-sh64.c:445 elf64-sh64.c:2890 +#: elf32-sh64.c:446 elf64-sh64.c:2896 #, c-format msgid "%s: encountered datalabel symbol in input" msgstr "" -#: elf32-sh64.c:522 +#: elf32-sh64.c:523 msgid "PTB mismatch: a SHmedia address (bit 0 == 1)" msgstr "" -#: elf32-sh64.c:525 +#: elf32-sh64.c:526 msgid "PTA mismatch: a SHcompact address (bit 0 == 0)" msgstr "" -#: elf32-sh64.c:543 +#: elf32-sh64.c:544 #, c-format msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16" msgstr "" -#: elf32-sh64.c:592 +#: elf32-sh64.c:593 msgid "%B: error: unaligned relocation type %d at %08x reloc %p\n" msgstr "" -#: elf32-sh64.c:668 +#: elf32-sh64.c:669 #, c-format msgid "%s: could not write out added .cranges entries" msgstr "" -#: elf32-sh64.c:728 +#: elf32-sh64.c:729 #, c-format msgid "%s: could not write out sorted .cranges entries" msgstr "" @@ -1478,31 +1512,31 @@ msgstr "" msgid "%B: 0x%lx: fatal: reloc overflow while relaxing" msgstr "" -#: elf32-sh.c:4558 elf64-sh64.c:1509 +#: elf32-sh.c:4559 elf64-sh64.c:1509 msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled" msgstr "" -#: elf32-sh.c:4709 +#: elf32-sh.c:4710 msgid "%B(%A): unresolvable relocation against symbol `%s'" msgstr "" -#: elf32-sh.c:4779 +#: elf32-sh.c:4780 msgid "%B: 0x%lx: fatal: unaligned branch target for relax-support relocation" msgstr "" -#: elf32-sh.c:4812 elf32-sh.c:4827 +#: elf32-sh.c:4813 elf32-sh.c:4828 msgid "%B: 0x%lx: fatal: unaligned %s relocation 0x%lx" msgstr "" -#: elf32-sh.c:4841 +#: elf32-sh.c:4842 msgid "%B: 0x%lx: fatal: R_SH_PSHA relocation %d not in range -32..32" msgstr "" -#: elf32-sh.c:4855 +#: elf32-sh.c:4856 msgid "%B: 0x%lx: fatal: R_SH_PSHL relocation %d not in range -32..32" msgstr "" -#: elf32-sh.c:6599 elf64-alpha.c:4725 +#: elf32-sh.c:6600 elf64-alpha.c:4486 msgid "%B: TLS local exec code cannot be linked into shared objects" msgstr "" @@ -1518,223 +1552,218 @@ msgstr "" msgid "%B: Failed to add renamed symbol %s" msgstr "" -#: elf32-sparc.c:2501 elf64-sparc.c:2340 -msgid "%B: probably compiled without -fPIC?" -msgstr "" - -#: elf32-sparc.c:3324 +#: elf32-sparc.c:87 msgid "%B: compiled for a 64 bit system and target is 32 bit" msgstr "" -#: elf32-sparc.c:3337 +#: elf32-sparc.c:100 msgid "%B: linking little endian files with big endian files" msgstr "" -#: elf32-v850.c:769 +#: elf32-v850.c:160 #, c-format msgid "Variable `%s' cannot occupy in multiple small data regions" msgstr "" -#: elf32-v850.c:772 +#: elf32-v850.c:163 #, c-format msgid "" "Variable `%s' can only be in one of the small, zero, and tiny data regions" msgstr "" -#: elf32-v850.c:775 +#: elf32-v850.c:166 #, c-format msgid "" "Variable `%s' cannot be in both small and zero data regions simultaneously" msgstr "" -#: elf32-v850.c:778 +#: elf32-v850.c:169 #, c-format msgid "" "Variable `%s' cannot be in both small and tiny data regions simultaneously" msgstr "" -#: elf32-v850.c:781 +#: elf32-v850.c:172 #, c-format msgid "" "Variable `%s' cannot be in both zero and tiny data regions simultaneously" msgstr "" -#: elf32-v850.c:1090 +#: elf32-v850.c:475 #, c-format msgid "FAILED to find previous HI16 reloc\n" msgstr "" -#: elf32-v850.c:1761 +#: elf32-v850.c:1684 msgid "could not locate special linker symbol __gp" msgstr "" -#: elf32-v850.c:1765 +#: elf32-v850.c:1688 msgid "could not locate special linker symbol __ep" msgstr "" -#: elf32-v850.c:1769 +#: elf32-v850.c:1692 msgid "could not locate special linker symbol __ctbp" msgstr "" -#: elf32-v850.c:1954 +#: elf32-v850.c:1870 msgid "%B: Architecture mismatch with previous modules" msgstr "" -#: elf32-v850.c:1975 +#: elf32-v850.c:1889 #, c-format msgid "private flags = %lx: " msgstr "" -#: elf32-v850.c:1980 +#: elf32-v850.c:1894 #, c-format msgid "v850 architecture" msgstr "" -#: elf32-v850.c:1981 +#: elf32-v850.c:1895 #, c-format msgid "v850e architecture" msgstr "" -#: elf32-v850.c:1982 +#: elf32-v850.c:1896 #, c-format msgid "v850e1 architecture" msgstr "" -#: elf32-vax.c:549 +#: elf32-vax.c:531 #, c-format msgid " [nonpic]" msgstr "" -#: elf32-vax.c:552 +#: elf32-vax.c:534 #, c-format msgid " [d-float]" msgstr "" -#: elf32-vax.c:555 +#: elf32-vax.c:537 #, c-format msgid " [g-float]" msgstr "" -#: elf32-vax.c:663 +#: elf32-vax.c:647 #, c-format msgid "" "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of " "%ld" msgstr "" -#: elf32-vax.c:1636 +#: elf32-vax.c:1597 #, c-format msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored" msgstr "" -#: elf32-vax.c:1760 +#: elf32-vax.c:1721 #, c-format msgid "%s: warning: %s relocation against symbol `%s' from %s section" msgstr "" -#: elf32-vax.c:1766 +#: elf32-vax.c:1727 #, c-format msgid "%s: warning: %s relocation to 0x%x from %s section" msgstr "" -#: elf32-xstormy16.c:462 elf32-ia64.c:2394 elf64-ia64.c:2394 +#: elf32-xstormy16.c:425 elf32-ia64.c:2546 elf64-ia64.c:2546 msgid "non-zero addend in @fptr reloc" msgstr "" -#: elf32-xtensa.c:709 +#: elf32-xtensa.c:705 msgid "%B(%A): invalid property table" msgstr "" -#: elf32-xtensa.c:2209 +#: elf32-xtensa.c:2202 msgid "%B(%A+0x%lx): relocation offset out of range (size=0x%x)" msgstr "" -#: elf32-xtensa.c:2266 +#: elf32-xtensa.c:2259 msgid "dynamic relocation in read-only section" msgstr "" -#: elf32-xtensa.c:2430 +#: elf32-xtensa.c:2423 msgid "internal inconsistency in size of .got.loc section" msgstr "" -#: elf32-xtensa.c:2744 +#: elf32-xtensa.c:2737 msgid "%B: incompatible machine type. Output is 0x%x. Input is 0x%x" msgstr "" -#: elf32-xtensa.c:3890 elf32-xtensa.c:3898 +#: elf32-xtensa.c:3883 elf32-xtensa.c:3891 msgid "Attempt to convert L32R/CALLX to CALL failed" msgstr "" -#: elf32-xtensa.c:5476 elf32-xtensa.c:5552 elf32-xtensa.c:6505 -#: elf32-xtensa.c:6559 +#: elf32-xtensa.c:5469 elf32-xtensa.c:5545 elf32-xtensa.c:6498 +#: elf32-xtensa.c:6552 msgid "" "%B(%A+0x%lx): could not decode instruction; possible configuration mismatch" msgstr "" -#: elf32-xtensa.c:6378 elf32-xtensa.c:6541 +#: elf32-xtensa.c:6371 elf32-xtensa.c:6534 msgid "" "%B(%A+0x%lx): could not decode instruction for XTENSA_ASM_SIMPLIFY " "relocation; possible configuration mismatch" msgstr "" -#: elf32-xtensa.c:7859 +#: elf32-xtensa.c:7852 msgid "invalid relocation address" msgstr "" -#: elf32-xtensa.c:7908 +#: elf32-xtensa.c:7901 msgid "overflow after relaxation" msgstr "" -#: elf32-xtensa.c:9036 +#: elf32-xtensa.c:9029 msgid "%B(%A+0x%lx): unexpected fix for %s relocation" msgstr "" -#: elf64-alpha.c:1069 +#: elf64-alpha.c:443 msgid "GPDISP relocation did not find ldah and lda instructions" msgstr "" -#: elf64-alpha.c:3557 -#, c-format -msgid "Symbol %s has no GOT subsection for offset 0x%x" -msgstr "" - -#: elf64-alpha.c:3642 +#: elf64-alpha.c:2383 msgid "%B: .got subsegment exceeds 64K (size %d)" msgstr "" -#: elf64-alpha.c:4479 elf64-alpha.c:4491 +#: elf64-alpha.c:4230 elf64-alpha.c:4242 msgid "%B: gp-relative relocation against dynamic symbol %s" msgstr "" -#: elf64-alpha.c:4517 elf64-alpha.c:4650 +#: elf64-alpha.c:4268 elf64-alpha.c:4403 msgid "%B: pc-relative relocation against dynamic symbol %s" msgstr "" -#: elf64-alpha.c:4545 +#: elf64-alpha.c:4296 msgid "%B: change in gp: BRSGP %s" msgstr "" -#: elf64-alpha.c:4570 +#: elf64-alpha.c:4321 msgid "" msgstr "" -#: elf64-alpha.c:4575 +#: elf64-alpha.c:4326 msgid "%B: !samegp reloc against symbol without .prologue: %s" msgstr "" -#: elf64-alpha.c:4626 +#: elf64-alpha.c:4378 msgid "%B: unhandled dynamic relocation against %s" msgstr "" -#: elf64-alpha.c:4709 +#: elf64-alpha.c:4410 +msgid "%B: pc-relative relocation against undefined weak symbol %s" +msgstr "" + +#: elf64-alpha.c:4470 msgid "%B: dtp-relative relocation against dynamic symbol %s" msgstr "" -#: elf64-alpha.c:4732 +#: elf64-alpha.c:4493 msgid "%B: tp-relative relocation against dynamic symbol %s" msgstr "" -#: elf64-hppa.c:2085 +#: elf64-hppa.c:2046 #, c-format msgid "stub entry for %s cannot load .plt, dp offset = %ld" msgstr "" @@ -1780,80 +1809,84 @@ msgid "" "register is $%ld." msgstr "" -#: elf64-mmix.c:2201 +#: elf64-mmix.c:2204 #, c-format msgid "" "%s: Error: multiple definition of `%s'; start of %s is set in a earlier " "linked file\n" msgstr "" -#: elf64-mmix.c:2260 +#: elf64-mmix.c:2262 msgid "Register section has contents\n" msgstr "" -#: elf64-mmix.c:2453 +#: elf64-mmix.c:2451 #, c-format msgid "" "Internal inconsistency: remaining %u != max %u.\n" " Please report this bug." msgstr "" -#: elf64-ppc.c:2490 libbfd.c:826 +#: elf64-ppc.c:2499 libbfd.c:928 msgid "%B: compiled for a big endian system and target is little endian" msgstr "" -#: elf64-ppc.c:2493 libbfd.c:828 +#: elf64-ppc.c:2502 libbfd.c:930 msgid "%B: compiled for a little endian system and target is big endian" msgstr "" -#: elf64-ppc.c:5640 +#: elf64-ppc.c:5707 #, c-format msgid "" "copy reloc against `%s' requires lazy plt linking; avoid setting " "LD_BIND_NOW=1 or upgrade gcc" msgstr "" -#: elf64-ppc.c:6043 +#: elf64-ppc.c:6133 +msgid "dynreloc miscount for %B, section %A" +msgstr "" + +#: elf64-ppc.c:6235 msgid "%B: .opd is not a regular array of opd entries" msgstr "" -#: elf64-ppc.c:6052 +#: elf64-ppc.c:6244 msgid "%B: unexpected reloc type %u in .opd section" msgstr "" -#: elf64-ppc.c:6072 +#: elf64-ppc.c:6265 msgid "%B: undefined sym `%s' in .opd section" msgstr "" -#: elf64-ppc.c:6757 elf64-ppc.c:7132 +#: elf64-ppc.c:6915 elf64-ppc.c:7294 #, c-format msgid "%s defined in removed toc entry" msgstr "" -#: elf64-ppc.c:7921 +#: elf64-ppc.c:8081 #, c-format msgid "can't find branch stub `%s'" msgstr "" -#: elf64-ppc.c:7960 elf64-ppc.c:8036 +#: elf64-ppc.c:8120 elf64-ppc.c:8196 #, c-format msgid "linkage table error against `%s'" msgstr "" -#: elf64-ppc.c:8165 +#: elf64-ppc.c:8325 #, c-format msgid "can't build branch stub `%s'" msgstr "" -#: elf64-ppc.c:9093 +#: elf64-ppc.c:9253 msgid ".glink and .plt too far apart" msgstr "" -#: elf64-ppc.c:9206 +#: elf64-ppc.c:9366 msgid "stubs don't match calculated size" msgstr "" -#: elf64-ppc.c:9218 +#: elf64-ppc.c:9378 #, c-format msgid "" "linker stubs in %u group%s\n" @@ -1864,32 +1897,24 @@ msgid "" " plt call %lu" msgstr "" -#: elf64-ppc.c:9455 -msgid "%B(%A+0x%lx): %s used with TLS symbol %s" -msgstr "" - -#: elf64-ppc.c:9456 -msgid "%B(%A+0x%lx): %s used with non-TLS symbol %s" -msgstr "" - -#: elf64-ppc.c:9856 +#: elf64-ppc.c:10018 msgid "" "%B(%A+0x%lx): automatic multiple TOCs not supported using your crt files; " "recompile with -mminimal-toc or upgrade gcc" msgstr "" -#: elf64-ppc.c:9864 +#: elf64-ppc.c:10026 msgid "" "%B(%A+0x%lx): sibling call optimization to `%s' does not allow automatic " "multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, " "or make `%s' extern" msgstr "" -#: elf64-ppc.c:10508 +#: elf64-ppc.c:10670 msgid "%B: relocation %s is not supported for symbol %s." msgstr "" -#: elf64-ppc.c:10587 +#: elf64-ppc.c:10749 msgid "%B: error: relocation %s not a multiple of %d" msgstr "" @@ -1898,148 +1923,154 @@ msgstr "" msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n" msgstr "" -#: elf64-sparc.c:1419 -msgid "%B: check_relocs: unhandled reloc type %d" -msgstr "" - -#: elf64-sparc.c:1455 +#: elf64-sparc.c:438 msgid "%B: Only registers %%g[2367] can be declared using STT_REGISTER" msgstr "" -#: elf64-sparc.c:1475 +#: elf64-sparc.c:458 msgid "Register %%g%d used incompatibly: %s in %B, previously %s in %B" msgstr "" -#: elf64-sparc.c:1498 +#: elf64-sparc.c:481 msgid "Symbol `%s' has differing types: REGISTER in %B, previously %s in %B" msgstr "" -#: elf64-sparc.c:1543 +#: elf64-sparc.c:526 msgid "Symbol `%s' has differing types: %s in %B, previously REGISTER in %B" msgstr "" -#: elf64-sparc.c:3071 +#: elf64-sparc.c:677 msgid "%B: linking UltraSPARC specific with HAL specific code" msgstr "" -#: elf64-x86-64.c:667 elf64-x86-64.c:792 elf64-x86-64.c:1988 +#: elf64-x86-64.c:688 elf64-x86-64.c:814 elf64-x86-64.c:2055 msgid "" "%B: relocation %s against `%s' can not be used when making a shared object; " "recompile with -fPIC" msgstr "" -#: elf64-x86-64.c:735 +#: elf64-x86-64.c:756 msgid "%B: %s' accessed both as normal and thread local symbol" msgstr "" -#: elf64-x86-64.c:1984 +#: elf64-x86-64.c:1986 +msgid "" +"%B: relocation R_X86_64_GOTOFF64 against protected function `%s' can not be " +"used when making a shared object" +msgstr "" + +#: elf64-x86-64.c:2051 msgid "" "%B: relocation R_X86_64_PC32 against protected function `%s' can not be used " "when making a shared object" msgstr "" -#: elf.c:296 +#: elf.c:288 msgid "%B: invalid string offset %u >= %lu for section `%s'" msgstr "" -#: elf.c:543 +#: elf.c:552 msgid "%B: invalid SHT_GROUP entry" msgstr "" -#: elf.c:613 +#: elf.c:622 msgid "%B: no group info for section %A" msgstr "" -#: elf.c:650 +#: elf.c:659 msgid "%B: unknown [%d] section `%s' in group [%s]" msgstr "" -#: elf.c:1011 +#: elf.c:1042 #, c-format msgid "" "\n" "Program Header:\n" msgstr "" -#: elf.c:1063 +#: elf.c:1094 #, c-format msgid "" "\n" "Dynamic Section:\n" msgstr "" -#: elf.c:1188 +#: elf.c:1219 #, c-format msgid "" "\n" "Version definitions:\n" msgstr "" -#: elf.c:1211 +#: elf.c:1244 #, c-format msgid "" "\n" "Version References:\n" msgstr "" -#: elf.c:1216 +#: elf.c:1249 #, c-format msgid " required from %s:\n" msgstr "" -#: elf.c:1905 +#: elf.c:1958 msgid "%B: invalid link %lu for reloc section %s (index %u)" msgstr "" -#: elf.c:2910 -msgid "%B: warning: sh_link not set for section `%S'" +#: elf.c:3095 elflink.c:7621 +msgid "%B: warning: sh_link not set for section `%A'" +msgstr "" + +#: elf.c:3105 +msgid "%B: sh_link of section `%A' points to discarded section `%A' of `%B'" msgstr "" -#: elf.c:3904 +#: elf.c:4103 msgid "%B: Not enough room for program headers (allocated %u, need %u)" msgstr "" -#: elf.c:4010 +#: elf.c:4206 msgid "" "%B: The first section in the PT_DYNAMIC segment is not the .dynamic section" msgstr "" -#: elf.c:4054 +#: elf.c:4250 msgid "%B: Not enough room for program headers, try linking with -N" msgstr "" -#: elf.c:4145 +#: elf.c:4341 msgid "%B: section %A lma 0x%lx overlaps previous sections" msgstr "" -#: elf.c:4546 +#: elf.c:4742 msgid "%B: warning: allocated section `%s' not in segment" msgstr "" -#: elf.c:4850 +#: elf.c:5035 msgid "%B: symbol `%s' required but not present" msgstr "" -#: elf.c:5147 +#: elf.c:5332 msgid "%B: warning: Empty loadable segment detected, is this intentional ?\n" msgstr "" -#: elf.c:5761 +#: elf.c:5950 #, c-format msgid "" "Unable to find equivalent output section for symbol '%s' from section '%s'" msgstr "" -#: elf.c:6620 +#: elf.c:6906 msgid "%B: unsupported relocation type %s" msgstr "" -#: elfcode.h:1039 +#: elfcode.h:1110 #, c-format msgid "%s: version count (%ld) does not match symbol count (%ld)" msgstr "" -#: elfcode.h:1266 +#: elfcode.h:1337 #, c-format msgid "%s(%s): relocation %d has invalid symbol index %ld" msgstr "" @@ -2048,299 +2079,314 @@ msgstr "" msgid "%B(%A): warning: unresolvable relocation against symbol `%s'" msgstr "" -#: elflink.c:941 +#: elflink.c:942 msgid "" "%s: TLS definition in %B section %A mismatches non-TLS definition in %B " "section %A" msgstr "" -#: elflink.c:945 +#: elflink.c:946 msgid "%s: TLS reference in %B mismatches non-TLS reference in %B" msgstr "" -#: elflink.c:949 +#: elflink.c:950 msgid "%s: TLS definition in %B section %A mismatches non-TLS reference in %B" msgstr "" -#: elflink.c:953 +#: elflink.c:954 msgid "%s: TLS reference in %B mismatches non-TLS definition in %B section %A" msgstr "" -#: elflink.c:1508 +#: elflink.c:1513 msgid "%B: unexpected redefinition of indirect versioned symbol `%s'" msgstr "" -#: elflink.c:1825 +#: elflink.c:1829 msgid "%B: undefined versioned symbol name %s" msgstr "" -#: elflink.c:1974 +#: elflink.c:1977 msgid "" "%B: bad reloc symbol index (0x%lx >= 0x%lx) for offset 0x%lx in section `%A'" msgstr "" -#: elflink.c:2164 +#: elflink.c:2169 msgid "%B: relocation size mismatch in %B section %A" msgstr "" -#: elflink.c:2454 +#: elflink.c:2459 #, c-format msgid "warning: type and size of dynamic symbol `%s' are not defined" msgstr "" -#: elflink.c:2775 +#: elflink.c:2780 msgid "warning: creating a DT_TEXTREL in a shared object." msgstr "" -#: elflink.c:3702 +#: elflink.c:3714 msgid "%B: %s: invalid version %u (max %d)" msgstr "" -#: elflink.c:3738 +#: elflink.c:3750 msgid "%B: %s: invalid needed version %d" msgstr "" -#: elflink.c:3919 +#: elflink.c:3931 msgid "Warning: alignment %u of symbol `%s' in %B is smaller than %u in %B" msgstr "" -#: elflink.c:3931 +#: elflink.c:3943 msgid "Warning: size of symbol `%s' changed from %lu in %B to %lu in %B" msgstr "" -#: elflink.c:4098 +#: elflink.c:4110 #, c-format msgid "%s: invalid DSO for symbol `%s' definition" msgstr "" -#: elflink.c:5155 +#: elflink.c:5170 #, c-format msgid "%s: undefined version: %s" msgstr "" -#: elflink.c:5221 +#: elflink.c:5236 msgid "%B: .preinit_array section is not allowed in DSO" msgstr "" -#: elflink.c:5961 +#: elflink.c:5993 msgid "Not enough memory to sort relocations" msgstr "" -#: elflink.c:6352 +#: elflink.c:6384 msgid "%B: %s symbol `%s' in %B is referenced by DSO" msgstr "" -#: elflink.c:6433 +#: elflink.c:6467 msgid "%B: could not find output section %A for input section %A" msgstr "" -#: elflink.c:6530 +#: elflink.c:6564 msgid "%B: %s symbol `%s' isn't defined" msgstr "" -#: elflink.c:7017 +#: elflink.c:7057 msgid "" -"`%s' referenced in section `%A' of %B: defined in discarded section `%A' of %" -"B\n" +"error: %B contains a reloc (0x%s) for section %A that references a non-" +"existent global symbol" msgstr "" -#: elflink.c:7551 -msgid "%B: warning: sh_link not set for section `%A'" +#: elflink.c:7091 +msgid "" +"%X`%s' referenced in section `%A' of %B: defined in discarded section `%A' " +"of %B" msgstr "" -#: elflink.c:7624 +#: elflink.c:7694 #, c-format msgid "%A has both ordered and unordered sections" msgstr "" -#: elflink.c:8437 elflink.c:8478 +#: elflink.c:8507 elflink.c:8548 msgid "%B: could not find output section %s" msgstr "" -#: elflink.c:8442 +#: elflink.c:8512 #, c-format msgid "warning: %s section has zero size" msgstr "" -#: elflink.c:9017 +#: elflink.c:9128 msgid "Warning: gc-sections option ignored" msgstr "" -#: elflink.c:9606 -msgid "%B: ignoring duplicate section `%A'\n" +#: elflink.c:9708 +msgid "%B: ignoring duplicate section `%A'" msgstr "" -#: elflink.c:9613 elflink.c:9620 -msgid "%B: duplicate section `%A' has different size\n" +#: elflink.c:9715 elflink.c:9722 +msgid "%B: duplicate section `%A' has different size" msgstr "" -#: elflink.c:9628 elflink.c:9633 -msgid "%B: warning: could not read contents of section `%A'\n" +#: elflink.c:9730 elflink.c:9735 +msgid "%B: warning: could not read contents of section `%A'" msgstr "" -#: elflink.c:9637 -msgid "%B: warning: duplicate section `%A' has different contents\n" +#: elflink.c:9739 +msgid "%B: warning: duplicate section `%A' has different contents" msgstr "" -#: elfxx-mips.c:860 +#: elfxx-mips.c:866 msgid "static procedure (no name)" msgstr "" -#: elfxx-mips.c:2508 +#: elfxx-mips.c:2513 msgid "not enough GOT space for local GOT entries" msgstr "" -#: elfxx-mips.c:4353 +#: elfxx-mips.c:4356 msgid "%B: %A+0x%lx: jump to stub routine which is not jal" msgstr "" -#: elfxx-mips.c:5919 +#: elfxx-mips.c:4993 elfxx-mips.c:5214 +msgid "%B: Warning: bad `%s' option size %u smaller than its header" +msgstr "" + +#: elfxx-mips.c:5951 msgid "%B: Malformed reloc detected for section %s" msgstr "" -#: elfxx-mips.c:5995 +#: elfxx-mips.c:6027 msgid "%B: CALL16 reloc at 0x%lx not against global symbol" msgstr "" -#: elfxx-mips.c:9308 +#: elfxx-mips.c:9365 #, c-format msgid "%s: illegal section name `%s'" msgstr "" -#: elfxx-mips.c:9632 +#: elfxx-mips.c:9689 msgid "%B: endianness incompatible with that of the selected emulation" msgstr "" -#: elfxx-mips.c:9644 +#: elfxx-mips.c:9701 msgid "%B: ABI is incompatible with that of the selected emulation" msgstr "" -#: elfxx-mips.c:9716 +#: elfxx-mips.c:9773 msgid "%B: warning: linking PIC files with non-PIC files" msgstr "" -#: elfxx-mips.c:9733 +#: elfxx-mips.c:9790 msgid "%B: linking 32-bit code with 64-bit code" msgstr "" -#: elfxx-mips.c:9761 +#: elfxx-mips.c:9818 msgid "%B: linking %s module with previous %s modules" msgstr "" -#: elfxx-mips.c:9784 +#: elfxx-mips.c:9841 msgid "%B: ABI mismatch: linking %s module with previous %s modules" msgstr "" -#: elfxx-mips.c:9849 +#: elfxx-mips.c:9906 #, c-format msgid " [abi=O32]" msgstr "" -#: elfxx-mips.c:9851 +#: elfxx-mips.c:9908 #, c-format msgid " [abi=O64]" msgstr "" -#: elfxx-mips.c:9853 +#: elfxx-mips.c:9910 #, c-format msgid " [abi=EABI32]" msgstr "" -#: elfxx-mips.c:9855 +#: elfxx-mips.c:9912 #, c-format msgid " [abi=EABI64]" msgstr "" -#: elfxx-mips.c:9857 +#: elfxx-mips.c:9914 #, c-format msgid " [abi unknown]" msgstr "" -#: elfxx-mips.c:9859 +#: elfxx-mips.c:9916 #, c-format msgid " [abi=N32]" msgstr "" -#: elfxx-mips.c:9861 +#: elfxx-mips.c:9918 #, c-format msgid " [abi=64]" msgstr "" -#: elfxx-mips.c:9863 +#: elfxx-mips.c:9920 #, c-format msgid " [no abi set]" msgstr "" -#: elfxx-mips.c:9866 +#: elfxx-mips.c:9923 #, c-format msgid " [mips1]" msgstr "" -#: elfxx-mips.c:9868 +#: elfxx-mips.c:9925 #, c-format msgid " [mips2]" msgstr "" -#: elfxx-mips.c:9870 +#: elfxx-mips.c:9927 #, c-format msgid " [mips3]" msgstr "" -#: elfxx-mips.c:9872 +#: elfxx-mips.c:9929 #, c-format msgid " [mips4]" msgstr "" -#: elfxx-mips.c:9874 +#: elfxx-mips.c:9931 #, c-format msgid " [mips5]" msgstr "" -#: elfxx-mips.c:9876 +#: elfxx-mips.c:9933 #, c-format msgid " [mips32]" msgstr "" -#: elfxx-mips.c:9878 +#: elfxx-mips.c:9935 #, c-format msgid " [mips64]" msgstr "" -#: elfxx-mips.c:9880 +#: elfxx-mips.c:9937 #, c-format msgid " [mips32r2]" msgstr "" -#: elfxx-mips.c:9882 +#: elfxx-mips.c:9939 #, c-format msgid " [mips64r2]" msgstr "" -#: elfxx-mips.c:9884 +#: elfxx-mips.c:9941 #, c-format msgid " [unknown ISA]" msgstr "" -#: elfxx-mips.c:9887 +#: elfxx-mips.c:9944 #, c-format msgid " [mdmx]" msgstr "" -#: elfxx-mips.c:9890 +#: elfxx-mips.c:9947 #, c-format msgid " [mips16]" msgstr "" -#: elfxx-mips.c:9893 +#: elfxx-mips.c:9950 #, c-format msgid " [32bitmode]" msgstr "" -#: elfxx-mips.c:9895 +#: elfxx-mips.c:9952 #, c-format msgid " [not 32bitmode]" msgstr "" +#: elfxx-sparc.c:402 +#, c-format +msgid "invalid relocation type %d" +msgstr "" + +#: elfxx-sparc.c:2780 +msgid "%B: probably compiled without -fPIC?" +msgstr "" + #: i386linux.c:457 m68klinux.c:461 sparclinux.c:458 #, c-format msgid "Output file requires shared library `%s'\n" @@ -2361,75 +2407,75 @@ msgstr "" msgid "Warning: fixup count mismatch\n" msgstr "" -#: ieee.c:293 +#: ieee.c:157 #, c-format msgid "%s: string too long (%d chars, max 65535)" msgstr "" -#: ieee.c:428 +#: ieee.c:284 #, c-format msgid "%s: unrecognized symbol `%s' flags 0x%x" msgstr "" -#: ieee.c:938 +#: ieee.c:786 msgid "%B: unimplemented ATI record %u for symbol %u" msgstr "" -#: ieee.c:962 +#: ieee.c:810 msgid "%B: unexpected ATN type %d in external part" msgstr "" -#: ieee.c:984 +#: ieee.c:832 msgid "%B: unexpected type after ATN" msgstr "" -#: ihex.c:264 +#: ihex.c:228 msgid "%B:%d: unexpected character `%s' in Intel Hex file" msgstr "" -#: ihex.c:372 +#: ihex.c:335 msgid "%B:%u: bad checksum in Intel Hex file (expected %u, found %u)" msgstr "" -#: ihex.c:426 +#: ihex.c:389 msgid "%B:%u: bad extended address record length in Intel Hex file" msgstr "" -#: ihex.c:443 +#: ihex.c:406 msgid "%B:%u: bad extended start address length in Intel Hex file" msgstr "" -#: ihex.c:460 +#: ihex.c:423 msgid "%B:%u: bad extended linear address record length in Intel Hex file" msgstr "" -#: ihex.c:477 +#: ihex.c:440 msgid "%B:%u: bad extended linear start address length in Intel Hex file" msgstr "" -#: ihex.c:494 +#: ihex.c:457 msgid "%B:%u: unrecognized ihex type %u in Intel Hex file" msgstr "" -#: ihex.c:619 +#: ihex.c:578 msgid "%B: internal error in ihex_read_section" msgstr "" -#: ihex.c:653 +#: ihex.c:612 msgid "%B: bad section length in ihex_read_section" msgstr "" -#: ihex.c:870 +#: ihex.c:824 #, c-format msgid "%s: address 0x%s out of range for Intel Hex file" msgstr "" -#: libbfd.c:856 +#: libbfd.c:958 #, c-format msgid "Deprecated %s called at %s line %d in %s\n" msgstr "" -#: libbfd.c:859 +#: libbfd.c:961 #, c-format msgid "Deprecated %s called\n" msgstr "" @@ -2438,20 +2484,20 @@ msgstr "" msgid "%B: indirect symbol `%s' to `%s' is a loop" msgstr "" -#: linker.c:2741 +#: linker.c:2743 #, c-format msgid "Attempt to do relocatable link with %s input and %s output" msgstr "" -#: linker.c:3038 +#: linker.c:3040 msgid "%B: warning: ignoring duplicate section `%A'\n" msgstr "" -#: linker.c:3052 +#: linker.c:3054 msgid "%B: warning: duplicate section `%A' has different size\n" msgstr "" -#: merge.c:796 +#: merge.c:817 #, c-format msgid "%s: access beyond end of merged section (%ld)" msgstr "" @@ -2598,7 +2644,7 @@ msgid "" "08lx\n" msgstr "" -#: oasys.c:1033 +#: oasys.c:874 #, c-format msgid "%s: can not represent section `%s' in oasys" msgstr "" @@ -2609,122 +2655,121 @@ msgid "Unhandled OSF/1 core file section msgstr "" #. XXX code yet to be written. -#: peicode.h:760 +#: peicode.h:731 msgid "%B: Unhandled import type; %x" msgstr "" -#: peicode.h:765 +#: peicode.h:736 msgid "%B: Unrecognised import type; %x" msgstr "" -#: peicode.h:779 +#: peicode.h:750 msgid "%B: Unrecognised import name type; %x" msgstr "" -#: peicode.h:1169 +#: peicode.h:1120 msgid "%B: Unrecognised machine type (0x%x) in Import Library Format archive" msgstr "" -#: peicode.h:1181 +#: peicode.h:1132 msgid "" "%B: Recognised but unhandled machine type (0x%x) in Import Library Format " "archive" msgstr "" -#: peicode.h:1199 +#: peicode.h:1150 msgid "%B: size field is zero in Import Library Format header" msgstr "" -#: peicode.h:1230 +#: peicode.h:1181 msgid "%B: string not null terminated in ILF object file." msgstr "" -#: pe-mips.c:627 +#: pe-mips.c:588 msgid "%B: `ld -r' not supported with PE MIPS objects\n" msgstr "" #. OK, at this point the following variables are set up: #. src = VMA of the memory we're fixing up #. mem = pointer to memory we're fixing up -#. val = VMA of what we need to refer to -#. -#: pe-mips.c:749 +#. val = VMA of what we need to refer to. +#: pe-mips.c:704 msgid "%B: unimplemented %s\n" msgstr "" -#: pe-mips.c:775 +#: pe-mips.c:730 msgid "%B: jump too far away\n" msgstr "" -#: pe-mips.c:801 +#: pe-mips.c:756 msgid "%B: bad pair/reflo after refhi\n" msgstr "" -#: ppcboot.c:418 +#: ppcboot.c:419 #, c-format msgid "" "\n" "ppcboot header:\n" msgstr "" -#: ppcboot.c:419 +#: ppcboot.c:420 #, c-format msgid "Entry offset = 0x%.8lx (%ld)\n" msgstr "" -#: ppcboot.c:420 +#: ppcboot.c:421 #, c-format msgid "Length = 0x%.8lx (%ld)\n" msgstr "" -#: ppcboot.c:423 +#: ppcboot.c:424 #, c-format msgid "Flag field = 0x%.2x\n" msgstr "" -#: ppcboot.c:429 +#: ppcboot.c:430 #, c-format msgid "Partition name = \"%s\"\n" msgstr "" -#: ppcboot.c:448 +#: ppcboot.c:449 #, c-format msgid "" "\n" "Partition[%d] start = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" msgstr "" -#: ppcboot.c:454 +#: ppcboot.c:455 #, c-format msgid "Partition[%d] end = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" msgstr "" -#: ppcboot.c:460 +#: ppcboot.c:461 #, c-format msgid "Partition[%d] sector = 0x%.8lx (%ld)\n" msgstr "" -#: ppcboot.c:461 +#: ppcboot.c:462 #, c-format msgid "Partition[%d] length = 0x%.8lx (%ld)\n" msgstr "" -#: som.c:5269 +#: som.c:5069 #, c-format msgid "" "\n" "Exec Auxiliary Header\n" msgstr "" -#: som.c:5543 +#: som.c:5330 msgid "som_sizeof_headers unimplemented" msgstr "" -#: srec.c:302 +#: srec.c:259 msgid "%B:%d: Unexpected character `%s' in S-record file\n" msgstr "" -#: stabs.c:296 +#: stabs.c:276 msgid "%B(%A+0x%lx): Stabs entry has invalid string index." msgstr "" @@ -2732,118 +2777,118 @@ msgstr "" msgid "Unsupported .stab relocation" msgstr "" -#: vms-gsd.c:356 +#: vms-gsd.c:337 #, c-format msgid "bfd_make_section (%s) failed" msgstr "" -#: vms-gsd.c:371 +#: vms-gsd.c:352 #, c-format msgid "bfd_set_section_flags (%s, %x) failed" msgstr "" -#: vms-gsd.c:407 +#: vms-gsd.c:387 #, c-format msgid "Size mismatch section %s=%lx, %s=%lx" msgstr "" -#: vms-gsd.c:702 +#: vms-gsd.c:678 #, c-format msgid "unknown gsd/egsd subtype %d" msgstr "" -#: vms-hdr.c:409 +#: vms-hdr.c:327 msgid "Object module NOT error-free !\n" msgstr "" -#: vms-misc.c:541 +#: vms-misc.c:473 #, c-format msgid "Stack overflow (%d) in _bfd_vms_push" msgstr "" -#: vms-misc.c:559 +#: vms-misc.c:488 msgid "Stack underflow in _bfd_vms_pop" msgstr "" -#: vms-misc.c:912 +#: vms-misc.c:802 msgid "_bfd_vms_output_counted called with zero bytes" msgstr "" -#: vms-misc.c:917 +#: vms-misc.c:807 msgid "_bfd_vms_output_counted called with too many bytes" msgstr "" -#: vms-misc.c:1048 +#: vms-misc.c:925 #, c-format msgid "Symbol %s replaced by %s\n" msgstr "" -#: vms-misc.c:1111 +#: vms-misc.c:984 #, c-format msgid "failed to enter %s" msgstr "" -#: vms-tir.c:102 +#: vms-tir.c:55 msgid "No Mem !" msgstr "" -#: vms-tir.c:383 +#: vms-tir.c:298 #, c-format msgid "bad section index in %s" msgstr "" -#: vms-tir.c:396 +#: vms-tir.c:311 #, c-format msgid "unsupported STA cmd %s" msgstr "" -#: vms-tir.c:401 vms-tir.c:1247 +#: vms-tir.c:316 vms-tir.c:1118 #, c-format msgid "reserved STA cmd %d" msgstr "" -#: vms-tir.c:502 vms-tir.c:525 +#: vms-tir.c:408 vms-tir.c:430 #, c-format msgid "%s: no symbol \"%s\"" msgstr "" -#. unsigned shift -#. rotate +#. Unsigned shift. +#. Rotate. #. Redefine symbol to current location. #. Define a literal. -#: vms-tir.c:592 vms-tir.c:704 vms-tir.c:814 vms-tir.c:832 vms-tir.c:840 -#: vms-tir.c:849 vms-tir.c:1570 +#: vms-tir.c:495 vms-tir.c:604 vms-tir.c:702 vms-tir.c:719 vms-tir.c:726 +#: vms-tir.c:734 vms-tir.c:1438 #, c-format msgid "%s: not supported" msgstr "" -#: vms-tir.c:597 vms-tir.c:1425 +#: vms-tir.c:500 vms-tir.c:1295 #, c-format msgid "%s: not implemented" msgstr "" -#: vms-tir.c:601 vms-tir.c:1429 +#: vms-tir.c:504 vms-tir.c:1299 #, c-format msgid "reserved STO cmd %d" msgstr "" -#: vms-tir.c:719 vms-tir.c:1575 +#: vms-tir.c:619 vms-tir.c:1443 #, c-format msgid "reserved OPR cmd %d" msgstr "" -#: vms-tir.c:787 vms-tir.c:1639 +#: vms-tir.c:679 vms-tir.c:1507 #, c-format msgid "reserved CTL cmd %d" msgstr "" #. stack byte from image #. arg: none. -#: vms-tir.c:1155 +#: vms-tir.c:1026 msgid "stack-from-image not implemented" msgstr "" -#: vms-tir.c:1173 +#: vms-tir.c:1044 msgid "stack-entry-mask not fully implemented" msgstr "" @@ -2854,346 +2899,346 @@ msgstr "" #. #. compare argument descriptor with symbol argument (ARG$V_PASSMECH) #. and stack TRUE (args match) or FALSE (args dont match) value. -#: vms-tir.c:1187 +#: vms-tir.c:1058 msgid "PASSMECH not fully implemented" msgstr "" -#: vms-tir.c:1206 +#: vms-tir.c:1077 msgid "stack-local-symbol not fully implemented" msgstr "" -#: vms-tir.c:1219 +#: vms-tir.c:1090 msgid "stack-literal not fully implemented" msgstr "" -#: vms-tir.c:1240 +#: vms-tir.c:1111 msgid "stack-local-symbol-entry-point-mask not fully implemented" msgstr "" -#: vms-tir.c:1517 vms-tir.c:1529 vms-tir.c:1541 vms-tir.c:1553 vms-tir.c:1618 -#: vms-tir.c:1626 vms-tir.c:1634 +#: vms-tir.c:1385 vms-tir.c:1397 vms-tir.c:1409 vms-tir.c:1421 vms-tir.c:1486 +#: vms-tir.c:1494 vms-tir.c:1502 #, c-format msgid "%s: not fully implemented" msgstr "" -#: vms-tir.c:1691 +#: vms-tir.c:1560 #, c-format msgid "obj code %d not found" msgstr "" -#: vms-tir.c:2029 +#: vms-tir.c:1868 #, c-format msgid "SEC_RELOC with no relocs in section %s" msgstr "" -#: vms-tir.c:2304 +#: vms-tir.c:2150 #, c-format msgid "Unhandled relocation %s" msgstr "" -#: xcofflink.c:1243 +#: xcofflink.c:564 +#, c-format +msgid "%s: XCOFF shared object when not producing XCOFF output" +msgstr "" + +#: xcofflink.c:585 +#, c-format +msgid "%s: dynamic object with no .loader section" +msgstr "" + +#: xcofflink.c:1148 msgid "%B: `%s' has line numbers but no enclosing section" msgstr "" -#: xcofflink.c:1296 +#: xcofflink.c:1200 msgid "%B: class %d symbol `%s' has no aux entries" msgstr "" -#: xcofflink.c:1319 +#: xcofflink.c:1223 msgid "%B: symbol `%s' has unrecognized csect type %d" msgstr "" -#: xcofflink.c:1331 +#: xcofflink.c:1235 msgid "%B: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d" msgstr "" -#: xcofflink.c:1367 +#: xcofflink.c:1271 msgid "%B: XMC_TC0 symbol `%s' is class %d scnlen %d" msgstr "" -#: xcofflink.c:1518 +#: xcofflink.c:1417 msgid "%B: csect `%s' not in enclosing section" msgstr "" -#: xcofflink.c:1625 +#: xcofflink.c:1524 msgid "%B: misplaced XTY_LD `%s'" msgstr "" -#: xcofflink.c:1956 +#: xcofflink.c:1839 msgid "%B: reloc %s:%d not in csect" msgstr "" -#: xcofflink.c:2093 -#, c-format -msgid "%s: XCOFF shared object when not producing XCOFF output" -msgstr "" - -#: xcofflink.c:2114 +#: xcofflink.c:2637 #, c-format -msgid "%s: dynamic object with no .loader section" +msgid "%s: no such symbol" msgstr "" -#: xcofflink.c:2759 +#: xcofflink.c:2866 #, c-format -msgid "%s: no such symbol" +msgid "warning: attempt to export undefined symbol `%s'" msgstr "" -#: xcofflink.c:2892 +#: xcofflink.c:3033 msgid "error: undefined symbol __rtinit" msgstr "" -#: xcofflink.c:3449 -#, c-format -msgid "warning: attempt to export undefined symbol `%s'" -msgstr "" - -#: xcofflink.c:4444 +#: xcofflink.c:3653 #, c-format msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling" msgstr "" -#: xcofflink.c:5285 +#: xcofflink.c:4489 msgid "%B: loader reloc in unrecognized section `%A'" msgstr "" -#: xcofflink.c:5306 +#: xcofflink.c:4510 msgid "%B: `%s' in loader reloc but not loader sym" msgstr "" -#: xcofflink.c:5321 +#: xcofflink.c:4525 msgid "%B: loader reloc in read-only section %A" msgstr "" -#: xcofflink.c:5747 xcofflink.c:5809 xcofflink.c:6111 +#: xcofflink.c:4934 xcofflink.c:4996 xcofflink.c:5291 #, c-format msgid "%s: loader reloc in unrecognized section `%s'" msgstr "" -#: xcofflink.c:6122 +#: xcofflink.c:5302 #, c-format msgid "%s: `%s' in loader reloc but not loader sym" msgstr "" -#: elf32-ia64.c:987 elf64-ia64.c:987 +#: elf32-ia64.c:1138 elf64-ia64.c:1138 msgid "" "%B: Can't relax br at 0x%lx in section `%A'. Please use brl or indirect " "branch." msgstr "" -#: elf32-ia64.c:2339 elf64-ia64.c:2339 +#: elf32-ia64.c:2491 elf64-ia64.c:2491 msgid "@pltoff reloc against local symbol" msgstr "" -#: elf32-ia64.c:3757 elf64-ia64.c:3757 +#: elf32-ia64.c:3932 elf64-ia64.c:3932 #, c-format msgid "%s: short data segment overflowed (0x%lx >= 0x400000)" msgstr "" -#: elf32-ia64.c:3768 elf64-ia64.c:3768 +#: elf32-ia64.c:3943 elf64-ia64.c:3943 #, c-format msgid "%s: __gp does not cover short data segment" msgstr "" -#: elf32-ia64.c:4015 elf64-ia64.c:4015 +#: elf32-ia64.c:4190 elf64-ia64.c:4190 msgid "%B: non-pic code with imm relocation against dynamic symbol `%s'" msgstr "" -#: elf32-ia64.c:4080 elf64-ia64.c:4080 +#: elf32-ia64.c:4257 elf64-ia64.c:4257 msgid "%B: @gprel relocation against dynamic symbol %s" msgstr "" -#: elf32-ia64.c:4140 elf64-ia64.c:4140 +#: elf32-ia64.c:4320 elf64-ia64.c:4320 msgid "%B: linking non-pic code in a position independent executable" msgstr "" -#: elf32-ia64.c:4277 elf64-ia64.c:4277 +#: elf32-ia64.c:4457 elf64-ia64.c:4457 msgid "%B: @internal branch to dynamic symbol %s" msgstr "" -#: elf32-ia64.c:4279 elf64-ia64.c:4279 +#: elf32-ia64.c:4459 elf64-ia64.c:4459 msgid "%B: speculation fixup to dynamic symbol %s" msgstr "" -#: elf32-ia64.c:4281 elf64-ia64.c:4281 +#: elf32-ia64.c:4461 elf64-ia64.c:4461 msgid "%B: @pcrel relocation against dynamic symbol %s" msgstr "" -#: elf32-ia64.c:4488 elf64-ia64.c:4488 +#: elf32-ia64.c:4668 elf64-ia64.c:4668 msgid "unsupported reloc" msgstr "" -#: elf32-ia64.c:4528 elf64-ia64.c:4528 +#: elf32-ia64.c:4701 elf64-ia64.c:4701 msgid "" "%B: Can't relax br (%s) to `%s' at 0x%lx in section `%A' with size 0x%lx (> " "0x1000000)." msgstr "" -#: elf32-ia64.c:4789 elf64-ia64.c:4789 +#: elf32-ia64.c:4962 elf64-ia64.c:4962 msgid "%B: linking trap-on-NULL-dereference with non-trapping files" msgstr "" -#: elf32-ia64.c:4798 elf64-ia64.c:4798 +#: elf32-ia64.c:4971 elf64-ia64.c:4971 msgid "%B: linking big-endian files with little-endian files" msgstr "" -#: elf32-ia64.c:4807 elf64-ia64.c:4807 +#: elf32-ia64.c:4980 elf64-ia64.c:4980 msgid "%B: linking 64-bit files with 32-bit files" msgstr "" -#: elf32-ia64.c:4816 elf64-ia64.c:4816 +#: elf32-ia64.c:4989 elf64-ia64.c:4989 msgid "%B: linking constant-gp files with non-constant-gp files" msgstr "" -#: elf32-ia64.c:4826 elf64-ia64.c:4826 +#: elf32-ia64.c:4999 elf64-ia64.c:4999 msgid "%B: linking auto-pic files with non-auto-pic files" msgstr "" -#: peigen.c:1014 pepigen.c:1014 +#: peigen.c:979 pepigen.c:979 #, c-format msgid "%s: line number overflow: 0x%lx > 0xffff" msgstr "" -#: peigen.c:1041 pepigen.c:1041 +#: peigen.c:1006 pepigen.c:1006 msgid "Export Directory [.edata (or where ever we found it)]" msgstr "" -#: peigen.c:1042 pepigen.c:1042 +#: peigen.c:1007 pepigen.c:1007 msgid "Import Directory [parts of .idata]" msgstr "" -#: peigen.c:1043 pepigen.c:1043 +#: peigen.c:1008 pepigen.c:1008 msgid "Resource Directory [.rsrc]" msgstr "" -#: peigen.c:1044 pepigen.c:1044 +#: peigen.c:1009 pepigen.c:1009 msgid "Exception Directory [.pdata]" msgstr "" -#: peigen.c:1045 pepigen.c:1045 +#: peigen.c:1010 pepigen.c:1010 msgid "Security Directory" msgstr "" -#: peigen.c:1046 pepigen.c:1046 +#: peigen.c:1011 pepigen.c:1011 msgid "Base Relocation Directory [.reloc]" msgstr "" -#: peigen.c:1047 pepigen.c:1047 +#: peigen.c:1012 pepigen.c:1012 msgid "Debug Directory" msgstr "" -#: peigen.c:1048 pepigen.c:1048 +#: peigen.c:1013 pepigen.c:1013 msgid "Description Directory" msgstr "" -#: peigen.c:1049 pepigen.c:1049 +#: peigen.c:1014 pepigen.c:1014 msgid "Special Directory" msgstr "" -#: peigen.c:1050 pepigen.c:1050 +#: peigen.c:1015 pepigen.c:1015 msgid "Thread Storage Directory [.tls]" msgstr "" -#: peigen.c:1051 pepigen.c:1051 +#: peigen.c:1016 pepigen.c:1016 msgid "Load Configuration Directory" msgstr "" -#: peigen.c:1052 pepigen.c:1052 +#: peigen.c:1017 pepigen.c:1017 msgid "Bound Import Directory" msgstr "" -#: peigen.c:1053 pepigen.c:1053 +#: peigen.c:1018 pepigen.c:1018 msgid "Import Address Table Directory" msgstr "" -#: peigen.c:1054 pepigen.c:1054 +#: peigen.c:1019 pepigen.c:1019 msgid "Delay Import Directory" msgstr "" -#: peigen.c:1055 peigen.c:1056 pepigen.c:1055 pepigen.c:1056 +#: peigen.c:1020 peigen.c:1021 pepigen.c:1020 pepigen.c:1021 msgid "Reserved" msgstr "" -#: peigen.c:1118 pepigen.c:1118 +#: peigen.c:1081 pepigen.c:1081 #, c-format msgid "" "\n" "There is an import table, but the section containing it could not be found\n" msgstr "" -#: peigen.c:1123 pepigen.c:1123 +#: peigen.c:1086 pepigen.c:1086 #, c-format msgid "" "\n" "There is an import table in %s at 0x%lx\n" msgstr "" -#: peigen.c:1159 pepigen.c:1159 +#: peigen.c:1129 pepigen.c:1129 #, c-format msgid "" "\n" "Function descriptor located at the start address: %04lx\n" msgstr "" -#: peigen.c:1162 pepigen.c:1162 +#: peigen.c:1132 pepigen.c:1132 #, c-format msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n" msgstr "" -#: peigen.c:1170 pepigen.c:1170 +#: peigen.c:1140 pepigen.c:1140 #, c-format msgid "" "\n" "No reldata section! Function descriptor not decoded.\n" msgstr "" -#: peigen.c:1175 pepigen.c:1175 +#: peigen.c:1145 pepigen.c:1145 #, c-format msgid "" "\n" "The Import Tables (interpreted %s section contents)\n" msgstr "" -#: peigen.c:1178 pepigen.c:1178 +#: peigen.c:1148 pepigen.c:1148 #, c-format msgid "" " vma: Hint Time Forward DLL First\n" " Table Stamp Chain Name Thunk\n" msgstr "" -#: peigen.c:1223 pepigen.c:1223 +#: peigen.c:1196 pepigen.c:1196 #, c-format msgid "" "\n" "\tDLL Name: %s\n" msgstr "" -#: peigen.c:1234 pepigen.c:1234 +#: peigen.c:1207 pepigen.c:1207 #, c-format msgid "\tvma: Hint/Ord Member-Name Bound-To\n" msgstr "" -#: peigen.c:1259 pepigen.c:1259 +#: peigen.c:1232 pepigen.c:1232 #, c-format msgid "" "\n" "There is a first thunk, but the section containing it could not be found\n" msgstr "" -#: peigen.c:1399 pepigen.c:1399 +#: peigen.c:1368 pepigen.c:1368 #, c-format msgid "" "\n" "There is an export table, but the section containing it could not be found\n" msgstr "" -#: peigen.c:1404 pepigen.c:1404 +#: peigen.c:1373 pepigen.c:1373 #, c-format msgid "" "\n" "There is an export table in %s at 0x%lx\n" msgstr "" -#: peigen.c:1435 pepigen.c:1435 +#: peigen.c:1404 pepigen.c:1404 #, c-format msgid "" "\n" @@ -3201,128 +3246,128 @@ msgid "" "\n" msgstr "" -#: peigen.c:1439 pepigen.c:1439 +#: peigen.c:1408 pepigen.c:1408 #, c-format msgid "Export Flags \t\t\t%lx\n" msgstr "" -#: peigen.c:1442 pepigen.c:1442 +#: peigen.c:1411 pepigen.c:1411 #, c-format msgid "Time/Date stamp \t\t%lx\n" msgstr "" -#: peigen.c:1445 pepigen.c:1445 +#: peigen.c:1414 pepigen.c:1414 #, c-format msgid "Major/Minor \t\t\t%d/%d\n" msgstr "" -#: peigen.c:1448 pepigen.c:1448 +#: peigen.c:1417 pepigen.c:1417 #, c-format msgid "Name \t\t\t\t" msgstr "" -#: peigen.c:1454 pepigen.c:1454 +#: peigen.c:1423 pepigen.c:1423 #, c-format msgid "Ordinal Base \t\t\t%ld\n" msgstr "" -#: peigen.c:1457 pepigen.c:1457 +#: peigen.c:1426 pepigen.c:1426 #, c-format msgid "Number in:\n" msgstr "" -#: peigen.c:1460 pepigen.c:1460 +#: peigen.c:1429 pepigen.c:1429 #, c-format msgid "\tExport Address Table \t\t%08lx\n" msgstr "" -#: peigen.c:1464 pepigen.c:1464 +#: peigen.c:1433 pepigen.c:1433 #, c-format msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n" msgstr "" -#: peigen.c:1467 pepigen.c:1467 +#: peigen.c:1436 pepigen.c:1436 #, c-format msgid "Table Addresses\n" msgstr "" -#: peigen.c:1470 pepigen.c:1470 +#: peigen.c:1439 pepigen.c:1439 #, c-format msgid "\tExport Address Table \t\t" msgstr "" -#: peigen.c:1475 pepigen.c:1475 +#: peigen.c:1444 pepigen.c:1444 #, c-format msgid "\tName Pointer Table \t\t" msgstr "" -#: peigen.c:1480 pepigen.c:1480 +#: peigen.c:1449 pepigen.c:1449 #, c-format msgid "\tOrdinal Table \t\t\t" msgstr "" -#: peigen.c:1495 pepigen.c:1495 +#: peigen.c:1463 pepigen.c:1463 #, c-format msgid "" "\n" "Export Address Table -- Ordinal Base %ld\n" msgstr "" -#: peigen.c:1514 pepigen.c:1514 +#: peigen.c:1482 pepigen.c:1482 msgid "Forwarder RVA" msgstr "" -#: peigen.c:1525 pepigen.c:1525 +#: peigen.c:1493 pepigen.c:1493 msgid "Export RVA" msgstr "" -#: peigen.c:1532 pepigen.c:1532 +#: peigen.c:1500 pepigen.c:1500 #, c-format msgid "" "\n" "[Ordinal/Name Pointer] Table\n" msgstr "" -#: peigen.c:1587 pepigen.c:1587 +#: peigen.c:1553 pepigen.c:1553 #, c-format msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n" msgstr "" -#: peigen.c:1591 pepigen.c:1591 +#: peigen.c:1557 pepigen.c:1557 #, c-format msgid "" "\n" "The Function Table (interpreted .pdata section contents)\n" msgstr "" -#: peigen.c:1594 pepigen.c:1594 +#: peigen.c:1560 pepigen.c:1560 #, c-format msgid " vma:\t\t\tBegin Address End Address Unwind Info\n" msgstr "" -#: peigen.c:1596 pepigen.c:1596 +#: peigen.c:1562 pepigen.c:1562 #, c-format msgid "" " vma:\t\tBegin End EH EH PrologEnd Exception\n" " \t\tAddress Address Handler Data Address Mask\n" msgstr "" -#: peigen.c:1666 pepigen.c:1666 +#: peigen.c:1632 pepigen.c:1632 #, c-format msgid " Register save millicode" msgstr "" -#: peigen.c:1669 pepigen.c:1669 +#: peigen.c:1635 pepigen.c:1635 #, c-format msgid " Register restore millicode" msgstr "" -#: peigen.c:1672 pepigen.c:1672 +#: peigen.c:1638 pepigen.c:1638 #, c-format msgid " Glue code sequence" msgstr "" -#: peigen.c:1724 pepigen.c:1724 +#: peigen.c:1688 pepigen.c:1688 #, c-format msgid "" "\n" @@ -3330,14 +3375,14 @@ msgid "" "PE File Base Relocations (interpreted .reloc section contents)\n" msgstr "" -#: peigen.c:1754 pepigen.c:1754 +#: peigen.c:1718 pepigen.c:1718 #, c-format msgid "" "\n" "Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n" msgstr "" -#: peigen.c:1767 pepigen.c:1767 +#: peigen.c:1731 pepigen.c:1731 #, c-format msgid "\treloc %4d offset %4x [%4lx] %s" msgstr "" @@ -3345,7 +3390,7 @@ msgstr "" #. The MS dumpbin program reportedly ands with 0xff0f before #. printing the characteristics field. Not sure why. No reason to #. emulate it here. -#: peigen.c:1807 pepigen.c:1807 +#: peigen.c:1769 pepigen.c:1769 #, c-format msgid "" "\n" diff -uprN binutils-2.16.91.0.1/bfd/po/SRC-POTFILES.in binutils-2.16.91.0.2/bfd/po/SRC-POTFILES.in --- binutils-2.16.91.0.1/bfd/po/SRC-POTFILES.in 2004-11-22 12:33:31.000000000 -0800 +++ binutils-2.16.91.0.2/bfd/po/SRC-POTFILES.in 2005-07-20 12:27:27.475163036 -0700 @@ -86,6 +86,7 @@ cpu-ip2k.c cpu-iq2000.c cpu-m10200.c cpu-m10300.c +cpu-m32c.c cpu-m32r.c cpu-m68hc11.c cpu-m68hc12.c @@ -95,6 +96,7 @@ cpu-maxq.c cpu-mcore.c cpu-mips.c cpu-mmix.c +cpu-ms1.c cpu-msp430.c cpu-ns32k.c cpu-openrisc.c @@ -148,6 +150,7 @@ elf32-i860.c elf32-i960.c elf32-ip2k.c elf32-iq2000.c +elf32-m32c.c elf32-m32r.c elf32-m68hc11.c elf32-m68hc12.c @@ -156,6 +159,7 @@ elf32-m68k.c elf32-m88k.c elf32-mcore.c elf32-mips.c +elf32-ms1.c elf32-msp430.c elf32-openrisc.c elf32-or32.c @@ -194,7 +198,9 @@ elf-m10200.c elf-m10300.c elfn32-mips.c elf-strtab.c +elf-vxworks.c elfxx-mips.c +elfxx-sparc.c epoc-pe-arm.c epoc-pei-arm.c format.c diff -uprN binutils-2.16.91.0.1/bfd/po/vi.po binutils-2.16.91.0.2/bfd/po/vi.po --- binutils-2.16.91.0.1/bfd/po/vi.po 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/bfd/po/vi.po 2005-07-20 12:27:27.492160234 -0700 @@ -0,0 +1,3272 @@ +# translation of bfd-2.15.96.po to Vietnamese +# Copyright (C) 2005 Free Software Foundation, Inc. +# Phan Vinh Thinh , 2005. +# +msgid "" +msgstr "" +"Project-Id-Version: bfd 2.15.96\n" +"Report-Msgid-Bugs-To: \n" +"POT-Creation-Date: 2005-03-05 22:14+1030\n" +"PO-Revision-Date: 2005-06-22 20:01+0400\n" +"Last-Translator: Phan Vinh Thinh \n" +"Language-Team: Vietnamese \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=UTF-8\n" +"Content-Transfer-Encoding: 8bit\n" +"X-Generator: KBabel 1.9.1\n" + +#: aout-adobe.c:204 +msgid "%B: Unknown section type in a.out.adobe file: %x\n" +msgstr "%B: Không rõ dạng phân đoạn trong tập tin a.out.adobe: %x\n" + +#: aout-cris.c:207 +#, c-format +msgid "%s: Invalid relocation type exported: %d" +msgstr "%s: Đã xuất dạng phân chia lại sai: %d" + +#: aout-cris.c:251 +msgid "%B: Invalid relocation type imported: %d" +msgstr "%B: Đã nhập dạng phân chia lại sai: %d" + +#: aout-cris.c:262 +msgid "%B: Bad relocation record imported: %d" +msgstr "%B: Đã nhập bản ghi phân chia lại xấu: %d" + +#: aoutx.h:1287 aoutx.h:1626 +#, c-format +msgid "%s: can not represent section `%s' in a.out object file format" +msgstr "%s: không mô tả được phân đoạn `%s' trong định dạng tập tin a.out" + +#: aoutx.h:1592 +#, c-format +msgid "%s: can not represent section for symbol `%s' in a.out object file format" +msgstr "%s: không mô tả được phân đoạn cho ký tự `%s' trong định dạng tập tin a.out" + +#: aoutx.h:1594 +msgid "*unknown*" +msgstr "*không rõ*" + +#: aoutx.h:3682 +#, c-format +msgid "%s: relocatable link from %s to %s not supported" +msgstr "%s: không hỗ trợ việc liên kết có thể đặt vị trí lại từ %s tới %s" + +#: archive.c:1729 +msgid "Warning: writing archive was slow: rewriting timestamp\n" +msgstr "Cảnh báo: ghi kho quá chậm: đang ghi lại tem đánh dấu thời gian\n" + +#: archive.c:1992 +msgid "Reading archive file mod timestamp" +msgstr "Đang đọc tem đánh dấu thời gian sử đổi của tập tin kho chứa" + +#: archive.c:2018 +msgid "Writing updated armap timestamp" +msgstr "Đang ghi tem đánh dấu thời gian của armap đã đánh dấu" + +#: bfd.c:279 +msgid "No error" +msgstr "Không lỗi" + +#: bfd.c:280 +msgid "System call error" +msgstr "Lỗi gọi hệ thống" + +#: bfd.c:281 +msgid "Invalid bfd target" +msgstr "Sai đích của bfd" + +#: bfd.c:282 +msgid "File in wrong format" +msgstr "Tập tin ở trong định dạng sai" + +#: bfd.c:283 +msgid "Archive object file in wrong format" +msgstr "Tập tin kho vật thể ở trong định dạng sai" + +#: bfd.c:284 +msgid "Invalid operation" +msgstr "Sai thao tác" + +#: bfd.c:285 +msgid "Memory exhausted" +msgstr "Cạn bộ nhớ" + +#: bfd.c:286 +msgid "No symbols" +msgstr "Không ký tự" + +#: bfd.c:287 +msgid "Archive has no index; run ranlib to add one" +msgstr "Tập tin kho không có chỉ mục; hãy chạy ranlib để thêm" + +#: bfd.c:288 +msgid "No more archived files" +msgstr "Không còn tập tin kho nào" + +#: bfd.c:289 +msgid "Malformed archive" +msgstr "Kho bị lỗi" + +#: bfd.c:290 +msgid "File format not recognized" +msgstr "Không nhận ra định dạng tập tin" + +#: bfd.c:291 +msgid "File format is ambiguous" +msgstr "Dạng tập tin không rõ ràng" + +#: bfd.c:292 +msgid "Section has no contents" +msgstr "Phần không có nội dung" + +#: bfd.c:293 +msgid "Nonrepresentable section on output" +msgstr "Không có phần nào trên đầu ra" + +#: bfd.c:294 +msgid "Symbol needs debug section which does not exist" +msgstr "Ký tự cần phần tìm sửa lỗi, và nó không tồn tại" + +#: bfd.c:295 +msgid "Bad value" +msgstr "Giá trị xấu" + +#: bfd.c:296 +msgid "File truncated" +msgstr "Đã cắt ngắn tập tin" + +#: bfd.c:297 +msgid "File too big" +msgstr "Tập tin quá lớn" + +#: bfd.c:298 +msgid "#" +msgstr "#" + +#: bfd.c:768 +#, c-format +msgid "BFD %s assertion fail %s:%d" +msgstr "BFD %s sự xác nhận không thành công %s:%d" + +#: bfd.c:784 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d in %s\n" +msgstr "BFD %s lỗi nội bộ, thoát tại %s dòng %d trong %s\n" + +#: bfd.c:788 +#, c-format +msgid "BFD %s internal error, aborting at %s line %d\n" +msgstr "BFD %s lỗi nội bộ, thoát tại %s dòng %d\n" + +#: bfd.c:790 +msgid "Please report this bug.\n" +msgstr "Xin hãy báo cáo lỗi này.\n" + +#: bfdwin.c:202 +#, c-format +msgid "not mapping: data=%lx mapped=%d\n" +msgstr "chưa ánh xạ: dữ liệu=%lx đã ánh xạ=%d\n" + +#: bfdwin.c:205 +#, c-format +msgid "not mapping: env var not set\n" +msgstr "chưa ánh xạ: không đặt biến môi trường\n" + +#: binary.c:309 +#, c-format +msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx." +msgstr "Cảnh báo: Ghi phần `%s' tới bộ tập tin to lớn (có nghĩa là âm) 0x%lx." + +#: coff64-rs6000.c:2107 coff-rs6000.c:3608 +msgid "%B: symbol `%s' has unrecognized smclas %d" +msgstr "%B: ký tự `%s' có smclas không nhận ra %d" + +#: coff-a29k.c:120 +msgid "Missing IHCONST" +msgstr "Thiếu IHCONST" + +#: coff-a29k.c:181 +msgid "Missing IHIHALF" +msgstr "Thiếu IHIHALF" + +#: coff-a29k.c:213 coff-or32.c:227 +msgid "Unrecognized reloc" +msgstr "reloc không nhận ra" + +#: coff-a29k.c:409 +msgid "missing IHCONST reloc" +msgstr "thiếu IHCONST reloc" + +#: coff-a29k.c:499 +msgid "missing IHIHALF reloc" +msgstr "thiếu IHIHALF reloc" + +#: coff-alpha.c:881 coff-alpha.c:918 coff-alpha.c:1972 coff-mips.c:985 +msgid "GP relative relocation used when GP not defined" +msgstr "Sử dụng định vị lại tương đối GP khi chưa xác định GP" + +#: coff-alpha.c:1467 +msgid "using multiple gp values" +msgstr "sử dụng nhiều giá trị gp" + +#: coff-arm.c:1066 elf32-arm.c:1425 +#, c-format +msgid "%B: unable to find THUMB glue '%s' for `%s'" +msgstr "%B: không tìm thấy dán THUMB '%s' cho `%s'" + +#: coff-arm.c:1096 elf32-arm.c:1459 +#, c-format +msgid "%B: unable to find ARM glue '%s' for `%s'" +msgstr "%B: không tìm thấy dán ARM '%s' cho `%s'" + +#: coff-arm.c:1394 elf32-arm.c:2165 +#, c-format +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: arm call to thumb" +msgstr "" +"%B(%s): cảnh báo: chưa bật dùng ảnh hưởng lẫn nhau.\n" +" lần xuất hiện đầu tiên: %B: gọi arm tới thumb" + +#: coff-arm.c:1484 +#, c-format +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: thumb call to arm\n" +" consider relinking with --support-old-code enabled" +msgstr "" +"%B(%s): cảnh báo: chưa bật dùng ảnh hưởng lẫn nhau.\n" +" lần xuất hiện đầu tiên: %B: gọi thumb tới arm\n" +" coi như liên kết lại với --support-old-code bật" + +#: coff-arm.c:1776 cofflink.c:3013 coff-tic80.c:687 +msgid "%B: bad reloc address 0x%lx in section `%A'" +msgstr "%B: địa chỉ reloc xấu 0x%lx trong phần `%A'" + +#: coff-arm.c:2110 +msgid "%B: illegal symbol index in reloc: %d" +msgstr "%B: chỉ mục ký tự không cho phép trong reloc: %d" + +#: coff-arm.c:2243 +#, c-format +msgid "ERROR: %B is compiled for APCS-%d, whereas %B is compiled for APCS-%d" +msgstr "LỖI: %B được biên dịch cho APCS-%d, trong khi %B được biên dịch cho APCS-%d" + +#: coff-arm.c:2259 elf32-arm.c:3583 +#, c-format +msgid "ERROR: %B passes floats in float registers, whereas %B passes them in integer registers" +msgstr "LỖI: %B đi qua trôi trong bản ghi trôi, trong khi %B đi qua chúng trong bản ghi số nguyên" + +#: coff-arm.c:2262 elf32-arm.c:3587 +#, c-format +msgid "ERROR: %B passes floats in integer registers, whereas %B passes them in float registers" +msgstr "LỖI: %B đi qua trôi trong bản ghi số nguyên, trong khi %B đi qua chúng trong bản ghi trôi" + +#: coff-arm.c:2276 +#, c-format +msgid "ERROR: %B is compiled as position independent code, whereas target %B is absolute position" +msgstr "LỖI: %B được biên dịch như mã không phụ thuộc vị trí, trong khi %B là vị trí tuyệt đối" + +#: coff-arm.c:2279 +#, c-format +msgid "ERROR: %B is compiled as absolute position code, whereas target %B is position independent" +msgstr "LỖI: %B được biên dịch như mã vị trí tuyệt đối, trong khi %B phụ thuộc vị trí" + +#: coff-arm.c:2307 elf32-arm.c:3652 +#, c-format +msgid "Warning: %B supports interworking, whereas %B does not" +msgstr "Cảnh báo: %B hỗ trợ ảnh hưởng lẫn nhau, trong khi %B thì không" + +#: coff-arm.c:2310 elf32-arm.c:3658 +#, c-format +msgid "Warning: %B does not support interworking, whereas %B does" +msgstr "Cảnh báo: %B không hỗ trợ ảnh hưởng lẫn nhau, trong khi %B có" + +#: coff-arm.c:2336 +#, c-format +msgid "private flags = %x:" +msgstr "cờ cá nhân = %x:" + +#: coff-arm.c:2344 elf32-arm.c:3709 +#, c-format +msgid " [floats passed in float registers]" +msgstr " [trôi đi qua trong bản ghi trôi]" + +#: coff-arm.c:2346 +#, c-format +msgid " [floats passed in integer registers]" +msgstr " [trôi đi qua trong bản ghi số nguyên]" + +#: coff-arm.c:2349 elf32-arm.c:3712 +#, c-format +msgid " [position independent]" +msgstr " [không phụ thuộc vị trí]" + +#: coff-arm.c:2351 +#, c-format +msgid " [absolute position]" +msgstr " [vị trí tuyệt đối]" + +#: coff-arm.c:2355 +#, c-format +msgid " [interworking flag not initialised]" +msgstr " [chưa đặt cờ ảnh hưởng lẫn nhau]" + +#: coff-arm.c:2357 +#, c-format +msgid " [interworking supported]" +msgstr " [hỗ trợ ảnh hưởng lẫn nhau]" + +#: coff-arm.c:2359 +#, c-format +msgid " [interworking not supported]" +msgstr " [không hỗ trợ ảnh hưởng lẫn nhau]" + +#: coff-arm.c:2407 elf32-arm.c:3390 +#, c-format +msgid "Warning: Not setting interworking flag of %B since it has already been specified as non-interworking" +msgstr "Cảnh báo: Chưa thiết lập cờ ảnh hưởng lẫn nhau của %B vì nó đã được xác định là không ảnh hưởng lẫn nhau" + +#: coff-arm.c:2411 elf32-arm.c:3394 +#, c-format +msgid "Warning: Clearing the interworking flag of %B due to outside request" +msgstr "Cảnh báo: Đang xoá cờ ảnh hưởng lẫn nhau của %B theo yêu cầu bên ngoài" + +#: coffcode.h:859 +msgid "%B: warning: COMDAT symbol '%s' does not match section name '%s'" +msgstr "%B: cảnh báo: ký tự COMDAT '%s' không tương ứng tên phần '%s'" + +#. Generate a warning message rather using the 'unhandled' +#. variable as this will allow some .sys files generate by +#. other toolchains to be processed. See bugzilla issue 196. +#: coffcode.h:1072 +msgid "%B: Warning: Ignoring section flag IMAGE_SCN_MEM_NOT_PAGED in section %s" +msgstr "%B: Cảnh báo: Đang lờ đi cờ của phần IMAGE_SCN_MEM_NOT_PAGED trong phần %s" + +#: coffcode.h:1127 +msgid "%B (%s): Section flag %s (0x%x) ignored" +msgstr "%B (%s): Đã lờ đi cờ của phần %s (0x%x)" + +#: coffcode.h:2255 +#, c-format +msgid "Unrecognized TI COFF target id '0x%x'" +msgstr "Không nhận ra id đích của TI COFF '0x%x'" + +#: coffcode.h:4375 +msgid "%B: warning: line number table read failed" +msgstr "%B: cảnh báo: đọc bảng số thứ tự dòng không thành công" + +#: coffcode.h:4407 +msgid "%B: warning: illegal symbol index %ld in line numbers" +msgstr "%B: cảnh báo: chỉ mục ký tự không cho phép %ld trong các số thứ tự dòng" + +#: coffcode.h:4421 +msgid "%B: warning: duplicate line number information for `%s'" +msgstr "%B: cảnh báo: thông tin về số dòng lặp lại cho `%s'" + +#: coffcode.h:4771 +msgid "%B: Unrecognized storage class %d for %s symbol `%s'" +msgstr "%B: Không nhận ra lớp của kho %d cho %s ký tự `%s'" + +#: coffcode.h:4904 +msgid "warning: %B: local symbol `%s' has no section" +msgstr "cảnh báo: %B: ký tự nội bộ `%s' không có phần đoạn" + +#: coffcode.h:5010 coff-i860.c:586 coff-tic54x.c:376 +msgid "%B: warning: illegal symbol index %ld in relocs" +msgstr "%B: cảnh báo: chỉ mục ký tự không cho phép %ld trong các reloc" + +#: coffcode.h:5048 +msgid "%B: illegal relocation type %d at address 0x%lx" +msgstr "%B: dạng reloc không cho phép %d tại địa chỉ 0x%lx" + +#: coffgen.c:1594 +msgid "%B: bad string table size %lu" +msgstr "%B: kích thước bảng chuỗi xấu %lu" + +#: coff-h8300.c:1126 +#, c-format +msgid "cannot handle R_MEM_INDIRECT reloc when using %s output" +msgstr "không điều khiển được reloc R_MEM_INDIRECT khi sử dụng đầu ra %s" + +#: coff-i860.c:142 +#, c-format +msgid "Relocation `%s' not yet implemented\n" +msgstr "Chưa phát triển reloc `%s'\n" + +#: coff-i960.c:137 coff-i960.c:486 +msgid "uncertain calling convention for non-COFF symbol" +msgstr "quy ước gọi không chắc chắn cho ký tự không phải COFF" + +#: cofflink.c:507 elflink.c:3955 +msgid "Warning: type of symbol `%s' changed from %d to %d in %B" +msgstr "Cảnh báo: dạng của ký tự `%s' thay đổi từ %d thành %d trong %B" + +#: cofflink.c:2293 +msgid "%B: relocs in section `%A', but it has no contents" +msgstr "%B: reloc trong phần `%A', nhưng không có nội dung" + +#: cofflink.c:2624 coffswap.h:890 +#, c-format +msgid "%s: %s: reloc overflow: 0x%lx > 0xffff" +msgstr "%s: %s: reloc vượt quá giới hạn: 0x%lx > 0xffff" + +#: cofflink.c:2633 coffswap.h:876 +#, c-format +msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff" +msgstr "%s: cảnh báo: %s: số dòng vượt quá giới hạn: 0x%lx > 0xffff" + +#: coff-m68k.c:482 elf32-m68k.c:2128 +msgid "unsupported reloc type" +msgstr "dạng reloc chưa hỗ trợ" + +#: coff-maxq.c:128 +msgid "Can't Make it a Short Jump" +msgstr "Không thể Làm nó một Bước nhảy Ngắn" + +#: coff-maxq.c:193 +msgid "Exceeds Long Jump Range" +msgstr "Vượt quá Phạm vi Bước nhảy Dài" + +#: coff-maxq.c:204 coff-maxq.c:278 +msgid "Absolute address Exceeds 16 bit Range" +msgstr "Địa chỉ tuyệt đối Vượt quá Phạm vi 16 bit" + +#: coff-maxq.c:242 +msgid "Absolute address Exceeds 8 bit Range" +msgstr "Địa chỉ tuyệt đối Vượt quá Phạm vi 8 bit" + +#: coff-maxq.c:335 +msgid "Unrecognized Reloc Type" +msgstr "Dạng Reloc Không nhận ra" + +#: coff-mips.c:686 elf32-mips.c:940 elf64-mips.c:1864 elfn32-mips.c:1718 +msgid "GP relative relocation when _gp not defined" +msgstr "Reloc GP tương ứng khi chưa xác định _gp" + +#: coff-rs6000.c:2783 +#, c-format +msgid "%s: unsupported relocation type 0x%02x" +msgstr "%s: dạng reloc chưa hỗ trợ 0x%02x" + +#: coff-rs6000.c:2876 +#, c-format +msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry" +msgstr "%s: TOC reloc tại 0x%x tới ký tự `%s' không có mục TOC" + +#: coff-tic4x.c:174 coff-tic54x.c:282 coff-tic80.c:450 +#, c-format +msgid "Unrecognized reloc type 0x%x" +msgstr "Dạng reloc không nhận ra 0x%x" + +#: coff-tic4x.c:219 +#, c-format +msgid "%s: warning: illegal symbol index %ld in relocs" +msgstr "%s: cảnh báo: chỉ mục ký tự không cho phép %ld trong các reloc" + +#: coff-w65.c:366 +#, c-format +msgid "ignoring reloc %s\n" +msgstr "lờ đi reloc %s\n" + +#: cpu-arm.c:184 cpu-arm.c:193 +msgid "ERROR: %B is compiled for the EP9312, whereas %B is compiled for XScale" +msgstr "LỖI: %B được biên dịch cho EP9312, trong khi %B được biên dịch cho XScale" + +#: cpu-arm.c:324 +#, c-format +msgid "warning: unable to update contents of %s section in %s" +msgstr "cảnh báo: không cập nhật được nội dung của phần %s trong %s" + +#: dwarf2.c:296 +msgid "Dwarf Error: Can't find .debug_str section." +msgstr "Lỗi Dwarf: Không tìm thấy phần .debug_str." + +#: dwarf2.c:314 +#, c-format +msgid "Dwarf Error: DW_FORM_strp offset (%lu) greater than or equal to .debug_str size (%lu)." +msgstr "Lỗi Dwarf: DW_FORM_strp (%lu) lớn hơn hoặc bằng kích thước .debug_str (%lu)." + +#: dwarf2.c:388 +msgid "Dwarf Error: Can't find .debug_abbrev section." +msgstr "Lỗi Dwarf: Không tìm thấy phần .debug_abbrev." + +#: dwarf2.c:403 +#, c-format +msgid "Dwarf Error: Abbrev offset (%lu) greater than or equal to .debug_abbrev size (%lu)." +msgstr "Lỗi Dwarf: Abbrev (%lu) lớn hơn hoặc bằng kích thước .debug_abbrev (%lu)." + +#: dwarf2.c:601 +#, c-format +msgid "Dwarf Error: Invalid or unhandled FORM value: %u." +msgstr "Lỗi Dwarf: Giá trị FORM sai hoặc không thể điều khiển: %u." + +#: dwarf2.c:773 +msgid "Dwarf Error: mangled line number section (bad file number)." +msgstr "Lỗi Dwarf: phần số dòng bị hỏng (số của tập tin xấu)." + +#: dwarf2.c:866 +msgid "Dwarf Error: Can't find .debug_line section." +msgstr "Lỗi Dwarf: Không tìm thấy phần .debug_line." + +#: dwarf2.c:883 +#, c-format +msgid "Dwarf Error: Line offset (%lu) greater than or equal to .debug_line size (%lu)." +msgstr "Lỗi Dwarf: Dòng (%lu) lớn hơn hoặc bằng kích thước .debug_line (%lu)." + +#: dwarf2.c:1088 +msgid "Dwarf Error: mangled line number section." +msgstr "Lỗi Dwarf: phần số dòng xấu." + +#: dwarf2.c:1285 dwarf2.c:1343 dwarf2.c:1498 +#, c-format +msgid "Dwarf Error: Could not find abbrev number %u." +msgstr "Lỗi Dwarf: Không tìm thấy số của abbrev %u." + +#: dwarf2.c:1459 +#, c-format +msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2 information." +msgstr "Lỗi Dwarf: tìm thấy dwarf phiên bản '%u', trình đọc này chỉ điều khiển thông tin phiên bản 2." + +#: dwarf2.c:1466 +#, c-format +msgid "Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'." +msgstr "Lỗi Dwarf: tìm thấy kích thước địa chỉ '%u', trình đọc này không điều khiển được kích thước lớn hơn '%u'." + +#: dwarf2.c:1489 +#, c-format +msgid "Dwarf Error: Bad abbrev number: %u." +msgstr "Lỗi Dwarf: Số abbrev xấu: %u." + +#: ecoff.c:1269 +#, c-format +msgid "Unknown basic type %d" +msgstr "Không rõ dạng cơ bản %d" + +#: ecoff.c:1529 +#, c-format +msgid "" +"\n" +" End+1 symbol: %ld" +msgstr "" +"\n" +" Ký hiệu End+1: %ld" + +#: ecoff.c:1536 ecoff.c:1539 +#, c-format +msgid "" +"\n" +" First symbol: %ld" +msgstr "" +"\n" +" Ký hiệu đầu tiên: %ld" + +#: ecoff.c:1551 +#, c-format +msgid "" +"\n" +" End+1 symbol: %-7ld Type: %s" +msgstr "" +"\n" +" Ký hiệu End+1: %-7ld Dạng: %s" + +#: ecoff.c:1558 +#, c-format +msgid "" +"\n" +" Local symbol: %ld" +msgstr "" +"\n" +" Ký hiệu nội bộ: %ld" + +#: ecoff.c:1566 +#, c-format +msgid "" +"\n" +" struct; End+1 symbol: %ld" +msgstr "" +"\n" +" cấu trúc; ký hiệu End+1: %ld" + +#: ecoff.c:1571 +#, c-format +msgid "" +"\n" +" union; End+1 symbol: %ld" +msgstr "" +"\n" +" kết hợp; ký hiệu End+1: %ld" + +#: ecoff.c:1576 +#, c-format +msgid "" +"\n" +" enum; End+1 symbol: %ld" +msgstr "" +"\n" +" đếm; ký hiệu End+1: %ld" + +#: ecoff.c:1582 +#, c-format +msgid "" +"\n" +" Type: %s" +msgstr "" +"\n" +" Dạng: %s" + +#: elf32-arm.c:1794 +msgid "%B: BE8 images only valid in big-endian mode." +msgstr "%B: hình ảnh BE8 chỉ đúng trong chế độ big-endian." + +#: elf32-arm.c:1953 +#, c-format +msgid "Invalid TARGET2 relocation type '%s'." +msgstr "Sai dạng reloc của TARGET2 '%s'." + +#: elf32-arm.c:2060 +msgid "" +"%B(%s): warning: interworking not enabled.\n" +" first occurrence: %B: thumb call to arm" +msgstr "" +"%B(%s): cảnh báo: chưa bật dùng ảnh hưởng lẫn nhau.\n" +" lần xuất hiện đầu: %B: gọi ngón tay cái tới bàn tay" + +#: elf32-arm.c:2476 +msgid "\\%B: Warning: Arm BLX instruction targets Arm function '%s'." +msgstr "\\%B: Cảnh báo: Sự chỉ thị Cánh tay BLX tới chức năng Cánh tay '%s'." + +#: elf32-arm.c:2665 +msgid "%B: Warning: Thumb BLX instruction targets thumb function '%s'." +msgstr "%B: Cảnh báo: Sự chỉ thị Ngón tay cái BLX tới chức năng Ngón tay cái '%s'." + +#: elf32-arm.c:3185 elf32-sh.c:4610 elf64-sh64.c:1537 +msgid "%B(%A+0x%lx): %s relocation against SEC_MERGE section" +msgstr "%B(%A+0x%lx): %s reloc đối lại phần SEC_MERGE" + +#: elf32-arm.c:3277 +msgid "%B(%A): warning: unresolvable relocation %d against symbol `%s'" +msgstr "%B(%A): cảnh báo: không thể tìm thấy reloc %d đối lại ký hiệu `%s'" + +#: elf32-arm.c:3329 elf32-avr.c:875 elf32-cr16c.c:773 elf32-cris.c:1502 +#: elf32-crx.c:911 elf32-d10v.c:564 elf32-fr30.c:595 elf32-frv.c:4107 +#: elf32-h8300.c:494 elf32-i860.c:1189 elf32-ip2k.c:1550 elf32-iq2000.c:611 +#: elf32-m32r.c:3250 elf32-m68hc1x.c:1189 elf32-msp430.c:503 +#: elf32-openrisc.c:415 elf32-v850.c:1749 elf32-xstormy16.c:954 +#: elf64-mmix.c:1517 elf-m10200.c:427 elf-m10300.c:1527 +msgid "internal error: out of range error" +msgstr "lỗi nội bộ: lỗi vượt giới hạn" + +#: elf32-arm.c:3333 elf32-avr.c:879 elf32-cr16c.c:777 elf32-cris.c:1506 +#: elf32-crx.c:915 elf32-d10v.c:568 elf32-fr30.c:599 elf32-frv.c:4111 +#: elf32-h8300.c:498 elf32-i860.c:1193 elf32-iq2000.c:615 elf32-m32r.c:3254 +#: elf32-m68hc1x.c:1193 elf32-msp430.c:507 elf32-openrisc.c:419 +#: elf32-v850.c:1753 elf32-xstormy16.c:958 elf64-mmix.c:1521 elf-m10200.c:431 +#: elf-m10300.c:1531 elfxx-mips.c:7179 +msgid "internal error: unsupported relocation error" +msgstr "lỗi nội bộ: lỗi reloc chưa hỗ trợ" + +#: elf32-arm.c:3337 elf32-cr16c.c:781 elf32-crx.c:919 elf32-d10v.c:572 +#: elf32-h8300.c:502 elf32-m32r.c:3258 elf32-m68hc1x.c:1197 elf-m10200.c:435 +#: elf-m10300.c:1535 +msgid "internal error: dangerous error" +msgstr "lỗi nội bộ: lỗi nguy hiểm" + +#: elf32-arm.c:3341 elf32-avr.c:887 elf32-cr16c.c:785 elf32-cris.c:1514 +#: elf32-crx.c:923 elf32-d10v.c:576 elf32-fr30.c:607 elf32-frv.c:4119 +#: elf32-h8300.c:506 elf32-i860.c:1201 elf32-ip2k.c:1565 elf32-iq2000.c:623 +#: elf32-m32r.c:3262 elf32-m68hc1x.c:1201 elf32-msp430.c:515 +#: elf32-openrisc.c:427 elf32-v850.c:1773 elf32-xstormy16.c:966 +#: elf64-mmix.c:1529 elf-m10200.c:439 elf-m10300.c:1539 +msgid "internal error: unknown error" +msgstr "lỗi nội bộ: lỗi không rõ" + +#: elf32-arm.c:3440 +msgid "Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it" +msgstr "Cảnh báo: Đang xóa cờ ảnh hưởng lẫn nhau của %B vì mã không ảnh hưởng lẫn nhau trong %B đã liên kết với nó" + +#: elf32-arm.c:3559 +msgid "ERROR: Source object %B has EABI version %d, but target %B has EABI version %d" +msgstr "LỖI: Đối tượng nguồn %B có phiên bản EABI %d, nhưng đích %B có phiên bản EABI %d" + +#: elf32-arm.c:3572 +msgid "ERROR: %B is compiled for APCS-%d, whereas target %B uses APCS-%d" +msgstr "LỖI: %B được biên dịch cho APCS-%d, trong khi đích %B sử dụng APCS-%d" + +#: elf32-arm.c:3597 +msgid "ERROR: %B uses VFP instructions, whereas %B does not" +msgstr "LỖI: %B sử dụng các chỉ dẫn VFP, trong khi %B thì không" + +#: elf32-arm.c:3601 +msgid "ERROR: %B uses FPA instructions, whereas %B does not" +msgstr "LỖI: %B sử dụng các chỉ dẫn FPA, trong khi %B thì không" + +#: elf32-arm.c:3611 +msgid "ERROR: %B uses Maverick instructions, whereas %B does not" +msgstr "LỖI: %B sử dụng các chỉ dẫn Maverick, trong khi %B thì không" + +#: elf32-arm.c:3615 +msgid "ERROR: %B does not use Maverick instructions, whereas %B does" +msgstr "LỖI: %B không sử dụng các chỉ dẫn Maverick, trong khi %B thì có" + +#: elf32-arm.c:3634 +msgid "ERROR: %B uses software FP, whereas %B uses hardware FP" +msgstr "LỖI: %B sử dụng phần mềm FP, trong khi %B sử dụng phần cứng FP" + +#: elf32-arm.c:3638 +msgid "ERROR: %B uses hardware FP, whereas %B uses software FP" +msgstr "LỖI: %B sử dụng phần cứng FP, trong khi %B sử dụng phần mềm FP" + +#. Ignore init flag - it may not be set, despite the flags field +#. containing valid data. +#. Ignore init flag - it may not be set, despite the flags field containing valid data. +#: elf32-arm.c:3685 elf32-cris.c:3243 elf32-m68hc1x.c:1333 elf32-m68k.c:397 +#: elf32-vax.c:546 elfxx-mips.c:9846 +#, c-format +msgid "private flags = %lx:" +msgstr "các cờ cá nhân = %lx:" + +#: elf32-arm.c:3694 +#, c-format +msgid " [interworking enabled]" +msgstr " [bật dùng ảnh hưởng lẫn nhau]" + +#: elf32-arm.c:3702 +#, c-format +msgid " [VFP float format]" +msgstr " [định dạng trôi VFP]" + +#: elf32-arm.c:3704 +#, c-format +msgid " [Maverick float format]" +msgstr " [định dạng trôi Maverick]" + +#: elf32-arm.c:3706 +#, c-format +msgid " [FPA float format]" +msgstr " [định dạng trôi FPA]" + +#: elf32-arm.c:3715 +#, c-format +msgid " [new ABI]" +msgstr " [ABI mới]" + +#: elf32-arm.c:3718 +#, c-format +msgid " [old ABI]" +msgstr " [ABI cũ]" + +#: elf32-arm.c:3721 +#, c-format +msgid " [software FP]" +msgstr " [phần mềm FP]" + +#: elf32-arm.c:3730 +#, c-format +msgid " [Version1 EABI]" +msgstr " [EABI Phiên bản 1]" + +#: elf32-arm.c:3733 elf32-arm.c:3744 +#, c-format +msgid " [sorted symbol table]" +msgstr " [bảng ký hiệu đã sắp xếp]" + +#: elf32-arm.c:3735 elf32-arm.c:3746 +#, c-format +msgid " [unsorted symbol table]" +msgstr " [bảng ký hiệu chưa sắp xếp]" + +#: elf32-arm.c:3741 +#, c-format +msgid " [Version2 EABI]" +msgstr " [EABI Phiên bản 2]" + +#: elf32-arm.c:3749 +#, c-format +msgid " [dynamic symbols use segment index]" +msgstr " [các ký hiệu động sử dụng chỉ mục phần]" + +#: elf32-arm.c:3752 +#, c-format +msgid " [mapping symbols precede others]" +msgstr " [ký hiệu ánh xạ đứng trước]" + +#: elf32-arm.c:3759 +#, c-format +msgid " [Version3 EABI]" +msgstr " [EABI Phiên bản 3]" + +#: elf32-arm.c:3763 +#, c-format +msgid " [Version4 EABI]" +msgstr " [EABI Phiên bản 4]" + +#: elf32-arm.c:3766 +#, c-format +msgid " [BE8]" +msgstr " [BE8]" + +#: elf32-arm.c:3769 +#, c-format +msgid " [LE8]" +msgstr " [LE8]" + +#: elf32-arm.c:3775 +#, c-format +msgid " " +msgstr " " + +#: elf32-arm.c:3782 +#, c-format +msgid " [relocatable executable]" +msgstr " [có thể thực hiện có thể định vị lại]" + +#: elf32-arm.c:3785 +#, c-format +msgid " [has entry point]" +msgstr " [có điểm mục]" + +#: elf32-arm.c:3790 +#, c-format +msgid "" +msgstr "" + +#: elf32-avr.c:883 elf32-cris.c:1510 elf32-fr30.c:603 elf32-frv.c:4115 +#: elf32-i860.c:1197 elf32-ip2k.c:1561 elf32-iq2000.c:619 elf32-msp430.c:511 +#: elf32-openrisc.c:423 elf32-v850.c:1757 elf32-xstormy16.c:962 +#: elf64-mmix.c:1525 +msgid "internal error: dangerous relocation" +msgstr "lỗi nội bộ: định vị lại nguy hiểm" + +#: elf32-cris.c:1050 +msgid "%B, section %A: unresolvable relocation %s against symbol `%s'" +msgstr "%B, phần %A: định vị lại không tìm thấy %s đối với ký hiệu `%s'" + +#: elf32-cris.c:1105 +msgid "%B, section %A: No PLT nor GOT for relocation %s against symbol `%s'" +msgstr "%B, phần %A: Không PLT hoặc GOT cho định vị lại %s đối với ký hiệu `%s'" + +#: elf32-cris.c:1107 +msgid "%B, section %A: No PLT for relocation %s against symbol `%s'" +msgstr "%B, phần %A: Không PLT cho định vị lại %s đối với ký hiệu `%s'" + +#: elf32-cris.c:1113 elf32-cris.c:1245 +msgid "[whose name is lost]" +msgstr "[tên của chúng bị mất]" + +#: elf32-cris.c:1231 +msgid "%B, section %A: relocation %s with non-zero addend %d against local symbol" +msgstr "%B, phần %A: định vị lại %s với phần thêm không rỗng %d đối với ký hiệu nội bộ" + +#: elf32-cris.c:1239 +msgid "%B, section %A: relocation %s with non-zero addend %d against symbol `%s'" +msgstr "%B, phần %A: định vị lại %s với phần thêm không rỗng %d đối với ký hiệu `%s'" + +#: elf32-cris.c:1265 +msgid "%B, section %A: relocation %s is not allowed for global symbol: `%s'" +msgstr "%B, phần %A: định vị lại %s không cho phép cho ký hiệu toàn cầu: `%s'" + +#: elf32-cris.c:1281 +msgid "%B, section %A: relocation %s with no GOT created" +msgstr "%B, phần %A: đã tạo định vị lại %s không có GOT" + +#: elf32-cris.c:1399 +msgid "%B: Internal inconsistency; no relocation section %s" +msgstr "%B: Thay đổi nội bộ; không có phần định vị lại %s" + +#: elf32-cris.c:2507 +msgid "" +"%B, section %A:\n" +" v10/v32 compatible object %s must not contain a PIC relocation" +msgstr "" +"%B, phần %A:\n" +" vật thể tương thích v10/v32 %s không được chứa định vị lại PIC" + +#: elf32-cris.c:2694 elf32-cris.c:2762 +msgid "" +"%B, section %A:\n" +" relocation %s should not be used in a shared object; recompile with -fPIC" +msgstr "" +"%B, phần %A:\n" +" không được sử dụng định vị lại %s trong một vật thể chia sẻ; hãy biên dịch lại với -fPIC" + +#: elf32-cris.c:3192 +msgid "Unexpected machine number" +msgstr "Số của máy không mong đợi" + +#: elf32-cris.c:3246 +#, c-format +msgid " [symbols have a _ prefix]" +msgstr " [ký hiệu có một _ ở trước]" + +#: elf32-cris.c:3249 +#, c-format +msgid " [v10 and v32]" +msgstr " [v10 và v32]" + +#: elf32-cris.c:3252 +#, c-format +msgid " [v32]" +msgstr " [v32]" + +#: elf32-cris.c:3297 +msgid "%B: uses _-prefixed symbols, but writing file with non-prefixed symbols" +msgstr "%B: dùng ký hiệu có _ ở trước, nhưng ghi tập tin với ký hiệu không có tiền tố đó" + +#: elf32-cris.c:3298 +msgid "%B: uses non-prefixed symbols, but writing file with _-prefixed symbols" +msgstr "%B: dùng ký hiệu không có tiền tố, nhưng ghi tập tin với ký hiệu có _ ở trước" + +#: elf32-cris.c:3317 +msgid "%B contains CRIS v32 code, incompatible with previous objects" +msgstr "%B chứa mã CRIS v32, không tương thích với các vật thể trước" + +#: elf32-cris.c:3319 +msgid "%B contains non-CRIS-v32 code, incompatible with previous objects" +msgstr "%B chứa mã không phải CRIS v32, không tương thích với các vật thể trước" + +#: elf32-frv.c:1522 elf32-frv.c:1671 +msgid "relocation requires zero addend" +msgstr "định vị lại yêu cầu phần thêm rỗng" + +#: elf32-frv.c:2901 +msgid "%B(%A+0x%x): relocation to `%s+%x' may have caused the error above" +msgstr "%B(%A+0x%x): định vị lại tới `%s+%x' có thể gây ra lỗi trên" + +#: elf32-frv.c:2914 +msgid "relocation references symbol not defined in the module" +msgstr "định vị lại chỉ đến ký hiệu chưa xác định trong môđun" + +#: elf32-frv.c:2990 +msgid "R_FRV_GETTLSOFF not applied to a call instruction" +msgstr "R_FRV_GETTLSOFF không áp dụng tới một chỉ dẫn gọi call" + +#: elf32-frv.c:3032 +msgid "R_FRV_GOTTLSDESC12 not applied to an lddi instruction" +msgstr "R_FRV_GOTTLSDESC12 không áp dụng tới một chỉ dẫn lddi" + +#: elf32-frv.c:3103 +msgid "R_FRV_GOTTLSDESCHI not applied to a sethi instruction" +msgstr "R_FRV_GOTTLSDESCHI không áp dụng tới một chỉ dẫn sethi" + +#: elf32-frv.c:3140 +msgid "R_FRV_GOTTLSDESCLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_GOTTLSDESCLO không áp dụng tới một chỉ dẫn setlo hay setlos" + +#: elf32-frv.c:3188 +msgid "R_FRV_TLSDESC_RELAX not applied to an ldd instruction" +msgstr "R_FRV_TLSDESC_RELAX không áp dụng tới một chỉ dẫn ldd" + +#: elf32-frv.c:3272 +msgid "R_FRV_GETTLSOFF_RELAX not applied to a calll instruction" +msgstr "R_FRV_GETTLSOFF_RELAX không áp dụng tới một chỉ dẫn calll" + +#: elf32-frv.c:3327 +msgid "R_FRV_GOTTLSOFF12 not applied to an ldi instruction" +msgstr "R_FRV_GOTTLSOFF12 không áp dụng tới một chỉ dẫn ldi" + +#: elf32-frv.c:3357 +msgid "R_FRV_GOTTLSOFFHI not applied to a sethi instruction" +msgstr "R_FRV_GOTTLSOFFHI không áp dụng tới một chỉ dẫn sethi" + +#: elf32-frv.c:3386 +msgid "R_FRV_GOTTLSOFFLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_GOTTLSOFFLO không áp dụng tới một chỉ dẫn setlo hay setlos" + +#: elf32-frv.c:3417 +msgid "R_FRV_TLSOFF_RELAX not applied to an ld instruction" +msgstr "R_FRV_TLSOFF_RELAX không áp dụng tới một chỉ dẫn ld" + +#: elf32-frv.c:3462 +msgid "R_FRV_TLSMOFFHI not applied to a sethi instruction" +msgstr "R_FRV_TLSMOFFHI không áp dụng tới một chỉ dẫn sethi" + +#: elf32-frv.c:3489 +msgid "R_FRV_TLSMOFFLO not applied to a setlo or setlos instruction" +msgstr "R_FRV_TLSMOFFLO không áp dụng tới một chỉ dẫn setlo hay setlos" + +#: elf32-frv.c:3610 +msgid "R_FRV_FUNCDESC references dynamic symbol with nonzero addend" +msgstr "R_FRV_FUNCDESC chỉ đến ký hiệu động với phần thêm không rỗng" + +#: elf32-frv.c:3649 elf32-frv.c:3762 +msgid "cannot emit fixups in read-only section" +msgstr "không thể sửa đổi trong phần chỉ đọc" + +#: elf32-frv.c:3675 elf32-frv.c:3802 +msgid "cannot emit dynamic relocations in read-only section" +msgstr "không thể định vị lại động trong phần chỉ đọc" + +#: elf32-frv.c:3720 +msgid "R_FRV_FUNCDESC_VALUE references dynamic symbol with nonzero addend" +msgstr "R_FRV_FUNCDESC_VALUE chỉ đến ký hiệu động với phần thêm không rỗng" + +#: elf32-frv.c:3970 elf32-frv.c:4126 +msgid "%B(%A+0x%lx): reloc against `%s': %s" +msgstr "%B(%A+0x%lx): reloc đối với `%s': %s" + +#: elf32-frv.c:3972 elf32-frv.c:3976 +msgid "relocation references a different segment" +msgstr "định vị lại chỉ đến một đoạn khác" + +#: elf32-frv.c:6344 +msgid "%B: unsupported relocation type %i" +msgstr "%B: dạng định vị lại không hỗ trợ %i" + +#: elf32-frv.c:6662 +#, c-format +msgid "%s: compiled with %s and linked with modules that use non-pic relocations" +msgstr "%s: biên dịch với %s và liên kết với môđun sử dụng định vị lại không pic" + +#: elf32-frv.c:6715 elf32-iq2000.c:796 +#, c-format +msgid "%s: compiled with %s and linked with modules compiled with %s" +msgstr "%s: biên dịch với %s và liên kết với môđun biên dịch với %s" + +#: elf32-frv.c:6727 +#, c-format +msgid "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: sử dụng vùng e_flags không biết (0x%lx) khác với mođun trước (0x%lx)" + +#: elf32-frv.c:6748 +#, c-format +msgid "%s: cannot link non-fdpic object file into fdpic executable" +msgstr "%s: không thể liên kết tập tin vật thể không phải fdpic vào một fdpic có thể thực hiện" + +#: elf32-frv.c:6752 +#, c-format +msgid "%s: cannot link fdpic object file into non-fdpic executable" +msgstr "%s: không thể liên kết tập tin vật thể fdpic vào một tập tin không phải fdpic có thể thực hiện" + +#: elf32-frv.c:6777 elf32-iq2000.c:833 +#, c-format +msgid "private flags = 0x%lx:" +msgstr "cờ riêng = 0x%lx:" + +#: elf32-gen.c:83 elf64-gen.c:83 +msgid "%B: Relocations in generic ELF (EM: %d)" +msgstr "%B: Định vị lại trong ELF chung (EM: %d)" + +#: elf32-hppa.c:542 elf32-m68hc1x.c:161 elf64-ppc.c:3644 +msgid "%B: cannot create stub entry %s" +msgstr "%B: không thể tạo mục gốc %s" + +#: elf32-hppa.c:795 elf32-hppa.c:3359 +msgid "%B(%A+0x%lx): cannot reach %s, recompile with -ffunction-sections" +msgstr "%B(%A+0x%lx): không thể tìm đến %s, hãy biên dịch lại với -ffunction-sections" + +#: elf32-hppa.c:1176 +msgid "%B: relocation %s can not be used when making a shared object; recompile with -fPIC" +msgstr "%B: không dùng được định vị lại %s khi tạo một vật thể chia sẽ, hãy biên dịch lại với -fPIC" + +#: elf32-hppa.c:1370 +#, c-format +msgid "Could not find relocation section for %s" +msgstr "Không tìm thấy phần định vị lại cho %s" + +#: elf32-hppa.c:2623 +msgid "%B: duplicate export stub %s" +msgstr "%B: xuất gốc %s trùng nhau" + +#: elf32-hppa.c:3214 +msgid "%B(%A+0x%lx): %s fixup for insn 0x%x is not supported in a non-shared link" +msgstr "%B(%A+0x%lx): %s sửa đổi cho insn 0x%x không được hỗ trợ trong một liên kết không chia sẻ" + +#: elf32-hppa.c:3844 +msgid "%B(%A+0x%lx): cannot handle %s for %s" +msgstr "%B(%A+0x%lx): không điều khiển được %s cho %s" + +#: elf32-hppa.c:4137 +msgid ".got section not immediately after .plt section" +msgstr "phần .got không đứng ngay sau phần .plt" + +#: elf32-i386.c:326 +msgid "%B: invalid relocation type %d" +msgstr "%B: dạng định vị lại sai %d" + +#: elf32-i386.c:865 elf32-s390.c:985 elf32-sparc.c:910 elf32-xtensa.c:788 +#: elf64-s390.c:938 elf64-x86-64.c:646 +msgid "%B: bad symbol index: %d" +msgstr "%B: chỉ mục ký hiệu xấu: %d" + +#: elf32-i386.c:973 elf32-s390.c:1162 elf32-sh.c:6388 elf32-sparc.c:1033 +#: elf64-s390.c:1124 +msgid "%B: `%s' accessed both as normal and thread local symbol" +msgstr "%B: đã truy cập `%s' theo cả hai như thông thường và ký hiệu luồng nội bộ" + +#: elf32-i386.c:1088 elf32-s390.c:1271 elf64-ppc.c:4676 elf64-s390.c:1236 +#: elf64-x86-64.c:882 +msgid "%B: bad relocation section name `%s'" +msgstr "%B: tên phần định lại xấu `%s'" + +#: elf32-i386.c:2043 +msgid "%B: unrecognized relocation (0x%x) in section `%A'" +msgstr "%B: định vị lại không nhận ra (0x%x) trong phần `%A'" + +#: elf32-i386.c:2287 +msgid "%B: relocation R_386_GOTOFF against protected function `%s' can not be used when making a shared object" +msgstr "%B: không dùng được định vị lại R_386_GOTOFF đối với hàm số đã bảo vệ `%s' khi tạo một vật thể chia sẻ" + +#: elf32-i386.c:2931 elf32-m68k.c:1700 elf32-s390.c:2993 elf32-sparc.c:2859 +#: elf32-xtensa.c:2321 elf64-s390.c:2990 elf64-sparc.c:2684 +#: elf64-x86-64.c:2438 +msgid "%B(%A+0x%lx): unresolvable relocation against symbol `%s'" +msgstr "%B(%A+0x%lx): định vị lại không tìm thấy đối với ký hiệu `%s'" + +#: elf32-i386.c:2971 elf32-m68k.c:1740 elf32-s390.c:3044 elf64-s390.c:3041 +#: elf64-x86-64.c:2482 +msgid "%B(%A+0x%lx): reloc against `%s': error %d" +msgstr "%B(%A+0x%lx): reloc đối với `%s': lỗi %d" + +#: elf32-ip2k.c:557 elf32-ip2k.c:563 elf32-ip2k.c:726 elf32-ip2k.c:732 +msgid "ip2k relaxer: switch table without complete matching relocation information." +msgstr "trình giảm nhẹ ip2k: chuyển đổi bảng không có tương ứng hoàn toàn với thông tin định vị lại." + +#: elf32-ip2k.c:580 elf32-ip2k.c:759 +msgid "ip2k relaxer: switch table header corrupt." +msgstr "trình giảm nhẹ ip2k: phần đầu của bảng chuyển đổi bị hỏng." + +#: elf32-ip2k.c:1377 +#, c-format +msgid "ip2k linker: missing page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "trình liên kết ip2k: thiếu hướng dẫn trang tại 0x%08lx (đích = 0x%08lx)." + +#: elf32-ip2k.c:1391 +#, c-format +msgid "ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)." +msgstr "trình liên kết ip2k: thừa hướng dẫn trang tại 0x%08lx (đích = 0x%08lx)." + +#. Only if it's not an unresolved symbol. +#: elf32-ip2k.c:1557 +msgid "unsupported relocation between data/insn address spaces" +msgstr "định vị lại không hỗ trợ giữa không gian địa chỉ dữ liệu/insn" + +#: elf32-iq2000.c:809 +#, c-format +msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%s: sử dụng vùng e_flags (0x%lx) khác với mođun trước (0x%lx)" + +#: elf32-m32r.c:1530 +msgid "SDA relocation when _SDA_BASE_ not defined" +msgstr "định vị lại SDA khi chưa xác định _SDA_BASE_" + +#: elf32-m32r.c:2604 elf64-alpha.c:4181 elf64-alpha.c:4307 elf32-ia64.c:3910 +#: elf64-ia64.c:3910 +msgid "%B: unknown relocation type %d" +msgstr "%B: dạng định vị lại không rõ %d" + +#: elf32-m32r.c:2789 elf64-sh64.c:1626 elf-m10300.c:1481 +#, c-format +msgid "%s: warning: unresolvable relocation against symbol `%s' from %s section" +msgstr "%s: cảnh báo: định vị lại không tìm thấy đối với ký hiệu `%s' từ phần %s" + +#: elf32-m32r.c:3187 +msgid "%B: The target (%s) of an %s relocation is in the wrong section (%A)" +msgstr "%B: Đích (%s) của một định vị lại %s nằm trong phần sai (%A)" + +#: elf32-m32r.c:3719 +msgid "%B: Instruction set mismatch with previous modules" +msgstr "%B: Bộ chỉ dẫn không tương ứng với các môđun trước" + +#: elf32-m32r.c:3741 +#, c-format +msgid "private flags = %lx" +msgstr "cờ riêng = %lx" + +#: elf32-m32r.c:3746 +#, c-format +msgid ": m32r instructions" +msgstr ": các chỉ dẫn m32r" + +#: elf32-m32r.c:3747 +#, c-format +msgid ": m32rx instructions" +msgstr ": các chỉ dẫn m32rx" + +#: elf32-m32r.c:3748 +#, c-format +msgid ": m32r2 instructions" +msgstr ": các chỉ dẫn m32r2" + +#: elf32-m68hc1x.c:1101 +#, c-format +msgid "Reference to the far symbol `%s' using a wrong relocation may result in incorrect execution" +msgstr "Liên kết tới ký hiệu xa `%s' sử dụng một định vị lại sai có thể dẫn đến sự thực hiện sai" + +#: elf32-m68hc1x.c:1124 +#, c-format +msgid "banked address [%lx:%04lx] (%lx) is not in the same bank as current banked address [%lx:%04lx] (%lx)" +msgstr "địa chỉ ngân hàng [%lx:%04lx] (%lx) không trong cùng ngân hàng với địa chỉ ngân hàng hiện thời [%lx:%04lx] (%lx)" + +#: elf32-m68hc1x.c:1143 +#, c-format +msgid "reference to a banked address [%lx:%04lx] in the normal address space at %04lx" +msgstr "liên kết tới một địa chỉ ngân hàng [%lx:%04lx] trong không gian địa chỉ thông thường tại %04lx" + +#: elf32-m68hc1x.c:1276 +msgid "%B: linking files compiled for 16-bit integers (-mshort) and others for 32-bit integers" +msgstr "%B: đang liên kết các tập tin biên dịch cho số nguyên 16 bit (-mshort) và những tập tin khác cho số nguyên 32 bit" + +#: elf32-m68hc1x.c:1283 +msgid "%B: linking files compiled for 32-bit double (-fshort-double) and others for 64-bit double" +msgstr "%B: đang liên kết các tập tin biên dịch 32 bit đôi (-mshort) và những tập tin khác cho 64 bit đôi" + +#: elf32-m68hc1x.c:1292 +msgid "%B: linking files compiled for HCS12 with others compiled for HC12" +msgstr "%B: đang liên kết tập tin biên dịch cho HCS12 với các tập tin khác biên dịch cho HC12" + +#: elf32-m68hc1x.c:1308 elf32-ppc.c:2298 elf64-sparc.c:3090 elfxx-mips.c:9807 +msgid "%B: uses different e_flags (0x%lx) fields than previous modules (0x%lx)" +msgstr "%B: sử dụng vùng e_flags (0x%lx) khác với mođun trước (0x%lx)" + +#: elf32-m68hc1x.c:1336 +#, c-format +msgid "[abi=32-bit int, " +msgstr "[abi= int 32 bit, " + +#: elf32-m68hc1x.c:1338 +#, c-format +msgid "[abi=16-bit int, " +msgstr "[abi= int 16 bit, " + +#: elf32-m68hc1x.c:1341 +#, c-format +msgid "64-bit double, " +msgstr "64 bit đôi, " + +#: elf32-m68hc1x.c:1343 +#, c-format +msgid "32-bit double, " +msgstr "32 bit đôi, " + +#: elf32-m68hc1x.c:1346 +#, c-format +msgid "cpu=HC11]" +msgstr "cpu=HC11]" + +#: elf32-m68hc1x.c:1348 +#, c-format +msgid "cpu=HCS12]" +msgstr "cpu=HCS12]" + +#: elf32-m68hc1x.c:1350 +#, c-format +msgid "cpu=HC12]" +msgstr "cpu=HC12]" + +#: elf32-m68hc1x.c:1353 +#, c-format +msgid " [memory=bank-model]" +msgstr " [bộ nhớ=kiểu nhà băng]" + +#: elf32-m68hc1x.c:1355 +#, c-format +msgid " [memory=flat]" +msgstr " [bộ nhớ=phẳng]" + +#: elf32-m68k.c:400 +#, c-format +msgid " [cpu32]" +msgstr " [cpu32]" + +#: elf32-m68k.c:403 +#, c-format +msgid " [m68000]" +msgstr " [m68000]" + +#: elf32-mcore.c:353 elf32-mcore.c:455 +msgid "%B: Relocation %s (%d) is not currently supported.\n" +msgstr "%B: Hiện thời chưa hỗ trợ định vị lại %s (%d).\n" + +#: elf32-mcore.c:441 +msgid "%B: Unknown relocation type %d\n" +msgstr "%B: Dạng định vị lại không rõ %d\n" + +#: elf32-mips.c:971 elf64-mips.c:1929 elfn32-mips.c:1774 +msgid "literal relocation occurs for an external symbol" +msgstr "định vị lại văn bản cho một ký hiệu ở ngoài" + +#: elf32-mips.c:1011 elf64-mips.c:1972 elfn32-mips.c:1815 +msgid "32bits gp relative relocation occurs for an external symbol" +msgstr "định vị lại tương đối 32 bit gp cho một ký hiệu ở ngoài" + +#: elf32-mips.c:1134 elf64-mips.c:2066 elfn32-mips.c:1915 +#, c-format +msgid "Linking mips16 objects into %s format is not supported" +msgstr "Không hỗ trợ liên kết vật thể mips16 vào định dạng %s" + +#: elf32-ppc.c:2181 +#, c-format +msgid "generic linker can't handle %s" +msgstr "trình liên kết chung không điều khiển được %s" + +#: elf32-ppc.c:2263 +msgid "%B: compiled with -mrelocatable and linked with modules compiled normally" +msgstr "%B: đã biên dịch với -mrelocatable và đã liên kết với các môđun biên dịch bình thường" + +#: elf32-ppc.c:2271 +msgid "%B: compiled normally and linked with modules compiled with -mrelocatable" +msgstr "%B: đã biên dịch bình thường và đã liên kết với các môđun biên dịch với -mrelocatable" + +#: elf32-ppc.c:3526 +msgid "%B: relocation %s cannot be used when making a shared object" +msgstr "%B: không sử dụng được định vị lại %s khi tạo một vật thể chia sẻ" + +#. It does not make sense to have a procedure linkage +#. table entry for a local symbol. +#: elf32-ppc.c:3731 +msgid "%B(%A+0x%lx): %s reloc against local symbol" +msgstr "%B(%A+0x%lx): %s reloc đối với ký hiệu nội bộ" + +#: elf32-ppc.c:4935 elf64-ppc.c:9967 +msgid "%B: unknown relocation type %d for symbol %s" +msgstr "%B: dạng định vị lại %d không rõ cho ký hiệu %s" + +#: elf32-ppc.c:5184 +msgid "%B(%A+0x%lx): non-zero addend on %s reloc against `%s'" +msgstr "%B(%A+0x%lx): phần thêm không rỗng trên reloc %s đối với `%s'" + +#: elf32-ppc.c:5510 elf32-ppc.c:5536 elf32-ppc.c:5595 +msgid "%B: the target (%s) of a %s relocation is in the wrong output section (%s)" +msgstr "%B: đích (%s) của một định vị lại %s nằm trong phần ra không đúng (%s)" + +#: elf32-ppc.c:5650 +msgid "%B: relocation %s is not yet supported for symbol %s." +msgstr "%B: định vị lại %s chưa hỗ trợ cho ký hiệu %s." + +#: elf32-ppc.c:5705 elf64-ppc.c:10606 +msgid "%B(%A+0x%lx): unresolvable %s relocation against symbol `%s'" +msgstr "%B(%A+0x%lx): định vị lại không thể tìm thấy %s đối với ký hiệu `%s'" + +#: elf32-ppc.c:5756 elf64-ppc.c:10653 +msgid "%B(%A+0x%lx): %s reloc against `%s': error %d" +msgstr "%B(%A+0x%lx): %s reloc đối với `%s': lỗi %d" + +#: elf32-ppc.c:5999 +msgid "corrupt or empty %s section in %B" +msgstr "phần %s bị hỏng hoặc rỗng trong %B" + +#: elf32-ppc.c:6006 +msgid "unable to read in %s section from %B" +msgstr "không đọc được trong phần %s từ %B" + +#: elf32-ppc.c:6012 +msgid "corrupt %s section in %B" +msgstr "phần %s hỏng trong %B" + +#: elf32-ppc.c:6055 +msgid "warning: unable to set size of %s section in %B" +msgstr "cảnh báo: không đặt được kích thước của phần %s trong %B" + +#: elf32-ppc.c:6104 +msgid "failed to allocate space for new APUinfo section." +msgstr "phân phối không gian cho phần APUinfo mới không thành công." + +#: elf32-ppc.c:6123 +msgid "failed to compute new APUinfo section." +msgstr "tính toán phần APUinfo mới không thành công." + +#: elf32-ppc.c:6126 +msgid "failed to install new APUinfo section." +msgstr "cài đặt phần APUinfo mới không thành công." + +#: elf32-s390.c:2234 elf64-s390.c:2205 +msgid "%B(%A+0x%lx): invalid instruction for TLS relocation %s" +msgstr "%B(%A+0x%lx): chỉ dẫn sai cho định vị lại TLS %s" + +#: elf32-sh64.c:218 elf64-sh64.c:2319 +#, c-format +msgid "%s: compiled as 32-bit object and %s is 64-bit" +msgstr "%s: biên dịch như một vật thể 32 bit và %s là 64 bit" + +#: elf32-sh64.c:221 elf64-sh64.c:2322 +#, c-format +msgid "%s: compiled as 64-bit object and %s is 32-bit" +msgstr "%s: biên dịch như một vật thể 64 bit và %s là 32 bit" + +#: elf32-sh64.c:223 elf64-sh64.c:2324 +#, c-format +msgid "%s: object size does not match that of target %s" +msgstr "%s: kích thước vật thể không tương ứng với đối tượng đích %s" + +#: elf32-sh64.c:445 elf64-sh64.c:2890 +#, c-format +msgid "%s: encountered datalabel symbol in input" +msgstr "%s: tìm thấy ký hiệu nhãn dữ liệu trong nhập vào" + +#: elf32-sh64.c:522 +msgid "PTB mismatch: a SHmedia address (bit 0 == 1)" +msgstr "không tương ứng PTB: một địa chỉ SHmedia (bit 0 == 1)" + +#: elf32-sh64.c:525 +msgid "PTA mismatch: a SHcompact address (bit 0 == 0)" +msgstr "không tương ứng PTA: một địa chỉ SHcompact (bit 0 == 0)" + +#: elf32-sh64.c:543 +#, c-format +msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16" +msgstr "%s: Lỗi GAS: insn PTB không mong đợi với R_SH_PT_16" + +#: elf32-sh64.c:592 +msgid "%B: error: unaligned relocation type %d at %08x reloc %p\n" +msgstr "%B: lỗi: dạng định vị lại chưa sắp hàng %d tại %08x reloc %p\n" + +#: elf32-sh64.c:668 +#, c-format +msgid "%s: could not write out added .cranges entries" +msgstr "%s: không ghi ra được các mục .cranges đã thêm vào" + +#: elf32-sh64.c:728 +#, c-format +msgid "%s: could not write out sorted .cranges entries" +msgstr "%s: không ghi ra được các mục .cranges đã sắp xếp" + +#: elf32-sh.c:2176 +msgid "%B: 0x%lx: warning: bad R_SH_USES offset" +msgstr "%B: 0x%lx: cảnh báo: bộ R_SH_USES xấu" + +#: elf32-sh.c:2188 +msgid "%B: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x" +msgstr "%B: 0x%lx: cảnh báo: R_SH_USES chỉ tới một insn không nhận ra 0x%x" + +#: elf32-sh.c:2205 +msgid "%B: 0x%lx: warning: bad R_SH_USES load offset" +msgstr "%B: 0x%lx: cảnh báo: bộ nạp R_SH_USES xấu" + +#: elf32-sh.c:2220 +msgid "%B: 0x%lx: warning: could not find expected reloc" +msgstr "%B: 0x%lx: cảnh báo: không tìm thấy reloc mong đợi" + +#: elf32-sh.c:2248 +msgid "%B: 0x%lx: warning: symbol in unexpected section" +msgstr "%B: 0x%lx: cảnh báo: ký hiệu nằm trong phần không mong đợi" + +#: elf32-sh.c:2361 +msgid "%B: 0x%lx: warning: could not find expected COUNT reloc" +msgstr "%B: 0x%lx: cảnh báo: không tìm thấy reloc COUNT mong đợi" + +#: elf32-sh.c:2370 +msgid "%B: 0x%lx: warning: bad count" +msgstr "%B: 0x%lx: cảnh báo: số đếm xấu" + +#: elf32-sh.c:2765 elf32-sh.c:3135 +msgid "%B: 0x%lx: fatal: reloc overflow while relaxing" +msgstr "%B: 0x%lx: lỗi nặng: reloc tràn ra khi giảm nhẹ" + +#: elf32-sh.c:4558 elf64-sh64.c:1509 +msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled" +msgstr "Không điều khiển STO_SH5_ISA32 không mong đợi trên ký hiệu nội bộ" + +#: elf32-sh.c:4709 +msgid "%B(%A): unresolvable relocation against symbol `%s'" +msgstr "%B(%A): định vị lại không tìm thấy đối với ký hiệu `%s'" + +#: elf32-sh.c:4779 +msgid "%B: 0x%lx: fatal: unaligned branch target for relax-support relocation" +msgstr "" + +#: elf32-sh.c:4812 elf32-sh.c:4827 +msgid "%B: 0x%lx: fatal: unaligned %s relocation 0x%lx" +msgstr "" + +#: elf32-sh.c:4841 +msgid "%B: 0x%lx: fatal: R_SH_PSHA relocation %d not in range -32..32" +msgstr "" + +#: elf32-sh.c:4855 +msgid "%B: 0x%lx: fatal: R_SH_PSHL relocation %d not in range -32..32" +msgstr "" + +#: elf32-sh.c:6599 elf64-alpha.c:4725 +msgid "%B: TLS local exec code cannot be linked into shared objects" +msgstr "" + +#: elf32-sh-symbian.c:128 +msgid "%B: IMPORT AS directive for %s conceals previous IMPORT AS" +msgstr "" + +#: elf32-sh-symbian.c:381 +msgid "%B: Unrecognised .directive command: %s" +msgstr "" + +#: elf32-sh-symbian.c:502 +msgid "%B: Failed to add renamed symbol %s" +msgstr "" + +#: elf32-sparc.c:2501 elf64-sparc.c:2340 +msgid "%B: probably compiled without -fPIC?" +msgstr "" + +#: elf32-sparc.c:3324 +msgid "%B: compiled for a 64 bit system and target is 32 bit" +msgstr "" + +#: elf32-sparc.c:3337 +msgid "%B: linking little endian files with big endian files" +msgstr "" + +#: elf32-v850.c:769 +#, c-format +msgid "Variable `%s' cannot occupy in multiple small data regions" +msgstr "" + +#: elf32-v850.c:772 +#, c-format +msgid "Variable `%s' can only be in one of the small, zero, and tiny data regions" +msgstr "" + +#: elf32-v850.c:775 +#, c-format +msgid "Variable `%s' cannot be in both small and zero data regions simultaneously" +msgstr "" + +#: elf32-v850.c:778 +#, c-format +msgid "Variable `%s' cannot be in both small and tiny data regions simultaneously" +msgstr "" + +#: elf32-v850.c:781 +#, c-format +msgid "Variable `%s' cannot be in both zero and tiny data regions simultaneously" +msgstr "" + +#: elf32-v850.c:1090 +#, c-format +msgid "FAILED to find previous HI16 reloc\n" +msgstr "" + +#: elf32-v850.c:1761 +msgid "could not locate special linker symbol __gp" +msgstr "" + +#: elf32-v850.c:1765 +msgid "could not locate special linker symbol __ep" +msgstr "" + +#: elf32-v850.c:1769 +msgid "could not locate special linker symbol __ctbp" +msgstr "" + +#: elf32-v850.c:1954 +msgid "%B: Architecture mismatch with previous modules" +msgstr "" + +#: elf32-v850.c:1975 +#, c-format +msgid "private flags = %lx: " +msgstr "" + +#: elf32-v850.c:1980 +#, c-format +msgid "v850 architecture" +msgstr "" + +#: elf32-v850.c:1981 +#, c-format +msgid "v850e architecture" +msgstr "" + +#: elf32-v850.c:1982 +#, c-format +msgid "v850e1 architecture" +msgstr "" + +#: elf32-vax.c:549 +#, c-format +msgid " [nonpic]" +msgstr "" + +#: elf32-vax.c:552 +#, c-format +msgid " [d-float]" +msgstr "" + +#: elf32-vax.c:555 +#, c-format +msgid " [g-float]" +msgstr "" + +#: elf32-vax.c:663 +#, c-format +msgid "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of %ld" +msgstr "" + +#: elf32-vax.c:1636 +#, c-format +msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored" +msgstr "" + +#: elf32-vax.c:1760 +#, c-format +msgid "%s: warning: %s relocation against symbol `%s' from %s section" +msgstr "" + +#: elf32-vax.c:1766 +#, c-format +msgid "%s: warning: %s relocation to 0x%x from %s section" +msgstr "" + +#: elf32-xstormy16.c:462 elf32-ia64.c:2394 elf64-ia64.c:2394 +msgid "non-zero addend in @fptr reloc" +msgstr "" + +#: elf32-xtensa.c:709 +msgid "%B(%A): invalid property table" +msgstr "" + +#: elf32-xtensa.c:2209 +msgid "%B(%A+0x%lx): relocation offset out of range (size=0x%x)" +msgstr "" + +#: elf32-xtensa.c:2266 +msgid "dynamic relocation in read-only section" +msgstr "" + +#: elf32-xtensa.c:2430 +msgid "internal inconsistency in size of .got.loc section" +msgstr "" + +#: elf32-xtensa.c:2744 +msgid "%B: incompatible machine type. Output is 0x%x. Input is 0x%x" +msgstr "" + +#: elf32-xtensa.c:3890 elf32-xtensa.c:3898 +msgid "Attempt to convert L32R/CALLX to CALL failed" +msgstr "" + +#: elf32-xtensa.c:5476 elf32-xtensa.c:5552 elf32-xtensa.c:6505 +#: elf32-xtensa.c:6559 +msgid "%B(%A+0x%lx): could not decode instruction; possible configuration mismatch" +msgstr "" + +#: elf32-xtensa.c:6378 elf32-xtensa.c:6541 +msgid "%B(%A+0x%lx): could not decode instruction for XTENSA_ASM_SIMPLIFY relocation; possible configuration mismatch" +msgstr "" + +#: elf32-xtensa.c:7859 +msgid "invalid relocation address" +msgstr "" + +#: elf32-xtensa.c:7908 +msgid "overflow after relaxation" +msgstr "" + +#: elf32-xtensa.c:9036 +msgid "%B(%A+0x%lx): unexpected fix for %s relocation" +msgstr "" + +#: elf64-alpha.c:1069 +msgid "GPDISP relocation did not find ldah and lda instructions" +msgstr "" + +#: elf64-alpha.c:3557 +#, c-format +msgid "Symbol %s has no GOT subsection for offset 0x%x" +msgstr "" + +#: elf64-alpha.c:3642 +msgid "%B: .got subsegment exceeds 64K (size %d)" +msgstr "" + +#: elf64-alpha.c:4479 elf64-alpha.c:4491 +msgid "%B: gp-relative relocation against dynamic symbol %s" +msgstr "" + +#: elf64-alpha.c:4517 elf64-alpha.c:4650 +msgid "%B: pc-relative relocation against dynamic symbol %s" +msgstr "" + +#: elf64-alpha.c:4545 +msgid "%B: change in gp: BRSGP %s" +msgstr "" + +#: elf64-alpha.c:4570 +msgid "" +msgstr "" + +#: elf64-alpha.c:4575 +msgid "%B: !samegp reloc against symbol without .prologue: %s" +msgstr "" + +#: elf64-alpha.c:4626 +msgid "%B: unhandled dynamic relocation against %s" +msgstr "" + +#: elf64-alpha.c:4709 +msgid "%B: dtp-relative relocation against dynamic symbol %s" +msgstr "" + +#: elf64-alpha.c:4732 +msgid "%B: tp-relative relocation against dynamic symbol %s" +msgstr "" + +#: elf64-hppa.c:2085 +#, c-format +msgid "stub entry for %s cannot load .plt, dp offset = %ld" +msgstr "" + +#: elf64-mmix.c:1163 +#, c-format +msgid "" +"%s: Internal inconsistency error for value for\n" +" linker-allocated global register: linked: 0x%lx%08lx != relaxed: 0x%lx%08lx\n" +msgstr "" + +#: elf64-mmix.c:1602 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: (unknown) in %s" +msgstr "" + +#: elf64-mmix.c:1607 +#, c-format +msgid "%s: base-plus-offset relocation against register symbol: %s in %s" +msgstr "" + +#: elf64-mmix.c:1651 +#, c-format +msgid "%s: register relocation against non-register symbol: (unknown) in %s" +msgstr "" + +#: elf64-mmix.c:1656 +#, c-format +msgid "%s: register relocation against non-register symbol: %s in %s" +msgstr "" + +#: elf64-mmix.c:1693 +#, c-format +msgid "%s: directive LOCAL valid only with a register or absolute value" +msgstr "" + +#: elf64-mmix.c:1721 +#, c-format +msgid "%s: LOCAL directive: Register $%ld is not a local register. First global register is $%ld." +msgstr "" + +#: elf64-mmix.c:2201 +#, c-format +msgid "%s: Error: multiple definition of `%s'; start of %s is set in a earlier linked file\n" +msgstr "" + +#: elf64-mmix.c:2260 +msgid "Register section has contents\n" +msgstr "" + +#: elf64-mmix.c:2453 +#, c-format +msgid "" +"Internal inconsistency: remaining %u != max %u.\n" +" Please report this bug." +msgstr "" + +#: elf64-ppc.c:2490 libbfd.c:826 +msgid "%B: compiled for a big endian system and target is little endian" +msgstr "" + +#: elf64-ppc.c:2493 libbfd.c:828 +msgid "%B: compiled for a little endian system and target is big endian" +msgstr "" + +#: elf64-ppc.c:5640 +#, c-format +msgid "copy reloc against `%s' requires lazy plt linking; avoid setting LD_BIND_NOW=1 or upgrade gcc" +msgstr "" + +#: elf64-ppc.c:6043 +msgid "%B: .opd is not a regular array of opd entries" +msgstr "" + +#: elf64-ppc.c:6052 +msgid "%B: unexpected reloc type %u in .opd section" +msgstr "" + +#: elf64-ppc.c:6072 +msgid "%B: undefined sym `%s' in .opd section" +msgstr "" + +#: elf64-ppc.c:6757 elf64-ppc.c:7132 +#, c-format +msgid "%s defined in removed toc entry" +msgstr "" + +#: elf64-ppc.c:7921 +#, c-format +msgid "can't find branch stub `%s'" +msgstr "" + +#: elf64-ppc.c:7960 elf64-ppc.c:8036 +#, c-format +msgid "linkage table error against `%s'" +msgstr "" + +#: elf64-ppc.c:8165 +#, c-format +msgid "can't build branch stub `%s'" +msgstr "" + +#: elf64-ppc.c:9093 +msgid ".glink and .plt too far apart" +msgstr "" + +#: elf64-ppc.c:9206 +msgid "stubs don't match calculated size" +msgstr "" + +#: elf64-ppc.c:9218 +#, c-format +msgid "" +"linker stubs in %u group%s\n" +" branch %lu\n" +" toc adjust %lu\n" +" long branch %lu\n" +" long toc adj %lu\n" +" plt call %lu" +msgstr "" + +#: elf64-ppc.c:9455 +msgid "%B(%A+0x%lx): %s used with TLS symbol %s" +msgstr "" + +#: elf64-ppc.c:9456 +msgid "%B(%A+0x%lx): %s used with non-TLS symbol %s" +msgstr "" + +#: elf64-ppc.c:9856 +msgid "%B(%A+0x%lx): automatic multiple TOCs not supported using your crt files; recompile with -mminimal-toc or upgrade gcc" +msgstr "" + +#: elf64-ppc.c:9864 +msgid "%B(%A+0x%lx): sibling call optimization to `%s' does not allow automatic multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `%s' extern" +msgstr "" + +#: elf64-ppc.c:10508 +msgid "%B: relocation %s is not supported for symbol %s." +msgstr "" + +#: elf64-ppc.c:10587 +msgid "%B: error: relocation %s not a multiple of %d" +msgstr "" + +#: elf64-sh64.c:1673 +#, c-format +msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n" +msgstr "" + +#: elf64-sparc.c:1419 +msgid "%B: check_relocs: unhandled reloc type %d" +msgstr "" + +#: elf64-sparc.c:1455 +msgid "%B: Only registers %%g[2367] can be declared using STT_REGISTER" +msgstr "" + +#: elf64-sparc.c:1475 +msgid "Register %%g%d used incompatibly: %s in %B, previously %s in %B" +msgstr "" + +#: elf64-sparc.c:1498 +msgid "Symbol `%s' has differing types: REGISTER in %B, previously %s in %B" +msgstr "" + +#: elf64-sparc.c:1543 +msgid "Symbol `%s' has differing types: %s in %B, previously REGISTER in %B" +msgstr "" + +#: elf64-sparc.c:3071 +msgid "%B: linking UltraSPARC specific with HAL specific code" +msgstr "" + +#: elf64-x86-64.c:667 elf64-x86-64.c:792 elf64-x86-64.c:1988 +msgid "%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC" +msgstr "" + +#: elf64-x86-64.c:735 +msgid "%B: %s' accessed both as normal and thread local symbol" +msgstr "" + +#: elf64-x86-64.c:1984 +msgid "%B: relocation R_X86_64_PC32 against protected function `%s' can not be used when making a shared object" +msgstr "" + +#: elf.c:296 +msgid "%B: invalid string offset %u >= %lu for section `%s'" +msgstr "" + +#: elf.c:543 +msgid "%B: invalid SHT_GROUP entry" +msgstr "" + +#: elf.c:613 +msgid "%B: no group info for section %A" +msgstr "" + +#: elf.c:650 +msgid "%B: unknown [%d] section `%s' in group [%s]" +msgstr "" + +#: elf.c:1011 +#, c-format +msgid "" +"\n" +"Program Header:\n" +msgstr "" + +#: elf.c:1063 +#, c-format +msgid "" +"\n" +"Dynamic Section:\n" +msgstr "" + +#: elf.c:1188 +#, c-format +msgid "" +"\n" +"Version definitions:\n" +msgstr "" + +#: elf.c:1211 +#, c-format +msgid "" +"\n" +"Version References:\n" +msgstr "" + +#: elf.c:1216 +#, c-format +msgid " required from %s:\n" +msgstr "" + +#: elf.c:1905 +msgid "%B: invalid link %lu for reloc section %s (index %u)" +msgstr "" + +#: elf.c:2910 +msgid "%B: warning: sh_link not set for section `%S'" +msgstr "" + +#: elf.c:3904 +msgid "%B: Not enough room for program headers (allocated %u, need %u)" +msgstr "" + +#: elf.c:4010 +msgid "%B: The first section in the PT_DYNAMIC segment is not the .dynamic section" +msgstr "" + +#: elf.c:4054 +msgid "%B: Not enough room for program headers, try linking with -N" +msgstr "" + +#: elf.c:4145 +msgid "%B: section %A lma 0x%lx overlaps previous sections" +msgstr "" + +#: elf.c:4546 +msgid "%B: warning: allocated section `%s' not in segment" +msgstr "" + +#: elf.c:4850 +msgid "%B: symbol `%s' required but not present" +msgstr "" + +#: elf.c:5147 +msgid "%B: warning: Empty loadable segment detected, is this intentional ?\n" +msgstr "" + +#: elf.c:5761 +#, c-format +msgid "Unable to find equivalent output section for symbol '%s' from section '%s'" +msgstr "" + +#: elf.c:6620 +msgid "%B: unsupported relocation type %s" +msgstr "" + +#: elfcode.h:1039 +#, c-format +msgid "%s: version count (%ld) does not match symbol count (%ld)" +msgstr "" + +#: elfcode.h:1266 +#, c-format +msgid "%s(%s): relocation %d has invalid symbol index %ld" +msgstr "" + +#: elf-hppa.h:1401 elf-hppa.h:1427 elf-hppa.h:1442 +msgid "%B(%A): warning: unresolvable relocation against symbol `%s'" +msgstr "" + +#: elflink.c:941 +msgid "%s: TLS definition in %B section %A mismatches non-TLS definition in %B section %A" +msgstr "" + +#: elflink.c:945 +msgid "%s: TLS reference in %B mismatches non-TLS reference in %B" +msgstr "" + +#: elflink.c:949 +msgid "%s: TLS definition in %B section %A mismatches non-TLS reference in %B" +msgstr "" + +#: elflink.c:953 +msgid "%s: TLS reference in %B mismatches non-TLS definition in %B section %A" +msgstr "" + +#: elflink.c:1508 +msgid "%B: unexpected redefinition of indirect versioned symbol `%s'" +msgstr "" + +#: elflink.c:1825 +msgid "%B: undefined versioned symbol name %s" +msgstr "" + +#: elflink.c:1974 +msgid "%B: bad reloc symbol index (0x%lx >= 0x%lx) for offset 0x%lx in section `%A'" +msgstr "" + +#: elflink.c:2164 +msgid "%B: relocation size mismatch in %B section %A" +msgstr "" + +#: elflink.c:2454 +#, c-format +msgid "warning: type and size of dynamic symbol `%s' are not defined" +msgstr "" + +#: elflink.c:2775 +msgid "warning: creating a DT_TEXTREL in a shared object." +msgstr "" + +#: elflink.c:3702 +msgid "%B: %s: invalid version %u (max %d)" +msgstr "" + +#: elflink.c:3738 +msgid "%B: %s: invalid needed version %d" +msgstr "" + +#: elflink.c:3919 +msgid "Warning: alignment %u of symbol `%s' in %B is smaller than %u in %B" +msgstr "" + +#: elflink.c:3931 +msgid "Warning: size of symbol `%s' changed from %lu in %B to %lu in %B" +msgstr "" + +#: elflink.c:4098 +#, c-format +msgid "%s: invalid DSO for symbol `%s' definition" +msgstr "" + +#: elflink.c:5155 +#, c-format +msgid "%s: undefined version: %s" +msgstr "" + +#: elflink.c:5221 +msgid "%B: .preinit_array section is not allowed in DSO" +msgstr "" + +#: elflink.c:5961 +msgid "Not enough memory to sort relocations" +msgstr "" + +#: elflink.c:6352 +msgid "%B: %s symbol `%s' in %B is referenced by DSO" +msgstr "" + +#: elflink.c:6433 +msgid "%B: could not find output section %A for input section %A" +msgstr "" + +#: elflink.c:6530 +msgid "%B: %s symbol `%s' isn't defined" +msgstr "" + +#: elflink.c:7017 +msgid "`%s' referenced in section `%A' of %B: defined in discarded section `%A' of %B\n" +msgstr "" + +#: elflink.c:7551 +msgid "%B: warning: sh_link not set for section `%A'" +msgstr "" + +#: elflink.c:7624 +#, c-format +msgid "%A has both ordered and unordered sections" +msgstr "" + +#: elflink.c:8437 elflink.c:8478 +msgid "%B: could not find output section %s" +msgstr "" + +#: elflink.c:8442 +#, c-format +msgid "warning: %s section has zero size" +msgstr "" + +#: elflink.c:9017 +msgid "Warning: gc-sections option ignored" +msgstr "" + +#: elflink.c:9606 +msgid "%B: ignoring duplicate section `%A'\n" +msgstr "" + +#: elflink.c:9613 elflink.c:9620 +msgid "%B: duplicate section `%A' has different size\n" +msgstr "" + +#: elflink.c:9628 elflink.c:9633 +msgid "%B: warning: could not read contents of section `%A'\n" +msgstr "" + +#: elflink.c:9637 +msgid "%B: warning: duplicate section `%A' has different contents\n" +msgstr "" + +#: elfxx-mips.c:860 +msgid "static procedure (no name)" +msgstr "" + +#: elfxx-mips.c:2508 +msgid "not enough GOT space for local GOT entries" +msgstr "" + +#: elfxx-mips.c:4353 +msgid "%B: %A+0x%lx: jump to stub routine which is not jal" +msgstr "" + +#: elfxx-mips.c:5919 +msgid "%B: Malformed reloc detected for section %s" +msgstr "" + +#: elfxx-mips.c:5995 +msgid "%B: CALL16 reloc at 0x%lx not against global symbol" +msgstr "" + +#: elfxx-mips.c:9308 +#, c-format +msgid "%s: illegal section name `%s'" +msgstr "" + +#: elfxx-mips.c:9632 +msgid "%B: endianness incompatible with that of the selected emulation" +msgstr "" + +#: elfxx-mips.c:9644 +msgid "%B: ABI is incompatible with that of the selected emulation" +msgstr "" + +#: elfxx-mips.c:9716 +msgid "%B: warning: linking PIC files with non-PIC files" +msgstr "" + +#: elfxx-mips.c:9733 +msgid "%B: linking 32-bit code with 64-bit code" +msgstr "" + +#: elfxx-mips.c:9761 +msgid "%B: linking %s module with previous %s modules" +msgstr "" + +#: elfxx-mips.c:9784 +msgid "%B: ABI mismatch: linking %s module with previous %s modules" +msgstr "" + +#: elfxx-mips.c:9849 +#, c-format +msgid " [abi=O32]" +msgstr "" + +#: elfxx-mips.c:9851 +#, c-format +msgid " [abi=O64]" +msgstr "" + +#: elfxx-mips.c:9853 +#, c-format +msgid " [abi=EABI32]" +msgstr "" + +#: elfxx-mips.c:9855 +#, c-format +msgid " [abi=EABI64]" +msgstr "" + +#: elfxx-mips.c:9857 +#, c-format +msgid " [abi unknown]" +msgstr "" + +#: elfxx-mips.c:9859 +#, c-format +msgid " [abi=N32]" +msgstr "" + +#: elfxx-mips.c:9861 +#, c-format +msgid " [abi=64]" +msgstr "" + +#: elfxx-mips.c:9863 +#, c-format +msgid " [no abi set]" +msgstr "" + +#: elfxx-mips.c:9866 +#, c-format +msgid " [mips1]" +msgstr "" + +#: elfxx-mips.c:9868 +#, c-format +msgid " [mips2]" +msgstr "" + +#: elfxx-mips.c:9870 +#, c-format +msgid " [mips3]" +msgstr "" + +#: elfxx-mips.c:9872 +#, c-format +msgid " [mips4]" +msgstr "" + +#: elfxx-mips.c:9874 +#, c-format +msgid " [mips5]" +msgstr "" + +#: elfxx-mips.c:9876 +#, c-format +msgid " [mips32]" +msgstr "" + +#: elfxx-mips.c:9878 +#, c-format +msgid " [mips64]" +msgstr "" + +#: elfxx-mips.c:9880 +#, c-format +msgid " [mips32r2]" +msgstr "" + +#: elfxx-mips.c:9882 +#, c-format +msgid " [mips64r2]" +msgstr "" + +#: elfxx-mips.c:9884 +#, c-format +msgid " [unknown ISA]" +msgstr "" + +#: elfxx-mips.c:9887 +#, c-format +msgid " [mdmx]" +msgstr "" + +#: elfxx-mips.c:9890 +#, c-format +msgid " [mips16]" +msgstr "" + +#: elfxx-mips.c:9893 +#, c-format +msgid " [32bitmode]" +msgstr "" + +#: elfxx-mips.c:9895 +#, c-format +msgid " [not 32bitmode]" +msgstr "" + +#: i386linux.c:457 m68klinux.c:461 sparclinux.c:458 +#, c-format +msgid "Output file requires shared library `%s'\n" +msgstr "" + +#: i386linux.c:465 m68klinux.c:469 sparclinux.c:466 +#, c-format +msgid "Output file requires shared library `%s.so.%s'\n" +msgstr "" + +#: i386linux.c:654 i386linux.c:704 m68klinux.c:661 m68klinux.c:709 +#: sparclinux.c:656 sparclinux.c:706 +#, c-format +msgid "Symbol %s not defined for fixups\n" +msgstr "" + +#: i386linux.c:728 m68klinux.c:733 sparclinux.c:730 +msgid "Warning: fixup count mismatch\n" +msgstr "" + +#: ieee.c:293 +#, c-format +msgid "%s: string too long (%d chars, max 65535)" +msgstr "" + +#: ieee.c:428 +#, c-format +msgid "%s: unrecognized symbol `%s' flags 0x%x" +msgstr "" + +#: ieee.c:938 +msgid "%B: unimplemented ATI record %u for symbol %u" +msgstr "" + +#: ieee.c:962 +msgid "%B: unexpected ATN type %d in external part" +msgstr "" + +#: ieee.c:984 +msgid "%B: unexpected type after ATN" +msgstr "" + +#: ihex.c:264 +msgid "%B:%d: unexpected character `%s' in Intel Hex file" +msgstr "" + +#: ihex.c:372 +msgid "%B:%u: bad checksum in Intel Hex file (expected %u, found %u)" +msgstr "" + +#: ihex.c:426 +msgid "%B:%u: bad extended address record length in Intel Hex file" +msgstr "" + +#: ihex.c:443 +msgid "%B:%u: bad extended start address length in Intel Hex file" +msgstr "" + +#: ihex.c:460 +msgid "%B:%u: bad extended linear address record length in Intel Hex file" +msgstr "" + +#: ihex.c:477 +msgid "%B:%u: bad extended linear start address length in Intel Hex file" +msgstr "" + +#: ihex.c:494 +msgid "%B:%u: unrecognized ihex type %u in Intel Hex file" +msgstr "" + +#: ihex.c:619 +msgid "%B: internal error in ihex_read_section" +msgstr "" + +#: ihex.c:653 +msgid "%B: bad section length in ihex_read_section" +msgstr "" + +#: ihex.c:870 +#, c-format +msgid "%s: address 0x%s out of range for Intel Hex file" +msgstr "" + +#: libbfd.c:856 +#, c-format +msgid "Deprecated %s called at %s line %d in %s\n" +msgstr "" + +#: libbfd.c:859 +#, c-format +msgid "Deprecated %s called\n" +msgstr "" + +#: linker.c:1873 +msgid "%B: indirect symbol `%s' to `%s' is a loop" +msgstr "" + +#: linker.c:2741 +#, c-format +msgid "Attempt to do relocatable link with %s input and %s output" +msgstr "" + +#: linker.c:3038 +msgid "%B: warning: ignoring duplicate section `%A'\n" +msgstr "" + +#: linker.c:3052 +msgid "%B: warning: duplicate section `%A' has different size\n" +msgstr "" + +#: merge.c:796 +#, c-format +msgid "%s: access beyond end of merged section (%ld)" +msgstr "" + +#: mmo.c:456 +#, c-format +msgid "%s: No core to allocate section name %s\n" +msgstr "" + +#: mmo.c:531 +#, c-format +msgid "%s: No core to allocate a symbol %d bytes long\n" +msgstr "" + +#: mmo.c:1187 +#, c-format +msgid "%s: invalid mmo file: initialization value for $255 is not `Main'\n" +msgstr "" + +#: mmo.c:1332 +#, c-format +msgid "%s: unsupported wide character sequence 0x%02X 0x%02X after symbol name starting with `%s'\n" +msgstr "" + +#: mmo.c:1566 +#, c-format +msgid "%s: invalid mmo file: unsupported lopcode `%d'\n" +msgstr "" + +#: mmo.c:1576 +#, c-format +msgid "%s: invalid mmo file: expected YZ = 1 got YZ = %d for lop_quote\n" +msgstr "" + +#: mmo.c:1612 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_loc\n" +msgstr "" + +#: mmo.c:1658 +#, c-format +msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_fixo\n" +msgstr "" + +#: mmo.c:1697 +#, c-format +msgid "%s: invalid mmo file: expected y = 0, got y = %d for lop_fixrx\n" +msgstr "" + +#: mmo.c:1706 +#, c-format +msgid "%s: invalid mmo file: expected z = 16 or z = 24, got z = %d for lop_fixrx\n" +msgstr "" + +#: mmo.c:1729 +#, c-format +msgid "%s: invalid mmo file: leading byte of operand word must be 0 or 1, got %d for lop_fixrx\n" +msgstr "" + +#: mmo.c:1752 +#, c-format +msgid "%s: cannot allocate file name for file number %d, %d bytes\n" +msgstr "" + +#: mmo.c:1772 +#, c-format +msgid "%s: invalid mmo file: file number %d `%s', was already entered as `%s'\n" +msgstr "" + +#: mmo.c:1785 +#, c-format +msgid "%s: invalid mmo file: file name for number %d was not specified before use\n" +msgstr "" + +#: mmo.c:1891 +#, c-format +msgid "%s: invalid mmo file: fields y and z of lop_stab non-zero, y: %d, z: %d\n" +msgstr "" + +#: mmo.c:1927 +#, c-format +msgid "%s: invalid mmo file: lop_end not last item in file\n" +msgstr "" + +#: mmo.c:1940 +#, c-format +msgid "%s: invalid mmo file: YZ of lop_end (%ld) not equal to the number of tetras to the preceding lop_stab (%ld)\n" +msgstr "" + +#: mmo.c:2647 +#, c-format +msgid "%s: invalid symbol table: duplicate symbol `%s'\n" +msgstr "" + +#: mmo.c:2890 +#, c-format +msgid "%s: Bad symbol definition: `Main' set to %s rather than the start address %s\n" +msgstr "" + +#: mmo.c:2982 +#, c-format +msgid "%s: warning: symbol table too large for mmo, larger than 65535 32-bit words: %d. Only `Main' will be emitted.\n" +msgstr "" + +#: mmo.c:3027 +#, c-format +msgid "%s: internal error, symbol table changed size from %d to %d words\n" +msgstr "" + +#: mmo.c:3079 +#, c-format +msgid "%s: internal error, internal register section %s had contents\n" +msgstr "" + +#: mmo.c:3130 +#, c-format +msgid "%s: no initialized registers; section length 0\n" +msgstr "" + +#: mmo.c:3136 +#, c-format +msgid "%s: too many initialized registers; section length %ld\n" +msgstr "" + +#: mmo.c:3141 +#, c-format +msgid "%s: invalid start address for initialized registers of length %ld: 0x%lx%08lx\n" +msgstr "" + +#: oasys.c:1033 +#, c-format +msgid "%s: can not represent section `%s' in oasys" +msgstr "" + +#: osf-core.c:137 +#, c-format +msgid "Unhandled OSF/1 core file section type %d\n" +msgstr "" + +#. XXX code yet to be written. +#: peicode.h:760 +msgid "%B: Unhandled import type; %x" +msgstr "" + +#: peicode.h:765 +msgid "%B: Unrecognised import type; %x" +msgstr "" + +#: peicode.h:779 +msgid "%B: Unrecognised import name type; %x" +msgstr "" + +#: peicode.h:1169 +msgid "%B: Unrecognised machine type (0x%x) in Import Library Format archive" +msgstr "" + +#: peicode.h:1181 +msgid "%B: Recognised but unhandled machine type (0x%x) in Import Library Format archive" +msgstr "" + +#: peicode.h:1199 +msgid "%B: size field is zero in Import Library Format header" +msgstr "" + +#: peicode.h:1230 +msgid "%B: string not null terminated in ILF object file." +msgstr "" + +#: pe-mips.c:627 +msgid "%B: `ld -r' not supported with PE MIPS objects\n" +msgstr "" + +#. OK, at this point the following variables are set up: +#. src = VMA of the memory we're fixing up +#. mem = pointer to memory we're fixing up +#. val = VMA of what we need to refer to +#. +#: pe-mips.c:749 +msgid "%B: unimplemented %s\n" +msgstr "" + +#: pe-mips.c:775 +msgid "%B: jump too far away\n" +msgstr "" + +#: pe-mips.c:801 +msgid "%B: bad pair/reflo after refhi\n" +msgstr "" + +#: ppcboot.c:418 +#, c-format +msgid "" +"\n" +"ppcboot header:\n" +msgstr "" + +#: ppcboot.c:419 +#, c-format +msgid "Entry offset = 0x%.8lx (%ld)\n" +msgstr "" + +#: ppcboot.c:420 +#, c-format +msgid "Length = 0x%.8lx (%ld)\n" +msgstr "" + +#: ppcboot.c:423 +#, c-format +msgid "Flag field = 0x%.2x\n" +msgstr "" + +#: ppcboot.c:429 +#, c-format +msgid "Partition name = \"%s\"\n" +msgstr "" + +#: ppcboot.c:448 +#, c-format +msgid "" +"\n" +"Partition[%d] start = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "" + +#: ppcboot.c:454 +#, c-format +msgid "Partition[%d] end = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n" +msgstr "" + +#: ppcboot.c:460 +#, c-format +msgid "Partition[%d] sector = 0x%.8lx (%ld)\n" +msgstr "" + +#: ppcboot.c:461 +#, c-format +msgid "Partition[%d] length = 0x%.8lx (%ld)\n" +msgstr "" + +#: som.c:5269 +#, c-format +msgid "" +"\n" +"Exec Auxiliary Header\n" +msgstr "" + +#: som.c:5543 +msgid "som_sizeof_headers unimplemented" +msgstr "" + +#: srec.c:302 +msgid "%B:%d: Unexpected character `%s' in S-record file\n" +msgstr "" + +#: stabs.c:296 +msgid "%B(%A+0x%lx): Stabs entry has invalid string index." +msgstr "" + +#: syms.c:1048 +msgid "Unsupported .stab relocation" +msgstr "" + +#: vms-gsd.c:356 +#, c-format +msgid "bfd_make_section (%s) failed" +msgstr "" + +#: vms-gsd.c:371 +#, c-format +msgid "bfd_set_section_flags (%s, %x) failed" +msgstr "" + +#: vms-gsd.c:407 +#, c-format +msgid "Size mismatch section %s=%lx, %s=%lx" +msgstr "" + +#: vms-gsd.c:702 +#, c-format +msgid "unknown gsd/egsd subtype %d" +msgstr "" + +#: vms-hdr.c:409 +msgid "Object module NOT error-free !\n" +msgstr "" + +#: vms-misc.c:541 +#, c-format +msgid "Stack overflow (%d) in _bfd_vms_push" +msgstr "" + +#: vms-misc.c:559 +msgid "Stack underflow in _bfd_vms_pop" +msgstr "" + +#: vms-misc.c:912 +msgid "_bfd_vms_output_counted called with zero bytes" +msgstr "" + +#: vms-misc.c:917 +msgid "_bfd_vms_output_counted called with too many bytes" +msgstr "" + +#: vms-misc.c:1048 +#, c-format +msgid "Symbol %s replaced by %s\n" +msgstr "" + +#: vms-misc.c:1111 +#, c-format +msgid "failed to enter %s" +msgstr "" + +#: vms-tir.c:102 +msgid "No Mem !" +msgstr "" + +#: vms-tir.c:383 +#, c-format +msgid "bad section index in %s" +msgstr "" + +#: vms-tir.c:396 +#, c-format +msgid "unsupported STA cmd %s" +msgstr "" + +#: vms-tir.c:401 vms-tir.c:1247 +#, c-format +msgid "reserved STA cmd %d" +msgstr "" + +#: vms-tir.c:502 vms-tir.c:525 +#, c-format +msgid "%s: no symbol \"%s\"" +msgstr "" + +#. unsigned shift +#. rotate +#. Redefine symbol to current location. +#. Define a literal. +#: vms-tir.c:592 vms-tir.c:704 vms-tir.c:814 vms-tir.c:832 vms-tir.c:840 +#: vms-tir.c:849 vms-tir.c:1570 +#, c-format +msgid "%s: not supported" +msgstr "" + +#: vms-tir.c:597 vms-tir.c:1425 +#, c-format +msgid "%s: not implemented" +msgstr "" + +#: vms-tir.c:601 vms-tir.c:1429 +#, c-format +msgid "reserved STO cmd %d" +msgstr "" + +#: vms-tir.c:719 vms-tir.c:1575 +#, c-format +msgid "reserved OPR cmd %d" +msgstr "" + +#: vms-tir.c:787 vms-tir.c:1639 +#, c-format +msgid "reserved CTL cmd %d" +msgstr "" + +#. stack byte from image +#. arg: none. +#: vms-tir.c:1155 +msgid "stack-from-image not implemented" +msgstr "" + +#: vms-tir.c:1173 +msgid "stack-entry-mask not fully implemented" +msgstr "" + +#. compare procedure argument +#. arg: cs symbol name +#. by argument index +#. da argument descriptor +#. +#. compare argument descriptor with symbol argument (ARG$V_PASSMECH) +#. and stack TRUE (args match) or FALSE (args dont match) value. +#: vms-tir.c:1187 +msgid "PASSMECH not fully implemented" +msgstr "" + +#: vms-tir.c:1206 +msgid "stack-local-symbol not fully implemented" +msgstr "" + +#: vms-tir.c:1219 +msgid "stack-literal not fully implemented" +msgstr "" + +#: vms-tir.c:1240 +msgid "stack-local-symbol-entry-point-mask not fully implemented" +msgstr "" + +#: vms-tir.c:1517 vms-tir.c:1529 vms-tir.c:1541 vms-tir.c:1553 vms-tir.c:1618 +#: vms-tir.c:1626 vms-tir.c:1634 +#, c-format +msgid "%s: not fully implemented" +msgstr "" + +#: vms-tir.c:1691 +#, c-format +msgid "obj code %d not found" +msgstr "" + +#: vms-tir.c:2029 +#, c-format +msgid "SEC_RELOC with no relocs in section %s" +msgstr "" + +#: vms-tir.c:2304 +#, c-format +msgid "Unhandled relocation %s" +msgstr "" + +#: xcofflink.c:1243 +msgid "%B: `%s' has line numbers but no enclosing section" +msgstr "" + +#: xcofflink.c:1296 +msgid "%B: class %d symbol `%s' has no aux entries" +msgstr "" + +#: xcofflink.c:1319 +msgid "%B: symbol `%s' has unrecognized csect type %d" +msgstr "" + +#: xcofflink.c:1331 +msgid "%B: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d" +msgstr "" + +#: xcofflink.c:1367 +msgid "%B: XMC_TC0 symbol `%s' is class %d scnlen %d" +msgstr "" + +#: xcofflink.c:1518 +msgid "%B: csect `%s' not in enclosing section" +msgstr "" + +#: xcofflink.c:1625 +msgid "%B: misplaced XTY_LD `%s'" +msgstr "" + +#: xcofflink.c:1956 +msgid "%B: reloc %s:%d not in csect" +msgstr "" + +#: xcofflink.c:2093 +#, c-format +msgid "%s: XCOFF shared object when not producing XCOFF output" +msgstr "" + +#: xcofflink.c:2114 +#, c-format +msgid "%s: dynamic object with no .loader section" +msgstr "" + +#: xcofflink.c:2759 +#, c-format +msgid "%s: no such symbol" +msgstr "" + +#: xcofflink.c:2892 +msgid "error: undefined symbol __rtinit" +msgstr "" + +#: xcofflink.c:3449 +#, c-format +msgid "warning: attempt to export undefined symbol `%s'" +msgstr "" + +#: xcofflink.c:4444 +#, c-format +msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling" +msgstr "" + +#: xcofflink.c:5285 +msgid "%B: loader reloc in unrecognized section `%A'" +msgstr "" + +#: xcofflink.c:5306 +msgid "%B: `%s' in loader reloc but not loader sym" +msgstr "" + +#: xcofflink.c:5321 +msgid "%B: loader reloc in read-only section %A" +msgstr "" + +#: xcofflink.c:5747 xcofflink.c:5809 xcofflink.c:6111 +#, c-format +msgid "%s: loader reloc in unrecognized section `%s'" +msgstr "" + +#: xcofflink.c:6122 +#, c-format +msgid "%s: `%s' in loader reloc but not loader sym" +msgstr "" + +#: elf32-ia64.c:987 elf64-ia64.c:987 +msgid "%B: Can't relax br at 0x%lx in section `%A'. Please use brl or indirect branch." +msgstr "" + +#: elf32-ia64.c:2339 elf64-ia64.c:2339 +msgid "@pltoff reloc against local symbol" +msgstr "" + +#: elf32-ia64.c:3757 elf64-ia64.c:3757 +#, c-format +msgid "%s: short data segment overflowed (0x%lx >= 0x400000)" +msgstr "" + +#: elf32-ia64.c:3768 elf64-ia64.c:3768 +#, c-format +msgid "%s: __gp does not cover short data segment" +msgstr "" + +#: elf32-ia64.c:4015 elf64-ia64.c:4015 +msgid "%B: non-pic code with imm relocation against dynamic symbol `%s'" +msgstr "" + +#: elf32-ia64.c:4080 elf64-ia64.c:4080 +msgid "%B: @gprel relocation against dynamic symbol %s" +msgstr "" + +#: elf32-ia64.c:4140 elf64-ia64.c:4140 +msgid "%B: linking non-pic code in a position independent executable" +msgstr "" + +#: elf32-ia64.c:4277 elf64-ia64.c:4277 +msgid "%B: @internal branch to dynamic symbol %s" +msgstr "" + +#: elf32-ia64.c:4279 elf64-ia64.c:4279 +msgid "%B: speculation fixup to dynamic symbol %s" +msgstr "" + +#: elf32-ia64.c:4281 elf64-ia64.c:4281 +msgid "%B: @pcrel relocation against dynamic symbol %s" +msgstr "" + +#: elf32-ia64.c:4488 elf64-ia64.c:4488 +msgid "unsupported reloc" +msgstr "" + +#: elf32-ia64.c:4528 elf64-ia64.c:4528 +msgid "%B: Can't relax br (%s) to `%s' at 0x%lx in section `%A' with size 0x%lx (> 0x1000000)." +msgstr "" + +#: elf32-ia64.c:4789 elf64-ia64.c:4789 +msgid "%B: linking trap-on-NULL-dereference with non-trapping files" +msgstr "" + +#: elf32-ia64.c:4798 elf64-ia64.c:4798 +msgid "%B: linking big-endian files with little-endian files" +msgstr "" + +#: elf32-ia64.c:4807 elf64-ia64.c:4807 +msgid "%B: linking 64-bit files with 32-bit files" +msgstr "" + +#: elf32-ia64.c:4816 elf64-ia64.c:4816 +msgid "%B: linking constant-gp files with non-constant-gp files" +msgstr "" + +#: elf32-ia64.c:4826 elf64-ia64.c:4826 +msgid "%B: linking auto-pic files with non-auto-pic files" +msgstr "" + +#: peigen.c:1014 pepigen.c:1014 +#, c-format +msgid "%s: line number overflow: 0x%lx > 0xffff" +msgstr "" + +#: peigen.c:1041 pepigen.c:1041 +msgid "Export Directory [.edata (or where ever we found it)]" +msgstr "" + +#: peigen.c:1042 pepigen.c:1042 +msgid "Import Directory [parts of .idata]" +msgstr "" + +#: peigen.c:1043 pepigen.c:1043 +msgid "Resource Directory [.rsrc]" +msgstr "" + +#: peigen.c:1044 pepigen.c:1044 +msgid "Exception Directory [.pdata]" +msgstr "" + +#: peigen.c:1045 pepigen.c:1045 +msgid "Security Directory" +msgstr "" + +#: peigen.c:1046 pepigen.c:1046 +msgid "Base Relocation Directory [.reloc]" +msgstr "" + +#: peigen.c:1047 pepigen.c:1047 +msgid "Debug Directory" +msgstr "" + +#: peigen.c:1048 pepigen.c:1048 +msgid "Description Directory" +msgstr "" + +#: peigen.c:1049 pepigen.c:1049 +msgid "Special Directory" +msgstr "" + +#: peigen.c:1050 pepigen.c:1050 +msgid "Thread Storage Directory [.tls]" +msgstr "" + +#: peigen.c:1051 pepigen.c:1051 +msgid "Load Configuration Directory" +msgstr "" + +#: peigen.c:1052 pepigen.c:1052 +msgid "Bound Import Directory" +msgstr "" + +#: peigen.c:1053 pepigen.c:1053 +msgid "Import Address Table Directory" +msgstr "" + +#: peigen.c:1054 pepigen.c:1054 +msgid "Delay Import Directory" +msgstr "" + +#: peigen.c:1055 peigen.c:1056 pepigen.c:1055 pepigen.c:1056 +msgid "Reserved" +msgstr "" + +#: peigen.c:1118 pepigen.c:1118 +#, c-format +msgid "" +"\n" +"There is an import table, but the section containing it could not be found\n" +msgstr "" + +#: peigen.c:1123 pepigen.c:1123 +#, c-format +msgid "" +"\n" +"There is an import table in %s at 0x%lx\n" +msgstr "" + +#: peigen.c:1159 pepigen.c:1159 +#, c-format +msgid "" +"\n" +"Function descriptor located at the start address: %04lx\n" +msgstr "" + +#: peigen.c:1162 pepigen.c:1162 +#, c-format +msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n" +msgstr "" + +#: peigen.c:1170 pepigen.c:1170 +#, c-format +msgid "" +"\n" +"No reldata section! Function descriptor not decoded.\n" +msgstr "" + +#: peigen.c:1175 pepigen.c:1175 +#, c-format +msgid "" +"\n" +"The Import Tables (interpreted %s section contents)\n" +msgstr "" + +#: peigen.c:1178 pepigen.c:1178 +#, c-format +msgid "" +" vma: Hint Time Forward DLL First\n" +" Table Stamp Chain Name Thunk\n" +msgstr "" + +#: peigen.c:1223 pepigen.c:1223 +#, c-format +msgid "" +"\n" +"\tDLL Name: %s\n" +msgstr "" + +#: peigen.c:1234 pepigen.c:1234 +#, c-format +msgid "\tvma: Hint/Ord Member-Name Bound-To\n" +msgstr "" + +#: peigen.c:1259 pepigen.c:1259 +#, c-format +msgid "" +"\n" +"There is a first thunk, but the section containing it could not be found\n" +msgstr "" + +#: peigen.c:1399 pepigen.c:1399 +#, c-format +msgid "" +"\n" +"There is an export table, but the section containing it could not be found\n" +msgstr "" + +#: peigen.c:1404 pepigen.c:1404 +#, c-format +msgid "" +"\n" +"There is an export table in %s at 0x%lx\n" +msgstr "" + +#: peigen.c:1435 pepigen.c:1435 +#, c-format +msgid "" +"\n" +"The Export Tables (interpreted %s section contents)\n" +"\n" +msgstr "" + +#: peigen.c:1439 pepigen.c:1439 +#, c-format +msgid "Export Flags \t\t\t%lx\n" +msgstr "" + +#: peigen.c:1442 pepigen.c:1442 +#, c-format +msgid "Time/Date stamp \t\t%lx\n" +msgstr "" + +#: peigen.c:1445 pepigen.c:1445 +#, c-format +msgid "Major/Minor \t\t\t%d/%d\n" +msgstr "" + +#: peigen.c:1448 pepigen.c:1448 +#, c-format +msgid "Name \t\t\t\t" +msgstr "" + +#: peigen.c:1454 pepigen.c:1454 +#, c-format +msgid "Ordinal Base \t\t\t%ld\n" +msgstr "" + +#: peigen.c:1457 pepigen.c:1457 +#, c-format +msgid "Number in:\n" +msgstr "" + +#: peigen.c:1460 pepigen.c:1460 +#, c-format +msgid "\tExport Address Table \t\t%08lx\n" +msgstr "" + +#: peigen.c:1464 pepigen.c:1464 +#, c-format +msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n" +msgstr "" + +#: peigen.c:1467 pepigen.c:1467 +#, c-format +msgid "Table Addresses\n" +msgstr "" + +#: peigen.c:1470 pepigen.c:1470 +#, c-format +msgid "\tExport Address Table \t\t" +msgstr "" + +#: peigen.c:1475 pepigen.c:1475 +#, c-format +msgid "\tName Pointer Table \t\t" +msgstr "" + +#: peigen.c:1480 pepigen.c:1480 +#, c-format +msgid "\tOrdinal Table \t\t\t" +msgstr "" + +#: peigen.c:1495 pepigen.c:1495 +#, c-format +msgid "" +"\n" +"Export Address Table -- Ordinal Base %ld\n" +msgstr "" + +#: peigen.c:1514 pepigen.c:1514 +msgid "Forwarder RVA" +msgstr "" + +#: peigen.c:1525 pepigen.c:1525 +msgid "Export RVA" +msgstr "" + +#: peigen.c:1532 pepigen.c:1532 +#, c-format +msgid "" +"\n" +"[Ordinal/Name Pointer] Table\n" +msgstr "" + +#: peigen.c:1587 pepigen.c:1587 +#, c-format +msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n" +msgstr "" + +#: peigen.c:1591 pepigen.c:1591 +#, c-format +msgid "" +"\n" +"The Function Table (interpreted .pdata section contents)\n" +msgstr "" + +#: peigen.c:1594 pepigen.c:1594 +#, c-format +msgid " vma:\t\t\tBegin Address End Address Unwind Info\n" +msgstr "" + +#: peigen.c:1596 pepigen.c:1596 +#, c-format +msgid "" +" vma:\t\tBegin End EH EH PrologEnd Exception\n" +" \t\tAddress Address Handler Data Address Mask\n" +msgstr "" + +#: peigen.c:1666 pepigen.c:1666 +#, c-format +msgid " Register save millicode" +msgstr "" + +#: peigen.c:1669 pepigen.c:1669 +#, c-format +msgid " Register restore millicode" +msgstr "" + +#: peigen.c:1672 pepigen.c:1672 +#, c-format +msgid " Glue code sequence" +msgstr "" + +#: peigen.c:1724 pepigen.c:1724 +#, c-format +msgid "" +"\n" +"\n" +"PE File Base Relocations (interpreted .reloc section contents)\n" +msgstr "" + +#: peigen.c:1754 pepigen.c:1754 +#, c-format +msgid "" +"\n" +"Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n" +msgstr "" + +#: peigen.c:1767 pepigen.c:1767 +#, c-format +msgid "\treloc %4d offset %4x [%4lx] %s" +msgstr "" + +#. The MS dumpbin program reportedly ands with 0xff0f before +#. printing the characteristics field. Not sure why. No reason to +#. emulate it here. +#: peigen.c:1807 pepigen.c:1807 +#, c-format +msgid "" +"\n" +"Characteristics 0x%x\n" +msgstr "" diff -uprN binutils-2.16.91.0.1/bfd/reloc.c binutils-2.16.91.0.2/bfd/reloc.c --- binutils-2.16.91.0.1/bfd/reloc.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/reloc.c 2005-07-20 12:27:27.439168972 -0700 @@ -3069,6 +3069,43 @@ ENUMDOC DLX relocs ENUM + BFD_RELOC_M16C_8_PCREL8 +ENUMX + BFD_RELOC_M16C_16_PCREL8 +ENUMX + BFD_RELOC_M16C_8_PCREL16 +ENUMX + BFD_RELOC_M16C_8_ELABEL24 +ENUMX + BFD_RELOC_M16C_8_ABS16 +ENUMX + BFD_RELOC_M16C_16_ABS16 +ENUMX + BFD_RELOC_M16C_16_ABS24 +ENUMX + BFD_RELOC_M16C_16_ABS32 +ENUMX + BFD_RELOC_M16C_24_ABS16 +ENUMX + BFD_RELOC_M16C_24_ABS24 +ENUMX + BFD_RELOC_M16C_24_ABS32 +ENUMX + BFD_RELOC_M16C_32_ABS16 +ENUMX + BFD_RELOC_M16C_32_ABS24 +ENUMX + BFD_RELOC_M16C_32_ABS32 +ENUMX + BFD_RELOC_M16C_40_ABS16 +ENUMX + BFD_RELOC_M16C_40_ABS24 +ENUMX + BFD_RELOC_M16C_40_ABS32 +ENUMDOC + Renesas M16C/M32C Relocations. + +ENUM BFD_RELOC_M32R_24 ENUMDOC Renesas M32R (formerly Mitsubishi M32R) relocs. @@ -4044,7 +4081,7 @@ ENUMX ENUMDOC NS CR16C Relocations. -ENUM +ENUM BFD_RELOC_CRX_REL4 ENUMX BFD_RELOC_CRX_REL8 @@ -4257,6 +4294,27 @@ ENUMDOC Relocations used by VAX ELF. ENUM + BFD_RELOC_MS1_PC16 +ENUMDOC + Morpho MS1 - 16 bit immediate relocation. +ENUM + BFD_RELOC_MS1_HI16 +ENUMDOC + Morpho MS1 - Hi 16 bits of an address. +ENUM + BFD_RELOC_MS1_LO16 +ENUMDOC + Morpho MS1 - Low 16 bits of an address. +ENUM + BFD_RELOC_MS1_GNU_VTINHERIT +ENUMDOC + Morpho MS1 - Used to tell the linker which vtable entries are used. +ENUM + BFD_RELOC_MS1_GNU_VTENTRY +ENUMDOC + Morpho MS1 - Used to tell the linker which vtable entries are used. + +ENUM BFD_RELOC_MSP430_10_PCREL ENUMX BFD_RELOC_MSP430_16_PCREL @@ -4520,27 +4578,6 @@ bfd_generic_relax_section (bfd *abfd ATT return TRUE; } -/* Mark sections containing global symbols. This is called through - bfd_link_hash_traverse. */ - -static bfd_boolean -bfd_mark_used_section (struct bfd_link_hash_entry *h, - void *data ATTRIBUTE_UNUSED) -{ - if (h->type == bfd_link_hash_warning) - h = h->u.i.link; - - if (h->type == bfd_link_hash_defined - || h->type == bfd_link_hash_defweak) - { - asection *s = h->u.def.section; - if (s != NULL && s->output_section != NULL) - s->output_section->flags |= SEC_KEEP; - } - - return TRUE; -} - /* INTERNAL_FUNCTION bfd_generic_gc_sections @@ -4551,18 +4588,13 @@ SYNOPSIS DESCRIPTION Provides default handling for relaxing for back ends which - don't do section gc -- i.e., does nothing besides the special - case for marking sections having global symbols. + don't do section gc -- i.e., does nothing. */ bfd_boolean bfd_generic_gc_sections (bfd *abfd ATTRIBUTE_UNUSED, - struct bfd_link_info *info) + struct bfd_link_info *info ATTRIBUTE_UNUSED) { - /* If called when info->gc_sections is 0, then mark all sections - containing global symbols with SEC_KEEP. */ - if (!info->gc_sections && !info->relocatable) - bfd_link_hash_traverse (info->hash, bfd_mark_used_section, NULL); return TRUE; } diff -uprN binutils-2.16.91.0.1/bfd/section.c binutils-2.16.91.0.2/bfd/section.c --- binutils-2.16.91.0.1/bfd/section.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/section.c 2005-07-20 12:27:27.441168642 -0700 @@ -354,8 +354,9 @@ CODE_FRAGMENT . output sections that have an input section. *} . unsigned int linker_has_input : 1; . -. {* A mark flag used by some linker backends for garbage collection. *} +. {* Mark flags used by some linker backends for garbage collection. *} . unsigned int gc_mark : 1; +. unsigned int gc_mark_from_eh : 1; . . {* The following flags are used by the ELF linker. *} . @@ -661,18 +662,18 @@ static const asymbol global_syms[] = #define STD_SECTION(SEC, FLAGS, SYM, NAME, IDX) \ const asymbol * const SYM = (asymbol *) &global_syms[IDX]; \ - asection SEC = \ + asection SEC = \ /* name, id, index, next, prev, flags, user_set_vma, */ \ { NAME, IDX, 0, NULL, NULL, FLAGS, 0, \ \ - /* linker_mark, linker_has_input, gc_mark, segment_mark, */ \ + /* linker_mark, linker_has_input, gc_mark, gc_mark_from_eh, */ \ 0, 0, 1, 0, \ \ - /* sec_info_type, use_rela_p, has_tls_reloc, has_gp_reloc, */ \ - 0, 0, 0, 0, \ + /* segment_mark, sec_info_type, use_rela_p, has_tls_reloc, */ \ + 0, 0, 0, 0, \ \ - /* need_finalize_relax, reloc_done, */ \ - 0, 0, \ + /* has_gp_reloc, need_finalize_relax, reloc_done, */ \ + 0, 0, 0, \ \ /* vma, lma, size, rawsize */ \ 0, 0, 0, 0, \ @@ -686,8 +687,8 @@ static const asymbol global_syms[] = /* line_filepos, userdata, contents, lineno, lineno_count, */ \ 0, NULL, NULL, NULL, 0, \ \ - /* entsize, kept_section, moving_line_filepos, */ \ - 0, NULL, 0, \ + /* entsize, kept_section, moving_line_filepos, */ \ + 0, NULL, 0, \ \ /* target_index, used_by_bfd, constructor_chain, owner, */ \ 0, NULL, NULL, NULL, \ diff -uprN binutils-2.16.91.0.1/bfd/targets.c binutils-2.16.91.0.2/bfd/targets.c --- binutils-2.16.91.0.1/bfd/targets.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/targets.c 2005-07-20 12:27:27.444168147 -0700 @@ -583,6 +583,7 @@ extern const bfd_target bfd_elf32_little extern const bfd_target bfd_elf32_littlearm_symbian_vec; extern const bfd_target bfd_elf32_littlearm_vxworks_vec; extern const bfd_target bfd_elf32_littlemips_vec; +extern const bfd_target bfd_elf32_m32c_vec; extern const bfd_target bfd_elf32_m32r_vec; extern const bfd_target bfd_elf32_m32rle_vec; extern const bfd_target bfd_elf32_m32rlin_vec; @@ -595,6 +596,7 @@ extern const bfd_target bfd_elf32_mcore_ extern const bfd_target bfd_elf32_mcore_little_vec; extern const bfd_target bfd_elf32_mn10200_vec; extern const bfd_target bfd_elf32_mn10300_vec; +extern const bfd_target bfd_elf32_ms1_vec; extern const bfd_target bfd_elf32_msp430_vec; extern const bfd_target bfd_elf32_nbigmips_vec; extern const bfd_target bfd_elf32_nlittlemips_vec; @@ -606,6 +608,7 @@ extern const bfd_target bfd_elf32_pj_vec extern const bfd_target bfd_elf32_pjl_vec; extern const bfd_target bfd_elf32_powerpc_vec; extern const bfd_target bfd_elf32_powerpcle_vec; +extern const bfd_target bfd_elf32_powerpc_vxworks_vec; extern const bfd_target bfd_elf32_s390_vec; extern const bfd_target bfd_elf32_sh64_vec; extern const bfd_target bfd_elf32_sh64l_vec; @@ -790,7 +793,6 @@ extern const bfd_target sco5_core_vec; extern const bfd_target trad_core_vec; extern const bfd_target bfd_elf32_am33lin_vec; -extern const bfd_target bfd_elf32_ms1_vec; static const bfd_target * const _bfd_target_vector[] = { #ifdef SELECT_VECS @@ -888,6 +890,7 @@ static const bfd_target * const _bfd_tar &bfd_elf32_littlearm_symbian_vec, &bfd_elf32_littlearm_vxworks_vec, &bfd_elf32_littlemips_vec, + &bfd_elf32_m32c_vec, &bfd_elf32_m32r_vec, &bfd_elf32_m32rle_vec, &bfd_elf32_m32rlin_vec, @@ -900,6 +903,7 @@ static const bfd_target * const _bfd_tar &bfd_elf32_mcore_little_vec, &bfd_elf32_mn10200_vec, &bfd_elf32_mn10300_vec, + &bfd_elf32_ms1_vec, &bfd_elf32_msp430_vec, #ifdef BFD64 &bfd_elf32_nbigmips_vec, @@ -912,6 +916,7 @@ static const bfd_target * const _bfd_tar &bfd_elf32_pj_vec, &bfd_elf32_pjl_vec, &bfd_elf32_powerpc_vec, + &bfd_elf32_powerpc_vxworks_vec, &bfd_elf32_powerpcle_vec, &bfd_elf32_s390_vec, &bfd_elf32_sh_vec, @@ -1121,7 +1126,6 @@ static const bfd_target * const _bfd_tar &we32kcoff_vec, &z8kcoff_vec, &bfd_elf32_am33lin_vec, - &bfd_elf32_ms1_vec, #endif /* not SELECT_VECS */ /* Always support S-records, for convenience. */ diff -uprN binutils-2.16.91.0.1/bfd/version.h binutils-2.16.91.0.2/bfd/version.h --- binutils-2.16.91.0.1/bfd/version.h 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/version.h 2005-07-20 12:27:27.444168147 -0700 @@ -1,3 +1,3 @@ -#define BFD_VERSION_DATE 20050622 +#define BFD_VERSION_DATE 20050720 #define BFD_VERSION @bfd_version@ #define BFD_VERSION_STRING @bfd_version_string@ diff -uprN binutils-2.16.91.0.1/bfd/vms.h binutils-2.16.91.0.2/bfd/vms.h --- binutils-2.16.91.0.1/bfd/vms.h 2005-05-10 15:46:43.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/vms.h 2005-07-20 12:27:27.449167323 -0700 @@ -620,8 +620,8 @@ struct vms_private_data_struct #define SECTION_NAME_TEMPLATE "__SEC__%d" #if VMS_DEBUG -extern void _bfd_vms_debug (int, char *, ..); -extern void _bfd_hexdump (int, unsignedchar *, int, int); +extern void _bfd_vms_debug (int, char *, ...) ATTRIBUTE_PRINTF_2; +extern void _bfd_hexdump (int, unsigned char *, int, int); #define vms_debug _bfd_vms_debug #endif diff -uprN binutils-2.16.91.0.1/bfd/xtensa-modules.c binutils-2.16.91.0.2/bfd/xtensa-modules.c --- binutils-2.16.91.0.1/bfd/xtensa-modules.c 2005-05-10 15:46:43.000000000 -0700 +++ binutils-2.16.91.0.2/bfd/xtensa-modules.c 2005-07-20 12:27:27.469164026 -0700 @@ -29,6 +29,7 @@ static xtensa_sysreg_internal sysregs[] { "LBEG", 0, 0 }, { "LEND", 1, 0 }, { "LCOUNT", 2, 0 }, + { "PTEVADDR", 83, 0 }, { "DDR", 104, 0 }, { "176", 176, 0 }, { "208", 208, 0 }, @@ -70,10 +71,13 @@ static xtensa_sysreg_internal sysregs[] { "IBREAKA1", 129, 0 }, { "IBREAKENABLE", 96, 0 }, { "ICOUNTLEVEL", 237, 0 }, - { "DEBUGCAUSE", 233, 0 } + { "DEBUGCAUSE", 233, 0 }, + { "RASID", 90, 0 }, + { "ITLBCFG", 91, 0 }, + { "DTLBCFG", 92, 0 } }; -#define NUM_SYSREGS 45 +#define NUM_SYSREGS 49 #define MAX_SPECIAL_REG 245 #define MAX_USER_REG 0 @@ -96,13 +100,14 @@ static xtensa_state_internal states[] = { "EXCSAVE2", 32, 0 }, { "EXCSAVE3", 32, 0 }, { "EXCSAVE4", 32, 0 }, - { "EPS2", 13, 0 }, - { "EPS3", 13, 0 }, - { "EPS4", 13, 0 }, + { "EPS2", 15, 0 }, + { "EPS3", 15, 0 }, + { "EPS4", 15, 0 }, { "EXCCAUSE", 6, 0 }, { "PSINTLEVEL", 4, 0 }, { "PSUM", 1, 0 }, { "PSWOE", 1, 0 }, + { "PSRING", 2, 0 }, { "PSEXCM", 1, 0 }, { "DEPC", 32, 0 }, { "EXCVADDR", 32, 0 }, @@ -131,10 +136,16 @@ static xtensa_state_internal states[] = { "DBNUM", 4, 0 }, { "CCOMPARE0", 32, 0 }, { "CCOMPARE1", 32, 0 }, - { "CCOMPARE2", 32, 0 } + { "CCOMPARE2", 32, 0 }, + { "ASID3", 8, 0 }, + { "ASID2", 8, 0 }, + { "ASID1", 8, 0 }, + { "INSTPGSZID4", 2, 0 }, + { "DATAPGSZID4", 2, 0 }, + { "PTBASE", 10, 0 } }; -#define NUM_STATES 51 +#define NUM_STATES 58 /* Macros for xtensa_state numbers (for use in iclasses because the state numbers are not available when the iclass table is generated). */ @@ -161,35 +172,42 @@ static xtensa_state_internal states[] = #define STATE_PSINTLEVEL 19 #define STATE_PSUM 20 #define STATE_PSWOE 21 -#define STATE_PSEXCM 22 -#define STATE_DEPC 23 -#define STATE_EXCVADDR 24 -#define STATE_WindowBase 25 -#define STATE_WindowStart 26 -#define STATE_PSCALLINC 27 -#define STATE_PSOWB 28 -#define STATE_LBEG 29 -#define STATE_LEND 30 -#define STATE_SAR 31 -#define STATE_LITBADDR 32 -#define STATE_LITBEN 33 -#define STATE_MISC0 34 -#define STATE_MISC1 35 -#define STATE_InOCDMode 36 -#define STATE_INTENABLE 37 -#define STATE_DBREAKA0 38 -#define STATE_DBREAKC0 39 -#define STATE_DBREAKA1 40 -#define STATE_DBREAKC1 41 -#define STATE_IBREAKA0 42 -#define STATE_IBREAKA1 43 -#define STATE_IBREAKENABLE 44 -#define STATE_ICOUNTLEVEL 45 -#define STATE_DEBUGCAUSE 46 -#define STATE_DBNUM 47 -#define STATE_CCOMPARE0 48 -#define STATE_CCOMPARE1 49 -#define STATE_CCOMPARE2 50 +#define STATE_PSRING 22 +#define STATE_PSEXCM 23 +#define STATE_DEPC 24 +#define STATE_EXCVADDR 25 +#define STATE_WindowBase 26 +#define STATE_WindowStart 27 +#define STATE_PSCALLINC 28 +#define STATE_PSOWB 29 +#define STATE_LBEG 30 +#define STATE_LEND 31 +#define STATE_SAR 32 +#define STATE_LITBADDR 33 +#define STATE_LITBEN 34 +#define STATE_MISC0 35 +#define STATE_MISC1 36 +#define STATE_InOCDMode 37 +#define STATE_INTENABLE 38 +#define STATE_DBREAKA0 39 +#define STATE_DBREAKC0 40 +#define STATE_DBREAKA1 41 +#define STATE_DBREAKC1 42 +#define STATE_IBREAKA0 43 +#define STATE_IBREAKA1 44 +#define STATE_IBREAKENABLE 45 +#define STATE_ICOUNTLEVEL 46 +#define STATE_DEBUGCAUSE 47 +#define STATE_DBNUM 48 +#define STATE_CCOMPARE0 49 +#define STATE_CCOMPARE1 50 +#define STATE_CCOMPARE2 51 +#define STATE_ASID3 52 +#define STATE_ASID2 53 +#define STATE_ASID1 54 +#define STATE_INSTPGSZID4 55 +#define STATE_DATAPGSZID4 56 +#define STATE_PTBASE 57 /* Field definitions. */ @@ -2244,11 +2262,14 @@ static xtensa_operand_internal operands[ /* Iclass table. */ static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { - { { STATE_PSEXCM }, 'o' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PSEXCM }, 'm' }, { { STATE_EPC1 }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_DEPC }, 'i' } }; @@ -2335,6 +2356,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_WindowBase }, 'm' } }; @@ -2351,7 +2374,8 @@ static xtensa_arg_internal Iclass_xt_icl static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { { { STATE_EPC1 }, 'i' }, - { { STATE_PSEXCM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, + { { STATE_PSRING }, 'i' }, { { STATE_WindowBase }, 'm' }, { { STATE_WindowStart }, 'm' }, { { STATE_PSOWB }, 'i' } @@ -2363,17 +2387,29 @@ static xtensa_arg_internal Iclass_xt_icl { { 12 /* immrx4 */ }, 'i' } }; +static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { { { 6 /* art */ }, 'i' }, { { 4 /* ars */ }, 'i' }, { { 12 /* immrx4 */ }, 'i' } }; +static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { { { 6 /* art */ }, 'o' } }; static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_WindowBase }, 'i' } }; @@ -2382,6 +2418,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_WindowBase }, 'o' } }; @@ -2390,6 +2428,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_WindowBase }, 'm' } }; @@ -2398,6 +2438,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_WindowStart }, 'i' } }; @@ -2406,6 +2448,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_WindowStart }, 'o' } }; @@ -2414,6 +2458,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_WindowStart }, 'm' } }; @@ -2707,6 +2753,7 @@ static xtensa_arg_internal Iclass_xt_icl { { STATE_PSWOE }, 'i' }, { { STATE_PSCALLINC }, 'i' }, { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_PSUM }, 'i' }, { { STATE_PSEXCM }, 'i' }, { { STATE_PSINTLEVEL }, 'm' } @@ -2842,10 +2889,20 @@ static xtensa_arg_internal Iclass_xt_icl { { 6 /* art */ }, 'o' } }; +static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = { { { 6 /* art */ }, 'o' } }; +static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { { { 6 /* art */ }, 'o' } }; @@ -2854,6 +2911,7 @@ static xtensa_arg_internal Iclass_xt_icl { { STATE_PSWOE }, 'i' }, { { STATE_PSCALLINC }, 'i' }, { { STATE_PSOWB }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_PSUM }, 'i' }, { { STATE_PSEXCM }, 'i' }, { { STATE_PSINTLEVEL }, 'i' } @@ -2867,8 +2925,9 @@ static xtensa_arg_internal Iclass_xt_icl { { STATE_PSWOE }, 'o' }, { { STATE_PSCALLINC }, 'o' }, { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, { { STATE_PSINTLEVEL }, 'o' } }; @@ -2880,6 +2939,7 @@ static xtensa_arg_internal Iclass_xt_icl { { STATE_PSWOE }, 'm' }, { { STATE_PSCALLINC }, 'm' }, { { STATE_PSOWB }, 'm' }, + { { STATE_PSRING }, 'm' }, { { STATE_PSUM }, 'm' }, { { STATE_PSEXCM }, 'm' }, { { STATE_PSINTLEVEL }, 'm' } @@ -2890,6 +2950,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPC1 }, 'i' } }; @@ -2898,6 +2960,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPC1 }, 'o' } }; @@ -2906,6 +2970,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPC1 }, 'm' } }; @@ -2914,6 +2980,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE1 }, 'i' } }; @@ -2922,6 +2990,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE1 }, 'o' } }; @@ -2930,6 +3000,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE1 }, 'm' } }; @@ -2938,6 +3010,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPC2 }, 'i' } }; @@ -2946,6 +3020,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPC2 }, 'o' } }; @@ -2954,6 +3030,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPC2 }, 'm' } }; @@ -2962,6 +3040,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE2 }, 'i' } }; @@ -2970,6 +3050,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE2 }, 'o' } }; @@ -2978,6 +3060,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE2 }, 'm' } }; @@ -2986,6 +3070,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPC3 }, 'i' } }; @@ -2994,6 +3080,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPC3 }, 'o' } }; @@ -3002,6 +3090,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPC3 }, 'm' } }; @@ -3010,6 +3100,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE3 }, 'i' } }; @@ -3018,6 +3110,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE3 }, 'o' } }; @@ -3026,6 +3120,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE3 }, 'm' } }; @@ -3034,6 +3130,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPC4 }, 'i' } }; @@ -3042,6 +3140,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPC4 }, 'o' } }; @@ -3050,6 +3150,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPC4 }, 'm' } }; @@ -3058,6 +3160,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE4 }, 'i' } }; @@ -3066,6 +3170,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE4 }, 'o' } }; @@ -3074,6 +3180,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EXCSAVE4 }, 'm' } }; @@ -3082,6 +3190,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPS2 }, 'i' } }; @@ -3090,6 +3200,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPS2 }, 'o' } }; @@ -3098,6 +3210,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPS2 }, 'm' } }; @@ -3106,6 +3220,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPS3 }, 'i' } }; @@ -3114,6 +3230,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPS3 }, 'o' } }; @@ -3122,6 +3240,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPS3 }, 'm' } }; @@ -3130,6 +3250,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPS4 }, 'i' } }; @@ -3138,6 +3260,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPS4 }, 'o' } }; @@ -3146,6 +3270,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EPS4 }, 'm' } }; @@ -3154,6 +3280,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EXCVADDR }, 'i' } }; @@ -3162,6 +3290,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EXCVADDR }, 'o' } }; @@ -3170,6 +3300,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EXCVADDR }, 'm' } }; @@ -3178,6 +3310,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_DEPC }, 'i' } }; @@ -3186,6 +3320,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_DEPC }, 'o' } }; @@ -3194,6 +3330,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_DEPC }, 'm' } }; @@ -3202,6 +3340,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EXCCAUSE }, 'i' }, { { STATE_XTSYNC }, 'i' } }; @@ -3211,6 +3351,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EXCCAUSE }, 'o' } }; @@ -3219,6 +3361,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_EXCCAUSE }, 'm' } }; @@ -3227,6 +3371,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_MISC0 }, 'i' } }; @@ -3235,6 +3381,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_MISC0 }, 'o' } }; @@ -3243,6 +3391,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_MISC0 }, 'm' } }; @@ -3251,6 +3401,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_MISC1 }, 'i' } }; @@ -3259,6 +3411,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_MISC1 }, 'o' } }; @@ -3267,6 +3421,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_MISC1 }, 'm' } }; @@ -3274,6 +3430,11 @@ static xtensa_arg_internal Iclass_xt_icl { { 6 /* art */ }, 'o' } }; +static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { { { 40 /* s */ }, 'i' } }; @@ -3282,8 +3443,9 @@ static xtensa_arg_internal Iclass_xt_icl { { STATE_PSWOE }, 'o' }, { { STATE_PSCALLINC }, 'o' }, { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'm' }, { { STATE_PSUM }, 'o' }, - { { STATE_PSEXCM }, 'o' }, + { { STATE_PSEXCM }, 'm' }, { { STATE_PSINTLEVEL }, 'o' }, { { STATE_EPC1 }, 'i' }, { { STATE_EPC2 }, 'i' }, @@ -3300,6 +3462,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_PSINTLEVEL }, 'o' } }; @@ -3308,6 +3472,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_INTERRUPT }, 'i' } }; @@ -3316,6 +3482,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' }, { { STATE_INTERRUPT }, 'm' } }; @@ -3325,6 +3493,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' }, { { STATE_INTERRUPT }, 'm' } }; @@ -3334,6 +3504,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_INTENABLE }, 'i' } }; @@ -3342,6 +3514,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_INTENABLE }, 'o' } }; @@ -3350,6 +3524,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_INTENABLE }, 'm' } }; @@ -3377,6 +3553,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_DBREAKA0 }, 'i' } }; @@ -3385,6 +3563,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_DBREAKA0 }, 'o' }, { { STATE_XTSYNC }, 'o' } }; @@ -3394,6 +3574,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_DBREAKA0 }, 'm' }, { { STATE_XTSYNC }, 'o' } }; @@ -3403,6 +3585,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_DBREAKC0 }, 'i' } }; @@ -3411,6 +3595,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_DBREAKC0 }, 'o' }, { { STATE_XTSYNC }, 'o' } }; @@ -3420,6 +3606,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_DBREAKC0 }, 'm' }, { { STATE_XTSYNC }, 'o' } }; @@ -3429,6 +3617,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_DBREAKA1 }, 'i' } }; @@ -3437,6 +3627,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_DBREAKA1 }, 'o' }, { { STATE_XTSYNC }, 'o' } }; @@ -3446,6 +3638,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_DBREAKA1 }, 'm' }, { { STATE_XTSYNC }, 'o' } }; @@ -3455,6 +3649,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_DBREAKC1 }, 'i' } }; @@ -3463,6 +3659,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_DBREAKC1 }, 'o' }, { { STATE_XTSYNC }, 'o' } }; @@ -3472,6 +3670,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_DBREAKC1 }, 'm' }, { { STATE_XTSYNC }, 'o' } }; @@ -3481,6 +3681,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_IBREAKA0 }, 'i' } }; @@ -3489,6 +3691,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_IBREAKA0 }, 'o' } }; @@ -3497,6 +3701,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_IBREAKA0 }, 'm' } }; @@ -3505,6 +3711,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_IBREAKA1 }, 'i' } }; @@ -3513,6 +3721,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_IBREAKA1 }, 'o' } }; @@ -3521,6 +3731,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_IBREAKA1 }, 'm' } }; @@ -3529,6 +3741,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_IBREAKENABLE }, 'i' } }; @@ -3537,6 +3751,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_IBREAKENABLE }, 'o' } }; @@ -3545,6 +3761,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_IBREAKENABLE }, 'm' } }; @@ -3553,6 +3771,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_DEBUGCAUSE }, 'i' }, { { STATE_DBNUM }, 'i' } }; @@ -3562,6 +3782,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_DEBUGCAUSE }, 'o' }, { { STATE_DBNUM }, 'o' } }; @@ -3571,6 +3793,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_DEBUGCAUSE }, 'm' }, { { STATE_DBNUM }, 'm' } }; @@ -3580,6 +3804,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_ICOUNT }, 'i' } }; @@ -3588,6 +3814,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' }, { { STATE_ICOUNT }, 'o' } }; @@ -3597,6 +3825,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' }, { { STATE_ICOUNT }, 'm' } }; @@ -3606,6 +3836,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_ICOUNTLEVEL }, 'i' } }; @@ -3614,6 +3846,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_ICOUNTLEVEL }, 'o' } }; @@ -3622,6 +3856,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_ICOUNTLEVEL }, 'm' } }; @@ -3630,6 +3866,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_DDR }, 'i' } }; @@ -3638,6 +3876,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' }, { { STATE_DDR }, 'o' } }; @@ -3647,6 +3887,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' }, { { STATE_DDR }, 'm' } }; @@ -3657,6 +3899,7 @@ static xtensa_arg_internal Iclass_xt_icl { { STATE_PSWOE }, 'o' }, { { STATE_PSCALLINC }, 'o' }, { { STATE_PSOWB }, 'o' }, + { { STATE_PSRING }, 'o' }, { { STATE_PSUM }, 'o' }, { { STATE_PSEXCM }, 'o' }, { { STATE_PSINTLEVEL }, 'o' }, @@ -3672,6 +3915,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_CCOUNT }, 'i' } }; @@ -3680,6 +3925,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' }, { { STATE_CCOUNT }, 'o' } }; @@ -3689,6 +3936,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' }, { { STATE_CCOUNT }, 'm' } }; @@ -3698,6 +3947,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_CCOMPARE0 }, 'i' } }; @@ -3706,6 +3957,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_CCOMPARE0 }, 'o' }, { { STATE_INTERRUPT }, 'm' } }; @@ -3715,6 +3968,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_CCOMPARE0 }, 'm' }, { { STATE_INTERRUPT }, 'm' } }; @@ -3724,6 +3979,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_CCOMPARE1 }, 'i' } }; @@ -3732,6 +3989,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_CCOMPARE1 }, 'o' }, { { STATE_INTERRUPT }, 'm' } }; @@ -3741,6 +4000,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_CCOMPARE1 }, 'm' }, { { STATE_INTERRUPT }, 'm' } }; @@ -3750,6 +4011,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_CCOMPARE2 }, 'i' } }; @@ -3758,6 +4021,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_CCOMPARE2 }, 'o' }, { { STATE_INTERRUPT }, 'm' } }; @@ -3767,6 +4032,8 @@ static xtensa_arg_internal Iclass_xt_icl }; static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_CCOMPARE2 }, 'm' }, { { STATE_INTERRUPT }, 'm' } }; @@ -3781,16 +4048,31 @@ static xtensa_arg_internal Iclass_xt_icl { { 21 /* uimm8x4 */ }, 'i' } }; +static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { { { 6 /* art */ }, 'o' }, { { 4 /* ars */ }, 'i' } }; +static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { { { 6 /* art */ }, 'i' }, { { 4 /* ars */ }, 'i' } }; +static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { { { 4 /* ars */ }, 'i' }, { { 21 /* uimm8x4 */ }, 'i' } @@ -3801,11 +4083,21 @@ static xtensa_arg_internal Iclass_xt_icl { { 22 /* uimm4x16 */ }, 'i' } }; +static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { { { 4 /* ars */ }, 'i' }, { { 21 /* uimm8x4 */ }, 'i' } }; +static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { { { 4 /* ars */ }, 'i' }, { { 21 /* uimm8x4 */ }, 'i' } @@ -3816,16 +4108,164 @@ static xtensa_arg_internal Iclass_xt_icl { { 4 /* ars */ }, 'i' } }; +static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { { { 6 /* art */ }, 'o' }, { { 4 /* ars */ }, 'i' } }; +static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'o' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_PTBASE }, 'm' }, + { { STATE_EXCVADDR }, 'i' }, + { { STATE_XTSYNC }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'i' }, + { { STATE_ASID2 }, 'i' }, + { { STATE_ASID1 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'o' }, + { { STATE_ASID2 }, 'o' }, + { { STATE_ASID1 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_ASID3 }, 'm' }, + { { STATE_ASID2 }, 'm' }, + { { STATE_ASID1 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_INSTPGSZID4 }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { + { { 6 /* art */ }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID4 }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { + { { 6 /* art */ }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID4 }, 'o' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { + { { 6 /* art */ }, 'm' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { + { { STATE_XTSYNC }, 'o' }, + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, + { { STATE_DATAPGSZID4 }, 'm' } +}; + static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { { { 4 /* ars */ }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' } }; @@ -3834,12 +4274,19 @@ static xtensa_arg_internal Iclass_xt_icl { { 4 /* ars */ }, 'i' } }; +static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { { { 6 /* art */ }, 'i' }, { { 4 /* ars */ }, 'i' } }; static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' }, { { STATE_XTSYNC }, 'o' } }; @@ -3847,16 +4294,44 @@ static xtensa_arg_internal Iclass_xt_icl { { 4 /* ars */ }, 'i' } }; +static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { { { 6 /* art */ }, 'o' }, { { 4 /* ars */ }, 'i' } }; +static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { { { 6 /* art */ }, 'i' }, { { 4 /* ars */ }, 'i' } }; +static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { + { { STATE_PSEXCM }, 'i' }, + { { STATE_PSRING }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { + { { STATE_PTBASE }, 'i' }, + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + +static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { + { { STATE_EXCVADDR }, 'i' } +}; + static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { { { 6 /* art */ }, 'o' }, { { 4 /* ars */ }, 'i' } @@ -3866,9 +4341,9 @@ static xtensa_iclass_internal iclasses[] { 0, 0 /* xt_iclass_excw */, 0, 0, 0, 0 }, { 0, 0 /* xt_iclass_rfe */, - 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, { 0, 0 /* xt_iclass_rfde */, - 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, { 0, 0 /* xt_iclass_syscall */, 0, 0, 0, 0 }, { 0, 0 /* xt_iclass_simcall */, @@ -3890,27 +4365,27 @@ static xtensa_iclass_internal iclasses[] { 2, Iclass_xt_iclass_movsp_args, 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rotw_args, - 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_retw_args, 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, { 0, 0 /* xt_iclass_rfwou */, - 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, + 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, { 3, Iclass_xt_iclass_l32e_args, - 0, 0, 0, 0 }, + 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, { 3, Iclass_xt_iclass_s32e_args, - 0, 0, 0, 0 }, + 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_windowbase_args, - 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_windowbase_args, - 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_windowbase_args, - 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_windowstart_args, - 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_windowstart_args, - 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_windowstart_args, - 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, { 3, Iclass_xt_iclass_add_n_args, 0, 0, 0, 0 }, { 3, Iclass_xt_iclass_addi_n_args, @@ -4016,7 +4491,7 @@ static xtensa_iclass_internal iclasses[] { 0, 0 /* xt_iclass_sync */, 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_rsil_args, - 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, + 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_lend_args, 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_lend_args, @@ -4048,259 +4523,289 @@ static xtensa_iclass_internal iclasses[] { 1, Iclass_xt_iclass_xsr_litbase_args, 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_176_args, - 0, 0, 0, 0 }, + 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_208_args, - 0, 0, 0, 0 }, + 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_ps_args, - 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, + 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_ps_args, - 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, + 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_ps_args, - 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, + 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_epc1_args, - 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_epc1_args, - 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_epc1_args, - 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_excsave1_args, - 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_excsave1_args, - 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_excsave1_args, - 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_epc2_args, - 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_epc2_args, - 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_epc2_args, - 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_excsave2_args, - 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_excsave2_args, - 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_excsave2_args, - 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_epc3_args, - 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_epc3_args, - 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_epc3_args, - 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_excsave3_args, - 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_excsave3_args, - 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_excsave3_args, - 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_epc4_args, - 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_epc4_args, - 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_epc4_args, - 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_excsave4_args, - 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_excsave4_args, - 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_excsave4_args, - 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_eps2_args, - 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_eps2_args, - 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_eps2_args, - 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_eps3_args, - 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_eps3_args, - 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_eps3_args, - 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_eps4_args, - 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_eps4_args, - 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_eps4_args, - 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_excvaddr_args, - 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_excvaddr_args, - 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_excvaddr_args, - 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_depc_args, - 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_depc_args, - 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_depc_args, - 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_exccause_args, - 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_exccause_args, - 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_exccause_args, - 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_misc0_args, - 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_misc0_args, - 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_misc0_args, - 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_misc1_args, - 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_misc1_args, - 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_misc1_args, - 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_prid_args, - 0, 0, 0, 0 }, + 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rfi_args, - 14, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, + 15, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wait_args, - 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_interrupt_args, - 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_intset_args, - 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_intclear_args, - 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_intenable_args, - 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_intenable_args, - 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_intenable_args, - 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_break_args, 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_break_n_args, 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_dbreaka0_args, - 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_dbreaka0_args, - 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_dbreaka0_args, - 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_dbreakc0_args, - 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_dbreakc0_args, - 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_dbreakc0_args, - 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_dbreaka1_args, - 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_dbreaka1_args, - 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_dbreaka1_args, - 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_dbreakc1_args, - 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_dbreakc1_args, - 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_dbreakc1_args, - 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_ibreaka0_args, - 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_ibreaka0_args, - 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_ibreaka0_args, - 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_ibreaka1_args, - 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_ibreaka1_args, - 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_ibreaka1_args, - 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_ibreakenable_args, - 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_ibreakenable_args, - 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_ibreakenable_args, - 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_debugcause_args, - 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_debugcause_args, - 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_debugcause_args, - 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_icount_args, - 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_icount_args, - 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_icount_args, - 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_icountlevel_args, - 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_icountlevel_args, - 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_icountlevel_args, - 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_ddr_args, - 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_ddr_args, - 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_ddr_args, - 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, { 0, 0 /* xt_iclass_rfdo */, - 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, + 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, { 0, 0 /* xt_iclass_rfdd */, 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_ccount_args, - 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_ccount_args, - 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_ccount_args, - 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_ccompare0_args, - 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_ccompare0_args, - 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_ccompare0_args, - 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_ccompare1_args, - 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_ccompare1_args, - 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_ccompare1_args, - 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_rsr_ccompare2_args, - 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_wsr_ccompare2_args, - 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_xsr_ccompare2_args, - 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, + 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_icache_args, 0, 0, 0, 0 }, { 2, Iclass_xt_iclass_icache_inv_args, - 0, 0, 0, 0 }, + 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_licx_args, - 0, 0, 0, 0 }, + 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_sicx_args, - 0, 0, 0, 0 }, + 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_dcache_args, 0, 0, 0, 0 }, { 2, Iclass_xt_iclass_dcache_ind_args, - 0, 0, 0, 0 }, + 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_dcache_inv_args, - 0, 0, 0, 0 }, + 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_dpf_args, 0, 0, 0, 0 }, { 2, Iclass_xt_iclass_sdct_args, - 0, 0, 0, 0 }, + 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_ldct_args, - 0, 0, 0, 0 }, + 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_ptevaddr_args, + 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_ptevaddr_args, + 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_ptevaddr_args, + 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_rasid_args, + 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_rasid_args, + 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_rasid_args, + 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_itlbcfg_args, + 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_itlbcfg_args, + 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_itlbcfg_args, + 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, + 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, + 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, + { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, + 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_idtlb_args, - 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_rdtlb_args, - 0, 0, 0, 0 }, + 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_wdtlb_args, - 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, + 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, { 1, Iclass_xt_iclass_iitlb_args, - 0, 0, 0, 0 }, + 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_ritlb_args, - 0, 0, 0, 0 }, + 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_witlb_args, - 0, 0, 0, 0 }, + 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_ldpte */, + 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_hwwitlba */, + 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, + { 0, 0 /* xt_iclass_hwwdtlba */, + 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, { 2, Iclass_xt_iclass_nsa_args, 0, 0, 0, 0 } }; @@ -5893,6 +6398,78 @@ Opcode_ldct_Slot_inst_encode (xtensa_ins } static void +Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5331; +} + +static void +Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5330; +} + +static void +Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5316; +} + +static void +Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a30; +} + +static void +Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a31; +} + +static void +Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5a16; +} + +static void +Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b30; +} + +static void +Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b31; +} + +static void +Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5b16; +} + +static void +Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c30; +} + +static void +Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c31; +} + +static void +Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x5c16; +} + +static void Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xc05; @@ -5953,6 +6530,24 @@ Opcode_witlb_Slot_inst_encode (xtensa_in } static void +Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0xf1f; +} + +static void +Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x105; +} + +static void +Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) +{ + slotbuf[0] = 0x905; +} + +static void Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) { slotbuf[0] = 0xe04; @@ -7020,6 +7615,54 @@ xtensa_opcode_encode_fn Opcode_ldct_enco Opcode_ldct_Slot_inst_encode, 0, 0 }; +xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { + Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { + Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { + Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { + Opcode_rsr_rasid_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { + Opcode_wsr_rasid_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { + Opcode_xsr_rasid_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { + Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { + Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { + Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { + Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { + Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { + Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0 +}; + xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { Opcode_idtlb_Slot_inst_encode, 0, 0 }; @@ -7060,6 +7703,18 @@ xtensa_opcode_encode_fn Opcode_witlb_enc Opcode_witlb_Slot_inst_encode, 0, 0 }; +xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { + Opcode_ldpte_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { + Opcode_hwwitlba_Slot_inst_encode, 0, 0 +}; + +xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { + Opcode_hwwdtlba_Slot_inst_encode, 0, 0 +}; + xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { Opcode_nsa_Slot_inst_encode, 0, 0 }; @@ -7864,40 +8519,85 @@ static xtensa_opcode_internal opcodes[] { "ldct", 212 /* xt_iclass_ldct */, 0, Opcode_ldct_encode_fns, 0, 0 }, - { "idtlb", 213 /* xt_iclass_idtlb */, + { "wsr.ptevaddr", 213 /* xt_iclass_wsr.ptevaddr */, + 0, + Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, + { "rsr.ptevaddr", 214 /* xt_iclass_rsr.ptevaddr */, + 0, + Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, + { "xsr.ptevaddr", 215 /* xt_iclass_xsr.ptevaddr */, + 0, + Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, + { "rsr.rasid", 216 /* xt_iclass_rsr.rasid */, + 0, + Opcode_rsr_rasid_encode_fns, 0, 0 }, + { "wsr.rasid", 217 /* xt_iclass_wsr.rasid */, + 0, + Opcode_wsr_rasid_encode_fns, 0, 0 }, + { "xsr.rasid", 218 /* xt_iclass_xsr.rasid */, + 0, + Opcode_xsr_rasid_encode_fns, 0, 0 }, + { "rsr.itlbcfg", 219 /* xt_iclass_rsr.itlbcfg */, + 0, + Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, + { "wsr.itlbcfg", 220 /* xt_iclass_wsr.itlbcfg */, + 0, + Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, + { "xsr.itlbcfg", 221 /* xt_iclass_xsr.itlbcfg */, + 0, + Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, + { "rsr.dtlbcfg", 222 /* xt_iclass_rsr.dtlbcfg */, + 0, + Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, + { "wsr.dtlbcfg", 223 /* xt_iclass_wsr.dtlbcfg */, + 0, + Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, + { "xsr.dtlbcfg", 224 /* xt_iclass_xsr.dtlbcfg */, + 0, + Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, + { "idtlb", 225 /* xt_iclass_idtlb */, 0, Opcode_idtlb_encode_fns, 0, 0 }, - { "pdtlb", 214 /* xt_iclass_rdtlb */, + { "pdtlb", 226 /* xt_iclass_rdtlb */, 0, Opcode_pdtlb_encode_fns, 0, 0 }, - { "rdtlb0", 214 /* xt_iclass_rdtlb */, + { "rdtlb0", 226 /* xt_iclass_rdtlb */, 0, Opcode_rdtlb0_encode_fns, 0, 0 }, - { "rdtlb1", 214 /* xt_iclass_rdtlb */, + { "rdtlb1", 226 /* xt_iclass_rdtlb */, 0, Opcode_rdtlb1_encode_fns, 0, 0 }, - { "wdtlb", 215 /* xt_iclass_wdtlb */, + { "wdtlb", 227 /* xt_iclass_wdtlb */, 0, Opcode_wdtlb_encode_fns, 0, 0 }, - { "iitlb", 216 /* xt_iclass_iitlb */, + { "iitlb", 228 /* xt_iclass_iitlb */, 0, Opcode_iitlb_encode_fns, 0, 0 }, - { "pitlb", 217 /* xt_iclass_ritlb */, + { "pitlb", 229 /* xt_iclass_ritlb */, 0, Opcode_pitlb_encode_fns, 0, 0 }, - { "ritlb0", 217 /* xt_iclass_ritlb */, + { "ritlb0", 229 /* xt_iclass_ritlb */, 0, Opcode_ritlb0_encode_fns, 0, 0 }, - { "ritlb1", 217 /* xt_iclass_ritlb */, + { "ritlb1", 229 /* xt_iclass_ritlb */, 0, Opcode_ritlb1_encode_fns, 0, 0 }, - { "witlb", 218 /* xt_iclass_witlb */, + { "witlb", 230 /* xt_iclass_witlb */, 0, Opcode_witlb_encode_fns, 0, 0 }, - { "nsa", 219 /* xt_iclass_nsa */, + { "ldpte", 231 /* xt_iclass_ldpte */, + 0, + Opcode_ldpte_encode_fns, 0, 0 }, + { "hwwitlba", 232 /* xt_iclass_hwwitlba */, + XTENSA_OPCODE_IS_BRANCH, + Opcode_hwwitlba_encode_fns, 0, 0 }, + { "hwwdtlba", 233 /* xt_iclass_hwwdtlba */, + 0, + Opcode_hwwdtlba_encode_fns, 0, 0 }, + { "nsa", 234 /* xt_iclass_nsa */, 0, Opcode_nsa_encode_fns, 0, 0 }, - { "nsau", 219 /* xt_iclass_nsa */, + { "nsau", 234 /* xt_iclass_nsa */, 0, Opcode_nsau_encode_fns, 0, 0 } }; @@ -7923,7 +8623,10 @@ Slot_inst_decode (const xtensa_insnbuf i switch (Field_m_Slot_inst_get (insn)) { case 0: - return 77; /* ill */ + if (Field_s_Slot_inst_get (insn) == 0 && + Field_n_Slot_inst_get (insn) == 0) + return 77; /* ill */ + break; case 2: switch (Field_n_Slot_inst_get (insn)) { @@ -8053,34 +8756,42 @@ Slot_inst_decode (const xtensa_insnbuf i return 13; /* rotw */ break; case 14: - return 274; /* nsa */ + return 289; /* nsa */ case 15: - return 275; /* nsau */ + return 290; /* nsau */ } break; case 5: switch (Field_r_Slot_inst_get (insn)) { + case 1: + return 287; /* hwwitlba */ case 3: - return 271; /* ritlb0 */ + return 283; /* ritlb0 */ case 4: - return 269; /* iitlb */ + if (Field_t_Slot_inst_get (insn) == 0) + return 281; /* iitlb */ + break; case 5: - return 270; /* pitlb */ + return 282; /* pitlb */ case 6: - return 273; /* witlb */ + return 285; /* witlb */ case 7: - return 272; /* ritlb1 */ + return 284; /* ritlb1 */ + case 9: + return 288; /* hwwdtlba */ case 11: - return 266; /* rdtlb0 */ + return 278; /* rdtlb0 */ case 12: - return 264; /* idtlb */ + if (Field_t_Slot_inst_get (insn) == 0) + return 276; /* idtlb */ + break; case 13: - return 265; /* pdtlb */ + return 277; /* pdtlb */ case 14: - return 268; /* wdtlb */ + return 280; /* wdtlb */ case 15: - return 267; /* rdtlb1 */ + return 279; /* rdtlb1 */ } break; case 6: @@ -8138,6 +8849,14 @@ Slot_inst_decode (const xtensa_insnbuf i return 22; /* xsr.windowbase */ case 73: return 25; /* xsr.windowstart */ + case 83: + return 266; /* xsr.ptevaddr */ + case 90: + return 269; /* xsr.rasid */ + case 91: + return 272; /* xsr.itlbcfg */ + case 92: + return 275; /* xsr.dtlbcfg */ case 96: return 218; /* xsr.ibreakenable */ case 104: @@ -8236,11 +8955,15 @@ Slot_inst_decode (const xtensa_insnbuf i case 9: return 262; /* sdct */ case 14: - if (Field_t_Slot_inst_get (insn) == 0) + if (Field_t_Slot_inst_get (insn) == 0 && + Field_s_Slot_inst_get (insn) == 0) return 231; /* rfdo */ - if (Field_t_Slot_inst_get (insn) == 1) + if (Field_t_Slot_inst_get (insn) == 1 && + Field_s_Slot_inst_get (insn) == 0) return 232; /* rfdd */ break; + case 15: + return 286; /* ldpte */ } break; } @@ -8265,6 +8988,14 @@ Slot_inst_decode (const xtensa_insnbuf i return 20; /* rsr.windowbase */ case 73: return 23; /* rsr.windowstart */ + case 83: + return 265; /* rsr.ptevaddr */ + case 90: + return 267; /* rsr.rasid */ + case 91: + return 270; /* rsr.itlbcfg */ + case 92: + return 273; /* rsr.dtlbcfg */ case 96: return 216; /* rsr.ibreakenable */ case 104: @@ -8358,6 +9089,14 @@ Slot_inst_decode (const xtensa_insnbuf i return 21; /* wsr.windowbase */ case 73: return 24; /* wsr.windowstart */ + case 83: + return 264; /* wsr.ptevaddr */ + case 90: + return 268; /* wsr.rasid */ + case 91: + return 271; /* wsr.itlbcfg */ + case 92: + return 274; /* wsr.dtlbcfg */ case 96: return 217; /* wsr.ibreakenable */ case 104: @@ -8664,7 +9403,9 @@ Slot_inst16b_decode (const xtensa_insnbu return 34; /* nop.n */ break; case 6: - return 30; /* ill.n */ + if (Field_s_Slot_inst16b_get (insn) == 0) + return 30; /* ill.n */ + break; } break; } @@ -9090,8 +9831,8 @@ xtensa_isa_internal xtensa_modules = { 3, slots, 39 /* num_fields */, 70, operands, - 220, iclasses, - 276, opcodes, 0, + 235, iclasses, + 291, opcodes, 0, 1, regfiles, NUM_STATES, states, 0, NUM_SYSREGS, sysregs, 0, diff -uprN binutils-2.16.91.0.1/binutils/binemul.c binutils-2.16.91.0.2/binutils/binemul.c --- binutils-2.16.91.0.1/binutils/binemul.c 2005-05-10 15:46:43.000000000 -0700 +++ binutils-2.16.91.0.2/binutils/binemul.c 2005-07-20 12:27:27.518155947 -0700 @@ -1,6 +1,6 @@ /* Binutils emulation layer. Copyright 2002, 2003 Free Software Foundation, Inc. - Written by Tom Rix, Redhat. + Written by Tom Rix, Red Hat Inc. This file is part of GNU Binutils. diff -uprN binutils-2.16.91.0.1/binutils/binemul.h binutils-2.16.91.0.2/binutils/binemul.h --- binutils-2.16.91.0.1/binutils/binemul.h 2005-05-10 15:46:43.000000000 -0700 +++ binutils-2.16.91.0.2/binutils/binemul.h 2005-07-20 12:27:27.530153968 -0700 @@ -1,6 +1,6 @@ /* Binutils emulation layer. Copyright 2002, 2003 Free Software Foundation, Inc. - Written by Tom Rix, Redhat. + Written by Tom Rix, Red Hat Inc. This file is part of GNU Binutils. @@ -40,7 +40,7 @@ extern bfd_boolean ar_emul_default_parse fprintf (fp, _(" emulation options: \n")) #define AR_EMUL_ELEMENT_CHECK(abfd, file_name) \ - do { if ((abfd) == (bfd *) NULL) bfd_fatal (file_name); } while (0) + do { if ((abfd) == NULL) bfd_fatal (file_name); } while (0) #define AR_EMUL_APPEND_PRINT_VERBOSE(verbose, file_name) \ do { if (verbose) printf ("a - %s\n", file_name); } while (0) diff -uprN binutils-2.16.91.0.1/binutils/bucomm.h binutils-2.16.91.0.2/binutils/bucomm.h --- binutils-2.16.91.0.1/binutils/bucomm.h 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/binutils/bucomm.h 2005-07-20 12:27:27.535153144 -0700 @@ -28,11 +28,7 @@ #include "config.h" #include "bin-bugs.h" -#ifdef ANSI_PROTOTYPES #include -#else -#include -#endif #ifdef USE_BINARY_FOPEN #include "fopen-bin.h" @@ -72,21 +68,21 @@ extern char *strrchr (); #endif #endif -#ifdef NEED_DECLARATION_STRSTR +#if !HAVE_DECL_STRSTR extern char *strstr (); #endif #ifdef HAVE_SBRK -#ifdef NEED_DECLARATION_SBRK +#if !HAVE_DECL_SBRK extern char *sbrk (); #endif #endif -#ifdef NEED_DECLARATION_GETENV +#if !HAVE_DECL_GETENV extern char *getenv (); #endif -#ifdef NEED_DECLARATION_ENVIRON +#if !HAVE_DECL_ENVIRON extern char **environ; #endif @@ -159,7 +155,7 @@ void bfd_nonfatal (const char *); void bfd_fatal (const char *) ATTRIBUTE_NORETURN; -void report (const char *, va_list); +void report (const char *, va_list) ATTRIBUTE_PRINTF(1,0); void fatal (const char *, ...) ATTRIBUTE_PRINTF_1 ATTRIBUTE_NORETURN; diff -uprN binutils-2.16.91.0.1/binutils/ChangeLog binutils-2.16.91.0.2/binutils/ChangeLog --- binutils-2.16.91.0.1/binutils/ChangeLog 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/binutils/ChangeLog 2005-07-20 12:27:27.496159574 -0700 @@ -1,3 +1,88 @@ +2005-07-19 Ben Elliston + + * readelf.c (read_and_display_attr_value): Remove comment adjacent + to DW_ATE_decimal_float about it being a GNU extension. + +2005-07-18 Nick Clifton + + * binemul.c: Fix name of Red Hat. + * binemul.h: Likewise. + * emul_aix.c: Likewise. + * emul_vanilla: Likewise. + +2005-07-18 Ben Elliston + + * readelf.c (read_and_display_attr_value): Handle a DW_AT_encoding + value of DW_ATE_decimal_float instead of DW_ATE_GNU_decimal_float. + +2005-07-16 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2005-07-15 Eric Christopher + + * MAINTAINERS: Change affiliation. + +2005-07-14 Jim Blandy + + * readelf.c: #include "elf/m32c.h" + (guess_is_rela, dump_relocations, get_machine_name): Add cases for + EM_M32C. + * Makefile.am (readelf.o): Update dependencies. + * Makefile.in: Regenerated. + +2005-07-08 Ben Elliston + + * bucomm.h: Include unconditionally, not only when + ANSI_PROTOTYPES is defined. Remove #ifdef logic. + * dlltool.c: Likewise. + * dllwrap.c: Likewise. + +2005-07-07 Kaveh R. Ghazi + + * bucomm.h (report): Add format attribute. + * dlltool.c (inform): Likewise. + * dllwrap.c (display, inform, warn): Likewise. + * objdump.c (objdump_sprintf): Likewise. + * readelf.c (error, warn): Likewise. Fix format bugs. + +2005-07-05 Dmitry V. Levin + Nick Clifton + + * strings.c (filename_and_size_t): New typedef. + (strings_a_section): Skip sections with size greater or equal to + the file size. Cache the file size to avoid repeated stat()s. + (strings_object_file): Pass filename_and_size_t argument to + strings_a_section() via bfd_map_over_sections(). + +2005-07-04 Alan Modra + + PR 1004 + * objcopy.c (copy_object): Use bfd_make_section_with_flags. + (write_debugging_info): Likewise. + (setup_section): Use bfd_make_section_anyway_with_flags. + +2005-07-01 Steve Ellcey + + * configure.in (AM_BINUTILS_WARNINGS): Add. + (BFD_NEED_DECLARATION): Replace with AC_CHECK_DECLS. + * configure: Regenerate. + * config.in: Regenerate. + * objdump.c (NEED_DECLARATION_*): Replace with !HAVE_DECL_*. + * bucomm.h: (NEED_DECLARATION_*): Ditto. + +2005-06-30 Ben Elliston + + * Makefile.am (check-DEJAGNU): Don't search for expect. + * Makefile.in: Regenerate. + +2005-06-30 Ben Elliston + + * Makefile.am (EXPECT): Set to expect. + (RUNTEST): Likewise, set to runtest. + * Makefile.in: Regenerate. + 2005-06-17 Jakub Jelinek * readelf.c (CHECK_ENTSIZE_VALUES, CHECK_ENTSIZE): Define. diff -uprN binutils-2.16.91.0.1/binutils/config.in binutils-2.16.91.0.2/binutils/config.in --- binutils-2.16.91.0.1/binutils/config.in 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/binutils/config.in 2005-07-20 12:27:27.535153144 -0700 @@ -29,13 +29,33 @@ /* Define to 1 if you have the `dcgettext' function. */ #undef HAVE_DCGETTEXT +/* Define to 1 if you have the declaration of `environ', and to 0 if you + don't. */ +#undef HAVE_DECL_ENVIRON + +/* Define to 1 if you have the declaration of `fprintf', and to 0 if you + don't. */ +#undef HAVE_DECL_FPRINTF + /* Define to 1 if you have the declaration of `getc_unlocked', and to 0 if you don't. */ #undef HAVE_DECL_GETC_UNLOCKED +/* Define to 1 if you have the declaration of `getenv', and to 0 if you don't. + */ +#undef HAVE_DECL_GETENV + /* Is the prototype for getopt in in the expected format? */ #undef HAVE_DECL_GETOPT +/* Define to 1 if you have the declaration of `sbrk', and to 0 if you don't. + */ +#undef HAVE_DECL_SBRK + +/* Define to 1 if you have the declaration of `strstr', and to 0 if you don't. + */ +#undef HAVE_DECL_STRSTR + /* Define to 1 if you have the header file. */ #undef HAVE_DLFCN_H @@ -177,21 +197,6 @@ /* Define to 1 if you have the `__argz_stringify' function. */ #undef HAVE___ARGZ_STRINGIFY -/* Define if environ is not declared in system header files. */ -#undef NEED_DECLARATION_ENVIRON - -/* Define if fprintf is not declared in system header files. */ -#undef NEED_DECLARATION_FPRINTF - -/* Define if getenv is not declared in system header files. */ -#undef NEED_DECLARATION_GETENV - -/* Define if sbrk is not declared in system header files. */ -#undef NEED_DECLARATION_SBRK - -/* Define if strstr is not declared in system header files. */ -#undef NEED_DECLARATION_STRSTR - /* Name of package */ #undef PACKAGE diff -uprN binutils-2.16.91.0.1/binutils/configure binutils-2.16.91.0.2/binutils/configure --- binutils-2.16.91.0.1/binutils/configure 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/binutils/configure 2005-07-20 12:27:27.550150671 -0700 @@ -4074,6 +4074,7 @@ echo "$as_me: error: bad value ${enablev { (exit 1); exit 1; }; } ;; esac fi; + WARN_CFLAGS="-W -Wall -Wstrict-prototypes -Wmissing-prototypes" # Check whether --enable-werror or --disable-werror was given. @@ -4120,6 +4121,7 @@ fi + ac_config_headers="$ac_config_headers config.h:config.in" @@ -10089,9 +10091,9 @@ _ACEOF fi -echo "$as_me:$LINENO: checking whether fprintf must be declared" >&5 -echo $ECHO_N "checking whether fprintf must be declared... $ECHO_C" >&6 -if test "${bfd_cv_decl_needed_fprintf+set}" = set; then +echo "$as_me:$LINENO: checking whether fprintf is declared" >&5 +echo $ECHO_N "checking whether fprintf is declared... $ECHO_C" >&6 +if test "${ac_cv_have_decl_fprintf+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF @@ -10100,25 +10102,14 @@ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ - -#include -#ifdef HAVE_STRING_H -#include -#else -#ifdef HAVE_STRINGS_H -#include -#endif -#endif -#ifdef HAVE_STDLIB_H -#include -#endif -#ifdef HAVE_UNISTD_H -#include -#endif +$ac_includes_default int main () { -char *(*pfn) = (char *(*)) fprintf +#ifndef fprintf + char *p = (char *) fprintf; +#endif + ; return 0; } @@ -10145,29 +10136,34 @@ if { (eval echo "$as_me:$LINENO: \"$ac_c ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - bfd_cv_decl_needed_fprintf=no + ac_cv_have_decl_fprintf=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -bfd_cv_decl_needed_fprintf=yes +ac_cv_have_decl_fprintf=no fi rm -f conftest.err conftest.$ac_objext conftest.$ac_ext fi +echo "$as_me:$LINENO: result: $ac_cv_have_decl_fprintf" >&5 +echo "${ECHO_T}$ac_cv_have_decl_fprintf" >&6 +if test $ac_cv_have_decl_fprintf = yes; then -echo "$as_me:$LINENO: result: $bfd_cv_decl_needed_fprintf" >&5 -echo "${ECHO_T}$bfd_cv_decl_needed_fprintf" >&6 -if test $bfd_cv_decl_needed_fprintf = yes; then +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_FPRINTF 1 +_ACEOF -cat >>confdefs.h <<\_ACEOF -#define NEED_DECLARATION_FPRINTF 1 + +else + cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_FPRINTF 0 _ACEOF -fi -echo "$as_me:$LINENO: checking whether strstr must be declared" >&5 -echo $ECHO_N "checking whether strstr must be declared... $ECHO_C" >&6 -if test "${bfd_cv_decl_needed_strstr+set}" = set; then +fi +echo "$as_me:$LINENO: checking whether strstr is declared" >&5 +echo $ECHO_N "checking whether strstr is declared... $ECHO_C" >&6 +if test "${ac_cv_have_decl_strstr+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF @@ -10176,25 +10172,14 @@ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ - -#include -#ifdef HAVE_STRING_H -#include -#else -#ifdef HAVE_STRINGS_H -#include -#endif -#endif -#ifdef HAVE_STDLIB_H -#include -#endif -#ifdef HAVE_UNISTD_H -#include -#endif +$ac_includes_default int main () { -char *(*pfn) = (char *(*)) strstr +#ifndef strstr + char *p = (char *) strstr; +#endif + ; return 0; } @@ -10221,29 +10206,34 @@ if { (eval echo "$as_me:$LINENO: \"$ac_c ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - bfd_cv_decl_needed_strstr=no + ac_cv_have_decl_strstr=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -bfd_cv_decl_needed_strstr=yes +ac_cv_have_decl_strstr=no fi rm -f conftest.err conftest.$ac_objext conftest.$ac_ext fi +echo "$as_me:$LINENO: result: $ac_cv_have_decl_strstr" >&5 +echo "${ECHO_T}$ac_cv_have_decl_strstr" >&6 +if test $ac_cv_have_decl_strstr = yes; then -echo "$as_me:$LINENO: result: $bfd_cv_decl_needed_strstr" >&5 -echo "${ECHO_T}$bfd_cv_decl_needed_strstr" >&6 -if test $bfd_cv_decl_needed_strstr = yes; then +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_STRSTR 1 +_ACEOF -cat >>confdefs.h <<\_ACEOF -#define NEED_DECLARATION_STRSTR 1 + +else + cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_STRSTR 0 _ACEOF -fi -echo "$as_me:$LINENO: checking whether sbrk must be declared" >&5 -echo $ECHO_N "checking whether sbrk must be declared... $ECHO_C" >&6 -if test "${bfd_cv_decl_needed_sbrk+set}" = set; then +fi +echo "$as_me:$LINENO: checking whether sbrk is declared" >&5 +echo $ECHO_N "checking whether sbrk is declared... $ECHO_C" >&6 +if test "${ac_cv_have_decl_sbrk+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF @@ -10252,25 +10242,14 @@ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ - -#include -#ifdef HAVE_STRING_H -#include -#else -#ifdef HAVE_STRINGS_H -#include -#endif -#endif -#ifdef HAVE_STDLIB_H -#include -#endif -#ifdef HAVE_UNISTD_H -#include -#endif +$ac_includes_default int main () { -char *(*pfn) = (char *(*)) sbrk +#ifndef sbrk + char *p = (char *) sbrk; +#endif + ; return 0; } @@ -10297,29 +10276,34 @@ if { (eval echo "$as_me:$LINENO: \"$ac_c ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - bfd_cv_decl_needed_sbrk=no + ac_cv_have_decl_sbrk=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -bfd_cv_decl_needed_sbrk=yes +ac_cv_have_decl_sbrk=no fi rm -f conftest.err conftest.$ac_objext conftest.$ac_ext fi +echo "$as_me:$LINENO: result: $ac_cv_have_decl_sbrk" >&5 +echo "${ECHO_T}$ac_cv_have_decl_sbrk" >&6 +if test $ac_cv_have_decl_sbrk = yes; then -echo "$as_me:$LINENO: result: $bfd_cv_decl_needed_sbrk" >&5 -echo "${ECHO_T}$bfd_cv_decl_needed_sbrk" >&6 -if test $bfd_cv_decl_needed_sbrk = yes; then +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_SBRK 1 +_ACEOF -cat >>confdefs.h <<\_ACEOF -#define NEED_DECLARATION_SBRK 1 + +else + cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_SBRK 0 _ACEOF -fi -echo "$as_me:$LINENO: checking whether getenv must be declared" >&5 -echo $ECHO_N "checking whether getenv must be declared... $ECHO_C" >&6 -if test "${bfd_cv_decl_needed_getenv+set}" = set; then +fi +echo "$as_me:$LINENO: checking whether getenv is declared" >&5 +echo $ECHO_N "checking whether getenv is declared... $ECHO_C" >&6 +if test "${ac_cv_have_decl_getenv+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF @@ -10328,25 +10312,14 @@ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ - -#include -#ifdef HAVE_STRING_H -#include -#else -#ifdef HAVE_STRINGS_H -#include -#endif -#endif -#ifdef HAVE_STDLIB_H -#include -#endif -#ifdef HAVE_UNISTD_H -#include -#endif +$ac_includes_default int main () { -char *(*pfn) = (char *(*)) getenv +#ifndef getenv + char *p = (char *) getenv; +#endif + ; return 0; } @@ -10373,29 +10346,34 @@ if { (eval echo "$as_me:$LINENO: \"$ac_c ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - bfd_cv_decl_needed_getenv=no + ac_cv_have_decl_getenv=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -bfd_cv_decl_needed_getenv=yes +ac_cv_have_decl_getenv=no fi rm -f conftest.err conftest.$ac_objext conftest.$ac_ext fi +echo "$as_me:$LINENO: result: $ac_cv_have_decl_getenv" >&5 +echo "${ECHO_T}$ac_cv_have_decl_getenv" >&6 +if test $ac_cv_have_decl_getenv = yes; then -echo "$as_me:$LINENO: result: $bfd_cv_decl_needed_getenv" >&5 -echo "${ECHO_T}$bfd_cv_decl_needed_getenv" >&6 -if test $bfd_cv_decl_needed_getenv = yes; then +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_GETENV 1 +_ACEOF -cat >>confdefs.h <<\_ACEOF -#define NEED_DECLARATION_GETENV 1 + +else + cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_GETENV 0 _ACEOF -fi -echo "$as_me:$LINENO: checking whether environ must be declared" >&5 -echo $ECHO_N "checking whether environ must be declared... $ECHO_C" >&6 -if test "${bfd_cv_decl_needed_environ+set}" = set; then +fi +echo "$as_me:$LINENO: checking whether environ is declared" >&5 +echo $ECHO_N "checking whether environ is declared... $ECHO_C" >&6 +if test "${ac_cv_have_decl_environ+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF @@ -10404,25 +10382,14 @@ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ - -#include -#ifdef HAVE_STRING_H -#include -#else -#ifdef HAVE_STRINGS_H -#include -#endif -#endif -#ifdef HAVE_STDLIB_H -#include -#endif -#ifdef HAVE_UNISTD_H -#include -#endif +$ac_includes_default int main () { -char *(*pfn) = (char *(*)) environ +#ifndef environ + char *p = (char *) environ; +#endif + ; return 0; } @@ -10449,26 +10416,31 @@ if { (eval echo "$as_me:$LINENO: \"$ac_c ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then - bfd_cv_decl_needed_environ=no + ac_cv_have_decl_environ=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 -bfd_cv_decl_needed_environ=yes +ac_cv_have_decl_environ=no fi rm -f conftest.err conftest.$ac_objext conftest.$ac_ext fi +echo "$as_me:$LINENO: result: $ac_cv_have_decl_environ" >&5 +echo "${ECHO_T}$ac_cv_have_decl_environ" >&6 +if test $ac_cv_have_decl_environ = yes; then -echo "$as_me:$LINENO: result: $bfd_cv_decl_needed_environ" >&5 -echo "${ECHO_T}$bfd_cv_decl_needed_environ" >&6 -if test $bfd_cv_decl_needed_environ = yes; then +cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_ENVIRON 1 +_ACEOF -cat >>confdefs.h <<\_ACEOF -#define NEED_DECLARATION_ENVIRON 1 + +else + cat >>confdefs.h <<_ACEOF +#define HAVE_DECL_ENVIRON 0 _ACEOF -fi +fi echo "$as_me:$LINENO: checking whether getc_unlocked is declared" >&5 echo $ECHO_N "checking whether getc_unlocked is declared... $ECHO_C" >&6 if test "${ac_cv_have_decl_getc_unlocked+set}" = set; then diff -uprN binutils-2.16.91.0.1/binutils/configure.in binutils-2.16.91.0.2/binutils/configure.in --- binutils-2.16.91.0.1/binutils/configure.in 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/binutils/configure.in 2005-07-20 12:27:27.551150506 -0700 @@ -29,49 +29,8 @@ AC_ARG_ENABLE(commonbfdlib, *) AC_MSG_ERROR([bad value ${enableval} for BFD commonbfdlib option]) ;; esac])dnl -dnl FIXME: The following is bfd/warning.m4 contents expanded -dnl When converting to current autotools, please replace with -dnl AM_BINUTILS_WARNINGS -WARN_CFLAGS="-W -Wall -Wstrict-prototypes -Wmissing-prototypes" - -AC_ARG_ENABLE(werror, - [ --enable-werror treat compile warnings as errors], - [case "${enableval}" in - yes | y) ERROR_ON_WARNING="yes" ;; - no | n) ERROR_ON_WARNING="no" ;; - *) AC_MSG_ERROR(bad value ${enableval} for --enable-werror) ;; - esac]) - -# Enable -Werror by default when using gcc -if test "${GCC}" = yes -a -z "${ERROR_ON_WARNING}" ; then - ERROR_ON_WARNING=yes -fi - -NO_WERROR= -if test "${ERROR_ON_WARNING}" = yes ; then - WARN_CFLAGS="$WARN_CFLAGS -Werror" - NO_WERROR="-Wno-error" -fi +AM_BINUTILS_WARNINGS -AC_ARG_ENABLE(build-warnings, -[ --enable-build-warnings Enable build-time compiler warnings], -[case "${enableval}" in - yes) ;; - no) WARN_CFLAGS="-w";; - ,*) t=`echo "${enableval}" | sed -e "s/,/ /g"` - WARN_CFLAGS="${WARN_CFLAGS} ${t}";; - *,) t=`echo "${enableval}" | sed -e "s/,/ /g"` - WARN_CFLAGS="${t} ${WARN_CFLAGS}";; - *) WARN_CFLAGS=`echo "${enableval}" | sed -e "s/,/ /g"`;; -esac]) - -if test x"$silent" != x"yes" && test x"$WARN_CFLAGS" != x""; then - echo "Setting warning flags = $WARN_CFLAGS" 6>&1 -fi - -AC_SUBST(WARN_CFLAGS) -AC_SUBST(NO_WERROR) - AM_CONFIG_HEADER(config.h:config.in) if test -z "$target" ; then @@ -223,12 +182,7 @@ if test $bu_cv_header_utime_h = yes; the AC_DEFINE(HAVE_GOOD_UTIME_H, 1, [Does define struct utimbuf?]) fi -BFD_NEED_DECLARATION(fprintf) -BFD_NEED_DECLARATION(strstr) -BFD_NEED_DECLARATION(sbrk) -BFD_NEED_DECLARATION(getenv) -BFD_NEED_DECLARATION(environ) -AC_CHECK_DECLS(getc_unlocked) +AC_CHECK_DECLS([fprintf, strstr, sbrk, getenv, environ, getc_unlocked]) BFD_BINARY_FOPEN diff -uprN binutils-2.16.91.0.1/binutils/dlltool.c binutils-2.16.91.0.2/binutils/dlltool.c --- binutils-2.16.91.0.1/binutils/dlltool.c 2005-05-10 15:46:43.000000000 -0700 +++ binutils-2.16.91.0.2/binutils/dlltool.c 2005-07-20 12:27:27.562148692 -0700 @@ -254,13 +254,7 @@ #include #include - -#ifdef ANSI_PROTOTYPES #include -#else -#include -#endif - #include #ifdef DLLTOOL_ARM @@ -708,7 +702,7 @@ static void fill_ordinals (export_type * static int alphafunc (const void *, const void *); static void mangle_defs (void); static void usage (FILE *, int); -static void inform (const char *, ...); +static void inform (const char *, ...) ATTRIBUTE_PRINTF_1; static void set_dll_name_from_def (const char *); static char * diff -uprN binutils-2.16.91.0.1/binutils/dllwrap.c binutils-2.16.91.0.2/binutils/dllwrap.c --- binutils-2.16.91.0.1/binutils/dllwrap.c 2005-05-10 15:46:43.000000000 -0700 +++ binutils-2.16.91.0.2/binutils/dllwrap.c 2005-07-20 12:27:27.563148528 -0700 @@ -38,12 +38,7 @@ #include #include - -#ifdef ANSI_PROTOTYPES #include -#else -#include -#endif #ifdef HAVE_SYS_WAIT_H #include @@ -118,9 +113,9 @@ static int run (const char *, char *); static char *mybasename (const char *); static int strhash (const char *); static void usage (FILE *, int); -static void display (const char *, va_list); -static void inform (const char *, ...); -static void warn (const char *, ...); +static void display (const char *, va_list) ATTRIBUTE_PRINTF(1,0); +static void inform (const char *, ...) ATTRIBUTE_PRINTF_1; +static void warn (const char *, ...) ATTRIBUTE_PRINTF_1; static char *look_for_prog (const char *, const char *, int); static char *deduce_name (const char *); static void delete_temp_files (void); diff -uprN binutils-2.16.91.0.1/binutils/emul_aix.c binutils-2.16.91.0.2/binutils/emul_aix.c --- binutils-2.16.91.0.1/binutils/emul_aix.c 2005-05-10 15:46:43.000000000 -0700 +++ binutils-2.16.91.0.2/binutils/emul_aix.c 2005-07-20 12:27:27.564148363 -0700 @@ -1,6 +1,6 @@ /* Binutils emulation layer. Copyright 2002, 2003 Free Software Foundation, Inc. - Written by Tom Rix, Redhat. + Written by Tom Rix, Red Hat Inc. This file is part of GNU Binutils. diff -uprN binutils-2.16.91.0.1/binutils/emul_vanilla.c binutils-2.16.91.0.2/binutils/emul_vanilla.c --- binutils-2.16.91.0.1/binutils/emul_vanilla.c 2005-05-10 15:46:43.000000000 -0700 +++ binutils-2.16.91.0.2/binutils/emul_vanilla.c 2005-07-20 12:27:27.564148363 -0700 @@ -1,6 +1,6 @@ /* Binutils emulation layer. Copyright (C) 2002 Free Software Foundation, Inc. - Written by Tom Rix, Redhat. + Written by Tom Rix, Red Hat Inc. This file is part of GNU Binutils. diff -uprN binutils-2.16.91.0.1/binutils/MAINTAINERS binutils-2.16.91.0.2/binutils/MAINTAINERS --- binutils-2.16.91.0.1/binutils/MAINTAINERS 2005-04-29 10:50:26.000000000 -0700 +++ binutils-2.16.91.0.2/binutils/MAINTAINERS 2005-07-20 12:27:27.501158750 -0700 @@ -86,7 +86,7 @@ responsibility among the other maintaine M68k Ben Elliston M88k Mark Kettenis MAXQ Inderpreet Singh - MIPS Eric Christopher + MIPS Eric Christopher MIPS Thiemo Seufer MMIX Hans-Peter Nilsson MN10300 Eric Christopher diff -uprN binutils-2.16.91.0.1/binutils/Makefile.am binutils-2.16.91.0.2/binutils/Makefile.am --- binutils-2.16.91.0.1/binutils/Makefile.am 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/binutils/Makefile.am 2005-07-20 12:27:27.502158585 -0700 @@ -119,12 +119,8 @@ po/POTFILES.in: @MAINT@ Makefile for f in $(POTFILES); do echo $$f; done | LC_COLLATE= sort > tmp \ && mv tmp $(srcdir)/po/POTFILES.in -EXPECT = `if [ -f $$r/../expect/expect ] ; then \ - echo $$r/../expect/expect ; \ - else echo expect ; fi` -RUNTEST = `if [ -f ${srcdir}/../dejagnu/runtest ] ; then \ - echo ${srcdir}/../dejagnu/runtest ; \ - else echo runtest ; fi` +EXPECT = expect +RUNTEST = runtest CC_FOR_TARGET = ` \ if [ -f $$r/../gcc/xgcc ] ; then \ @@ -145,10 +141,6 @@ check-DEJAGNU: site.exp srcdir=`cd $(srcdir) && pwd`; export srcdir; \ r=`pwd`; export r; \ EXPECT=$(EXPECT); export EXPECT; \ - if [ -f $(top_builddir)/../expect/expect ]; then \ - TCL_LIBRARY=`cd $(top_srcdir)/../tcl/library && pwd`; \ - export TCL_LIBRARY; \ - fi; \ runtest=$(RUNTEST); \ if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \ CC_FOR_TARGET="$(CC_FOR_TARGET)" CFLAGS_FOR_TARGET="$(CFLAGS)" \ @@ -492,16 +484,16 @@ readelf.o: readelf.c ../bfd/bfd.h $(INCD $(INCDIR)/elf/frv.h $(INCDIR)/elf/h8.h $(INCDIR)/elf/hppa.h \ $(INCDIR)/elf/i386.h $(INCDIR)/elf/i370.h $(INCDIR)/elf/i860.h \ $(INCDIR)/elf/i960.h $(INCDIR)/elf/ia64.h $(INCDIR)/elf/ip2k.h \ - $(INCDIR)/elf/m32r.h $(INCDIR)/elf/m68k.h $(INCDIR)/elf/m68hc11.h \ - $(INCDIR)/elf/mcore.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/mmix.h \ - $(INCDIR)/elf/mn10200.h $(INCDIR)/elf/mn10300.h $(INCDIR)/elf/msp430.h \ - $(INCDIR)/elf/ms1.h \ - $(INCDIR)/elf/or32.h $(INCDIR)/elf/pj.h $(INCDIR)/elf/ppc.h \ - $(INCDIR)/elf/ppc64.h $(INCDIR)/elf/s390.h $(INCDIR)/elf/sh.h \ - $(INCDIR)/elf/sparc.h $(INCDIR)/elf/v850.h $(INCDIR)/elf/vax.h \ - $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/xstormy16.h $(INCDIR)/elf/crx.h \ - $(INCDIR)/elf/iq2000.h $(INCDIR)/elf/xtensa.h $(INCDIR)/aout/ar.h \ - bucomm.h config.h $(INCDIR)/bin-bugs.h $(INCDIR)/fopen-same.h \ + $(INCDIR)/elf/m32c.h $(INCDIR)/elf/m32r.h $(INCDIR)/elf/m68k.h \ + $(INCDIR)/elf/m68hc11.h $(INCDIR)/elf/mcore.h $(INCDIR)/elf/mips.h \ + $(INCDIR)/elf/mmix.h $(INCDIR)/elf/mn10200.h $(INCDIR)/elf/mn10300.h \ + $(INCDIR)/elf/ms1.h $(INCDIR)/elf/msp430.h $(INCDIR)/elf/or32.h \ + $(INCDIR)/elf/pj.h $(INCDIR)/elf/ppc.h $(INCDIR)/elf/ppc64.h \ + $(INCDIR)/elf/s390.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/sparc.h \ + $(INCDIR)/elf/v850.h $(INCDIR)/elf/vax.h $(INCDIR)/elf/x86-64.h \ + $(INCDIR)/elf/xstormy16.h $(INCDIR)/elf/crx.h $(INCDIR)/elf/iq2000.h \ + $(INCDIR)/elf/xtensa.h $(INCDIR)/aout/ar.h bucomm.h \ + config.h $(INCDIR)/bin-bugs.h $(INCDIR)/fopen-same.h \ $(INCDIR)/libiberty.h unwind-ia64.h rename.o: rename.c ../bfd/bfd.h $(INCDIR)/ansidecl.h \ $(INCDIR)/symcat.h bucomm.h config.h $(INCDIR)/bin-bugs.h \ diff -uprN binutils-2.16.91.0.1/binutils/Makefile.in binutils-2.16.91.0.2/binutils/Makefile.in --- binutils-2.16.91.0.1/binutils/Makefile.in 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/binutils/Makefile.in 2005-07-20 12:27:27.504158255 -0700 @@ -436,14 +436,8 @@ BFDLIB = ../bfd/libbfd.la OPCODES = ../opcodes/libopcodes.la LIBIBERTY = ../libiberty/libiberty.a POTFILES = $(CFILES) $(DEBUG_SRCS) $(HFILES) -EXPECT = `if [ -f $$r/../expect/expect ] ; then \ - echo $$r/../expect/expect ; \ - else echo expect ; fi` - -RUNTEST = `if [ -f ${srcdir}/../dejagnu/runtest ] ; then \ - echo ${srcdir}/../dejagnu/runtest ; \ - else echo runtest ; fi` - +EXPECT = expect +RUNTEST = runtest CC_FOR_TARGET = ` \ if [ -f $$r/../gcc/xgcc ] ; then \ if [ -f $$r/../newlib/Makefile ] ; then \ @@ -950,10 +944,6 @@ check-DEJAGNU: site.exp srcdir=`cd $(srcdir) && pwd`; export srcdir; \ r=`pwd`; export r; \ EXPECT=$(EXPECT); export EXPECT; \ - if [ -f $(top_builddir)/../expect/expect ]; then \ - TCL_LIBRARY=`cd $(top_srcdir)/../tcl/library && pwd`; \ - export TCL_LIBRARY; \ - fi; \ runtest=$(RUNTEST); \ if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \ CC_FOR_TARGET="$(CC_FOR_TARGET)" CFLAGS_FOR_TARGET="$(CFLAGS)" \ @@ -1244,7 +1234,8 @@ readelf.o: readelf.c ../bfd/bfd.h $(INCD $(INCDIR)/elf/ppc64.h $(INCDIR)/elf/s390.h $(INCDIR)/elf/sh.h \ $(INCDIR)/elf/sparc.h $(INCDIR)/elf/v850.h $(INCDIR)/elf/vax.h \ $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/xstormy16.h $(INCDIR)/elf/crx.h \ - $(INCDIR)/elf/iq2000.h $(INCDIR)/elf/xtensa.h $(INCDIR)/aout/ar.h \ + $(INCDIR)/elf/iq2000.h $(INCDIR)/elf/xtensa.h $(INCDIR)/elf/m32c.h \ + $(INCDIR)/aout/ar.h \ bucomm.h config.h $(INCDIR)/bin-bugs.h $(INCDIR)/fopen-same.h \ $(INCDIR)/libiberty.h unwind-ia64.h rename.o: rename.c ../bfd/bfd.h $(INCDIR)/ansidecl.h \ diff -uprN binutils-2.16.91.0.1/binutils/objcopy.c binutils-2.16.91.0.2/binutils/objcopy.c --- binutils-2.16.91.0.1/binutils/objcopy.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/binutils/objcopy.c 2005-07-20 12:27:27.567147868 -0700 @@ -1290,7 +1290,15 @@ copy_object (bfd *ibfd, bfd *obfd) { flagword flags; - padd->section = bfd_make_section (obfd, padd->name); + pset = find_section_list (padd->name, FALSE); + if (pset != NULL) + pset->used = TRUE; + + flags = SEC_HAS_CONTENTS | SEC_READONLY | SEC_DATA; + if (pset != NULL && pset->set_flags) + flags = pset->flags | SEC_HAS_CONTENTS; + + padd->section = bfd_make_section_with_flags (obfd, padd->name, flags); if (padd->section == NULL) { non_fatal (_("can't create section `%s': %s"), @@ -1304,21 +1312,6 @@ copy_object (bfd *ibfd, bfd *obfd) return FALSE; } - pset = find_section_list (padd->name, FALSE); - if (pset != NULL) - pset->used = TRUE; - - if (pset != NULL && pset->set_flags) - flags = pset->flags | SEC_HAS_CONTENTS; - else - flags = SEC_HAS_CONTENTS | SEC_READONLY | SEC_DATA; - - if (! bfd_set_section_flags (obfd, padd->section, flags)) - { - bfd_nonfatal (bfd_get_filename (obfd)); - return FALSE; - } - if (pset != NULL) { if (pset->change_vma != CHANGE_IGNORE) @@ -2001,7 +1994,12 @@ setup_section (bfd *ibfd, sec_ptr isecti name = n; } - osection = bfd_make_section_anyway (obfd, name); + if (p != NULL && p->set_flags) + flags = p->flags | (flags & (SEC_HAS_CONTENTS | SEC_RELOC)); + else if (strip_symbols == STRIP_NONDEBUG && (flags & SEC_ALLOC) != 0) + flags &= ~(SEC_HAS_CONTENTS | SEC_LOAD); + + osection = bfd_make_section_anyway_with_flags (obfd, name, flags); if (osection == NULL) { @@ -2009,6 +2007,12 @@ setup_section (bfd *ibfd, sec_ptr isecti goto loser; } + if (strip_symbols == STRIP_NONDEBUG + && obfd->xvec->flavour == bfd_target_elf_flavour + && (flags & SEC_ALLOC) != 0 + && (p == NULL || !p->set_flags)) + elf_section_type (osection) = SHT_NOBITS; + size = bfd_section_size (ibfd, isection); if (copy_byte >= 0) size = (size + interleave - 1) / interleave; @@ -2057,21 +2061,6 @@ setup_section (bfd *ibfd, sec_ptr isecti goto loser; } - if (p != NULL && p->set_flags) - flags = p->flags | (flags & (SEC_HAS_CONTENTS | SEC_RELOC)); - else if (strip_symbols == STRIP_NONDEBUG && (flags & SEC_ALLOC) != 0) - { - flags &= ~(SEC_HAS_CONTENTS | SEC_LOAD); - if (obfd->xvec->flavour == bfd_target_elf_flavour) - elf_section_type (osection) = SHT_NOBITS; - } - - if (!bfd_set_section_flags (obfd, osection, flags)) - { - err = _("flags"); - goto loser; - } - /* Copy merge entity size. */ osection->entsize = isection->entsize; @@ -2353,28 +2342,22 @@ write_debugging_info (bfd *obfd, void *d bfd_byte *syms, *strings; bfd_size_type symsize, stringsize; asection *stabsec, *stabstrsec; + flagword flags; if (! write_stabs_in_sections_debugging_info (obfd, dhandle, &syms, &symsize, &strings, &stringsize)) return FALSE; - stabsec = bfd_make_section (obfd, ".stab"); - stabstrsec = bfd_make_section (obfd, ".stabstr"); + flags = SEC_HAS_CONTENTS | SEC_READONLY | SEC_DEBUGGING; + stabsec = bfd_make_section_with_flags (obfd, ".stab", flags); + stabstrsec = bfd_make_section_with_flags (obfd, ".stabstr", flags); if (stabsec == NULL || stabstrsec == NULL || ! bfd_set_section_size (obfd, stabsec, symsize) || ! bfd_set_section_size (obfd, stabstrsec, stringsize) || ! bfd_set_section_alignment (obfd, stabsec, 2) - || ! bfd_set_section_alignment (obfd, stabstrsec, 0) - || ! bfd_set_section_flags (obfd, stabsec, - (SEC_HAS_CONTENTS - | SEC_READONLY - | SEC_DEBUGGING)) - || ! bfd_set_section_flags (obfd, stabstrsec, - (SEC_HAS_CONTENTS - | SEC_READONLY - | SEC_DEBUGGING))) + || ! bfd_set_section_alignment (obfd, stabstrsec, 0)) { non_fatal (_("%s: can't create debugging section: %s"), bfd_get_filename (obfd), diff -uprN binutils-2.16.91.0.1/binutils/objdump.c binutils-2.16.91.0.2/binutils/objdump.c --- binutils-2.16.91.0.1/binutils/objdump.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/binutils/objdump.c 2005-07-20 12:27:27.570147374 -0700 @@ -65,7 +65,7 @@ #define BYTES_IN_WORD 32 #include "aout/aout64.h" -#ifdef NEED_DECLARATION_FPRINTF +#if !HAVE_DECL_FPRINTF /* This is needed by init_disassemble_info(). */ extern int fprintf (FILE *, const char *, ...); #endif @@ -1190,7 +1190,7 @@ typedef struct /* sprintf to a "stream". */ -static int +static int ATTRIBUTE_PRINTF_2 objdump_sprintf (SFILE *f, const char *format, ...) { size_t n; diff -uprN binutils-2.16.91.0.1/binutils/po/binutils.pot binutils-2.16.91.0.2/binutils/po/binutils.pot --- binutils-2.16.91.0.1/binutils/po/binutils.pot 2005-04-09 12:03:02.000000000 -0700 +++ binutils-2.16.91.0.2/binutils/po/binutils.pot 2005-07-20 12:27:27.607141273 -0700 @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2005-03-03 21:03+1030\n" +"POT-Creation-Date: 2005-07-11 09:31-0500\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -16,29 +16,30 @@ msgstr "" "Content-Type: text/plain; charset=CHARSET\n" "Content-Transfer-Encoding: 8bit\n" -#: addr2line.c:73 +#: addr2line.c:76 #, c-format msgid "Usage: %s [option(s)] [addr(s)]\n" msgstr "" -#: addr2line.c:74 +#: addr2line.c:77 #, c-format msgid " Convert addresses into line number/file name pairs.\n" msgstr "" -#: addr2line.c:75 +#: addr2line.c:78 #, c-format msgid "" " If no addresses are specified on the command line, they will be read from " "stdin\n" msgstr "" -#: addr2line.c:76 +#: addr2line.c:79 #, c-format msgid "" " The options are:\n" " -b --target= Set the binary file format\n" " -e --exe= Set the input file name (default is a.out)\n" +" -i --inlines\t\t Unwind inlined functions\n" " -s --basenames Strip directory names\n" " -f --functions Show function names\n" " -C --demangle[=style] Demangle function names\n" @@ -47,164 +48,164 @@ msgid "" "\n" msgstr "" -#: addr2line.c:88 ar.c:263 coffdump.c:467 nlmconv.c:1110 objcopy.c:478 -#: objcopy.c:512 readelf.c:2631 size.c:99 srconv.c:1731 strings.c:667 -#: sysdump.c:655 windres.c:672 +#: addr2line.c:92 ar.c:261 coffdump.c:465 nlmconv.c:1110 objcopy.c:485 +#: objcopy.c:519 readelf.c:2757 size.c:101 srconv.c:1731 strings.c:721 +#: sysdump.c:648 windres.c:672 #, c-format msgid "Report bugs to %s\n" msgstr "" -#: addr2line.c:241 +#: addr2line.c:252 #, c-format msgid "%s: can not get addresses from archive" msgstr "" -#: addr2line.c:311 nm.c:1519 objdump.c:2848 +#: addr2line.c:322 nm.c:1520 objdump.c:2858 #, c-format msgid "unknown demangling style `%s'" msgstr "" -#: ar.c:205 +#: ar.c:203 #, c-format msgid "no entry %s in archive\n" msgstr "" -#: ar.c:221 +#: ar.c:219 #, c-format msgid "" "Usage: %s [emulation options] [-]{dmpqrstx}[abcfilNoPsSuvV] [member-name] " "[count] archive-file file...\n" msgstr "" -#: ar.c:224 +#: ar.c:222 #, c-format msgid " %s -M [ \n" msgstr "" #. xgetext:c-format -#: dlltool.c:3067 +#: dlltool.c:3036 #, c-format msgid "" " -m --machine Create as DLL for . [default: %s]\n" msgstr "" -#: dlltool.c:3068 +#: dlltool.c:3037 #, c-format msgid "" " possible : arm[_interwork], i386, mcore[-elf]{-le|-be}, " "ppc, thumb\n" msgstr "" -#: dlltool.c:3069 +#: dlltool.c:3038 #, c-format msgid " -e --output-exp Generate an export file.\n" msgstr "" -#: dlltool.c:3070 +#: dlltool.c:3039 #, c-format msgid " -l --output-lib Generate an interface library.\n" msgstr "" -#: dlltool.c:3071 +#: dlltool.c:3040 #, c-format msgid " -a --add-indirect Add dll indirects to export file.\n" msgstr "" -#: dlltool.c:3072 +#: dlltool.c:3041 #, c-format msgid "" " -D --dllname Name of input dll to put into interface lib.\n" msgstr "" -#: dlltool.c:3073 +#: dlltool.c:3042 #, c-format msgid " -d --input-def Name of .def file to be read in.\n" msgstr "" -#: dlltool.c:3074 +#: dlltool.c:3043 #, c-format msgid " -z --output-def Name of .def file to be created.\n" msgstr "" -#: dlltool.c:3075 +#: dlltool.c:3044 #, c-format msgid " --export-all-symbols Export all symbols to .def\n" msgstr "" -#: dlltool.c:3076 +#: dlltool.c:3045 #, c-format msgid " --no-export-all-symbols Only export listed symbols\n" msgstr "" -#: dlltool.c:3077 +#: dlltool.c:3046 #, c-format msgid " --exclude-symbols Don't export \n" msgstr "" -#: dlltool.c:3078 +#: dlltool.c:3047 #, c-format msgid " --no-default-excludes Clear default exclude symbols\n" msgstr "" -#: dlltool.c:3079 +#: dlltool.c:3048 #, c-format msgid " -b --base-file Read linker generated base file.\n" msgstr "" -#: dlltool.c:3080 +#: dlltool.c:3049 #, c-format msgid " -x --no-idata4 Don't generate idata$4 section.\n" msgstr "" -#: dlltool.c:3081 +#: dlltool.c:3050 #, c-format msgid " -c --no-idata5 Don't generate idata$5 section.\n" msgstr "" -#: dlltool.c:3082 +#: dlltool.c:3051 #, c-format msgid "" " -U --add-underscore Add underscores to symbols in interface " "library.\n" msgstr "" -#: dlltool.c:3083 +#: dlltool.c:3052 #, c-format msgid " -k --kill-at Kill @ from exported names.\n" msgstr "" -#: dlltool.c:3084 +#: dlltool.c:3053 #, c-format msgid " -A --add-stdcall-alias Add aliases without @.\n" msgstr "" -#: dlltool.c:3085 +#: dlltool.c:3054 #, c-format msgid " -p --ext-prefix-alias Add aliases with .\n" msgstr "" -#: dlltool.c:3086 +#: dlltool.c:3055 #, c-format msgid " -S --as Use for assembler.\n" msgstr "" -#: dlltool.c:3087 +#: dlltool.c:3056 #, c-format msgid " -f --as-flags Pass to the assembler.\n" msgstr "" -#: dlltool.c:3088 +#: dlltool.c:3057 #, c-format msgid "" " -C --compat-implib Create backward compatible import library.\n" msgstr "" -#: dlltool.c:3089 +#: dlltool.c:3058 #, c-format msgid "" " -n --no-delete Keep temp files (repeat for extra " "preservation).\n" msgstr "" -#: dlltool.c:3090 +#: dlltool.c:3059 #, c-format msgid "" " -t --temp-prefix Use to construct temp file names.\n" msgstr "" -#: dlltool.c:3091 +#: dlltool.c:3060 #, c-format msgid " -v --verbose Be verbose.\n" msgstr "" -#: dlltool.c:3092 +#: dlltool.c:3061 #, c-format msgid " -V --version Display the program version.\n" msgstr "" -#: dlltool.c:3093 +#: dlltool.c:3062 #, c-format msgid " -h --help Display this information.\n" msgstr "" -#: dlltool.c:3095 +#: dlltool.c:3064 #, c-format msgid "" " -M --mcore-elf Process mcore-elf object files into .\n" msgstr "" -#: dlltool.c:3096 +#: dlltool.c:3065 #, c-format msgid " -L --linker Use as the linker.\n" msgstr "" -#: dlltool.c:3097 +#: dlltool.c:3066 #, c-format msgid " -F --linker-flags Pass to the linker.\n" msgstr "" -#: dlltool.c:3211 +#: dlltool.c:3180 #, c-format msgid "Path components stripped from dllname, '%s'." msgstr "" -#: dlltool.c:3256 +#: dlltool.c:3225 #, c-format msgid "Unable to open base-file: %s" msgstr "" -#: dlltool.c:3288 +#: dlltool.c:3257 #, c-format msgid "Machine '%s' not supported" msgstr "" -#: dlltool.c:3392 dllwrap.c:209 +#: dlltool.c:3361 dllwrap.c:204 #, c-format msgid "Tried file: %s" msgstr "" -#: dlltool.c:3399 dllwrap.c:216 +#: dlltool.c:3368 dllwrap.c:211 #, c-format msgid "Using file: %s" msgstr "" -#: dllwrap.c:299 +#: dllwrap.c:294 #, c-format msgid "Keeping temporary base file %s" msgstr "" -#: dllwrap.c:301 +#: dllwrap.c:296 #, c-format msgid "Deleting temporary base file %s" msgstr "" -#: dllwrap.c:315 +#: dllwrap.c:310 #, c-format msgid "Keeping temporary exp file %s" msgstr "" -#: dllwrap.c:317 +#: dllwrap.c:312 #, c-format msgid "Deleting temporary exp file %s" msgstr "" -#: dllwrap.c:330 +#: dllwrap.c:325 #, c-format msgid "Keeping temporary def file %s" msgstr "" -#: dllwrap.c:332 +#: dllwrap.c:327 #, c-format msgid "Deleting temporary def file %s" msgstr "" -#: dllwrap.c:480 +#: dllwrap.c:475 #, c-format msgid " Generic options:\n" msgstr "" -#: dllwrap.c:481 +#: dllwrap.c:476 #, c-format msgid " --quiet, -q Work quietly\n" msgstr "" -#: dllwrap.c:482 +#: dllwrap.c:477 #, c-format msgid " --verbose, -v Verbose\n" msgstr "" -#: dllwrap.c:483 +#: dllwrap.c:478 #, c-format msgid " --version Print dllwrap version\n" msgstr "" -#: dllwrap.c:484 +#: dllwrap.c:479 #, c-format msgid " --implib Synonym for --output-lib\n" msgstr "" -#: dllwrap.c:485 +#: dllwrap.c:480 #, c-format msgid " Options for %s:\n" msgstr "" -#: dllwrap.c:486 +#: dllwrap.c:481 #, c-format msgid " --driver-name Defaults to \"gcc\"\n" msgstr "" -#: dllwrap.c:487 +#: dllwrap.c:482 #, c-format msgid " --driver-flags Override default ld flags\n" msgstr "" -#: dllwrap.c:488 +#: dllwrap.c:483 #, c-format msgid " --dlltool-name Defaults to \"dlltool\"\n" msgstr "" -#: dllwrap.c:489 +#: dllwrap.c:484 #, c-format msgid " --entry Specify alternate DLL entry point\n" msgstr "" -#: dllwrap.c:490 +#: dllwrap.c:485 #, c-format msgid " --image-base Specify image base address\n" msgstr "" -#: dllwrap.c:491 +#: dllwrap.c:486 #, c-format msgid " --target i386-cygwin32 or i386-mingw32\n" msgstr "" -#: dllwrap.c:492 +#: dllwrap.c:487 #, c-format msgid " --dry-run Show what needs to be run\n" msgstr "" -#: dllwrap.c:493 +#: dllwrap.c:488 #, c-format msgid " --mno-cygwin Create Mingw DLL\n" msgstr "" -#: dllwrap.c:494 +#: dllwrap.c:489 #, c-format msgid " Options passed to DLLTOOL:\n" msgstr "" -#: dllwrap.c:495 +#: dllwrap.c:490 #, c-format msgid " --machine \n" msgstr "" -#: dllwrap.c:496 +#: dllwrap.c:491 #, c-format msgid " --output-exp Generate export file.\n" msgstr "" -#: dllwrap.c:497 +#: dllwrap.c:492 #, c-format msgid " --output-lib Generate input library.\n" msgstr "" -#: dllwrap.c:498 +#: dllwrap.c:493 #, c-format msgid " --add-indirect Add dll indirects to export file.\n" msgstr "" -#: dllwrap.c:499 +#: dllwrap.c:494 #, c-format msgid " --dllname Name of input dll to put into output lib.\n" msgstr "" -#: dllwrap.c:500 +#: dllwrap.c:495 #, c-format msgid " --def Name input .def file\n" msgstr "" -#: dllwrap.c:501 +#: dllwrap.c:496 #, c-format msgid " --output-def Name output .def file\n" msgstr "" -#: dllwrap.c:502 +#: dllwrap.c:497 #, c-format msgid " --export-all-symbols Export all symbols to .def\n" msgstr "" -#: dllwrap.c:503 +#: dllwrap.c:498 #, c-format msgid " --no-export-all-symbols Only export .drectve symbols\n" msgstr "" -#: dllwrap.c:504 +#: dllwrap.c:499 #, c-format msgid " --exclude-symbols Exclude from .def\n" msgstr "" -#: dllwrap.c:505 +#: dllwrap.c:500 #, c-format msgid " --no-default-excludes Zap default exclude symbols\n" msgstr "" -#: dllwrap.c:506 +#: dllwrap.c:501 #, c-format msgid " --base-file Read linker generated base file\n" msgstr "" -#: dllwrap.c:507 +#: dllwrap.c:502 #, c-format msgid " --no-idata4 Don't generate idata$4 section\n" msgstr "" -#: dllwrap.c:508 +#: dllwrap.c:503 #, c-format msgid " --no-idata5 Don't generate idata$5 section\n" msgstr "" -#: dllwrap.c:509 +#: dllwrap.c:504 #, c-format msgid " -U Add underscores to .lib\n" msgstr "" -#: dllwrap.c:510 +#: dllwrap.c:505 #, c-format msgid " -k Kill @ from exported names\n" msgstr "" -#: dllwrap.c:511 +#: dllwrap.c:506 #, c-format msgid " --add-stdcall-alias Add aliases without @\n" msgstr "" -#: dllwrap.c:512 +#: dllwrap.c:507 #, c-format msgid " --as Use for assembler\n" msgstr "" -#: dllwrap.c:513 +#: dllwrap.c:508 #, c-format msgid " --nodelete Keep temp files.\n" msgstr "" -#: dllwrap.c:514 +#: dllwrap.c:509 #, c-format msgid " Rest are passed unmodified to the language driver\n" msgstr "" -#: dllwrap.c:784 +#: dllwrap.c:779 msgid "Must provide at least one of -o or --dllname options" msgstr "" -#: dllwrap.c:813 +#: dllwrap.c:808 msgid "" "no export definition file provided.\n" "Creating one, but that may not be what you want" msgstr "" -#: dllwrap.c:972 +#: dllwrap.c:967 #, c-format msgid "DLLTOOL name : %s\n" msgstr "" -#: dllwrap.c:973 +#: dllwrap.c:968 #, c-format msgid "DLLTOOL options : %s\n" msgstr "" -#: dllwrap.c:974 +#: dllwrap.c:969 #, c-format msgid "DRIVER name : %s\n" msgstr "" -#: dllwrap.c:975 +#: dllwrap.c:970 #, c-format msgid "DRIVER options : %s\n" msgstr "" @@ -1576,7 +1577,7 @@ msgstr "" msgid "Execution of %s failed" msgstr "" -#: nm.c:224 size.c:80 strings.c:651 +#: nm.c:224 size.c:82 strings.c:705 #, c-format msgid "Usage: %s [option(s)] [file(s)]\n" msgstr "" @@ -1644,17 +1645,17 @@ msgstr "" msgid "%s: invalid output format" msgstr "" -#: nm.c:339 readelf.c:6342 readelf.c:6378 +#: nm.c:339 readelf.c:6617 readelf.c:6653 #, c-format msgid ": %d" msgstr "" -#: nm.c:341 readelf.c:6345 readelf.c:6390 +#: nm.c:341 readelf.c:6620 readelf.c:6665 #, c-format msgid ": %d" msgstr "" -#: nm.c:343 readelf.c:6347 readelf.c:6393 +#: nm.c:343 readelf.c:6622 readelf.c:6668 #, c-format msgid ": %d" msgstr "" @@ -1666,7 +1667,7 @@ msgid "" "Archive index:\n" msgstr "" -#: nm.c:1225 +#: nm.c:1226 #, c-format msgid "" "\n" @@ -1675,7 +1676,7 @@ msgid "" "\n" msgstr "" -#: nm.c:1227 +#: nm.c:1228 #, c-format msgid "" "\n" @@ -1684,7 +1685,7 @@ msgid "" "\n" msgstr "" -#: nm.c:1229 nm.c:1280 +#: nm.c:1230 nm.c:1281 #, c-format msgid "" "Name Value Class Type Size Line " @@ -1692,7 +1693,7 @@ msgid "" "\n" msgstr "" -#: nm.c:1232 nm.c:1283 +#: nm.c:1233 nm.c:1284 #, c-format msgid "" "Name Value Class Type " @@ -1700,7 +1701,7 @@ msgid "" "\n" msgstr "" -#: nm.c:1276 +#: nm.c:1277 #, c-format msgid "" "\n" @@ -1709,7 +1710,7 @@ msgid "" "\n" msgstr "" -#: nm.c:1278 +#: nm.c:1279 #, c-format msgid "" "\n" @@ -1718,39 +1719,39 @@ msgid "" "\n" msgstr "" -#: nm.c:1580 +#: nm.c:1581 msgid "Only -X 32_64 is supported" msgstr "" -#: nm.c:1600 +#: nm.c:1601 msgid "Using the --size-sort and --undefined-only options together" msgstr "" -#: nm.c:1601 +#: nm.c:1602 msgid "will produce no output, since undefined symbols have no size." msgstr "" -#: nm.c:1629 +#: nm.c:1630 #, c-format msgid "data size %ld" msgstr "" -#: objcopy.c:396 srconv.c:1721 +#: objcopy.c:401 srconv.c:1721 #, c-format msgid "Usage: %s [option(s)] in-file [out-file]\n" msgstr "" -#: objcopy.c:397 +#: objcopy.c:402 #, c-format msgid " Copies a binary file, possibly transforming it in the process\n" msgstr "" -#: objcopy.c:398 objcopy.c:487 +#: objcopy.c:403 objcopy.c:494 #, c-format msgid " The options are:\n" msgstr "" -#: objcopy.c:399 +#: objcopy.c:404 #, c-format msgid "" " -I --input-target Assume input file is in format \n" @@ -1780,9 +1781,11 @@ msgid "" " relocations\n" " --only-keep-debug Strip everything but the debug " "information\n" -" -K --keep-symbol Only copy symbol \n" +" -K --keep-symbol Do not strip symbol \n" " -L --localize-symbol Force symbol to be marked as a " "local\n" +" --globalize-symbol Force symbol to be marked as a " +"global\n" " -G --keep-global-symbol Localize all symbols except \n" " -W --weaken-symbol Force symbol to be marked as a " "weak\n" @@ -1839,6 +1842,7 @@ msgid "" " in \n" " --keep-symbols -K for all symbols listed in \n" " --localize-symbols -L for all symbols listed in \n" +" --globalize-symbols --globalize-symbol for all in \n" " --keep-global-symbols -G for all symbols listed in \n" " --weaken-symbols -W for all symbols listed in \n" " --alt-machine-code Use alternate machine code for output\n" @@ -1861,17 +1865,17 @@ msgid "" "supported\n" msgstr "" -#: objcopy.c:485 +#: objcopy.c:492 #, c-format msgid "Usage: %s in-file(s)\n" msgstr "" -#: objcopy.c:486 +#: objcopy.c:493 #, c-format msgid " Removes symbols and sections from files\n" msgstr "" -#: objcopy.c:488 +#: objcopy.c:495 #, c-format msgid "" " -I --input-target= Assume input file is in format \n" @@ -1890,7 +1894,7 @@ msgid "" " --only-keep-debug Strip everything but the debug " "information\n" " -N --strip-symbol= Do not copy symbol \n" -" -K --keep-symbol= Only copy symbol \n" +" -K --keep-symbol= Do not strip symbol \n" " -w --wildcard Permit wildcard in symbol comparison\n" " -x --discard-all Remove all non-global symbols\n" " -X --discard-locals Remove any compiler-generated symbols\n" @@ -1902,229 +1906,240 @@ msgid "" " -o Place stripped output into \n" msgstr "" -#: objcopy.c:560 +#: objcopy.c:567 #, c-format msgid "unrecognized section flag `%s'" msgstr "" -#: objcopy.c:561 +#: objcopy.c:568 #, c-format msgid "supported flags: %s" msgstr "" -#: objcopy.c:638 +#: objcopy.c:645 #, c-format msgid "cannot open '%s': %s" msgstr "" -#: objcopy.c:641 objcopy.c:2629 +#: objcopy.c:648 objcopy.c:2721 #, c-format msgid "%s: fread failed" msgstr "" -#: objcopy.c:714 +#: objcopy.c:721 #, c-format msgid "%s:%d: Ignoring rubbish found on this line" msgstr "" -#: objcopy.c:976 +#: objcopy.c:995 #, c-format msgid "%s: Multiple redefinition of symbol \"%s\"" msgstr "" -#: objcopy.c:980 +#: objcopy.c:999 #, c-format msgid "%s: Symbol \"%s\" is target of more than one redefinition" msgstr "" -#: objcopy.c:1008 +#: objcopy.c:1027 #, c-format msgid "couldn't open symbol redefinition file %s (error: %s)" msgstr "" -#: objcopy.c:1086 +#: objcopy.c:1105 #, c-format msgid "%s:%d: garbage found at end of line" msgstr "" -#: objcopy.c:1089 +#: objcopy.c:1108 #, c-format msgid "%s:%d: missing new symbol name" msgstr "" -#: objcopy.c:1099 +#: objcopy.c:1118 #, c-format msgid "%s:%d: premature end of file" msgstr "" -#: objcopy.c:1124 +#: objcopy.c:1144 +#, c-format +msgid "stat returns negative size for `%s'" +msgstr "" + +#: objcopy.c:1156 +#, c-format +msgid "copy from `%s' [unknown] to `%s' [unknown]\n" +msgstr "" + +#: objcopy.c:1211 msgid "Unable to change endianness of input file(s)" msgstr "" -#: objcopy.c:1133 +#: objcopy.c:1220 #, c-format -msgid "copy from %s(%s) to %s(%s)\n" +msgid "copy from `%s' [%s] to `%s' [%s]\n" msgstr "" -#: objcopy.c:1170 +#: objcopy.c:1257 objcopy.c:1714 #, c-format -msgid "Unable to recognise the format of the input file %s" +msgid "Unable to recognise the format of the input file `%s'" msgstr "" -#: objcopy.c:1174 +#: objcopy.c:1260 #, c-format -msgid "Warning: Output file cannot represent architecture %s" +msgid "Warning: Output file cannot represent architecture `%s'" msgstr "" -#: objcopy.c:1211 +#: objcopy.c:1304 #, c-format msgid "can't create section `%s': %s" msgstr "" -#: objcopy.c:1277 +#: objcopy.c:1355 msgid "there are no sections to be copied!" msgstr "" -#: objcopy.c:1323 +#: objcopy.c:1401 #, c-format msgid "Can't fill gap after %s: %s" msgstr "" -#: objcopy.c:1348 +#: objcopy.c:1426 #, c-format msgid "Can't add padding to %s: %s" msgstr "" -#: objcopy.c:1514 +#: objcopy.c:1593 #, c-format msgid "%s: error copying private BFD data: %s" msgstr "" -#: objcopy.c:1525 +#: objcopy.c:1604 msgid "unknown alternate machine code, ignored" msgstr "" -#: objcopy.c:1555 objcopy.c:1585 +#: objcopy.c:1634 objcopy.c:1664 #, c-format msgid "cannot mkdir %s for archive copying (error: %s)" msgstr "" -#: objcopy.c:1790 +#: objcopy.c:1786 +#, c-format +msgid "error: the input file '%s' is empty" +msgstr "" + +#: objcopy.c:1888 #, c-format msgid "Multiple renames of section %s" msgstr "" -#: objcopy.c:1841 +#: objcopy.c:1939 msgid "private header data" msgstr "" -#: objcopy.c:1849 +#: objcopy.c:1947 #, c-format msgid "%s: error in %s: %s" msgstr "" -#: objcopy.c:1903 +#: objcopy.c:2006 msgid "making" msgstr "" -#: objcopy.c:1912 +#: objcopy.c:2021 msgid "size" msgstr "" -#: objcopy.c:1926 +#: objcopy.c:2035 msgid "vma" msgstr "" -#: objcopy.c:1951 +#: objcopy.c:2060 msgid "alignment" msgstr "" -#: objcopy.c:1966 -msgid "flags" -msgstr "" - -#: objcopy.c:1988 +#: objcopy.c:2082 msgid "private data" msgstr "" -#: objcopy.c:1996 +#: objcopy.c:2090 #, c-format msgid "%s: section `%s': error in %s: %s" msgstr "" -#: objcopy.c:2274 +#: objcopy.c:2362 #, c-format msgid "%s: can't create debugging section: %s" msgstr "" -#: objcopy.c:2288 +#: objcopy.c:2376 #, c-format msgid "%s: can't set debugging section contents: %s" msgstr "" -#: objcopy.c:2297 +#: objcopy.c:2385 #, c-format msgid "%s: don't know how to write debugging information for %s" msgstr "" -#: objcopy.c:2472 +#: objcopy.c:2560 msgid "byte number must be non-negative" msgstr "" -#: objcopy.c:2482 +#: objcopy.c:2570 msgid "interleave must be positive" msgstr "" -#: objcopy.c:2502 objcopy.c:2510 +#: objcopy.c:2590 objcopy.c:2598 #, c-format msgid "%s both copied and removed" msgstr "" -#: objcopy.c:2603 objcopy.c:2674 objcopy.c:2774 objcopy.c:2805 objcopy.c:2829 -#: objcopy.c:2833 objcopy.c:2853 +#: objcopy.c:2695 objcopy.c:2766 objcopy.c:2866 objcopy.c:2897 objcopy.c:2921 +#: objcopy.c:2925 objcopy.c:2945 #, c-format msgid "bad format for %s" msgstr "" -#: objcopy.c:2624 +#: objcopy.c:2716 #, c-format msgid "cannot open: %s: %s" msgstr "" -#: objcopy.c:2743 +#: objcopy.c:2835 #, c-format msgid "Warning: truncating gap-fill from 0x%s to 0x%x" msgstr "" -#: objcopy.c:2903 +#: objcopy.c:2999 msgid "alternate machine code index must be positive" msgstr "" -#: objcopy.c:2961 +#: objcopy.c:3057 msgid "byte number must be less than interleave" msgstr "" -#: objcopy.c:2991 +#: objcopy.c:3087 #, c-format msgid "architecture %s unknown" msgstr "" -#: objcopy.c:2995 +#: objcopy.c:3091 msgid "" "Warning: input target 'binary' required for binary architecture parameter." msgstr "" -#: objcopy.c:2996 +#: objcopy.c:3092 #, c-format msgid " Argument %s ignored" msgstr "" -#: objcopy.c:3002 +#: objcopy.c:3098 #, c-format msgid "warning: could not locate '%s'. System error message: %s" msgstr "" -#: objcopy.c:3042 objcopy.c:3056 +#: objcopy.c:3140 objcopy.c:3154 #, c-format msgid "%s %s%c0x%s never used" msgstr "" @@ -2216,131 +2231,131 @@ msgid "" "\n" msgstr "" -#: objdump.c:378 +#: objdump.c:384 #, c-format msgid "Sections:\n" msgstr "" -#: objdump.c:381 objdump.c:385 +#: objdump.c:387 objdump.c:391 #, c-format msgid "Idx Name Size VMA LMA File off Algn" msgstr "" -#: objdump.c:387 +#: objdump.c:393 #, c-format msgid "" "Idx Name Size VMA LMA File off " "Algn" msgstr "" -#: objdump.c:391 +#: objdump.c:397 #, c-format msgid " Flags" msgstr "" -#: objdump.c:393 +#: objdump.c:399 #, c-format msgid " Pg" msgstr "" -#: objdump.c:436 +#: objdump.c:442 #, c-format msgid "%s: not a dynamic object" msgstr "" -#: objdump.c:1722 +#: objdump.c:1733 #, c-format msgid "Disassembly of section %s:\n" msgstr "" -#: objdump.c:1884 +#: objdump.c:1895 #, c-format msgid "Can't use supplied machine %s" msgstr "" -#: objdump.c:1903 +#: objdump.c:1914 #, c-format msgid "Can't disassemble for architecture %s\n" msgstr "" -#: objdump.c:1973 +#: objdump.c:1984 #, c-format msgid "" "No %s section present\n" "\n" msgstr "" -#: objdump.c:1982 +#: objdump.c:1993 #, c-format msgid "Reading %s section of %s failed: %s" msgstr "" -#: objdump.c:2026 +#: objdump.c:2037 #, c-format msgid "" "Contents of %s section:\n" "\n" msgstr "" -#: objdump.c:2153 +#: objdump.c:2164 #, c-format msgid "architecture: %s, " msgstr "" -#: objdump.c:2156 +#: objdump.c:2167 #, c-format msgid "flags 0x%08x:\n" msgstr "" -#: objdump.c:2170 +#: objdump.c:2181 #, c-format msgid "" "\n" "start address 0x" msgstr "" -#: objdump.c:2210 +#: objdump.c:2221 #, c-format msgid "Contents of section %s:\n" msgstr "" -#: objdump.c:2335 +#: objdump.c:2346 #, c-format msgid "no symbols\n" msgstr "" -#: objdump.c:2342 +#: objdump.c:2353 #, c-format msgid "no information for symbol number %ld\n" msgstr "" -#: objdump.c:2345 +#: objdump.c:2356 #, c-format msgid "could not determine the type of symbol number %ld\n" msgstr "" -#: objdump.c:2611 +#: objdump.c:2621 #, c-format msgid "" "\n" "%s: file format %s\n" msgstr "" -#: objdump.c:2662 +#: objdump.c:2672 #, c-format msgid "%s: printing debugging information failed" msgstr "" -#: objdump.c:2753 +#: objdump.c:2763 #, c-format msgid "In archive %s:\n" msgstr "" -#: objdump.c:2873 +#: objdump.c:2883 msgid "unrecognized -E option" msgstr "" -#: objdump.c:2884 +#: objdump.c:2894 #, c-format msgid "unrecognized --endian type `%s'" msgstr "" @@ -2380,186 +2395,191 @@ msgstr "" msgid "Last stabs entries before error:\n" msgstr "" -#: readelf.c:272 +#: readelf.c:274 #, c-format msgid "%s: Error: " msgstr "" -#: readelf.c:283 +#: readelf.c:285 #, c-format msgid "%s: Warning: " msgstr "" -#: readelf.c:298 +#: readelf.c:331 #, c-format -msgid "Unable to seek to 0x%x for %s\n" +msgid "Unable to seek to 0x%lx for %s\n" msgstr "" -#: readelf.c:310 +#: readelf.c:346 #, c-format -msgid "Out of memory allocating 0x%x bytes for %s\n" +msgid "Out of memory allocating 0x%lx bytes for %s\n" msgstr "" -#: readelf.c:318 +#: readelf.c:356 #, c-format -msgid "Unable to read in 0x%x bytes of %s\n" +msgid "Unable to read in 0x%lx bytes of %s\n" msgstr "" -#: readelf.c:364 readelf.c:412 readelf.c:615 readelf.c:647 +#: readelf.c:403 readelf.c:451 readelf.c:654 readelf.c:686 #, c-format msgid "Unhandled data length: %d\n" msgstr "" -#: readelf.c:752 +#: readelf.c:793 msgid "Don't know about relocations on this machine architecture\n" msgstr "" -#: readelf.c:772 readelf.c:799 readelf.c:842 readelf.c:869 +#: readelf.c:813 readelf.c:841 readelf.c:885 readelf.c:913 msgid "relocs" msgstr "" -#: readelf.c:782 readelf.c:809 readelf.c:852 readelf.c:879 +#: readelf.c:824 readelf.c:852 readelf.c:896 readelf.c:924 msgid "out of memory parsing relocs" msgstr "" -#: readelf.c:933 +#: readelf.c:978 #, c-format msgid "" " Offset Info Type Sym. Value Symbol's Name + Addend\n" msgstr "" -#: readelf.c:935 +#: readelf.c:980 #, c-format msgid " Offset Info Type Sym.Value Sym. Name + Addend\n" msgstr "" -#: readelf.c:940 +#: readelf.c:985 #, c-format msgid " Offset Info Type Sym. Value Symbol's Name\n" msgstr "" -#: readelf.c:942 +#: readelf.c:987 #, c-format msgid " Offset Info Type Sym.Value Sym. Name\n" msgstr "" -#: readelf.c:950 +#: readelf.c:995 #, c-format msgid "" " Offset Info Type Symbol's Value " "Symbol's Name + Addend\n" msgstr "" -#: readelf.c:952 +#: readelf.c:997 #, c-format msgid "" " Offset Info Type Sym. Value Sym. Name + " "Addend\n" msgstr "" -#: readelf.c:957 +#: readelf.c:1002 #, c-format msgid "" " Offset Info Type Symbol's Value " "Symbol's Name\n" msgstr "" -#: readelf.c:959 +#: readelf.c:1004 #, c-format msgid "" " Offset Info Type Sym. Value Sym. Name\n" msgstr "" -#: readelf.c:1239 readelf.c:1241 readelf.c:1324 readelf.c:1326 readelf.c:1335 -#: readelf.c:1337 +#: readelf.c:1292 readelf.c:1294 readelf.c:1400 readelf.c:1402 readelf.c:1411 +#: readelf.c:1413 #, c-format msgid "unrecognized: %-7lx" msgstr "" -#: readelf.c:1295 +#: readelf.c:1319 +#, c-format +msgid "" +msgstr "" + +#: readelf.c:1372 #, c-format msgid "" msgstr "" -#: readelf.c:1297 +#: readelf.c:1374 #, c-format msgid "" msgstr "" -#: readelf.c:1569 +#: readelf.c:1673 #, c-format msgid "Processor Specific: %lx" msgstr "" -#: readelf.c:1588 +#: readelf.c:1692 #, c-format msgid "Operating System specific: %lx" msgstr "" -#: readelf.c:1592 readelf.c:2370 +#: readelf.c:1696 readelf.c:2493 #, c-format msgid ": %lx" msgstr "" -#: readelf.c:1605 +#: readelf.c:1709 msgid "NONE (None)" msgstr "" -#: readelf.c:1606 +#: readelf.c:1710 msgid "REL (Relocatable file)" msgstr "" -#: readelf.c:1607 +#: readelf.c:1711 msgid "EXEC (Executable file)" msgstr "" -#: readelf.c:1608 +#: readelf.c:1712 msgid "DYN (Shared object file)" msgstr "" -#: readelf.c:1609 +#: readelf.c:1713 msgid "CORE (Core file)" msgstr "" -#: readelf.c:1613 +#: readelf.c:1717 #, c-format msgid "Processor Specific: (%x)" msgstr "" -#: readelf.c:1615 +#: readelf.c:1719 #, c-format msgid "OS Specific: (%x)" msgstr "" -#: readelf.c:1617 readelf.c:1724 readelf.c:2554 +#: readelf.c:1721 readelf.c:1830 readelf.c:2677 #, c-format msgid ": %x" msgstr "" -#: readelf.c:1629 +#: readelf.c:1733 msgid "None" msgstr "" -#: readelf.c:2229 +#: readelf.c:2335 msgid "Standalone App" msgstr "" -#: readelf.c:2232 readelf.c:2952 readelf.c:2968 +#: readelf.c:2338 readelf.c:3081 readelf.c:3097 #, c-format msgid "" msgstr "" -#: readelf.c:2597 +#: readelf.c:2721 #, c-format msgid "Usage: readelf elf-file(s)\n" msgstr "" -#: readelf.c:2598 +#: readelf.c:2722 #, c-format msgid " Display information about the contents of ELF format files\n" msgstr "" -#: readelf.c:2599 +#: readelf.c:2723 #, c-format msgid "" " Options are:\n" @@ -2570,6 +2590,8 @@ msgid "" " -S --section-headers Display the sections' header\n" " --sections An alias for --section-headers\n" " -g --section-groups Display the section groups\n" +" -N --full-section-name\n" +" Display the full section name\n" " -e --headers Equivalent to: -h -l -S\n" " -s --syms Display the symbol table\n" " --symbols An alias for --syms\n" @@ -2589,14 +2611,14 @@ msgid "" " Display the contents of DWARF2 debug sections\n" msgstr "" -#: readelf.c:2622 +#: readelf.c:2748 #, c-format msgid "" " -i --instruction-dump=\n" " Disassemble the contents of section \n" msgstr "" -#: readelf.c:2626 +#: readelf.c:2752 #, c-format msgid "" " -I --histogram Display histogram of bucket list lengths\n" @@ -2605,348 +2627,379 @@ msgid "" " -v --version Display the version number of readelf\n" msgstr "" -#: readelf.c:2651 readelf.c:12118 +#: readelf.c:2777 readelf.c:12469 msgid "Out of memory allocating dump request table." msgstr "" -#: readelf.c:2820 readelf.c:2888 +#: readelf.c:2949 readelf.c:3017 #, c-format msgid "Unrecognized debug option '%s'\n" msgstr "" -#: readelf.c:2922 +#: readelf.c:3051 #, c-format msgid "Invalid option '-%c'\n" msgstr "" -#: readelf.c:2936 +#: readelf.c:3065 msgid "Nothing to do.\n" msgstr "" -#: readelf.c:2948 readelf.c:2964 readelf.c:5906 +#: readelf.c:3077 readelf.c:3093 readelf.c:6163 msgid "none" msgstr "" -#: readelf.c:2965 +#: readelf.c:3094 msgid "2's complement, little endian" msgstr "" -#: readelf.c:2966 +#: readelf.c:3095 msgid "2's complement, big endian" msgstr "" -#: readelf.c:2984 +#: readelf.c:3113 msgid "Not an ELF file - it has the wrong magic bytes at the start\n" msgstr "" -#: readelf.c:2992 +#: readelf.c:3121 #, c-format msgid "ELF Header:\n" msgstr "" -#: readelf.c:2993 +#: readelf.c:3122 #, c-format msgid " Magic: " msgstr "" -#: readelf.c:2997 +#: readelf.c:3126 #, c-format msgid " Class: %s\n" msgstr "" -#: readelf.c:2999 +#: readelf.c:3128 #, c-format msgid " Data: %s\n" msgstr "" -#: readelf.c:3001 +#: readelf.c:3130 #, c-format msgid " Version: %d %s\n" msgstr "" -#: readelf.c:3008 +#: readelf.c:3137 #, c-format msgid " OS/ABI: %s\n" msgstr "" -#: readelf.c:3010 +#: readelf.c:3139 #, c-format msgid " ABI Version: %d\n" msgstr "" -#: readelf.c:3012 +#: readelf.c:3141 #, c-format msgid " Type: %s\n" msgstr "" -#: readelf.c:3014 +#: readelf.c:3143 #, c-format msgid " Machine: %s\n" msgstr "" -#: readelf.c:3016 +#: readelf.c:3145 #, c-format msgid " Version: 0x%lx\n" msgstr "" -#: readelf.c:3019 +#: readelf.c:3148 #, c-format msgid " Entry point address: " msgstr "" -#: readelf.c:3021 +#: readelf.c:3150 #, c-format msgid "" "\n" " Start of program headers: " msgstr "" -#: readelf.c:3023 +#: readelf.c:3152 #, c-format msgid "" " (bytes into file)\n" " Start of section headers: " msgstr "" -#: readelf.c:3025 +#: readelf.c:3154 #, c-format msgid " (bytes into file)\n" msgstr "" -#: readelf.c:3027 +#: readelf.c:3156 #, c-format msgid " Flags: 0x%lx%s\n" msgstr "" -#: readelf.c:3030 +#: readelf.c:3159 #, c-format msgid " Size of this header: %ld (bytes)\n" msgstr "" -#: readelf.c:3032 +#: readelf.c:3161 #, c-format msgid " Size of program headers: %ld (bytes)\n" msgstr "" -#: readelf.c:3034 +#: readelf.c:3163 #, c-format msgid " Number of program headers: %ld\n" msgstr "" -#: readelf.c:3036 +#: readelf.c:3165 #, c-format msgid " Size of section headers: %ld (bytes)\n" msgstr "" -#: readelf.c:3038 +#: readelf.c:3167 #, c-format msgid " Number of section headers: %ld" msgstr "" -#: readelf.c:3043 +#: readelf.c:3172 #, c-format msgid " Section header string table index: %ld" msgstr "" -#: readelf.c:3074 readelf.c:3107 +#: readelf.c:3203 readelf.c:3236 msgid "program headers" msgstr "" -#: readelf.c:3145 readelf.c:3446 readelf.c:3487 readelf.c:3546 readelf.c:3609 -#: readelf.c:3993 readelf.c:4017 readelf.c:5247 readelf.c:5291 readelf.c:5489 -#: readelf.c:6450 readelf.c:6464 readelf.c:11493 readelf.c:11912 -#: readelf.c:11979 +#: readelf.c:3274 readelf.c:3573 readelf.c:3614 readelf.c:3673 readelf.c:3736 +#: readelf.c:4205 readelf.c:4229 readelf.c:5504 readelf.c:5548 readelf.c:5746 +#: readelf.c:6725 readelf.c:6739 readelf.c:11844 readelf.c:12263 +#: readelf.c:12330 msgid "Out of memory\n" msgstr "" -#: readelf.c:3172 +#: readelf.c:3301 #, c-format msgid "" "\n" "There are no program headers in this file.\n" msgstr "" -#: readelf.c:3178 +#: readelf.c:3307 #, c-format msgid "" "\n" "Elf file type is %s\n" msgstr "" -#: readelf.c:3179 +#: readelf.c:3308 #, c-format msgid "Entry point " msgstr "" -#: readelf.c:3181 +#: readelf.c:3310 #, c-format msgid "" "\n" "There are %d program headers, starting at offset " msgstr "" -#: readelf.c:3193 readelf.c:3195 +#: readelf.c:3322 readelf.c:3324 #, c-format msgid "" "\n" "Program Headers:\n" msgstr "" -#: readelf.c:3199 +#: readelf.c:3328 #, c-format msgid "" " Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align\n" msgstr "" -#: readelf.c:3202 +#: readelf.c:3331 #, c-format msgid "" " Type Offset VirtAddr PhysAddr FileSiz " "MemSiz Flg Align\n" msgstr "" -#: readelf.c:3206 +#: readelf.c:3335 #, c-format msgid " Type Offset VirtAddr PhysAddr\n" msgstr "" -#: readelf.c:3208 +#: readelf.c:3337 #, c-format msgid " FileSiz MemSiz Flags Align\n" msgstr "" -#: readelf.c:3301 +#: readelf.c:3430 msgid "more than one dynamic segment\n" msgstr "" -#: readelf.c:3312 +#: readelf.c:3441 msgid "no .dynamic section in the dynamic segment" msgstr "" -#: readelf.c:3321 +#: readelf.c:3450 msgid "the .dynamic section is not contained within the dynamic segment" msgstr "" -#: readelf.c:3323 +#: readelf.c:3452 msgid "the .dynamic section is not the first section in the dynamic segment." msgstr "" -#: readelf.c:3337 +#: readelf.c:3466 msgid "Unable to find program interpreter name\n" msgstr "" -#: readelf.c:3344 +#: readelf.c:3473 #, c-format msgid "" "\n" " [Requesting program interpreter: %s]" msgstr "" -#: readelf.c:3356 +#: readelf.c:3485 #, c-format msgid "" "\n" " Section to Segment mapping:\n" msgstr "" -#: readelf.c:3357 +#: readelf.c:3486 #, c-format msgid " Segment Sections...\n" msgstr "" -#: readelf.c:3408 +#: readelf.c:3535 msgid "Cannot interpret virtual addresses without program headers.\n" msgstr "" -#: readelf.c:3424 +#: readelf.c:3551 #, c-format msgid "Virtual address 0x%lx not located in any PT_LOAD segment.\n" msgstr "" -#: readelf.c:3438 readelf.c:3479 +#: readelf.c:3565 readelf.c:3606 msgid "section headers" msgstr "" -#: readelf.c:3523 readelf.c:3586 +#: readelf.c:3650 readelf.c:3713 msgid "symbols" msgstr "" -#: readelf.c:3533 readelf.c:3596 +#: readelf.c:3660 readelf.c:3723 msgid "symtab shndx" msgstr "" -#: readelf.c:3697 readelf.c:3977 +#: readelf.c:3824 readelf.c:4189 #, c-format msgid "" "\n" "There are no sections in this file.\n" msgstr "" -#: readelf.c:3703 +#: readelf.c:3830 #, c-format msgid "There are %d section headers, starting at offset 0x%lx:\n" msgstr "" -#: readelf.c:3720 readelf.c:4079 readelf.c:4290 readelf.c:4591 readelf.c:5011 -#: readelf.c:6618 +#: readelf.c:3849 readelf.c:4306 readelf.c:4541 readelf.c:4844 readelf.c:5267 +#: readelf.c:6897 msgid "string table" msgstr "" -#: readelf.c:3765 +#: readelf.c:3888 +#, c-format +msgid "Section %d has invalid sh_entsize %lx (expected %lx)\n" +msgstr "" + +#: readelf.c:3908 msgid "File contains multiple dynamic symbol tables\n" msgstr "" -#: readelf.c:3777 +#: readelf.c:3921 msgid "File contains multiple dynamic string tables\n" msgstr "" -#: readelf.c:3782 +#: readelf.c:3926 msgid "dynamic strings" msgstr "" -#: readelf.c:3789 +#: readelf.c:3933 msgid "File contains multiple symtab shndx tables\n" msgstr "" -#: readelf.c:3828 +#: readelf.c:3980 #, c-format msgid "" "\n" "Section Headers:\n" msgstr "" -#: readelf.c:3830 +#: readelf.c:3982 #, c-format msgid "" "\n" "Section Header:\n" msgstr "" -#: readelf.c:3834 +#: readelf.c:3988 readelf.c:3999 readelf.c:4010 +#, c-format +msgid " [Nr] Name\n" +msgstr "" + +#: readelf.c:3989 +#, c-format +msgid " Type Addr Off Size ES Flg Lk Inf Al\n" +msgstr "" + +#: readelf.c:3993 #, c-format msgid "" " [Nr] Name Type Addr Off Size ES Flg Lk " "Inf Al\n" msgstr "" -#: readelf.c:3837 +#: readelf.c:4000 +#, c-format +msgid "" +" Type Address Off Size ES Flg Lk Inf Al\n" +msgstr "" + +#: readelf.c:4004 #, c-format msgid "" " [Nr] Name Type Address Off Size ES " "Flg Lk Inf Al\n" msgstr "" -#: readelf.c:3840 +#: readelf.c:4011 +#, c-format +msgid " Flags Type Address Offset\n" +msgstr "" + +#: readelf.c:4012 +#, c-format +msgid " Size EntSize Link Info Align\n" +msgstr "" + +#: readelf.c:4016 #, c-format msgid " [Nr] Name Type Address Offset\n" msgstr "" -#: readelf.c:3841 +#: readelf.c:4017 #, c-format msgid " Size EntSize Flags Link Info Align\n" msgstr "" -#: readelf.c:3936 +#: readelf.c:4147 #, c-format msgid "" "Key to Flags:\n" @@ -2955,753 +3008,767 @@ msgid "" " O (extra OS processing required) o (OS specific), p (processor specific)\n" msgstr "" -#: readelf.c:3954 +#: readelf.c:4165 #, c-format msgid "[: 0x%x]" msgstr "" -#: readelf.c:3984 +#: readelf.c:4196 msgid "Section headers are not available!\n" msgstr "" -#: readelf.c:4008 +#: readelf.c:4220 #, c-format msgid "" "\n" "There are no section groups in this file.\n" msgstr "" -#: readelf.c:4042 +#: readelf.c:4256 #, c-format msgid "Bad sh_link in group section `%s'\n" msgstr "" -#: readelf.c:4061 +#: readelf.c:4275 #, c-format msgid "Bad sh_info in group section `%s'\n" msgstr "" -#: readelf.c:4085 readelf.c:6947 +#: readelf.c:4314 readelf.c:7234 msgid "section data" msgstr "" -#: readelf.c:4097 +#: readelf.c:4326 #, c-format msgid " [Index] Name\n" msgstr "" -#: readelf.c:4114 +#: readelf.c:4340 #, c-format -msgid "section [%5u] already in group section [%5u]\n" +msgid "section [%5u] in group section [%5u] > maximum section [%5u]\n" msgstr "" -#: readelf.c:4127 +#: readelf.c:4346 +#, c-format +msgid "invalid section [%5u] in group section [%5u]\n" +msgstr "" + +#: readelf.c:4356 +#, c-format +msgid "section [%5u] in group section [%5u] already in group section [%5u]\n" +msgstr "" + +#: readelf.c:4369 #, c-format msgid "section 0 in group section [%5u]\n" msgstr "" -#: readelf.c:4224 +#: readelf.c:4465 #, c-format msgid "" "\n" "'%s' relocation section at offset 0x%lx contains %ld bytes:\n" msgstr "" -#: readelf.c:4236 +#: readelf.c:4477 #, c-format msgid "" "\n" "There are no dynamic relocations in this file.\n" msgstr "" -#: readelf.c:4260 +#: readelf.c:4501 #, c-format msgid "" "\n" "Relocation section " msgstr "" -#: readelf.c:4265 readelf.c:4666 readelf.c:4680 readelf.c:5025 +#: readelf.c:4506 readelf.c:4920 readelf.c:4934 readelf.c:5282 #, c-format msgid "'%s'" msgstr "" -#: readelf.c:4267 readelf.c:4682 readelf.c:5027 +#: readelf.c:4508 readelf.c:4936 readelf.c:5284 #, c-format msgid " at offset 0x%lx contains %lu entries:\n" msgstr "" -#: readelf.c:4308 +#: readelf.c:4560 #, c-format msgid "" "\n" "There are no relocations in this file.\n" msgstr "" -#: readelf.c:4482 readelf.c:4862 +#: readelf.c:4734 readelf.c:5116 msgid "unwind table" msgstr "" -#: readelf.c:4540 readelf.c:4959 +#: readelf.c:4793 readelf.c:5214 #, c-format msgid "Skipping unexpected relocation type %s\n" msgstr "" -#: readelf.c:4598 readelf.c:5018 readelf.c:5069 +#: readelf.c:4852 readelf.c:5275 readelf.c:5326 #, c-format msgid "" "\n" "There are no unwind sections in this file.\n" msgstr "" -#: readelf.c:4661 +#: readelf.c:4915 #, c-format msgid "" "\n" "Could not find unwind info section for " msgstr "" -#: readelf.c:4673 +#: readelf.c:4927 msgid "unwind info" msgstr "" -#: readelf.c:4675 readelf.c:5024 +#: readelf.c:4929 readelf.c:5281 #, c-format msgid "" "\n" "Unwind section " msgstr "" -#: readelf.c:5228 readelf.c:5272 +#: readelf.c:5485 readelf.c:5529 msgid "dynamic section" msgstr "" -#: readelf.c:5349 +#: readelf.c:5606 #, c-format msgid "" "\n" "There is no dynamic section in this file.\n" msgstr "" -#: readelf.c:5387 +#: readelf.c:5644 msgid "Unable to seek to end of file!" msgstr "" -#: readelf.c:5400 +#: readelf.c:5657 msgid "Unable to determine the number of symbols to load\n" msgstr "" -#: readelf.c:5435 +#: readelf.c:5692 msgid "Unable to seek to end of file\n" msgstr "" -#: readelf.c:5442 +#: readelf.c:5699 msgid "Unable to determine the length of the dynamic string table\n" msgstr "" -#: readelf.c:5447 +#: readelf.c:5704 msgid "dynamic string table" msgstr "" -#: readelf.c:5482 +#: readelf.c:5739 msgid "symbol information" msgstr "" -#: readelf.c:5507 +#: readelf.c:5764 #, c-format msgid "" "\n" "Dynamic section at offset 0x%lx contains %u entries:\n" msgstr "" -#: readelf.c:5510 +#: readelf.c:5767 #, c-format msgid " Tag Type Name/Value\n" msgstr "" -#: readelf.c:5546 +#: readelf.c:5803 #, c-format msgid "Auxiliary library" msgstr "" -#: readelf.c:5550 +#: readelf.c:5807 #, c-format msgid "Filter library" msgstr "" -#: readelf.c:5554 +#: readelf.c:5811 #, c-format msgid "Configuration file" msgstr "" -#: readelf.c:5558 +#: readelf.c:5815 #, c-format msgid "Dependency audit library" msgstr "" -#: readelf.c:5562 +#: readelf.c:5819 #, c-format msgid "Audit library" msgstr "" -#: readelf.c:5580 readelf.c:5608 readelf.c:5636 +#: readelf.c:5837 readelf.c:5865 readelf.c:5893 #, c-format msgid "Flags:" msgstr "" -#: readelf.c:5583 readelf.c:5611 readelf.c:5638 +#: readelf.c:5840 readelf.c:5868 readelf.c:5895 #, c-format msgid " None\n" msgstr "" -#: readelf.c:5759 +#: readelf.c:6016 #, c-format msgid "Shared library: [%s]" msgstr "" -#: readelf.c:5762 +#: readelf.c:6019 #, c-format msgid " program interpreter" msgstr "" -#: readelf.c:5766 +#: readelf.c:6023 #, c-format msgid "Library soname: [%s]" msgstr "" -#: readelf.c:5770 +#: readelf.c:6027 #, c-format msgid "Library rpath: [%s]" msgstr "" -#: readelf.c:5774 +#: readelf.c:6031 #, c-format msgid "Library runpath: [%s]" msgstr "" -#: readelf.c:5837 +#: readelf.c:6094 #, c-format msgid "Not needed object: [%s]\n" msgstr "" -#: readelf.c:5951 +#: readelf.c:6208 #, c-format msgid "" "\n" "Version definition section '%s' contains %ld entries:\n" msgstr "" -#: readelf.c:5954 +#: readelf.c:6211 #, c-format msgid " Addr: 0x" msgstr "" -#: readelf.c:5956 readelf.c:6148 +#: readelf.c:6213 readelf.c:6420 #, c-format msgid " Offset: %#08lx Link: %lx (%s)\n" msgstr "" -#: readelf.c:5961 +#: readelf.c:6222 msgid "version definition section" msgstr "" -#: readelf.c:5987 +#: readelf.c:6248 #, c-format msgid " %#06x: Rev: %d Flags: %s" msgstr "" -#: readelf.c:5990 +#: readelf.c:6251 #, c-format msgid " Index: %d Cnt: %d " msgstr "" -#: readelf.c:6001 +#: readelf.c:6262 #, c-format msgid "Name: %s\n" msgstr "" -#: readelf.c:6003 +#: readelf.c:6264 #, c-format msgid "Name index: %ld\n" msgstr "" -#: readelf.c:6018 +#: readelf.c:6279 #, c-format msgid " %#06x: Parent %d: %s\n" msgstr "" -#: readelf.c:6021 +#: readelf.c:6282 #, c-format msgid " %#06x: Parent %d, name index: %ld\n" msgstr "" -#: readelf.c:6040 +#: readelf.c:6301 #, c-format msgid "" "\n" "Version needs section '%s' contains %ld entries:\n" msgstr "" -#: readelf.c:6043 +#: readelf.c:6304 #, c-format msgid " Addr: 0x" msgstr "" -#: readelf.c:6045 +#: readelf.c:6306 #, c-format msgid " Offset: %#08lx Link to section: %ld (%s)\n" msgstr "" -#: readelf.c:6050 +#: readelf.c:6315 msgid "version need section" msgstr "" -#: readelf.c:6072 +#: readelf.c:6337 #, c-format msgid " %#06x: Version: %d" msgstr "" -#: readelf.c:6075 +#: readelf.c:6340 #, c-format msgid " File: %s" msgstr "" -#: readelf.c:6077 +#: readelf.c:6342 #, c-format msgid " File: %lx" msgstr "" -#: readelf.c:6079 +#: readelf.c:6344 #, c-format msgid " Cnt: %d\n" msgstr "" -#: readelf.c:6097 +#: readelf.c:6362 #, c-format msgid " %#06x: Name: %s" msgstr "" -#: readelf.c:6100 +#: readelf.c:6365 #, c-format msgid " %#06x: Name index: %lx" msgstr "" -#: readelf.c:6103 +#: readelf.c:6368 #, c-format msgid " Flags: %s Version: %d\n" msgstr "" -#: readelf.c:6139 +#: readelf.c:6411 msgid "version string table" msgstr "" -#: readelf.c:6143 +#: readelf.c:6415 #, c-format msgid "" "\n" "Version symbols section '%s' contains %d entries:\n" msgstr "" -#: readelf.c:6146 +#: readelf.c:6418 #, c-format msgid " Addr: " msgstr "" -#: readelf.c:6156 +#: readelf.c:6428 msgid "version symbol data" msgstr "" -#: readelf.c:6183 +#: readelf.c:6455 msgid " 0 (*local*) " msgstr "" -#: readelf.c:6187 +#: readelf.c:6459 msgid " 1 (*global*) " msgstr "" -#: readelf.c:6223 readelf.c:6677 +#: readelf.c:6497 readelf.c:6960 msgid "version need" msgstr "" -#: readelf.c:6233 +#: readelf.c:6507 msgid "version need aux (2)" msgstr "" -#: readelf.c:6275 readelf.c:6740 +#: readelf.c:6549 readelf.c:7025 msgid "version def" msgstr "" -#: readelf.c:6294 readelf.c:6755 +#: readelf.c:6569 readelf.c:7040 msgid "version def aux" msgstr "" -#: readelf.c:6325 +#: readelf.c:6600 #, c-format msgid "" "\n" "No version information found in this file.\n" msgstr "" -#: readelf.c:6456 +#: readelf.c:6731 msgid "Unable to read in dynamic data\n" msgstr "" -#: readelf.c:6509 +#: readelf.c:6784 msgid "Unable to seek to start of dynamic information" msgstr "" -#: readelf.c:6515 +#: readelf.c:6790 msgid "Failed to read in number of buckets\n" msgstr "" -#: readelf.c:6521 +#: readelf.c:6796 msgid "Failed to read in number of chains\n" msgstr "" -#: readelf.c:6541 +#: readelf.c:6816 #, c-format msgid "" "\n" "Symbol table for image:\n" msgstr "" -#: readelf.c:6543 +#: readelf.c:6818 #, c-format msgid " Num Buc: Value Size Type Bind Vis Ndx Name\n" msgstr "" -#: readelf.c:6545 +#: readelf.c:6820 #, c-format msgid " Num Buc: Value Size Type Bind Vis Ndx Name\n" msgstr "" -#: readelf.c:6597 +#: readelf.c:6873 #, c-format msgid "" "\n" "Symbol table '%s' contains %lu entries:\n" msgstr "" -#: readelf.c:6601 +#: readelf.c:6877 #, c-format msgid " Num: Value Size Type Bind Vis Ndx Name\n" msgstr "" -#: readelf.c:6603 +#: readelf.c:6879 #, c-format msgid " Num: Value Size Type Bind Vis Ndx Name\n" msgstr "" -#: readelf.c:6649 +#: readelf.c:6930 msgid "version data" msgstr "" -#: readelf.c:6690 +#: readelf.c:6973 msgid "version need aux (3)" msgstr "" -#: readelf.c:6715 +#: readelf.c:7000 msgid "bad dynamic symbol" msgstr "" -#: readelf.c:6778 +#: readelf.c:7064 #, c-format msgid "" "\n" "Dynamic symbol information is not available for displaying symbols.\n" msgstr "" -#: readelf.c:6790 +#: readelf.c:7076 #, c-format msgid "" "\n" "Histogram for bucket list length (total of %lu buckets):\n" msgstr "" -#: readelf.c:6792 +#: readelf.c:7078 #, c-format msgid " Length Number %% of total Coverage\n" msgstr "" -#: readelf.c:6797 readelf.c:6813 readelf.c:10967 readelf.c:11159 +#: readelf.c:7083 readelf.c:7099 readelf.c:11311 readelf.c:11503 msgid "Out of memory" msgstr "" -#: readelf.c:6862 +#: readelf.c:7148 #, c-format msgid "" "\n" "Dynamic info segment at offset 0x%lx contains %d entries:\n" msgstr "" -#: readelf.c:6865 +#: readelf.c:7151 #, c-format msgid " Num: Name BoundTo Flags\n" msgstr "" -#: readelf.c:6917 +#: readelf.c:7203 #, c-format msgid "" "\n" "Assembly dump of section %s\n" msgstr "" -#: readelf.c:6938 +#: readelf.c:7224 #, c-format msgid "" "\n" "Section '%s' has no data to dump.\n" msgstr "" -#: readelf.c:6943 +#: readelf.c:7229 #, c-format msgid "" "\n" "Hex dump of section '%s':\n" msgstr "" -#: readelf.c:7090 +#: readelf.c:7377 msgid "badly formed extended line op encountered!\n" msgstr "" -#: readelf.c:7097 +#: readelf.c:7384 #, c-format msgid " Extended opcode %d: " msgstr "" -#: readelf.c:7102 +#: readelf.c:7389 #, c-format msgid "" "End of Sequence\n" "\n" msgstr "" -#: readelf.c:7108 +#: readelf.c:7395 #, c-format msgid "set Address to 0x%lx\n" msgstr "" -#: readelf.c:7113 +#: readelf.c:7400 #, c-format msgid " define new File Table entry\n" msgstr "" -#: readelf.c:7114 readelf.c:9032 +#: readelf.c:7401 readelf.c:9340 #, c-format msgid " Entry\tDir\tTime\tSize\tName\n" msgstr "" -#: readelf.c:7116 +#: readelf.c:7403 #, c-format msgid " %d\t" msgstr "" -#: readelf.c:7119 readelf.c:7121 readelf.c:7123 readelf.c:9044 readelf.c:9046 -#: readelf.c:9048 +#: readelf.c:7406 readelf.c:7408 readelf.c:7410 readelf.c:9352 readelf.c:9354 +#: readelf.c:9356 #, c-format msgid "%lu\t" msgstr "" -#: readelf.c:7124 +#: readelf.c:7411 #, c-format msgid "" "%s\n" "\n" msgstr "" -#: readelf.c:7128 +#: readelf.c:7415 #, c-format msgid "UNKNOWN: length %d\n" msgstr "" -#: readelf.c:7155 +#: readelf.c:7442 msgid "debug_str section data" msgstr "" -#: readelf.c:7173 +#: readelf.c:7460 msgid "" msgstr "" -#: readelf.c:7176 +#: readelf.c:7464 +#, c-format +msgid "DW_FORM_strp offset too big: %lx\n" +msgstr "" + +#: readelf.c:7465 msgid "" msgstr "" -#: readelf.c:7201 +#: readelf.c:7491 msgid "debug_loc section data" msgstr "" -#: readelf.c:7235 +#: readelf.c:7525 msgid "debug_range section data" msgstr "" -#: readelf.c:7307 +#: readelf.c:7599 #, c-format -msgid "" -"%s: skipping unexpected symbol type %s in relocation in section .rela%s\n" +msgid "skipping unexpected symbol type %s in relocation in section .rela%s\n" msgstr "" -#: readelf.c:7321 +#: readelf.c:7625 #, c-format msgid "skipping unexpected symbol type %s in relocation in section .rela.%s\n" msgstr "" -#: readelf.c:7565 +#: readelf.c:7869 #, c-format msgid "Unknown TAG value: %lx" msgstr "" -#: readelf.c:7601 +#: readelf.c:7905 #, c-format msgid "Unknown FORM value: %lx" msgstr "" -#: readelf.c:7610 +#: readelf.c:7914 #, c-format msgid " %lu byte block: " msgstr "" -#: readelf.c:7944 +#: readelf.c:8248 #, c-format msgid "(User defined location op)" msgstr "" -#: readelf.c:7946 +#: readelf.c:8250 #, c-format msgid "(Unknown location op)" msgstr "" -#: readelf.c:8015 +#: readelf.c:8319 msgid "Internal error: DWARF version is not 2 or 3.\n" msgstr "" -#: readelf.c:8113 +#: readelf.c:8417 msgid "DW_FORM_data8 is unsupported when sizeof (unsigned long) != 8\n" msgstr "" -#: readelf.c:8162 +#: readelf.c:8466 #, c-format msgid " (indirect string, offset: 0x%lx): %s" msgstr "" -#: readelf.c:8171 +#: readelf.c:8475 #, c-format -msgid "Unrecognized form: %d\n" +msgid "Unrecognized form: %lu\n" msgstr "" -#: readelf.c:8256 +#: readelf.c:8560 #, c-format msgid "(not inlined)" msgstr "" -#: readelf.c:8259 +#: readelf.c:8563 #, c-format msgid "(inlined)" msgstr "" -#: readelf.c:8262 +#: readelf.c:8566 #, c-format msgid "(declared as inline but ignored)" msgstr "" -#: readelf.c:8265 +#: readelf.c:8569 #, c-format msgid "(declared as inline and inlined)" msgstr "" -#: readelf.c:8268 +#: readelf.c:8572 #, c-format msgid " (Unknown inline attribute value: %lx)" msgstr "" -#: readelf.c:8413 readelf.c:9537 +#: readelf.c:8719 readelf.c:9879 #, c-format msgid " [without DW_AT_frame_base]" msgstr "" -#: readelf.c:8416 +#: readelf.c:8722 #, c-format msgid "(location list)" msgstr "" -#: readelf.c:8534 +#: readelf.c:8840 #, c-format msgid "Unknown AT value: %lx" msgstr "" -#: readelf.c:8602 +#: readelf.c:8908 msgid "No comp units in .debug_info section ?" msgstr "" -#: readelf.c:8611 +#: readelf.c:8917 #, c-format msgid "Not enough memory for a debug info array of %u entries" msgstr "" -#: readelf.c:8619 readelf.c:9630 +#: readelf.c:8925 readelf.c:9972 #, c-format msgid "" "The section %s contains:\n" "\n" msgstr "" -#: readelf.c:8693 +#: readelf.c:8999 #, c-format -msgid " Compilation Unit @ %lx:\n" +msgid " Compilation Unit @ offset 0x%lx:\n" msgstr "" -#: readelf.c:8694 +#: readelf.c:9000 #, c-format msgid " Length: %ld\n" msgstr "" -#: readelf.c:8695 +#: readelf.c:9001 #, c-format msgid " Version: %d\n" msgstr "" -#: readelf.c:8696 +#: readelf.c:9002 #, c-format msgid " Abbrev Offset: %ld\n" msgstr "" -#: readelf.c:8697 +#: readelf.c:9003 #, c-format msgid " Pointer Size: %d\n" msgstr "" -#: readelf.c:8702 +#: readelf.c:9008 msgid "Only version 2 and 3 DWARF debug information is currently supported.\n" msgstr "" -#: readelf.c:8717 +#: readelf.c:9023 msgid "Unable to locate .debug_abbrev section!\n" msgstr "" -#: readelf.c:8722 +#: readelf.c:9028 msgid "debug_abbrev section data" msgstr "" -#: readelf.c:8759 +#: readelf.c:9065 #, c-format msgid "Unable to locate entry %lu in the abbreviation table\n" msgstr "" -#: readelf.c:8765 +#: readelf.c:9071 #, c-format msgid " <%d><%lx>: Abbrev Number: %lu (%s)\n" msgstr "" -#: readelf.c:8838 +#: readelf.c:9144 #, c-format msgid "%s section needs a populated .debug_info section\n" msgstr "" -#: readelf.c:8845 +#: readelf.c:9151 #, c-format msgid "%s section has more comp units than .debug_info section\n" msgstr "" -#: readelf.c:8847 +#: readelf.c:9153 #, c-format msgid "" "assuming that the pointer size is %d, from the last comp unit in ." @@ -3709,11 +3776,11 @@ msgid "" "\n" msgstr "" -#: readelf.c:8891 +#: readelf.c:9197 msgid "extracting information from .debug_info section" msgstr "" -#: readelf.c:8909 +#: readelf.c:9215 #, c-format msgid "" "\n" @@ -3721,284 +3788,288 @@ msgid "" "\n" msgstr "" -#: readelf.c:8948 +#: readelf.c:9254 msgid "The line info appears to be corrupt - the section is too small\n" msgstr "" -#: readelf.c:8957 +#: readelf.c:9263 msgid "Only DWARF version 2 and 3 line info is currently supported.\n" msgstr "" -#: readelf.c:8984 +#: readelf.c:9290 #, c-format msgid " Length: %ld\n" msgstr "" -#: readelf.c:8985 +#: readelf.c:9291 #, c-format msgid " DWARF Version: %d\n" msgstr "" -#: readelf.c:8986 +#: readelf.c:9292 #, c-format msgid " Prologue Length: %d\n" msgstr "" -#: readelf.c:8987 +#: readelf.c:9293 #, c-format msgid " Minimum Instruction Length: %d\n" msgstr "" -#: readelf.c:8988 +#: readelf.c:9294 #, c-format msgid " Initial value of 'is_stmt': %d\n" msgstr "" -#: readelf.c:8989 +#: readelf.c:9295 #, c-format msgid " Line Base: %d\n" msgstr "" -#: readelf.c:8990 +#: readelf.c:9296 #, c-format msgid " Line Range: %d\n" msgstr "" -#: readelf.c:8991 +#: readelf.c:9297 #, c-format msgid " Opcode Base: %d\n" msgstr "" -#: readelf.c:8992 +#: readelf.c:9298 #, c-format -msgid " (Pointer size: %u)\n" +msgid " (Pointer size: %u)%s\n" msgstr "" -#: readelf.c:9001 +#: readelf.c:9309 #, c-format msgid "" "\n" " Opcodes:\n" msgstr "" -#: readelf.c:9004 +#: readelf.c:9312 #, c-format msgid " Opcode %d has %d args\n" msgstr "" -#: readelf.c:9010 +#: readelf.c:9318 #, c-format msgid "" "\n" " The Directory Table is empty.\n" msgstr "" -#: readelf.c:9013 +#: readelf.c:9321 #, c-format msgid "" "\n" " The Directory Table:\n" msgstr "" -#: readelf.c:9017 +#: readelf.c:9325 #, c-format msgid " %s\n" msgstr "" -#: readelf.c:9028 +#: readelf.c:9336 #, c-format msgid "" "\n" " The File Name Table is empty.\n" msgstr "" -#: readelf.c:9031 +#: readelf.c:9339 #, c-format msgid "" "\n" " The File Name Table:\n" msgstr "" -#: readelf.c:9039 +#: readelf.c:9347 #, c-format msgid " %d\t" msgstr "" -#: readelf.c:9050 +#: readelf.c:9358 #, c-format msgid "%s\n" msgstr "" #. Now display the statements. -#: readelf.c:9058 +#: readelf.c:9366 #, c-format msgid "" "\n" " Line Number Statements:\n" msgstr "" -#: readelf.c:9073 +#: readelf.c:9381 #, c-format msgid " Special opcode %d: advance Address by %d to 0x%lx" msgstr "" -#: readelf.c:9077 +#: readelf.c:9385 #, c-format msgid " and Line by %d to %d\n" msgstr "" -#: readelf.c:9088 +#: readelf.c:9393 +msgid "Extend line ops need a valid pointer size, guessing at 4\n" +msgstr "" + +#: readelf.c:9402 #, c-format msgid " Copy\n" msgstr "" -#: readelf.c:9095 +#: readelf.c:9409 #, c-format msgid " Advance PC by %d to %lx\n" msgstr "" -#: readelf.c:9103 +#: readelf.c:9417 #, c-format msgid " Advance Line by %d to %d\n" msgstr "" -#: readelf.c:9110 +#: readelf.c:9424 #, c-format msgid " Set File Name to entry %d in the File Name Table\n" msgstr "" -#: readelf.c:9118 +#: readelf.c:9432 #, c-format msgid " Set column to %d\n" msgstr "" -#: readelf.c:9125 +#: readelf.c:9439 #, c-format msgid " Set is_stmt to %d\n" msgstr "" -#: readelf.c:9130 +#: readelf.c:9444 #, c-format msgid " Set basic block\n" msgstr "" -#: readelf.c:9138 +#: readelf.c:9452 #, c-format msgid " Advance PC by constant %d to 0x%lx\n" msgstr "" -#: readelf.c:9146 +#: readelf.c:9460 #, c-format msgid " Advance PC by fixed size amount %d to 0x%lx\n" msgstr "" -#: readelf.c:9151 +#: readelf.c:9465 #, c-format msgid " Set prologue_end to true\n" msgstr "" -#: readelf.c:9155 +#: readelf.c:9469 #, c-format msgid " Set epilogue_begin to true\n" msgstr "" -#: readelf.c:9161 +#: readelf.c:9475 #, c-format msgid " Set ISA to %d\n" msgstr "" -#: readelf.c:9165 +#: readelf.c:9479 #, c-format msgid " Unknown opcode %d with operands: " msgstr "" -#: readelf.c:9193 readelf.c:9279 readelf.c:9354 +#: readelf.c:9507 readelf.c:9593 readelf.c:9668 #, c-format msgid "" "Contents of the %s section:\n" "\n" msgstr "" -#: readelf.c:9233 +#: readelf.c:9547 msgid "Only DWARF 2 and 3 pubnames are currently supported\n" msgstr "" -#: readelf.c:9240 +#: readelf.c:9554 #, c-format msgid " Length: %ld\n" msgstr "" -#: readelf.c:9242 +#: readelf.c:9556 #, c-format msgid " Version: %d\n" msgstr "" -#: readelf.c:9244 +#: readelf.c:9558 #, c-format msgid " Offset into .debug_info section: %ld\n" msgstr "" -#: readelf.c:9246 +#: readelf.c:9560 #, c-format msgid " Size of area in .debug_info section: %ld\n" msgstr "" -#: readelf.c:9249 +#: readelf.c:9563 #, c-format msgid "" "\n" " Offset\tName\n" msgstr "" -#: readelf.c:9300 +#: readelf.c:9614 #, c-format msgid " DW_MACINFO_start_file - lineno: %d filenum: %d\n" msgstr "" -#: readelf.c:9306 +#: readelf.c:9620 #, c-format msgid " DW_MACINFO_end_file\n" msgstr "" -#: readelf.c:9314 +#: readelf.c:9628 #, c-format msgid " DW_MACINFO_define - lineno : %d macro : %s\n" msgstr "" -#: readelf.c:9323 +#: readelf.c:9637 #, c-format msgid " DW_MACINFO_undef - lineno : %d macro : %s\n" msgstr "" -#: readelf.c:9335 +#: readelf.c:9649 #, c-format msgid " DW_MACINFO_vendor_ext - constant : %d string : %s\n" msgstr "" -#: readelf.c:9363 +#: readelf.c:9677 #, c-format msgid " Number TAG\n" msgstr "" -#: readelf.c:9369 +#: readelf.c:9683 #, c-format msgid " %ld %s [%s]\n" msgstr "" -#: readelf.c:9372 +#: readelf.c:9686 msgid "has children" msgstr "" -#: readelf.c:9372 +#: readelf.c:9686 msgid "no children" msgstr "" -#: readelf.c:9375 +#: readelf.c:9689 #, c-format msgid " %-18s %s\n" msgstr "" -#: readelf.c:9410 +#: readelf.c:9724 #, c-format msgid "" "\n" @@ -4006,105 +4077,120 @@ msgid "" msgstr "" #. FIXME: Should we handle this case? -#: readelf.c:9455 +#: readelf.c:9769 msgid "Location lists in .debug_info section aren't in ascending order!\n" msgstr "" -#: readelf.c:9458 +#: readelf.c:9772 msgid "No location lists in .debug_info section!\n" msgstr "" -#: readelf.c:9461 +#: readelf.c:9775 #, c-format msgid "Location lists in .debug_loc section start at 0x%lx\n" msgstr "" -#: readelf.c:9464 +#: readelf.c:9778 #, c-format msgid "" "Contents of the .debug_loc section:\n" "\n" msgstr "" -#: readelf.c:9465 +#: readelf.c:9779 #, c-format msgid " Offset Begin End Expression\n" msgstr "" -#: readelf.c:9495 +#: readelf.c:9809 #, c-format msgid "There is a hole [0x%lx - 0x%lx] in .debug_loc section.\n" msgstr "" -#: readelf.c:9498 +#: readelf.c:9812 #, c-format msgid "There is an overlap [0x%lx - 0x%lx] in .debug_loc section.\n" msgstr "" -#: readelf.c:9512 readelf.c:9837 +#: readelf.c:9819 +#, c-format +msgid "Offset 0x%lx is bigger than .debug_loc section size.\n" +msgstr "" + +#: readelf.c:9828 readelf.c:9855 readelf.c:9865 +#, c-format +msgid "Location list starting at offset 0x%lx is not terminated.\n" +msgstr "" + +#: readelf.c:9840 readelf.c:10179 #, c-format msgid " %8.8lx \n" msgstr "" -#: readelf.c:9540 readelf.c:9854 +#: readelf.c:9848 +#, c-format +msgid " %8.8lx %8.8lx %8.8lx (base address)\n" +msgstr "" + +#: readelf.c:9882 readelf.c:10196 msgid " (start == end)" msgstr "" -#: readelf.c:9542 readelf.c:9856 +#: readelf.c:9884 readelf.c:10198 msgid " (start > end)" msgstr "" -#: readelf.c:9566 +#: readelf.c:9908 #, c-format msgid "" "\n" "The .debug_str section is empty.\n" msgstr "" -#: readelf.c:9570 +#: readelf.c:9912 #, c-format msgid "" "Contents of the .debug_str section:\n" "\n" msgstr "" -#: readelf.c:9675 +#: readelf.c:10017 msgid "Only DWARF 2 and 3 aranges are currently supported.\n" msgstr "" -#: readelf.c:9679 +#: readelf.c:10021 #, c-format msgid " Length: %ld\n" msgstr "" -#: readelf.c:9680 +#: readelf.c:10022 #, c-format msgid " Version: %d\n" msgstr "" -#: readelf.c:9681 +#: readelf.c:10023 #, c-format msgid " Offset into .debug_info: %lx\n" msgstr "" -#: readelf.c:9682 +#: readelf.c:10024 #, c-format msgid " Pointer Size: %d\n" msgstr "" -#: readelf.c:9683 +#: readelf.c:10025 #, c-format msgid " Segment Size: %d\n" msgstr "" -#: readelf.c:9685 +#: readelf.c:10027 #, c-format msgid "" "\n" " Address Length\n" msgstr "" -#: readelf.c:9741 +#: readelf.c:10083 #, c-format msgid "" "\n" @@ -4112,312 +4198,312 @@ msgid "" msgstr "" #. FIXME: Should we handle this case? -#: readelf.c:9786 +#: readelf.c:10128 msgid "Range lists in .debug_info section aren't in ascending order!\n" msgstr "" -#: readelf.c:9789 +#: readelf.c:10131 msgid "No range lists in .debug_info section!\n" msgstr "" -#: readelf.c:9792 +#: readelf.c:10134 #, c-format msgid "Range lists in .debug_ranges section start at 0x%lx\n" msgstr "" -#: readelf.c:9795 +#: readelf.c:10137 #, c-format msgid "" "Contents of the .debug_ranges section:\n" "\n" msgstr "" -#: readelf.c:9796 +#: readelf.c:10138 #, c-format msgid " Offset Begin End\n" msgstr "" -#: readelf.c:9820 +#: readelf.c:10162 #, c-format msgid "There is a hole [0x%lx - 0x%lx] in .debug_ranges section.\n" msgstr "" -#: readelf.c:9823 +#: readelf.c:10165 #, c-format msgid "There is an overlap [0x%lx - 0x%lx] in .debug_ranges section.\n" msgstr "" -#: readelf.c:10017 +#: readelf.c:10359 #, c-format msgid "The section %s contains:\n" msgstr "" -#: readelf.c:10663 +#: readelf.c:11007 #, c-format msgid "unsupported or unknown DW_CFA_%d\n" msgstr "" -#: readelf.c:10688 +#: readelf.c:11032 #, c-format msgid "Displaying the debug contents of section %s is not yet supported.\n" msgstr "" -#: readelf.c:10732 +#: readelf.c:11076 #, c-format msgid "" "\n" "Section '%s' has no debugging data.\n" msgstr "" -#: readelf.c:10746 +#: readelf.c:11090 msgid "debug section data" msgstr "" -#: readelf.c:10765 +#: readelf.c:11109 #, c-format msgid "Unrecognized debug section: %s\n" msgstr "" -#: readelf.c:10800 +#: readelf.c:11144 #, c-format msgid "Section %d was not dumped because it does not exist!\n" msgstr "" -#: readelf.c:10872 readelf.c:11236 +#: readelf.c:11216 readelf.c:11584 msgid "liblist" msgstr "" -#: readelf.c:10961 +#: readelf.c:11305 msgid "options" msgstr "" -#: readelf.c:10991 +#: readelf.c:11335 #, c-format msgid "" "\n" "Section '%s' contains %d entries:\n" msgstr "" -#: readelf.c:11152 +#: readelf.c:11496 msgid "conflict list found without a dynamic symbol table" msgstr "" -#: readelf.c:11168 readelf.c:11182 +#: readelf.c:11512 readelf.c:11526 msgid "conflict" msgstr "" -#: readelf.c:11192 +#: readelf.c:11536 #, c-format msgid "" "\n" "Section '.conflict' contains %lu entries:\n" msgstr "" -#: readelf.c:11194 +#: readelf.c:11538 msgid " Num: Index Value Name" msgstr "" -#: readelf.c:11243 +#: readelf.c:11591 msgid "liblist string table" msgstr "" -#: readelf.c:11252 +#: readelf.c:11601 #, c-format msgid "" "\n" "Library list section '%s' contains %lu entries:\n" msgstr "" -#: readelf.c:11303 +#: readelf.c:11654 msgid "NT_AUXV (auxiliary vector)" msgstr "" -#: readelf.c:11305 +#: readelf.c:11656 msgid "NT_PRSTATUS (prstatus structure)" msgstr "" -#: readelf.c:11307 +#: readelf.c:11658 msgid "NT_FPREGSET (floating point registers)" msgstr "" -#: readelf.c:11309 +#: readelf.c:11660 msgid "NT_PRPSINFO (prpsinfo structure)" msgstr "" -#: readelf.c:11311 +#: readelf.c:11662 msgid "NT_TASKSTRUCT (task structure)" msgstr "" -#: readelf.c:11313 +#: readelf.c:11664 msgid "NT_PRXFPREG (user_xfpregs structure)" msgstr "" -#: readelf.c:11315 +#: readelf.c:11666 msgid "NT_PSTATUS (pstatus structure)" msgstr "" -#: readelf.c:11317 +#: readelf.c:11668 msgid "NT_FPREGS (floating point registers)" msgstr "" -#: readelf.c:11319 +#: readelf.c:11670 msgid "NT_PSINFO (psinfo structure)" msgstr "" -#: readelf.c:11321 +#: readelf.c:11672 msgid "NT_LWPSTATUS (lwpstatus_t structure)" msgstr "" -#: readelf.c:11323 +#: readelf.c:11674 msgid "NT_LWPSINFO (lwpsinfo_t structure)" msgstr "" -#: readelf.c:11325 +#: readelf.c:11676 msgid "NT_WIN32PSTATUS (win32_pstatus structure)" msgstr "" -#: readelf.c:11333 +#: readelf.c:11684 msgid "NT_VERSION (version)" msgstr "" -#: readelf.c:11335 +#: readelf.c:11686 msgid "NT_ARCH (architecture)" msgstr "" -#: readelf.c:11340 readelf.c:11362 +#: readelf.c:11691 readelf.c:11713 #, c-format msgid "Unknown note type: (0x%08x)" msgstr "" #. NetBSD core "procinfo" structure. -#: readelf.c:11352 +#: readelf.c:11703 msgid "NetBSD procinfo structure" msgstr "" -#: readelf.c:11379 readelf.c:11393 +#: readelf.c:11730 readelf.c:11744 msgid "PT_GETREGS (reg structure)" msgstr "" -#: readelf.c:11381 readelf.c:11395 +#: readelf.c:11732 readelf.c:11746 msgid "PT_GETFPREGS (fpreg structure)" msgstr "" -#: readelf.c:11401 +#: readelf.c:11752 #, c-format msgid "PT_FIRSTMACH+%d" msgstr "" -#: readelf.c:11447 +#: readelf.c:11798 msgid "notes" msgstr "" -#: readelf.c:11453 +#: readelf.c:11804 #, c-format msgid "" "\n" "Notes at offset 0x%08lx with length 0x%08lx:\n" msgstr "" -#: readelf.c:11455 +#: readelf.c:11806 #, c-format msgid " Owner\t\tData size\tDescription\n" msgstr "" -#: readelf.c:11474 +#: readelf.c:11825 #, c-format -msgid "corrupt note found at offset %x into core notes\n" +msgid "corrupt note found at offset %lx into core notes\n" msgstr "" -#: readelf.c:11476 +#: readelf.c:11827 #, c-format -msgid " type: %x, namesize: %08lx, descsize: %08lx\n" +msgid " type: %lx, namesize: %08lx, descsize: %08lx\n" msgstr "" -#: readelf.c:11574 +#: readelf.c:11925 #, c-format msgid "No note segments present in the core file.\n" msgstr "" -#: readelf.c:11653 +#: readelf.c:12004 msgid "" "This instance of readelf has been built without support for a\n" "64 bit data type and so it cannot read 64 bit ELF files.\n" msgstr "" -#: readelf.c:11700 readelf.c:12059 +#: readelf.c:12051 readelf.c:12410 #, c-format msgid "%s: Failed to read file header\n" msgstr "" -#: readelf.c:11713 +#: readelf.c:12064 #, c-format msgid "" "\n" "File: %s\n" msgstr "" -#: readelf.c:11876 readelf.c:11897 readelf.c:11934 readelf.c:12014 +#: readelf.c:12227 readelf.c:12248 readelf.c:12285 readelf.c:12365 #, c-format msgid "%s: failed to read archive header\n" msgstr "" -#: readelf.c:11887 +#: readelf.c:12238 #, c-format msgid "%s: failed to skip archive symbol table\n" msgstr "" -#: readelf.c:11919 +#: readelf.c:12270 #, c-format msgid "%s: failed to read string table\n" msgstr "" -#: readelf.c:11955 +#: readelf.c:12306 #, c-format msgid "%s: invalid archive string table offset %lu\n" msgstr "" -#: readelf.c:11971 +#: readelf.c:12322 #, c-format msgid "%s: bad archive file name\n" msgstr "" -#: readelf.c:12003 +#: readelf.c:12354 #, c-format msgid "%s: failed to seek to next archive header\n" msgstr "" -#: readelf.c:12037 +#: readelf.c:12388 #, c-format msgid "'%s': No such file\n" msgstr "" -#: readelf.c:12039 +#: readelf.c:12390 #, c-format msgid "Could not locate '%s'. System error message: %s\n" msgstr "" -#: readelf.c:12046 +#: readelf.c:12397 #, c-format msgid "'%s' is not an ordinary file\n" msgstr "" -#: readelf.c:12053 +#: readelf.c:12404 #, c-format msgid "Input file '%s' is not readable.\n" msgstr "" -#: rename.c:127 +#: rename.c:129 #, c-format msgid "%s: cannot set time: %s" msgstr "" #. We have to clean up here. -#: rename.c:162 rename.c:200 +#: rename.c:164 rename.c:202 #, c-format msgid "unable to rename '%s' reason: %s" msgstr "" -#: rename.c:208 +#: rename.c:210 #, c-format msgid "unable to copy file '%s' reason: %s" msgstr "" @@ -4799,17 +4885,17 @@ msgstr "" msgid "can't open `%s' for output: %s" msgstr "" -#: size.c:81 +#: size.c:83 #, c-format msgid " Displays the sizes of sections inside binary files\n" msgstr "" -#: size.c:82 +#: size.c:84 #, c-format msgid " If no input file(s) are specified, a.out is assumed\n" msgstr "" -#: size.c:83 +#: size.c:85 #, c-format msgid "" " The options are:\n" @@ -4824,12 +4910,12 @@ msgid "" "\n" msgstr "" -#: size.c:153 +#: size.c:155 #, c-format msgid "invalid argument to --format: %s" msgstr "" -#: size.c:180 +#: size.c:182 #, c-format msgid "Invalid radix: %s\n" msgstr "" @@ -4988,22 +5074,22 @@ msgstr "" msgid "Unrecognized demangled builtin type\n" msgstr "" -#: strings.c:206 +#: strings.c:215 #, c-format msgid "invalid number %s" msgstr "" -#: strings.c:643 +#: strings.c:697 #, c-format msgid "invalid integer argument %s" msgstr "" -#: strings.c:652 +#: strings.c:706 #, c-format msgid " Display printable strings in [file(s)] (stdin by default)\n" msgstr "" -#: strings.c:653 +#: strings.c:707 #, c-format msgid "" " The options are:\n" @@ -5023,12 +5109,12 @@ msgid "" " -v --version Print the program's version number\n" msgstr "" -#: sysdump.c:649 +#: sysdump.c:642 #, c-format msgid "Print a human readable interpretation of a SYSROFF object file\n" msgstr "" -#: sysdump.c:650 +#: sysdump.c:643 #, c-format msgid "" " The options are:\n" @@ -5036,7 +5122,7 @@ msgid "" " -v --version Print the program's version number\n" msgstr "" -#: sysdump.c:715 +#: sysdump.c:708 #, c-format msgid "cannot open input file %s" msgstr "" diff -uprN binutils-2.16.91.0.1/binutils/readelf.c binutils-2.16.91.0.2/binutils/readelf.c --- binutils-2.16.91.0.1/binutils/readelf.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/binutils/readelf.c 2005-07-20 12:27:27.590144076 -0700 @@ -86,6 +86,7 @@ #include "elf/i960.h" #include "elf/ia64.h" #include "elf/ip2k.h" +#include "elf/m32c.h" #include "elf/m32r.h" #include "elf/m68k.h" #include "elf/m68hc11.h" @@ -264,7 +265,7 @@ static void (*byte_put) (unsigned char * #define streq(a,b) (strcmp ((a), (b)) == 0) #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) -static void +static void ATTRIBUTE_PRINTF_1 error (const char *message, ...) { va_list args; @@ -275,7 +276,7 @@ error (const char *message, ...) va_end (args); } -static void +static void ATTRIBUTE_PRINTF_1 warn (const char *message, ...) { va_list args; @@ -327,7 +328,7 @@ get_data (void *var, FILE *file, long of if (fseek (file, archive_file_offset + offset, SEEK_SET)) { - error (_("Unable to seek to 0x%x for %s\n"), + error (_("Unable to seek to 0x%lx for %s\n"), archive_file_offset + offset, reason); return NULL; } @@ -342,8 +343,8 @@ get_data (void *var, FILE *file, long of if (mvar == NULL) { - error (_("Out of memory allocating 0x%x bytes for %s\n"), - size * nmemb, reason); + error (_("Out of memory allocating 0x%lx bytes for %s\n"), + (unsigned long)(size * nmemb), reason); return NULL; } @@ -352,7 +353,8 @@ get_data (void *var, FILE *file, long of if (fread (mvar, size, nmemb, file) != nmemb) { - error (_("Unable to read in 0x%x bytes of %s\n"), size * nmemb, reason); + error (_("Unable to read in 0x%lx bytes of %s\n"), + (unsigned long)(size * nmemb), reason); if (mvar != var) free (mvar); return NULL; @@ -766,6 +768,7 @@ guess_is_rela (unsigned long e_machine) case EM_XTENSA: case EM_XTENSA_OLD: case EM_M32R: + case EM_M32C: case EM_MS1: return TRUE; @@ -1275,6 +1278,10 @@ dump_relocations (FILE *file, rtype = elf_xtensa_reloc_type (type); break; + case EM_M32C: + rtype = elf_m32c_reloc_type (type); + break; + case EM_MS1: rtype = elf_ms1_reloc_type (type); break; @@ -1817,6 +1824,7 @@ get_machine_name (unsigned e_machine) case EM_IQ2000: return "Vitesse IQ2000"; case EM_XTENSA_OLD: case EM_XTENSA: return "Tensilica Xtensa Processor"; + case EM_M32C: return "Renesas M32c"; case EM_MS1: return "Morpho Techologies MS1 processor"; default: snprintf (buff, sizeof (buff), _(": %x"), e_machine); @@ -7453,7 +7461,7 @@ fetch_indirect_string (unsigned long off if (offset > debug_str_size) { - warn (_("DW_FORM_strp offset too big: %x\n"), offset); + warn (_("DW_FORM_strp offset too big: %lx\n"), offset); return _(""); } @@ -8464,7 +8472,7 @@ read_and_display_attr_value (unsigned lo break; default: - warn (_("Unrecognized form: %d\n"), form); + warn (_("Unrecognized form: %lu\n"), form); break; } @@ -8607,8 +8615,7 @@ read_and_display_attr_value (unsigned lo case DW_ATE_unsigned_char: printf ("(unsigned char)"); break; /* DWARF 2.1 value. */ case DW_ATE_imaginary_float: printf ("(imaginary float)"); break; - /* GNU extension. */ - case DW_ATE_GNU_decimal_float: printf ("(decimal float)"); break; + case DW_ATE_decimal_float: printf ("(decimal float)"); break; default: if (uvalue >= DW_ATE_lo_user && uvalue <= DW_ATE_hi_user) @@ -9799,10 +9806,10 @@ display_debug_loc (Elf_Internal_Shdr *se { if (start < next) warn (_("There is a hole [0x%lx - 0x%lx] in .debug_loc section.\n"), - start - section_begin, next - section_begin); + (long)(start - section_begin), (long)(next - section_begin)); else if (start > next) warn (_("There is an overlap [0x%lx - 0x%lx] in .debug_loc section.\n"), - start - section_begin, next - section_begin); + (long)(start - section_begin), (long)(next - section_begin)); } start = next; @@ -10152,10 +10159,10 @@ display_debug_ranges (Elf_Internal_Shdr { if (start < next) warn (_("There is a hole [0x%lx - 0x%lx] in .debug_ranges section.\n"), - start - section_begin, next - section_begin); + (long)(start - section_begin), (long)(next - section_begin)); else if (start > next) warn (_("There is an overlap [0x%lx - 0x%lx] in .debug_ranges section.\n"), - start - section_begin, next - section_begin); + (long)(start - section_begin), (long)(next - section_begin)); } start = next; @@ -10528,7 +10535,7 @@ display_debug_frames (Elf_Internal_Shdr if (!cie) { - warn ("Invalid CIE pointer %08lx in FDE at %08lx\n", + warn ("Invalid CIE pointer %08lx in FDE at %p\n", cie_id, saved_start); start = block_end; fc->ncols = 0; @@ -11814,9 +11821,9 @@ process_corefile_note_segment (FILE *fil if (((char *) next) > (((char *) pnotes) + length)) { - warn (_("corrupt note found at offset %x into core notes\n"), - ((char *) external) - ((char *) pnotes)); - warn (_(" type: %x, namesize: %08lx, descsize: %08lx\n"), + warn (_("corrupt note found at offset %lx into core notes\n"), + (long)((char *)external - (char *)pnotes)); + warn (_(" type: %lx, namesize: %08lx, descsize: %08lx\n"), inote.type, inote.namesz, inote.descsz); break; } @@ -12295,7 +12302,7 @@ process_archive (char *file_name, FILE * off = strtoul (arhdr.ar_name + 1, NULL, 10); if (off >= longnames_size) { - error (_("%s: invalid archive string table offset %lu\n"), off); + error (_("%s: invalid archive string table offset %lu\n"), file_name, off); ret = 1; break; } @@ -12311,7 +12318,7 @@ process_archive (char *file_name, FILE * if (nameend == NULL) { - error (_("%s: bad archive file name\n")); + error (_("%s: bad archive file name\n"), file_name); ret = 1; break; } diff -uprN binutils-2.16.91.0.1/binutils/strings.c binutils-2.16.91.0.2/binutils/strings.c --- binutils-2.16.91.0.1/binutils/strings.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/binutils/strings.c 2005-07-20 12:27:27.592143746 -0700 @@ -1,6 +1,6 @@ /* strings -- print the strings of printable characters in files Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, - 2002, 2003, 2004 Free Software Foundation, Inc. + 2002, 2003, 2004, 2005 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -151,6 +151,15 @@ static struct option long_options[] = {NULL, 0, NULL, 0} }; +/* Records the size of a named file so that we + do not repeatedly run bfd_stat() on it. */ + +typedef struct +{ + const char * filename; + bfd_size_type filesize; +} filename_and_size_t; + static void strings_a_section (bfd *, asection *, void *); static bfd_boolean strings_object_file (const char *); static bfd_boolean strings_file (char *file); @@ -314,27 +323,62 @@ main (int argc, char **argv) return (exit_status); } -/* Scan section SECT of the file ABFD, whose printable name is FILE. - If it contains initialized data, - set `got_a_section' and print the strings in it. */ +/* Scan section SECT of the file ABFD, whose printable name is in + ARG->filename and whose size might be in ARG->filesize. If it + contains initialized data set `got_a_section' and print the + strings in it. + + FIXME: We ought to be able to return error codes/messages for + certain conditions. */ static void -strings_a_section (bfd *abfd, asection *sect, void *filearg) +strings_a_section (bfd *abfd, asection *sect, void *arg) { - const char *file = (const char *) filearg; + filename_and_size_t * filename_and_sizep; + bfd_size_type *filesizep; + bfd_size_type sectsize; + void *mem; + + if ((sect->flags & DATA_FLAGS) != DATA_FLAGS) + return; - if ((sect->flags & DATA_FLAGS) == DATA_FLAGS) + sectsize = bfd_get_section_size (sect); + + if (sectsize <= 0) + return; + + /* Get the size of the file. This might have been cached for us. */ + filename_and_sizep = (filename_and_size_t *) arg; + filesizep = & filename_and_sizep->filesize; + + if (*filesizep == 0) { - bfd_size_type sz = bfd_get_section_size (sect); - void *mem = xmalloc (sz); + struct stat st; + + if (bfd_stat (abfd, &st)) + return; - if (bfd_get_section_contents (abfd, sect, mem, (file_ptr) 0, sz)) - { - got_a_section = TRUE; - print_strings (file, (FILE *) NULL, sect->filepos, 0, sz, mem); - } - free (mem); + /* Cache the result so that we do not repeatedly stat this file. */ + *filesizep = st.st_size; } + + /* Compare the size of the section against the size of the file. + If the section is bigger then the file must be corrupt and + we should not try dumping it. */ + if (sectsize >= *filesizep) + return; + + mem = xmalloc (sectsize); + + if (bfd_get_section_contents (abfd, sect, mem, (file_ptr) 0, sectsize)) + { + got_a_section = TRUE; + + print_strings (filename_and_sizep->filename, NULL, sect->filepos, + 0, sectsize, mem); + } + + free (mem); } /* Scan all of the sections in FILE, and print the strings @@ -346,7 +390,10 @@ strings_a_section (bfd *abfd, asection * static bfd_boolean strings_object_file (const char *file) { - bfd *abfd = bfd_openr (file, target); + filename_and_size_t filename_and_size; + bfd *abfd; + + abfd = bfd_openr (file, target); if (abfd == NULL) /* Treat the file as a non-object file. */ @@ -362,7 +409,9 @@ strings_object_file (const char *file) } got_a_section = FALSE; - bfd_map_over_sections (abfd, strings_a_section, (void *) file); + filename_and_size.filename = file; + filename_and_size.filesize = 0; + bfd_map_over_sections (abfd, strings_a_section, & filename_and_size); if (!bfd_close (abfd)) { diff -uprN binutils-2.16.91.0.1/binutils.spec binutils-2.16.91.0.2/binutils.spec --- binutils-2.16.91.0.1/binutils.spec 2005-06-22 13:18:33.000000000 -0700 +++ binutils-2.16.91.0.2/binutils.spec 2005-07-20 08:44:10.000000000 -0700 @@ -12,7 +12,7 @@ Summary: A GNU collection of binary utilities. Name: binutils -Version: 2.16.91.0.1 +Version: 2.16.91.0.2 Release: 1 License: GPLv2 Group: Development/Tools diff -uprN binutils-2.16.91.0.1/ChangeLog binutils-2.16.91.0.2/ChangeLog --- binutils-2.16.91.0.1/ChangeLog 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/ChangeLog 2005-07-20 12:27:26.533318346 -0700 @@ -1,3 +1,77 @@ +2005-07-16 Kelley Cook + + * all files: Update FSF address. + +2005-07-14 Jim Blandy + + * configure.in: Add cases for Renesas m32c. + * configure: Regenerated. + +2005-07-14 Kelley Cook + + * COPYING, compile, config-ml.in, config.guess, + config.sub, install-sh, missing, mkinstalldirs, + symlink-tree, ylwrap: Sync from upstream sources. + +2005-07-13 Eric Christopher + + * configure.in: Add toplevel noconfigdir support for tpf. + * configure: Regenerate. + +2005-07-11 Jakub Jelinek + + * Makefile.def (target_modules): Add libssp. + * configure.in (target_libraries): Add target-libssp. + * configure: Rebuilt. + * Makefile.in: Rebuilt. + +2005-07-11 Paolo Bonzini + + PR ada/22340 + + * Makefile.def: Sync with gcc. + * Makefile.tpl (POSTSTAGE1_FLAGS_TO_PASS): Fix pasto. + * Makefile.in: Regenerate. + +2005-07-07 Andreas Schwab + + * Makefile.def (flags_to_pass): Add CFLAGS_FOR_BUILD. + * Makefile.tpl (EXTRA_GCC_FLAGS): Don't pass CFLAGS_FOR_BUILD here. + * Makefile.in: Regenerated. + +2005-07-07 Kazu Hirata + + * configure.in: Add --enable-libssp and --disable-libssp. + * configure: Regenerate with autoconf-2.13. + +2005-07-06 Geoffrey Keating + + * configure.in: Don't build sim or rda when targetting darwin. + * configure: Regenerate. + +2005-07-04 Ben Elliston + + * src-release (do-proto-toplev): Remove dejagnu bits. + (DEJAGNU_SUPPORT_DIRS): Remove. + (dejagnu.tar.bz2, dejagnu.tar): Likewise. + (GDBD_SUPPORT_DIRS): Likewise. + (gdb+dejagnu.tar.bz2, gdb+dejagnu.tar): Likewise. + (INSIGHTD_SUPPORT_DIRS): Likewise. + (insight+dejagnu.tar.bz2, insight+dejagnu.tar): Likewise. + +2005-06-30 Ben Elliston + + * setup.com (mpw): Remove unused directive. + +2005-06-22 Paolo Bonzini + + * Makefile.def (stagefeedback): Come after profile. + Define profiledbootstrap target. + * Makefile.tpl (profiledbootstrap): Remove. + (stageprofile-end): Zap stagefeedback. + (stagefeedback-start): Copy all .gcda files, not only GCC's. + * Makefile.in: Regenerate. + 2005-06-13 Zack Weinberg * depcomp: Update from automake CVS. Add 'ia64hp' stanza. @@ -59,7 +133,7 @@ * configure.in: Always pass --target to target configures as otherwise rebuilds that do --recheck will fail. - * confiugure: Rebuilt. + * configure: Rebuilt. 2005-05-04 Paolo Bonzini diff -uprN binutils-2.16.91.0.1/config/ChangeLog binutils-2.16.91.0.2/config/ChangeLog --- binutils-2.16.91.0.1/config/ChangeLog 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/config/ChangeLog 2005-07-20 12:27:27.609140944 -0700 @@ -1,3 +1,7 @@ +2005-07-16 Kelley Cook + + * all files: Update FSF address. + 2005-06-14 Tom Tromey PR libgcj/19877: diff -uprN binutils-2.16.91.0.1/config/lead-dot.m4 binutils-2.16.91.0.2/config/lead-dot.m4 --- binutils-2.16.91.0.1/config/lead-dot.m4 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/config/lead-dot.m4 2005-07-20 12:27:27.609140944 -0700 @@ -13,8 +13,8 @@ # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA -# 02111-1307, USA. +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA +# 02110-1301, USA. # serial 1 diff -uprN binutils-2.16.91.0.1/config/warnings.m4 binutils-2.16.91.0.2/config/warnings.m4 --- binutils-2.16.91.0.1/config/warnings.m4 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/config/warnings.m4 2005-07-20 12:27:27.610140779 -0700 @@ -16,8 +16,8 @@ #You should have received a copy of the GNU General Public License #along with GCC; see the file COPYING. If not, write to the Free -#Software Foundation, 59 Temple Place - Suite 330, Boston, MA -#02111-1307, USA. +#Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA +#02110-1301, USA. # ACX_PROG_CC_WARNING_OPTS([-Wfoo -Wbar -Wbaz]) # Sets @WARN_CFLAGS@ to the subset of the given options which the diff -uprN binutils-2.16.91.0.1/config.guess binutils-2.16.91.0.2/config.guess --- binutils-2.16.91.0.1/config.guess 2004-11-22 12:33:30.000000000 -0800 +++ binutils-2.16.91.0.2/config.guess 2005-07-20 12:27:26.608305980 -0700 @@ -1,9 +1,9 @@ #! /bin/sh # Attempt to guess a canonical system name. # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, -# 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. +# 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. -timestamp='2004-11-12' +timestamp='2005-07-08' # This file is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by @@ -17,13 +17,15 @@ timestamp='2004-11-12' # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA +# 02110-1301, USA. # # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. + # Originally written by Per Bothner . # Please send patches to . Submit a context # diff and a properly formatted ChangeLog entry. @@ -53,7 +55,7 @@ version="\ GNU config.guess ($timestamp) Originally written by Per Bothner. -Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 +Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO @@ -66,11 +68,11 @@ Try \`$me --help' for more information." while test $# -gt 0 ; do case $1 in --time-stamp | --time* | -t ) - echo "$timestamp" ; exit 0 ;; + echo "$timestamp" ; exit ;; --version | -v ) - echo "$version" ; exit 0 ;; + echo "$version" ; exit ;; --help | --h* | -h ) - echo "$usage"; exit 0 ;; + echo "$usage"; exit ;; -- ) # Stop option processing shift; break ;; - ) # Use stdin as input. @@ -123,7 +125,7 @@ case $CC_FOR_BUILD,$HOST_CC,$CC in ;; ,,*) CC_FOR_BUILD=$CC ;; ,*,*) CC_FOR_BUILD=$HOST_CC ;; -esac ;' +esac ; set_cc_for_build= ;' # This is needed to find uname on a Pyramid OSx when run in the BSD universe. # (ghazi@noc.rutgers.edu 1994-08-24) @@ -196,55 +198,20 @@ case "${UNAME_MACHINE}:${UNAME_SYSTEM}:$ # contains redundant information, the shorter form: # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM is used. echo "${machine}-${os}${release}" - exit 0 ;; - amd64:OpenBSD:*:*) - echo x86_64-unknown-openbsd${UNAME_RELEASE} - exit 0 ;; - amiga:OpenBSD:*:*) - echo m68k-unknown-openbsd${UNAME_RELEASE} - exit 0 ;; - cats:OpenBSD:*:*) - echo arm-unknown-openbsd${UNAME_RELEASE} - exit 0 ;; - hp300:OpenBSD:*:*) - echo m68k-unknown-openbsd${UNAME_RELEASE} - exit 0 ;; - luna88k:OpenBSD:*:*) - echo m88k-unknown-openbsd${UNAME_RELEASE} - exit 0 ;; - mac68k:OpenBSD:*:*) - echo m68k-unknown-openbsd${UNAME_RELEASE} - exit 0 ;; - macppc:OpenBSD:*:*) - echo powerpc-unknown-openbsd${UNAME_RELEASE} - exit 0 ;; - mvme68k:OpenBSD:*:*) - echo m68k-unknown-openbsd${UNAME_RELEASE} - exit 0 ;; - mvme88k:OpenBSD:*:*) - echo m88k-unknown-openbsd${UNAME_RELEASE} - exit 0 ;; - mvmeppc:OpenBSD:*:*) - echo powerpc-unknown-openbsd${UNAME_RELEASE} - exit 0 ;; - sgi:OpenBSD:*:*) - echo mips64-unknown-openbsd${UNAME_RELEASE} - exit 0 ;; - sun3:OpenBSD:*:*) - echo m68k-unknown-openbsd${UNAME_RELEASE} - exit 0 ;; + exit ;; *:OpenBSD:*:*) - echo ${UNAME_MACHINE}-unknown-openbsd${UNAME_RELEASE} - exit 0 ;; + UNAME_MACHINE_ARCH=`arch | sed 's/OpenBSD.//'` + echo ${UNAME_MACHINE_ARCH}-unknown-openbsd${UNAME_RELEASE} + exit ;; *:ekkoBSD:*:*) echo ${UNAME_MACHINE}-unknown-ekkobsd${UNAME_RELEASE} - exit 0 ;; + exit ;; macppc:MirBSD:*:*) echo powerppc-unknown-mirbsd${UNAME_RELEASE} - exit 0 ;; + exit ;; *:MirBSD:*:*) echo ${UNAME_MACHINE}-unknown-mirbsd${UNAME_RELEASE} - exit 0 ;; + exit ;; alpha:OSF1:*:*) case $UNAME_RELEASE in *4.0) @@ -297,40 +264,43 @@ case "${UNAME_MACHINE}:${UNAME_SYSTEM}:$ # A Xn.n version is an unreleased experimental baselevel. # 1.2 uses "1.2" for uname -r. echo ${UNAME_MACHINE}-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^[PVTX]//' | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` - exit 0 ;; + exit ;; Alpha\ *:Windows_NT*:*) # How do we know it's Interix rather than the generic POSIX subsystem? # Should we change UNAME_MACHINE based on the output of uname instead # of the specific Alpha model? echo alpha-pc-interix - exit 0 ;; + exit ;; 21064:Windows_NT:50:3) echo alpha-dec-winnt3.5 - exit 0 ;; + exit ;; Amiga*:UNIX_System_V:4.0:*) echo m68k-unknown-sysv4 - exit 0;; + exit ;; *:[Aa]miga[Oo][Ss]:*:*) echo ${UNAME_MACHINE}-unknown-amigaos - exit 0 ;; + exit ;; *:[Mm]orph[Oo][Ss]:*:*) echo ${UNAME_MACHINE}-unknown-morphos - exit 0 ;; + exit ;; *:OS/390:*:*) echo i370-ibm-openedition - exit 0 ;; + exit ;; *:z/VM:*:*) echo s390-ibm-zvmoe - exit 0 ;; + exit ;; *:OS400:*:*) echo powerpc-ibm-os400 - exit 0 ;; + exit ;; arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*) echo arm-acorn-riscix${UNAME_RELEASE} - exit 0;; + exit ;; + arm:riscos:*:*|arm:RISCOS:*:*) + echo arm-unknown-riscos + exit ;; SR2?01:HI-UX/MPP:*:* | SR8000:HI-UX/MPP:*:*) echo hppa1.1-hitachi-hiuxmpp - exit 0;; + exit ;; Pyramid*:OSx*:*:* | MIS*:OSx*:*:* | MIS*:SMP_DC-OSx*:*:*) # akee@wpdis03.wpafb.af.mil (Earle F. Ake) contributed MIS and NILE. if test "`(/bin/universe) 2>/dev/null`" = att ; then @@ -338,32 +308,32 @@ case "${UNAME_MACHINE}:${UNAME_SYSTEM}:$ else echo pyramid-pyramid-bsd fi - exit 0 ;; + exit ;; NILE*:*:*:dcosx) echo pyramid-pyramid-svr4 - exit 0 ;; + exit ;; DRS?6000:unix:4.0:6*) echo sparc-icl-nx6 - exit 0 ;; + exit ;; DRS?6000:UNIX_SV:4.2*:7* | DRS?6000:isis:4.2*:7*) case `/usr/bin/uname -p` in - sparc) echo sparc-icl-nx7 && exit 0 ;; + sparc) echo sparc-icl-nx7; exit ;; esac ;; sun4H:SunOS:5.*:*) echo sparc-hal-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` - exit 0 ;; + exit ;; sun4*:SunOS:5.*:* | tadpole*:SunOS:5.*:*) echo sparc-sun-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` - exit 0 ;; + exit ;; i86pc:SunOS:5.*:*) echo i386-pc-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` - exit 0 ;; + exit ;; sun4*:SunOS:6*:*) # According to config.sub, this is the proper way to canonicalize # SunOS6. Hard to guess exactly what SunOS6 will be like, but # it's likely to be more like Solaris than SunOS4. echo sparc-sun-solaris3`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` - exit 0 ;; + exit ;; sun4*:SunOS:*:*) case "`/usr/bin/arch -k`" in Series*|S4*) @@ -372,10 +342,10 @@ case "${UNAME_MACHINE}:${UNAME_SYSTEM}:$ esac # Japanese Language versions have a version number like `4.1.3-JL'. echo sparc-sun-sunos`echo ${UNAME_RELEASE}|sed -e 's/-/_/'` - exit 0 ;; + exit ;; sun3*:SunOS:*:*) echo m68k-sun-sunos${UNAME_RELEASE} - exit 0 ;; + exit ;; sun*:*:4.2BSD:*) UNAME_RELEASE=`(sed 1q /etc/motd | awk '{print substr($5,1,3)}') 2>/dev/null` test "x${UNAME_RELEASE}" = "x" && UNAME_RELEASE=3 @@ -387,10 +357,10 @@ case "${UNAME_MACHINE}:${UNAME_SYSTEM}:$ echo sparc-sun-sunos${UNAME_RELEASE} ;; esac - exit 0 ;; + exit ;; aushp:SunOS:*:*) echo sparc-auspex-sunos${UNAME_RELEASE} - exit 0 ;; + exit ;; # The situation for MiNT is a little confusing. The machine name # can be virtually everything (everything which is not # "atarist" or "atariste" at least should have a processor @@ -401,40 +371,40 @@ case "${UNAME_MACHINE}:${UNAME_SYSTEM}:$ # be no problem. atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} - exit 0 ;; + exit ;; atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} - exit 0 ;; + exit ;; *falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} - exit 0 ;; + exit ;; milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*) echo m68k-milan-mint${UNAME_RELEASE} - exit 0 ;; + exit ;; hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*) echo m68k-hades-mint${UNAME_RELEASE} - exit 0 ;; + exit ;; *:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*) echo m68k-unknown-mint${UNAME_RELEASE} - exit 0 ;; + exit ;; m68k:machten:*:*) echo m68k-apple-machten${UNAME_RELEASE} - exit 0 ;; + exit ;; powerpc:machten:*:*) echo powerpc-apple-machten${UNAME_RELEASE} - exit 0 ;; + exit ;; RISC*:Mach:*:*) echo mips-dec-mach_bsd4.3 - exit 0 ;; + exit ;; RISC*:ULTRIX:*:*) echo mips-dec-ultrix${UNAME_RELEASE} - exit 0 ;; + exit ;; VAX*:ULTRIX*:*:*) echo vax-dec-ultrix${UNAME_RELEASE} - exit 0 ;; + exit ;; 2020:CLIX:*:* | 2430:CLIX:*:*) echo clipper-intergraph-clix${UNAME_RELEASE} - exit 0 ;; + exit ;; mips:*:*:UMIPS | mips:*:*:RISCos) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c @@ -458,32 +428,33 @@ case "${UNAME_MACHINE}:${UNAME_SYSTEM}:$ exit (-1); } EOF - $CC_FOR_BUILD -o $dummy $dummy.c \ - && $dummy `echo "${UNAME_RELEASE}" | sed -n 's/\([0-9]*\).*/\1/p'` \ - && exit 0 + $CC_FOR_BUILD -o $dummy $dummy.c && + dummyarg=`echo "${UNAME_RELEASE}" | sed -n 's/\([0-9]*\).*/\1/p'` && + SYSTEM_NAME=`$dummy $dummyarg` && + { echo "$SYSTEM_NAME"; exit; } echo mips-mips-riscos${UNAME_RELEASE} - exit 0 ;; + exit ;; Motorola:PowerMAX_OS:*:*) echo powerpc-motorola-powermax - exit 0 ;; + exit ;; Motorola:*:4.3:PL8-*) echo powerpc-harris-powermax - exit 0 ;; + exit ;; Night_Hawk:*:*:PowerMAX_OS | Synergy:PowerMAX_OS:*:*) echo powerpc-harris-powermax - exit 0 ;; + exit ;; Night_Hawk:Power_UNIX:*:*) echo powerpc-harris-powerunix - exit 0 ;; + exit ;; m88k:CX/UX:7*:*) echo m88k-harris-cxux7 - exit 0 ;; + exit ;; m88k:*:4*:R4*) echo m88k-motorola-sysv4 - exit 0 ;; + exit ;; m88k:*:3*:R3*) echo m88k-motorola-sysv3 - exit 0 ;; + exit ;; AViiON:dgux:*:*) # DG/UX returns AViiON for all architectures UNAME_PROCESSOR=`/usr/bin/uname -p` @@ -499,29 +470,29 @@ EOF else echo i586-dg-dgux${UNAME_RELEASE} fi - exit 0 ;; + exit ;; M88*:DolphinOS:*:*) # DolphinOS (SVR3) echo m88k-dolphin-sysv3 - exit 0 ;; + exit ;; M88*:*:R3*:*) # Delta 88k system running SVR3 echo m88k-motorola-sysv3 - exit 0 ;; + exit ;; XD88*:*:*:*) # Tektronix XD88 system running UTekV (SVR3) echo m88k-tektronix-sysv3 - exit 0 ;; + exit ;; Tek43[0-9][0-9]:UTek:*:*) # Tektronix 4300 system running UTek (BSD) echo m68k-tektronix-bsd - exit 0 ;; + exit ;; *:IRIX*:*:*) echo mips-sgi-irix`echo ${UNAME_RELEASE}|sed -e 's/-/_/g'` - exit 0 ;; + exit ;; ????????:AIX?:[12].1:2) # AIX 2.2.1 or AIX 2.1.1 is RT/PC AIX. - echo romp-ibm-aix # uname -m gives an 8 hex-code CPU id - exit 0 ;; # Note that: echo "'`uname -s`'" gives 'AIX ' + echo romp-ibm-aix # uname -m gives an 8 hex-code CPU id + exit ;; # Note that: echo "'`uname -s`'" gives 'AIX ' i*86:AIX:*:*) echo i386-ibm-aix - exit 0 ;; + exit ;; ia64:AIX:*:*) if [ -x /usr/bin/oslevel ] ; then IBM_REV=`/usr/bin/oslevel` @@ -529,7 +500,7 @@ EOF IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} fi echo ${UNAME_MACHINE}-ibm-aix${IBM_REV} - exit 0 ;; + exit ;; *:AIX:2:3) if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then eval $set_cc_for_build @@ -544,14 +515,18 @@ EOF exit(0); } EOF - $CC_FOR_BUILD -o $dummy $dummy.c && $dummy && exit 0 - echo rs6000-ibm-aix3.2.5 + if $CC_FOR_BUILD -o $dummy $dummy.c && SYSTEM_NAME=`$dummy` + then + echo "$SYSTEM_NAME" + else + echo rs6000-ibm-aix3.2.5 + fi elif grep bos324 /usr/include/stdio.h >/dev/null 2>&1; then echo rs6000-ibm-aix3.2.4 else echo rs6000-ibm-aix3.2 fi - exit 0 ;; + exit ;; *:AIX:*:[45]) IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }'` if /usr/sbin/lsattr -El ${IBM_CPU_ID} | grep ' POWER' >/dev/null 2>&1; then @@ -565,28 +540,28 @@ EOF IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} fi echo ${IBM_ARCH}-ibm-aix${IBM_REV} - exit 0 ;; + exit ;; *:AIX:*:*) echo rs6000-ibm-aix - exit 0 ;; + exit ;; ibmrt:4.4BSD:*|romp-ibm:BSD:*) echo romp-ibm-bsd4.4 - exit 0 ;; + exit ;; ibmrt:*BSD:*|romp-ibm:BSD:*) # covers RT/PC BSD and echo romp-ibm-bsd${UNAME_RELEASE} # 4.3 with uname added to - exit 0 ;; # report: romp-ibm BSD 4.3 + exit ;; # report: romp-ibm BSD 4.3 *:BOSX:*:*) echo rs6000-bull-bosx - exit 0 ;; + exit ;; DPX/2?00:B.O.S.:*:*) echo m68k-bull-sysv3 - exit 0 ;; + exit ;; 9000/[34]??:4.3bsd:1.*:*) echo m68k-hp-bsd - exit 0 ;; + exit ;; hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*) echo m68k-hp-bsd4.4 - exit 0 ;; + exit ;; 9000/[34678]??:HP-UX:*:*) HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` case "${UNAME_MACHINE}" in @@ -648,9 +623,19 @@ EOF esac if [ ${HP_ARCH} = "hppa2.0w" ] then - # avoid double evaluation of $set_cc_for_build - test -n "$CC_FOR_BUILD" || eval $set_cc_for_build - if echo __LP64__ | (CCOPTS= $CC_FOR_BUILD -E -) | grep __LP64__ >/dev/null + eval $set_cc_for_build + + # hppa2.0w-hp-hpux* has a 64-bit kernel and a compiler generating + # 32-bit code. hppa64-hp-hpux* has the same kernel and a compiler + # generating 64-bit code. GNU and HP use different nomenclature: + # + # $ CC_FOR_BUILD=cc ./config.guess + # => hppa2.0w-hp-hpux11.23 + # $ CC_FOR_BUILD="cc +DA2.0w" ./config.guess + # => hppa64-hp-hpux11.23 + + if echo __LP64__ | (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | + grep __LP64__ >/dev/null then HP_ARCH="hppa2.0w" else @@ -658,11 +643,11 @@ EOF fi fi echo ${HP_ARCH}-hp-hpux${HPUX_REV} - exit 0 ;; + exit ;; ia64:HP-UX:*:*) HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` echo ia64-hp-hpux${HPUX_REV} - exit 0 ;; + exit ;; 3050*:HI-UX:*:*) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c @@ -690,158 +675,166 @@ EOF exit (0); } EOF - $CC_FOR_BUILD -o $dummy $dummy.c && $dummy && exit 0 + $CC_FOR_BUILD -o $dummy $dummy.c && SYSTEM_NAME=`$dummy` && + { echo "$SYSTEM_NAME"; exit; } echo unknown-hitachi-hiuxwe2 - exit 0 ;; + exit ;; 9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:* ) echo hppa1.1-hp-bsd - exit 0 ;; + exit ;; 9000/8??:4.3bsd:*:*) echo hppa1.0-hp-bsd - exit 0 ;; + exit ;; *9??*:MPE/iX:*:* | *3000*:MPE/iX:*:*) echo hppa1.0-hp-mpeix - exit 0 ;; + exit ;; hp7??:OSF1:*:* | hp8?[79]:OSF1:*:* ) echo hppa1.1-hp-osf - exit 0 ;; + exit ;; hp8??:OSF1:*:*) echo hppa1.0-hp-osf - exit 0 ;; + exit ;; i*86:OSF1:*:*) if [ -x /usr/sbin/sysversion ] ; then echo ${UNAME_MACHINE}-unknown-osf1mk else echo ${UNAME_MACHINE}-unknown-osf1 fi - exit 0 ;; + exit ;; parisc*:Lites*:*:*) echo hppa1.1-hp-lites - exit 0 ;; + exit ;; C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*) echo c1-convex-bsd - exit 0 ;; + exit ;; C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*) if getsysinfo -f scalar_acc then echo c32-convex-bsd else echo c2-convex-bsd fi - exit 0 ;; + exit ;; C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*) echo c34-convex-bsd - exit 0 ;; + exit ;; C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*) echo c38-convex-bsd - exit 0 ;; + exit ;; C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*) echo c4-convex-bsd - exit 0 ;; + exit ;; CRAY*Y-MP:*:*:*) echo ymp-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' - exit 0 ;; + exit ;; CRAY*[A-Z]90:*:*:*) echo ${UNAME_MACHINE}-cray-unicos${UNAME_RELEASE} \ | sed -e 's/CRAY.*\([A-Z]90\)/\1/' \ -e y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/ \ -e 's/\.[^.]*$/.X/' - exit 0 ;; + exit ;; CRAY*TS:*:*:*) echo t90-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' - exit 0 ;; + exit ;; CRAY*T3E:*:*:*) echo alphaev5-cray-unicosmk${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' - exit 0 ;; + exit ;; CRAY*SV1:*:*:*) echo sv1-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' - exit 0 ;; + exit ;; *:UNICOS/mp:*:*) echo craynv-cray-unicosmp${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' - exit 0 ;; + exit ;; F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*) FUJITSU_PROC=`uname -m | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'` echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" - exit 0 ;; + exit ;; 5000:UNIX_System_V:4.*:*) FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` FUJITSU_REL=`echo ${UNAME_RELEASE} | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/ /_/'` echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" - exit 0 ;; + exit ;; i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*) echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE} - exit 0 ;; + exit ;; sparc*:BSD/OS:*:*) echo sparc-unknown-bsdi${UNAME_RELEASE} - exit 0 ;; + exit ;; *:BSD/OS:*:*) echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} - exit 0 ;; + exit ;; *:FreeBSD:*:*) echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` - exit 0 ;; + exit ;; i*:CYGWIN*:*) echo ${UNAME_MACHINE}-pc-cygwin - exit 0 ;; + exit ;; i*:MINGW*:*) echo ${UNAME_MACHINE}-pc-mingw32 - exit 0 ;; + exit ;; + i*:windows32*:*) + # uname -m includes "-pc" on this system. + echo ${UNAME_MACHINE}-mingw32 + exit ;; i*:PW*:*) echo ${UNAME_MACHINE}-pc-pw32 - exit 0 ;; + exit ;; x86:Interix*:[34]*) echo i586-pc-interix${UNAME_RELEASE}|sed -e 's/\..*//' - exit 0 ;; + exit ;; [345]86:Windows_95:* | [345]86:Windows_98:* | [345]86:Windows_NT:*) echo i${UNAME_MACHINE}-pc-mks - exit 0 ;; + exit ;; i*:Windows_NT*:* | Pentium*:Windows_NT*:*) # How do we know it's Interix rather than the generic POSIX subsystem? # It also conflicts with pre-2.0 versions of AT&T UWIN. Should we # UNAME_MACHINE based on the output of uname instead of i386? echo i586-pc-interix - exit 0 ;; + exit ;; i*:UWIN*:*) echo ${UNAME_MACHINE}-pc-uwin - exit 0 ;; + exit ;; + amd64:CYGWIN*:*:*) + echo x86_64-unknown-cygwin + exit ;; p*:CYGWIN*:*) echo powerpcle-unknown-cygwin - exit 0 ;; + exit ;; prep*:SunOS:5.*:*) echo powerpcle-unknown-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` - exit 0 ;; + exit ;; *:GNU:*:*) # the GNU system echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` - exit 0 ;; + exit ;; *:GNU/*:*:*) # other systems with GNU libc and userland echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-gnu - exit 0 ;; + exit ;; i*86:Minix:*:*) echo ${UNAME_MACHINE}-pc-minix - exit 0 ;; + exit ;; arm*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu - exit 0 ;; + exit ;; cris:Linux:*:*) echo cris-axis-linux-gnu - exit 0 ;; + exit ;; crisv32:Linux:*:*) echo crisv32-axis-linux-gnu - exit 0 ;; + exit ;; frv:Linux:*:*) echo frv-unknown-linux-gnu - exit 0 ;; + exit ;; ia64:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu - exit 0 ;; + exit ;; m32r*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu - exit 0 ;; + exit ;; m68*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu - exit 0 ;; + exit ;; mips:Linux:*:*) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c @@ -859,7 +852,7 @@ EOF #endif EOF eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^CPU=` - test x"${CPU}" != x && echo "${CPU}-unknown-linux-gnu" && exit 0 + test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; } ;; mips64:Linux:*:*) eval $set_cc_for_build @@ -878,14 +871,14 @@ EOF #endif EOF eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^CPU=` - test x"${CPU}" != x && echo "${CPU}-unknown-linux-gnu" && exit 0 + test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; } ;; ppc:Linux:*:*) echo powerpc-unknown-linux-gnu - exit 0 ;; + exit ;; ppc64:Linux:*:*) echo powerpc64-unknown-linux-gnu - exit 0 ;; + exit ;; alpha:Linux:*:*) case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in EV5) UNAME_MACHINE=alphaev5 ;; @@ -899,7 +892,7 @@ EOF objdump --private-headers /bin/sh | grep ld.so.1 >/dev/null if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} - exit 0 ;; + exit ;; parisc:Linux:*:* | hppa:Linux:*:*) # Look for CPU level case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in @@ -907,25 +900,25 @@ EOF PA8*) echo hppa2.0-unknown-linux-gnu ;; *) echo hppa-unknown-linux-gnu ;; esac - exit 0 ;; + exit ;; parisc64:Linux:*:* | hppa64:Linux:*:*) echo hppa64-unknown-linux-gnu - exit 0 ;; + exit ;; s390:Linux:*:* | s390x:Linux:*:*) echo ${UNAME_MACHINE}-ibm-linux - exit 0 ;; + exit ;; sh64*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu - exit 0 ;; + exit ;; sh*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu - exit 0 ;; + exit ;; sparc:Linux:*:* | sparc64:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu - exit 0 ;; + exit ;; x86_64:Linux:*:*) echo x86_64-unknown-linux-gnu - exit 0 ;; + exit ;; i*86:Linux:*:*) # The BFD linker knows what the default object file format is, so # first see if it will tell us. cd to the root directory to prevent @@ -943,15 +936,15 @@ EOF ;; a.out-i386-linux) echo "${UNAME_MACHINE}-pc-linux-gnuaout" - exit 0 ;; + exit ;; coff-i386) echo "${UNAME_MACHINE}-pc-linux-gnucoff" - exit 0 ;; + exit ;; "") # Either a pre-BFD a.out linker (linux-gnuoldld) or # one that does not give us useful --help. echo "${UNAME_MACHINE}-pc-linux-gnuoldld" - exit 0 ;; + exit ;; esac # Determine whether the default compiler is a.out or elf eval $set_cc_for_build @@ -979,15 +972,18 @@ EOF #endif EOF eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^LIBC=` - test x"${LIBC}" != x && echo "${UNAME_MACHINE}-pc-linux-${LIBC}" && exit 0 - test x"${TENTATIVE}" != x && echo "${TENTATIVE}" && exit 0 + test x"${LIBC}" != x && { + echo "${UNAME_MACHINE}-pc-linux-${LIBC}" + exit + } + test x"${TENTATIVE}" != x && { echo "${TENTATIVE}"; exit; } ;; i*86:DYNIX/ptx:4*:*) # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. # earlier versions are messed up and put the nodename in both # sysname and nodename. echo i386-sequent-sysv4 - exit 0 ;; + exit ;; i*86:UNIX_SV:4.2MP:2.*) # Unixware is an offshoot of SVR4, but it has its own version # number series starting with 2... @@ -995,27 +991,27 @@ EOF # I just have to hope. -- rms. # Use sysv4.2uw... so that sysv4* matches it. echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION} - exit 0 ;; + exit ;; i*86:OS/2:*:*) # If we were able to find `uname', then EMX Unix compatibility # is probably installed. echo ${UNAME_MACHINE}-pc-os2-emx - exit 0 ;; + exit ;; i*86:XTS-300:*:STOP) echo ${UNAME_MACHINE}-unknown-stop - exit 0 ;; + exit ;; i*86:atheos:*:*) echo ${UNAME_MACHINE}-unknown-atheos - exit 0 ;; - i*86:syllable:*:*) + exit ;; + i*86:syllable:*:*) echo ${UNAME_MACHINE}-pc-syllable - exit 0 ;; + exit ;; i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.0*:*) echo i386-unknown-lynxos${UNAME_RELEASE} - exit 0 ;; + exit ;; i*86:*DOS:*:*) echo ${UNAME_MACHINE}-pc-msdosdjgpp - exit 0 ;; + exit ;; i*86:*:4.*:* | i*86:SYSTEM_V:4.*:*) UNAME_REL=`echo ${UNAME_RELEASE} | sed 's/\/MP$//'` if grep Novell /usr/include/link.h >/dev/null 2>/dev/null; then @@ -1023,15 +1019,16 @@ EOF else echo ${UNAME_MACHINE}-pc-sysv${UNAME_REL} fi - exit 0 ;; - i*86:*:5:[78]*) + exit ;; + i*86:*:5:[678]*) + # UnixWare 7.x, OpenUNIX and OpenServer 6. case `/bin/uname -X | grep "^Machine"` in *486*) UNAME_MACHINE=i486 ;; *Pentium) UNAME_MACHINE=i586 ;; *Pent*|*Celeron) UNAME_MACHINE=i686 ;; esac echo ${UNAME_MACHINE}-unknown-sysv${UNAME_RELEASE}${UNAME_SYSTEM}${UNAME_VERSION} - exit 0 ;; + exit ;; i*86:*:3.2:*) if test -f /usr/options/cb.name; then UNAME_REL=`sed -n 's/.*Version //p' /dev/null 2>&1 ; then echo i860-stardent-sysv${UNAME_RELEASE} # Stardent Vistra i860-SVR4 else # Add other i860-SVR4 vendors below as they are discovered. echo i860-unknown-sysv${UNAME_RELEASE} # Unknown i860-SVR4 fi - exit 0 ;; + exit ;; mini*:CTIX:SYS*5:*) # "miniframe" echo m68010-convergent-sysv - exit 0 ;; + exit ;; mc68k:UNIX:SYSTEM5:3.51m) echo m68k-convergent-sysv - exit 0 ;; + exit ;; M680?0:D-NIX:5.3:*) echo m68k-diab-dnix - exit 0 ;; + exit ;; M68*:*:R3V[5678]*:*) - test -r /sysV68 && echo 'm68k-motorola-sysv' && exit 0 ;; + test -r /sysV68 && { echo 'm68k-motorola-sysv'; exit; } ;; 3[345]??:*:4.0:3.0 | 3[34]??A:*:4.0:3.0 | 3[34]??,*:*:4.0:3.0 | 3[34]??/*:*:4.0:3.0 | 4400:*:4.0:3.0 | 4850:*:4.0:3.0 | SKA40:*:4.0:3.0 | SDS2:*:4.0:3.0 | SHG2:*:4.0:3.0 | S7501*:*:4.0:3.0) OS_REL='' test -r /etc/.relid \ && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid` /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ - && echo i486-ncr-sysv4.3${OS_REL} && exit 0 + && { echo i486-ncr-sysv4.3${OS_REL}; exit; } /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ - && echo i586-ncr-sysv4.3${OS_REL} && exit 0 ;; + && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;; 3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*) /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ - && echo i486-ncr-sysv4 && exit 0 ;; + && { echo i486-ncr-sysv4; exit; } ;; m68*:LynxOS:2.*:* | m68*:LynxOS:3.0*:*) echo m68k-unknown-lynxos${UNAME_RELEASE} - exit 0 ;; + exit ;; mc68030:UNIX_System_V:4.*:*) echo m68k-atari-sysv4 - exit 0 ;; + exit ;; TSUNAMI:LynxOS:2.*:*) echo sparc-unknown-lynxos${UNAME_RELEASE} - exit 0 ;; + exit ;; rs6000:LynxOS:2.*:*) echo rs6000-unknown-lynxos${UNAME_RELEASE} - exit 0 ;; + exit ;; PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.0*:*) echo powerpc-unknown-lynxos${UNAME_RELEASE} - exit 0 ;; + exit ;; SM[BE]S:UNIX_SV:*:*) echo mips-dde-sysv${UNAME_RELEASE} - exit 0 ;; + exit ;; RM*:ReliantUNIX-*:*:*) echo mips-sni-sysv4 - exit 0 ;; + exit ;; RM*:SINIX-*:*:*) echo mips-sni-sysv4 - exit 0 ;; + exit ;; *:SINIX-*:*:*) if uname -p 2>/dev/null >/dev/null ; then UNAME_MACHINE=`(uname -p) 2>/dev/null` @@ -1123,61 +1120,65 @@ EOF else echo ns32k-sni-sysv fi - exit 0 ;; + exit ;; PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort # says echo i586-unisys-sysv4 - exit 0 ;; + exit ;; *:UNIX_System_V:4*:FTX*) # From Gerald Hewes . # How about differentiating between stratus architectures? -djm echo hppa1.1-stratus-sysv4 - exit 0 ;; + exit ;; *:*:*:FTX*) # From seanf@swdc.stratus.com. echo i860-stratus-sysv4 - exit 0 ;; + exit ;; + i*86:VOS:*:*) + # From Paul.Green@stratus.com. + echo ${UNAME_MACHINE}-stratus-vos + exit ;; *:VOS:*:*) # From Paul.Green@stratus.com. echo hppa1.1-stratus-vos - exit 0 ;; + exit ;; mc68*:A/UX:*:*) echo m68k-apple-aux${UNAME_RELEASE} - exit 0 ;; + exit ;; news*:NEWS-OS:6*:*) echo mips-sony-newsos6 - exit 0 ;; + exit ;; R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*) if [ -d /usr/nec ]; then echo mips-nec-sysv${UNAME_RELEASE} else echo mips-unknown-sysv${UNAME_RELEASE} fi - exit 0 ;; + exit ;; BeBox:BeOS:*:*) # BeOS running on hardware made by Be, PPC only. echo powerpc-be-beos - exit 0 ;; + exit ;; BeMac:BeOS:*:*) # BeOS running on Mac or Mac clone, PPC only. echo powerpc-apple-beos - exit 0 ;; + exit ;; BePC:BeOS:*:*) # BeOS running on Intel PC compatible. echo i586-pc-beos - exit 0 ;; + exit ;; SX-4:SUPER-UX:*:*) echo sx4-nec-superux${UNAME_RELEASE} - exit 0 ;; + exit ;; SX-5:SUPER-UX:*:*) echo sx5-nec-superux${UNAME_RELEASE} - exit 0 ;; + exit ;; SX-6:SUPER-UX:*:*) echo sx6-nec-superux${UNAME_RELEASE} - exit 0 ;; + exit ;; Power*:Rhapsody:*:*) echo powerpc-apple-rhapsody${UNAME_RELEASE} - exit 0 ;; + exit ;; *:Rhapsody:*:*) echo ${UNAME_MACHINE}-apple-rhapsody${UNAME_RELEASE} - exit 0 ;; + exit ;; *:Darwin:*:*) UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown case $UNAME_PROCESSOR in @@ -1185,7 +1186,7 @@ EOF unknown) UNAME_PROCESSOR=powerpc ;; esac echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} - exit 0 ;; + exit ;; *:procnto*:*:* | *:QNX:[0123456789]*:*) UNAME_PROCESSOR=`uname -p` if test "$UNAME_PROCESSOR" = "x86"; then @@ -1193,22 +1194,25 @@ EOF UNAME_MACHINE=pc fi echo ${UNAME_PROCESSOR}-${UNAME_MACHINE}-nto-qnx${UNAME_RELEASE} - exit 0 ;; + exit ;; *:QNX:*:4*) echo i386-pc-qnx - exit 0 ;; + exit ;; + NSE-?:NONSTOP_KERNEL:*:*) + echo nse-tandem-nsk${UNAME_RELEASE} + exit ;; NSR-?:NONSTOP_KERNEL:*:*) echo nsr-tandem-nsk${UNAME_RELEASE} - exit 0 ;; + exit ;; *:NonStop-UX:*:*) echo mips-compaq-nonstopux - exit 0 ;; + exit ;; BS2000:POSIX*:*:*) echo bs2000-siemens-sysv - exit 0 ;; + exit ;; DS/*:UNIX_System_V:*:*) echo ${UNAME_MACHINE}-${UNAME_SYSTEM}-${UNAME_RELEASE} - exit 0 ;; + exit ;; *:Plan9:*:*) # "uname -m" is not consistent, so use $cputype instead. 386 # is converted to i386 for consistency with other x86 @@ -1219,41 +1223,44 @@ EOF UNAME_MACHINE="$cputype" fi echo ${UNAME_MACHINE}-unknown-plan9 - exit 0 ;; + exit ;; *:TOPS-10:*:*) echo pdp10-unknown-tops10 - exit 0 ;; + exit ;; *:TENEX:*:*) echo pdp10-unknown-tenex - exit 0 ;; + exit ;; KS10:TOPS-20:*:* | KL10:TOPS-20:*:* | TYPE4:TOPS-20:*:*) echo pdp10-dec-tops20 - exit 0 ;; + exit ;; XKL-1:TOPS-20:*:* | TYPE5:TOPS-20:*:*) echo pdp10-xkl-tops20 - exit 0 ;; + exit ;; *:TOPS-20:*:*) echo pdp10-unknown-tops20 - exit 0 ;; + exit ;; *:ITS:*:*) echo pdp10-unknown-its - exit 0 ;; + exit ;; SEI:*:*:SEIUX) echo mips-sei-seiux${UNAME_RELEASE} - exit 0 ;; + exit ;; *:DragonFly:*:*) echo ${UNAME_MACHINE}-unknown-dragonfly`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` - exit 0 ;; + exit ;; *:*VMS:*:*) UNAME_MACHINE=`(uname -p) 2>/dev/null` case "${UNAME_MACHINE}" in - A*) echo alpha-dec-vms && exit 0 ;; - I*) echo ia64-dec-vms && exit 0 ;; - V*) echo vax-dec-vms && exit 0 ;; + A*) echo alpha-dec-vms ; exit ;; + I*) echo ia64-dec-vms ; exit ;; + V*) echo vax-dec-vms ; exit ;; esac ;; *:XENIX:*:SysV) echo i386-pc-xenix - exit 0 ;; + exit ;; + i*86:skyos:*:*) + echo ${UNAME_MACHINE}-pc-skyos`echo ${UNAME_RELEASE}` | sed -e 's/ .*$//' + exit ;; esac #echo '(No uname command or uname output not recognized.)' 1>&2 @@ -1285,7 +1292,7 @@ main () #endif #if defined (__arm) && defined (__acorn) && defined (__unix) - printf ("arm-acorn-riscix"); exit (0); + printf ("arm-acorn-riscix\n"); exit (0); #endif #if defined (hp300) && !defined (hpux) @@ -1374,11 +1381,12 @@ main () } EOF -$CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null && $dummy && exit 0 +$CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null && SYSTEM_NAME=`$dummy` && + { echo "$SYSTEM_NAME"; exit; } # Apollos put the system type in the environment. -test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit 0; } +test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit; } # Convex versions that predate uname can use getsysinfo(1) @@ -1387,22 +1395,22 @@ then case `getsysinfo -f cpu_type` in c1*) echo c1-convex-bsd - exit 0 ;; + exit ;; c2*) if getsysinfo -f scalar_acc then echo c32-convex-bsd else echo c2-convex-bsd fi - exit 0 ;; + exit ;; c34*) echo c34-convex-bsd - exit 0 ;; + exit ;; c38*) echo c38-convex-bsd - exit 0 ;; + exit ;; c4*) echo c4-convex-bsd - exit 0 ;; + exit ;; esac fi @@ -1413,7 +1421,9 @@ This script, last modified $timestamp, h the operating system you are using. It is advised that you download the most up to date version of the config scripts from - ftp://ftp.gnu.org/pub/gnu/config/ + http://savannah.gnu.org/cgi-bin/viewcvs/*checkout*/config/config/config.guess +and + http://savannah.gnu.org/cgi-bin/viewcvs/*checkout*/config/config/config.sub If the version you run ($0) is already up to date, please send the following data and any information you think might be diff -uprN binutils-2.16.91.0.1/config-ml.in binutils-2.16.91.0.2/config-ml.in --- binutils-2.16.91.0.1/config-ml.in 2004-11-22 12:33:30.000000000 -0800 +++ binutils-2.16.91.0.2/config-ml.in 2005-07-20 12:27:26.599307464 -0700 @@ -16,8 +16,8 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, -# Boston, MA 02111-1307, USA. +# Foundation, Inc., 51 Franklin Street, Fifth Floor, +# Boston, MA 02110-1301, USA. # # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a diff -uprN binutils-2.16.91.0.1/config.sub binutils-2.16.91.0.2/config.sub --- binutils-2.16.91.0.1/config.sub 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/config.sub 2005-07-20 12:27:26.614304991 -0700 @@ -3,7 +3,7 @@ # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, # 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. -timestamp='2005-04-22' +timestamp='2005-07-08' # This file is (in principle) common to ALL GNU software. # The presence of a machine in this file suggests that SOME GNU software @@ -21,14 +21,15 @@ timestamp='2005-04-22' # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, -# Boston, MA 02111-1307, USA. - +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA +# 02110-1301, USA. +# # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. + # Please send patches to . Submit a context # diff and a properly formatted ChangeLog entry. # @@ -83,11 +84,11 @@ Try \`$me --help' for more information." while test $# -gt 0 ; do case $1 in --time-stamp | --time* | -t ) - echo "$timestamp" ; exit 0 ;; + echo "$timestamp" ; exit ;; --version | -v ) - echo "$version" ; exit 0 ;; + echo "$version" ; exit ;; --help | --h* | -h ) - echo "$usage"; exit 0 ;; + echo "$usage"; exit ;; -- ) # Stop option processing shift; break ;; - ) # Use stdin as input. @@ -99,7 +100,7 @@ while test $# -gt 0 ; do *local*) # First pass through any local machine types. echo $1 - exit 0;; + exit ;; * ) break ;; @@ -251,6 +252,7 @@ case $basic_machine in | mips64vr4100 | mips64vr4100el \ | mips64vr4300 | mips64vr4300el \ | mips64vr5000 | mips64vr5000el \ + | mips64vr5900 | mips64vr5900el \ | mipsisa32 | mipsisa32el \ | mipsisa32r2 | mipsisa32r2el \ | mipsisa64 | mipsisa64el \ @@ -259,13 +261,14 @@ case $basic_machine in | mipsisa64sr71k | mipsisa64sr71kel \ | mipstx39 | mipstx39el \ | mn10200 | mn10300 \ + | ms1 \ | msp430 \ | ns16k | ns32k \ - | openrisc | or32 \ + | or32 \ | pdp10 | pdp11 | pj | pjl \ | powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \ | pyramid \ - | sh | sh[1234] | sh[23]e | sh[34]eb | shbe | shle | sh[1234]le | sh3ele \ + | sh | sh[1234] | sh[24]a | sh[23]e | sh[34]eb | shbe | shle | sh[1234]le | sh3ele \ | sh64 | sh64le \ | sparc | sparc64 | sparc64b | sparc86x | sparclet | sparclite \ | sparcv8 | sparcv9 | sparcv9b \ @@ -328,6 +331,7 @@ case $basic_machine in | mips64vr4100-* | mips64vr4100el-* \ | mips64vr4300-* | mips64vr4300el-* \ | mips64vr5000-* | mips64vr5000el-* \ + | mips64vr5900-* | mips64vr5900el-* \ | mipsisa32-* | mipsisa32el-* \ | mipsisa32r2-* | mipsisa32r2el-* \ | mipsisa64-* | mipsisa64el-* \ @@ -336,6 +340,7 @@ case $basic_machine in | mipsisa64sr71k-* | mipsisa64sr71kel-* \ | mipstx39-* | mipstx39el-* \ | mmix-* \ + | ms1-* \ | msp430-* \ | none-* | np1-* | ns16k-* | ns32k-* \ | orion-* \ @@ -343,7 +348,7 @@ case $basic_machine in | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \ | pyramid-* \ | romp-* | rs6000-* \ - | sh-* | sh[1234]-* | sh[23]e-* | sh[34]eb-* | shbe-* \ + | sh-* | sh[1234]-* | sh[24]a-* | sh[23]e-* | sh[34]eb-* | shbe-* \ | shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \ | sparc-* | sparc64-* | sparc64b-* | sparc86x-* | sparclet-* \ | sparclite-* \ @@ -770,9 +775,8 @@ case $basic_machine in basic_machine=hppa1.1-oki os=-proelf ;; - or32 | or32-*) + openrisc | openrisc-*) basic_machine=or32-unknown - os=-coff ;; os400) basic_machine=powerpc-ibm @@ -1098,12 +1102,9 @@ case $basic_machine in we32k) basic_machine=we32k-att ;; - sh3 | sh4 | sh[34]eb | sh[1234]le | sh[23]ele) + sh[1234] | sh[24]a | sh[34]eb | sh[1234]le | sh[23]ele) basic_machine=sh-unknown ;; - sh64) - basic_machine=sh64-unknown - ;; sparc | sparcv8 | sparcv9 | sparcv9b) basic_machine=sparc-sun ;; @@ -1190,7 +1191,8 @@ case $os in | -storm-chaos* | -tops10* | -tenex* | -tops20* | -its* \ | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \ | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \ - | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly*) + | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \ + | -skyos* | -haiku*) # Remember, each alternative MUST END IN *, to match a version number. ;; -qnx*) @@ -1208,7 +1210,7 @@ case $os in os=`echo $os | sed -e 's|nto|nto-qnx|'` ;; -sim | -es1800* | -hms* | -xray | -os68k* | -none* | -v88r* \ - | -windows* | -osx | -abug | -netware* | -os9* | -beos* \ + | -windows* | -osx | -abug | -netware* | -os9* | -beos* | -haiku* \ | -macos* | -mpw* | -magic* | -mmixware* | -mon960* | -lnews*) ;; -mac*) @@ -1397,6 +1399,9 @@ case $basic_machine in *-be) os=-beos ;; + *-haiku) + os=-haiku + ;; *-ibm) os=-aix ;; @@ -1568,7 +1573,7 @@ case $basic_machine in esac echo $basic_machine$os -exit 0 +exit # Local variables: # eval: (add-hook 'write-file-hooks 'time-stamp) diff -uprN binutils-2.16.91.0.1/configure binutils-2.16.91.0.2/configure --- binutils-2.16.91.0.1/configure 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/configure 2005-07-20 12:27:26.705289988 -0700 @@ -14,6 +14,8 @@ ac_default_prefix=/usr/local ac_help="$ac_help --enable-libada Builds libada directory" ac_help="$ac_help + --enable-libssp Builds libssp directory" +ac_help="$ac_help --with-mpfr-dir=PATH Specify source directory for MPFR library" ac_help="$ac_help --with-mpfr=PATH Specify directory for installed MPFR library" @@ -591,7 +593,7 @@ else { echo "configure: error: can not r fi echo $ac_n "checking host system type""... $ac_c" 1>&6 -echo "configure:595: checking host system type" >&5 +echo "configure:597: checking host system type" >&5 host_alias=$host case "$host_alias" in @@ -612,7 +614,7 @@ host_os=`echo $host | sed 's/^\([^-]*\)- echo "$ac_t""$host" 1>&6 echo $ac_n "checking target system type""... $ac_c" 1>&6 -echo "configure:616: checking target system type" >&5 +echo "configure:618: checking target system type" >&5 target_alias=$target case "$target_alias" in @@ -630,7 +632,7 @@ target_os=`echo $target | sed 's/^\([^-] echo "$ac_t""$target" 1>&6 echo $ac_n "checking build system type""... $ac_c" 1>&6 -echo "configure:634: checking build system type" >&5 +echo "configure:636: checking build system type" >&5 build_alias=$build case "$build_alias" in @@ -685,7 +687,7 @@ test "$program_transform_name" = "" && p # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" # ./install, which can be erroneously created by make from ./install.sh. echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6 -echo "configure:689: checking for a BSD compatible install" >&5 +echo "configure:691: checking for a BSD compatible install" >&5 if test -z "$INSTALL"; then if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -738,7 +740,7 @@ test -z "$INSTALL_SCRIPT" && INSTALL_SCR test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' echo $ac_n "checking whether ln works""... $ac_c" 1>&6 -echo "configure:742: checking whether ln works" >&5 +echo "configure:744: checking whether ln works" >&5 if eval "test \"`echo '$''{'acx_cv_prog_LN'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -762,7 +764,7 @@ else fi echo $ac_n "checking whether ln -s works""... $ac_c" 1>&6 -echo "configure:766: checking whether ln -s works" >&5 +echo "configure:768: checking whether ln -s works" >&5 if eval "test \"`echo '$''{'ac_cv_prog_LN_S'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -900,6 +902,7 @@ target_libraries="target-libiberty \ target-newlib \ target-libstdc++-v3 \ target-libmudflap \ + target-libssp \ target-libgfortran \ ${libgcj} \ target-libobjc \ @@ -1089,6 +1092,18 @@ if test "${ENABLE_LIBADA}" != "yes" ; th noconfigdirs="$noconfigdirs gnattools" fi +# Check whether --enable-libssp or --disable-libssp was given. +if test "${enable_libssp+set}" = set; then + enableval="$enable_libssp" + ENABLE_LIBSSP=$enableval +else + ENABLE_LIBSSP=yes +fi + +if test "${ENABLE_LIBSSP}" != "yes" ; then + noconfigdirs="$noconfigdirs target-libssp" +fi + # Save it here so that, even in case of --enable-libgcj, if the Java # front-end isn't enabled, we still get libgcj disabled. libgcj_saved=$libgcj @@ -1135,9 +1150,11 @@ case "${target}" in ;; powerpc-*-darwin*) noconfigdirs="$noconfigdirs bfd binutils ld gas opcodes gdb gprof" + noconfigdirs="$noconfigdirs sim target-rda" ;; *-*-darwin*) noconfigdirs="$noconfigdirs bfd binutils ld gas opcodes gdb gprof" + noconfigdirs="$noconfigdirs sim target-rda" noconfigdirs="$noconfigdirs ${libgcj}" ;; *-*-freebsd[12] | *-*-freebsd[12].* | *-*-freebsd*aout*) @@ -1185,12 +1202,19 @@ case "${target}" in *-*-rtems*) noconfigdirs="$noconfigdirs target-libgloss ${libgcj}" ;; + # The tpf target doesn't support gdb yet. + *-*-tpf*) + noconfigdirs="$noconfigdirs target-newlib target-libgloss target-libiberty ${libgcj} target-libmudflap gdb tcl tk libgui itcl" + ;; *-*-uclinux*) noconfigdirs="$noconfigdirs target-newlib target-libgloss target-rda ${libgcj}" ;; *-*-vxworks*) noconfigdirs="$noconfigdirs target-newlib target-libgloss target-libiberty ${libgcj}" ;; + m32c-*-*) + noconfigdirs="$noconfigdirs target-libstdc++-v3" + ;; alpha*-dec-osf*) # ld works, but does not support shared libraries. # newlib is not 64 bit ready. I'm not sure about fileutils. @@ -1789,7 +1813,7 @@ else # Extract the first word of "gcc", so it can be a program name with args. set dummy gcc; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1793: checking for $ac_word" >&5 +echo "configure:1817: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1819,7 +1843,7 @@ if test -z "$CC"; then # Extract the first word of "cc", so it can be a program name with args. set dummy cc; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1823: checking for $ac_word" >&5 +echo "configure:1847: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1870,7 +1894,7 @@ fi # Extract the first word of "cl", so it can be a program name with args. set dummy cl; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1874: checking for $ac_word" >&5 +echo "configure:1898: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1902,7 +1926,7 @@ fi fi echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 -echo "configure:1906: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 +echo "configure:1930: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 ac_ext=c # CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. @@ -1913,12 +1937,12 @@ cross_compiling=$ac_cv_prog_cc_cross cat > conftest.$ac_ext << EOF -#line 1917 "configure" +#line 1941 "configure" #include "confdefs.h" main(){return(0);} EOF -if { (eval echo configure:1922: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:1946: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then ac_cv_prog_cc_works=yes # If we can't run a trivial program, we are probably using a cross compiler. if (./conftest; exit) 2>/dev/null; then @@ -1944,12 +1968,12 @@ if test $ac_cv_prog_cc_works = no; then { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } fi echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 -echo "configure:1948: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 +echo "configure:1972: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 cross_compiling=$ac_cv_prog_cc_cross echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 -echo "configure:1953: checking whether we are using GNU C" >&5 +echo "configure:1977: checking whether we are using GNU C" >&5 if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1958,7 +1982,7 @@ else yes; #endif EOF -if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1962: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then +if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1986: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then ac_cv_prog_gcc=yes else ac_cv_prog_gcc=no @@ -1977,7 +2001,7 @@ ac_test_CFLAGS="${CFLAGS+set}" ac_save_CFLAGS="$CFLAGS" CFLAGS= echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 -echo "configure:1981: checking whether ${CC-cc} accepts -g" >&5 +echo "configure:2005: checking whether ${CC-cc} accepts -g" >&5 if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2044,7 +2068,7 @@ fi # Extract the first word of "${ac_tool_prefix}gnatbind", so it can be a program name with args. set dummy ${ac_tool_prefix}gnatbind; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2048: checking for $ac_word" >&5 +echo "configure:2072: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_GNATBIND'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2076,7 +2100,7 @@ if test -n "$ac_tool_prefix"; then # Extract the first word of "gnatbind", so it can be a program name with args. set dummy gnatbind; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2080: checking for $ac_word" >&5 +echo "configure:2104: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_GNATBIND'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2109,7 +2133,7 @@ fi fi echo $ac_n "checking whether compiler driver understands Ada""... $ac_c" 1>&6 -echo "configure:2113: checking whether compiler driver understands Ada" >&5 +echo "configure:2137: checking whether compiler driver understands Ada" >&5 if eval "test \"`echo '$''{'acx_cv_cc_gcc_supports_ada'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2141,7 +2165,7 @@ else fi echo $ac_n "checking how to compare bootstrapped objects""... $ac_c" 1>&6 -echo "configure:2145: checking how to compare bootstrapped objects" >&5 +echo "configure:2169: checking how to compare bootstrapped objects" >&5 if eval "test \"`echo '$''{'gcc_cv_prog_cmp_skip'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2239,9 +2263,9 @@ saved_CFLAGS="$CFLAGS" CFLAGS="$CFLAGS $gmpinc" # Check GMP actually works echo $ac_n "checking for correct version of gmp.h""... $ac_c" 1>&6 -echo "configure:2243: checking for correct version of gmp.h" >&5 +echo "configure:2267: checking for correct version of gmp.h" >&5 cat > conftest.$ac_ext <&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:2280: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* echo "$ac_t""yes" 1>&6 else @@ -2265,12 +2289,12 @@ rm -f conftest* if test x"$have_gmp" = xyes; then echo $ac_n "checking for MPFR""... $ac_c" 1>&6 -echo "configure:2269: checking for MPFR" >&5 +echo "configure:2293: checking for MPFR" >&5 saved_LIBS="$LIBS" LIBS="$LIBS $gmplibs" cat > conftest.$ac_ext < #include @@ -2278,7 +2302,7 @@ int main() { mpfr_t n; mpfr_init(n); ; return 0; } EOF -if { (eval echo configure:2282: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2306: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* echo "$ac_t""yes" 1>&6 else @@ -2772,7 +2796,7 @@ do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2776: checking for $ac_word" >&5 +echo "configure:2800: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CONFIGURED_BISON'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2807,7 +2831,7 @@ do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2811: checking for $ac_word" >&5 +echo "configure:2835: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CONFIGURED_YACC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2842,7 +2866,7 @@ do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2846: checking for $ac_word" >&5 +echo "configure:2870: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CONFIGURED_M4'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2877,7 +2901,7 @@ do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2881: checking for $ac_word" >&5 +echo "configure:2905: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CONFIGURED_FLEX'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2912,7 +2936,7 @@ do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2916: checking for $ac_word" >&5 +echo "configure:2940: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CONFIGURED_LEX'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2947,7 +2971,7 @@ do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2951: checking for $ac_word" >&5 +echo "configure:2975: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CONFIGURED_MAKEINFO'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3554,7 +3578,7 @@ test -n "$target_alias" && ncn_target_to # Extract the first word of "${ncn_tool_prefix}ar", so it can be a program name with args. set dummy ${ncn_tool_prefix}ar; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3558: checking for $ac_word" >&5 +echo "configure:3582: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_AR'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3587,7 +3611,7 @@ if test -z "$ac_cv_prog_AR" ; then # Extract the first word of "ar", so it can be a program name with args. set dummy ar; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3591: checking for $ac_word" >&5 +echo "configure:3615: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_AR'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3626,7 +3650,7 @@ fi # Extract the first word of "${ncn_tool_prefix}as", so it can be a program name with args. set dummy ${ncn_tool_prefix}as; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3630: checking for $ac_word" >&5 +echo "configure:3654: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_AS'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3659,7 +3683,7 @@ if test -z "$ac_cv_prog_AS" ; then # Extract the first word of "as", so it can be a program name with args. set dummy as; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3663: checking for $ac_word" >&5 +echo "configure:3687: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_AS'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3698,7 +3722,7 @@ fi # Extract the first word of "${ncn_tool_prefix}dlltool", so it can be a program name with args. set dummy ${ncn_tool_prefix}dlltool; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3702: checking for $ac_word" >&5 +echo "configure:3726: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_DLLTOOL'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3731,7 +3755,7 @@ if test -z "$ac_cv_prog_DLLTOOL" ; then # Extract the first word of "dlltool", so it can be a program name with args. set dummy dlltool; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3735: checking for $ac_word" >&5 +echo "configure:3759: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_DLLTOOL'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3770,7 +3794,7 @@ fi # Extract the first word of "${ncn_tool_prefix}ld", so it can be a program name with args. set dummy ${ncn_tool_prefix}ld; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3774: checking for $ac_word" >&5 +echo "configure:3798: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_LD'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3803,7 +3827,7 @@ if test -z "$ac_cv_prog_LD" ; then # Extract the first word of "ld", so it can be a program name with args. set dummy ld; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3807: checking for $ac_word" >&5 +echo "configure:3831: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_LD'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3842,7 +3866,7 @@ fi # Extract the first word of "${ncn_tool_prefix}nm", so it can be a program name with args. set dummy ${ncn_tool_prefix}nm; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3846: checking for $ac_word" >&5 +echo "configure:3870: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_NM'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3875,7 +3899,7 @@ if test -z "$ac_cv_prog_NM" ; then # Extract the first word of "nm", so it can be a program name with args. set dummy nm; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3879: checking for $ac_word" >&5 +echo "configure:3903: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_NM'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3914,7 +3938,7 @@ fi # Extract the first word of "${ncn_tool_prefix}ranlib", so it can be a program name with args. set dummy ${ncn_tool_prefix}ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3918: checking for $ac_word" >&5 +echo "configure:3942: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3947,7 +3971,7 @@ if test -z "$ac_cv_prog_RANLIB" ; then # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3951: checking for $ac_word" >&5 +echo "configure:3975: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3986,7 +4010,7 @@ fi # Extract the first word of "${ncn_tool_prefix}windres", so it can be a program name with args. set dummy ${ncn_tool_prefix}windres; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3990: checking for $ac_word" >&5 +echo "configure:4014: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_WINDRES'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4019,7 +4043,7 @@ if test -z "$ac_cv_prog_WINDRES" ; then # Extract the first word of "windres", so it can be a program name with args. set dummy windres; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4023: checking for $ac_word" >&5 +echo "configure:4047: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_WINDRES'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4058,7 +4082,7 @@ fi # Extract the first word of "${ncn_tool_prefix}objcopy", so it can be a program name with args. set dummy ${ncn_tool_prefix}objcopy; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4062: checking for $ac_word" >&5 +echo "configure:4086: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_OBJCOPY'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4091,7 +4115,7 @@ if test -z "$ac_cv_prog_OBJCOPY" ; then # Extract the first word of "objcopy", so it can be a program name with args. set dummy objcopy; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4095: checking for $ac_word" >&5 +echo "configure:4119: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_OBJCOPY'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4130,7 +4154,7 @@ fi # Extract the first word of "${ncn_tool_prefix}objdump", so it can be a program name with args. set dummy ${ncn_tool_prefix}objdump; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4134: checking for $ac_word" >&5 +echo "configure:4158: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_OBJDUMP'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4163,7 +4187,7 @@ if test -z "$ac_cv_prog_OBJDUMP" ; then # Extract the first word of "objdump", so it can be a program name with args. set dummy objdump; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4167: checking for $ac_word" >&5 +echo "configure:4191: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_OBJDUMP'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4209,7 +4233,7 @@ fi # Extract the first word of "${ncn_target_tool_prefix}ar", so it can be a program name with args. set dummy ${ncn_target_tool_prefix}ar; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4213: checking for $ac_word" >&5 +echo "configure:4237: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CONFIGURED_AR_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4242,7 +4266,7 @@ if test -z "$ac_cv_prog_CONFIGURED_AR_FO # Extract the first word of "ar", so it can be a program name with args. set dummy ar; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4246: checking for $ac_word" >&5 +echo "configure:4270: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_CONFIGURED_AR_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4281,7 +4305,7 @@ fi # Extract the first word of "${ncn_target_tool_prefix}as", so it can be a program name with args. set dummy ${ncn_target_tool_prefix}as; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4285: checking for $ac_word" >&5 +echo "configure:4309: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CONFIGURED_AS_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4314,7 +4338,7 @@ if test -z "$ac_cv_prog_CONFIGURED_AS_FO # Extract the first word of "as", so it can be a program name with args. set dummy as; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4318: checking for $ac_word" >&5 +echo "configure:4342: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_CONFIGURED_AS_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4353,7 +4377,7 @@ fi # Extract the first word of "${ncn_target_tool_prefix}dlltool", so it can be a program name with args. set dummy ${ncn_target_tool_prefix}dlltool; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4357: checking for $ac_word" >&5 +echo "configure:4381: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CONFIGURED_DLLTOOL_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4386,7 +4410,7 @@ if test -z "$ac_cv_prog_CONFIGURED_DLLTO # Extract the first word of "dlltool", so it can be a program name with args. set dummy dlltool; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4390: checking for $ac_word" >&5 +echo "configure:4414: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_CONFIGURED_DLLTOOL_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4425,7 +4449,7 @@ fi # Extract the first word of "${ncn_target_tool_prefix}ld", so it can be a program name with args. set dummy ${ncn_target_tool_prefix}ld; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4429: checking for $ac_word" >&5 +echo "configure:4453: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CONFIGURED_LD_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4458,7 +4482,7 @@ if test -z "$ac_cv_prog_CONFIGURED_LD_FO # Extract the first word of "ld", so it can be a program name with args. set dummy ld; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4462: checking for $ac_word" >&5 +echo "configure:4486: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_CONFIGURED_LD_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4497,7 +4521,7 @@ fi # Extract the first word of "${ncn_target_tool_prefix}nm", so it can be a program name with args. set dummy ${ncn_target_tool_prefix}nm; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4501: checking for $ac_word" >&5 +echo "configure:4525: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CONFIGURED_NM_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4530,7 +4554,7 @@ if test -z "$ac_cv_prog_CONFIGURED_NM_FO # Extract the first word of "nm", so it can be a program name with args. set dummy nm; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4534: checking for $ac_word" >&5 +echo "configure:4558: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_CONFIGURED_NM_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4569,7 +4593,7 @@ fi # Extract the first word of "${ncn_target_tool_prefix}ranlib", so it can be a program name with args. set dummy ${ncn_target_tool_prefix}ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4573: checking for $ac_word" >&5 +echo "configure:4597: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CONFIGURED_RANLIB_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4602,7 +4626,7 @@ if test -z "$ac_cv_prog_CONFIGURED_RANLI # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4606: checking for $ac_word" >&5 +echo "configure:4630: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_CONFIGURED_RANLIB_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4641,7 +4665,7 @@ fi # Extract the first word of "${ncn_target_tool_prefix}windres", so it can be a program name with args. set dummy ${ncn_target_tool_prefix}windres; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4645: checking for $ac_word" >&5 +echo "configure:4669: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CONFIGURED_WINDRES_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4674,7 +4698,7 @@ if test -z "$ac_cv_prog_CONFIGURED_WINDR # Extract the first word of "windres", so it can be a program name with args. set dummy windres; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4678: checking for $ac_word" >&5 +echo "configure:4702: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_ncn_cv_CONFIGURED_WINDRES_FOR_TARGET'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4759,7 +4783,7 @@ RANLIB_FOR_TARGET=${RANLIB_FOR_TARGET}${ NM_FOR_TARGET=${NM_FOR_TARGET}${extra_nmflags_for_target} echo $ac_n "checking whether to enable maintainer-specific portions of Makefiles""... $ac_c" 1>&6 -echo "configure:4763: checking whether to enable maintainer-specific portions of Makefiles" >&5 +echo "configure:4787: checking whether to enable maintainer-specific portions of Makefiles" >&5 # Check whether --enable-maintainer-mode or --disable-maintainer-mode was given. if test "${enable_maintainer_mode+set}" = set; then enableval="$enable_maintainer_mode" @@ -4806,7 +4830,7 @@ esac # gcc for stageN-gcc and stagePREV-gcc for stage(N-1). In case this is not # possible, however, we can resort to mv. echo $ac_n "checking if symbolic links between directories work""... $ac_c" 1>&6 -echo "configure:4810: checking if symbolic links between directories work" >&5 +echo "configure:4834: checking if symbolic links between directories work" >&5 if eval "test \"`echo '$''{'gcc_cv_prog_ln_s_dir'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4920,34 +4944,15 @@ trap 'rm -f $CONFIG_STATUS conftest*; ex # Transform confdefs.h into DEFS. # Protect against shell expansion while executing Makefile rules. # Protect against Makefile macro expansion. -# -# If the first sed substitution is executed (which looks for macros that -# take arguments), then we branch to the quote section. Otherwise, -# look for a macro that doesn't take arguments. -cat >confdef2opt.sed <<\_ACEOF -t clear -: clear -s,^[ ]*#[ ]*define[ ][ ]*\([^ (][^ (]*([^)]*)\)[ ]*\(.*\),-D\1=\2,g -t quote -s,^[ ]*#[ ]*define[ ][ ]*\([^ ][^ ]*\)[ ]*\(.*\),-D\1=\2,g -t quote -d -: quote -s,[ `~#$^&*(){}\\|;'"<>?],\\&,g -s,\[,\\&,g -s,\],\\&,g -s,\$,$$,g -p -_ACEOF -# We use echo to avoid assuming a particular line-breaking character. -# The extra dot is to prevent the shell from consuming trailing -# line-breaks from the sub-command output. A line-break within -# single-quotes doesn't work because, if this script is created in a -# platform that uses two characters for line-breaks (e.g., DOS), tr -# would break. -ac_LF_and_DOT=`echo; echo .` -DEFS=`sed -n -f confdef2opt.sed confdefs.h | tr "$ac_LF_and_DOT" ' .'` -rm -f confdef2opt.sed +cat > conftest.defs <<\EOF +s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%-D\1=\2%g +s%[ `~#$^&*(){}\\|;'"<>?]%\\&%g +s%\[%\\&%g +s%\]%\\&%g +s%\$%$$%g +EOF +DEFS=`sed -f conftest.defs confdefs.h | tr '\012' ' '` +rm -f conftest.defs # Without the "./", some shells look in PATH for config.status. diff -uprN binutils-2.16.91.0.1/configure.in binutils-2.16.91.0.2/configure.in --- binutils-2.16.91.0.1/configure.in 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/configure.in 2005-07-20 12:27:26.792275644 -0700 @@ -13,7 +13,7 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ############################################################################## ### WARNING: this file contains embedded tabs. Do not run untabify on this file. @@ -147,6 +147,7 @@ target_libraries="target-libiberty \ target-newlib \ target-libstdc++-v3 \ target-libmudflap \ + target-libssp \ target-libgfortran \ ${libgcj} \ target-libobjc \ @@ -306,6 +307,14 @@ if test "${ENABLE_LIBADA}" != "yes" ; th noconfigdirs="$noconfigdirs gnattools" fi +AC_ARG_ENABLE(libssp, +[ --enable-libssp Builds libssp directory], +ENABLE_LIBSSP=$enableval, +ENABLE_LIBSSP=yes) +if test "${ENABLE_LIBSSP}" != "yes" ; then + noconfigdirs="$noconfigdirs target-libssp" +fi + # Save it here so that, even in case of --enable-libgcj, if the Java # front-end isn't enabled, we still get libgcj disabled. libgcj_saved=$libgcj @@ -352,9 +361,11 @@ case "${target}" in ;; powerpc-*-darwin*) noconfigdirs="$noconfigdirs bfd binutils ld gas opcodes gdb gprof" + noconfigdirs="$noconfigdirs sim target-rda" ;; *-*-darwin*) noconfigdirs="$noconfigdirs bfd binutils ld gas opcodes gdb gprof" + noconfigdirs="$noconfigdirs sim target-rda" noconfigdirs="$noconfigdirs ${libgcj}" ;; *-*-freebsd[[12]] | *-*-freebsd[[12]].* | *-*-freebsd*aout*) @@ -402,12 +413,19 @@ case "${target}" in *-*-rtems*) noconfigdirs="$noconfigdirs target-libgloss ${libgcj}" ;; + # The tpf target doesn't support gdb yet. + *-*-tpf*) + noconfigdirs="$noconfigdirs target-newlib target-libgloss target-libiberty ${libgcj} target-libmudflap gdb tcl tk libgui itcl" + ;; *-*-uclinux*) noconfigdirs="$noconfigdirs target-newlib target-libgloss target-rda ${libgcj}" ;; *-*-vxworks*) noconfigdirs="$noconfigdirs target-newlib target-libgloss target-libiberty ${libgcj}" ;; + m32c-*-*) + noconfigdirs="$noconfigdirs target-libstdc++-v3" + ;; alpha*-dec-osf*) # ld works, but does not support shared libraries. # newlib is not 64 bit ready. I'm not sure about fileutils. diff -uprN binutils-2.16.91.0.1/COPYING binutils-2.16.91.0.2/COPYING --- binutils-2.16.91.0.1/COPYING 1999-06-03 11:01:52.000000000 -0700 +++ binutils-2.16.91.0.2/COPYING 2005-07-20 12:27:26.482326754 -0700 @@ -2,7 +2,7 @@ Version 2, June 1991 Copyright (C) 1989, 1991 Free Software Foundation, Inc. - 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. @@ -291,7 +291,7 @@ convey the exclusion of warranty; and ea the "copyright" line and a pointer to where the full notice is found. - Copyright (C) 19yy + Copyright (C) This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -305,7 +305,7 @@ the "copyright" line and a pointer to wh You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA Also add information on how to contact you by electronic and paper mail. @@ -313,7 +313,7 @@ Also add information on how to contact y If the program is interactive, make it output a short notice like this when it starts in an interactive mode: - Gnomovision version 69, Copyright (C) 19yy name of author + Gnomovision version 69, Copyright (C) year name of author Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details. diff -uprN binutils-2.16.91.0.1/COPYING.LIB binutils-2.16.91.0.2/COPYING.LIB --- binutils-2.16.91.0.1/COPYING.LIB 1999-06-03 11:01:52.000000000 -0700 +++ binutils-2.16.91.0.2/COPYING.LIB 2005-07-20 12:27:26.500323786 -0700 @@ -2,7 +2,7 @@ Version 2, June 1991 Copyright (C) 1991 Free Software Foundation, Inc. - 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. @@ -464,8 +464,8 @@ convey the exclusion of warranty; and ea You should have received a copy of the GNU Library General Public License along with this library; if not, write to the Free - Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, - MA 02111-1307, USA + Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + MA 02110-1301, USA Also add information on how to contact you by electronic and paper mail. diff -uprN binutils-2.16.91.0.1/COPYING.LIBGLOSS binutils-2.16.91.0.2/COPYING.LIBGLOSS --- binutils-2.16.91.0.1/COPYING.LIBGLOSS 2003-01-21 10:21:32.000000000 -0800 +++ binutils-2.16.91.0.2/COPYING.LIBGLOSS 2005-07-20 12:27:26.508322467 -0700 @@ -126,8 +126,8 @@ GNU General Public License for more deta You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. +the Free Software Foundation, 51 Franklin Street, Fifth Floor, +Boston, MA 02110-1301, USA. (4) Advanced Micro Devices diff -uprN binutils-2.16.91.0.1/COPYING.NEWLIB binutils-2.16.91.0.2/COPYING.NEWLIB --- binutils-2.16.91.0.1/COPYING.NEWLIB 2004-03-03 12:24:33.000000000 -0800 +++ binutils-2.16.91.0.2/COPYING.NEWLIB 2005-07-20 12:27:26.513321643 -0700 @@ -561,8 +561,8 @@ warranty of MERCHANTABILITY or FITNESS F You should have received a copy of the GNU Lesser General Public License along with the GNU C Library; if not, write to the Free - Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - 02111-1307 USA. + Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301 USA. (22) Xavier Leroy LGPL License (i[3456]86-*-linux* targets only) diff -uprN binutils-2.16.91.0.1/cpu/ChangeLog binutils-2.16.91.0.2/cpu/ChangeLog --- binutils-2.16.91.0.1/cpu/ChangeLog 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/cpu/ChangeLog 2005-07-20 12:27:27.618139460 -0700 @@ -1,3 +1,65 @@ +2005-07-18 Nick Clifton + + * m32c.cpu (f-16-8, f-24-8, f-32-16, f-dsp-8-u24): New opcode + components. + (f-lab32-jmp-s): Fix insertion sequence. + (Dsp-8-u24, Lab-5-3, Lab32-jmp-s): New operands. + (Dsp-40-s8): Make parameter be signed. + (Dsp-40-s16): Likewise. + (Dsp-48-s8): Likewise. + (Dsp-48-s16): Likewise. + (Imm-13-u3): Likewise. (Despite its name!) + (BitBase16-16-s8): Make the parameter be unsigned. + (BitBase16-8-u11-S): Likewise. + (Lab-8-8, Lab-8-16, Lab-16-8, jcnd16-5, jcnd16, jcnd32, jmp16.s, + jmp16.b, jmp16.w, jmp32.s, jmp32.b, jmp32.w, jsp16.w, jsr32.w): Allow + relaxation. + + * m32c.opc: Fix formatting. + Use safe-ctype.h instead of ctype.h + Move duplicated code sequences into a macro. + Fix compile time warnings about signedness mismatches. + Remove dead code. + (parse_lab_5_3): New parser function. + +2005-07-16 Jim Blandy + + * m32c.opc (m32c_cgen_insn_supported): Use int, not CGEN_BITSET, + to represent isa sets. + +2005-07-15 Jim Blandy + + * m32c.cpu, m32c.opc: Fix copyright. + +2005-07-14 Jim Blandy + + * m32c.cpu, m32c.opc: Machine description for the Renesas M32C. + +2005-07-14 Alan Modra + + * ms1.opc (print_dollarhex): Correct format string. + +2005-07-06 Alan Modra + + * iq2000.cpu: Include from binutils cpu dir. + +2005-07-05 Nick Clifton + + * iq2000.opc (parse_lo16, parse_mlo16): Make value parameter + unsigned in order to avoid compile time warnings about sign + conflicts. + + * ms1.opc (parse_*): Likewise. + (parse_imm16): Use a "void *" as it is passed both signed and + unsigned arguments. + +2005-07-01 Nick Clifton + + * frv.opc: Update to ISO C90 function declaration style. + * iq2000.opc: Likewise. + * m32r.opc: Likewise. + * sh.opc: Likewise. + 2005-06-15 Dave Brolley Contributed by Red Hat. @@ -305,7 +367,7 @@ media-expand-halfword-to-double-semantics, mexpdhd, cmexpdhd, cmhtob): Use new operands. * frv.opc (CGEN_VERBOSE_ASSEMBLER_ERRORS): Define. - (parse_even_register): New function. + (parse_even_register): New function. 2003-06-03 Nick Clifton diff -uprN binutils-2.16.91.0.1/cpu/frv.opc binutils-2.16.91.0.2/cpu/frv.opc --- binutils-2.16.91.0.1/cpu/frv.opc 2005-05-10 15:46:44.000000000 -0700 +++ binutils-2.16.91.0.2/cpu/frv.opc 2005-07-20 12:27:27.626138141 -0700 @@ -18,9 +18,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. - -*/ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ /* This file is an addendum to frv.cpu. Heavy use of C code isn't appropriate in .cpu files, so it resides here. This especially applies @@ -35,8 +34,7 @@ -opc.c additions use: "-- opc.c" -asm.c additions use: "-- asm.c" -dis.c additions use: "-- dis.c" - -ibd.h additions use: "-- ibd.h" -*/ + -ibd.h additions use: "-- ibd.h". */ /* -- opc.h */ @@ -51,161 +49,150 @@ /* Vliw support. */ #define FRV_VLIW_SIZE 8 /* fr550 has largest vliw size of 8. */ #define PAD_VLIW_COMBO ,UNIT_NIL,UNIT_NIL,UNIT_NIL,UNIT_NIL + typedef CGEN_ATTR_VALUE_TYPE VLIW_COMBO[FRV_VLIW_SIZE]; typedef struct { - int next_slot; - int constraint_violation; - unsigned long mach; - unsigned long elf_flags; - CGEN_ATTR_VALUE_TYPE *unit_mapping; - VLIW_COMBO *current_vliw; - CGEN_ATTR_VALUE_TYPE major[FRV_VLIW_SIZE]; - const CGEN_INSN* insn[FRV_VLIW_SIZE]; + int next_slot; + int constraint_violation; + unsigned long mach; + unsigned long elf_flags; + CGEN_ATTR_VALUE_TYPE * unit_mapping; + VLIW_COMBO * current_vliw; + CGEN_ATTR_VALUE_TYPE major[FRV_VLIW_SIZE]; + const CGEN_INSN * insn[FRV_VLIW_SIZE]; } FRV_VLIW; -int frv_is_branch_major PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long)); -int frv_is_float_major PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long)); -int frv_is_media_major PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long)); -int frv_is_branch_insn PARAMS ((const CGEN_INSN *)); -int frv_is_float_insn PARAMS ((const CGEN_INSN *)); -int frv_is_media_insn PARAMS ((const CGEN_INSN *)); -void frv_vliw_reset PARAMS ((FRV_VLIW *, unsigned long mach, unsigned long elf_flags)); -int frv_vliw_add_insn PARAMS ((FRV_VLIW *, const CGEN_INSN *)); -int spr_valid PARAMS ((long)); +int frv_is_branch_major (CGEN_ATTR_VALUE_TYPE, unsigned long); +int frv_is_float_major (CGEN_ATTR_VALUE_TYPE, unsigned long); +int frv_is_media_major (CGEN_ATTR_VALUE_TYPE, unsigned long); +int frv_is_branch_insn (const CGEN_INSN *); +int frv_is_float_insn (const CGEN_INSN *); +int frv_is_media_insn (const CGEN_INSN *); +void frv_vliw_reset (FRV_VLIW *, unsigned long, unsigned long); +int frv_vliw_add_insn (FRV_VLIW *, const CGEN_INSN *); +int spr_valid (long); /* -- */ /* -- opc.c */ #include "elf/frv.h" #include -static int match_unit - PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, CGEN_ATTR_VALUE_TYPE)); -static int match_vliw - PARAMS ((VLIW_COMBO *, VLIW_COMBO *, int)); -static VLIW_COMBO * add_next_to_vliw - PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); -static int find_major_in_vliw - PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); -static int fr400_check_insn_major_constraints - PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); -static int fr450_check_insn_major_constraints - PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); -static int fr500_check_insn_major_constraints - PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); -static int fr550_check_insn_major_constraints - PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, const CGEN_INSN *)); -static int check_insn_major_constraints - PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, const CGEN_INSN *)); +/* Returns TRUE if {MAJOR,MACH} is a major branch of the FRV + development tree. */ -int +bfd_boolean frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) { switch (mach) { case bfd_mach_fr400: if (major >= FR400_MAJOR_B_1 && major <= FR400_MAJOR_B_6) - return 1; /* is a branch */ + return TRUE; break; case bfd_mach_fr450: if (major >= FR450_MAJOR_B_1 && major <= FR450_MAJOR_B_6) - return 1; /* is a branch */ + return TRUE; break; default: if (major >= FR500_MAJOR_B_1 && major <= FR500_MAJOR_B_6) - return 1; /* is a branch */ + return TRUE; break; } - return 0; /* not a branch */ + return FALSE; } -int +/* Returns TRUE if {MAJOR,MACH} supports floating point insns. */ + +bfd_boolean frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) { switch (mach) { case bfd_mach_fr400: case bfd_mach_fr450: - return 0; /* No float insns */ + return FALSE; default: if (major >= FR500_MAJOR_F_1 && major <= FR500_MAJOR_F_8) - return 1; /* is a float insn */ + return TRUE; break; } - return 0; /* not a branch */ + return FALSE; } -int +/* Returns TRUE if {MAJOR,MACH} supports media insns. */ + +bfd_boolean frv_is_media_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) { switch (mach) { case bfd_mach_fr400: if (major >= FR400_MAJOR_M_1 && major <= FR400_MAJOR_M_2) - return 1; /* is a media insn */ + return TRUE; break; case bfd_mach_fr450: if (major >= FR450_MAJOR_M_1 && major <= FR450_MAJOR_M_6) - return 1; /* is a media insn */ + return TRUE; break; default: if (major >= FR500_MAJOR_M_1 && major <= FR500_MAJOR_M_8) - return 1; /* is a media insn */ + return TRUE; break; } - return 0; /* not a branch */ + return FALSE; } -int +bfd_boolean frv_is_branch_insn (const CGEN_INSN *insn) { if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), bfd_mach_fr400)) - return 1; + return TRUE; if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR), bfd_mach_fr450)) - return 1; + return TRUE; if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), bfd_mach_fr500)) - return 1; + return TRUE; - return 0; + return FALSE; } -int +bfd_boolean frv_is_float_insn (const CGEN_INSN *insn) { if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), bfd_mach_fr400)) - return 1; + return TRUE; if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR), bfd_mach_fr450)) - return 1; + return TRUE; if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), bfd_mach_fr500)) - return 1; + return TRUE; - return 0; + return FALSE; } -int +bfd_boolean frv_is_media_insn (const CGEN_INSN *insn) { if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), bfd_mach_fr400)) - return 1; + return TRUE; if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR), bfd_mach_fr450)) - return 1; + return TRUE; if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), bfd_mach_fr500)) - return 1; + return TRUE; - return 0; + return FALSE; } /* This table represents the allowable packing for vliw insns for the fr400. @@ -443,10 +430,10 @@ frv_vliw_reset (FRV_VLIW *vliw, unsigned } } -/* Return 1 if unit1 is a match for unit2. +/* Return TRUE if unit1 is a match for unit2. Unit1 comes from the insn's UNIT attribute. unit2 comes from one of the *_allowed_vliw tables above. */ -static int +static bfd_boolean match_unit (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit1, CGEN_ATTR_VALUE_TYPE unit2) { @@ -454,9 +441,9 @@ match_unit (FRV_VLIW *vliw, unit1 = vliw->unit_mapping[unit1]; if (unit1 == unit2) - return 1; + return TRUE; if (unit1 < unit2) - return 0; + return FALSE; switch (unit1) { @@ -466,36 +453,34 @@ match_unit (FRV_VLIW *vliw, /* The 01 versions of these units are within 2 enums of the 0 or 1 versions. */ if (unit1 - unit2 <= 2) - return 1; + return TRUE; break; case UNIT_IALL: case UNIT_FMALL: /* The ALL versions of these units are within 5 enums of the 0, 1, 2 or 3 versions. */ if (unit1 - unit2 <= 5) - return 1; + return TRUE; break; default: break; } - return 0; + return FALSE; } -/* Return 1 if the vliws match, 0 otherwise. */ +/* Return TRUE if the vliws match, FALSE otherwise. */ -static int +static bfd_boolean match_vliw (VLIW_COMBO *vliw1, VLIW_COMBO *vliw2, int vliw_size) { int i; for (i = 0; i < vliw_size; ++i) - { - if ((*vliw1)[i] != (*vliw2)[i]) - return 0; - } + if ((*vliw1)[i] != (*vliw2)[i]) + return FALSE; - return 1; + return TRUE; } /* Find the next vliw vliw in the table that can accomodate the new insn. @@ -512,7 +497,7 @@ add_next_to_vliw (FRV_VLIW *vliw, CGEN_A { fprintf (stderr, "frv-opc.c line %d: bad vliw->next_slot value.\n", __LINE__); - abort (); /* Should never happen */ + abort (); /* Should never happen. */ } /* The table is sorted by units allowed within slots, so vliws with @@ -529,28 +514,26 @@ add_next_to_vliw (FRV_VLIW *vliw, CGEN_A return NULL; } -/* Look for the given major insn type in the given vliw. Return 1 if found, - return 0 otherwise. */ +/* Look for the given major insn type in the given vliw. + Returns TRUE if found, FALSE otherwise. */ -static int +static bfd_boolean find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) { int i; for (i = 0; i < vliw->next_slot; ++i) if (vliw->major[i] == major) - return 1; + return TRUE; - return 0; + return FALSE; } /* Check for constraints between the insns in the vliw due to major insn types. */ -static int -fr400_check_insn_major_constraints ( - FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major -) +static bfd_boolean +fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) { /* In the cpu file, all media insns are represented as being allowed in both media units. This makes it easier since this is the case for fr500. @@ -562,17 +545,15 @@ fr400_check_insn_major_constraints ( return ! find_major_in_vliw (vliw, FR400_MAJOR_M_1) && ! find_major_in_vliw (vliw, FR400_MAJOR_M_2); case FR400_MAJOR_M_1: - return !find_major_in_vliw (vliw, FR400_MAJOR_M_2); + return ! find_major_in_vliw (vliw, FR400_MAJOR_M_2); default: break; } - return 1; + return TRUE; } -static int -fr450_check_insn_major_constraints ( - FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major -) +static bfd_boolean +fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) { CGEN_ATTR_VALUE_TYPE other_major; @@ -582,7 +563,7 @@ fr450_check_insn_major_constraints ( /* (M4, M5) and (M4, M6) are allowed. */ if (other_major == FR450_MAJOR_M_4) if (major == FR450_MAJOR_M_5 || major == FR450_MAJOR_M_6) - return 1; + return TRUE; /* Otherwise, instructions in even-numbered media categories cannot be executed in parallel with other media instructions. */ @@ -602,38 +583,37 @@ fr450_check_insn_major_constraints ( || other_major == FR450_MAJOR_M_6); default: - return 1; + return TRUE; } } -static int -find_unit_in_vliw ( - FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit -) +static bfd_boolean +find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit) { int i; + for (i = 0; i < vliw->next_slot; ++i) if (CGEN_INSN_ATTR_VALUE (vliw->insn[i], CGEN_INSN_UNIT) == unit) - return 1; + return TRUE; - return 0; /* not found */ + return FALSE; /* Not found. */ } -static int -find_major_in_slot ( - FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major, CGEN_ATTR_VALUE_TYPE slot -) +static bfd_boolean +find_major_in_slot (FRV_VLIW *vliw, + CGEN_ATTR_VALUE_TYPE major, + CGEN_ATTR_VALUE_TYPE slot) { int i; for (i = 0; i < vliw->next_slot; ++i) if (vliw->major[i] == major && (*vliw->current_vliw)[i] == slot) - return 1; + return TRUE; - return 0; + return FALSE; } -static int +static bfd_boolean fr550_find_media_in_vliw (FRV_VLIW *vliw) { int i; @@ -649,13 +629,13 @@ fr550_find_media_in_vliw (FRV_VLIW *vliw || CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MCLRACC_1) continue; - return 1; /* found one */ + return TRUE; /* Found one. */ } - return 0; + return FALSE; } -static int +static bfd_boolean fr550_find_float_in_vliw (FRV_VLIW *vliw) { int i; @@ -669,16 +649,16 @@ fr550_find_float_in_vliw (FRV_VLIW *vliw if (CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_FNOP) continue; - return 1; /* found one */ + return TRUE; /* Found one. */ } - return 0; + return FALSE; } -static int -fr550_check_insn_major_constraints ( - FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major, const CGEN_INSN *insn -) +static bfd_boolean +fr550_check_insn_major_constraints (FRV_VLIW *vliw, + CGEN_ATTR_VALUE_TYPE major, + const CGEN_INSN *insn) { CGEN_ATTR_VALUE_TYPE unit; CGEN_ATTR_VALUE_TYPE slot = (*vliw->current_vliw)[vliw->next_slot]; @@ -692,8 +672,8 @@ fr550_check_insn_major_constraints ( break; case UNIT_FM2: case UNIT_FM3: - /* Floating point insns other than FNOP in slot f2 or f3 cannot coexist with - media insns. */ + /* Floating point insns other than FNOP in slot f2 or f3 cannot coexist + with media insns. */ if (major >= FR550_MAJOR_F_1 && major <= FR550_MAJOR_F_4 && CGEN_INSN_NUM (insn) != FRV_INSN_FNOP) return ! fr550_find_media_in_vliw (vliw); @@ -703,30 +683,31 @@ fr550_check_insn_major_constraints ( && CGEN_INSN_NUM (insn) != FRV_INSN_MNOP) return ! fr550_find_float_in_vliw (vliw); /* F-2 in slot f2 or f3 cannot coexist with F-2 or F-4 in slot f1 or f2 - respectively. - */ + respectively. */ if (major == FR550_MAJOR_F_2) - return ! find_major_in_slot (vliw, FR550_MAJOR_F_2, slot - (UNIT_FM2 - UNIT_FM0)) - && ! find_major_in_slot (vliw, FR550_MAJOR_F_4, slot - (UNIT_FM2 - UNIT_FM0)); + return ! find_major_in_slot (vliw, FR550_MAJOR_F_2, + slot - (UNIT_FM2 - UNIT_FM0)) + && ! find_major_in_slot (vliw, FR550_MAJOR_F_4, + slot - (UNIT_FM2 - UNIT_FM0)); /* M-2 or M-5 in slot m2 or m3 cannot coexist with M-2 in slot m1 or m2 respectively. */ if (major == FR550_MAJOR_M_2 || major == FR550_MAJOR_M_5) - return ! find_major_in_slot (vliw, FR550_MAJOR_M_2, slot - (UNIT_FM2 - UNIT_FM0)); + return ! find_major_in_slot (vliw, FR550_MAJOR_M_2, + slot - (UNIT_FM2 - UNIT_FM0)); /* M-4 in slot m2 or m3 cannot coexist with M-4 in slot m1 or m2 respectively. */ if (major == FR550_MAJOR_M_4) - return ! find_major_in_slot (vliw, FR550_MAJOR_M_4, slot - (UNIT_FM2 - UNIT_FM0)); + return ! find_major_in_slot (vliw, FR550_MAJOR_M_4, + slot - (UNIT_FM2 - UNIT_FM0)); break; default: break; } - return 1; /* all ok */ + return TRUE; /* All OK. */ } -static int -fr500_check_insn_major_constraints ( - FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major -) +static bfd_boolean +fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) { /* TODO: A table might be faster for some of the more complex instances here. */ @@ -745,7 +726,7 @@ fr500_check_insn_major_constraints ( case FR500_MAJOR_F_4: case FR500_MAJOR_F_8: case FR500_MAJOR_M_8: - return 1; /* OK */ + return TRUE; /* OK */ case FR500_MAJOR_I_2: /* Cannot coexist with I-3 insn. */ return ! find_major_in_vliw (vliw, FR500_MAJOR_I_3); @@ -829,35 +810,33 @@ fr500_check_insn_major_constraints ( abort (); break; } - return 1; + return TRUE; } -static int -check_insn_major_constraints ( - FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major, const CGEN_INSN *insn -) +static bfd_boolean +check_insn_major_constraints (FRV_VLIW *vliw, + CGEN_ATTR_VALUE_TYPE major, + const CGEN_INSN *insn) { - int rc; switch (vliw->mach) { case bfd_mach_fr400: - rc = fr400_check_insn_major_constraints (vliw, major); - break; + return fr400_check_insn_major_constraints (vliw, major); + case bfd_mach_fr450: - rc = fr450_check_insn_major_constraints (vliw, major); - break; + return fr450_check_insn_major_constraints (vliw, major); + case bfd_mach_fr550: - rc = fr550_check_insn_major_constraints (vliw, major, insn); - break; + return fr550_check_insn_major_constraints (vliw, major, insn); + default: - rc = fr500_check_insn_major_constraints (vliw, major); - break; + return fr500_check_insn_major_constraints (vliw, major); } - return rc; } -/* Add in insn to the VLIW vliw if possible. Return 0 if successful, - non-zero otherwise. */ +/* Add in insn to the VLIW vliw if possible. + Return 0 if successful, non-zero otherwise. */ + int frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn) { @@ -878,7 +857,7 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const { fprintf (stderr, "frv-opc.c line %d: bad insn unit.\n", __LINE__); - abort (); /* no UNIT specified for this insn in frv.cpu */ + abort (); /* No UNIT specified for this insn in frv.cpu. */ } switch (vliw->mach) @@ -934,42 +913,16 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const return 1; } -int -spr_valid (regno) - long regno; +bfd_boolean +spr_valid (long regno) { - if (regno < 0) return 0; - if (regno <= 4095) return 1; - return 0; + if (regno < 0) return FALSE; + if (regno <= 4095) return TRUE; + return FALSE; } /* -- */ /* -- asm.c */ -static const char * parse_ulo16 - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_uslo16 - PARAMS ((CGEN_CPU_DESC, const char **, int, signed long *)); -static const char * parse_uhi16 - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static long parse_register_number - PARAMS ((const char **)); -static const char * parse_spr - PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *)); -static const char * parse_d12 - PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); -static const char * parse_s12 - PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); -static const char * parse_u12 - PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); -static const char * parse_even_register - PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *)); -static const char * parse_A0 - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_A1 - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_A - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *, unsigned long)); - inline static const char * parse_symbolic_address (CGEN_CPU_DESC cd, const char **strp, @@ -1111,11 +1064,10 @@ parse_ld_annotation (CGEN_CPU_DESC cd, } static const char * -parse_ulo16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_ulo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -1127,7 +1079,7 @@ parse_ulo16 (cd, strp, opindex, valuep) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing `)'"; ++*strp; @@ -1142,7 +1094,7 @@ parse_ulo16 (cd, strp, opindex, valuep) *strp += 9; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1154,7 +1106,7 @@ parse_ulo16 (cd, strp, opindex, valuep) *strp += 7; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1166,7 +1118,7 @@ parse_ulo16 (cd, strp, opindex, valuep) *strp += 15; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_FUNCDESC_GOTLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1178,7 +1130,7 @@ parse_ulo16 (cd, strp, opindex, valuep) *strp += 10; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTOFFLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1190,7 +1142,7 @@ parse_ulo16 (cd, strp, opindex, valuep) *strp += 18; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_FUNCDESC_GOTOFFLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1202,7 +1154,7 @@ parse_ulo16 (cd, strp, opindex, valuep) *strp += 14; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTTLSDESCLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1214,7 +1166,7 @@ parse_ulo16 (cd, strp, opindex, valuep) *strp += 11; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_TLSMOFFLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1226,7 +1178,7 @@ parse_ulo16 (cd, strp, opindex, valuep) *strp += 13; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTTLSOFFLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1238,11 +1190,10 @@ parse_ulo16 (cd, strp, opindex, valuep) } static const char * -parse_uslo16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - signed long *valuep; +parse_uslo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + signed long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -1254,7 +1205,7 @@ parse_uslo16 (cd, strp, opindex, valuep) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing `)'"; ++*strp; @@ -1269,7 +1220,7 @@ parse_uslo16 (cd, strp, opindex, valuep) *strp += 9; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1281,7 +1232,7 @@ parse_uslo16 (cd, strp, opindex, valuep) *strp += 7; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1293,7 +1244,7 @@ parse_uslo16 (cd, strp, opindex, valuep) *strp += 15; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_FUNCDESC_GOTLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1305,7 +1256,7 @@ parse_uslo16 (cd, strp, opindex, valuep) *strp += 10; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTOFFLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1317,7 +1268,7 @@ parse_uslo16 (cd, strp, opindex, valuep) *strp += 18; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_FUNCDESC_GOTOFFLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1329,7 +1280,7 @@ parse_uslo16 (cd, strp, opindex, valuep) *strp += 14; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTTLSDESCLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1341,7 +1292,7 @@ parse_uslo16 (cd, strp, opindex, valuep) *strp += 11; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_TLSMOFFLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1353,7 +1304,7 @@ parse_uslo16 (cd, strp, opindex, valuep) *strp += 13; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTTLSOFFLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1365,11 +1316,10 @@ parse_uslo16 (cd, strp, opindex, valuep) } static const char * -parse_uhi16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_uhi16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -1381,7 +1331,7 @@ parse_uhi16 (cd, strp, opindex, valuep) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_HI16, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing `)'"; ++*strp; @@ -1403,7 +1353,7 @@ parse_uhi16 (cd, strp, opindex, valuep) *strp += 9; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELHI, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1415,7 +1365,7 @@ parse_uhi16 (cd, strp, opindex, valuep) *strp += 7; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTHI, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1427,7 +1377,7 @@ parse_uhi16 (cd, strp, opindex, valuep) *strp += 15; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_FUNCDESC_GOTHI, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1439,7 +1389,7 @@ parse_uhi16 (cd, strp, opindex, valuep) *strp += 10; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTOFFHI, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1451,7 +1401,7 @@ parse_uhi16 (cd, strp, opindex, valuep) *strp += 18; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_FUNCDESC_GOTOFFHI, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1475,7 +1425,7 @@ parse_uhi16 (cd, strp, opindex, valuep) *strp += 11; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_TLSMOFFHI, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1487,7 +1437,7 @@ parse_uhi16 (cd, strp, opindex, valuep) *strp += 13; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTTLSOFFHI, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1499,10 +1449,10 @@ parse_uhi16 (cd, strp, opindex, valuep) } static long -parse_register_number (strp) - const char **strp; +parse_register_number (const char **strp) { int regno; + if (**strp < '0' || **strp > '9') return -1; /* error */ @@ -1514,11 +1464,10 @@ parse_register_number (strp) } static const char * -parse_spr (cd, strp, table, valuep) - CGEN_CPU_DESC cd; - const char **strp; - CGEN_KEYWORD * table; - long *valuep; +parse_spr (CGEN_CPU_DESC cd, + const char **strp, + CGEN_KEYWORD * table, + long *valuep) { const char *save_strp; long regno; @@ -1529,10 +1478,10 @@ parse_spr (cd, strp, table, valuep) *strp += 4; regno = parse_register_number (strp); if (**strp != ']') - return "missing `]'"; + return _("missing `]'"); ++*strp; if (! spr_valid (regno)) - return "Special purpose register number is out of range"; + return _("Special purpose register number is out of range"); *valuep = regno; return NULL; } @@ -1542,7 +1491,7 @@ parse_spr (cd, strp, table, valuep) if (regno != -1) { if (! spr_valid (regno)) - return "Special purpose register number is out of range"; + return _("Special purpose register number is out of range"); *valuep = regno; return NULL; } @@ -1552,11 +1501,10 @@ parse_spr (cd, strp, table, valuep) } static const char * -parse_d12 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - long *valuep; +parse_d12 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -1570,7 +1518,7 @@ parse_d12 (cd, strp, opindex, valuep) *strp += 9; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GPREL12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing `)'"; ++*strp; @@ -1582,7 +1530,7 @@ parse_d12 (cd, strp, opindex, valuep) *strp += 7; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOT12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1594,7 +1542,7 @@ parse_d12 (cd, strp, opindex, valuep) *strp += 15; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_FUNCDESC_GOT12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1606,7 +1554,7 @@ parse_d12 (cd, strp, opindex, valuep) *strp += 10; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTOFF12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1618,7 +1566,7 @@ parse_d12 (cd, strp, opindex, valuep) *strp += 18; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_FUNCDESC_GOTOFF12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1630,7 +1578,7 @@ parse_d12 (cd, strp, opindex, valuep) *strp += 14; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTTLSDESC12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1642,7 +1590,7 @@ parse_d12 (cd, strp, opindex, valuep) *strp += 11; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_TLSMOFF12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1654,7 +1602,7 @@ parse_d12 (cd, strp, opindex, valuep) *strp += 13; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTTLSOFF12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1666,11 +1614,10 @@ parse_d12 (cd, strp, opindex, valuep) } static const char * -parse_s12 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - long *valuep; +parse_s12 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -1684,7 +1631,7 @@ parse_s12 (cd, strp, opindex, valuep) *strp += 9; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GPREL12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing `)'"; ++*strp; @@ -1696,7 +1643,7 @@ parse_s12 (cd, strp, opindex, valuep) *strp += 7; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOT12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1708,7 +1655,7 @@ parse_s12 (cd, strp, opindex, valuep) *strp += 15; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_FUNCDESC_GOT12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1720,7 +1667,7 @@ parse_s12 (cd, strp, opindex, valuep) *strp += 10; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTOFF12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1732,7 +1679,7 @@ parse_s12 (cd, strp, opindex, valuep) *strp += 18; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_FUNCDESC_GOTOFF12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1744,7 +1691,7 @@ parse_s12 (cd, strp, opindex, valuep) *strp += 14; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTTLSDESC12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1756,7 +1703,7 @@ parse_s12 (cd, strp, opindex, valuep) *strp += 11; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_TLSMOFF12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1768,7 +1715,7 @@ parse_s12 (cd, strp, opindex, valuep) *strp += 13; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTTLSOFF12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -1783,11 +1730,10 @@ parse_s12 (cd, strp, opindex, valuep) } static const char * -parse_u12 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - long *valuep; +parse_u12 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -1800,7 +1746,7 @@ parse_u12 (cd, strp, opindex, valuep) *strp += 9; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELU12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing `)'"; ++*strp; @@ -1816,12 +1762,11 @@ parse_u12 (cd, strp, opindex, valuep) } static const char * -parse_A (cd, strp, opindex, valuep, A) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; - unsigned long A; +parse_A (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep, + unsigned long A) { const char *errmsg; @@ -1833,37 +1778,34 @@ parse_A (cd, strp, opindex, valuep, A) return errmsg; if (*valuep != A) - return "Value of A operand must be 0 or 1"; + return _("Value of A operand must be 0 or 1"); return NULL; } static const char * -parse_A0 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_A0 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { return parse_A (cd, strp, opindex, valuep, 0); } static const char * -parse_A1 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_A1 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { return parse_A (cd, strp, opindex, valuep, 1); } static const char * -parse_even_register (cd, strP, tableP, valueP) - CGEN_CPU_DESC cd; - const char ** strP; - CGEN_KEYWORD * tableP; - long * valueP; +parse_even_register (CGEN_CPU_DESC cd, + const char ** strP, + CGEN_KEYWORD * tableP, + long * valueP) { const char * errmsg; const char * saved_star_strP = * strP; @@ -1900,7 +1842,7 @@ parse_call_label (CGEN_CPU_DESC cd, BFD_RELOC_FRV_GETTLSOFF, resultp, &value); if (**strp != ')') - return "missing `)'"; + return _("missing `)'"); ++*strp; *valuep = value; return errmsg; @@ -1913,33 +1855,25 @@ parse_call_label (CGEN_CPU_DESC cd, /* -- */ /* -- dis.c */ -static void print_spr - PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned)); -static void print_hi - PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); -static void print_lo - PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); - static void print_at (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - PTR dis_info, + void * dis_info, long reloc_ann ATTRIBUTE_UNUSED, long value ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED - ) + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; + (*info->fprintf_func) (info->stream, "@"); } static void -print_spr (cd, dis_info, names, regno, attrs) - CGEN_CPU_DESC cd; - PTR dis_info; - CGEN_KEYWORD *names; - long regno; - unsigned int attrs; +print_spr (CGEN_CPU_DESC cd, + void * dis_info, + CGEN_KEYWORD *names, + long regno, + unsigned int attrs) { /* Use the register index format for any unnamed registers. */ if (cgen_keyword_lookup_value (names, regno) == NULL) @@ -1952,29 +1886,25 @@ print_spr (cd, dis_info, names, regno, a } static void -print_hi (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_hi (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; - if (value) - (*info->fprintf_func) (info->stream, "0x%lx", value); - else - (*info->fprintf_func) (info->stream, "hi(0x%lx)", value); + + (*info->fprintf_func) (info->stream, value ? "0x%lx" : "hi(0x%lx)", value); } static void -print_lo (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_lo (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; if (value) diff -uprN binutils-2.16.91.0.1/cpu/iq2000.cpu binutils-2.16.91.0.2/cpu/iq2000.cpu --- binutils-2.16.91.0.1/cpu/iq2000.cpu 2004-11-22 12:33:31.000000000 -0800 +++ binutils-2.16.91.0.2/cpu/iq2000.cpu 2005-07-20 12:27:27.630137481 -0700 @@ -1173,10 +1173,10 @@ (if (keep-mach? (iq2000)) -(include "iq2000m.cpu")) +(include "../../cpu/iq2000m.cpu")) (if (keep-mach? (iq10)) -(include "iq10.cpu")) +(include "../../cpu/iq10.cpu")) diff -uprN binutils-2.16.91.0.1/cpu/iq2000.opc binutils-2.16.91.0.2/cpu/iq2000.opc --- binutils-2.16.91.0.1/cpu/iq2000.opc 2005-05-10 15:46:44.000000000 -0700 +++ binutils-2.16.91.0.2/cpu/iq2000.opc 2005-07-20 12:27:27.637136327 -0700 @@ -1,6 +1,6 @@ /* IQ2000 opcode support. -*- C -*- - Copyright 2000, 2001, 2002 Free Software Foundation, Inc. + Copyright 2000, 2001, 2002, 2005 Free Software Foundation, Inc. Contributed by Red Hat Inc; developed under contract from Fujitsu. @@ -18,9 +18,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. - -*/ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ /* This file is an addendum to iq2000.cpu. Heavy use of C code isn't appropriate in .cpu files, so it resides here. This especially applies @@ -35,8 +34,7 @@ -opc.c additions use: "-- opc.c" -asm.c additions use: "-- asm.c" -dis.c additions use: "-- dis.c" - -ibd.h additions use: "-- ibd.h" -*/ + -ibd.h additions use: "-- ibd.h". */ /* -- opc.h */ @@ -52,30 +50,30 @@ instructions have same mnemonics but different functionality. */ #define CGEN_VALIDATE_INSN_SUPPORTED -extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn); +extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); /* -- asm.c */ -static const char * parse_mimm PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); -static const char * parse_imm PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_hi16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_lo16 PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); + +#include "safe-ctype.h" + +static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'"); /* Special check to ensure that instruction exists for given machine. */ + int -iq2000_cgen_insn_supported (cd, insn) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; +iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) { int machs = cd->machs; - return ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0); + return (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0; } -static int iq2000_cgen_isa_register (strp) - const char **strp; +static int +iq2000_cgen_isa_register (const char **strp) { int len; int ch1, ch2; + if (**strp == 'r' || **strp == 'R') { len = strlen (*strp); @@ -95,7 +93,9 @@ static int iq2000_cgen_isa_register (str return 1; } } - if (**strp == '%' && tolower((*strp)[1]) != 'l' && tolower((*strp)[1]) != 'h') + if (**strp == '%' + && TOLOWER ((*strp)[1]) != 'l' + && TOLOWER ((*strp)[1]) != 'h') return 1; return 0; } @@ -103,16 +103,14 @@ static int iq2000_cgen_isa_register (str /* Handle negated literal. */ static const char * -parse_mimm (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - long *valuep; +parse_mimm (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { const char *errmsg; - long value; - /* Verify this isn't a register */ + /* Verify this isn't a register. */ if (iq2000_cgen_isa_register (strp)) errmsg = _("immediate value cannot be register"); else @@ -123,7 +121,8 @@ parse_mimm (cd, strp, opindex, valuep) if (errmsg == NULL) { long x = (-value) & 0xFFFF0000; - if (x != 0 && x != 0xFFFF0000) + + if (x != 0 && x != (long) 0xFFFF0000) errmsg = _("immediate value out of range"); else *valuep = (-value & 0xFFFF); @@ -135,14 +134,12 @@ parse_mimm (cd, strp, opindex, valuep) /* Handle signed/unsigned literal. */ static const char * -parse_imm (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_imm (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { const char *errmsg; - long value; if (iq2000_cgen_isa_register (strp)) errmsg = _("immediate value cannot be register"); @@ -154,7 +151,8 @@ parse_imm (cd, strp, opindex, valuep) if (errmsg == NULL) { long x = value & 0xFFFF0000; - if (x != 0 && x != 0xFFFF0000) + + if (x != 0 && x != (long) 0xFFFF0000) errmsg = _("immediate value out of range"); else *valuep = (value & 0xFFFF); @@ -166,23 +164,23 @@ parse_imm (cd, strp, opindex, valuep) /* Handle iq10 21-bit jmp offset. */ static const char * -parse_jtargq10 (cd, strp, opindex, reloc, type_addr, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - int reloc; - enum cgen_parse_operand_result *type_addr; - bfd_vma *valuep; +parse_jtargq10 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + int reloc ATTRIBUTE_UNUSED, + enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED, + bfd_vma *valuep) { const char *errmsg; bfd_vma value; enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_OFFSET_21, - &result_type, &value); + & result_type, & value); if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) { - /* Check value is within 23-bits (remembering that 2-bit shift right will occur). */ + /* Check value is within 23-bits + (remembering that 2-bit shift right will occur). */ if (value > 0x7fffff) return _("21-bit offset out of range"); } @@ -193,11 +191,10 @@ parse_jtargq10 (cd, strp, opindex, reloc /* Handle high(). */ static const char * -parse_hi16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_hi16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { if (strncasecmp (*strp, "%hi(", 4) == 0) { @@ -207,17 +204,17 @@ parse_hi16 (cd, strp, opindex, valuep) *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return _("missing `)'"); + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) { - /* if value has top-bit of %lo on, then it will + /* If value has top-bit of %lo on, then it will sign-propagate and so we compensate by adding - 1 to the resultant %hi value */ + 1 to the resultant %hi value. */ if (value & 0x8000) value += 0x10000; value >>= 16; @@ -227,8 +224,8 @@ parse_hi16 (cd, strp, opindex, valuep) return errmsg; } - /* we add %uhi in case a user just wants the high 16-bits or is using - an insn like ori for %lo which does not sign-propagate */ + /* We add %uhi in case a user just wants the high 16-bits or is using + an insn like ori for %lo which does not sign-propagate. */ if (strncasecmp (*strp, "%uhi(", 5) == 0) { enum cgen_parse_operand_result result_type; @@ -237,16 +234,15 @@ parse_hi16 (cd, strp, opindex, valuep) *strp += 5; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_UHI16, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return _("missing `)'"); + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - { - value >>= 16; - } + value >>= 16; + *valuep = value; return errmsg; @@ -260,11 +256,10 @@ parse_hi16 (cd, strp, opindex, valuep) handles the case where %lo() isn't present. */ static const char * -parse_lo16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - long *valuep; +parse_lo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { if (strncasecmp (*strp, "%lo(", 4) == 0) { @@ -274,9 +269,9 @@ parse_lo16 (cd, strp, opindex, valuep) *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return _("missing `)'"); + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) @@ -293,11 +288,10 @@ parse_lo16 (cd, strp, opindex, valuep) handles the case where %lo() isn't present. */ static const char * -parse_mlo16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - long *valuep; +parse_mlo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { if (strncasecmp (*strp, "%lo(", 4) == 0) { @@ -307,9 +301,9 @@ parse_mlo16 (cd, strp, opindex, valuep) *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return _("missing `)'"); + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) diff -uprN binutils-2.16.91.0.1/cpu/m32c.cpu binutils-2.16.91.0.2/cpu/m32c.cpu --- binutils-2.16.91.0.1/cpu/m32c.cpu 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/cpu/m32c.cpu 2005-07-20 12:27:27.659132700 -0700 @@ -0,0 +1,10313 @@ +; Renesas M32C CPU description. -*- Scheme -*- +; +; Copyright 2005 Free Software Foundation, Inc. +; +; Contributed by Red Hat Inc; developed under contract from Renesas. +; +; This file is part of the GNU Binutils. +; +; This program is free software; you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation; either version 2 of the License, or +; (at your option) any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program; if not, write to the Free Software +; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +(include "simplify.inc") + +(define-arch + (name m32c) + (comment "Renesas M32C") + (default-alignment forced) + (insn-lsb0? #f) + (machs m16c m32c) + (isas m16c m32c) +) + +(define-isa + (name m16c) + + (default-insn-bitsize 32) + + ; Number of bytes of insn we can initially fetch. + (base-insn-bitsize 32) + + ; Used in computing bit numbers. + (default-insn-word-bitsize 32) + + (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by. + + ; fetches 1 insn at a time. + (liw-insns 1) + + ; executes 1 insn at a time. + (parallel-insns 1) + ) + +(define-isa + (name m32c) + + (default-insn-bitsize 32) + + ; Number of bytes of insn we can initially fetch. + (base-insn-bitsize 32) + + ; Used in computing bit numbers. + (default-insn-word-bitsize 32) + + (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by. + + ; fetches 1 insn at a time. + (liw-insns 1) + + ; executes 1 insn at a time. + (parallel-insns 1) + ) + +(define-cpu + ; cpu names must be distinct from the architecture name and machine names. + ; The "b" suffix stands for "base" and is the convention. + ; The "f" suffix stands for "family" and is the convention. + (name m16cbf) + (comment "Renesas M16C base family") + (insn-endian big) + (data-endian little) + (word-bitsize 16) +) + +(define-cpu + ; cpu names must be distinct from the architecture name and machine names. + ; The "b" suffix stands for "base" and is the convention. + ; The "f" suffix stands for "family" and is the convention. + (name m32cbf) + (comment "Renesas M32C base family") + (insn-endian big) + (data-endian little) + (word-bitsize 16) +) + +(define-mach + (name m16c) + (comment "Generic M16C cpu") + (cpu m32cbf) +) + +(define-mach + (name m32c) + (comment "Generic M32C cpu") + (cpu m32cbf) +) + +; Model descriptions. + +(define-model + (name m16c) + (comment "m16c") (attrs) + (mach m16c) + + ; `state' is a list of variables for recording model state + ; (state) + (unit u-exec "Execution Unit" () + 1 1 ; issue done + () ; state + () ; inputs + () ; outputs + () ; profile action (default) + ) +) + +(define-model + (name m32c) + (comment "m32c") (attrs) + (mach m32c) + + ; `state' is a list of variables for recording model state + ; (state) + (unit u-exec "Execution Unit" () + 1 1 ; issue done + () ; state + () ; inputs + () ; outputs + () ; profile action (default) + ) +) + +; Macros to simplify MACH attribute specification. + +(define-pmacro all-isas () (ISA m16c,m32c)) +(define-pmacro m16c-isa () (ISA m16c)) +(define-pmacro m32c-isa () (ISA m32c)) + +(define-pmacro MACH16 (MACH m16c)) +(define-pmacro MACH32 (MACH m32c)) + +(define-pmacro (machine size) + (MACH (.sym m size c)) (ISA (.sym m size c))) + +;============================================================= +; Fields +;------------------------------------------------------------- +; Main opcodes +; +(dnf f-0-1 "opcode" (all-isas) 0 1) +(dnf f-0-2 "opcode" (all-isas) 0 2) +(dnf f-0-3 "opcode" (all-isas) 0 3) +(dnf f-0-4 "opcode" (all-isas) 0 4) +(dnf f-1-3 "opcode" (all-isas) 1 3) +(dnf f-2-2 "opcode" (all-isas) 2 2) +(dnf f-3-4 "opcode" (all-isas) 3 4) +(dnf f-3-1 "opcode" (all-isas) 3 1) +(dnf f-4-1 "opcode" (all-isas) 4 1) +(dnf f-4-3 "opcode" (all-isas) 4 3) +(dnf f-4-4 "opcode" (all-isas) 4 4) +(dnf f-4-6 "opcode" (all-isas) 4 6) +(dnf f-5-1 "opcode" (all-isas) 5 1) +(dnf f-5-3 "opcode" (all-isas) 5 3) +(dnf f-6-2 "opcode" (all-isas) 6 2) +(dnf f-7-1 "opcode" (all-isas) 7 1) +(dnf f-8-1 "opcode" (all-isas) 8 1) +(dnf f-8-2 "opcode" (all-isas) 8 2) +(dnf f-8-3 "opcode" (all-isas) 8 3) +(dnf f-8-4 "opcode" (all-isas) 8 4) +(dnf f-8-8 "opcode" (all-isas) 8 8) +(dnf f-9-3 "opcode" (all-isas) 9 3) +(dnf f-9-1 "opcode" (all-isas) 9 1) +(dnf f-10-1 "opcode" (all-isas) 10 1) +(dnf f-10-2 "opcode" (all-isas) 10 2) +(dnf f-10-3 "opcode" (all-isas) 10 3) +(dnf f-11-1 "opcode" (all-isas) 11 1) +(dnf f-12-1 "opcode" (all-isas) 12 1) +(dnf f-12-2 "opcode" (all-isas) 12 2) +(dnf f-12-3 "opcode" (all-isas) 12 3) +(dnf f-12-4 "opcode" (all-isas) 12 4) +(dnf f-12-6 "opcode" (all-isas) 12 6) +(dnf f-13-3 "opcode" (all-isas) 13 3) +(dnf f-14-1 "opcode" (all-isas) 14 1) +(dnf f-14-2 "opcode" (all-isas) 14 2) +(dnf f-15-1 "opcode" (all-isas) 15 1) +(dnf f-16-1 "opcode" (all-isas) 16 1) +(dnf f-16-2 "opcode" (all-isas) 16 2) +(dnf f-16-4 "opcode" (all-isas) 16 4) +(dnf f-16-8 "opcode" (all-isas) 16 8) +(dnf f-18-1 "opcode" (all-isas) 18 1) +(dnf f-18-2 "opcode" (all-isas) 18 2) +(dnf f-18-3 "opcode" (all-isas) 18 3) +(dnf f-20-1 "opcode" (all-isas) 20 1) +(dnf f-20-3 "opcode" (all-isas) 20 3) +(dnf f-20-2 "opcode" (all-isas) 20 2) +(dnf f-20-4 "opcode" (all-isas) 20 4) +(dnf f-21-3 "opcode" (all-isas) 21 3) +(dnf f-24-2 "opcode" (all-isas) 24 2) +(dnf f-24-8 "opcode" (all-isas) 24 8) +(dnf f-32-16 "opcode" (all-isas) 32 16) + +;------------------------------------------------------------- +; Registers +;------------------------------------------------------------- + +(dnf f-src16-rn "source Rn for m16c" (MACH16 m16c-isa) 10 2) +(dnf f-src16-an "source An for m16c" (MACH16 m16c-isa) 11 1) + +(dnf f-src32-an-unprefixed "destination An for m32c" (MACH32 m32c-isa) 11 1) +(dnf f-src32-an-prefixed "destination An for m32c" (MACH32 m32c-isa) 19 1) + +; QI mode gr encoding for m32c is different than for m16c. The hardware +; is indexed using the m16c encoding, so perform the transformation here. +; register m16c m32c +; ---------------------- +; r0l 00'b 10'b +; r0h 01'b 00'b +; r1l 10'b 11'b +; r1h 11'b 01'b +(df f-src32-rn-unprefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 10 2 UINT + ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert + ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract +) +; QI mode gr encoding for m32c is different than for m16c. The hardware +; is indexed using the m16c encoding, so perform the transformation here. +; register m16c m32c +; ---------------------- +; r0l 00'b 10'b +; r0h 01'b 00'b +; r1l 10'b 11'b +; r1h 11'b 01'b +(df f-src32-rn-prefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 18 2 UINT + ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert + ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract +) +; HI mode gr encoding for m32c is different than for m16c. The hardware +; is indexed using the m16c encoding, so perform the transformation here. +; register m16c m32c +; ---------------------- +; r0 00'b 10'b +; r1 01'b 11'b +; r2 10'b 00'b +; r3 11'b 01'b +(df f-src32-rn-unprefixed-HI "source Rn HI for m32c" (MACH32 m32c-isa) 10 2 UINT + ((value pc) (mod USI (add value 2) 4)) ; insert + ((value pc) (mod USI (add value 2) 4)) ; extract +) + +; HI mode gr encoding for m32c is different than for m16c. The hardware +; is indexed using the m16c encoding, so perform the transformation here. +; register m16c m32c +; ---------------------- +; r0 00'b 10'b +; r1 01'b 11'b +; r2 10'b 00'b +; r3 11'b 01'b +(df f-src32-rn-prefixed-HI "source Rn HI for m32c" (MACH32 m32c-isa) 18 2 UINT + ((value pc) (mod USI (add value 2) 4)) ; insert + ((value pc) (mod USI (add value 2) 4)) ; extract +) + +; SI mode gr encoding for m32c is as follows: +; register encoding index +; ------------------------- +; r2r0 10'b 0 +; r3r1 11'b 1 +(df f-src32-rn-unprefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 10 2 UINT + ((value pc) (add USI value 2)) ; insert + ((value pc) (sub USI value 2)) ; extract +) +(df f-src32-rn-prefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 18 2 UINT + ((value pc) (add USI value 2)) ; insert + ((value pc) (sub USI value 2)) ; extract +) + +(dnf f-dst32-rn-ext-unprefixed "destination Rn for m32c" (MACH32 m32c-isa) 9 1) + +(dnf f-dst16-rn "destination Rn for m16c" (MACH16 m16c-isa) 14 2) +(dnf f-dst16-rn-ext "destination Rn for m16c" (MACH16 m16c-isa) 14 1) +(dnf f-dst16-rn-QI-s "destination Rn for m16c" (MACH16 m16c-isa) 5 1) + +(dnf f-dst16-an "destination An for m16c" (MACH16 m16c-isa) 15 1) +(dnf f-dst16-an-s "destination An for m16c" (MACH16 m16c-isa) 4 1) + +(dnf f-dst32-an-unprefixed "destination An for m32c" (MACH32 m32c-isa) 9 1) +(dnf f-dst32-an-prefixed "destination An for m32c" (MACH32 m32c-isa) 17 1) + +; QI mode gr encoding for m32c is different than for m16c. The hardware +; is indexed using the m16c encoding, so perform the transformation here. +; register m16c m32c +; ---------------------- +; r0l 00'b 10'b +; r0h 01'b 00'b +; r1l 10'b 11'b +; r1h 11'b 01'b +(df f-dst32-rn-unprefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 8 2 UINT + ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert + ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract +) +(df f-dst32-rn-prefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 16 2 UINT + ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert + ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract +) +; HI mode gr encoding for m32c is different than for m16c. The hardware +; is indexed using the m16c encoding, so perform the transformation here. +; register m16c m32c +; ---------------------- +; r0 00'b 10'b +; r1 01'b 11'b +; r2 10'b 00'b +; r3 11'b 01'b +(df f-dst32-rn-unprefixed-HI "destination Rn HI for m32c" (MACH32 m32c-isa) 8 2 UINT + ((value pc) (mod USI (add value 2) 4)) ; insert + ((value pc) (mod USI (add value 2) 4)) ; extract +) +(df f-dst32-rn-prefixed-HI "destination Rn HI for m32c" (MACH32 m32c-isa) 16 2 UINT + ((value pc) (mod USI (add value 2) 4)) ; insert + ((value pc) (mod USI (add value 2) 4)) ; extract +) +; SI mode gr encoding for m32c is as follows: +; register encoding index +; ------------------------- +; r2r0 10'b 0 +; r3r1 11'b 1 +(df f-dst32-rn-unprefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 8 2 UINT + ((value pc) (add USI value 2)) ; insert + ((value pc) (sub USI value 2)) ; extract +) +(df f-dst32-rn-prefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 16 2 UINT + ((value pc) (add USI value 2)) ; insert + ((value pc) (sub USI value 2)) ; extract +) + +(dnf f-dst16-1-S "destination R0[hl] for m16c" (MACH16 m16c-isa) 5 1) + +;------------------------------------------------------------- +; Immediates embedded in the base insn +;------------------------------------------------------------- + +(df f-imm-8-s4 "4 bit signed" (all-isas) 8 4 INT #f #f) +(df f-imm-12-s4 "4 bit signed" (all-isas) 12 4 INT #f #f) +(df f-imm-13-u3 "3 bit unsigned" (all-isas) 13 3 UINT #f #f) +(df f-imm-20-s4 "4 bit signed" (all-isas) 20 4 INT #f #f) + +(df f-imm1-S "1 bit immediate for short format binary insns" (MACH32 m32c-isa) 2 1 UINT + ((value pc) (sub USI value 1)) ; insert + ((value pc) (add USI value 1)) ; extract +) + +(dnmf f-imm3-S "3 bit unsigned for short format insns" (all-isas) UINT + (f-2-2 f-7-1) + (sequence () ; insert + (set (ifield f-7-1) (and (sub (ifield f-imm3-S) 1) 1)) + (set (ifield f-2-2) (and (srl (sub (ifield f-imm3-S) 1) 1) #x3)) + ) + (sequence () ; extract + (set (ifield f-imm3-S) (add (or (sll (ifield f-2-2) 1) + (ifield f-7-1)) + 1)) + ) +) + +;------------------------------------------------------------- +; Immediates and displacements beyond the base insn +;------------------------------------------------------------- + +(df f-dsp-8-u6 "6 bit unsigned" (all-isas) 8 6 UINT #f #f) +(df f-dsp-8-u8 "8 bit unsigned" (all-isas) 8 8 UINT #f #f) +(df f-dsp-8-s8 "8 bit signed" (all-isas) 8 8 INT #f #f) +(df f-dsp-10-u6 "6 bit unsigned" (all-isas) 10 6 UINT #f #f) +(df f-dsp-16-u8 "8 bit unsigned" (all-isas) 16 8 UINT #f #f) +(df f-dsp-16-s8 "8 bit signed" (all-isas) 16 8 INT #f #f) +(df f-dsp-24-u8 "8 bit unsigned" (all-isas) 24 8 UINT #f #f) +(df f-dsp-24-s8 "8 bit signed" (all-isas) 24 8 INT #f #f) +(df f-dsp-32-u8 "8 bit unsigned" (all-isas) 32 8 UINT #f #f) +(df f-dsp-32-s8 "8 bit signed" (all-isas) 32 8 INT #f #f) +(df f-dsp-40-u8 "8 bit unsigned" (all-isas) 40 8 UINT #f #f) +(df f-dsp-40-s8 "8 bit signed" (all-isas) 40 8 INT #f #f) +(df f-dsp-48-u8 "8 bit unsigned" (all-isas) 48 8 UINT #f #f) +(df f-dsp-48-s8 "8 bit signed" (all-isas) 48 8 INT #f #f) +(df f-dsp-56-u8 "8 bit unsigned" (all-isas) 56 8 UINT #f #f) +(df f-dsp-56-s8 "8 bit signed" (all-isas) 56 8 INT #f #f) +(df f-dsp-64-u8 "8 bit unsigned" (all-isas) 64 8 UINT #f #f) +(df f-dsp-64-s8 "8 bit signed" (all-isas) 64 8 INT #f #f) + +; Insn opcode endianness is big, but the immediate fields are stored +; in little endian. Handle this here at the field level for all immediate +; fields longer that 1 byte. +; +; CGEN can't handle a field which spans a 32 bit word boundary, so +; handle those as multi ifields. +; +; Take care in expressions using 'srl' or 'sll' as part of some larger +; expression meant to yield sign-extended values. CGEN translates +; uses of those operators into C expressions whose type is 'unsigned +; int', which tends to make the whole expression 'unsigned int'. +; Expressions like (set (ifield foo) X), however, just take X and +; store it in some member of 'struct cgen_fields', all of whose +; members are 'long'. On machines where 'long' is larger than +; 'unsigned int', assigning a "sign-extended" unsigned int to a long +; just produces a very large positive value. insert_normal will +; range-check the field's value and produce odd error messages like +; this: +; +; Error: operand out of range (4160684031 not between -2147483648 and 2147483647) `add.l #-265,-270[fb]' +; +; Annoyingly, the code will work fine on machines where 'long' and +; 'unsigned int' are the same size: the assignment will produce a +; negative number. +; +; Just tell yourself over and over: overflow detection is expensive, +; and you're glad C doesn't do it, because it never happens in real +; life. + +(df f-dsp-8-u16 "16 bit unsigned" (all-isas) 8 16 UINT + ((value pc) (or UHI + (and (srl value 8) #x00ff) + (and (sll value 8) #xff00))) ; insert + ((value pc) (or UHI + (and UHI (srl UHI value 8) #x00ff) + (and UHI (sll UHI value 8) #xff00))) ; extract +) + +(df f-dsp-8-s16 "8 bit signed" (all-isas) 8 16 INT + ((value pc) (ext INT + (trunc HI + (or (and (srl value 8) #x00ff) + (and (sll value 8) #xff00))))) ; insert + ((value pc) (ext INT + (trunc HI + (or (and (srl value 8) #x00ff) + (and (sll value 8) #xff00))))) ; extract +) + +(df f-dsp-16-u16 "16 bit unsigned" (all-isas) 16 16 UINT + ((value pc) (or UHI + (and (srl value 8) #x00ff) + (and (sll value 8) #xff00))) ; insert + ((value pc) (or UHI + (and UHI (srl UHI value 8) #x00ff) + (and UHI (sll UHI value 8) #xff00))) ; extract +) + +(df f-dsp-16-s16 "16 bit signed" (all-isas) 16 16 INT + ((value pc) (ext INT + (trunc HI + (or (and (srl value 8) #x00ff) + (and (sll value 8) #xff00))))) ; insert + ((value pc) (ext INT + (trunc HI + (or (and (srl value 8) #x00ff) + (and (sll value 8) #xff00))))) ; extract +) + +(dnmf f-dsp-24-u16 "16 bit unsigned" (all-isas) UINT + (f-dsp-24-u8 f-dsp-32-u8) + (sequence () ; insert + (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u16) #xff)) + (set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-24-u16) 8) #xff)) + ) + (sequence () ; extract + (set (ifield f-dsp-24-u16) (or (sll (ifield f-dsp-32-u8) 8) + (ifield f-dsp-24-u8))) + ) +) + +(dnmf f-dsp-24-s16 "16 bit signed" (all-isas) INT + (f-dsp-24-u8 f-dsp-32-u8) + (sequence () ; insert + (set (ifield f-dsp-24-u8) + (and (ifield f-dsp-24-s16) #xff)) + (set (ifield f-dsp-32-u8) + (and (srl (ifield f-dsp-24-s16) 8) #xff)) + ) + (sequence () ; extract + (set (ifield f-dsp-24-s16) + (ext INT + (trunc HI (or (sll (ifield f-dsp-32-u8) 8) + (ifield f-dsp-24-u8))))) + ) +) + +(df f-dsp-32-u16 "16 bit unsigned" (all-isas) 32 16 UINT + ((value pc) (or UHI + (and (srl value 8) #x00ff) + (and (sll value 8) #xff00))) ; insert + ((value pc) (or UHI + (and UHI (srl UHI value 8) #x00ff) + (and UHI (sll UHI value 8) #xff00))) ; extract +) + +(df f-dsp-32-s16 "16 bit signed" (all-isas) 32 16 INT + ((value pc) (ext INT + (trunc HI + (or (and (srl value 8) #x00ff) + (and (sll value 8) #xff00))))) ; insert + ((value pc) (ext INT + (trunc HI + (or (and (srl value 8) #x00ff) + (and (sll value 8) #xff00))))) ; extract +) + +(df f-dsp-40-u16 "16 bit unsigned" (all-isas) 40 16 UINT + ((value pc) (or UHI + (and (srl value 8) #x00ff) + (and (sll value 8) #xff00))) ; insert + ((value pc) (or UHI + (and UHI (srl UHI value 8) #x00ff) + (and UHI (sll UHI value 8) #xff00))) ; extract +) + +(df f-dsp-40-s16 "16 bit signed" (all-isas) 40 16 INT + ((value pc) (ext INT + (trunc HI + (or (and (srl value 8) #x00ff) + (and (sll value 8) #xff00))))) ; insert + ((value pc) (ext INT + (trunc HI + (or (and (srl value 8) #x00ff) + (and (sll value 8) #xff00))))) ; extract +) + +(df f-dsp-48-u16 "16 bit unsigned" (all-isas) 48 16 UINT + ((value pc) (or UHI + (and (srl value 8) #x00ff) + (and (sll value 8) #xff00))) ; insert + ((value pc) (or UHI + (and UHI (srl UHI value 8) #x00ff) + (and UHI (sll UHI value 8) #xff00))) ; extract +) + +(df f-dsp-48-s16 "16 bit signed" (all-isas) 48 16 INT + ((value pc) (ext INT + (trunc HI + (or (and (srl value 8) #x00ff) + (and (sll value 8) #xff00))))) ; insert + ((value pc) (ext INT + (trunc HI + (or (and (srl value 8) #x00ff) + (and (sll value 8) #xff00))))) ; extract +) + +(df f-dsp-64-u16 "16 bit unsigned" (all-isas) 64 16 UINT + ((value pc) (or UHI + (and (srl value 8) #x00ff) + (and (sll value 8) #xff00))) ; insert + ((value pc) (or UHI + (and UHI (srl UHI value 8) #x00ff) + (and UHI (sll UHI value 8) #xff00))) ; extract +) +(df f-dsp-8-u24 "24 bit unsigned" (all-isas) 8 24 UINT + ((value pc) (or SI + (or (srl value 16) (and value #xff00)) + (sll (and value #xff) 16))) + ((value pc) (or SI + (or (srl value 16) (and value #xff00)) + (sll (and value #xff) 16))) + ) + +(dnmf f-dsp-16-u24 "24 bit unsigned" (all-isas) UINT + (f-dsp-16-u16 f-dsp-32-u8) + (sequence () ; insert + (set (ifield f-dsp-16-u16) (and (ifield f-dsp-16-u24) #xffff)) + (set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-16-u24) 16) #xff)) + ) + (sequence () ; extract + (set (ifield f-dsp-16-u24) (or (sll (ifield f-dsp-32-u8) 16) + (ifield f-dsp-16-u16))) + ) +) + +(dnmf f-dsp-24-u24 "24 bit unsigned" (all-isas) UINT + (f-dsp-24-u8 f-dsp-32-u16) + (sequence () ; insert + (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u24) #xff)) + (set (ifield f-dsp-32-u16) (and (srl (ifield f-dsp-24-u24) 8) #xffff)) + ) + (sequence () ; extract + (set (ifield f-dsp-24-u24) (or (sll (ifield f-dsp-32-u16) 8) + (ifield f-dsp-24-u8))) + ) +) + +(df f-dsp-32-u24 "24 bit unsigned" (all-isas) 32 24 UINT + ((value pc) (or USI + (or USI + (and (srl value 16) #x0000ff) + (and value #x00ff00)) + (and (sll value 16) #xff0000))) ; insert + ((value pc) (or USI + (or USI + (and USI (srl UHI value 16) #x0000ff) + (and USI value #x00ff00)) + (and USI (sll UHI value 16) #xff0000))) ; extract +) + +(df f-dsp-40-u24 "24 bit unsigned" (all-isas) 40 24 UINT + ((value pc) (or USI + (or USI + (and (srl value 16) #x0000ff) + (and value #x00ff00)) + (and (sll value 16) #xff0000))) ; insert + ((value pc) (or USI + (or USI + (and USI (srl UHI value 16) #x0000ff) + (and USI value #x00ff00)) + (and USI (sll UHI value 16) #xff0000))) ; extract +) + +(dnmf f-dsp-40-s32 "32 bit signed" (all-isas) INT + (f-dsp-40-u24 f-dsp-64-u8) + (sequence () ; insert + (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-40-s32) 24) #xff)) + (set (ifield f-dsp-40-u24) (and (ifield f-dsp-40-s32) #xffffff)) + ) + (sequence () ; extract + (set (ifield f-dsp-40-s32) (or (and (ifield f-dsp-40-u24) #xffffff) + (and (sll (ifield f-dsp-64-u8) 24) #xff000000))) + ) +) + +(dnmf f-dsp-48-u24 "24 bit unsigned" (all-isas) UINT + (f-dsp-48-u16 f-dsp-64-u8) + (sequence () ; insert + (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u24) 16) #xff)) + (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u24) #xffff)) + ) + (sequence () ; extract + (set (ifield f-dsp-48-u24) (or (and (ifield f-dsp-48-u16) #xffff) + (and (sll (ifield f-dsp-64-u8) 16) #xff0000))) + ) +) + +(dnmf f-dsp-16-s32 "32 bit signed" (all-isas) INT + (f-dsp-16-u16 f-dsp-32-u16) + (sequence () ; insert + (set (ifield f-dsp-32-u16) (and (srl (ifield f-dsp-16-s32) 16) #xffff)) + (set (ifield f-dsp-16-u16) (and (ifield f-dsp-16-s32) #xffff)) + ) + (sequence () ; extract + (set (ifield f-dsp-16-s32) (or (and (ifield f-dsp-16-u16) #xffff) + (and (sll (ifield f-dsp-32-u16) 16) #xffff0000))) + ) +) + +(dnmf f-dsp-24-s32 "32 bit signed" (all-isas) INT + (f-dsp-24-u8 f-dsp-32-u24) + (sequence () ; insert + (set (ifield f-dsp-32-u24) (and (srl (ifield f-dsp-24-s32) 8) #xffffff)) + (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-s32) #xff)) + ) + (sequence () ; extract + (set (ifield f-dsp-24-s32) (or (and (ifield f-dsp-24-u8) #xff) + (and (sll (ifield f-dsp-32-u24) 8) #xffffff00))) + ) +) + +(df f-dsp-32-s32 "32 bit signed" (all-isas) 32 32 INT + ((value pc) + + ;; insert + (ext INT + (or SI + (or SI + (and (srl value 24) #x000000ff) + (and (srl value 8) #x0000ff00)) + (or SI + (and (sll value 8) #x00ff0000) + (and (sll value 24) #xff000000))))) + + ;; extract + ((value pc) + (ext INT + (or SI + (or SI + (and (srl value 24) #x000000ff) + (and (srl value 8) #x0000ff00)) + (or SI + (and (sll value 8) #x00ff0000) + (and (sll value 24) #xff000000))))) +) + +(dnmf f-dsp-48-u32 "32 bit unsigned" (all-isas) UINT + (f-dsp-48-u16 f-dsp-64-u16) + (sequence () ; insert + (set (ifield f-dsp-64-u16) (and (srl (ifield f-dsp-48-u32) 16) #xffff)) + (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u32) #xffff)) + ) + (sequence () ; extract + (set (ifield f-dsp-48-u32) (or (and (ifield f-dsp-48-u16) #xffff) + (and (sll (ifield f-dsp-64-u16) 16) #xffff0000))) + ) +) + +(dnmf f-dsp-48-s32 "32 bit signed" (all-isas) INT + (f-dsp-48-u16 f-dsp-64-u16) + (sequence () ; insert + (set (ifield f-dsp-64-u16) (and (srl (ifield f-dsp-48-s32) 16) #xffff)) + (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-s32) #xffff)) + ) + (sequence () ; extract + (set (ifield f-dsp-48-s32) (or (and (ifield f-dsp-48-u16) #xffff) + (and (sll (ifield f-dsp-64-u16) 16) #xffff0000))) + ) +) + +(dnmf f-dsp-56-s16 "16 bit signed" (all-isas) INT + (f-dsp-56-u8 f-dsp-64-u8) + (sequence () ; insert + (set (ifield f-dsp-56-u8) + (and (ifield f-dsp-56-s16) #xff)) + (set (ifield f-dsp-64-u8) + (and (srl (ifield f-dsp-56-s16) 8) #xff)) + ) + (sequence () ; extract + (set (ifield f-dsp-56-s16) + (ext INT + (trunc HI (or (sll (ifield f-dsp-64-u8) 8) + (ifield f-dsp-56-u8))))) + ) +) + +(df f-dsp-64-s16 " 16 bit signed" (all-isas) 64 16 INT + ((value pc) (ext INT + (trunc HI + (or (and (srl value 8) #x00ff) + (and (sll value 8) #xff00))))) ; insert + ((value pc) (ext INT + (trunc HI + (or (and (srl value 8) #x00ff) + (and (sll value 8) #xff00))))) ; extract +) + +;------------------------------------------------------------- +; Bit indices +;------------------------------------------------------------- + +(dnf f-bitno16-S "bit index for m16c" (all-isas) 5 3) +(dnf f-bitno32-prefixed "bit index for m32c" (all-isas) 21 3) +(dnf f-bitno32-unprefixed "bit index for m32c" (all-isas) 13 3) + +(dnmf f-bitbase16-u11-S "unsigned bit,base:11" (all-isas) UINT + (f-bitno16-S f-dsp-8-u8) + (sequence () ; insert + (set (ifield f-bitno16-S) (and f-bitbase16-u11-S #x7)) + (set (ifield f-dsp-8-u8) (and (srl (ifield f-bitbase16-u11-S) 3) #xff)) + ) + (sequence () ; extract + (set (ifield f-bitbase16-u11-S) (or (sll (ifield f-dsp-8-u8) 3) + (ifield f-bitno16-S))) + ) +) + +(dnmf f-bitbase32-16-u11-unprefixed "unsigned bit,base:11" (all-isas) UINT + (f-bitno32-unprefixed f-dsp-16-u8) + (sequence () ; insert + (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u11-unprefixed #x7)) + (set (ifield f-dsp-16-u8) (and (srl (ifield f-bitbase32-16-u11-unprefixed) 3) #xff)) + ) + (sequence () ; extract + (set (ifield f-bitbase32-16-u11-unprefixed) (or (sll (ifield f-dsp-16-u8) 3) + (ifield f-bitno32-unprefixed))) + ) +) +(dnmf f-bitbase32-16-s11-unprefixed "signed bit,base:11" (all-isas) INT + (f-bitno32-unprefixed f-dsp-16-s8) + (sequence () ; insert + (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-s11-unprefixed #x7)) + (set (ifield f-dsp-16-s8) (sra INT (ifield f-bitbase32-16-s11-unprefixed) 3)) + ) + (sequence () ; extract + (set (ifield f-bitbase32-16-s11-unprefixed) (or (sll (ifield f-dsp-16-s8) 3) + (ifield f-bitno32-unprefixed))) + ) +) +(dnmf f-bitbase32-16-u19-unprefixed "unsigned bit,base:19" (all-isas) UINT + (f-bitno32-unprefixed f-dsp-16-u16) + (sequence () ; insert + (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u19-unprefixed #x7)) + (set (ifield f-dsp-16-u16) (and (srl (ifield f-bitbase32-16-u19-unprefixed) 3) #xffff)) + ) + (sequence () ; extract + (set (ifield f-bitbase32-16-u19-unprefixed) (or (sll (ifield f-dsp-16-u16) 3) + (ifield f-bitno32-unprefixed))) + ) +) +(dnmf f-bitbase32-16-s19-unprefixed "signed bit,base:11" (all-isas) INT + (f-bitno32-unprefixed f-dsp-16-s16) + (sequence () ; insert + (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-s19-unprefixed #x7)) + (set (ifield f-dsp-16-s16) (sra INT (ifield f-bitbase32-16-s19-unprefixed) 3)) + ) + (sequence () ; extract + (set (ifield f-bitbase32-16-s19-unprefixed) (or (sll (ifield f-dsp-16-s16) 3) + (ifield f-bitno32-unprefixed))) + ) +) +; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-( +(dnmf f-bitbase32-16-u27-unprefixed "unsigned bit,base:27" (all-isas) UINT + (f-bitno32-unprefixed f-dsp-16-u16 f-dsp-32-u8) + (sequence () ; insert + (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u27-unprefixed #x7)) + (set (ifield f-dsp-16-u16) (and (srl (ifield f-bitbase32-16-u27-unprefixed) 3) #xffff)) + (set (ifield f-dsp-32-u8) (and (srl (ifield f-bitbase32-16-u27-unprefixed) 19) #xff)) + ) + (sequence () ; extract + (set (ifield f-bitbase32-16-u27-unprefixed) (or (sll (ifield f-dsp-16-u16) 3) + (or (sll (ifield f-dsp-32-u8) 19) + (ifield f-bitno32-unprefixed)))) + ) +) +(dnmf f-bitbase32-24-u11-prefixed "unsigned bit,base:11" (all-isas) UINT + (f-bitno32-prefixed f-dsp-24-u8) + (sequence () ; insert + (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u11-prefixed #x7)) + (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u11-prefixed) 3) #xff)) + ) + (sequence () ; extract + (set (ifield f-bitbase32-24-u11-prefixed) (or (sll (ifield f-dsp-24-u8) 3) + (ifield f-bitno32-prefixed))) + ) +) +(dnmf f-bitbase32-24-s11-prefixed "signed bit,base:11" (all-isas) INT + (f-bitno32-prefixed f-dsp-24-s8) + (sequence () ; insert + (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-s11-prefixed #x7)) + (set (ifield f-dsp-24-s8) (sra INT (ifield f-bitbase32-24-s11-prefixed) 3)) + ) + (sequence () ; extract + (set (ifield f-bitbase32-24-s11-prefixed) (or (sll (ifield f-dsp-24-s8) 3) + (ifield f-bitno32-prefixed))) + ) +) +; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-( +(dnmf f-bitbase32-24-u19-prefixed "unsigned bit,base:19" (all-isas) UINT + (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-u8) + (sequence () ; insert + (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u19-prefixed #x7)) + (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u19-prefixed) 3) #xff)) + (set (ifield f-dsp-32-u8) (and (srl (ifield f-bitbase32-24-u19-prefixed) 11) #xff)) + ) + (sequence () ; extract + (set (ifield f-bitbase32-24-u19-prefixed) (or (sll (ifield f-dsp-24-u8) 3) + (or (sll (ifield f-dsp-32-u8) 11) + (ifield f-bitno32-prefixed)))) + ) +) +; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-( +(dnmf f-bitbase32-24-s19-prefixed "signed bit,base:11" (all-isas) INT + (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-s8) + (sequence () ; insert + (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-s19-prefixed #x7)) + (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-s19-prefixed) 3) #xff)) + (set (ifield f-dsp-32-s8) (sra INT (ifield f-bitbase32-24-s19-prefixed) 11)) + ) + (sequence () ; extract + (set (ifield f-bitbase32-24-s19-prefixed) (or (sll (ifield f-dsp-24-u8) 3) + (or (sll (ifield f-dsp-32-s8) 11) + (ifield f-bitno32-prefixed)))) + ) +) +; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-( +(dnmf f-bitbase32-24-u27-prefixed "unsigned bit,base:27" (all-isas) UINT + (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-u16) + (sequence () ; insert + (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u27-prefixed #x7)) + (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u27-prefixed) 3) #xff)) + (set (ifield f-dsp-32-u16) (and (srl (ifield f-bitbase32-24-u27-prefixed) 11) #xffff)) + ) + (sequence () ; extract + (set (ifield f-bitbase32-24-u27-prefixed) (or (sll (ifield f-dsp-24-u8) 3) + (or (sll (ifield f-dsp-32-u16) 11) + (ifield f-bitno32-prefixed)))) + ) +) + +;------------------------------------------------------------- +; Labels +;------------------------------------------------------------- + +(df f-lab-5-3 "3 bit pc relative unsigned offset" (PCREL-ADDR all-isas) 5 3 UINT + ((value pc) (sub SI value (add SI pc 2))) ; insert + ((value pc) (add SI value (add SI pc 2))) ; extract +) +(dnmf f-lab32-jmp-s "unsigned 3 bit pc relative offset" (PCREL-ADDR all-isas) UINT + (f-2-2 f-7-1) + (sequence ((SI val)) ; insert + (set val (sub (sub (ifield f-lab32-jmp-s) pc) 2)) + (set (ifield f-7-1) (and val #x1)) + (set (ifield f-2-2) (srl val 1)) + ) + (sequence () ; extract + (set (ifield f-lab32-jmp-s) (add pc (add (or (sll (ifield f-2-2) 1) + (ifield f-7-1)) + 2))) + ) +) +(df f-lab-8-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 8 8 INT + ((value pc) (sub SI value (add SI pc 1))) ; insert + ((value pc) (add SI value (add SI pc 1))) ; extract +) +(df f-lab-8-16 "16 bit pc relative signed offset" (PCREL-ADDR SIGN-OPT all-isas) 8 16 UINT + ((value pc) (or SI (sll (and (sub value (add pc 1)) #xff) 8) + (srl (and (sub value (add pc 1)) #xffff) 8))) + ((value pc) (add SI (or (srl (and value #xffff) 8) + (sra (sll (and value #xff) 24) 16)) (add pc 1))) + ) +(df f-lab-8-24 "24 bit absolute" (all-isas ABS-ADDR) 8 24 UINT + ((value pc) (or SI + (or (srl value 16) (and value #xff00)) + (sll (and value #xff) 16))) + ((value pc) (or SI + (or (srl value 16) (and value #xff00)) + (sll (and value #xff) 16))) + ) +(df f-lab-16-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 16 8 INT + ((value pc) (sub SI value (add SI pc 2))) ; insert + ((value pc) (add SI value (add SI pc 2))) ; extract +) +(df f-lab-24-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 24 8 INT + ((value pc) (sub SI value (add SI pc 2))) ; insert + ((value pc) (add SI value (add SI pc 2))) ; extract +) +(df f-lab-32-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 32 8 INT + ((value pc) (sub SI value (add SI pc 2))) ; insert + ((value pc) (add SI value (add SI pc 2))) ; extract +) +(df f-lab-40-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 40 8 INT + ((value pc) (sub SI value (add SI pc 2))) ; insert + ((value pc) (add SI value (add SI pc 2))) ; extract +) + +;------------------------------------------------------------- +; Condition codes +;------------------------------------------------------------- + +(dnf f-cond16 "condition code" (all-isas) 12 4) +(dnf f-cond16j-5 "condition code" (all-isas) 5 3) + +(dnmf f-cond32 "condition code" (all-isas) UINT + (f-9-1 f-13-3) + (sequence () ; insert + (set (ifield f-9-1) (and (srl (ifield f-cond32) 3) 1)) + (set (ifield f-13-3) (and (ifield f-cond32) #x7)) + ) + (sequence () ; extract + (set (ifield f-cond32) (or (sll (ifield f-9-1) 3) + (ifield f-13-3))) + ) +) + +(dnmf f-cond32j "condition code" (all-isas) UINT + (f-1-3 f-7-1) + (sequence () ; insert + (set (ifield f-1-3) (and (srl (ifield f-cond32j) 1) #x7)) + (set (ifield f-7-1) (and (ifield f-cond32j) #x1)) + ) + (sequence () ; extract + (set (ifield f-cond32j) (or (sll (ifield f-1-3) 1) + (ifield f-7-1))) + ) +) + +;============================================================= +; Hardware +; +(dnh h-pc "program counter" (PC all-isas) (pc USI) () () ()) + +;------------------------------------------------------------- +; General registers +; The actual registers are 16 bits +;------------------------------------------------------------- + +(define-hardware + (name h-gr) + (comment "general 16 bit registers") + (attrs all-isas CACHE-ADDR) + (type register HI (4)) + (indices keyword "" (("r0" 0) ("r1" 1) ("r2" 2) ("r3" 3)))) + +; Define different views of the grs as VIRTUAL with getter/setter specs +; +(define-hardware + (name h-gr-QI) + (comment "general 8 bit registers") + (attrs all-isas VIRTUAL) + (type register QI (4)) + (indices keyword "" (("r0l" 0) ("r0h" 1) ("r1l" 2) ("r1h" 3))) + (get (index) (and (if SI (mod index 2) + (srl (reg h-gr (div index 2)) 8) + (reg h-gr (div index 2))) + #xff)) + (set (index newval) (set (reg h-gr (div index 2)) + (if SI (mod index 2) + (or (and (reg h-gr (div index 2)) #xff) + (sll (and newval #xff) 8)) + (or (and (reg h-gr (div index 2)) #xff00) + (and newval #xff)))))) + +(define-hardware + (name h-gr-HI) + (comment "general 16 bit registers") + (attrs all-isas VIRTUAL) + (type register HI (4)) + (indices keyword "" (("r0" 0) ("r1" 1) ("r2" 2) ("r3" 3))) + (get (index) (reg h-gr index)) + (set (index newval) (set (reg h-gr index) newval))) + +(define-hardware + (name h-gr-SI) + (comment "general 32 bit registers") + (attrs all-isas VIRTUAL) + (type register SI (2)) + (indices keyword "" (("r2r0" 0) ("r3r1" 1))) + (get (index) (or SI + (and (reg h-gr index) #xffff) + (and (sll (reg h-gr (add index 2)) 16) #xffff0000))) + (set (index newval) (sequence () + (set (reg h-gr index) (and newval #xffff)) + (set (reg h-gr (add index 2)) (srl newval 16))))) + +(define-hardware + (name h-gr-ext-QI) + (comment "general 16 bit registers") + (attrs all-isas VIRTUAL) + (type register HI (2)) + (indices keyword "" (("r0l" 0) ("r1l" 1))) + (get (index) (reg h-gr-QI (mul index 2))) + (set (index newval) (set (reg h-gr (mul index 2)) newval))) + +(define-hardware + (name h-gr-ext-HI) + (comment "general 16 bit registers") + (attrs all-isas VIRTUAL) + (type register SI (2)) + (indices keyword "" (("r0" 0) ("r1" 1))) + (get (index) (reg h-gr (mul index 2))) + (set (index newval) (set (reg h-gr-SI index) newval))) + +(define-hardware + (name h-r0l) + (comment "r0l register") + (attrs all-isas VIRTUAL) + (type register QI) + (indices keyword "" (("r0l" 0))) + (get () (reg h-gr-QI 0)) + (set (newval) (set (reg h-gr-QI 0) newval))) + +(define-hardware + (name h-r0h) + (comment "r0h register") + (attrs all-isas VIRTUAL) + (type register QI) + (indices keyword "" (("r0h" 0))) + (get () (reg h-gr-QI 1)) + (set (newval) (set (reg h-gr-QI 1) newval))) + +(define-hardware + (name h-r1l) + (comment "r1l register") + (attrs all-isas VIRTUAL) + (type register QI) + (indices keyword "" (("r1l" 0))) + (get () (reg h-gr-QI 2)) + (set (newval) (set (reg h-gr-QI 2) newval))) + +(define-hardware + (name h-r1h) + (comment "r1h register") + (attrs all-isas VIRTUAL) + (type register QI) + (indices keyword "" (("r1h" 0))) + (get () (reg h-gr-QI 3)) + (set (newval) (set (reg h-gr-QI 3) newval))) + +(define-hardware + (name h-r0) + (comment "r0 register") + (attrs all-isas VIRTUAL) + (type register HI) + (indices keyword "" (("r0" 0))) + (get () (reg h-gr 0)) + (set (newval) (set (reg h-gr 0) newval))) + +(define-hardware + (name h-r1) + (comment "r1 register") + (attrs all-isas VIRTUAL) + (type register HI) + (indices keyword "" (("r1" 0))) + (get () (reg h-gr 1)) + (set (newval) (set (reg h-gr 1) newval))) + +(define-hardware + (name h-r2) + (comment "r2 register") + (attrs all-isas VIRTUAL) + (type register HI) + (indices keyword "" (("r2" 0))) + (get () (reg h-gr 2)) + (set (newval) (set (reg h-gr 2) newval))) + +(define-hardware + (name h-r3) + (comment "r3 register") + (attrs all-isas VIRTUAL) + (type register HI) + (indices keyword "" (("r3" 0))) + (get () (reg h-gr 3)) + (set (newval) (set (reg h-gr 3) newval))) + +(define-hardware + (name h-r0l-r0h) + (comment "r0l or r0h") + (attrs all-isas VIRTUAL) + (type register QI (2)) + (indices keyword "" (("r0l" 0) ("r0h" 1))) + (get (index) (reg h-gr-QI index)) + (set (index newval) (set (reg h-gr-QI index) newval))) + +(define-hardware + (name h-r2r0) + (comment "r2r0 register") + (attrs all-isas VIRTUAL) + (type register SI) + (indices keyword "" (("r2r0" 0))) + (get () (or (sll (reg h-gr 2) 16) (reg h-gr 0))) + (set (newval) + (sequence () + (set (reg h-gr 0) newval) + (set (reg h-gr 2) (sra newval 16))))) + +(define-hardware + (name h-r3r1) + (comment "r3r1 register") + (attrs all-isas VIRTUAL) + (type register SI) + (indices keyword "" (("r3r1" 0))) + (get () (or (sll (reg h-gr 3) 16) (reg h-gr 1))) + (set (newval) + (sequence () + (set (reg h-gr 1) newval) + (set (reg h-gr 3) (sra newval 16))))) + +(define-hardware + (name h-r1r2r0) + (comment "r1r2r0 register") + (attrs all-isas VIRTUAL) + (type register DI) + (indices keyword "" (("r1r2r0" 0))) + (get () (or DI (sll DI (reg h-gr 1) 32) (or (sll (reg h-gr 2) 16) (reg h-gr 0)))) + (set (newval) + (sequence () + (set (reg h-gr 0) newval) + (set (reg h-gr 2) (sra newval 16)) + (set (reg h-gr 1) (sra newval 32))))) + +;------------------------------------------------------------- +; Address registers +;------------------------------------------------------------- + +(define-hardware + (name h-ar) + (comment "address registers") + (attrs all-isas) + (type register USI (2)) + (indices keyword "" (("a0" 0) ("a1" 1))) + (get (index) (c-call USI "h_ar_get_handler" index)) + (set (index newval) (c-call VOID "h_ar_set_handler" index newval))) + +; Define different views of the ars as VIRTUAL with getter/setter specs +(define-hardware + (name h-ar-QI) + (comment "8 bit view of address register") + (attrs all-isas VIRTUAL) + (type register QI (2)) + (indices keyword "" (("a0" 0) ("a1" 1))) + (get (index) (reg h-ar index)) + (set (index newval) (set (reg h-ar index) newval))) + +(define-hardware + (name h-ar-HI) + (comment "16 bit view of address register") + (attrs all-isas VIRTUAL) + (type register HI (2)) + (indices keyword "" (("a0" 0) ("a1" 1))) + (get (index) (reg h-ar index)) + (set (index newval) (set (reg h-ar index) newval))) + +(define-hardware + (name h-ar-SI) + (comment "32 bit view of address register") + (attrs all-isas VIRTUAL) + (type register SI) + (indices keyword "" (("a1a0" 0))) + (get () (or SI (sll SI (ext SI (reg h-ar 1)) 16) (ext SI (reg h-ar 0)))) + (set (newval) (sequence () + (set (reg h-ar 0) (and newval #xffff)) + (set (reg h-ar 1) (and (srl newval 16) #xffff))))) + +(define-hardware + (name h-a0) + (comment "16 bit view of address register") + (attrs all-isas VIRTUAL) + (type register HI) + (indices keyword "" (("a0" 0))) + (get () (reg h-ar 0)) + (set (newval) (set (reg h-ar 0) newval))) + +(define-hardware + (name h-a1) + (comment "16 bit view of address register") + (attrs all-isas VIRTUAL) + (type register HI) + (indices keyword "" (("a1" 1))) + (get () (reg h-ar 1)) + (set (newval) (set (reg h-ar 1) newval))) + +; SB Register +(define-hardware + (name h-sb) + (comment "SB register") + (attrs all-isas) + (type register USI) + (get () (c-call USI "h_sb_get_handler")) + (set (newval) (c-call VOID "h_sb_set_handler" newval)) +) + +; FB Register +(define-hardware + (name h-fb) + (comment "FB register") + (attrs all-isas) + (type register USI) + (get () (c-call USI "h_fb_get_handler")) + (set (newval) (c-call VOID "h_fb_set_handler" newval)) +) + +; SP Register +(define-hardware + (name h-sp) + (comment "SP register") + (attrs all-isas) + (type register USI) + (get () (c-call USI "h_sp_get_handler")) + (set (newval) (c-call VOID "h_sp_set_handler" newval)) +) + +;------------------------------------------------------------- +; condition-code bits +;------------------------------------------------------------- + +(define-hardware + (name h-sbit) + (comment "sign bit") + (attrs all-isas) + (type register BI) +) + +(define-hardware + (name h-zbit) + (comment "zero bit") + (attrs all-isas) + (type register BI) +) + +(define-hardware + (name h-obit) + (comment "overflow bit") + (attrs all-isas) + (type register BI) +) + +(define-hardware + (name h-cbit) + (comment "carry bit") + (attrs all-isas) + (type register BI) +) + +(define-hardware + (name h-ubit) + (comment "stack pointer select bit") + (attrs all-isas) + (type register BI) +) + +(define-hardware + (name h-ibit) + (comment "interrupt enable bit") + (attrs all-isas) + (type register BI) +) + +(define-hardware + (name h-bbit) + (comment "register bank select bit") + (attrs all-isas) + (type register BI) +) + +(define-hardware + (name h-dbit) + (comment "debug bit") + (attrs all-isas) + (type register BI) +) + +(define-hardware + (name h-dct0) + (comment "dma transfer count 000") + (attrs all-isas) + (type register UHI) +) +(define-hardware + (name h-dct1) + (comment "dma transfer count 001") + (attrs all-isas) + (type register UHI) +) +(define-hardware + (name h-svf) + (comment "save flag 011") + (attrs all-isas) + (type register UHI) +) +(define-hardware + (name h-drc0) + (comment "dma transfer count reload 100") + (attrs all-isas) + (type register UHI) +) +(define-hardware + (name h-drc1) + (comment "dma transfer count reload 101") + (attrs all-isas) + (type register UHI) +) +(define-hardware + (name h-dmd0) + (comment "dma mode 110") + (attrs all-isas) + (type register UQI) +) +(define-hardware + (name h-dmd1) + (comment "dma mode 111") + (attrs all-isas) + (type register UQI) +) +(define-hardware + (name h-intb) + (comment "interrupt table 000") + (attrs all-isas) + (type register USI) +) +(define-hardware + (name h-svp) + (comment "save pc 100") + (attrs all-isas) + (type register UHI) +) +(define-hardware + (name h-vct) + (comment "vector 101") + (attrs all-isas) + (type register USI) +) +(define-hardware + (name h-isp) + (comment "interrupt stack ptr 111") + (attrs all-isas) + (type register USI) +) +(define-hardware + (name h-dma0) + (comment "dma mem addr 010") + (attrs all-isas) + (type register USI) +) +(define-hardware + (name h-dma1) + (comment "dma mem addr 011") + (attrs all-isas) + (type register USI) +) +(define-hardware + (name h-dra0) + (comment "dma mem addr reload 100") + (attrs all-isas) + (type register USI) +) +(define-hardware + (name h-dra1) + (comment "dma mem addr reload 101") + (attrs all-isas) + (type register USI) +) +(define-hardware + (name h-dsa0) + (comment "dma sfr addr 110") + (attrs all-isas) + (type register USI) +) +(define-hardware + (name h-dsa1) + (comment "dma sfr addr 111") + (attrs all-isas) + (type register USI) +) + +;------------------------------------------------------------- +; Condition code operand hardware +;------------------------------------------------------------- + +(define-hardware + (name h-cond16) + (comment "condition code hardware for m16c") + (attrs m16c-isa MACH16) + (type immediate UQI) + (values keyword "" + (("geu" #x00) ("c" #x00) + ("gtu" #x01) + ("eq" #x02) ("z" #x02) + ("n" #x03) + ("le" #x04) + ("o" #x05) + ("ge" #x06) + ("ltu" #xf8) ("nc" #xf8) + ("leu" #xf9) + ("ne" #xfa) ("nz" #xfa) + ("pz" #xfb) + ("gt" #xfc) + ("no" #xfd) + ("lt" #xfe) + ) + ) +) +(define-hardware + (name h-cond16c) + (comment "condition code hardware for m16c") + (attrs m16c-isa MACH16) + (type immediate UQI) + (values keyword "" + (("geu" #x00) ("c" #x00) + ("gtu" #x01) + ("eq" #x02) ("z" #x02) + ("n" #x03) + ("ltu" #x04) ("nc" #x04) + ("leu" #x05) + ("ne" #x06) ("nz" #x06) + ("pz" #x07) + ("le" #x08) + ("o" #x09) + ("ge" #x0a) + ("gt" #x0c) + ("no" #x0d) + ("lt" #x0e) + ) + ) +) +(define-hardware + (name h-cond16j) + (comment "condition code hardware for m16c") + (attrs m16c-isa MACH16) + (type immediate UQI) + (values keyword "" + (("le" #x08) + ("o" #x09) + ("ge" #x0a) + ("gt" #x0c) + ("no" #x0d) + ("lt" #x0e) + ) + ) +) +(define-hardware + (name h-cond16j-5) + (comment "condition code hardware for m16c") + (attrs m16c-isa MACH16) + (type immediate UQI) + (values keyword "" + (("geu" #x00) ("c" #x00) + ("gtu" #x01) + ("eq" #x02) ("z" #x02) + ("n" #x03) + ("ltu" #x04) ("nc" #x04) + ("leu" #x05) + ("ne" #x06) ("nz" #x06) + ("pz" #x07) + ) + ) +) + +(define-hardware + (name h-cond32) + (comment "condition code hardware for m32c") + (attrs m32c-isa MACH32) + (type immediate UQI) + (values keyword "" + (("ltu" #x00) ("nc" #x00) + ("leu" #x01) + ("ne" #x02) ("nz" #x02) + ("pz" #x03) + ("no" #x04) + ("gt" #x05) + ("ge" #x06) + ("geu" #x08) ("c" #x08) + ("gtu" #x09) + ("eq" #x0a) ("z" #x0a) + ("n" #x0b) + ("o" #x0c) + ("le" #x0d) + ("lt" #x0e) + ) + ) +) + +(define-hardware + (name h-cr1-32) + (comment "control registers") + (attrs m32c-isa MACH32) + (type immediate UQI) + (values keyword "" (("dct0" 0) ("dct1" 1) ("flg" 2) ("svf" 3) ("drc0" 4) + ("drc1" 5) ("dmd0" 6) ("dmd1" 7)))) +(define-hardware + (name h-cr2-32) + (comment "control registers") + (attrs m32c-isa MACH32) + (type immediate UQI) + (values keyword "" (("intb" 0) ("sp" 1) ("sb" 2) ("fb" 3) ("svp" 4) + ("vct" 5) ("isp" 7)))) + +(define-hardware + (name h-cr3-32) + (comment "control registers") + (attrs m32c-isa MACH32) + (type immediate UQI) + (values keyword "" (("dma0" 2) ("dma1" 3) ("dra0" 4) + ("dra1" 5) ("dsa0" 6) ("dsa1" 7)))) +(define-hardware + (name h-cr-16) + (comment "control registers") + (attrs m16c-isa MACH16) + (type immediate UQI) + (values keyword "" (("intbl" 1) ("intbh" 2) ("flg" 3) ("isp" 4) + ("sp" 5) ("sb" 6) ("fb" 7)))) + +(define-hardware + (name h-flags) + (comment "flag hardware for m32c") + (attrs all-isas) + (type immediate UQI) + (values keyword "" + (("c" #x0) + ("d" #x1) + ("z" #x2) + ("s" #x3) + ("b" #x4) + ("o" #x5) + ("i" #x6) + ("u" #x7) + ) + ) +) + +;------------------------------------------------------------- +; Misc helper hardware +;------------------------------------------------------------- + +(define-hardware + (name h-shimm) + (comment "shift immediate") + (attrs all-isas) + (type immediate (INT 4)) + (values keyword "" (("1" 0) ("2" 1) ("3" 2) ("4" 3) ("5" 4) ("6" 5) ("7" 6) + ("8" 7) ("-1" -8) ("-2" -7) ("-3" -6) ("-4" -5) ("-5" -4) + ("-6" -3) ("-7" -2) ("-8" -1) + ))) +(define-hardware + (name h-bit-index) + (comment "bit index for the next insn") + (attrs m32c-isa MACH32) + (type register UHI) +) +(define-hardware + (name h-src-index) + (comment "source index for the next insn") + (attrs m32c-isa MACH32) + (type register UHI) +) +(define-hardware + (name h-dst-index) + (comment "destination index for the next insn") + (attrs m32c-isa MACH32) + (type register UHI) +) +(define-hardware + (name h-src-indirect) + (comment "indirect src for the next insn") + (attrs all-isas) + (type register UHI) +) +(define-hardware + (name h-dst-indirect) + (comment "indirect dst for the next insn") + (attrs all-isas) + (type register UHI) +) +(define-hardware + (name h-none) + (comment "for storing unused values") + (attrs m32c-isa MACH32) + (type register SI) +) + +;============================================================= +; Operands +;------------------------------------------------------------- +; Source Registers +;------------------------------------------------------------- + +(dnop Src16RnQI "general register QI view" (MACH16 m16c-isa) h-gr-QI f-src16-rn) +(dnop Src16RnHI "general register QH view" (MACH16 m16c-isa) h-gr-HI f-src16-rn) + +(dnop Src32RnUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-src32-rn-unprefixed-QI) +(dnop Src32RnUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-src32-rn-unprefixed-HI) +(dnop Src32RnUnprefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-src32-rn-unprefixed-SI) + +(dnop Src32RnPrefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-src32-rn-prefixed-QI) +(dnop Src32RnPrefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-src32-rn-prefixed-HI) +(dnop Src32RnPrefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-src32-rn-prefixed-SI) + +(dnop Src16An "address register" (MACH16 m16c-isa) h-ar f-src16-an) +(dnop Src16AnQI "address register QI view" (MACH16 m16c-isa) h-ar-QI f-src16-an) +(dnop Src16AnHI "address register HI view" (MACH16 m16c-isa) h-ar-HI f-src16-an) + +(dnop Src32AnUnprefixed "address register" (MACH32 m32c-isa) h-ar f-src32-an-unprefixed) +(dnop Src32AnUnprefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-src32-an-unprefixed) +(dnop Src32AnUnprefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-src32-an-unprefixed) +(dnop Src32AnUnprefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-src32-an-unprefixed) + +(dnop Src32AnPrefixed "address register" (MACH32 m32c-isa) h-ar f-src32-an-prefixed) +(dnop Src32AnPrefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-src32-an-prefixed) +(dnop Src32AnPrefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-src32-an-prefixed) +(dnop Src32AnPrefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-src32-an-prefixed) + +; Destination Registers +; +(dnop Dst16RnQI "general register QI view" (MACH16 m16c-isa) h-gr-QI f-dst16-rn) +(dnop Dst16RnHI "general register HI view" (MACH16 m16c-isa) h-gr-HI f-dst16-rn) +(dnop Dst16RnSI "general register SI view" (MACH16 m16c-isa) h-gr-SI f-dst16-rn) +(dnop Dst16RnExtQI "general register QI/HI view for 'ext' insns" (MACH16 m16c-isa) h-gr-ext-QI f-dst16-rn-ext) + +(dnop Dst32R0QI-S "general register QI view" (MACH32 m32c-isa) h-r0l f-nil) +(dnop Dst32R0HI-S "general register HI view" (MACH32 m32c-isa) h-r0 f-nil) + +(dnop Dst32RnUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-unprefixed-QI) +(dnop Dst32RnUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-dst32-rn-unprefixed-HI) +(dnop Dst32RnUnprefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-dst32-rn-unprefixed-SI) +(dnop Dst32RnExtUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-ext-QI f-dst32-rn-ext-unprefixed) +(dnop Dst32RnExtUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-ext-HI f-dst32-rn-ext-unprefixed) + +(dnop Dst32RnPrefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-prefixed-QI) +(dnop Dst32RnPrefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-dst32-rn-prefixed-HI) +(dnop Dst32RnPrefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-dst32-rn-prefixed-SI) + +(dnop Dst16RnQI-S "general register QI view" (MACH16 m16c-isa) h-r0l-r0h f-dst16-rn-QI-s) + +(dnop Dst16AnQI-S "address register QI view" (MACH16 m16c-isa) h-ar-QI f-dst16-rn-QI-s) + +(dnop Bit16Rn "general register bit view" (MACH16 m16c-isa) h-gr-HI f-dst16-rn) + +(dnop Bit32RnPrefixed "general register bit view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-prefixed-QI) +(dnop Bit32RnUnprefixed "general register bit view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-unprefixed-QI) + +(dnop R0 "r0" (all-isas) h-r0 f-nil) +(dnop R1 "r1" (all-isas) h-r1 f-nil) +(dnop R2 "r2" (all-isas) h-r2 f-nil) +(dnop R3 "r3" (all-isas) h-r3 f-nil) +(dnop R0l "r0l" (all-isas) h-r0l f-nil) +(dnop R0h "r0h" (all-isas) h-r0h f-nil) +(dnop R2R0 "r2r0" (all-isas) h-r2r0 f-nil) +(dnop R3R1 "r3r1" (all-isas) h-r3r1 f-nil) +(dnop R1R2R0 "r1r2r0" (all-isas) h-r1r2r0 f-nil) + +(dnop Dst16An "address register" (MACH16 m16c-isa) h-ar f-dst16-an) +(dnop Dst16AnQI "address register QI view" (MACH16 m16c-isa) h-ar-QI f-dst16-an) +(dnop Dst16AnHI "address register HI view" (MACH16 m16c-isa) h-ar-HI f-dst16-an) +(dnop Dst16AnSI "address register SI view" (MACH16 m16c-isa) h-ar-SI f-dst16-an) +(dnop Dst16An-S "address register HI view" (MACH16 m16c-isa) h-ar-HI f-dst16-an-s) + +(dnop Dst32AnUnprefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed) +(dnop Dst32AnUnprefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-dst32-an-unprefixed) +(dnop Dst32AnUnprefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-dst32-an-unprefixed) +(dnop Dst32AnUnprefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed) + +(dnop Dst32AnExtUnprefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed) + +(dnop Dst32AnPrefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed) +(dnop Dst32AnPrefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-dst32-an-prefixed) +(dnop Dst32AnPrefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-dst32-an-prefixed) +(dnop Dst32AnPrefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed) + +(dnop Bit16An "address register bit view" (MACH16 m16c-isa) h-ar f-dst16-an) + +(dnop Bit32AnPrefixed "address register bit" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed) +(dnop Bit32AnUnprefixed "address register bit" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed) + +(dnop A0 "a0" (all-isas) h-a0 f-nil) +(dnop A1 "a1" (all-isas) h-a1 f-nil) + +(dnop sb "SB register" (all-isas SEM-ONLY) h-sb f-nil) +(dnop fb "FB register" (all-isas SEM-ONLY) h-fb f-nil) +(dnop sp "SP register" (all-isas SEM-ONLY) h-sp f-nil) + +(define-full-operand SrcDst16-r0l-r0h-S-normal "r0l/r0h pair" (MACH16 m16c-isa) + h-sint DFLT f-5-1 + ((parse "r0l_r0h") (print "r0l_r0h")) () () +) + +(define-full-operand Regsetpop "popm regset" (all-isas) h-uint + DFLT f-8-8 ((parse "pop_regset") (print "pop_regset")) () ()) +(define-full-operand Regsetpush "pushm regset" (all-isas) h-uint + DFLT f-8-8 ((parse "push_regset") (print "push_regset")) () ()) + +(dnop Rn16-push-S "r0[lh]" (MACH16 m16c-isa) h-gr-QI f-4-1) +(dnop An16-push-S "a[01]" (MACH16 m16c-isa) h-ar-HI f-4-1) + +;------------------------------------------------------------- +; Offsets and absolutes +;------------------------------------------------------------- + +(define-full-operand Dsp-8-u6 "unsigned 6 bit displacement at offset 8 bits" (all-isas) + h-uint DFLT f-dsp-8-u6 + ((parse "unsigned6")) () () +) +(define-full-operand Dsp-8-u8 "unsigned 8 bit displacement at offset 8 bits" (all-isas) + h-uint DFLT f-dsp-8-u8 + ((parse "unsigned8")) () () +) +(define-full-operand Dsp-8-u16 "unsigned 16 bit displacement at offset 8 bits" (all-isas) + h-uint DFLT f-dsp-8-u16 + ((parse "unsigned16")) () () +) +(define-full-operand Dsp-8-s8 "signed 8 bit displacement at offset 8 bits" (all-isas) + h-sint DFLT f-dsp-8-s8 + ((parse "signed8")) () () +) +(define-full-operand Dsp-8-u24 "unsigned 24 bit displacement at offset 8 bits" (all-isas) + h-uint DFLT f-dsp-8-u24 + ((parse "unsigned24")) () () +) +(define-full-operand Dsp-10-u6 "unsigned 6 bit displacement at offset 10 bits" (all-isas) + h-uint DFLT f-dsp-10-u6 + ((parse "unsigned6")) () () +) +(define-full-operand Dsp-16-u8 "unsigned 8 bit displacement at offset 16 bits" (all-isas) + h-uint DFLT f-dsp-16-u8 + ((parse "unsigned8")) () () +) +(define-full-operand Dsp-16-u16 "unsigned 16 bit displacement at offset 16 bits" (all-isas) + h-uint DFLT f-dsp-16-u16 + ((parse "unsigned16")) () () +) +(define-full-operand Dsp-16-u20 "unsigned 20 bit displacement at offset 16 bits" (all-isas) + h-uint DFLT f-dsp-16-u24 + ((parse "unsigned20")) () () +) +(define-full-operand Dsp-16-u24 "unsigned 24 bit displacement at offset 16 bits" (all-isas) + h-uint DFLT f-dsp-16-u24 + ((parse "unsigned24")) () () +) +(define-full-operand Dsp-16-s8 "signed 8 bit displacement at offset 16 bits" (all-isas) + h-sint DFLT f-dsp-16-s8 + ((parse "signed8")) () () +) +(define-full-operand Dsp-16-s16 "signed 16 bit displacement at offset 16 bits" (all-isas) + h-sint DFLT f-dsp-16-s16 + ((parse "signed16")) () () +) +(define-full-operand Dsp-24-u8 "unsigned 8 bit displacement at offset 24 bits" (all-isas) + h-uint DFLT f-dsp-24-u8 + ((parse "unsigned8")) () () +) +(define-full-operand Dsp-24-u16 "unsigned 16 bit displacement at offset 24 bits" (all-isas) + h-uint DFLT f-dsp-24-u16 + ((parse "unsigned16")) () () +) +(define-full-operand Dsp-24-u20 "unsigned 20 bit displacement at offset 24 bits" (all-isas) + h-uint DFLT f-dsp-24-u24 + ((parse "unsigned20")) () () +) +(define-full-operand Dsp-24-u24 "unsigned 24 bit displacement at offset 24 bits" (all-isas) + h-uint DFLT f-dsp-24-u24 + ((parse "unsigned24")) () () +) +(define-full-operand Dsp-24-s8 "signed 8 bit displacement at offset 24 bits" (all-isas) + h-sint DFLT f-dsp-24-s8 + ((parse "signed8")) () () +) +(define-full-operand Dsp-24-s16 "signed 16 bit displacement at offset 24 bits" (all-isas) + h-sint DFLT f-dsp-24-s16 + ((parse "signed16")) () () +) +(define-full-operand Dsp-32-u8 "unsigned 8 bit displacement at offset 32 bits" (all-isas) + h-uint DFLT f-dsp-32-u8 + ((parse "unsigned8")) () () +) +(define-full-operand Dsp-32-u16 "unsigned 16 bit displacement at offset 32 bits" (all-isas) + h-uint DFLT f-dsp-32-u16 + ((parse "unsigned16")) () () +) +(define-full-operand Dsp-32-u24 "unsigned 24 bit displacement at offset 32 bits" (all-isas) + h-uint DFLT f-dsp-32-u24 + ((parse "unsigned24")) () () +) +(define-full-operand Dsp-32-u20 "unsigned 20 bit displacement at offset 32 bits" (all-isas) + h-uint DFLT f-dsp-32-u24 + ((parse "unsigned20")) () () +) +(define-full-operand Dsp-32-s8 "signed 8 bit displacement at offset 32 bits" (all-isas) + h-sint DFLT f-dsp-32-s8 + ((parse "signed8")) () () +) +(define-full-operand Dsp-32-s16 "signed 16 bit displacement at offset 32 bits" (all-isas) + h-sint DFLT f-dsp-32-s16 + ((parse "signed16")) () () +) +(define-full-operand Dsp-40-u8 "unsigned 8 bit displacement at offset 40 bits" (all-isas) + h-uint DFLT f-dsp-40-u8 + ((parse "unsigned8")) () () +) +(define-full-operand Dsp-40-s8 "signed 8 bit displacement at offset 40 bits" (all-isas) + h-sint DFLT f-dsp-40-s8 + ((parse "signed8")) () () +) +(define-full-operand Dsp-40-u16 "unsigned 16 bit displacement at offset 40 bits" (all-isas) + h-uint DFLT f-dsp-40-u16 + ((parse "unsigned16")) () () +) +(define-full-operand Dsp-40-s16 "signed 16 bit displacement at offset 40 bits" (all-isas) + h-sint DFLT f-dsp-40-s16 + ((parse "signed16")) () () +) +(define-full-operand Dsp-40-u24 "unsigned 24 bit displacement at offset 40 bits" (all-isas) + h-uint DFLT f-dsp-40-u24 + ((parse "unsigned24")) () () +) +(define-full-operand Dsp-48-u8 "unsigned 8 bit displacement at offset 48 bits" (all-isas) + h-uint DFLT f-dsp-48-u8 + ((parse "unsigned8")) () () +) +(define-full-operand Dsp-48-s8 "signed 8 bit displacement at offset 48 bits" (all-isas) + h-sint DFLT f-dsp-48-s8 + ((parse "signed8")) () () +) +(define-full-operand Dsp-48-u16 "unsigned 16 bit displacement at offset 48 bits" (all-isas) + h-uint DFLT f-dsp-48-u16 + ((parse "unsigned16")) () () +) +(define-full-operand Dsp-48-s16 "signed 16 bit displacement at offset 48 bits" (all-isas) + h-sint DFLT f-dsp-48-s16 + ((parse "signed16")) () () +) +(define-full-operand Dsp-48-u24 "unsigned 24 bit displacement at offset 48 bits" (all-isas) + h-uint DFLT f-dsp-48-u24 + ((parse "unsigned24")) () () +) + +(define-full-operand Imm-8-s4 "signed 4 bit immediate at offset 8 bits" (all-isas) + h-sint DFLT f-imm-8-s4 + ((parse "signed4")) () () +) +(define-full-operand Imm-sh-8-s4 "signed 4 bit shift immediate at offset 8 bits" (all-isas) + h-shimm DFLT f-imm-8-s4 + () () () +) +(define-full-operand Imm-8-QI "signed 8 bit immediate at offset 8 bits" (all-isas) + h-sint DFLT f-dsp-8-s8 + ((parse "signed8")) () () +) +(define-full-operand Imm-8-HI "signed 16 bit immediate at offset 8 bits" (all-isas) + h-sint DFLT f-dsp-8-s16 + ((parse "signed16")) () () +) +(define-full-operand Imm-12-s4 "signed 4 bit immediate at offset 12 bits" (all-isas) + h-sint DFLT f-imm-12-s4 + ((parse "signed4")) () () +) +(define-full-operand Imm-sh-12-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas) + h-shimm DFLT f-imm-12-s4 + () () () +) +(define-full-operand Imm-13-u3 "signed 3 bit immediate at offset 13 bits" (all-isas) + h-sint DFLT f-imm-13-u3 + ((parse "signed4")) () () +) +(define-full-operand Imm-20-s4 "signed 4 bit immediate at offset 20 bits" (all-isas) + h-sint DFLT f-imm-20-s4 + ((parse "signed4")) () () +) +(define-full-operand Imm-sh-20-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas) + h-shimm DFLT f-imm-20-s4 + () () () +) +(define-full-operand Imm-16-QI "signed 8 bit immediate at offset 16 bits" (all-isas) + h-sint DFLT f-dsp-16-s8 + ((parse "signed8")) () () +) +(define-full-operand Imm-16-HI "signed 16 bit immediate at offset 16 bits" (all-isas) + h-sint DFLT f-dsp-16-s16 + ((parse "signed16")) () () +) +(define-full-operand Imm-16-SI "signed 32 bit immediate at offset 16 bits" (all-isas) + h-sint DFLT f-dsp-16-s32 + ((parse "signed32")) () () +) +(define-full-operand Imm-24-QI "signed 8 bit immediate at offset 24 bits" (all-isas) + h-sint DFLT f-dsp-24-s8 + ((parse "signed8")) () () +) +(define-full-operand Imm-24-HI "signed 16 bit immediate at offset 24 bits" (all-isas) + h-sint DFLT f-dsp-24-s16 + ((parse "signed16")) () () +) +(define-full-operand Imm-24-SI "signed 32 bit immediate at offset 24 bits" (all-isas) + h-sint DFLT f-dsp-24-s32 + ((parse "signed32")) () () +) +(define-full-operand Imm-32-QI "signed 8 bit immediate at offset 32 bits" (all-isas) + h-sint DFLT f-dsp-32-s8 + ((parse "signed8")) () () +) +(define-full-operand Imm-32-SI "signed 32 bit immediate at offset 32 bits" (all-isas) + h-sint DFLT f-dsp-32-s32 + ((parse "signed32")) () () +) +(define-full-operand Imm-32-HI "signed 16 bit immediate at offset 32 bits" (all-isas) + h-sint DFLT f-dsp-32-s16 + ((parse "signed16")) () () +) +(define-full-operand Imm-40-QI "signed 8 bit immediate at offset 40 bits" (all-isas) + h-sint DFLT f-dsp-40-s8 + ((parse "signed8")) () () +) +(define-full-operand Imm-40-HI "signed 16 bit immediate at offset 40 bits" (all-isas) + h-sint DFLT f-dsp-40-s16 + ((parse "signed16")) () () +) +(define-full-operand Imm-40-SI "signed 32 bit immediate at offset 40 bits" (all-isas) + h-sint DFLT f-dsp-40-s32 + ((parse "signed32")) () () +) +(define-full-operand Imm-48-QI "signed 8 bit immediate at offset 48 bits" (all-isas) + h-sint DFLT f-dsp-48-s8 + ((parse "signed8")) () () +) +(define-full-operand Imm-48-HI "signed 16 bit immediate at offset 48 bits" (all-isas) + h-sint DFLT f-dsp-48-s16 + ((parse "signed16")) () () +) +(define-full-operand Imm-48-SI "signed 32 bit immediate at offset 48 bits" (all-isas) + h-sint DFLT f-dsp-48-s32 + ((parse "signed32")) () () +) +(define-full-operand Imm-56-QI "signed 8 bit immediate at offset 56 bits" (all-isas) + h-sint DFLT f-dsp-56-s8 + ((parse "signed8")) () () +) +(define-full-operand Imm-56-HI "signed 16 bit immediate at offset 56 bits" (all-isas) + h-sint DFLT f-dsp-56-s16 + ((parse "signed16")) () () +) +(define-full-operand Imm-64-HI "signed 16 bit immediate at offset 64 bits" (all-isas) + h-sint DFLT f-dsp-64-s16 + ((parse "signed16")) () () +) +(define-full-operand Imm1-S "signed 1 bit immediate for short format binary insns" (m32c-isa) + h-sint DFLT f-imm1-S + ((parse "imm1_S")) () () +) +(define-full-operand Imm3-S "signed 3 bit immediate for short format binary insns" (m32c-isa) + h-sint DFLT f-imm3-S + ((parse "imm3_S")) () () +) + +;------------------------------------------------------------- +; Bit numbers +;------------------------------------------------------------- + +(define-full-operand Bitno16R "bit number for indexing registers" (m16c-isa) + h-uint DFLT f-dsp-16-u8 + ((parse "Bitno16R")) () () +) +(dnop Bitno32Prefixed "bit number for indexing objects" (m32c-isa) h-uint f-bitno32-prefixed) +(dnop Bitno32Unprefixed "bit number for indexing objects" (m32c-isa) h-uint f-bitno32-unprefixed) + +(define-full-operand BitBase16-16-u8 "unsigned bit,base:8 at offset 16for m16c" (m16c-isa) + h-uint DFLT f-dsp-16-u8 + ((parse "unsigned_bitbase8") (print "unsigned_bitbase")) () () +) +(define-full-operand BitBase16-16-s8 "signed bit,base:8 at offset 16for m16c" (m16c-isa) + h-sint DFLT f-dsp-16-s8 + ((parse "signed_bitbase8") (print "signed_bitbase")) () () +) +(define-full-operand BitBase16-16-u16 "unsigned bit,base:16 at offset 16 for m16c" (m16c-isa) + h-uint DFLT f-dsp-16-u16 + ((parse "unsigned_bitbase16") (print "unsigned_bitbase")) () () +) +(define-full-operand BitBase16-8-u11-S "signed bit,base:11 at offset 16 for m16c" (m16c-isa) + h-uint DFLT f-bitbase16-u11-S + ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () () +) + +(define-full-operand BitBase32-16-u11-Unprefixed "unsigned bit,base:11 at offset 16 for m32c" (m32c-isa) + h-uint DFLT f-bitbase32-16-u11-unprefixed + ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () () +) +(define-full-operand BitBase32-16-s11-Unprefixed "signed bit,base:11 at offset 16 for m32c" (m32c-isa) + h-sint DFLT f-bitbase32-16-s11-unprefixed + ((parse "signed_bitbase11") (print "signed_bitbase")) () () +) +(define-full-operand BitBase32-16-u19-Unprefixed "unsigned bit,base:19 at offset 16 for m32c" (m32c-isa) + h-uint DFLT f-bitbase32-16-u19-unprefixed + ((parse "unsigned_bitbase19") (print "unsigned_bitbase")) () () +) +(define-full-operand BitBase32-16-s19-Unprefixed "signed bit,base:19 at offset 16 for m32c" (m32c-isa) + h-sint DFLT f-bitbase32-16-s19-unprefixed + ((parse "signed_bitbase19") (print "signed_bitbase")) () () +) +(define-full-operand BitBase32-16-u27-Unprefixed "unsigned bit,base:27 at offset 16 for m32c" (m32c-isa) + h-uint DFLT f-bitbase32-16-u27-unprefixed + ((parse "unsigned_bitbase27") (print "unsigned_bitbase")) () () +) +(define-full-operand BitBase32-24-u11-Prefixed "unsigned bit,base:11 at offset 24 for m32c" (m32c-isa) + h-uint DFLT f-bitbase32-24-u11-prefixed + ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () () +) +(define-full-operand BitBase32-24-s11-Prefixed "signed bit,base:11 at offset 24 for m32c" (m32c-isa) + h-sint DFLT f-bitbase32-24-s11-prefixed + ((parse "signed_bitbase11") (print "signed_bitbase")) () () +) +(define-full-operand BitBase32-24-u19-Prefixed "unsigned bit,base:19 at offset 24 for m32c" (m32c-isa) + h-uint DFLT f-bitbase32-24-u19-prefixed + ((parse "unsigned_bitbase19") (print "unsigned_bitbase")) () () +) +(define-full-operand BitBase32-24-s19-Prefixed "signed bit,base:19 at offset 24 for m32c" (m32c-isa) + h-sint DFLT f-bitbase32-24-s19-prefixed + ((parse "signed_bitbase19") (print "signed_bitbase")) () () +) +(define-full-operand BitBase32-24-u27-Prefixed "unsigned bit,base:27 at offset 24 for m32c" (m32c-isa) + h-uint DFLT f-bitbase32-24-u27-prefixed + ((parse "unsigned_bitbase27") (print "unsigned_bitbase")) () () +) +;------------------------------------------------------------- +; Labels +;------------------------------------------------------------- + +(define-full-operand Lab-5-3 "3 bit label" (all-isas RELAX) + h-iaddr DFLT f-lab-5-3 + ((parse "lab_5_3")) () () ) + +(define-full-operand Lab32-jmp-s "3 bit label" (all-isas RELAX) + h-iaddr DFLT f-lab32-jmp-s + ((parse "lab_5_3")) () () ) + +(dnop Lab-8-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-8-8) +(dnop Lab-8-16 "16 bit label" (all-isas RELAX) h-iaddr f-lab-8-16) +(dnop Lab-8-24 "24 bit label" (all-isas) h-iaddr f-lab-8-24) +(dnop Lab-16-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-16-8) +(dnop Lab-24-8 "8 bit label" (all-isas) h-iaddr f-lab-24-8) +(dnop Lab-32-8 "8 bit label" (all-isas) h-iaddr f-lab-32-8) +(dnop Lab-40-8 "8 bit label" (all-isas) h-iaddr f-lab-40-8) + +;------------------------------------------------------------- +; Condition code bits +;------------------------------------------------------------- + +(dnop sbit "negative bit" (SEM-ONLY all-isas) h-sbit f-nil) +(dnop obit "overflow bit" (SEM-ONLY all-isas) h-obit f-nil) +(dnop zbit "zero bit" (SEM-ONLY all-isas) h-zbit f-nil) +(dnop cbit "carry bit" (SEM-ONLY all-isas) h-cbit f-nil) +(dnop ubit "stack ptr select bit" (SEM-ONLY all-isas) h-ubit f-nil) +(dnop ibit "interrupt enable bit" (SEM-ONLY all-isas) h-ibit f-nil) +(dnop bbit "reg bank select bit" (SEM-ONLY all-isas) h-bbit f-nil) +(dnop dbit "debug bit" (SEM-ONLY all-isas) h-dbit f-nil) + +;------------------------------------------------------------- +; Condition operands +;------------------------------------------------------------- + +(define-pmacro (cond-operand mach offset) + (dnop (.sym cond mach - offset) "condition" ((.sym m mach c-isa)) (.sym h-cond mach) (.sym f-dsp- offset -u8)) +) + +(cond-operand 16 16) +(cond-operand 16 24) +(cond-operand 16 32) +(cond-operand 32 16) +(cond-operand 32 24) +(cond-operand 32 32) +(cond-operand 32 40) + +(dnop cond16c "condition" (m16c-isa) h-cond16c f-cond16) +(dnop cond16j "condition" (m16c-isa) h-cond16j f-cond16) +(dnop cond16j5 "condition" (m16c-isa) h-cond16j-5 f-cond16j-5) +(dnop cond32 "condition" (m32c-isa) h-cond32 f-cond32) +(dnop cond32j "condition" (m32c-isa) h-cond32 f-cond32j) +(dnop sccond32 "scCND condition" (m32c-isa) h-cond32 f-cond16) +(dnop flags16 "flags" (m16c-isa) h-flags f-9-3) +(dnop flags32 "flags" (m32c-isa) h-flags f-13-3) +(dnop cr16 "control" (m16c-isa) h-cr-16 f-9-3) +(dnop cr1-Unprefixed-32 "control" (m32c-isa) h-cr1-32 f-13-3) +(dnop cr1-Prefixed-32 "control" (m32c-isa) h-cr1-32 f-21-3) +(dnop cr2-32 "control" (m32c-isa) h-cr2-32 f-13-3) +(dnop cr3-Unprefixed-32 "control" (m32c-isa) h-cr3-32 f-13-3) +(dnop cr3-Prefixed-32 "control" (m32c-isa) h-cr3-32 f-21-3) + +;------------------------------------------------------------- +; Suffixes +;------------------------------------------------------------- + +(define-full-operand Z "Suffix for zero format insns" (all-isas) + h-sint DFLT f-nil + ((parse "Z") (print "Z")) () () +) +(define-full-operand S "Suffix for short format insns" (all-isas) + h-sint DFLT f-nil + ((parse "S") (print "S")) () () +) +(define-full-operand Q "Suffix for quick format insns" (all-isas) + h-sint DFLT f-nil + ((parse "Q") (print "Q")) () () +) +(define-full-operand G "Suffix for general format insns" (all-isas) + h-sint DFLT f-nil + ((parse "G") (print "G")) () () +) +(define-full-operand X "Empty suffix" (all-isas) + h-sint DFLT f-nil + ((parse "X") (print "X")) () () +) +(define-full-operand size "any size specifier" (all-isas) + h-sint DFLT f-nil + ((parse "size") (print "size")) () () +) +;------------------------------------------------------------- +; Misc +;------------------------------------------------------------- + +(dnop BitIndex "Bit Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-bit-index f-nil) +(dnop SrcIndex "Source Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-src-index f-nil) +(dnop DstIndex "Destination Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-dst-index f-nil) +(dnop NoRemainder "Place holder for when the remainder is not kept" (SEM-ONLY MACH32 m32c-isa) h-none f-nil) + +;============================================================= +; Derived Operands + +; Memory reference macros that clip addresses appropriately. Refer to +; memory at ADDRESS in MODE, clipped appropriately for either the m16c +; or m32c. +(define-pmacro (mem16 mode address) + (mem mode (and #xffff address))) + +(define-pmacro (mem32 mode address) + (mem mode (and #xffffff address))) + +; Like mem16 and mem32, but takes MACH as a parameter. MACH must be +; either 16 or 32. +(define-pmacro (mem-mach mach mode address) + ((.sym mem mach) mode address)) + +;------------------------------------------------------------- +; Source +;------------------------------------------------------------- +; Rn direct +;------------------------------------------------------------- + +(define-pmacro (src16-Rn-direct-operand xmode) + (begin + (define-derived-operand + (name (.sym src16-Rn-direct- xmode)) + (comment (.str "m16c Rn direct source " xmode)) + (attrs (machine 16)) + (mode xmode) + (args ((.sym Src16Rn xmode))) + (syntax (.str "$Src16Rn" xmode)) + (base-ifield f-8-4) + (encoding (+ (f-8-2 0) (.sym Src16Rn xmode))) + (ifield-assertion (eq f-8-2 0)) + (getter (trunc xmode (.sym Src16Rn xmode))) + (setter (set (.sym Src16Rn xmode) newval)) + ) + ) +) +(src16-Rn-direct-operand QI) +(src16-Rn-direct-operand HI) + +(define-pmacro (src32-Rn-direct-operand group base xmode) + (begin + (define-derived-operand + (name (.sym src32-Rn-direct- group - xmode)) + (comment (.str "m32c Rn direct source " xmode)) + (attrs (machine 32)) + (mode xmode) + (args ((.sym Src32Rn group xmode))) + (syntax (.str "$Src32Rn" group xmode)) + (base-ifield (.sym f- base -11)) + (encoding (+ ((.sym f- base -3) 4) (.sym Src32Rn group xmode))) + (ifield-assertion (eq (.sym f- base -3) 4)) + (getter (trunc xmode (.sym Src32Rn group xmode))) + (setter (set (.sym Src32Rn group xmode) newval)) + ) + ) +) + +(src32-Rn-direct-operand Unprefixed 1 QI) +(src32-Rn-direct-operand Prefixed 9 QI) +(src32-Rn-direct-operand Unprefixed 1 HI) +(src32-Rn-direct-operand Prefixed 9 HI) +(src32-Rn-direct-operand Unprefixed 1 SI) +(src32-Rn-direct-operand Prefixed 9 SI) + +;------------------------------------------------------------- +; An direct +;------------------------------------------------------------- + +(define-pmacro (src16-An-direct-operand xmode) + (begin + (define-derived-operand + (name (.sym src16-An-direct- xmode)) + (comment (.str "m16c An direct destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args ((.sym Src16An xmode))) + (syntax (.str "$Src16An" xmode)) + (base-ifield f-8-4) + (encoding (+ (f-8-2 1) (f-10-1 0) (.sym Src16An xmode))) + (ifield-assertion (andif (eq f-8-2 1) (eq f-10-1 0))) + (getter (trunc xmode (.sym Src16An xmode))) + (setter (set (.sym Src16An xmode) newval)) + ) + ) +) +(src16-An-direct-operand QI) +(src16-An-direct-operand HI) + +(define-pmacro (src32-An-direct-operand group base1 base2 xmode) + (begin + (define-derived-operand + (name (.sym src32-An-direct- group - xmode)) + (comment (.str "m32c An direct destination " xmode)) + (attrs (machine 32)) + (mode xmode) + (args ((.sym Src32An group xmode))) + (syntax (.str "$Src32An" group xmode)) + (base-ifield (.sym f- base1 -11)) + (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Src32An group xmode))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1))) + (getter (trunc xmode (.sym Src32An group xmode))) + (setter (set (.sym Src32An group xmode) newval)) + ) + ) +) + +(src32-An-direct-operand Unprefixed 1 10 QI) +(src32-An-direct-operand Unprefixed 1 10 HI) +(src32-An-direct-operand Unprefixed 1 10 SI) +(src32-An-direct-operand Prefixed 9 18 QI) +(src32-An-direct-operand Prefixed 9 18 HI) +(src32-An-direct-operand Prefixed 9 18 SI) + +;------------------------------------------------------------- +; An indirect +;------------------------------------------------------------- + +(define-pmacro (src16-An-indirect-operand xmode) + (begin + (define-derived-operand + (name (.sym src16-An-indirect- xmode)) + (comment (.str "m16c An indirect destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args (Src16An)) + (syntax "[$Src16An]") + (base-ifield f-8-4) + (encoding (+ (f-8-2 1) (f-10-1 1) Src16An)) + (ifield-assertion (andif (eq f-8-2 1) (eq f-10-1 1))) + (getter (mem16 xmode Src16An)) + (setter (set (mem16 xmode Src16An) newval)) + ) + ) +) +(src16-An-indirect-operand QI) +(src16-An-indirect-operand HI) + +(define-pmacro (src32-An-indirect-operand group base1 base2 xmode) + (begin + (define-derived-operand + (name (.sym src32-An-indirect- group - xmode)) + (comment (.str "m32c An indirect destination " xmode)) + (attrs (machine 32)) + (mode xmode) + (args ((.sym Src32An group))) + (syntax (.str "[$Src32An" group "]")) + (base-ifield (.sym f- base1 -11)) + (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Src32An group))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0))) + (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) + (const 0))) + (setter (c-call DFLT (.str "operand_setter_" xmode) newval + (.sym Src32An group) (const 0))) +; (getter (mem32 xmode (.sym Src32An group))) +; (setter (set (mem32 xmode (.sym Src32An group)) newval)) + ) + ) +) + +(src32-An-indirect-operand Unprefixed 1 10 QI) +(src32-An-indirect-operand Unprefixed 1 10 HI) +(src32-An-indirect-operand Unprefixed 1 10 SI) +(src32-An-indirect-operand Prefixed 9 18 QI) +(src32-An-indirect-operand Prefixed 9 18 HI) +(src32-An-indirect-operand Prefixed 9 18 SI) + +;------------------------------------------------------------- +; dsp:d[r] relative +;------------------------------------------------------------- + +(define-pmacro (src16-relative-operand xmode) + (begin + (define-derived-operand + (name (.sym src16-16-8-SB-relative- xmode)) + (comment (.str "m16c dsp:8[sb] relative destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args (Dsp-16-u8)) + (syntax "${Dsp-16-u8}[sb]") + (base-ifield f-8-4) + (encoding (+ (f-8-4 #xA) Dsp-16-u8)) + (ifield-assertion (eq f-8-4 #xA)) + (getter (mem16 xmode (add Dsp-16-u8 (reg h-sb)))) + (setter (set (mem16 xmode (add Dsp-16-u8 (reg h-sb))) newval)) + ) + (define-derived-operand + (name (.sym src16-16-16-SB-relative- xmode)) + (comment (.str "m16c dsp:16[sb] relative destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args (Dsp-16-u16)) + (syntax "${Dsp-16-u16}[sb]") + (base-ifield f-8-4) + (encoding (+ (f-8-4 #xE) Dsp-16-u16)) + (ifield-assertion (eq f-8-4 #xE)) + (getter (mem16 xmode (add Dsp-16-u16 (reg h-sb)))) + (setter (set (mem16 xmode (add Dsp-16-u16 (reg h-sb))) newval)) + ) + (define-derived-operand + (name (.sym src16-16-8-FB-relative- xmode)) + (comment (.str "m16c dsp:8[fb] relative destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args (Dsp-16-s8)) + (syntax "${Dsp-16-s8}[fb]") + (base-ifield f-8-4) + (encoding (+ (f-8-4 #xB) Dsp-16-s8)) + (ifield-assertion (eq f-8-4 #xB)) + (getter (mem16 xmode (add Dsp-16-s8 (reg h-fb)))) + (setter (set (mem16 xmode (add Dsp-16-s8 (reg h-fb))) newval)) + ) + (define-derived-operand + (name (.sym src16-16-8-An-relative- xmode)) + (comment (.str "m16c dsp:8[An] relative destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args (Src16An Dsp-16-u8)) + (syntax "${Dsp-16-u8}[$Src16An]") + (base-ifield f-8-4) + (encoding (+ (f-8-2 2) (f-10-1 0) Dsp-16-u8 Src16An)) + (ifield-assertion (andif (eq f-8-2 2) (eq f-10-1 0))) + (getter (mem16 xmode (add Dsp-16-u8 Src16An))) + (setter (set (mem16 xmode (add Dsp-16-u8 Src16An)) newval)) + ) + (define-derived-operand + (name (.sym src16-16-16-An-relative- xmode)) + (comment (.str "m16c dsp:16[An] relative destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args (Src16An Dsp-16-u16)) + (syntax "${Dsp-16-u16}[$Src16An]") + (base-ifield f-8-4) + (encoding (+ (f-8-2 3) (f-10-1 0) Dsp-16-u16 Src16An)) + (ifield-assertion (andif (eq f-8-2 3) (eq f-10-1 0))) + (getter (mem16 xmode (add Dsp-16-u16 Src16An))) + (setter (set (mem16 xmode (add Dsp-16-u16 Src16An)) newval)) + ) + ) +) + +(src16-relative-operand QI) +(src16-relative-operand HI) + +(define-pmacro (src32-relative-operand offset group base1 base2 xmode) + (begin + (define-derived-operand + (name (.sym src32- offset -8-SB-relative- group - xmode)) + (comment (.str "m32c dsp:8[sb] relative destination " xmode)) + (attrs (machine 32)) + (mode xmode) + (args ((.sym Dsp- offset -u8))) + (syntax (.str "${Dsp-" offset "-u8}[sb]")) + (base-ifield (.sym f- base1 -11)) + (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u8))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2))) + (getter (c-call xmode (.str "operand_getter_" xmode) sb (.sym Dsp- offset -u8))) + (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb (.sym Dsp- offset -u8))) +; (getter (mem32 xmode (add (.sym Dsp- offset -u8) (reg h-sb)))) +; (setter (set (mem32 xmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval)) + ) + (define-derived-operand + (name (.sym src32- offset -16-SB-relative- group - xmode)) + (comment (.str "m32c dsp:16[sb] relative destination " xmode)) + (attrs (machine 32)) + (mode xmode) + (args ((.sym Dsp- offset -u16))) + (syntax (.str "${Dsp-" offset "-u16}[sb]")) + (base-ifield (.sym f- base1 -11)) + (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u16))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2))) + (getter (c-call xmode (.str "operand_getter_" xmode) sb (.sym Dsp- offset -u16))) + (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb (.sym Dsp- offset -u16))) +; (getter (mem32 xmode (add (.sym Dsp- offset -u16) (reg h-sb)))) +; (setter (set (mem32 xmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval)) + ) + (define-derived-operand + (name (.sym src32- offset -8-FB-relative- group - xmode)) + (comment (.str "m32c dsp:8[fb] relative destination " xmode)) + (attrs (machine 32)) + (mode xmode) + (args ((.sym Dsp- offset -s8))) + (syntax (.str "${Dsp-" offset "-s8}[fb]")) + (base-ifield (.sym f- base1 -11)) + (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s8))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3))) + (getter (c-call xmode (.str "operand_getter_" xmode) fb (.sym Dsp- offset -s8))) + (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb (.sym Dsp- offset -s8))) +; (getter (mem32 xmode (add (.sym Dsp- offset -s8) (reg h-fb)))) +; (setter (set (mem32 xmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval)) + ) + (define-derived-operand + (name (.sym src32- offset -16-FB-relative- group - xmode)) + (comment (.str "m32c dsp:16[fb] relative destination " xmode)) + (attrs (machine 32)) + (mode xmode) + (args ((.sym Dsp- offset -s16))) + (syntax (.str "${Dsp-" offset "-s16}[fb]")) + (base-ifield (.sym f- base1 -11)) + (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s16))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3))) + (getter (c-call xmode (.str "operand_getter_" xmode) fb (.sym Dsp- offset -s16))) + (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb (.sym Dsp- offset -s16))) +; (getter (mem32 xmode (add (.sym Dsp- offset -s16) (reg h-fb)))) +; (setter (set (mem32 xmode (add (.sym Dsp- offset -s16) (reg h-fb))) newval)) + ) + (define-derived-operand + (name (.sym src32- offset -8-An-relative- group - xmode)) + (comment (.str "m32c dsp:8[An] relative destination " xmode)) + (attrs (machine 32)) + (mode xmode) + (args ((.sym Src32An group) (.sym Dsp- offset -u8))) + (syntax (.str "${Dsp-" offset "-u8}[$Src32An" group "]")) + (base-ifield (.sym f- base1 -11)) + (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u8) (.sym Src32An group))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0))) + (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u8))) + (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u8))) +; (getter (mem32 xmode (add (.sym Dsp- offset -u8) (.sym Src32An group)))) +; (setter (set (mem32 xmode (add (.sym Dsp- offset -u8) (.sym Src32An group))) newval)) + ) + (define-derived-operand + (name (.sym src32- offset -16-An-relative- group - xmode)) + (comment (.str "m32c dsp:16[An] relative destination " xmode)) + (attrs (machine 32)) + (mode xmode) + (args ((.sym Src32An group) (.sym Dsp- offset -u16))) + (syntax (.str "${Dsp-" offset "-u16}[$Src32An" group "]")) + (base-ifield (.sym f- base1 -11)) + (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u16) (.sym Src32An group))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0))) + (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u16))) + (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u16))) +; (getter (mem32 xmode (add (.sym Dsp- offset -u16) (.sym Src32An group)))) +; (setter (set (mem32 xmode (add (.sym Dsp- offset -u16) (.sym Src32An group))) newval)) + ) + (define-derived-operand + (name (.sym src32- offset -24-An-relative- group - xmode)) + (comment (.str "m32c dsp:16[An] relative destination " xmode)) + (attrs (machine 32)) + (mode xmode) + (args ((.sym Src32An group) (.sym Dsp- offset -u24))) + (syntax (.str "${Dsp-" offset "-u24}[$Src32An" group "]")) + (base-ifield (.sym f- base1 -11)) + (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u24) (.sym Src32An group))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0))) + (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u24) )) + (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u24))) +; (getter (mem32 xmode (add (.sym Dsp- offset -u24) (.sym Src32An group)))) +; (setter (set (mem32 xmode (add (.sym Dsp- offset -u24) (.sym Src32An group))) newval)) + ) + ) +) + +(src32-relative-operand 16 Unprefixed 1 10 QI) +(src32-relative-operand 16 Unprefixed 1 10 HI) +(src32-relative-operand 16 Unprefixed 1 10 SI) +(src32-relative-operand 24 Prefixed 9 18 QI) +(src32-relative-operand 24 Prefixed 9 18 HI) +(src32-relative-operand 24 Prefixed 9 18 SI) + +;------------------------------------------------------------- +; Absolute address +;------------------------------------------------------------- + +(define-pmacro (src16-absolute xmode) + (begin + (define-derived-operand + (name (.sym src16-16-16-absolute- xmode)) + (comment (.str "m16c absolute address " xmode)) + (attrs (machine 16)) + (mode xmode) + (args (Dsp-16-u16)) + (syntax (.str "${Dsp-16-u16}")) + (base-ifield f-8-4) + (encoding (+ (f-8-4 #xF) Dsp-16-u16)) + (ifield-assertion (eq f-8-4 #xF)) + (getter (mem16 xmode Dsp-16-u16)) + (setter (set (mem16 xmode Dsp-16-u16) newval)) + ) + ) +) + +(src16-absolute QI) +(src16-absolute HI) + +(define-pmacro (src32-absolute offset group base1 base2 xmode) + (begin + (define-derived-operand + (name (.sym src32- offset -16-absolute- group - xmode)) + (comment (.str "m32c absolute address " xmode)) + (attrs (machine 32)) + (mode xmode) + (args ((.sym Dsp- offset -u16))) + (syntax (.str "${Dsp-" offset "-u16}")) + (base-ifield (.sym f- base1 -11)) + (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3))) + (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) (.sym Dsp- offset -u16))) + (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) (.sym Dsp- offset -u16))) +; (getter (mem32 xmode (.sym Dsp- offset -u16))) +; (setter (set (mem32 xmode (.sym Dsp- offset -u16)) newval)) + ) + (define-derived-operand + (name (.sym src32- offset -24-absolute- group - xmode)) + (comment (.str "m32c absolute address " xmode)) + (attrs (machine 32)) + (mode xmode) + (args ((.sym Dsp- offset -u24))) + (syntax (.str "${Dsp-" offset "-u24}")) + (base-ifield (.sym f- base1 -11)) + (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2))) + (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) (.sym Dsp- offset -u24))) + (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) (.sym Dsp- offset -u24))) +; (getter (mem32 xmode (.sym Dsp- offset -u24))) +; (setter (set (mem32 xmode (.sym Dsp- offset -u24)) newval)) + ) + ) +) + +(src32-absolute 16 Unprefixed 1 10 QI) +(src32-absolute 16 Unprefixed 1 10 HI) +(src32-absolute 16 Unprefixed 1 10 SI) +(src32-absolute 24 Prefixed 9 18 QI) +(src32-absolute 24 Prefixed 9 18 HI) +(src32-absolute 24 Prefixed 9 18 SI) + +;------------------------------------------------------------- +; An indirect indirect +; +; Double indirect addressing uses the lower 3 bytes of the value stored +; at the address referenced by 'op' as the effective address. +;------------------------------------------------------------- + +(define-pmacro (indirect-addr op) (and USI (mem32 USI op) #x00ffffff)) + +; (define-pmacro (src-An-indirect-indirect-operand xmode) +; (define-derived-operand +; (name (.sym src32-An-indirect-indirect- xmode)) +; (comment (.str "m32c An indirect indirect destination " xmode)) +; (attrs (machine 32)) +; (mode xmode) +; (args (Src32AnPrefixed)) +; (syntax (.str "[[$Src32AnPrefixed]]")) +; (base-ifield f-9-11) +; (encoding (+ (f-9-3 0) (f-18-1 0) Src32AnPrefixed)) +; (ifield-assertion (andif (eq f-9-3 0) (eq f-18-1 0))) +; (getter (mem32 xmode (indirect-addr Src32AnPrefixed))) +; (setter (set (mem32 xmode (indirect-addr Src32AnPrefixed)) newval)) +; ) +; ) + +; (src-An-indirect-indirect-operand QI) +; (src-An-indirect-indirect-operand HI) +; (src-An-indirect-indirect-operand SI) + +;------------------------------------------------------------- +; Relative indirect +;------------------------------------------------------------- + +(define-pmacro (src-relative-indirect-operand xmode) + (begin +; (define-derived-operand +; (name (.sym src32-24-8-SB-relative-indirect- xmode)) +; (comment (.str "m32c dsp:8[sb] relative source " xmode)) +; (attrs (machine 32)) +; (mode xmode) +; (args (Dsp-24-u8)) +; (syntax "[${Dsp-24-u8}[sb]]") +; (base-ifield f-9-11) +; (encoding (+ (f-9-3 1) (f-18-2 2) Dsp-24-u8)) +; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-2 2))) +; (getter (mem32 xmode (indirect-addr (add Dsp-24-u8 (reg h-sb))))) +; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u8 (reg h-sb)))) newval)) +; ) +; (define-derived-operand +; (name (.sym src32-24-16-SB-relative-indirect- xmode)) +; (comment (.str "m32c dsp:16[sb] relative source " xmode)) +; (attrs (machine 32)) +; (mode xmode) +; (args (Dsp-24-u16)) +; (syntax "[${Dsp-24-u16}[sb]]") +; (base-ifield f-9-11) +; (encoding (+ (f-9-3 2) (f-18-2 2) Dsp-24-u16)) +; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-2 2))) +; (getter (mem32 xmode (indirect-addr (add Dsp-24-u16 (reg h-sb))))) +; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u16 (reg h-sb)))) newval)) +; ) +; (define-derived-operand +; (name (.sym src32-24-8-FB-relative-indirect- xmode)) +; (comment (.str "m32c dsp:8[fb] relative source " xmode)) +; (attrs (machine 32)) +; (mode xmode) +; (args (Dsp-24-s8)) +; (syntax "[${Dsp-24-s8}[fb]]") +; (base-ifield f-9-11) +; (encoding (+ (f-9-3 1) (f-18-2 3) Dsp-24-s8)) +; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-2 3))) +; (getter (mem32 xmode (indirect-addr (add Dsp-24-s8 (reg h-fb))))) +; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-s8 (reg h-fb)))) newval)) +; ) +; (define-derived-operand +; (name (.sym src32-24-16-FB-relative-indirect- xmode)) +; (comment (.str "m32c dsp:16[fb] relative source " xmode)) +; (attrs (machine 32)) +; (mode xmode) +; (args (Dsp-24-s16)) +; (syntax "[${Dsp-24-s16}[fb]]") +; (base-ifield f-9-11) +; (encoding (+ (f-9-3 2) (f-18-2 3) Dsp-24-s16)) +; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-2 3))) +; (getter (mem32 xmode (indirect-addr (add Dsp-24-s16 (reg h-fb))))) +; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-s16 (reg h-fb)))) newval)) +; ) +; (define-derived-operand +; (name (.sym src32-24-8-An-relative-indirect- xmode)) +; (comment (.str "m32c dsp:8[An] relative indirect source " xmode)) +; (attrs (machine 32)) +; (mode xmode) +; (args (Src32AnPrefixed Dsp-24-u8)) +; (syntax "[${Dsp-24-u8}[$Src32AnPrefixed]]") +; (base-ifield f-9-11) +; (encoding (+ (f-9-3 1) (f-18-1 0) Dsp-24-u8 Src32AnPrefixed)) +; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-1 0))) +; (getter (mem32 xmode (indirect-addr (add Dsp-24-u8 Src32AnPrefixed)))) +; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u8 Src32AnPrefixed))) newval)) +; ) +; (define-derived-operand +; (name (.sym src32-24-16-An-relative-indirect- xmode)) +; (comment (.str "m32c dsp:16[An] relative source " xmode)) +; (attrs (machine 32)) +; (mode xmode) +; (args (Src32AnPrefixed Dsp-24-u16)) +; (syntax "[${Dsp-24-u16}[$Src32AnPrefixed]]") +; (base-ifield f-9-11) +; (encoding (+ (f-9-3 2) (f-18-1 0) Dsp-24-u16 Src32AnPrefixed)) +; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-1 0))) +; (getter (mem32 xmode (indirect-addr (add Dsp-24-u16 Src32AnPrefixed)))) +; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u16 Src32AnPrefixed))) newval)) +; ) +; (define-derived-operand +; (name (.sym src32-24-24-An-relative-indirect- xmode)) +; (comment (.str "m32c dsp:24[An] relative source " xmode)) +; (attrs (machine 32)) +; (mode xmode) +; (args (Src32AnPrefixed Dsp-24-u24)) +; (syntax "[${Dsp-24-u24}[$Src32AnPrefixed]]") +; (base-ifield f-9-11) +; (encoding (+ (f-9-3 3) (f-18-1 0) Dsp-24-u24 Src32AnPrefixed)) +; (ifield-assertion (andif (eq f-9-3 3) (eq f-18-1 0))) +; (getter (mem32 xmode (indirect-addr (add Dsp-24-u24 Src32AnPrefixed)))) +; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u24 Src32AnPrefixed))) newval)) +; ) + ) +) + +; (src-relative-indirect-operand QI) +; (src-relative-indirect-operand HI) +; (src-relative-indirect-operand SI) + +;------------------------------------------------------------- +; Absolute Indirect address +;------------------------------------------------------------- + +(define-pmacro (src32-absolute-indirect offset base1 base2 xmode) + (begin +; (define-derived-operand +; (name (.sym src32- offset -16-absolute-indirect-derived- xmode)) +; (comment (.str "m32c absolute indirect address " xmode)) +; (attrs (machine 32)) +; (mode xmode) +; (args ((.sym Dsp- offset -u16))) +; (syntax (.str "[${Dsp-" offset "-u16}]")) +; (base-ifield (.sym f- base1 -11)) +; (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16))) +; (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3))) +; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u16)))) +; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))) newval)) +; ) +; (define-derived-operand +; (name (.sym src32- offset -24-absolute-indirect-derived- xmode)) +; (comment (.str "m32c absolute indirect address " xmode)) +; (attrs (machine 32)) +; (mode xmode) +; (args ((.sym Dsp- offset -u24))) +; (syntax (.str "[${Dsp-" offset "-u24}]")) +; (base-ifield (.sym f- base1 -11)) +; (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24))) +; (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2))) +; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u24)))) +; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))) newval)) +; ) + ) +) + +(src32-absolute-indirect 24 9 18 QI) +(src32-absolute-indirect 24 9 18 HI) +(src32-absolute-indirect 24 9 18 SI) + +;------------------------------------------------------------- +; Register relative source operands for short format insns +;------------------------------------------------------------- + +(define-pmacro (src-2-S-operands mach xmode base opc1 opc2 opc3) + (begin + (define-derived-operand + (name (.sym src mach -2-S-8-SB-relative- xmode)) + (comment (.str "m" mach "c SB relative address")) + (attrs (machine mach)) + (mode xmode) + (args (Dsp-8-u8)) + (syntax "${Dsp-8-u8}[sb]") + (base-ifield (.sym f- base -2)) + (encoding (+ ((.sym f- base -2) opc1) Dsp-8-u8)) + (ifield-assertion (eq (.sym f- base -2) opc1)) + (getter (c-call xmode (.str "operand_getter_" xmode) sb Dsp-8-u8)) + (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb Dsp-8-u8)) +; (getter (mem-mach mach xmode (indirect-addr (add (reg h-sb) Dsp-8-u8)))) +; (setter (set (mem-mach mach xmode (indirect-addr (add (reg h-sb) Dsp-8-u8))) newval)) + ) + (define-derived-operand + (name (.sym src mach -2-S-8-FB-relative- xmode)) + (comment (.str "m" mach "c FB relative address")) + (attrs (machine mach)) + (mode xmode) + (args (Dsp-8-s8)) + (syntax "${Dsp-8-s8}[fb]") + (base-ifield (.sym f- base -2)) + (encoding (+ ((.sym f- base -2) opc2) Dsp-8-s8)) + (ifield-assertion (eq (.sym f- base -2) opc2)) + (getter (c-call xmode (.str "operand_getter_" xmode) fb Dsp-8-s8)) + (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb Dsp-8-s8)) +; (getter (mem-mach mach xmode (indirect-addr (add (reg h-fb) Dsp-8-s8)))) +; (setter (set (mem-mach mach xmode (indirect-addr (add (reg h-fb) Dsp-8-s8))) newval)) + ) + (define-derived-operand + (name (.sym src mach -2-S-16-absolute- xmode)) + (comment (.str "m" mach "c absolute address")) + (attrs (machine mach)) + (mode xmode) + (args (Dsp-8-u16)) + (syntax "${Dsp-8-u16}") + (base-ifield (.sym f- base -2)) + (encoding (+ ((.sym f- base -2) opc3) Dsp-8-u16)) + (ifield-assertion (eq (.sym f- base -2) opc3)) + (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) Dsp-8-u16)) + (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) Dsp-8-u16)) +; (getter (mem-mach mach xmode Dsp-8-u16)) +; (setter (set (mem-mach mach xmode Dsp-8-u16) newval)) + ) + ) +) + +(src-2-S-operands 16 QI 6 1 2 3) +(src-2-S-operands 32 QI 2 2 3 1) +(src-2-S-operands 32 HI 2 2 3 1) + +;============================================================= +; Derived Operands +;------------------------------------------------------------- +; Destination +;------------------------------------------------------------- +; Rn direct +;------------------------------------------------------------- + +(define-pmacro (dst16-Rn-direct-operand xmode) + (begin + (define-derived-operand + (name (.sym dst16-Rn-direct- xmode)) + (comment (.str "m16c Rn direct destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args ((.sym Dst16Rn xmode))) + (syntax (.str "$Dst16Rn" xmode)) + (base-ifield f-12-4) + (encoding (+ (f-12-2 0) (.sym Dst16Rn xmode))) + (ifield-assertion (eq f-12-2 0)) + (getter (trunc xmode (.sym Dst16Rn xmode))) + (setter (set (.sym Dst16Rn xmode) newval)) + ) + ) +) + +(dst16-Rn-direct-operand QI) +(dst16-Rn-direct-operand HI) +(dst16-Rn-direct-operand SI) + +(define-derived-operand + (name dst16-Rn-direct-Ext-QI) + (comment "m16c Rn direct destination QI") + (attrs (machine 16)) + (mode HI) + (args (Dst16RnExtQI)) + (syntax "$Dst16RnExtQI") + (base-ifield f-12-4) + (encoding (+ (f-12-2 0) Dst16RnExtQI (f-15-1 0))) + (ifield-assertion (andif (eq f-12-2 0) (eq f-15-1 0))) + (getter (trunc QI (.sym Dst16RnExtQI))) + (setter (set Dst16RnExtQI newval)) +) + +(define-pmacro (dst32-Rn-direct-operand group base xmode) + (begin + (define-derived-operand + (name (.sym dst32-Rn-direct- group - xmode)) + (comment (.str "m32c Rn direct destination " xmode)) + (attrs (machine 32)) + (mode xmode) + (args ((.sym Dst32Rn group xmode))) + (syntax (.str "$Dst32Rn" group xmode)) + (base-ifield (.sym f- base -6)) + (encoding (+ ((.sym f- base -3) 4) (.sym Dst32Rn group xmode))) + (ifield-assertion (eq (.sym f- base -3) 4)) + (getter (trunc xmode (.sym Dst32Rn group xmode))) + (setter (set (.sym Dst32Rn group xmode) newval)) + ) + ) +) + +(dst32-Rn-direct-operand Unprefixed 4 QI) +(dst32-Rn-direct-operand Prefixed 12 QI) +(dst32-Rn-direct-operand Unprefixed 4 HI) +(dst32-Rn-direct-operand Prefixed 12 HI) +(dst32-Rn-direct-operand Unprefixed 4 SI) +(dst32-Rn-direct-operand Prefixed 12 SI) + +(define-pmacro (dst32-Rn-direct-Ext-operand group base1 base2 smode dmode) + (begin + (define-derived-operand + (name (.sym dst32-Rn-direct- group - smode)) + (comment (.str "m32c Rn direct destination " smode)) + (attrs (machine 32)) + (mode dmode) + (args ((.sym Dst32Rn group smode))) + (syntax (.str "$Dst32Rn" group smode)) + (base-ifield (.sym f- base1 -6)) + (encoding (+ ((.sym f- base1 -3) 4) ((.sym f- base2 -1) 1) (.sym Dst32Rn group smode))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 4) (eq (.sym f- base2 -1) 1))) + (getter (trunc smode (.sym Dst32Rn group smode))) + (setter (set (.sym Dst32Rn group smode) newval)) + ) + ) +) + +(dst32-Rn-direct-Ext-operand ExtUnprefixed 4 8 QI HI) +(dst32-Rn-direct-Ext-operand ExtUnprefixed 4 8 HI SI) + +(define-derived-operand + (name dst32-R3-direct-Unprefixed-HI) + (comment "m32c R3 direct HI") + (attrs (machine 32)) + (mode HI) + (args (R3)) + (syntax "$R3") + (base-ifield f-4-6) + (encoding (+ (f-4-3 4) (f-8-2 #x1))) + (ifield-assertion (andif (eq f-4-3 4) (eq f-8-2 #x1))) + (getter (trunc HI R3)) + (setter (set R3 newval)) +) +;------------------------------------------------------------- +; An direct +;------------------------------------------------------------- + +(define-pmacro (dst16-An-direct-operand xmode) + (begin + (define-derived-operand + (name (.sym dst16-An-direct- xmode)) + (comment (.str "m16c An direct destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args ((.sym Dst16An xmode))) + (syntax (.str "$Dst16An" xmode)) + (base-ifield f-12-4) + (encoding (+ (f-12-2 1) (f-14-1 0) (.sym Dst16An xmode))) + (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 0))) + (getter (trunc xmode (.sym Dst16An xmode))) + (setter (set (.sym Dst16An xmode) newval)) + ) + ) +) + +(dst16-An-direct-operand QI) +(dst16-An-direct-operand HI) +(dst16-An-direct-operand SI) + +(define-pmacro (dst32-An-direct-operand group base1 base2 xmode) + (begin + (define-derived-operand + (name (.sym dst32-An-direct- group - xmode)) + (comment (.str "m32c An direct destination " xmode)) + (attrs (machine 32)) + (mode xmode) + (args ((.sym Dst32An group xmode))) + (syntax (.str "$Dst32An" group xmode)) + (base-ifield (.sym f- base1 -6)) + (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Dst32An group xmode))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1))) + (getter (trunc xmode (.sym Dst32An group xmode))) + (setter (set (.sym Dst32An group xmode) newval)) + ) + ) +) + +(dst32-An-direct-operand Unprefixed 4 8 QI) +(dst32-An-direct-operand Prefixed 12 16 QI) +(dst32-An-direct-operand Unprefixed 4 8 HI) +(dst32-An-direct-operand Prefixed 12 16 HI) +(dst32-An-direct-operand Unprefixed 4 8 SI) +(dst32-An-direct-operand Prefixed 12 16 SI) + +;------------------------------------------------------------- +; An indirect +;------------------------------------------------------------- + +(define-pmacro (dst16-An-indirect-operand xmode) + (begin + (define-derived-operand + (name (.sym dst16-An-indirect- xmode)) + (comment (.str "m16c An indirect destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args (Dst16An)) + (syntax "[$Dst16An]") + (base-ifield f-12-4) + (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An)) + (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1))) + (getter (mem16 xmode Dst16An)) + (setter (set (mem16 xmode Dst16An) newval)) + ) + ) +) + +(dst16-An-indirect-operand QI) +(dst16-An-indirect-operand HI) +(dst16-An-indirect-operand SI) + +(define-derived-operand + (name dst16-An-indirect-Ext-QI) + (comment "m16c An indirect destination QI") + (attrs (machine 16)) + (mode HI) + (args (Dst16An)) + (syntax "[$Dst16An]") + (base-ifield f-12-4) + (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An)) + (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1))) + (getter (mem16 QI Dst16An)) + (setter (set (mem16 HI Dst16An) newval)) +) + +(define-pmacro (dst32-An-indirect-operand group base1 base2 smode dmode) + (begin + (define-derived-operand + (name (.sym dst32-An-indirect- group - smode)) + (comment (.str "m32c An indirect destination " smode)) + (attrs (machine 32)) + (mode dmode) + (args ((.sym Dst32An group))) + (syntax (.str "[$Dst32An" group "]")) + (base-ifield (.sym f- base1 -6)) + (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Dst32An group))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0))) + (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) + (const 0))) + (setter (c-call DFLT (.str "operand_setter_" dmode) newval + (.sym Dst32An group) (const 0))) +; (getter (mem32 smode (.sym Dst32An group))) +; (setter (set (mem32 dmode (.sym Dst32An group)) newval)) + ) + ) +) + +(dst32-An-indirect-operand Unprefixed 4 8 QI QI) +(dst32-An-indirect-operand Prefixed 12 16 QI QI) +(dst32-An-indirect-operand Unprefixed 4 8 HI HI) +(dst32-An-indirect-operand Prefixed 12 16 HI HI) +(dst32-An-indirect-operand Unprefixed 4 8 SI SI) +(dst32-An-indirect-operand Prefixed 12 16 SI SI) +(dst32-An-indirect-operand ExtUnprefixed 4 8 QI HI) +(dst32-An-indirect-operand ExtUnprefixed 4 8 HI SI) + +;------------------------------------------------------------- +; dsp:d[r] relative +;------------------------------------------------------------- + +(define-pmacro (dst16-relative-operand offset xmode) + (begin + (define-derived-operand + (name (.sym dst16- offset -8-SB-relative- xmode)) + (comment (.str "m16c dsp:8[sb] relative destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args ((.sym Dsp- offset -u8))) + (syntax (.str "${Dsp-" offset "-u8}[sb]")) + (base-ifield f-12-4) + (encoding (+ (f-12-4 #xA) (.sym Dsp- offset -u8))) + (ifield-assertion (eq f-12-4 #xA)) + (getter (mem16 xmode (add (.sym Dsp- offset -u8) (reg h-sb)))) + (setter (set (mem16 xmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval)) + ) + (define-derived-operand + (name (.sym dst16- offset -16-SB-relative- xmode)) + (comment (.str "m16c dsp:16[sb] relative destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args ((.sym Dsp- offset -u16))) + (syntax (.str "${Dsp-" offset "-u16}[sb]")) + (base-ifield f-12-4) + (encoding (+ (f-12-4 #xE) (.sym Dsp- offset -u16))) + (ifield-assertion (eq f-12-4 #xE)) + (getter (mem16 xmode (add (.sym Dsp- offset -u16) (reg h-sb)))) + (setter (set (mem16 xmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval)) + ) + (define-derived-operand + (name (.sym dst16- offset -8-FB-relative- xmode)) + (comment (.str "m16c dsp:8[fb] relative destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args ((.sym Dsp- offset -s8))) + (syntax (.str "${Dsp-" offset "-s8}[fb]")) + (base-ifield f-12-4) + (encoding (+ (f-12-4 #xB) (.sym Dsp- offset -s8))) + (ifield-assertion (eq f-12-4 #xB)) + (getter (mem16 xmode (add (.sym Dsp- offset -s8) (reg h-fb)))) + (setter (set (mem16 xmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval)) + ) + (define-derived-operand + (name (.sym dst16- offset -8-An-relative- xmode)) + (comment (.str "m16c dsp:8[An] relative destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args (Dst16An (.sym Dsp- offset -u8))) + (syntax (.str "${Dsp-" offset "-u8}[$Dst16An]")) + (base-ifield f-12-4) + (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Dst16An)) + (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0))) + (getter (mem16 xmode (add (.sym Dsp- offset -u8) Dst16An))) + (setter (set (mem16 xmode (add (.sym Dsp- offset -u8) Dst16An)) newval)) + ) + (define-derived-operand + (name (.sym dst16- offset -16-An-relative- xmode)) + (comment (.str "m16c dsp:16[An] relative destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args (Dst16An (.sym Dsp- offset -u16))) + (syntax (.str "${Dsp-" offset "-u16}[$Dst16An]")) + (base-ifield f-12-4) + (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Dst16An)) + (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0))) + (getter (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An))) + (setter (set (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An)) newval)) + ) + ) +) + +(dst16-relative-operand 16 QI) +(dst16-relative-operand 24 QI) +(dst16-relative-operand 32 QI) +(dst16-relative-operand 40 QI) +(dst16-relative-operand 48 QI) +(dst16-relative-operand 16 HI) +(dst16-relative-operand 24 HI) +(dst16-relative-operand 32 HI) +(dst16-relative-operand 40 HI) +(dst16-relative-operand 48 HI) +(dst16-relative-operand 16 SI) +(dst16-relative-operand 24 SI) +(dst16-relative-operand 32 SI) +(dst16-relative-operand 40 SI) +(dst16-relative-operand 48 SI) + +(define-pmacro (dst16-relative-Ext-operand offset smode dmode) + (begin + (define-derived-operand + (name (.sym dst16- offset -8-SB-relative-Ext- smode)) + (comment (.str "m16c dsp:8[sb] relative destination " smode)) + (attrs (machine 16)) + (mode dmode) + (args ((.sym Dsp- offset -u8))) + (syntax (.str "${Dsp-" offset "-u8}[sb]")) + (base-ifield f-12-4) + (encoding (+ (f-12-4 #xA) (.sym Dsp- offset -u8))) + (ifield-assertion (eq f-12-4 #xA)) + (getter (mem16 smode (add (.sym Dsp- offset -u8) (reg h-sb)))) + (setter (set (mem16 dmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval)) + ) + (define-derived-operand + (name (.sym dst16- offset -16-SB-relative-Ext- smode)) + (comment (.str "m16c dsp:16[sb] relative destination " smode)) + (attrs (machine 16)) + (mode dmode) + (args ((.sym Dsp- offset -u16))) + (syntax (.str "${Dsp-" offset "-u16}[sb]")) + (base-ifield f-12-4) + (encoding (+ (f-12-4 #xE) (.sym Dsp- offset -u16))) + (ifield-assertion (eq f-12-4 #xE)) + (getter (mem16 smode (add (.sym Dsp- offset -u16) (reg h-sb)))) + (setter (set (mem16 dmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval)) + ) + (define-derived-operand + (name (.sym dst16- offset -8-FB-relative-Ext- smode)) + (comment (.str "m16c dsp:8[fb] relative destination " smode)) + (attrs (machine 16)) + (mode dmode) + (args ((.sym Dsp- offset -s8))) + (syntax (.str "${Dsp-" offset "-s8}[fb]")) + (base-ifield f-12-4) + (encoding (+ (f-12-4 #xB) (.sym Dsp- offset -s8))) + (ifield-assertion (eq f-12-4 #xB)) + (getter (mem16 smode (add (.sym Dsp- offset -s8) (reg h-fb)))) + (setter (set (mem16 dmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval)) + ) + (define-derived-operand + (name (.sym dst16- offset -8-An-relative-Ext- smode)) + (comment (.str "m16c dsp:8[An] relative destination " smode)) + (attrs (machine 16)) + (mode dmode) + (args (Dst16An (.sym Dsp- offset -u8))) + (syntax (.str "${Dsp-" offset "-u8}[$Dst16An]")) + (base-ifield f-12-4) + (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Dst16An)) + (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0))) + (getter (mem16 smode (add (.sym Dsp- offset -u8) Dst16An))) + (setter (set (mem16 dmode (add (.sym Dsp- offset -u8) Dst16An)) newval)) + ) + (define-derived-operand + (name (.sym dst16- offset -16-An-relative-Ext- smode)) + (comment (.str "m16c dsp:16[An] relative destination " smode)) + (attrs (machine 16)) + (mode dmode) + (args (Dst16An (.sym Dsp- offset -u16))) + (syntax (.str "${Dsp-" offset "-u16}[$Dst16An]")) + (base-ifield f-12-4) + (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Dst16An)) + (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0))) + (getter (mem16 smode (add (.sym Dsp- offset -u16) Dst16An))) + (setter (set (mem16 dmode (add (.sym Dsp- offset -u16) Dst16An)) newval)) + ) + ) +) + +(dst16-relative-Ext-operand 16 QI HI) + +(define-pmacro (dst32-relative-operand offset group base1 base2 smode dmode) + (begin + (define-derived-operand + (name (.sym dst32- offset -8-SB-relative- group - smode)) + (comment (.str "m32c dsp:8[sb] relative destination " smode)) + (attrs (machine 32)) + (mode dmode) + (args ((.sym Dsp- offset -u8))) + (syntax (.str "${Dsp-" offset "-u8}[sb]")) + (base-ifield (.sym f- base1 -6)) + (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u8))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2))) + (getter (c-call dmode (.str "operand_getter_" dmode) sb (.sym Dsp- offset -u8))) + (setter (c-call DFLT (.str "operand_setter_" dmode) newval sb (.sym Dsp- offset -u8))) +; (getter (mem32 smode (add (.sym Dsp- offset -u8) (reg h-sb)))) +; (setter (set (mem32 dmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval)) + ) + (define-derived-operand + (name (.sym dst32- offset -16-SB-relative- group - smode)) + (comment (.str "m32c dsp:16[sb] relative destination " smode)) + (attrs (machine 32)) + (mode dmode) + (args ((.sym Dsp- offset -u16))) + (syntax (.str "${Dsp-" offset "-u16}[sb]")) + (base-ifield (.sym f- base1 -6)) + (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u16))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2))) + (getter (c-call dmode (.str "operand_getter_" dmode) sb (.sym Dsp- offset -u16))) + (setter (c-call DFLT (.str "operand_setter_" dmode) newval sb (.sym Dsp- offset -u16))) +; (getter (mem32 smode (add (.sym Dsp- offset -u16) (reg h-sb)))) +; (setter (set (mem32 dmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval)) + ) + (define-derived-operand + (name (.sym dst32- offset -8-FB-relative- group - smode)) + (comment (.str "m32c dsp:8[fb] relative destination " smode)) + (attrs (machine 32)) + (mode dmode) + (args ((.sym Dsp- offset -s8))) + (syntax (.str "${Dsp-" offset "-s8}[fb]")) + (base-ifield (.sym f- base1 -6)) + (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s8))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3))) + (getter (c-call dmode (.str "operand_getter_" dmode) fb (.sym Dsp- offset -s8))) + (setter (c-call DFLT (.str "operand_setter_" dmode) newval fb (.sym Dsp- offset -s8))) +; (getter (mem32 smode (add (.sym Dsp- offset -s8) (reg h-fb)))) +; (setter (set (mem32 dmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval)) + ) + (define-derived-operand + (name (.sym dst32- offset -16-FB-relative- group - smode)) + (comment (.str "m32c dsp:16[fb] relative destination " smode)) + (attrs (machine 32)) + (mode dmode) + (args ((.sym Dsp- offset -s16))) + (syntax (.str "${Dsp-" offset "-s16}[fb]")) + (base-ifield (.sym f- base1 -6)) + (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s16))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3))) + (getter (c-call dmode (.str "operand_getter_" dmode) fb (.sym Dsp- offset -s16))) + (setter (c-call DFLT (.str "operand_setter_" dmode) newval fb (.sym Dsp- offset -s16))) +; (getter (mem32 smode (add (.sym Dsp- offset -s16) (reg h-fb)))) +; (setter (set (mem32 dmode (add (.sym Dsp- offset -s16) (reg h-fb))) newval)) + ) + (define-derived-operand + (name (.sym dst32- offset -8-An-relative- group - smode)) + (comment (.str "m32c dsp:8[An] relative destination " smode)) + (attrs (machine 32)) + (mode dmode) + (args ((.sym Dst32An group) (.sym Dsp- offset -u8))) + (syntax (.str "${Dsp-" offset "-u8}[$Dst32An" group "]")) + (base-ifield (.sym f- base1 -6)) + (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u8) (.sym Dst32An group))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0))) + (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u8))) + (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u8))) +; (getter (mem32 smode (add (.sym Dsp- offset -u8) (.sym Dst32An group)))) +; (setter (set (mem32 dmode (add (.sym Dsp- offset -u8) (.sym Dst32An group))) newval)) + ) + (define-derived-operand + (name (.sym dst32- offset -16-An-relative- group - smode)) + (comment (.str "m32c dsp:16[An] relative destination " smode)) + (attrs (machine 32)) + (mode dmode) + (args ((.sym Dst32An group) (.sym Dsp- offset -u16))) + (syntax (.str "${Dsp-" offset "-u16}[$Dst32An" group "]")) + (base-ifield (.sym f- base1 -6)) + (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u16) (.sym Dst32An group))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0))) + (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u16))) + (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u16))) +; (getter (mem32 smode (add (.sym Dsp- offset -u16) (.sym Dst32An group)))) +; (setter (set (mem32 dmode (add (.sym Dsp- offset -u16) (.sym Dst32An group))) newval)) + ) + (define-derived-operand + (name (.sym dst32- offset -24-An-relative- group - smode)) + (comment (.str "m32c dsp:16[An] relative destination " smode)) + (attrs (machine 32)) + (mode dmode) + (args ((.sym Dst32An group) (.sym Dsp- offset -u24))) + (syntax (.str "${Dsp-" offset "-u24}[$Dst32An" group "]")) + (base-ifield (.sym f- base1 -6)) + (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u24) (.sym Dst32An group))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0))) + (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u24))) + (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u24))) +; (getter (mem32 smode (add (.sym Dsp- offset -u24) (.sym Dst32An group)))) +; (setter (set (mem32 dmode (add (.sym Dsp- offset -u24) (.sym Dst32An group))) newval)) + ) + ) +) + +(dst32-relative-operand 16 Unprefixed 4 8 QI QI) +(dst32-relative-operand 24 Unprefixed 4 8 QI QI) +(dst32-relative-operand 32 Unprefixed 4 8 QI QI) +(dst32-relative-operand 40 Unprefixed 4 8 QI QI) +(dst32-relative-operand 16 Unprefixed 4 8 HI HI) +(dst32-relative-operand 24 Unprefixed 4 8 HI HI) +(dst32-relative-operand 32 Unprefixed 4 8 HI HI) +(dst32-relative-operand 40 Unprefixed 4 8 HI HI) +(dst32-relative-operand 16 Unprefixed 4 8 SI SI) +(dst32-relative-operand 24 Unprefixed 4 8 SI SI) +(dst32-relative-operand 32 Unprefixed 4 8 SI SI) +(dst32-relative-operand 40 Unprefixed 4 8 SI SI) + +(dst32-relative-operand 24 Prefixed 12 16 QI QI) +(dst32-relative-operand 32 Prefixed 12 16 QI QI) +(dst32-relative-operand 40 Prefixed 12 16 QI QI) +(dst32-relative-operand 48 Prefixed 12 16 QI QI) +(dst32-relative-operand 24 Prefixed 12 16 HI HI) +(dst32-relative-operand 32 Prefixed 12 16 HI HI) +(dst32-relative-operand 40 Prefixed 12 16 HI HI) +(dst32-relative-operand 48 Prefixed 12 16 HI HI) +(dst32-relative-operand 24 Prefixed 12 16 SI SI) +(dst32-relative-operand 32 Prefixed 12 16 SI SI) +(dst32-relative-operand 40 Prefixed 12 16 SI SI) +(dst32-relative-operand 48 Prefixed 12 16 SI SI) + +(dst32-relative-operand 16 ExtUnprefixed 4 8 QI HI) +(dst32-relative-operand 16 ExtUnprefixed 4 8 HI SI) + +;------------------------------------------------------------- +; Absolute address +;------------------------------------------------------------- + +(define-pmacro (dst16-absolute offset xmode) + (begin + (define-derived-operand + (name (.sym dst16- offset -16-absolute- xmode)) + (comment (.str "m16c absolute address " xmode)) + (attrs (machine 16)) + (mode xmode) + (args ((.sym Dsp- offset -u16))) + (syntax (.str "${Dsp-" offset "-u16}")) + (base-ifield f-12-4) + (encoding (+ (f-12-4 #xF) (.sym Dsp- offset -u16))) + (ifield-assertion (eq f-12-4 #xF)) + (getter (mem16 xmode (.sym Dsp- offset -u16))) + (setter (set (mem16 xmode (.sym Dsp- offset -u16)) newval)) + ) + ) +) + +(dst16-absolute 16 QI) +(dst16-absolute 24 QI) +(dst16-absolute 32 QI) +(dst16-absolute 40 QI) +(dst16-absolute 48 QI) +(dst16-absolute 16 HI) +(dst16-absolute 24 HI) +(dst16-absolute 32 HI) +(dst16-absolute 40 HI) +(dst16-absolute 48 HI) +(dst16-absolute 16 SI) +(dst16-absolute 24 SI) +(dst16-absolute 32 SI) +(dst16-absolute 40 SI) +(dst16-absolute 48 SI) + +(define-derived-operand + (name dst16-16-16-absolute-Ext-QI) + (comment "m16c absolute address QI") + (attrs (machine 16)) + (mode HI) + (args (Dsp-16-u16)) + (syntax "${Dsp-16-u16}") + (base-ifield f-12-4) + (encoding (+ (f-12-4 #xF) Dsp-16-u16)) + (ifield-assertion (eq f-12-4 #xF)) + (getter (mem16 QI Dsp-16-u16)) + (setter (set (mem16 HI Dsp-16-u16) newval)) +) + +(define-pmacro (dst32-absolute offset group base1 base2 smode dmode) + (begin + (define-derived-operand + (name (.sym dst32- offset -16-absolute- group - smode)) + (comment (.str "m32c absolute address " smode)) + (attrs (machine 32)) + (mode dmode) + (args ((.sym Dsp- offset -u16))) + (syntax (.str "${Dsp-" offset "-u16}")) + (base-ifield (.sym f- base1 -6)) + (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3))) + (getter (c-call smode (.str "operand_getter_" smode) (const 0) (.sym Dsp- offset -u16))) + (setter (c-call DFLT (.str "operand_setter_" dmode) newval (const 0) (.sym Dsp- offset -u16))) +; (getter (mem32 smode (.sym Dsp- offset -u16))) +; (setter (set (mem32 dmode (.sym Dsp- offset -u16)) newval)) + ) + (define-derived-operand + (name (.sym dst32- offset -24-absolute- group - smode)) + (comment (.str "m32c absolute address " smode)) + (attrs (machine 32)) + (mode dmode) + (args ((.sym Dsp- offset -u24))) + (syntax (.str "${Dsp-" offset "-u24}")) + (base-ifield (.sym f- base1 -6)) + (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2))) + (getter (c-call smode (.str "operand_getter_" smode) (const 0) (.sym Dsp- offset -u24))) + (setter (c-call DFLT (.str "operand_setter_" dmode) newval (const 0) (.sym Dsp- offset -u24))) +; (getter (mem32 smode (.sym Dsp- offset -u24))) +; (setter (set (mem32 dmode (.sym Dsp- offset -u24)) newval)) + ) + ) +) + +(dst32-absolute 16 Unprefixed 4 8 QI QI) +(dst32-absolute 24 Unprefixed 4 8 QI QI) +(dst32-absolute 32 Unprefixed 4 8 QI QI) +(dst32-absolute 40 Unprefixed 4 8 QI QI) +(dst32-absolute 16 Unprefixed 4 8 HI HI) +(dst32-absolute 24 Unprefixed 4 8 HI HI) +(dst32-absolute 32 Unprefixed 4 8 HI HI) +(dst32-absolute 40 Unprefixed 4 8 HI HI) +(dst32-absolute 16 Unprefixed 4 8 SI SI) +(dst32-absolute 24 Unprefixed 4 8 SI SI) +(dst32-absolute 32 Unprefixed 4 8 SI SI) +(dst32-absolute 40 Unprefixed 4 8 SI SI) + +(dst32-absolute 24 Prefixed 12 16 QI QI) +(dst32-absolute 32 Prefixed 12 16 QI QI) +(dst32-absolute 40 Prefixed 12 16 QI QI) +(dst32-absolute 48 Prefixed 12 16 QI QI) +(dst32-absolute 24 Prefixed 12 16 HI HI) +(dst32-absolute 32 Prefixed 12 16 HI HI) +(dst32-absolute 40 Prefixed 12 16 HI HI) +(dst32-absolute 48 Prefixed 12 16 HI HI) +(dst32-absolute 24 Prefixed 12 16 SI SI) +(dst32-absolute 32 Prefixed 12 16 SI SI) +(dst32-absolute 40 Prefixed 12 16 SI SI) +(dst32-absolute 48 Prefixed 12 16 SI SI) + +(dst32-absolute 16 ExtUnprefixed 4 8 QI HI) +(dst32-absolute 16 ExtUnprefixed 4 8 HI SI) + +;------------------------------------------------------------- +; An indirect indirect +;------------------------------------------------------------- + +;(define-pmacro (dst-An-indirect-indirect-operand xmode) +; (define-derived-operand +; (name (.sym dst32-An-indirect-indirect- xmode)) +; (comment (.str "m32c An indirect indirect destination " xmode)) +; (attrs (machine 32)) +; (mode xmode) +; (args (Dst32AnPrefixed)) +; (syntax (.str "[[$Dst32AnPrefixed]]")) +; (base-ifield f-12-6) +; (encoding (+ (f-12-3 0) (f-16-1 0) Dst32AnPrefixed)) +; (ifield-assertion (andif (eq f-12-3 0) (eq f-16-1 0))) +; (getter (mem32 xmode (indirect-addr Dst32AnPrefixed))) +; (setter (set (mem32 xmode (indirect-addr Dst32AnPrefixed)) newval)) +; ) +;) + +; (dst-An-indirect-indirect-operand QI) +; (dst-An-indirect-indirect-operand HI) +; (dst-An-indirect-indirect-operand SI) + +;------------------------------------------------------------- +; Relative indirect +;------------------------------------------------------------- + +(define-pmacro (dst-relative-indirect-operand offset xmode) + (begin +; (define-derived-operand +; (name (.sym dst32- offset -8-SB-relative-indirect- xmode)) +; (comment (.str "m32c dsp:8[sb] relative destination " xmode)) +; (attrs (machine 32)) +; (mode xmode) +; (args ((.sym Dsp- offset -u8))) +; (syntax (.str "[${Dsp-" offset "-u8}[sb]]")) +; (base-ifield f-12-6) +; (encoding (+ (f-12-3 1) (f-16-2 2) (.sym Dsp- offset -u8))) +; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-2 2))) +; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) (reg h-sb))))) +; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) (reg h-sb)))) newval)) +; ) +; (define-derived-operand +; (name (.sym dst32- offset -16-SB-relative-indirect- xmode)) +; (comment (.str "m32c dsp:16[sb] relative destination " xmode)) +; (attrs (machine 32)) +; (mode xmode) +; (args ((.sym Dsp- offset -u16))) +; (syntax (.str "[${Dsp-" offset "-u16}[sb]]")) +; (base-ifield f-12-6) +; (encoding (+ (f-12-3 2) (f-16-2 2) (.sym Dsp- offset -u16))) +; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-2 2))) +; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) (reg h-sb))))) +; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) (reg h-sb)))) newval)) +; ) +; (define-derived-operand +; (name (.sym dst32- offset -8-FB-relative-indirect- xmode)) +; (comment (.str "m32c dsp:8[fb] relative destination " xmode)) +; (attrs (machine 32)) +; (mode xmode) +; (args ((.sym Dsp- offset -s8))) +; (syntax (.str "[${Dsp-" offset "-s8}[fb]]")) +; (base-ifield f-12-6) +; (encoding (+ (f-12-3 1) (f-16-2 3) (.sym Dsp- offset -s8))) +; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-2 3))) +; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s8) (reg h-fb))))) +; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s8) (reg h-fb)))) newval)) +; ) +; (define-derived-operand +; (name (.sym dst32- offset -16-FB-relative-indirect- xmode)) +; (comment (.str "m32c dsp:16[fb] relative destination " xmode)) +; (attrs (machine 32)) +; (mode xmode) +; (args ((.sym Dsp- offset -s16))) +; (syntax (.str "[${Dsp-" offset "-s16}[fb]]")) +; (base-ifield f-12-6) +; (encoding (+ (f-12-3 2) (f-16-2 3) (.sym Dsp- offset -s16))) +; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-2 3))) +; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s16) (reg h-fb))))) +; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s16) (reg h-fb)))) newval)) +; ) +; (define-derived-operand +; (name (.sym dst32- offset -8-An-relative-indirect- xmode)) +; (comment (.str "m32c dsp:8[An] relative indirect destination " xmode)) +; (attrs (machine 32)) +; (mode xmode) +; (args (Dst32AnPrefixed (.sym Dsp- offset -u8))) +; (syntax (.str "[${Dsp-" offset "-u8}[$Dst32AnPrefixed]]")) +; (base-ifield f-12-6) +; (encoding (+ (f-12-3 1) (f-16-1 0) (.sym Dsp- offset -u8) Dst32AnPrefixed)) +; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-1 0))) +; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) Dst32AnPrefixed)))) +; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) Dst32AnPrefixed))) newval)) +; ) +; (define-derived-operand +; (name (.sym dst32- offset -16-An-relative-indirect- xmode)) +; (comment (.str "m32c dsp:16[An] relative destination " xmode)) +; (attrs (machine 32)) +; (mode xmode) +; (args (Dst32AnPrefixed (.sym Dsp- offset -u16))) +; (syntax (.str "[${Dsp-" offset "-u16}[$Dst32AnPrefixed]]")) +; (base-ifield f-12-6) +; (encoding (+ (f-12-3 2) (f-16-1 0) (.sym Dsp- offset -u16) Dst32AnPrefixed)) +; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-1 0))) +; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) Dst32AnPrefixed)))) +; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) Dst32AnPrefixed))) newval)) +; ) +; (define-derived-operand +; (name (.sym dst32- offset -24-An-relative-indirect- xmode)) +; (comment (.str "m32c dsp:24[An] relative destination " xmode)) +; (attrs (machine 32)) +; (mode xmode) +; (args (Dst32AnPrefixed (.sym Dsp- offset -u24))) +; (syntax (.str "[${Dsp-" offset "-u24}[$Dst32AnPrefixed]]")) +; (base-ifield f-12-6) +; (encoding (+ (f-12-3 3) (f-16-1 0) (.sym Dsp- offset -u24) Dst32AnPrefixed)) +; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-1 0))) +; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u24) Dst32AnPrefixed)))) +; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u24) Dst32AnPrefixed))) newval)) +; ) + ) +) + +; (dst-relative-indirect-operand 24 QI) +; (dst-relative-indirect-operand 32 QI) +; (dst-relative-indirect-operand 40 QI) +; (dst-relative-indirect-operand 48 QI) +; (dst-relative-indirect-operand 24 HI) +; (dst-relative-indirect-operand 32 HI) +; (dst-relative-indirect-operand 40 HI) +; (dst-relative-indirect-operand 48 HI) +; (dst-relative-indirect-operand 24 SI) +; (dst-relative-indirect-operand 32 SI) +; (dst-relative-indirect-operand 40 SI) +; (dst-relative-indirect-operand 48 SI) + +;------------------------------------------------------------- +; Absolute indirect +;------------------------------------------------------------- + +(define-pmacro (dst-absolute-indirect offset xmode) + (begin +; (define-derived-operand +; (name (.sym dst32- offset -16-absolute-indirect-derived- xmode)) +; (comment (.str "m32c absolute indirect address " xmode)) +; (attrs (machine 32)) +; (mode xmode) +; (args ((.sym Dsp- offset -u16))) +; (syntax (.str "[${Dsp-" offset "-u16}]")) +; (base-ifield f-12-6) +; (encoding (+ (f-12-3 3) (f-16-2 3) (.sym Dsp- offset -u16))) +; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-2 3))) +; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u16)))) +; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))) newval)) +; ) +; (define-derived-operand +; (name (.sym dst32- offset -24-absolute-indirect-derived- xmode)) +; (comment (.str "m32c absolute indirect address " xmode)) +; (attrs (machine 32)) +; (mode xmode) +; (args ((.sym Dsp- offset -u24))) +; (syntax (.str "[${Dsp-" offset "-u24}]")) +; (base-ifield f-12-6) +; (encoding (+ (f-12-3 3) (f-16-2 2) (.sym Dsp- offset -u24))) +; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-2 2))) +; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u24)))) +; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))) newval)) +; ) + ) +) + +(dst-absolute-indirect 24 QI) +(dst-absolute-indirect 32 QI) +(dst-absolute-indirect 40 QI) +(dst-absolute-indirect 48 QI) +(dst-absolute-indirect 24 HI) +(dst-absolute-indirect 32 HI) +(dst-absolute-indirect 40 HI) +(dst-absolute-indirect 48 HI) +(dst-absolute-indirect 24 SI) +(dst-absolute-indirect 32 SI) +(dst-absolute-indirect 40 SI) +(dst-absolute-indirect 48 SI) + +;------------------------------------------------------------- +; Bit operands +;------------------------------------------------------------- +(define-pmacro (get-register-bit reg bitno) + (and (srl reg bitno) 1) +) + +(define-pmacro (set-register-bit reg bitno value) + (set reg (or (and reg (inv (sll 1 bitno))) + (sll (and QI value 1) bitno))) +) + +(define-pmacro (get-memory-bit mach base bitno) + (and (srl (mem-mach mach QI (add base (div bitno 8))) + (mod bitno 8)) + 1) +) + +(define-pmacro (set-memory-bit mach base bitno value) + (sequence ((USI addr)) + (set addr (add base (div bitno 8))) + (set (mem-mach mach QI addr) + (or (and (mem-mach mach QI addr) + (inv (sll 1 (mod bitno 8)))) + (sll (and QI value 1) (mod bitno 8))))) +) + +;------------------------------------------------------------- +; Rn direct +;------------------------------------------------------------- + +(define-derived-operand + (name bit16-Rn-direct) + (comment "m16c Rn direct bit") + (attrs (machine 16)) + (mode BI) + (args (Bitno16R Bit16Rn)) + (syntax "$Bitno16R,$Bit16Rn") + (base-ifield f-12-4) + (encoding (+ (f-12-2 0) Bit16Rn Bitno16R)) + (ifield-assertion (eq f-12-2 0)) + (getter (get-register-bit Bit16Rn Bitno16R)) + (setter (set-register-bit Bit16Rn Bitno16R newval)) +) + +(define-pmacro (bit32-Rn-direct-operand group base) + (begin + (define-derived-operand + (name (.sym bit32-Rn-direct- group)) + (comment "m32c Rn direct bit") + (attrs (machine 32)) + (mode BI) + (args ((.sym Bitno32 group) (.sym Bit32Rn group))) + (syntax (.str "$Bitno32" group ",$Bit32Rn" group)) + (base-ifield (.sym f- base -6)) + (encoding (+ ((.sym f- base -3) 4) (.sym Bit32Rn group) (.sym Bitno32 group))) + (ifield-assertion (eq (.sym f- base -3) 4)) + (getter (get-register-bit (.sym Bit32Rn group) (.sym Bitno32 group))) + (setter (set-register-bit (.sym Bit32Rn group) (.sym Bitno32 group) newval)) + ) + ) +) + +(bit32-Rn-direct-operand Unprefixed 4) +(bit32-Rn-direct-operand Prefixed 12) + +;------------------------------------------------------------- +; An direct +;------------------------------------------------------------- + +(define-derived-operand + (name bit16-An-direct) + (comment "m16c An direct bit") + (attrs (machine 16)) + (mode BI) + (args (Bitno16R Bit16An)) + (syntax "$Bitno16R,$Bit16An") + (base-ifield f-12-4) + (encoding (+ (f-12-2 1) (f-14-1 0) Bit16An Bitno16R)) + (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 0))) + (getter (get-register-bit Bit16An Bitno16R)) + (setter (set-register-bit Bit16An Bitno16R newval)) +) + +(define-pmacro (bit32-An-direct-operand group base1 base2) + (begin + (define-derived-operand + (name (.sym bit32-An-direct- group)) + (comment "m32c An direct bit") + (attrs (machine 32)) + (mode BI) + (args ((.sym Bitno32 group) (.sym Bit32An group))) + (syntax (.str "$Bitno32" group ",$Bit32An" group)) + (base-ifield (.sym f- base1 -6)) + (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Bit32An group) (.sym Bitno32 group))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1))) + (getter (get-register-bit (.sym Bit32An group) (.sym Bitno32 group))) + (setter (set-register-bit (.sym Bit32An group) (.sym Bitno32 group) newval)) + ) + ) +) + +(bit32-An-direct-operand Unprefixed 4 8) +(bit32-An-direct-operand Prefixed 12 16) + +;------------------------------------------------------------- +; An indirect +;------------------------------------------------------------- + +(define-derived-operand + (name bit16-An-indirect) + (comment "m16c An indirect bit") + (attrs (machine 16)) + (mode BI) + (args (Bit16An)) + (syntax "[$Bit16An]") + (base-ifield f-12-4) + (encoding (+ (f-12-2 1) (f-14-1 1) Bit16An)) + (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1))) + (getter (get-memory-bit 16 0 Bit16An)) + (setter (set-memory-bit 16 0 Bit16An newval)) +) + +(define-pmacro (bit32-An-indirect-operand group base1 base2) + (begin + (define-derived-operand + (name (.sym bit32-An-indirect- group)) + (comment "m32c An indirect destination ") + (attrs (machine 32)) + (mode BI) + (args ((.sym Bitno32 group) (.sym Bit32An group))) + (syntax (.str "$Bitno32" group ",[$Bit32An" group "]")) + (base-ifield (.sym f- base1 -6)) + (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Bit32An group) (.sym Bitno32 group))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0))) + (getter (get-memory-bit 32 (.sym Bit32An group) (.sym Bitno32 group))) + (setter (set-memory-bit 32 (.sym Bit32An group) (.sym Bitno32 group) newval)) + ) + ) +) + +(bit32-An-indirect-operand Unprefixed 4 8) +(bit32-An-indirect-operand Prefixed 12 16) + +;------------------------------------------------------------- +; dsp:d[r] relative +;------------------------------------------------------------- + +(define-pmacro (bit16-relative-operand offset) + (begin + (define-derived-operand + (name (.sym bit16- offset -8-SB-relative)) + (comment (.str "m16c dsp:8[sb] relative bit " xmode)) + (attrs (machine 16)) + (mode BI) + (args ((.sym BitBase16- offset -u8))) + (syntax (.str "${BitBase16-" offset "-u8}[sb]")) + (base-ifield f-12-4) + (encoding (+ (f-12-4 #xA) (.sym BitBase16- offset -u8))) + (ifield-assertion (eq f-12-4 #xA)) + (getter (get-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u8))) + (setter (set-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u8) newval)) + ) + (define-derived-operand + (name (.sym bit16- offset -16-SB-relative)) + (comment (.str "m16c dsp:16[sb] relative bit " xmode)) + (attrs (machine 16)) + (mode BI) + (args ((.sym BitBase16- offset -u16))) + (syntax (.str "${BitBase16-" offset "-u16}[sb]")) + (base-ifield f-12-4) + (encoding (+ (f-12-4 #xE) (.sym BitBase16- offset -u16))) + (ifield-assertion (eq f-12-4 #xE)) + (getter (get-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u16))) + (setter (set-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u16) newval)) + ) + (define-derived-operand + (name (.sym bit16- offset -8-FB-relative)) + (comment (.str "m16c dsp:8[fb] relative bit " xmode)) + (attrs (machine 16)) + (mode BI) + (args ((.sym BitBase16- offset -s8))) + (syntax (.str "${BitBase16-" offset "-s8}[fb]")) + (base-ifield f-12-4) + (encoding (+ (f-12-4 #xB) (.sym BitBase16- offset -s8))) + (ifield-assertion (eq f-12-4 #xB)) + (getter (get-memory-bit 16 (reg h-fb) (.sym BitBase16- offset -s8))) + (setter (set-memory-bit 16 (reg h-fb) (.sym BitBase16- offset -s8) newval)) + ) + (define-derived-operand + (name (.sym bit16- offset -8-An-relative)) + (comment (.str "m16c dsp:8[An] relative bit " xmode)) + (attrs (machine 16)) + (mode BI) + (args (Bit16An (.sym Dsp- offset -u8))) + (syntax (.str "${Dsp-" offset "-u8}[$Bit16An]")) + (base-ifield f-12-4) + (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Bit16An)) + (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0))) + (getter (get-memory-bit 16 (.sym Dsp- offset -u8) Bit16An)) + (setter (set-memory-bit 16 (.sym Dsp- offset -u8) Bit16An newval)) + ) + (define-derived-operand + (name (.sym bit16- offset -16-An-relative)) + (comment (.str "m16c dsp:16[An] relative bit " xmode)) + (attrs (machine 16)) + (mode BI) + (args (Bit16An (.sym Dsp- offset -u16))) + (syntax (.str "${Dsp-" offset "-u16}[$Bit16An]")) + (base-ifield f-12-4) + (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Bit16An)) + (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0))) + (getter (get-memory-bit 16 (.sym Dsp- offset -u16) Bit16An)) + (setter (set-memory-bit 16 (.sym Dsp- offset -u16) Bit16An newval)) + ) + ) +) + +(bit16-relative-operand 16) + +(define-pmacro (bit32-relative-operand offset group base1 base2) + (begin + (define-derived-operand + (name (.sym bit32- offset -11-SB-relative- group)) + (comment "m32c bit,base:11[sb] relative bit") + (attrs (machine 32)) + (mode BI) + (args ((.sym BitBase32- offset -u11- group))) + (syntax (.str "${BitBase32-" offset "-u11-" group "}[sb]")) + (base-ifield (.sym f- base1 -12)) + (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u11- group))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2))) + (getter (get-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u11- group))) + (setter (set-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u11- group) newval)) + ) + (define-derived-operand + (name (.sym bit32- offset -19-SB-relative- group)) + (comment "m32c bit,base:19[sb] relative bit") + (attrs (machine 32)) + (mode BI) + (args ((.sym BitBase32- offset -u19- group))) + (syntax (.str "${BitBase32-" offset "-u19-" group "}[sb]")) + (base-ifield (.sym f- base1 -12)) + (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u19- group))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2))) + (getter (get-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u19- group))) + (setter (set-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u19- group) newval)) + ) + (define-derived-operand + (name (.sym bit32- offset -11-FB-relative- group)) + (comment "m32c bit,base:11[fb] relative bit") + (attrs (machine 32)) + (mode BI) + (args ((.sym BitBase32- offset -s11- group))) + (syntax (.str "${BitBase32-" offset "-s11-" group "}[fb]")) + (base-ifield (.sym f- base1 -12)) + (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -s11- group))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3))) + (getter (get-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s11- group))) + (setter (set-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s11- group) newval)) + ) + (define-derived-operand + (name (.sym bit32- offset -19-FB-relative- group)) + (comment "m32c bit,base:19[fb] relative bit") + (attrs (machine 32)) + (mode BI) + (args ((.sym BitBase32- offset -s19- group))) + (syntax (.str "${BitBase32-" offset "-s19-" group "}[fb]")) + (base-ifield (.sym f- base1 -12)) + (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -s19- group))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3))) + (getter (get-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s19- group))) + (setter (set-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s19- group) newval)) + ) + (define-derived-operand + (name (.sym bit32- offset -11-An-relative- group)) + (comment "m32c bit,base:11[An] relative bit") + (attrs (machine 32)) + (mode BI) + (args ((.sym BitBase32- offset -u11- group) (.sym Bit32An group))) + (syntax (.str "${BitBase32-" offset "-u11-" group "}[$Bit32An" group "]")) + (base-ifield (.sym f- base1 -12)) + (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u11- group) (.sym Bit32An group))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0))) + (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u11- group))) + (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u11- group) newval)) + ) + (define-derived-operand + (name (.sym bit32- offset -19-An-relative- group)) + (comment "m32c bit,base:19[An] relative bit") + (attrs (machine 32)) + (mode BI) + (args ((.sym BitBase32- offset -u19- group) (.sym Bit32An group))) + (syntax (.str "${BitBase32-" offset "-u19-" group "}[$Bit32An" group "]")) + (base-ifield (.sym f- base1 -12)) + (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u19- group) (.sym Bit32An group))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0))) + (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u19- group))) + (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u19- group) newval)) + ) + (define-derived-operand + (name (.sym bit32- offset -27-An-relative- group)) + (comment "m32c bit,base:27[An] relative bit") + (attrs (machine 32)) + (mode BI) + (args ((.sym BitBase32- offset -u27- group) (.sym Bit32An group))) + (syntax (.str "${BitBase32-" offset "-u27-" group "}[$Bit32An" group "]")) + (base-ifield (.sym f- base1 -12)) + (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u27- group) (.sym Bit32An group))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0))) + (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u27- group))) + (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u27- group) newval)) + ) + ) +) + +(bit32-relative-operand 16 Unprefixed 4 8) +(bit32-relative-operand 24 Prefixed 12 16) + +(define-derived-operand + (name bit16-11-SB-relative-S) + (comment "m16c bit,base:11[sb] relative bit") + (attrs (machine 16)) + (mode BI) + (args (BitBase16-8-u11-S)) + (syntax "${BitBase16-8-u11-S}[sb]") + (base-ifield (.sym f-5-3)) + (encoding (+ BitBase16-8-u11-S)) +; (ifield-assertion (#t)) + (getter (get-memory-bit 16 (reg h-sb) BitBase16-8-u11-S)) + (setter (set-memory-bit 16 (reg h-sb) BitBase16-8-u11-S newval)) +) + +(define-derived-operand + (name Rn16-push-S-derived) + (comment "m16c r0[lh] for push,pop short version") + (attrs (machine 16)) + (mode QI) + (args (Rn16-push-S)) + (syntax "${Rn16-push-S}") + (base-ifield (.sym f-4-1)) + (encoding (+ Rn16-push-S)) +; (ifield-assertion (#t)) + (getter (trunc QI Rn16-push-S)) + (setter (set Rn16-push-S newval)) +) + +(define-derived-operand + (name An16-push-S-derived) + (comment "m16c r0[lh] for push,pop short version") + (attrs (machine 16)) + (mode HI) + (args (An16-push-S)) + (syntax "${An16-push-S}") + (base-ifield (.sym f-4-1)) + (encoding (+ An16-push-S)) +; (ifield-assertion (#t)) + (getter (trunc QI An16-push-S)) + (setter (set An16-push-S newval)) +) + +;------------------------------------------------------------- +; Absolute address +;------------------------------------------------------------- + +(define-pmacro (bit16-absolute offset) + (begin + (define-derived-operand + (name (.sym bit16- offset -16-absolute)) + (comment "m16c absolute address") + (attrs (machine 16)) + (mode BI) + (args ((.sym BitBase16- offset -u16))) + (syntax (.str "${BitBase16-" offset "-u16}")) + (base-ifield f-12-4) + (encoding (+ (f-12-4 #xF) (.sym BitBase16- offset -u16))) + (ifield-assertion (eq f-12-4 #xF)) + (getter (get-memory-bit 16 0 (.sym BitBase16- offset -u16))) + (setter (set-memory-bit 16 0 (.sym BitBase16- offset -u16) newval)) + ) + ) +) + +(bit16-absolute 16) + +(define-pmacro (bit32-absolute offset group base1 base2) + (begin + (define-derived-operand + (name (.sym bit32- offset -19-absolute- group)) + (comment "m32c absolute address bit") + (attrs (machine 32)) + (mode BI) + (args ((.sym BitBase32- offset -u19- group))) + (syntax (.str "${BitBase32-" offset "-u19-" group "}")) + (base-ifield (.sym f- base1 -12)) + (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -u19- group))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3))) + (getter (get-memory-bit 32 0 (.sym BitBase32- offset -u19- group))) + (setter (set-memory-bit 32 0 (.sym BitBase32- offset -u19- group) newval)) + ) + (define-derived-operand + (name (.sym bit32- offset -27-absolute- group)) + (comment "m32c absolute address bit") + (attrs (machine 32)) + (mode BI) + (args ((.sym BitBase32- offset -u27- group))) + (syntax (.str "${BitBase32-" offset "-u27-" group "}")) + (base-ifield (.sym f- base1 -12)) + (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u27- group))) + (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2))) + (getter (get-memory-bit 32 0 (.sym BitBase32- offset -u27- group))) + (setter (set-memory-bit 32 0 (.sym BitBase32- offset -u27- group) newval)) + ) + ) +) + +(bit32-absolute 16 Unprefixed 4 8) +(bit32-absolute 24 Prefixed 12 16) + +;------------------------------------------------------------- +; Destination operands for short fomat insns +;------------------------------------------------------------- + +(define-derived-operand + (name dst16-3-S-R0l-direct-QI) + (comment "m16c R0l direct QI") + (attrs (machine 16)) + (mode QI) + (args (R0l)) + (syntax "r0l") + (base-ifield f-5-3) + (encoding (+ (f-5-3 4))) + (ifield-assertion (eq f-5-3 4)) + (getter (trunc QI R0l)) + (setter (set R0l newval)) +) +(define-derived-operand + (name dst16-3-S-R0h-direct-QI) + (comment "m16c R0h direct QI") + (attrs (machine 16)) + (mode QI) + (args (R0h)) + (syntax "r0h") + (base-ifield f-5-3) + (encoding (+ (f-5-3 3))) + (ifield-assertion (eq f-5-3 3)) + (getter (trunc QI R0h)) + (setter (set R0h newval)) +) +(define-derived-operand + (name dst16-3-S-8-8-SB-relative-QI) + (comment "m16c SB relative QI") + (attrs (machine 16)) + (mode QI) + (args (Dsp-8-u8)) + (syntax "${Dsp-8-u8}[sb]") + (base-ifield f-5-3) + (encoding (+ (f-5-3 5) Dsp-8-u8)) + (ifield-assertion (eq f-5-3 5)) + (getter (mem16 QI (add Dsp-8-u8 (reg h-sb)))) + (setter (set (mem16 QI (add Dsp-8-u8 (reg h-sb))) newval)) +) +(define-derived-operand + (name dst16-3-S-8-8-FB-relative-QI) + (comment "m16c FB relative QI") + (attrs (machine 16)) + (mode QI) + (args (Dsp-8-s8)) + (syntax "${Dsp-8-s8}[fb]") + (base-ifield f-5-3) + (encoding (+ (f-5-3 6) Dsp-8-s8)) + (ifield-assertion (eq f-5-3 6)) + (getter (mem16 QI (add Dsp-8-s8 (reg h-fb)))) + (setter (set (mem16 QI (add Dsp-8-s8 (reg h-fb))) newval)) +) +(define-derived-operand + (name dst16-3-S-8-16-absolute-QI) + (comment "m16c absolute address QI") + (attrs (machine 16)) + (mode QI) + (args (Dsp-8-u16)) + (syntax "${Dsp-8-u16}") + (base-ifield f-5-3) + (encoding (+ (f-5-3 7) Dsp-8-u16)) + (ifield-assertion (eq f-5-3 7)) + (getter (mem16 QI Dsp-8-u16)) + (setter (set (mem16 QI Dsp-8-u16) newval)) +) +(define-derived-operand + (name dst16-3-S-16-8-SB-relative-QI) + (comment "m16c SB relative QI") + (attrs (machine 16)) + (mode QI) + (args (Dsp-16-u8)) + (syntax "${Dsp-16-u8}[sb]") + (base-ifield f-5-3) + (encoding (+ (f-5-3 5) Dsp-16-u8)) + (ifield-assertion (eq f-5-3 5)) + (getter (mem16 QI (add Dsp-16-u8 (reg h-sb)))) + (setter (set (mem16 QI (add Dsp-16-u8 (reg h-sb))) newval)) +) +(define-derived-operand + (name dst16-3-S-16-8-FB-relative-QI) + (comment "m16c FB relative QI") + (attrs (machine 16)) + (mode QI) + (args (Dsp-16-s8)) + (syntax "${Dsp-16-s8}[fb]") + (base-ifield f-5-3) + (encoding (+ (f-5-3 6) Dsp-16-s8)) + (ifield-assertion (eq f-5-3 6)) + (getter (mem16 QI (add Dsp-16-s8 (reg h-fb)))) + (setter (set (mem16 QI (add Dsp-16-s8 (reg h-fb))) newval)) +) +(define-derived-operand + (name dst16-3-S-16-16-absolute-QI) + (comment "m16c absolute address QI") + (attrs (machine 16)) + (mode QI) + (args (Dsp-16-u16)) + (syntax "${Dsp-16-u16}") + (base-ifield f-5-3) + (encoding (+ (f-5-3 7) Dsp-16-u16)) + (ifield-assertion (eq f-5-3 7)) + (getter (mem16 QI Dsp-16-u16)) + (setter (set (mem16 QI Dsp-16-u16) newval)) +) +(define-derived-operand + (name srcdst16-r0l-r0h-S-derived) + (comment "m16c r0l/r0h operand for short format insns") + (attrs (machine 16)) + (mode SI) + (args (SrcDst16-r0l-r0h-S-normal)) + (syntax "${SrcDst16-r0l-r0h-S-normal}") + (base-ifield f-6-3) + (encoding (+ (f-6-2 0) SrcDst16-r0l-r0h-S-normal)) + (ifield-assertion (eq f-6-2 0)) + (getter (trunc SI SrcDst16-r0l-r0h-S-normal)) + (setter ()) ; no setter +) +(define-derived-operand + (name dst32-2-S-R0l-direct-QI) + (comment "m32c R0l direct QI") + (attrs (machine 32)) + (mode QI) + (args (R0l)) + (syntax "r0l") + (base-ifield f-2-2) + (encoding (+ (f-2-2 0))) + (ifield-assertion (eq f-2-2 0)) + (getter (trunc QI R0l)) + (setter (set R0l newval)) +) +(define-derived-operand + (name dst32-2-S-R0-direct-HI) + (comment "m32c R0 direct HI") + (attrs (machine 32)) + (mode HI) + (args (R0)) + (syntax "r0") + (base-ifield f-2-2) + (encoding (+ (f-2-2 0))) + (ifield-assertion (eq f-2-2 0)) + (getter (trunc HI R0)) + (setter (set R0 newval)) +) +(define-derived-operand + (name dst32-1-S-A0-direct-HI) + (comment "m32c A0 direct HI") + (attrs (machine 32)) + (mode HI) + (args (A0)) + (syntax "a0") + (base-ifield f-7-1) + (encoding (+ (f-7-1 0))) + (ifield-assertion (eq f-7-1 0)) + (getter (trunc HI A0)) + (setter (set A0 newval)) +) +(define-derived-operand + (name dst32-1-S-A1-direct-HI) + (comment "m32c A1 direct HI") + (attrs (machine 32)) + (mode HI) + (args (A1)) + (syntax "a1") + (base-ifield f-7-1) + (encoding (+ (f-7-1 1))) + (ifield-assertion (eq f-7-1 1)) + (getter (trunc HI A1)) + (setter (set A1 newval)) +) +(define-pmacro (dst32-2-S-operands xmode) + (begin + (define-derived-operand + (name (.sym dst32-2-S-8-SB-relative- xmode)) + (comment "m32c SB relative for short binary insns") + (attrs (machine 32)) + (mode xmode) + (args (Dsp-8-u8)) + (syntax "${Dsp-8-u8}[sb]") + (base-ifield f-2-2) + (encoding (+ (f-2-2 2) Dsp-8-u8)) + (ifield-assertion (eq f-2-2 2)) + (getter (c-call xmode (.str "operand_getter_" xmode) sb Dsp-8-u8)) + (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb Dsp-8-u8)) +; (getter (mem32 xmode (add Dsp-8-u8 (reg h-sb)))) +; (setter (set (mem32 xmode (add Dsp-8-u8 (reg h-sb))) newval)) + ) + (define-derived-operand + (name (.sym dst32-2-S-8-FB-relative- xmode)) + (comment "m32c FB relative for short binary insns") + (attrs (machine 32)) + (mode xmode) + (args (Dsp-8-s8)) + (syntax "${Dsp-8-s8}[fb]") + (base-ifield f-2-2) + (encoding (+ (f-2-2 3) Dsp-8-s8)) + (ifield-assertion (eq f-2-2 3)) + (getter (c-call xmode (.str "operand_getter_" xmode) fb Dsp-8-s8)) + (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb Dsp-8-s8)) +; (getter (mem32 xmode (add Dsp-8-s8 (reg h-fb)))) +; (setter (set (mem32 xmode (add Dsp-8-s8 (reg h-fb))) newval)) + ) + (define-derived-operand + (name (.sym dst32-2-S-16-absolute- xmode)) + (comment "m32c absolute address for short binary insns") + (attrs (machine 32)) + (mode xmode) + (args (Dsp-8-u16)) + (syntax "${Dsp-8-u16}") + (base-ifield f-2-2) + (encoding (+ (f-2-2 1) Dsp-8-u16)) + (ifield-assertion (eq f-2-2 1)) + (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) Dsp-8-u16)) + (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) Dsp-8-u16)) +; (getter (mem32 xmode Dsp-8-u16)) +; (setter (set (mem32 xmode Dsp-8-u16) newval)) + ) +; (define-derived-operand +; (name (.sym dst32-2-S-8-SB-relative-indirect- xmode)) +; (comment "m32c SB relative for short binary insns") +; (attrs (machine 32)) +; (mode xmode) +; (args (Dsp-16-u8)) +; (syntax "[${Dsp-16-u8}[sb]]") +; (base-ifield f-10-2) +; (encoding (+ (f-10-2 2) Dsp-16-u8)) +; (ifield-assertion (eq f-10-2 2)) +; (getter (mem32 xmode (indirect-addr (add Dsp-16-u8 (reg h-sb))))) +; (setter (set (mem32 xmode (indirect-addr (add Dsp-16-u8 (reg h-sb)))) newval)) +; ) +; (define-derived-operand +; (name (.sym dst32-2-S-8-FB-relative-indirect- xmode)) +; (comment "m32c FB relative for short binary insns") +; (attrs (machine 32)) +; (mode xmode) +; (args (Dsp-16-s8)) +; (syntax "[${Dsp-16-s8}[fb]]") +; (base-ifield f-10-2) +; (encoding (+ (f-10-2 3) Dsp-16-s8)) +; (ifield-assertion (eq f-10-2 3)) +; (getter (mem32 xmode (indirect-addr (add Dsp-16-s8 (reg h-fb))))) +; (setter (set (mem32 xmode (indirect-addr (add Dsp-16-s8 (reg h-fb)))) newval)) +; ) +; (define-derived-operand +; (name (.sym dst32-2-S-16-absolute-indirect- xmode)) +; (comment "m32c absolute address for short binary insns") +; (attrs (machine 32)) +; (mode xmode) +; (args (Dsp-16-u16)) +; (syntax "[${Dsp-16-u16}]") +; (base-ifield f-10-2) +; (encoding (+ (f-10-2 1) Dsp-16-u16)) +; (ifield-assertion (eq f-10-2 1)) +; (getter (mem32 xmode (indirect-addr Dsp-16-u16))) +; (setter (set (mem32 xmode (indirect-addr Dsp-16-u16)) newval)) +; ) + ) +) + +(dst32-2-S-operands QI) +(dst32-2-S-operands HI) +(dst32-2-S-operands SI) + +;============================================================= +; Anyof operands +;------------------------------------------------------------- +; Source operands with no additional fields +;------------------------------------------------------------- + +(define-pmacro (src16-basic-operand xmode) + (begin + (define-anyof-operand + (name (.sym src16-basic- xmode)) + (comment (.str "m16c source operand of size " xmode " with no additional fields")) + (attrs (machine 16)) + (mode xmode) + (choices + (.sym src16-Rn-direct- xmode) + (.sym src16-An-direct- xmode) + (.sym src16-An-indirect- xmode) + ) + ) + ) +) +(src16-basic-operand QI) +(src16-basic-operand HI) + +(define-pmacro (src32-basic-operand xmode) + (begin + (define-anyof-operand + (name (.sym src32-basic-Unprefixed- xmode)) + (comment (.str "m32c destination operand of size " xmode " with no additional fields")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym src32-Rn-direct-Unprefixed- xmode) + (.sym src32-An-direct-Unprefixed- xmode) + (.sym src32-An-indirect-Unprefixed- xmode) + ) + ) + (define-anyof-operand + (name (.sym src32-basic-Prefixed- xmode)) + (comment (.str "m32c destination operand of size " xmode " with no additional fields")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym src32-Rn-direct-Prefixed- xmode) + (.sym src32-An-direct-Prefixed- xmode) + (.sym src32-An-indirect-Prefixed- xmode) + ) + ) +; (define-anyof-operand +; (name (.sym src32-basic-indirect- xmode)) +; (comment (.str "m32c destination operand of size " xmode " indirect with no additional fields")) +; (attrs (machine 32)) +; (mode xmode) +; (choices +; (.sym src32-An-indirect-indirect- xmode) +; ) +; ) + ) +) + +(src32-basic-operand QI) +(src32-basic-operand HI) +(src32-basic-operand SI) + +(define-anyof-operand + (name src32-basic-ExtPrefixed-QI) + (comment "m32c source operand of size QI with no additional fields") + (attrs (machine 32)) + (mode QI) + (choices + src32-Rn-direct-Prefixed-QI + src32-An-indirect-Prefixed-QI + ) +) + +;------------------------------------------------------------- +; Source operands with additional fields at offset 16 bits +;------------------------------------------------------------- + +(define-pmacro (src16-16-operand xmode) + (begin + (define-anyof-operand + (name (.sym src16-16-8- xmode)) + (comment (.str "m16c source operand of size " xmode " with additional 8 bit fields at offset 16")) + (attrs (machine 16)) + (mode xmode) + (choices + (.sym src16-16-8-An-relative- xmode) + (.sym src16-16-8-SB-relative- xmode) + (.sym src16-16-8-FB-relative- xmode) + ) + ) + (define-anyof-operand + (name (.sym src16-16-16- xmode)) + (comment (.str "m16c source operand of size " xmode " with additional 16 bit fields at offset 16")) + (attrs (machine 16)) + (mode xmode) + (choices + (.sym src16-16-16-An-relative- xmode) + (.sym src16-16-16-SB-relative- xmode) + (.sym src16-16-16-absolute- xmode) + ) + ) + ) +) +(src16-16-operand QI) +(src16-16-operand HI) + +(define-pmacro (src32-16-operand xmode) + (begin + (define-anyof-operand + (name (.sym src32-16-8-Unprefixed- xmode)) + (comment (.str "m32c source operand of size " xmode " with additional 8 bit fields at offset 16")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym src32-16-8-An-relative-Unprefixed- xmode) + (.sym src32-16-8-SB-relative-Unprefixed- xmode) + (.sym src32-16-8-FB-relative-Unprefixed- xmode) + ) + ) + (define-anyof-operand + (name (.sym src32-16-16-Unprefixed- xmode)) + (comment (.str "m32c source operand of size " xmode " with additional 16 bit fields at offset 16")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym src32-16-16-An-relative-Unprefixed- xmode) + (.sym src32-16-16-SB-relative-Unprefixed- xmode) + (.sym src32-16-16-FB-relative-Unprefixed- xmode) + (.sym src32-16-16-absolute-Unprefixed- xmode) + ) + ) + (define-anyof-operand + (name (.sym src32-16-24-Unprefixed- xmode)) + (comment (.str "m32c source operand of size " xmode " with additional 24 bit fields at offset 16")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym src32-16-24-An-relative-Unprefixed- xmode) + (.sym src32-16-24-absolute-Unprefixed- xmode) + ) + ) + ) +) + +(src32-16-operand QI) +(src32-16-operand HI) +(src32-16-operand SI) + +;------------------------------------------------------------- +; Source operands with additional fields at offset 24 bits +;------------------------------------------------------------- + +(define-pmacro (src-24-operand group xmode) + (begin + (define-anyof-operand + (name (.sym src32-24-8- group - xmode)) + (comment (.str "m32c source operand of size " xmode " with additional 8 bit fields at offset 24")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym src32-24-8-An-relative- group - xmode) + (.sym src32-24-8-SB-relative- group - xmode) + (.sym src32-24-8-FB-relative- group - xmode) + ) + ) + (define-anyof-operand + (name (.sym src32-24-16- group - xmode)) + (comment (.str "m32c source operand of size " xmode " with additional 16 bit fields at offset 16")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym src32-24-16-An-relative- group - xmode) + (.sym src32-24-16-SB-relative- group - xmode) + (.sym src32-24-16-FB-relative- group - xmode) + (.sym src32-24-16-absolute- group - xmode) + ) + ) + (define-anyof-operand + (name (.sym src32-24-24- group - xmode)) + (comment (.str "m32c source operand of size " xmode " with additional 24 bit fields at offset 16")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym src32-24-24-An-relative- group - xmode) + (.sym src32-24-24-absolute- group - xmode) + ) + ) + ) +) + +(src-24-operand Prefixed QI) +(src-24-operand Prefixed HI) +(src-24-operand Prefixed SI) + +(define-pmacro (src-24-indirect-operand xmode) + (begin +; (define-anyof-operand +; (name (.sym src32-24-8-indirect- xmode)) +; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) +; (attrs (machine 32)) +; (mode xmode) +; (choices +; (.sym src32-24-8-An-relative-indirect- xmode) +; (.sym src32-24-8-SB-relative-indirect- xmode) +; (.sym src32-24-8-FB-relative-indirect- xmode) +; ) +; ) +; (define-anyof-operand +; (name (.sym src32-24-16-indirect- xmode)) +; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) +; (attrs (machine 32)) +; (mode xmode) +; (choices +; (.sym src32-24-16-An-relative-indirect- xmode) +; (.sym src32-24-16-SB-relative-indirect- xmode) +; (.sym src32-24-16-FB-relative-indirect- xmode) +; ) +; ) +; (define-anyof-operand +; (name (.sym src32-24-24-indirect- xmode)) +; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) +; (attrs (machine 32)) +; (mode xmode) +; (choices +; (.sym src32-24-24-An-relative-indirect- xmode) +; ) +; ) +; (define-anyof-operand +; (name (.sym src32-24-16-absolute-indirect- xmode)) +; (comment (.str "m32c source operand of size " xmode " 16 bit absolute indirect")) +; (attrs (machine 32)) +; (mode xmode) +; (choices +; (.sym src32-24-16-absolute-indirect-derived- xmode) +; ) +; ) +; (define-anyof-operand +; (name (.sym src32-24-24-absolute-indirect- xmode)) +; (comment (.str "m32c source operand of size " xmode " 24 bit absolute indirect")) +; (attrs (machine 32)) +; (mode xmode) +; (choices +; (.sym src32-24-24-absolute-indirect-derived- xmode) +; ) +; ) + ) +) + +; (src-24-indirect-operand QI) +; (src-24-indirect-operand HI) +; (src-24-indirect-operand SI) + +;------------------------------------------------------------- +; Destination operands with no additional fields +;------------------------------------------------------------- + +(define-pmacro (dst16-basic-operand xmode) + (begin + (define-anyof-operand + (name (.sym dst16-basic- xmode)) + (comment (.str "m16c destination operand of size " xmode " with no additional fields")) + (attrs (machine 16)) + (mode xmode) + (choices + (.sym dst16-Rn-direct- xmode) + (.sym dst16-An-direct- xmode) + (.sym dst16-An-indirect- xmode) + ) + ) + ) +) + +(dst16-basic-operand QI) +(dst16-basic-operand HI) +(dst16-basic-operand SI) + +(define-pmacro (dst32-basic-operand xmode) + (begin + (define-anyof-operand + (name (.sym dst32-basic-Unprefixed- xmode)) + (comment (.str "m32c destination operand of size " xmode " with no additional fields")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym dst32-Rn-direct-Unprefixed- xmode) + (.sym dst32-An-direct-Unprefixed- xmode) + (.sym dst32-An-indirect-Unprefixed- xmode) + ) + ) + (define-anyof-operand + (name (.sym dst32-basic-Prefixed- xmode)) + (comment (.str "m32c destination operand of size " xmode " with no additional fields")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym dst32-Rn-direct-Prefixed- xmode) + (.sym dst32-An-direct-Prefixed- xmode) + (.sym dst32-An-indirect-Prefixed- xmode) + ) + ) + ) +) + +(dst32-basic-operand QI) +(dst32-basic-operand HI) +(dst32-basic-operand SI) + +;------------------------------------------------------------- +; Destination operands with possible additional fields at offset 16 bits +;------------------------------------------------------------- + +(define-pmacro (dst16-16-operand xmode) + (begin + (define-anyof-operand + (name (.sym dst16-16- xmode)) + (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) + (attrs (machine 16)) + (mode xmode) + (choices + (.sym dst16-Rn-direct- xmode) + (.sym dst16-An-direct- xmode) + (.sym dst16-An-indirect- xmode) + (.sym dst16-16-8-An-relative- xmode) + (.sym dst16-16-16-An-relative- xmode) + (.sym dst16-16-8-SB-relative- xmode) + (.sym dst16-16-16-SB-relative- xmode) + (.sym dst16-16-8-FB-relative- xmode) + (.sym dst16-16-16-absolute- xmode) + ) + ) + (define-anyof-operand + (name (.sym dst16-16-8- xmode)) + (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) + (attrs (machine 16)) + (mode xmode) + (choices + (.sym dst16-16-8-An-relative- xmode) + (.sym dst16-16-8-SB-relative- xmode) + (.sym dst16-16-8-FB-relative- xmode) + ) + ) + (define-anyof-operand + (name (.sym dst16-16-16- xmode)) + (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) + (attrs (machine 16)) + (mode xmode) + (choices + (.sym dst16-16-16-An-relative- xmode) + (.sym dst16-16-16-SB-relative- xmode) + (.sym dst16-16-16-absolute- xmode) + ) + ) + ) +) + +(dst16-16-operand QI) +(dst16-16-operand HI) +(dst16-16-operand SI) + +(define-anyof-operand + (name dst16-16-Ext-QI) + (comment "m16c destination operand of size QI for 'ext' insns with additional fields at offset 16") + (attrs (machine 16)) + (mode QI) + (choices + dst16-Rn-direct-Ext-QI + dst16-An-indirect-Ext-QI + dst16-16-8-An-relative-Ext-QI + dst16-16-16-An-relative-Ext-QI + dst16-16-8-SB-relative-Ext-QI + dst16-16-16-SB-relative-Ext-QI + dst16-16-8-FB-relative-Ext-QI + dst16-16-16-absolute-Ext-QI + ) +) + +(define-derived-operand + (name dst16-An-indirect-Mova-HI) + (comment "m16c addressof An indirect destination HI") + (attrs (ISA m16c)) + (mode HI) + (args (Dst16An)) + (syntax "[$Dst16An]") + (base-ifield f-12-4) + (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An)) + (ifield-assertion + (andif (eq f-12-2 1) (eq f-14-1 1))) + (getter Dst16An) + (setter (nop)) + ) + +(define-derived-operand + (name dst16-16-8-An-relative-Mova-HI) + (comment + "m16c addressof dsp:8[An] relative destination HI") + (attrs (ISA m16c)) + (mode HI) + (args (Dst16An Dsp-16-u8)) + (syntax "${Dsp-16-u8}[$Dst16An]") + (base-ifield f-12-4) + (encoding + (+ (f-12-2 2) (f-14-1 0) Dsp-16-u8 Dst16An)) + (ifield-assertion + (andif (eq f-12-2 2) (eq f-14-1 0))) + (getter (add Dsp-16-u8 Dst16An)) + (setter (nop)) +) +(define-derived-operand + (name dst16-16-16-An-relative-Mova-HI) + (comment + "m16c addressof dsp:16[An] relative destination HI") + (attrs (ISA m16c)) + (mode HI) + (args (Dst16An Dsp-16-u16)) + (syntax "${Dsp-16-u16}[$Dst16An]") + (base-ifield f-12-4) + (encoding + (+ (f-12-2 3) (f-14-1 0) Dsp-16-u16 Dst16An)) + (ifield-assertion + (andif (eq f-12-2 3) (eq f-14-1 0))) + (getter (add Dsp-16-u16 Dst16An)) + (setter (nop)) + ) +(define-derived-operand + (name dst16-16-8-SB-relative-Mova-HI) + (comment + "m16c addressof dsp:8[sb] relative destination HI") + (attrs (ISA m16c)) + (mode HI) + (args (Dsp-16-u8)) + (syntax "${Dsp-16-u8}[sb]") + (base-ifield f-12-4) + (encoding (+ (f-12-4 10) Dsp-16-u8)) + (ifield-assertion (eq f-12-4 10)) + (getter (add Dsp-16-u8 (reg h-sb))) + (setter (nop)) +) +(define-derived-operand + (name dst16-16-16-SB-relative-Mova-HI) + (comment + "m16c addressof dsp:16[sb] relative destination HI") + (attrs (ISA m16c)) + (mode HI) + (args (Dsp-16-u16)) + (syntax "${Dsp-16-u16}[sb]") + (base-ifield f-12-4) + (encoding (+ (f-12-4 14) Dsp-16-u16)) + (ifield-assertion (eq f-12-4 14)) + (getter (add Dsp-16-u16 (reg h-sb))) + (setter (nop)) + ) +(define-derived-operand + (name dst16-16-8-FB-relative-Mova-HI) + (comment + "m16c addressof dsp:8[fb] relative destination HI") + (attrs (ISA m16c)) + (mode HI) + (args (Dsp-16-s8)) + (syntax "${Dsp-16-s8}[fb]") + (base-ifield f-12-4) + (encoding (+ (f-12-4 11) Dsp-16-s8)) + (ifield-assertion (eq f-12-4 11)) + (getter (add Dsp-16-s8 (reg h-fb))) + (setter (nop)) + ) +(define-derived-operand + (name dst16-16-16-absolute-Mova-HI) + (comment "m16c addressof absolute address HI") + (attrs (ISA m16c)) + (mode HI) + (args (Dsp-16-u16)) + (syntax "${Dsp-16-u16}") + (base-ifield f-12-4) + (encoding (+ (f-12-4 15) Dsp-16-u16)) + (ifield-assertion (eq f-12-4 15)) + (getter Dsp-16-u16) + (setter (nop)) + ) + +(define-anyof-operand + (name dst16-16-Mova-HI) + (comment "m16c addressof destination operand of size HI with additional fields at offset 16") + (attrs (machine 16)) + (mode HI) + (choices + dst16-An-indirect-Mova-HI + dst16-16-8-An-relative-Mova-HI + dst16-16-16-An-relative-Mova-HI + dst16-16-8-SB-relative-Mova-HI + dst16-16-16-SB-relative-Mova-HI + dst16-16-8-FB-relative-Mova-HI + dst16-16-16-absolute-Mova-HI + ) +) + +(define-derived-operand + (name dst32-An-indirect-Unprefixed-Mova-SI) + (comment "m32c addressof An indirect destination SI") + (attrs (ISA m32c)) + (mode SI) + (args (Dst32AnUnprefixed)) + (syntax "[$Dst32AnUnprefixed]") + (base-ifield f-4-6) + (encoding + (+ (f-4-3 0) (f-8-1 0) Dst32AnUnprefixed)) + (ifield-assertion + (andif (eq f-4-3 0) (eq f-8-1 0))) + (getter Dst32AnUnprefixed) + (setter (nop)) + ) + +(define-derived-operand + (name dst32-16-8-An-relative-Unprefixed-Mova-SI) + (comment "m32c addressof dsp:8[An] relative destination SI") + (attrs (ISA m32c)) + (mode SI) + (args (Dst32AnUnprefixed Dsp-16-u8)) + (syntax "${Dsp-16-u8}[$Dst32AnUnprefixed]") + (base-ifield f-4-6) + (encoding + (+ (f-4-3 1) + (f-8-1 0) + Dsp-16-u8 + Dst32AnUnprefixed)) + (ifield-assertion + (andif (eq f-4-3 1) (eq f-8-1 0))) + (getter (add Dsp-16-u8 Dst32AnUnprefixed)) + (setter (nop)) +) + +(define-derived-operand + (name dst32-16-16-An-relative-Unprefixed-Mova-SI) + (comment + "m32c addressof dsp:16[An] relative destination SI") + (attrs (ISA m32c)) + (mode SI) + (args (Dst32AnUnprefixed Dsp-16-u16)) + (syntax "${Dsp-16-u16}[$Dst32AnUnprefixed]") + (base-ifield f-4-6) + (encoding + (+ (f-4-3 2) + (f-8-1 0) + Dsp-16-u16 + Dst32AnUnprefixed)) + (ifield-assertion + (andif (eq f-4-3 2) (eq f-8-1 0))) + (getter (add Dsp-16-u16 Dst32AnUnprefixed)) + (setter (nop)) + ) + +(define-derived-operand + (name dst32-16-24-An-relative-Unprefixed-Mova-SI) + (comment "addressof m32c dsp:16[An] relative destination SI") + (attrs (ISA m32c)) + (mode SI) + (args (Dst32AnUnprefixed Dsp-16-u24)) + (syntax "${Dsp-16-u24}[$Dst32AnUnprefixed]") + (base-ifield f-4-6) + (encoding + (+ (f-4-3 3) + (f-8-1 0) + Dsp-16-u24 + Dst32AnUnprefixed)) + (ifield-assertion + (andif (eq f-4-3 3) (eq f-8-1 0))) + (getter (add Dsp-16-u24 Dst32AnUnprefixed)) + (setter (nop)) + ) + +(define-derived-operand + (name dst32-16-8-SB-relative-Unprefixed-Mova-SI) + (comment "m32c addressof dsp:8[sb] relative destination SI") + (attrs (ISA m32c)) + (mode SI) + (args (Dsp-16-u8)) + (syntax "${Dsp-16-u8}[sb]") + (base-ifield f-4-6) + (encoding (+ (f-4-3 1) (f-8-2 2) Dsp-16-u8)) + (ifield-assertion + (andif (eq f-4-3 1) (eq f-8-2 2))) + (getter (add Dsp-16-u8 (reg h-sb))) + (setter (nop)) + ) + +(define-derived-operand + (name dst32-16-16-SB-relative-Unprefixed-Mova-SI) + (comment "m32c addressof dsp:16[sb] relative destination SI") + (attrs (ISA m32c)) + (mode SI) + (args (Dsp-16-u16)) + (syntax "${Dsp-16-u16}[sb]") + (base-ifield f-4-6) + (encoding (+ (f-4-3 2) (f-8-2 2) Dsp-16-u16)) + (ifield-assertion + (andif (eq f-4-3 2) (eq f-8-2 2))) + (getter (add Dsp-16-u16 (reg h-sb))) + (setter (nop)) + ) + +(define-derived-operand + (name dst32-16-8-FB-relative-Unprefixed-Mova-SI) + (comment "m32c addressof dsp:8[fb] relative destination SI") + (attrs (ISA m32c)) + (mode SI) + (args (Dsp-16-s8)) + (syntax "${Dsp-16-s8}[fb]") + (base-ifield f-4-6) + (encoding (+ (f-4-3 1) (f-8-2 3) Dsp-16-s8)) + (ifield-assertion + (andif (eq f-4-3 1) (eq f-8-2 3))) + (getter (add Dsp-16-s8 (reg h-fb))) + (setter (nop)) + ) + +(define-derived-operand + (name dst32-16-16-FB-relative-Unprefixed-Mova-SI) + (comment "m32c addressof dsp:16[fb] relative destination SI") + (attrs (ISA m32c)) + (mode SI) + (args (Dsp-16-s16)) + (syntax "${Dsp-16-s16}[fb]") + (base-ifield f-4-6) + (encoding (+ (f-4-3 2) (f-8-2 3) Dsp-16-s16)) + (ifield-assertion + (andif (eq f-4-3 2) (eq f-8-2 3))) + (getter (add Dsp-16-s16 (reg h-fb))) + (setter (nop)) + ) + +(define-derived-operand + (name dst32-16-16-absolute-Unprefixed-Mova-SI) + (comment "m32c addressof absolute address SI") (attrs (ISA m32c)) + (mode SI) + (args (Dsp-16-u16)) + (syntax "${Dsp-16-u16}") + (base-ifield f-4-6) + (encoding (+ (f-4-3 3) (f-8-2 3) Dsp-16-u16)) + (ifield-assertion + (andif (eq f-4-3 3) (eq f-8-2 3))) + (getter Dsp-16-u16) + (setter (nop)) + ) + +(define-derived-operand + (name dst32-16-24-absolute-Unprefixed-Mova-SI) + (comment "m32c addressof absolute address SI") (attrs (ISA m32c)) + (mode SI) + (args (Dsp-16-u24)) + (syntax "${Dsp-16-u24}") + (base-ifield f-4-6) + (encoding (+ (f-4-3 3) (f-8-2 2) Dsp-16-u24)) + (ifield-assertion + (andif (eq f-4-3 3) (eq f-8-2 2))) + (getter Dsp-16-u24) + (setter (nop)) + ) + +(define-anyof-operand + (name dst32-16-Unprefixed-Mova-SI) + (comment + "m32c addressof destination operand of size SI with additional fields at offset 16") + (attrs (ISA m32c)) + (mode SI) + (choices + dst32-An-indirect-Unprefixed-Mova-SI + dst32-16-8-An-relative-Unprefixed-Mova-SI + dst32-16-16-An-relative-Unprefixed-Mova-SI + dst32-16-24-An-relative-Unprefixed-Mova-SI + dst32-16-8-SB-relative-Unprefixed-Mova-SI + dst32-16-16-SB-relative-Unprefixed-Mova-SI + dst32-16-8-FB-relative-Unprefixed-Mova-SI + dst32-16-16-FB-relative-Unprefixed-Mova-SI + dst32-16-16-absolute-Unprefixed-Mova-SI + dst32-16-24-absolute-Unprefixed-Mova-SI)) + +(define-pmacro (dst32-16-operand xmode) + (begin + (define-anyof-operand + (name (.sym dst32-16-Unprefixed- xmode)) + (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym dst32-Rn-direct-Unprefixed- xmode) + (.sym dst32-An-direct-Unprefixed- xmode) + (.sym dst32-An-indirect-Unprefixed- xmode) + (.sym dst32-16-8-An-relative-Unprefixed- xmode) + (.sym dst32-16-16-An-relative-Unprefixed- xmode) + (.sym dst32-16-24-An-relative-Unprefixed- xmode) + (.sym dst32-16-8-SB-relative-Unprefixed- xmode) + (.sym dst32-16-16-SB-relative-Unprefixed- xmode) + (.sym dst32-16-8-FB-relative-Unprefixed- xmode) + (.sym dst32-16-16-FB-relative-Unprefixed- xmode) + (.sym dst32-16-16-absolute-Unprefixed- xmode) + (.sym dst32-16-24-absolute-Unprefixed- xmode) + ) + ) + (define-anyof-operand + (name (.sym dst32-16-8-Unprefixed- xmode)) + (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym dst32-16-8-An-relative-Unprefixed- xmode) + (.sym dst32-16-8-SB-relative-Unprefixed- xmode) + (.sym dst32-16-8-FB-relative-Unprefixed- xmode) + ) + ) + (define-anyof-operand + (name (.sym dst32-16-16-Unprefixed- xmode)) + (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym dst32-16-16-An-relative-Unprefixed- xmode) + (.sym dst32-16-16-SB-relative-Unprefixed- xmode) + (.sym dst32-16-16-FB-relative-Unprefixed- xmode) + (.sym dst32-16-16-absolute-Unprefixed- xmode) + ) + ) + (define-anyof-operand + (name (.sym dst32-16-24-Unprefixed- xmode)) + (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym dst32-16-24-An-relative-Unprefixed- xmode) + (.sym dst32-16-24-absolute-Unprefixed- xmode) + ) + ) + ) +) + +(dst32-16-operand QI) +(dst32-16-operand HI) +(dst32-16-operand SI) + +(define-pmacro (dst32-16-Ext-operand smode dmode) + (begin + (define-anyof-operand + (name (.sym dst32-16-ExtUnprefixed- smode)) + (comment (.str "m32c destination operand of size " smode " with additional fields at offset 16")) + (attrs (machine 32)) + (mode dmode) + (choices + (.sym dst32-Rn-direct-ExtUnprefixed- smode) + (.sym dst32-An-direct-Unprefixed- dmode) ; ExtUnprefixed mode not required for this operand -- use the normal dmode version + (.sym dst32-An-indirect-ExtUnprefixed- smode) + (.sym dst32-16-8-An-relative-ExtUnprefixed- smode) + (.sym dst32-16-16-An-relative-ExtUnprefixed- smode) + (.sym dst32-16-24-An-relative-ExtUnprefixed- smode) + (.sym dst32-16-8-SB-relative-ExtUnprefixed- smode) + (.sym dst32-16-16-SB-relative-ExtUnprefixed- smode) + (.sym dst32-16-8-FB-relative-ExtUnprefixed- smode) + (.sym dst32-16-16-FB-relative-ExtUnprefixed- smode) + (.sym dst32-16-16-absolute-ExtUnprefixed- smode) + (.sym dst32-16-24-absolute-ExtUnprefixed- smode) + ) + ) + ) +) + +(dst32-16-Ext-operand QI HI) +(dst32-16-Ext-operand HI SI) + +(define-anyof-operand + (name dst32-16-Unprefixed-Mulex-HI) + (comment "m32c destination operand of size HI with additional fields at offset 16") + (attrs (machine 32)) + (mode HI) + (choices + dst32-R3-direct-Unprefixed-HI + dst32-An-direct-Unprefixed-HI + dst32-An-indirect-Unprefixed-HI + dst32-16-8-An-relative-Unprefixed-HI + dst32-16-16-An-relative-Unprefixed-HI + dst32-16-24-An-relative-Unprefixed-HI + dst32-16-8-SB-relative-Unprefixed-HI + dst32-16-16-SB-relative-Unprefixed-HI + dst32-16-8-FB-relative-Unprefixed-HI + dst32-16-16-FB-relative-Unprefixed-HI + dst32-16-16-absolute-Unprefixed-HI + dst32-16-24-absolute-Unprefixed-HI + ) +) +;------------------------------------------------------------- +; Destination operands with possible additional fields at offset 24 bits +;------------------------------------------------------------- + +(define-pmacro (dst16-24-operand xmode) + (begin + (define-anyof-operand + (name (.sym dst16-24- xmode)) + (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 24")) + (attrs (machine 16)) + (mode xmode) + (choices + (.sym dst16-Rn-direct- xmode) + (.sym dst16-An-direct- xmode) + (.sym dst16-An-indirect- xmode) + (.sym dst16-24-8-An-relative- xmode) + (.sym dst16-24-16-An-relative- xmode) + (.sym dst16-24-8-SB-relative- xmode) + (.sym dst16-24-16-SB-relative- xmode) + (.sym dst16-24-8-FB-relative- xmode) + (.sym dst16-24-16-absolute- xmode) + ) + ) + ) +) + +(dst16-24-operand QI) +(dst16-24-operand HI) + +(define-pmacro (dst32-24-operand xmode) + (begin + (define-anyof-operand + (name (.sym dst32-24-Unprefixed- xmode)) + (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym dst32-Rn-direct-Unprefixed- xmode) + (.sym dst32-An-direct-Unprefixed- xmode) + (.sym dst32-An-indirect-Unprefixed- xmode) + (.sym dst32-24-8-An-relative-Unprefixed- xmode) + (.sym dst32-24-16-An-relative-Unprefixed- xmode) + (.sym dst32-24-24-An-relative-Unprefixed- xmode) + (.sym dst32-24-8-SB-relative-Unprefixed- xmode) + (.sym dst32-24-16-SB-relative-Unprefixed- xmode) + (.sym dst32-24-8-FB-relative-Unprefixed- xmode) + (.sym dst32-24-16-FB-relative-Unprefixed- xmode) + (.sym dst32-24-16-absolute-Unprefixed- xmode) + (.sym dst32-24-24-absolute-Unprefixed- xmode) + ) + ) + (define-anyof-operand + (name (.sym dst32-24-Prefixed- xmode)) + (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym dst32-Rn-direct-Prefixed- xmode) + (.sym dst32-An-direct-Prefixed- xmode) + (.sym dst32-An-indirect-Prefixed- xmode) + (.sym dst32-24-8-An-relative-Prefixed- xmode) + (.sym dst32-24-16-An-relative-Prefixed- xmode) + (.sym dst32-24-24-An-relative-Prefixed- xmode) + (.sym dst32-24-8-SB-relative-Prefixed- xmode) + (.sym dst32-24-16-SB-relative-Prefixed- xmode) + (.sym dst32-24-8-FB-relative-Prefixed- xmode) + (.sym dst32-24-16-FB-relative-Prefixed- xmode) + (.sym dst32-24-16-absolute-Prefixed- xmode) + (.sym dst32-24-24-absolute-Prefixed- xmode) + ) + ) + (define-anyof-operand + (name (.sym dst32-24-8-Prefixed- xmode)) + (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym dst32-24-8-An-relative-Prefixed- xmode) + (.sym dst32-24-8-SB-relative-Prefixed- xmode) + (.sym dst32-24-8-FB-relative-Prefixed- xmode) + ) + ) + (define-anyof-operand + (name (.sym dst32-24-16-Prefixed- xmode)) + (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym dst32-24-16-An-relative-Prefixed- xmode) + (.sym dst32-24-16-SB-relative-Prefixed- xmode) + (.sym dst32-24-16-FB-relative-Prefixed- xmode) + (.sym dst32-24-16-absolute-Prefixed- xmode) + ) + ) + (define-anyof-operand + (name (.sym dst32-24-24-Prefixed- xmode)) + (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym dst32-24-24-An-relative-Prefixed- xmode) + (.sym dst32-24-24-absolute-Prefixed- xmode) + ) + ) +; (define-anyof-operand +; (name (.sym dst32-24-indirect- xmode)) +; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) +; (attrs (machine 32)) +; (mode xmode) +; (choices +; (.sym dst32-An-indirect-indirect- xmode) +; (.sym dst32-24-8-An-relative-indirect- xmode) +; (.sym dst32-24-16-An-relative-indirect- xmode) +; (.sym dst32-24-24-An-relative-indirect- xmode) +; (.sym dst32-24-8-SB-relative-indirect- xmode) +; (.sym dst32-24-16-SB-relative-indirect- xmode) +; (.sym dst32-24-8-FB-relative-indirect- xmode) +; (.sym dst32-24-16-FB-relative-indirect- xmode) +; ) +; ) +; (define-anyof-operand +; (name (.sym dst32-basic-indirect- xmode)) +; (comment (.str "m32c destination operand of size " xmode " with no additional fields")) +; (attrs (machine 32)) +; (mode xmode) +; (choices +; (.sym dst32-An-indirect-indirect- xmode) +; ) +; ) +; (define-anyof-operand +; (name (.sym dst32-24-8-indirect- xmode)) +; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) +; (attrs (machine 32)) +; (mode xmode) +; (choices +; (.sym dst32-24-8-An-relative-indirect- xmode) +; (.sym dst32-24-8-SB-relative-indirect- xmode) +; (.sym dst32-24-8-FB-relative-indirect- xmode) +; ) +; ) +; (define-anyof-operand +; (name (.sym dst32-24-16-indirect- xmode)) +; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) +; (attrs (machine 32)) +; (mode xmode) +; (choices +; (.sym dst32-24-16-An-relative-indirect- xmode) +; (.sym dst32-24-16-SB-relative-indirect- xmode) +; (.sym dst32-24-16-FB-relative-indirect- xmode) +; ) +; ) +; (define-anyof-operand +; (name (.sym dst32-24-24-indirect- xmode)) +; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) +; (attrs (machine 32)) +; (mode xmode) +; (choices +; (.sym dst32-24-24-An-relative-indirect- xmode) +; ) +; ) +; (define-anyof-operand +; (name (.sym dst32-24-absolute-indirect- xmode)) +; (comment (.str "m32c destination operand of size " xmode " absolute indirect")) +; (attrs (machine 32)) +; (mode xmode) +; (choices +; (.sym dst32-24-16-absolute-indirect-derived- xmode) +; (.sym dst32-24-24-absolute-indirect-derived- xmode) +; ) +; ) +; (define-anyof-operand +; (name (.sym dst32-24-16-absolute-indirect- xmode)) +; (comment (.str "m32c destination operand of size " xmode " absolute indirect")) +; (attrs (machine 32)) +; (mode xmode) +; (choices +; (.sym dst32-24-16-absolute-indirect-derived- xmode) +; ) +; ) +; (define-anyof-operand +; (name (.sym dst32-24-24-absolute-indirect- xmode)) +; (comment (.str "m32c destination operand of size " xmode " absolute indirect")) +; (attrs (machine 32)) +; (mode xmode) +; (choices +; (.sym dst32-24-24-absolute-indirect-derived- xmode) +; ) +; ) + ) +) + +(dst32-24-operand QI) +(dst32-24-operand HI) +(dst32-24-operand SI) + +;------------------------------------------------------------- +; Destination operands with possible additional fields at offset 32 bits +;------------------------------------------------------------- + +(define-pmacro (dst16-32-operand xmode) + (begin + (define-anyof-operand + (name (.sym dst16-32- xmode)) + (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 32")) + (attrs (machine 16)) + (mode xmode) + (choices + (.sym dst16-Rn-direct- xmode) + (.sym dst16-An-direct- xmode) + (.sym dst16-An-indirect- xmode) + (.sym dst16-32-8-An-relative- xmode) + (.sym dst16-32-16-An-relative- xmode) + (.sym dst16-32-8-SB-relative- xmode) + (.sym dst16-32-16-SB-relative- xmode) + (.sym dst16-32-8-FB-relative- xmode) + (.sym dst16-32-16-absolute- xmode) + ) + ) + ) +) +(dst16-32-operand QI) +(dst16-32-operand HI) + +; This macro actually handles operands at offset 32, 40 and 48 bits +(define-pmacro (dst32-32plus-operand offset xmode) + (begin + (define-anyof-operand + (name (.sym dst32- offset -Unprefixed- xmode)) + (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym dst32-Rn-direct-Unprefixed- xmode) + (.sym dst32-An-direct-Unprefixed- xmode) + (.sym dst32-An-indirect-Unprefixed- xmode) + (.sym dst32- offset -8-An-relative-Unprefixed- xmode) + (.sym dst32- offset -16-An-relative-Unprefixed- xmode) + (.sym dst32- offset -24-An-relative-Unprefixed- xmode) + (.sym dst32- offset -8-SB-relative-Unprefixed- xmode) + (.sym dst32- offset -16-SB-relative-Unprefixed- xmode) + (.sym dst32- offset -8-FB-relative-Unprefixed- xmode) + (.sym dst32- offset -16-FB-relative-Unprefixed- xmode) + (.sym dst32- offset -16-absolute-Unprefixed- xmode) + (.sym dst32- offset -24-absolute-Unprefixed- xmode) + ) + ) + (define-anyof-operand + (name (.sym dst32- offset -Prefixed- xmode)) + (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym dst32-Rn-direct-Prefixed- xmode) + (.sym dst32-An-direct-Prefixed- xmode) + (.sym dst32-An-indirect-Prefixed- xmode) + (.sym dst32- offset -8-An-relative-Prefixed- xmode) + (.sym dst32- offset -16-An-relative-Prefixed- xmode) + (.sym dst32- offset -24-An-relative-Prefixed- xmode) + (.sym dst32- offset -8-SB-relative-Prefixed- xmode) + (.sym dst32- offset -16-SB-relative-Prefixed- xmode) + (.sym dst32- offset -8-FB-relative-Prefixed- xmode) + (.sym dst32- offset -16-FB-relative-Prefixed- xmode) + (.sym dst32- offset -16-absolute-Prefixed- xmode) + (.sym dst32- offset -24-absolute-Prefixed- xmode) + ) + ) +; (define-anyof-operand +; (name (.sym dst32- offset -indirect- xmode)) +; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32")) +; (attrs (machine 32)) +; (mode xmode) +; (choices +; (.sym dst32-An-indirect-indirect- xmode) +; (.sym dst32- offset -8-An-relative-indirect- xmode) +; (.sym dst32- offset -16-An-relative-indirect- xmode) +; (.sym dst32- offset -24-An-relative-indirect- xmode) +; (.sym dst32- offset -8-SB-relative-indirect- xmode) +; (.sym dst32- offset -16-SB-relative-indirect- xmode) +; (.sym dst32- offset -8-FB-relative-indirect- xmode) +; (.sym dst32- offset -16-FB-relative-indirect- xmode) +; ) +; ) +; (define-anyof-operand +; (name (.sym dst32- offset -absolute-indirect- xmode)) +; (comment (.str "m32c destination operand of size " xmode " absolute indirect")) +; (attrs (machine 32)) +; (mode xmode) +; (choices +; (.sym dst32- offset -16-absolute-indirect-derived- xmode) +; (.sym dst32- offset -24-absolute-indirect-derived- xmode) +; ) +; ) + ) +) + +(dst32-32plus-operand 32 QI) +(dst32-32plus-operand 32 HI) +(dst32-32plus-operand 32 SI) +(dst32-32plus-operand 40 QI) +(dst32-32plus-operand 40 HI) +(dst32-32plus-operand 40 SI) + +;------------------------------------------------------------- +; Destination operands with possible additional fields at offset 48 bits +;------------------------------------------------------------- + +(define-pmacro (dst32-48-operand offset xmode) + (begin + (define-anyof-operand + (name (.sym dst32- offset -Prefixed- xmode)) + (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym dst32-Rn-direct-Prefixed- xmode) + (.sym dst32-An-direct-Prefixed- xmode) + (.sym dst32-An-indirect-Prefixed- xmode) + (.sym dst32- offset -8-An-relative-Prefixed- xmode) + (.sym dst32- offset -16-An-relative-Prefixed- xmode) + (.sym dst32- offset -24-An-relative-Prefixed- xmode) + (.sym dst32- offset -8-SB-relative-Prefixed- xmode) + (.sym dst32- offset -16-SB-relative-Prefixed- xmode) + (.sym dst32- offset -8-FB-relative-Prefixed- xmode) + (.sym dst32- offset -16-FB-relative-Prefixed- xmode) + (.sym dst32- offset -16-absolute-Prefixed- xmode) + (.sym dst32- offset -24-absolute-Prefixed- xmode) + ) + ) +; (define-anyof-operand +; (name (.sym dst32- offset -indirect- xmode)) +; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32")) +; (attrs (machine 32)) +; (mode xmode) +; (choices +; (.sym dst32-An-indirect-indirect- xmode) +; (.sym dst32- offset -8-An-relative-indirect- xmode) +; (.sym dst32- offset -16-An-relative-indirect- xmode) +; (.sym dst32- offset -24-An-relative-indirect- xmode) +; (.sym dst32- offset -8-SB-relative-indirect- xmode) +; (.sym dst32- offset -16-SB-relative-indirect- xmode) +; (.sym dst32- offset -8-FB-relative-indirect- xmode) +; (.sym dst32- offset -16-FB-relative-indirect- xmode) +; ) +; ) +; (define-anyof-operand +; (name (.sym dst32- offset -absolute-indirect- xmode)) +; (comment (.str "m32c destination operand of size " xmode " absolute indirect")) +; (attrs (machine 32)) +; (mode xmode) +; (choices +; (.sym dst32- offset -16-absolute-indirect-derived- xmode) +; (.sym dst32- offset -24-absolute-indirect-derived- xmode) +; ) +; ) + ) +) + +(dst32-48-operand 48 QI) +(dst32-48-operand 48 HI) +(dst32-48-operand 48 SI) + +;------------------------------------------------------------- +; Bit operands for m16c +;------------------------------------------------------------- + +(define-pmacro (bit16-operand offset) + (begin + (define-anyof-operand + (name (.sym bit16- offset)) + (comment (.str "m16c bit operand with possible additional fields at offset 24")) + (attrs (machine 16)) + (mode BI) + (choices + bit16-Rn-direct + bit16-An-direct + bit16-An-indirect + (.sym bit16- offset -8-An-relative) + (.sym bit16- offset -16-An-relative) + (.sym bit16- offset -8-SB-relative) + (.sym bit16- offset -16-SB-relative) + (.sym bit16- offset -8-FB-relative) + (.sym bit16- offset -16-absolute) + ) + ) + (define-anyof-operand + (name (.sym bit16- offset -basic)) + (comment (.str "m16c bit operand with no additional fields")) + (attrs (machine 16)) + (mode BI) + (choices + bit16-An-indirect + ) + ) + (define-anyof-operand + (name (.sym bit16- offset -8)) + (comment (.str "m16c bit operand with possible additional fields at offset 24")) + (attrs (machine 16)) + (mode BI) + (choices + bit16-Rn-direct + bit16-An-direct + (.sym bit16- offset -8-An-relative) + (.sym bit16- offset -8-SB-relative) + (.sym bit16- offset -8-FB-relative) + ) + ) + (define-anyof-operand + (name (.sym bit16- offset -16)) + (comment (.str "m16c bit operand with possible additional fields at offset 24")) + (attrs (machine 16)) + (mode BI) + (choices + (.sym bit16- offset -16-An-relative) + (.sym bit16- offset -16-SB-relative) + (.sym bit16- offset -16-absolute) + ) + ) + ) +) + +(bit16-operand 16) + +;------------------------------------------------------------- +; Bit operands for m32c +;------------------------------------------------------------- + +(define-pmacro (bit32-operand offset group) + (begin + (define-anyof-operand + (name (.sym bit32- offset - group)) + (comment (.str "m32c bit operand with possible additional fields at offset 24")) + (attrs (machine 32)) + (mode BI) + (choices + (.sym bit32-Rn-direct- group) + (.sym bit32-An-direct- group) + (.sym bit32-An-indirect- group) + (.sym bit32- offset -11-An-relative- group) + (.sym bit32- offset -19-An-relative- group) + (.sym bit32- offset -27-An-relative- group) + (.sym bit32- offset -11-SB-relative- group) + (.sym bit32- offset -19-SB-relative- group) + (.sym bit32- offset -11-FB-relative- group) + (.sym bit32- offset -19-FB-relative- group) + (.sym bit32- offset -19-absolute- group) + (.sym bit32- offset -27-absolute- group) + ) + ) + ) +) + +(bit32-operand 16 Unprefixed) +(bit32-operand 24 Prefixed) + +(define-anyof-operand + (name bit32-basic-Unprefixed) + (comment "m32c bit operand with no additional fields") + (attrs (machine 32)) + (mode BI) + (choices + bit32-Rn-direct-Unprefixed + bit32-An-direct-Unprefixed + bit32-An-indirect-Unprefixed + ) +) + +(define-anyof-operand + (name bit32-16-8-Unprefixed) + (comment "m32c bit operand with 8 bit additional fields") + (attrs (machine 32)) + (mode BI) + (choices + bit32-16-11-An-relative-Unprefixed + bit32-16-11-SB-relative-Unprefixed + bit32-16-11-FB-relative-Unprefixed + ) +) + +(define-anyof-operand + (name bit32-16-16-Unprefixed) + (comment "m32c bit operand with 16 bit additional fields") + (attrs (machine 32)) + (mode BI) + (choices + bit32-16-19-An-relative-Unprefixed + bit32-16-19-SB-relative-Unprefixed + bit32-16-19-FB-relative-Unprefixed + bit32-16-19-absolute-Unprefixed + ) +) + +(define-anyof-operand + (name bit32-16-24-Unprefixed) + (comment "m32c bit operand with 24 bit additional fields") + (attrs (machine 32)) + (mode BI) + (choices + bit32-16-27-An-relative-Unprefixed + bit32-16-27-absolute-Unprefixed + ) +) + +;------------------------------------------------------------- +; Operands for short format binary insns +;------------------------------------------------------------- + +(define-anyof-operand + (name src16-2-S) + (comment "m16c source operand of size QI for short format insns") + (attrs (machine 16)) + (mode QI) + (choices + src16-2-S-8-SB-relative-QI + src16-2-S-8-FB-relative-QI + src16-2-S-16-absolute-QI + ) +) + +(define-anyof-operand + (name src32-2-S-QI) + (comment "m32c source operand of size QI for short format insns") + (attrs (machine 32)) + (mode QI) + (choices + src32-2-S-8-SB-relative-QI + src32-2-S-8-FB-relative-QI + src32-2-S-16-absolute-QI + ) +) + +(define-anyof-operand + (name src32-2-S-HI) + (comment "m32c source operand of size QI for short format insns") + (attrs (machine 32)) + (mode HI) + (choices + src32-2-S-8-SB-relative-HI + src32-2-S-8-FB-relative-HI + src32-2-S-16-absolute-HI + ) +) + +(define-anyof-operand + (name Dst16-3-S-8) + (comment "m16c destination operand of size QI for short format insns") + (attrs (machine 16)) + (mode QI) + (choices + dst16-3-S-R0l-direct-QI + dst16-3-S-R0h-direct-QI + dst16-3-S-8-8-SB-relative-QI + dst16-3-S-8-8-FB-relative-QI + dst16-3-S-8-16-absolute-QI + ) +) + +(define-anyof-operand + (name Dst16-3-S-16) + (comment "m16c destination operand of size QI for short format insns") + (attrs (machine 16)) + (mode QI) + (choices + dst16-3-S-R0l-direct-QI + dst16-3-S-R0h-direct-QI + dst16-3-S-16-8-SB-relative-QI + dst16-3-S-16-8-FB-relative-QI + dst16-3-S-16-16-absolute-QI + ) +) + +(define-anyof-operand + (name srcdst16-r0l-r0h-S) + (comment "m16c r0l/r0h operand of size QI for short format insns") + (attrs (machine 16)) + (mode SI) + (choices + srcdst16-r0l-r0h-S-derived + ) +) + +(define-anyof-operand + (name dst32-2-S-basic-QI) + (comment "m32c r0l operand of size QI for short format binary insns") + (attrs (machine 32)) + (mode QI) + (choices + dst32-2-S-R0l-direct-QI + ) +) + +(define-anyof-operand + (name dst32-2-S-basic-HI) + (comment "m32c r0 operand of size HI for short format binary insns") + (attrs (machine 32)) + (mode HI) + (choices + dst32-2-S-R0-direct-HI + ) +) + +(define-pmacro (dst32-2-S-operands xmode) + (begin + (define-anyof-operand + (name (.sym dst32-2-S-8- xmode)) + (comment "m32c operand of size " xmode " for short format binary insns") + (attrs (machine 32)) + (mode xmode) + (choices + (.sym dst32-2-S-8-SB-relative- xmode) + (.sym dst32-2-S-8-FB-relative- xmode) + ) + ) + (define-anyof-operand + (name (.sym dst32-2-S-16- xmode)) + (comment "m32c operand of size " xmode " for short format binary insns") + (attrs (machine 32)) + (mode xmode) + (choices + (.sym dst32-2-S-16-absolute- xmode) + ) + ) +; (define-anyof-operand +; (name (.sym dst32-2-S-8-indirect- xmode)) +; (comment "m32c operand of size " xmode " for short format binary insns") +; (attrs (machine 32)) +; (mode xmode) +; (choices +; (.sym dst32-2-S-8-SB-relative-indirect- xmode) +; (.sym dst32-2-S-8-FB-relative-indirect- xmode) +; ) +; ) +; (define-anyof-operand +; (name (.sym dst32-2-S-absolute-indirect- xmode)) +; (comment "m32c operand of size " xmode " for short format binary insns") +; (attrs (machine 32)) +; (mode xmode) +; (choices +; (.sym dst32-2-S-16-absolute-indirect- xmode) +; ) +; ) + ) +) + +(dst32-2-S-operands QI) +(dst32-2-S-operands HI) +(dst32-2-S-operands SI) + +(define-anyof-operand + (name dst32-an-S) + (comment "m32c An operand for short format binary insns") + (attrs (machine 32)) + (mode HI) + (choices + dst32-1-S-A0-direct-HI + dst32-1-S-A1-direct-HI + ) +) + +(define-anyof-operand + (name bit16-11-S) + (comment "m16c bit operand for short format insns") + (attrs (machine 16)) + (mode BI) + (choices + bit16-11-SB-relative-S + ) +) + +(define-anyof-operand + (name Rn16-push-S-anyof) + (comment "m16c bit operand for short format insns") + (attrs (machine 16)) + (mode QI) + (choices + Rn16-push-S-derived + ) +) + +(define-anyof-operand + (name An16-push-S-anyof) + (comment "m16c bit operand for short format insns") + (attrs (machine 16)) + (mode HI) + (choices + An16-push-S-derived + ) +) + +;============================================================= +; Common macros for instruction definitions +; +(define-pmacro (set-z x) + (sequence () + (set zbit (zflag x))) + +) + +(define-pmacro (set-s x) + (sequence () + (set sbit (nflag x))) +) + +(define-pmacro (set-z-and-s x) + (sequence () + (set-z x) + (set-s x)) +) + +;============================================================= +; Unary insn macros +;------------------------------------------------------------- + +(define-pmacro (unary-insn-defn mach group mode wstr op encoding sem) + (dni (.sym op mach wstr - group) + (.str op wstr " dst" mach "-" group "-" mode) + ((machine mach)) + (.str op wstr " ${dst" mach "-" group "-" mode "}") + encoding + (sem mode (.sym dst mach - group - mode)) + ()) +) + + +(define-pmacro (unary16-defn mode wstr wbit op opc1 opc2 opc3 sem) + (unary-insn-defn 16 16 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16- mode)) + sem) +) + +(define-pmacro (unary32-defn mode wstr wbit op opc1 opc2 opc3 sem) + (begin + ; Multi insns are tried for assembly in the reverse order in which they appear here, so + ; define the absolute-indirect insns first in order to prevent them from being selected + ; when the mode is register-indirect +; (unary-insn-defn 32 24-absolute-indirect mode wstr op +; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) (f-20-4 opc3)) +; sem) + (unary-insn-defn 32 16-Unprefixed mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3)) + sem) +; (unary-insn-defn 32 24-indirect mode wstr op +; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-indirect- mode) (f-18-2 opc2) (f-20-4 opc3)) +; sem) + ) +) + +(define-pmacro (unary-insn-mach mach op opc1 opc2 opc3 sem) + (begin + (.apply (.sym unary mach -defn) (QI .b 0 op opc1 opc2 opc3 sem)) + (.apply (.sym unary mach -defn) (HI .w 1 op opc1 opc2 opc3 sem)) + ) +) + +(define-pmacro (unary-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) + (begin + (unary-insn-mach 16 op opc16-1 opc16-2 opc16-3 sem) + (unary-insn-mach 32 op opc32-1 opc32-2 opc32-3 sem) + ) +) + +;------------------------------------------------------------- +; Sign/zero extension macros +;------------------------------------------------------------- + +(define-pmacro (ext-insn-defn mach group smode dmode wstr op encoding sem) + (dni (.sym op mach wstr - group) + (.str op wstr " dst" mach "-" group "-" smode) + ((machine mach)) + (.str op wstr " ${dst" mach "-" group "-" smode "}") + encoding + (sem smode dmode (.sym dst mach - group - smode) (.sym dst mach - group - smode)) + ()) +) + +(define-pmacro (ext16-defn smode dmode wstr wbit op opc1 opc2 opc3 sem) + (ext-insn-defn 16 16-Ext smode dmode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-Ext- smode)) + sem) +) + +(define-pmacro (ext32-defn smode dmode wstr wbit op opc1 opc2 opc3 sem) + (ext-insn-defn 32 16-ExtUnprefixed smode dmode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst32-16-ExtUnprefixed- smode)) + sem) +) + +(define-pmacro (ext32-binary-insn src-group dst-group op wstr encoding sem) + (dni (.sym op 32 wstr - src-group - dst-group) + (.str op 32 wstr " src32-" src-group "-QI,dst32-" dst-group "-HI") + ((machine 32)) + (.str op wstr " ${src32-" src-group "-QI},${dst32-" dst-group "-HI}") + encoding + (sem QI HI (.sym src32- src-group -QI) (.sym dst32 - dst-group -HI)) + ()) +) + +(define-pmacro (ext32-binary-defn op wstr opc1 opc2 sem) + (begin + (ext32-binary-insn basic-ExtPrefixed 24-Prefixed op wstr + (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-basic-ExtPrefixed-QI dst32-24-Prefixed-HI (f-20-4 opc2)) + sem) + (ext32-binary-insn 24-24-Prefixed 48-Prefixed op wstr + (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-24-Prefixed-QI dst32-48-Prefixed-HI (f-20-4 opc2)) + sem) + (ext32-binary-insn 24-16-Prefixed 40-Prefixed op wstr + (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-16-Prefixed-QI dst32-40-Prefixed-HI (f-20-4 opc2)) + sem) + (ext32-binary-insn 24-8-Prefixed 32-Prefixed op wstr + (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-8-Prefixed-QI dst32-32-Prefixed-HI (f-20-4 opc2)) + sem) + ) +) + +;============================================================= +; Binary Arithmetic macros +; +;------------------------------------------------------------- +;.size:S src2,r0[l] -- for m32c +;------------------------------------------------------------- + +(define-pmacro (binary-arith32-S-src2 op xmode wstr wbit opc1 opc2 sem) + (dni (.sym op 32 wstr .S-src2-r0- xmode) + (.str op 32 wstr ":S src2,r0[l]") + ((machine 32)) + (.str op wstr"$S ${src32-2-S-" xmode "},${Dst32R0" xmode "-S}") + (+ opc1 opc2 (.sym src32-2-S- xmode) (f-7-1 wbit)) + (sem xmode (.sym src32-2-S- xmode) (.sym Dst32R0 xmode -S)) + ()) +) + +;------------------------------------------------------------- +;.b:S src2,r0l/r0h -- for m16c +;------------------------------------------------------------- + +(define-pmacro (binary-arith16-b-S-src2 op opc1 opc2 sem) + (begin + (dni (.sym op 16 .b.S-src2) + (.str op ".b:S src2,r0[lh]") + ((machine 16)) + (.str op ".b$S ${src16-2-S},${Dst16RnQI-S}") + (+ opc1 opc2 Dst16RnQI-S src16-2-S) + (sem QI src16-2-S Dst16RnQI-S) + ()) + (dni (.sym op 16 .b.S-r0l-r0h) + (.str op ".b:S r0l/r0h") + ((machine 16)) + (.str op ".b$S ${srcdst16-r0l-r0h-S}") + (+ opc1 opc2 srcdst16-r0l-r0h-S) + (if (eq srcdst16-r0l-r0h-S 0) + (sem QI R0h R0l) + (sem QI R0l R0h)) + ()) + ) +) + +;------------------------------------------------------------- +;.b:S #imm8,dst3 -- for m16c +;------------------------------------------------------------- + +(define-pmacro (binary-arith16-b-S-imm8-dst3 op sz opc1 opc2 sem) + (dni (.sym op 16 .b.S-imm8-dst3) + (.str op sz ":S imm8,dst3") + ((machine 16)) + (.str op sz "$S #${Imm-8-QI},${Dst16-3-S-16}") + (+ opc1 opc2 Dst16-3-S-16 Imm-8-QI) + (sem QI Imm-8-QI Dst16-3-S-16) + ()) +) + +;------------------------------------------------------------- +;.size:Q #imm4,sp -- for m16c +;------------------------------------------------------------- + +(define-pmacro (binary-arith16-Q-sp op opc1 opc2 opc3 sem) + (dni (.sym op 16 -Q-sp) + (.str op ":Q #imm4,sp") + ((machine 16)) + (.str op "${size}$Q #${Imm-12-s4},sp") + (+ opc1 opc2 opc3 Imm-12-s4) + (sem QI Imm-12-s4 sp) + ()) +) + +;------------------------------------------------------------- +;.size:G #imm,sp -- for m16c +;------------------------------------------------------------- + +(define-pmacro (binary-arith16-G-sp-defn mode wstr wbit op opc1 opc2 opc3 opc4 sem) + (dni (.sym op 16 wstr - G-sp) + (.str op wstr " imm-sp " mode) + ((machine 16)) + (.str op wstr "$G #${Imm-16-" mode "},sp") + (+ opc1 opc2 (f-7-1 wbit) opc3 opc4 (.sym Imm-16- mode)) + (sem mode (.sym Imm-16- mode) sp) + ()) +) + +(define-pmacro (binary-arith16-G-sp op opc1 opc2 opc3 opc4 sem) + (begin + (binary-arith16-G-sp-defn QI .b 0 op opc1 opc2 opc3 opc4 sem) + (binary-arith16-G-sp-defn HI .w 1 op opc1 opc2 opc3 opc4 sem) + ) +) + +;------------------------------------------------------------- +;.size:G #imm,dst -- for m16c and m32c +;------------------------------------------------------------- + +(define-pmacro (binary-arith-imm-dst-defn mach src dstgroup dmode wstr op suffix encoding sem) + (dni (.sym op mach wstr - imm-G - dstgroup) + (.str op wstr " " mach "-imm-G-" dstgroup "-" dmode) + ((machine mach)) + (.str op wstr "$"suffix " #${" src "},${dst" mach "-" dstgroup "-" dmode "}") + encoding + (sem dmode src (.sym dst mach - dstgroup - dmode)) + ()) +) + +; m16c variants +(define-pmacro (binary-arith16-imm-dst-defn smode dmode wstr wbit op suffix opc1 opc2 opc3 sem) + (begin + (binary-arith-imm-dst-defn 16 (.sym Imm-32- smode) 16-16 dmode wstr op suffix + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- dmode) (.sym Imm-32- smode)) + sem) + (binary-arith-imm-dst-defn 16 (.sym Imm-24- smode) 16-8 dmode wstr op suffix + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- dmode) (.sym Imm-24- smode)) + sem) + (binary-arith-imm-dst-defn 16 (.sym Imm-16- smode) basic dmode wstr op suffix + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- dmode) (.sym Imm-16- smode)) + sem) + ) +) + +; m32c Unprefixed variants +(define-pmacro (binary-arith32-imm-dst-Unprefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem) + (begin + (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 16-24-Unprefixed dmode wstr op suffix + (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-24-Unprefixed- dmode) (.sym Imm-40- smode)) + sem) + (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 16-16-Unprefixed dmode wstr op suffix + (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-16-Unprefixed- dmode) (.sym Imm-32- smode)) + sem) + (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) 16-8-Unprefixed dmode wstr op suffix + (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-8-Unprefixed- dmode) (.sym Imm-24- smode)) + sem) + (binary-arith-imm-dst-defn 32 (.sym Imm-16- smode) basic-Unprefixed dmode wstr op suffix + (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-basic-Unprefixed- dmode) (.sym Imm-16- smode)) + sem) + ) +) + +; m32c Prefixed variants +(define-pmacro (binary-arith32-imm-dst-Prefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem) + (begin + (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-Prefixed dmode wstr op suffix + (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-Prefixed- dmode) (.sym Imm-48- smode)) + sem) + (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-Prefixed dmode wstr op suffix + (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-Prefixed- dmode) (.sym Imm-40- smode)) + sem) + (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 24-8-Prefixed dmode wstr op suffix + (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-8-Prefixed- dmode) (.sym Imm-32- smode)) + sem) + (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) basic-Prefixed dmode wstr op suffix + (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-basic-Prefixed- dmode) (.sym Imm-24- smode)) + sem) + ) +) + +; All m32c variants +(define-pmacro (binary-arith32-imm-dst-defn smode dmode wstr wbit op suffix opc1 opc2 opc3 sem) + (begin + ; Multi insns are tried for assembly in the reverse order in which they appear here, so + ; define the absolute-indirect insns first in order to prevent them from being selected + ; when the mode is register-indirect +; (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-absolute-indirect dmode wstr op suffix +; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-absolute-indirect- dmode) (.sym Imm-48- smode)) +; sem) +; (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-absolute-indirect dmode wstr op suffix +; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-absolute-indirect- dmode) (.sym Imm-40- smode)) +; sem) + ; Unprefixed modes next + (binary-arith32-imm-dst-Unprefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem) + + ; Remaining indirect modes +; (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) basic-indirect dmode wstr op suffix +; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-basic-indirect- dmode) (.sym Imm-24- smode)) +; sem) +; (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-indirect dmode wstr op suffix +; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-indirect- dmode) (.sym Imm-48- smode)) +; sem) +; (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-indirect dmode wstr op suffix +; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-indirect- dmode) (.sym Imm-40- smode)) +; sem) +; (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 24-8-indirect dmode wstr op suffix +; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-8-indirect- dmode) (.sym Imm-32- smode)) +; sem) + ) +) + +(define-pmacro (binary-arith-imm-dst-mach mach op suffix opc1 opc2 opc3 sem) + (begin + (.apply (.sym binary-arith mach -imm-dst-defn) (QI QI .b 0 op suffix opc1 opc2 opc3 sem)) + (.apply (.sym binary-arith mach -imm-dst-defn) (HI HI .w 1 op suffix opc1 opc2 opc3 sem)) + ) +) + +(define-pmacro (binary-arith-imm-dst op suffix opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) + (begin + (binary-arith-imm-dst-mach 16 op suffix opc16-1 opc16-2 opc16-3 sem) + (binary-arith-imm-dst-mach 32 op suffix opc32-1 opc32-2 opc32-3 sem) + ) +) + +;------------------------------------------------------------- +;.size:Q #imm4,dst -- for m16c and m32c +;------------------------------------------------------------- + +(define-pmacro (binary-arith-imm4-dst-defn mach src dstgroup mode wstr op encoding sem) + (dni (.sym op mach wstr - imm4-Q - dstgroup) + (.str op wstr " " mach "-imm4-Q-" dstgroup "-" mode) + ((machine mach)) + (.str op wstr "$Q #${" src "},${dst" mach "-" dstgroup "-" mode "}") + encoding + (sem mode src (.sym dst mach - dstgroup - mode)) + ()) +) + +; m16c variants +(define-pmacro (binary-arith16-imm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem) + (binary-arith-imm4-dst-defn 16 Imm-8-s4 16 mode wstr op + (+ opc1 opc2 (f-7-1 wbit2) Imm-8-s4 (.sym dst16-16- mode)) + sem) +) + +(define-pmacro (binary-arith16-shimm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem) + (binary-arith-imm4-dst-defn 16 Imm-sh-8-s4 16 mode wstr op + (+ opc1 opc2 (f-7-1 wbit2) Imm-sh-8-s4 (.sym dst16-16- mode)) + sem) +) + +; m32c variants +(define-pmacro (binary-arith32-imm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem) + (begin + ; Multi insns are tried for assembly in the reverse order in which they appear here, so + ; define the absolute-indirect insns first in order to prevent them from being selected + ; when the mode is register-indirect +; (binary-arith-imm4-dst-defn 32 Imm-20-s4 24-absolute-indirect mode wstr op +; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) Imm-20-s4) +; sem) + (binary-arith-imm4-dst-defn 32 Imm-12-s4 16-Unprefixed mode wstr op + (+ (f-0-3 opc1) (f-3-1 wbit1) (f-7-1 wbit2) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4) + sem) +; (binary-arith-imm4-dst-defn 32 Imm-20-s4 24-indirect mode wstr op +; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-indirect- mode) (f-18-2 opc2) Imm-20-s4) +; sem) + ) +) + +(define-pmacro (binary-arith32-shimm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem) + (begin + ; Multi insns are tried for assembly in the reverse order in which they appear here, so + ; define the absolute-indirect insns first in order to prevent them from being selected + ; when the mode is register-indirect +; (binary-arith-imm4-dst-defn 32 Imm-sh-20-s4 24-absolute-indirect mode wstr op +; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) Imm-sh-20-s4) +; sem) + (binary-arith-imm4-dst-defn 32 Imm-sh-12-s4 16-Unprefixed mode wstr op + (+ (f-0-3 opc1) (f-3-1 wbit1) (f-7-1 wbit2) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) Imm-sh-12-s4) + sem) +; (binary-arith-imm4-dst-defn 32 Imm-sh-20-s4 24-indirect mode wstr op +; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-indirect- mode) (f-18-2 opc2) Imm-sh-20-s4) +; sem) + ) +) + +(define-pmacro (binary-arith-imm4-dst-mach mach op opc1 opc2 sem) + (begin + (.apply (.sym binary-arith mach -imm4-dst-defn) (QI .b 0 0 op opc1 opc2 sem)) + (.apply (.sym binary-arith mach -imm4-dst-defn) (HI .w 0 1 op opc1 opc2 sem)) + ) +) + +(define-pmacro (binary-arith-imm4-dst op opc16-1 opc16-2 opc32-1 opc32-2 sem) + (begin + (binary-arith-imm4-dst-mach 16 op opc16-1 opc16-2 sem) + (binary-arith-imm4-dst-mach 32 op opc32-1 opc32-2 sem) + ) +) + +;------------------------------------------------------------- +;.size:G src,dst -- for m16c and m32c +;------------------------------------------------------------- + +(define-pmacro (binary-arith-src-dst-defn mach srcgroup dstgroup smode dmode wstr op suffix encoding sem) + (dni (.sym op mach wstr - srcgroup - dstgroup) + (.str op wstr " dst" mach "-" srcgroup "-" dstgroup "-" dmode) + ((machine mach)) + (.str op wstr "$" suffix " ${src" mach "-" srcgroup "-" smode "},${dst" mach "-" dstgroup "-" dmode "}") + encoding + (sem dmode (.sym src mach - srcgroup - smode) (.sym dst mach - dstgroup - dmode)) + ()) +) + +; m16c variants +(define-pmacro (binary-arith16-src-dst-defn smode dmode wstr wbit op suffix opc1 opc2 sem) + (begin + (binary-arith-src-dst-defn 16 basic 16 smode dmode wstr op suffix + (+ opc1 opc2 (f-7-1 wbit) (.sym src16-basic- smode) (.sym dst16-16- dmode)) + sem) + (binary-arith-src-dst-defn 16 16-16 32 smode dmode wstr op suffix + (+ opc1 opc2 (f-7-1 wbit) (.sym src16-16-16- smode) (.sym dst16-32- dmode)) + sem) + (binary-arith-src-dst-defn 16 16-8 24 smode dmode wstr op suffix + (+ opc1 opc2 (f-7-1 wbit) (.sym src16-16-8- smode) (.sym dst16-24- dmode)) + sem) + ) +) + +; m32c Prefixed variants +(define-pmacro (binary-arith32-src-dst-Prefixed smode dmode wstr wbit op suffix opc1 opc2 sem) + (begin + (binary-arith-src-dst-defn 32 basic-Prefixed 24-Prefixed smode dmode wstr op suffix + (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-basic-Prefixed- smode) (.sym dst32-24-Prefixed- dmode) (f-20-4 opc2)) + sem) + (binary-arith-src-dst-defn 32 24-24-Prefixed 48-Prefixed smode dmode wstr op suffix + (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2)) + sem) + (binary-arith-src-dst-defn 32 24-16-Prefixed 40-Prefixed smode dmode wstr op suffix + (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2)) + sem) + (binary-arith-src-dst-defn 32 24-8-Prefixed 32-Prefixed smode dmode wstr op suffix + (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-Prefixed- dmode) (f-20-4 opc2)) + sem) + ) +) + +; all m32c variants +(define-pmacro (binary-arith32-src-dst-defn smode dmode wstr wbit op suffix opc1 opc2 sem) + (begin + ; Multi insns are tried for assembly in the reverse order in which they appear here, so + ; define the absolute-indirect insns first in order to prevent them from being selected + ; when the mode is register-indirect +; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-absolute-indirect smode dmode wstr op suffix +; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-absolute-indirect smode dmode wstr op suffix +; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-Prefixed smode dmode wstr op suffix +; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-Prefixed smode dmode wstr op suffix +; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-indirect smode dmode wstr op suffix +; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-indirect smode dmode wstr op suffix +; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 basic-Prefixed 24-absolute-indirect smode dmode wstr op suffix +; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-basic-Prefixed- smode) (.sym dst32-24-absolute-indirect- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 24-24-Prefixed 48-absolute-indirect smode dmode wstr op suffix +; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 24-16-Prefixed 40-absolute-indirect smode dmode wstr op suffix +; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 24-8-Prefixed 32-absolute-indirect smode dmode wstr op suffix +; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-absolute-indirect- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 basic-indirect 24-absolute-indirect smode dmode wstr op suffix +; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-basic-indirect- smode) (.sym dst32-24-absolute-indirect- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 24-24-indirect 48-absolute-indirect smode dmode wstr op suffix +; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-24-indirect- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 24-16-indirect 40-absolute-indirect smode dmode wstr op suffix +; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-16-indirect- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 24-8-indirect 32-absolute-indirect smode dmode wstr op suffix +; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-8-indirect- smode) (.sym dst32-32-absolute-indirect- dmode) (f-20-4 opc2)) +; sem) + (binary-arith-src-dst-defn 32 basic-Unprefixed 16-Unprefixed smode dmode wstr op suffix + (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-basic-Unprefixed- smode) (.sym dst32-16-Unprefixed- dmode) (f-12-4 opc2)) + sem) + (binary-arith-src-dst-defn 32 16-24-Unprefixed 40-Unprefixed smode dmode wstr op suffix + (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-24-Unprefixed- smode) (.sym dst32-40-Unprefixed- dmode) (f-12-4 opc2)) + sem) + (binary-arith-src-dst-defn 32 16-16-Unprefixed 32-Unprefixed smode dmode wstr op suffix + (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-16-Unprefixed- smode) (.sym dst32-32-Unprefixed- dmode) (f-12-4 opc2)) + sem) + (binary-arith-src-dst-defn 32 16-8-Unprefixed 24-Unprefixed smode dmode wstr op suffix + (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-8-Unprefixed- smode) (.sym dst32-24-Unprefixed- dmode) (f-12-4 opc2)) + sem) +; (binary-arith-src-dst-defn 32 basic-indirect 24-Prefixed smode dmode wstr op suffix +; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-basic-indirect- smode) (.sym dst32-24-Prefixed- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 24-24-indirect 48-Prefixed smode dmode wstr op suffix +; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-24-indirect- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 24-16-indirect 40-Prefixed smode dmode wstr op suffix +; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-16-indirect- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 24-8-indirect 32-Prefixed smode dmode wstr op suffix +; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-8-indirect- smode) (.sym dst32-32-Prefixed- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 basic-Prefixed 24-indirect smode dmode wstr op suffix +; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-basic-Prefixed- smode) (.sym dst32-24-indirect- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 24-24-Prefixed 48-indirect smode dmode wstr op suffix +; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 24-16-Prefixed 40-indirect smode dmode wstr op suffix +; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 24-8-Prefixed 32-indirect smode dmode wstr op suffix +; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-indirect- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 basic-indirect 24-indirect smode dmode wstr op suffix +; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-basic-indirect- smode) (.sym dst32-24-indirect- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 24-24-indirect 48-indirect smode dmode wstr op suffix +; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-24-indirect- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 24-16-indirect 40-indirect smode dmode wstr op suffix +; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-16-indirect- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2)) +; sem) +; (binary-arith-src-dst-defn 32 24-8-indirect 32-indirect smode dmode wstr op suffix +; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) +; (.sym src32-24-8-indirect- smode) (.sym dst32-32-indirect- dmode) (f-20-4 opc2)) +; sem) + ) +) + +(define-pmacro (binary-arith-src-dst-mach mach op suffix opc1 opc2 sem) + (begin + (.apply (.sym binary-arith mach -src-dst-defn) (QI QI .b 0 op suffix opc1 opc2 sem)) + (.apply (.sym binary-arith mach -src-dst-defn) (HI HI .w 1 op suffix opc1 opc2 sem)) + ) +) + +(define-pmacro (binary-arith-src-dst op suffix opc16-1 opc16-2 opc32-1 opc32-2 sem) + (begin + (binary-arith-src-dst-mach 16 op suffix opc16-1 opc16-2 sem) + (binary-arith-src-dst-mach 32 op suffix opc32-1 opc32-2 sem) + ) +) + +;------------------------------------------------------------- +;.size:S #imm,dst -- for m32c +;------------------------------------------------------------- + +(define-pmacro (binary-arith32-s-imm-dst-defn src dstgroup mode wstr op encoding sem) + (dni (.sym op 32 wstr - imm-S - dstgroup) + (.str op wstr " 32-imm-S-" dstgroup "-" mode) + ((machine 32)) + (.str op wstr "$S #${" src "},${dst32-" dstgroup "-" mode "}") + encoding + (sem mode src (.sym dst32- dstgroup - mode)) + ()) +) + +(define-pmacro (binary-arith32-z-imm-dst-defn src dstgroup mode wstr op encoding sem) + (dni (.sym op 32 wstr - imm-Z - dstgroup) + (.str op wstr " 32-imm-Z-" dstgroup "-" mode) + ((machine 32)) + (.str op wstr "$Z #0,${dst32-" dstgroup "-" mode "}") + encoding + (sem mode (const 0) (.sym dst32- dstgroup - mode)) + ()) +) + +(define-pmacro (binary-arith32-s-imm-dst mode wstr wbit op opc1 opc2 sem) + (begin +; (binary-arith32-s-imm-dst-defn (.sym Imm-32- mode) 2-S-absolute-indirect mode wstr op +; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-absolute-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-32- mode)) +; sem) + (binary-arith32-s-imm-dst-defn (.sym Imm-8- mode) 2-S-basic mode wstr op + (+ (f-0-2 opc1) (.sym dst32-2-S-basic- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-8- mode)) + sem) + (binary-arith32-s-imm-dst-defn (.sym Imm-24- mode) 2-S-16 mode wstr op + (+ (f-0-2 opc1) (.sym dst32-2-S-16- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-24- mode)) + sem) + (binary-arith32-s-imm-dst-defn (.sym Imm-16- mode) 2-S-8 mode wstr op + (+ (f-0-2 opc1) (.sym dst32-2-S-8- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-16- mode)) + sem) +; (binary-arith32-s-imm-dst-defn (.sym Imm-24- mode) 2-S-8-indirect mode wstr op +; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-8-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-24- mode)) +; sem) + ) +) + +(define-pmacro (binary-arith32-z-imm-dst mode wstr wbit op opc1 opc2 sem) + (begin +; (binary-arith32-z-imm-dst-defn (.sym Imm-32- mode) 2-S-absolute-indirect mode wstr op +; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-absolute-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-32- mode)) +; sem) + (binary-arith32-z-imm-dst-defn (.sym Imm-8- mode) 2-S-basic mode wstr op + (+ (f-0-2 opc1) (.sym dst32-2-S-basic- mode) (f-4-3 opc2) (f-7-1 wbit)) + sem) + (binary-arith32-z-imm-dst-defn (.sym Imm-24- mode) 2-S-16 mode wstr op + (+ (f-0-2 opc1) (.sym dst32-2-S-16- mode) (f-4-3 opc2) (f-7-1 wbit)) + sem) + (binary-arith32-z-imm-dst-defn (.sym Imm-16- mode) 2-S-8 mode wstr op + (+ (f-0-2 opc1) (.sym dst32-2-S-8- mode) (f-4-3 opc2) (f-7-1 wbit)) + sem) +; (binary-arith32-z-imm-dst-defn (.sym Imm-24- mode) 2-S-8-indirect mode wstr op +; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-8-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-24- mode)) +; sem) + ) +) + +;------------------------------------------------------------- +;.L:S #imm1,An -- for m32c +;------------------------------------------------------------- + +(define-pmacro (binary-arith32-l-s-imm1-an op opc1 opc2 sem) + (begin + (dni (.sym op 32.l-s-imm1-S-an) + (.str op ".l 32-imm1-S-an") + ((machine 32)) + (.str op ".l$S #${Imm1-S},${dst32-an-S}") + (+ opc1 Imm1-S opc2 dst32-an-S) + (sem SI Imm1-S dst32-an-S) + ()) + ) +) + +;------------------------------------------------------------- +;.L:Q #imm3,sp -- for m32c +;------------------------------------------------------------- + +(define-pmacro (binary-arith32-l-q-imm3-sp op opc1 opc2 sem) + (begin + (dni (.sym op 32.l-imm3-Q) + (.str op ".l 32-imm3-Q") + ((machine 32)) + (.str op ".l$Q #${Imm3-S},sp") + (+ opc1 Imm3-S opc2) + (sem SI Imm3-S sp) + ()) + ) +) + +;------------------------------------------------------------- +;.L:S #imm8,sp -- for m32c +;------------------------------------------------------------- + +(define-pmacro (binary-arith32-l-s-imm8-sp op opc1 opc2 opc3 opc4 sem) + (begin + (dni (.sym op 32.l-imm8-S) + (.str op ".l 32-imm8-S") + ((machine 32)) + (.str op ".l$S #${Imm-16-QI},sp") + (+ opc1 opc2 opc3 opc4 Imm-16-QI) + (sem SI Imm-16-QI sp) + ()) + ) +) + +;------------------------------------------------------------- +;.L:G #imm16,sp -- for m32c +;------------------------------------------------------------- + +(define-pmacro (binary-arith32-l-g-imm16-sp op opc1 opc2 opc3 opc4 sem) + (begin + (dni (.sym op 32.l-imm16-G) + (.str op ".l 32-imm16-G") + ((machine 32)) + (.str op ".l$G #${Imm-16-HI},sp") + (+ opc1 opc2 opc3 opc4 Imm-16-HI) + (sem SI Imm-16-HI sp) + ()) + ) +) + +;------------------------------------------------------------- +;jnz.size #imm4,dst,label -- for m16c and m32c +;------------------------------------------------------------- + +(define-pmacro (arith-jnz-imm4-dst-defn mach src dstgroup label mode wstr op encoding sem) + (dni (.sym op mach wstr - imm4 - dstgroup) + (.str op wstr " " mach "-imm4-" dstgroup "-" label "-" mode) + ((machine mach)) + (.str op wstr " #${" src "},${dst" mach "-" dstgroup "-" mode "},${" label "}") + encoding + (sem mode src (.sym dst mach - dstgroup - mode) label) + ()) +) + +; m16c variants +(define-pmacro (arith-jnz16-imm4-dst-defn mode wstr wbit op opc1 opc2 sem) + (begin + (arith-jnz-imm4-dst-defn 16 Imm-8-s4 basic Lab-16-8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) Imm-8-s4 (.sym dst16-basic- mode) Lab-16-8) + sem) + (arith-jnz-imm4-dst-defn 16 Imm-8-s4 16-16 Lab-32-8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) Imm-8-s4 (.sym dst16-16-16- mode) Lab-16-8) + sem) + (arith-jnz-imm4-dst-defn 16 Imm-8-s4 16-8 Lab-24-8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) Imm-8-s4 (.sym dst16-16-8- mode) Lab-16-8) + sem) + ) +) + +; m32c variants +(define-pmacro (arith-jnz32-imm4-dst-defn mode wstr wbit op opc1 opc2 sem) + (begin + (arith-jnz-imm4-dst-defn 32 Imm-12-s4 basic-Unprefixed Lab-16-8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4 Lab-16-8) + sem) + (arith-jnz-imm4-dst-defn 32 Imm-12-s4 16-24-Unprefixed Lab-40-8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4 Lab-40-8) + sem) + (arith-jnz-imm4-dst-defn 32 Imm-12-s4 16-16-Unprefixed Lab-32-8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4 Lab-32-8) + sem) + (arith-jnz-imm4-dst-defn 32 Imm-12-s4 16-8-Unprefixed Lab-24-8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4 Lab-24-8) + sem) + ) +) + +(define-pmacro (arith-jnz-imm4-dst-mach mach op opc1 opc2 sem) + (begin + (.apply (.sym arith-jnz mach -imm4-dst-defn) (QI .b 0 op opc1 opc2 sem)) + (.apply (.sym arith-jnz mach -imm4-dst-defn) (HI .w 1 op opc1 opc2 sem)) + ) +) + +(define-pmacro (arith-jnz-imm4-dst op opc16-1 opc16-2 opc32-1 opc32-2 sem) + (begin + (arith-jnz-imm4-dst-mach 16 op opc16-1 opc16-2 sem) + (arith-jnz-imm4-dst-mach 32 op opc32-1 opc32-2 sem) + ) +) + +;------------------------------------------------------------- +;mov.size dsp8[sp],dst -- for m16c and m32c +;------------------------------------------------------------- +(define-pmacro (mov-dspsp-dst-defn mach dstgroup dsp mode wstr op encoding sem) + (dni (.sym op mach wstr -dspsp-dst- dstgroup) + (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode) + ((machine mach)) + (.str op wstr " ${" dsp "}[sp],${dst" mach "-" dstgroup "-" mode "}") + encoding + (sem mach mode dsp (.sym dst mach - dstgroup - mode)) + ()) +) +(define-pmacro (mov-src-dspsp-defn mach dstgroup dsp mode wstr op encoding sem) + (dni (.sym op mach wstr -dst-dspsp- dstgroup) + (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode) + ((machine mach)) + (.str op wstr " ${dst" mach "-" dstgroup "-" mode "},${" dsp "}[sp]") + encoding + (sem mach mode (.sym dst mach - dstgroup - mode) dsp) + ()) +) + +; m16c variants +(define-pmacro (mov16-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem) + (begin + (mov-dspsp-dst-defn 16 basic Dsp-16-u8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-u8) + sem) + (mov-dspsp-dst-defn 16 16-16 Dsp-32-u8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-u8) + sem) + (mov-dspsp-dst-defn 16 16-8 Dsp-24-u8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-u8) + sem) + ) +) + +(define-pmacro (mov16-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem) + (begin + (mov-src-dspsp-defn 16 basic Dsp-16-u8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-u8) + sem) + (mov-src-dspsp-defn 16 16-16 Dsp-32-u8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-u8) + sem) + (mov-src-dspsp-defn 16 16-8 Dsp-24-u8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-u8) + sem) + ) +) + +; m32c variants +(define-pmacro (mov32-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem) + (begin + (mov-dspsp-dst-defn 32 basic-Unprefixed Dsp-16-u8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-u8) + sem) + (mov-dspsp-dst-defn 32 16-24-Unprefixed Dsp-40-u8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-u8) + sem) + (mov-dspsp-dst-defn 32 16-16-Unprefixed Dsp-32-u8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-u8) + sem) + (mov-dspsp-dst-defn 32 16-8-Unprefixed Dsp-24-u8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-u8) + sem) + ) +) +(define-pmacro (mov32-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem) + (begin + (mov-src-dspsp-defn 32 basic-Unprefixed Dsp-16-u8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-u8) + sem) + (mov-src-dspsp-defn 32 16-24-Unprefixed Dsp-40-u8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-u8) + sem) + (mov-src-dspsp-defn 32 16-16-Unprefixed Dsp-32-u8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-u8) + sem) + (mov-src-dspsp-defn 32 16-8-Unprefixed Dsp-24-u8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-u8) + sem) + ) +) + +(define-pmacro (mov-src-dspsp-mach mach op opc1 opc2 opc3 sem) + (begin + (.apply (.sym mov mach -src-dspsp-defn) (QI .b 0 op opc1 opc2 opc3 sem)) + (.apply (.sym mov mach -src-dspsp-defn) (HI .w 1 op opc1 opc2 opc3 sem)) + ) +) + +(define-pmacro (mov-dspsp-dst-mach mach op opc1 opc2 opc3 sem) + (begin + (.apply (.sym mov mach -dspsp-dst-defn) (QI .b 0 op opc1 opc2 opc3 sem)) + (.apply (.sym mov mach -dspsp-dst-defn) (HI .w 1 op opc1 opc2 opc3 sem)) + ) +) + +(define-pmacro (mov-dspsp-dst op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) + (begin + (mov-dspsp-dst-mach 16 op opc16-1 opc16-2 opc16-3 sem) + (mov-dspsp-dst-mach 32 op opc32-1 opc32-2 opc32-3 sem) + ) +) +(define-pmacro (mov-src-dspsp op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) + (begin + (mov-src-dspsp-mach 16 op opc16-1 opc16-2 opc16-3 sem) + (mov-src-dspsp-mach 32 op opc32-1 opc32-2 opc32-3 sem) + ) +) + +;------------------------------------------------------------- +; lde dsp24,dst -- for m16c +; TODO abs20[a0], [a0a1] for dsp24 +;------------------------------------------------------------- + +(define-pmacro (lde-defn mach dstgroup dsp mode wstr op encoding sem) + (dni (.sym op mach wstr -dst-dspsp- dstgroup) + (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode) + ((machine mach)) + (.str op wstr " ${" dsp "},${dst" mach "-" dstgroup "-" mode "}") + encoding + (sem mode (.sym dst mach - dstgroup - mode) dsp) + ()) +) + +(define-pmacro (lde-dst mode wstr wbit op opc1 opc2 opc3 sem) + (begin + (lde-defn 16 basic Dsp-16-u20 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-u20) + sem) + (lde-defn 16 16-16 Dsp-32-u20 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-u20) + sem) + (lde-defn 16 16-8 Dsp-24-u20 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-u20) + sem) + ) +) + +;------------------------------------------------------------- +; ste src,dsp24 -- for m16c +; TODO abs20[a0], [a0a1] for dsp24 +;------------------------------------------------------------- + +(define-pmacro (ste-defn mach dstgroup dsp mode wstr op encoding sem) + (dni (.sym op mach wstr -dst-dspsp- dstgroup) + (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode) + ((machine mach)) + (.str op wstr " ${dst" mach "-" dstgroup "-" mode "},${" dsp "}") + encoding + (sem mode (.sym dst mach - dstgroup - mode) dsp) + ()) +) + +(define-pmacro (ste-dst mode wstr wbit op opc1 opc2 opc3 sem) + (begin + (ste-defn 16 basic Dsp-16-u20 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-u20) + sem) + (ste-defn 16 16-16 Dsp-32-u20 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-u20) + sem) + (ste-defn 16 16-8 Dsp-24-u20 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-u20) + sem) + ) +) + +;============================================================= +; Division +;------------------------------------------------------------- + +(define-pmacro (div-sem divop modop opmode reg src quot rem max min) + (sequence () + (if (eq src 0) + (set obit (const BI 1)) + (sequence ((opmode quot-result) (opmode rem-result)) + (set quot-result (divop opmode (ext opmode reg) src)) + (set rem-result (modop opmode (ext opmode reg) src)) + (set obit (orif (gt opmode quot-result max) + (lt opmode quot-result min))) + (set quot quot-result) + (set rem rem-result)))) +) + +;.size #imm -- for m16c and m32c +(define-pmacro (div-imm-defn mach wstr op src encoding divop modop opmode reg quot rem max min sem) + (dni (.sym op mach wstr - src) + (.str op mach wstr "-" src) + ((machine mach)) + (.str op wstr " #${" src "}") + encoding + (sem divop modop opmode reg src quot rem max min) + ()) +) +(define-pmacro (div16-imm-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 opc4 sem) + (div-imm-defn 16 wstr op (.sym Imm-16 - smode) + (+ opc1 opc2 (f-7-1 wbit) opc3 opc4 (.sym Imm-16 - smode)) + divop modop opmode reg quot rem max min + sem) +) +(define-pmacro (div32-imm-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 opc4 sem) + (div-imm-defn 32 wstr op (.sym Imm-16 - smode) + (+ (f-0-4 opc1) (f-4-4 opc2) (f-8-3 opc3) (f-11-1 wbit) (f-12-4 opc4) (.sym Imm-16 - smode)) + divop modop opmode reg quot rem max min + sem) +) +(define-pmacro (div-imm-mach mach op divop modop opmode max-QI min-QI max-HI min-HI opc1 opc2 opc3 opc4 sem) + (begin + (.apply (.sym div mach -imm-defn) (QI .b 0 op divop modop opmode R0 R0l R0h max-QI min-QI opc1 opc2 opc3 opc4 sem)) + (.apply (.sym div mach -imm-defn) (HI .w 1 op divop modop opmode R2R0 R0 R2 max-HI min-HI opc1 opc2 opc3 opc4 sem)) + ) +) +(define-pmacro (div-imm op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc16-4 opc32-1 opc32-2 opc32-3 opc32-4 sem) + (begin + (div-imm-mach 16 op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc16-4 sem) + (div-imm-mach 32 op divop modop opmode max-QI min-QI max-HI min-HI opc32-1 opc32-2 opc32-3 opc32-4 sem) + ) +) + +;.size src -- for m16c and m32c +(define-pmacro (div-src-defn mach wstr op src encoding divop modop opmode reg quot rem max min sem) + (dni (.sym op mach wstr - src) + (.str op mach wstr "-" src) + ((machine mach)) + (.str op wstr " ${" src "}") + encoding + (sem divop modop opmode reg src quot rem max min) + ()) +) +(define-pmacro (div16-src-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 sem) + (div-src-defn 16 wstr op (.sym dst16-16 - smode) + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16 - smode)) + divop modop opmode reg quot rem max min + sem) +) +(define-pmacro (div32-src-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 sem) + (begin + ; Multi insns are tried for assembly in the reverse order in which they appear here, so + ; define the absolute-indirect insns first in order to prevent them from being selected + ; when the mode is register-indirect +; (div-src-defn 32 wstr op (.sym dst32-24-absolute-indirect- smode) +; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (f-18-2 opc2) (f-20-4 opc3) (.sym dst32-24-absolute-indirect - smode)) +; divop modop opmode reg quot rem max min +; sem) + (div-src-defn 32 wstr op (.sym dst32-16-Unprefixed- smode) + (+ (f-0-4 opc1) (f-7-1 wbit) (f-10-2 opc2) (f-12-4 opc3) (.sym dst32-16-Unprefixed- smode)) + divop modop opmode reg quot rem max min + sem) +; (div-src-defn 32 wstr op (.sym dst32-24-indirect- smode) +; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (f-18-2 opc2) (f-20-4 opc3) (.sym dst32-24-indirect - smode)) +; divop modop opmode reg quot rem max min +; sem) + ) +) +(define-pmacro (div-src-mach mach op divop modop opmode max-QI min-QI max-HI min-HI opc1 opc2 opc3 sem) + (begin + (.apply (.sym div mach -src-defn) (QI .b 0 op divop modop opmode R0 R0l R0h max-QI min-QI opc1 opc2 opc3 sem)) + (.apply (.sym div mach -src-defn) (HI .w 1 op divop modop opmode R2R0 R0 R2 max-HI min-HI opc1 opc2 opc3 sem)) + ) +) +(define-pmacro (div-src op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) + (begin + (div-src-mach 16 op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 sem) + (div-src-mach 32 op divop modop opmode max-QI min-QI max-HI min-HI opc32-1 opc32-2 opc32-3 sem) + ) +) + +;============================================================= +; Bit manipulation +; +(define-pmacro (bit-insn-defn mach op suffix opnd encoding sem) + (dni (.sym op mach - suffix - opnd) + (.str op mach ":" suffix " " opnd) + ((machine mach)) + (.str op "$" suffix " ${" opnd "}") + encoding + (sem opnd) + ()) +) + +(define-pmacro (bitsrc16-defn op opc1 opc2 opc3 sem) + (bit-insn-defn 16 op X bit16-16 + (+ opc1 opc2 opc3 bit16-16) + sem) +) + +(define-pmacro (bitsrc32-defn op opc1 opc2 opc3 sem) + (begin + (bit-insn-defn 32 op X bit32-24-Prefixed + (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) bit32-24-Prefixed (f-15-1 opc2) (f-18-3 opc3)) + sem) + ) +) + +(define-pmacro (bitsrc-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) + (begin + (bitsrc16-defn op opc16-1 opc16-2 opc16-3 sem) + (bitsrc32-defn op opc32-1 opc32-2 opc32-3 sem) + ) +) + +(define-pmacro (bitdst16-defn op opc1 opc2 opc3 opc4 opc5 opc6 sem) + (begin + (bit-insn-defn 16 op G bit16-16-basic (+ opc1 opc2 opc3 bit16-16-basic) sem) + (bit-insn-defn 16 op G bit16-16-16 (+ opc1 opc2 opc3 bit16-16-16) sem) + (bit-insn-defn 16 op S bit16-11-S (+ opc4 opc5 opc6 bit16-11-S) sem) + (bit-insn-defn 16 op G bit16-16-8 (+ opc1 opc2 opc3 bit16-16-8) sem) + ) +) + +(define-pmacro (bitdst32-defn op opc1 opc2 opc3 sem) + (begin + (bit-insn-defn 32 op X bit32-16-Unprefixed + (+ (f-0-4 opc1) bit32-16-Unprefixed (f-7-1 opc2) (f-10-3 opc3)) + sem) + ) +) + +(define-pmacro (bitdstnos-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) + (begin + (bitsrc16-defn op opc16-1 opc16-2 opc16-3 sem) + (bitdst32-defn op opc32-1 opc32-2 opc32-3 sem) + ) +) + +(define-pmacro (bitdst-insn op opc16-1 opc16-2 opc16-3 opc16-4 opc16-5 opc16-6 opc32-1 opc32-2 opc32-3 sem) + (begin + (bitdst16-defn op opc16-1 opc16-2 opc16-3 opc16-4 opc16-5 opc16-6 sem) + (bitdst32-defn op opc32-1 opc32-2 opc32-3 sem) + ) +) + +;============================================================= +; Bit condition +; +(define-pmacro (bitcond-insn-defn mach op bit-opnd cond-opnd encoding sem) + (dni (.sym op mach - bit-opnd - cond-opnd) + (.str op mach " " bit-opnd " " cond-opnd) + ((machine mach)) + (.str op "${" cond-opnd "} ${" bit-opnd "}") + encoding + (sem mach bit-opnd cond-opnd) + ()) +) + +(define-pmacro (bitcond16-defn op opc1 opc2 opc3 sem) + (begin + (bitcond-insn-defn 16 op bit16-16-basic cond16-16 (+ opc1 opc2 opc3 bit16-16-basic cond16-16) sem) + (bitcond-insn-defn 16 op bit16-16-16 cond16-32 (+ opc1 opc2 opc3 bit16-16-16 cond16-32) sem) + (bitcond-insn-defn 16 op bit16-16-8 cond16-24 (+ opc1 opc2 opc3 bit16-16-8 cond16-24) sem) + ) +) + +(define-pmacro (bitcond32-defn op opc1 opc2 opc3 sem) + (begin + (bitcond-insn-defn 32 op bit32-16-24-Unprefixed cond32-40 + (+ (f-0-4 opc1) bit32-16-24-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-40) + sem) + (bitcond-insn-defn 32 op bit32-16-16-Unprefixed cond32-32 + (+ (f-0-4 opc1) bit32-16-16-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-32) + sem) + (bitcond-insn-defn 32 op bit32-16-8-Unprefixed cond32-24 + (+ (f-0-4 opc1) bit32-16-8-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-24) + sem) + (bitcond-insn-defn 32 op bit32-basic-Unprefixed cond32-16 + (+ (f-0-4 opc1) bit32-basic-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-16) + sem) + ) +) + +(define-pmacro (bitcond-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) + (begin + (bitcond16-defn op opc16-1 opc16-2 opc16-3 sem) + (bitcond32-defn op opc32-1 opc32-2 opc32-3 sem) + ) +) + +;============================================================= +;.size #imm1,#imm2,dst -- for m32c +; +(define-pmacro (insn-imm1-imm2-dst-defn src1 src2 dstgroup xmode wstr op encoding sem) + (dni (.sym op 32 wstr - src1 - src2 - dstgroup) + (.str op 32 wstr "-" src1 "-" src2 "-" dstgroup "-" xmode) + ((machine 32)) + (.str op wstr " #${" src1 "},#${" src2 "},${dst32-" dstgroup "-" xmode "}") + encoding + (sem xmode src1 src2 (.sym dst32- dstgroup - xmode)) + ()) +) + +; m32c Prefixed variants +(define-pmacro (insn32-imm1-imm2-dst-Prefixed-defn xmode wstr wbit base1 base2 base3 base4 op opc1 opc2 opc3 sem) + (begin + (insn-imm1-imm2-dst-defn (.sym Imm-48- xmode) (.sym Imm- base4 - xmode) 24-24-Prefixed xmode wstr op + (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) + (.sym dst32-24-24-Prefixed- xmode) (.sym Imm-48- xmode) (.sym Imm- base4 - xmode)) + sem) + (insn-imm1-imm2-dst-defn (.sym Imm-40- xmode) (.sym Imm- base3 - xmode) 24-16-Prefixed xmode wstr op + (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) + (.sym dst32-24-16-Prefixed- xmode) (.sym Imm-40- xmode) (.sym Imm- base3 - xmode)) + sem) + (insn-imm1-imm2-dst-defn (.sym Imm-32- xmode) (.sym Imm- base2 - xmode) 24-8-Prefixed xmode wstr op + (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) + (.sym dst32-24-8-Prefixed- xmode) (.sym Imm-32- xmode) (.sym Imm- base2 - xmode)) + sem) + (insn-imm1-imm2-dst-defn (.sym Imm-24- xmode) (.sym Imm- base1 - xmode) basic-Prefixed xmode wstr op + (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) + (.sym dst32-basic-Prefixed- xmode) (.sym Imm-24- xmode) (.sym Imm- base1 - xmode)) + sem) + ) +) + +; m32c Unprefixed variants +(define-pmacro (insn32-imm1-imm2-dst-Unprefixed-defn xmode wstr wbit base1 base2 base3 base4 op opc1 opc2 opc3 sem) + (begin + (insn-imm1-imm2-dst-defn (.sym Imm-40- xmode) (.sym Imm- base4 - xmode) 16-24-Unprefixed xmode wstr op + (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) + (.sym dst32-16-24-Unprefixed- xmode) (.sym Imm-40- xmode) (.sym Imm- base4 - xmode)) + sem) + (insn-imm1-imm2-dst-defn (.sym Imm-32- xmode) (.sym Imm- base3 - xmode) 16-16-Unprefixed xmode wstr op + (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) + (.sym dst32-16-16-Unprefixed- xmode) (.sym Imm-32- xmode) (.sym Imm- base3 - xmode)) + sem) + (insn-imm1-imm2-dst-defn (.sym Imm-24- xmode) (.sym Imm- base2 - xmode) 16-8-Unprefixed xmode wstr op + (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) + (.sym dst32-16-8-Unprefixed- xmode) (.sym Imm-24- xmode) (.sym Imm- base2 - xmode)) + sem) + (insn-imm1-imm2-dst-defn (.sym Imm-16- xmode) (.sym Imm- base1 - xmode) basic-Unprefixed xmode wstr op + (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) + (.sym dst32-basic-Unprefixed- xmode) (.sym Imm-16- xmode) (.sym Imm- base1 - xmode)) + sem) + ) +) + +(define-pmacro (insn-imm1-imm2-dst-Prefixed op opc32-1 opc32-2 opc32-3 sem) + (begin + (insn32-imm1-imm2-dst-Prefixed-defn QI .b 0 32 40 48 56 op opc32-1 opc32-2 opc32-3 sem) + (insn32-imm1-imm2-dst-Prefixed-defn HI .w 1 40 48 56 64 op opc32-1 opc32-2 opc32-3 sem) + ) +) +(define-pmacro (insn-imm1-imm2-dst-Unprefixed op opc32-1 opc32-2 opc32-3 sem) + (begin + (insn32-imm1-imm2-dst-Unprefixed-defn QI .b 0 24 32 40 48 op opc32-1 opc32-2 opc32-3 sem) + (insn32-imm1-imm2-dst-Unprefixed-defn HI .w 1 32 40 48 56 op opc32-1 opc32-2 opc32-3 sem) + ) +) + +;============================================================= +; Insn definitions +;------------------------------------------------------------- +; abs - absolute +;------------------------------------------------------------- + +(define-pmacro (abs-sem mode dst) + (sequence ((mode result)) + (set result (abs mode dst)) + (set obit (eq result dst)) + (set-z-and-s result) + (set dst result)) +) +(unary-insn abs (f-0-4 7) (f-4-3 3) (f-8-4 #xF) #xA #x1 #xF abs-sem) + +;------------------------------------------------------------- +; adcf - addition carry flag +;------------------------------------------------------------- + +(define-pmacro (adcf-sem mode dst) + (sequence ((mode result)) + (set result (addc mode dst 0 cbit)) + (set obit (add-oflag mode dst 0 cbit)) + (set cbit (add-cflag mode dst 0 cbit)) + (set-z-and-s result) + (set dst result)) +) +(unary-insn adcf (f-0-4 7) (f-4-3 3) (f-8-4 #xE) #xB #x1 #xE adcf-sem) + +;------------------------------------------------------------- +; add - binary addition +;------------------------------------------------------------- + +(define-pmacro (add-sem mode src1 dst) + (sequence ((mode result)) + (set result (add mode src1 dst)) + (set obit (add-oflag mode src1 dst 0)) + (set cbit (add-cflag mode src1 dst 0)) + (set-z-and-s result) + (set dst result)) +) + +; add.L:G #imm32,dst (m32 #2) +(binary-arith32-imm-dst-defn SI SI .l 0 add G #x8 #x3 #x1 add-sem) +; add.size:G #imm,dst (m16 #1 m32 #1) +(binary-arith-imm-dst add G (f-0-4 7) (f-4-3 3) (f-8-4 4) #x8 #x2 #xE add-sem) +; add.size:Q #imm4,dst (m16 #2 m32 #3) +(binary-arith-imm4-dst add (f-0-4 #xC) (f-4-3 4) #x7 #x3 add-sem) +(binary-arith32-imm4-dst-defn SI .l 1 0 add #x7 #x3 add-sem) +; add.b:S #imm8,dst3 (m16 #3) +(binary-arith16-b-S-imm8-dst3 add ".b" (f-0-4 8) (f-4-1 0) add-sem) +; add.BW:Q #imm4,sp (m16 #7) +(binary-arith16-Q-sp add (f-0-4 7) (f-4-4 #xD) (f-8-4 #xB) add-sem) +; add.BW:G #imm,sp (m16 #6) +(binary-arith16-G-sp add (f-0-4 7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #xB) add-sem) +; add.BW:G src,dst (m16 #4 m32 #6) +(binary-arith-src-dst add G (f-0-4 #xA) (f-4-3 0) #x1 #x8 add-sem) +; add.B.S src2,r0l/r0h (m16 #5) +(binary-arith16-b-S-src2 add (f-0-4 2) (f-4-1 0) add-sem) +; add.L:G src,dst (m32 #7) +(binary-arith32-src-dst-defn SI SI .l 1 add G #x1 #x2 add-sem) +; add.L:S #imm{1,2},A0/A1 (m32 #5) +(binary-arith32-l-s-imm1-an add (f-0-2 2) (f-3-4 6) add-sem) +; add.L:Q #imm3,sp (m32 #9) +(binary-arith32-l-q-imm3-sp add (f-0-2 1) (f-4-3 1) add-sem) +; add.L:S #imm8,sp (m32 #10) +(binary-arith32-l-s-imm8-sp add (f-0-4 #xb) (f-4-4 6) (f-8-4 0) (f-12-4 3) add-sem) +; add.L:G #imm16,sp (m32 #8) +(binary-arith32-l-g-imm16-sp add (f-0-4 #xb) (f-4-4 6) (f-8-4 1) (f-12-4 3) add-sem) +; add.BW:S #imm,dst2 (m32 #4) +(binary-arith32-s-imm-dst QI .b 0 add #x0 #x3 add-sem) +(binary-arith32-s-imm-dst HI .w 1 add #x0 #x3 add-sem) + +;------------------------------------------------------------- +; adc - binary add with carry +;------------------------------------------------------------- + +(define-pmacro (addc-sem mode src dst) + (sequence ((mode result)) + (set result (addc mode src dst cbit)) + (set obit (add-oflag mode src dst cbit)) + (set cbit (add-cflag mode src dst cbit)) + (set-z-and-s result) + (set dst result)) +) + +; adc.size:G #imm,dst +(binary-arith16-imm-dst-defn QI QI .b 0 adc X (f-0-4 7) (f-4-3 3) (f-8-4 6) addc-sem) +(binary-arith16-imm-dst-defn HI HI .w 1 adc X (f-0-4 7) (f-4-3 3) (f-8-4 6) addc-sem) +(binary-arith32-imm-dst-Prefixed QI QI .b 0 adc X #x8 #x2 #xE addc-sem) +(binary-arith32-imm-dst-Prefixed HI HI .w 1 adc X #x8 #x2 #xE addc-sem) + +; adc.BW:G src,dst +(binary-arith16-src-dst-defn QI QI .b 0 adc X (f-0-4 #xB) (f-4-3 0) addc-sem) +(binary-arith16-src-dst-defn HI HI .w 1 adc X (f-0-4 #xB) (f-4-3 0) addc-sem) +(binary-arith32-src-dst-Prefixed QI QI .b 0 adc X #x1 #x4 addc-sem) +(binary-arith32-src-dst-Prefixed HI HI .w 1 adc X #x1 #x4 addc-sem) + +;------------------------------------------------------------- +; dadc - decimal add with carry +; dadd - decimal addition +;------------------------------------------------------------- + +(define-pmacro (dadc-sem mode src dst) + (sequence ((mode result)) + (set result (subc mode dst src (not cbit))) + (set cbit (sub-cflag mode dst src (not cbit))) + (set-z-and-s result) + (set dst result)) +) + +(define-pmacro (decimal-subtraction16-insn op opc1 opc2) + (begin + ; op.b #imm8,r0l + (dni (.sym op 16.b-imm8) + (.str op ".b #imm8") + ((machine 16)) + (.str op ".b #${Imm-16-QI}") + (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 opc1) Imm-16-QI) + ((.sym op -sem) QI Imm-16-QI R0l) + ()) + ; op.w #imm16,r0 + (dni (.sym op 16.w-imm16) + (.str op ".b #imm16") + ((machine 16)) + (.str op ".w #${Imm-16-HI}") + (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 opc1) Imm-16-HI) + ((.sym op -sem) HI Imm-16-HI R0) + ()) + ; op.b #r0h,r0l + (dni (.sym op 16.b-r0h-r0l) + (.str op ".b r0h,r0l") + ((machine 16)) + (.str op ".b r0h,r0l") + (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 opc2)) + ((.sym op -sem) QI R0h R0l) + ()) + ; op.w #r1,r0 + (dni (.sym op 16.w-r1-r0) + (.str op ".b r1,r0") + ((machine 16)) + (.str op ".w r1,r0") + (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 opc2)) + ((.sym op -sem) HI R1 R0) + ()) + ) +) + +; dadc for m16c +(decimal-subtraction16-insn dadc #xE #x6 ) + +; dadc.size #imm,dst +(binary-arith32-imm-dst-Prefixed QI QI .b 0 dadc X #x8 #x0 #xE dadc-sem) +(binary-arith32-imm-dst-Prefixed HI HI .w 1 dadc X #x8 #x0 #xE dadc-sem) +; dadc.BW src,dst +(binary-arith32-src-dst-Prefixed QI QI .b 0 dadc X #x1 #x8 dadc-sem) +(binary-arith32-src-dst-Prefixed HI HI .w 1 dadc X #x1 #x8 dadc-sem) + +(define-pmacro (dadd-sem mode src dst) + (sequence ((mode result)) + (set result (subc mode dst src 0)) + (set cbit (sub-cflag mode dst src 0)) + (set-z-and-s result) + (set dst result)) +) + +; dadd for m16c +(decimal-subtraction16-insn dadd #xC #x4) + +; dadd.size #imm,dst +(binary-arith32-imm-dst-Prefixed QI QI .b 0 dadd X #x8 #x1 #xE dadd-sem) +(binary-arith32-imm-dst-Prefixed HI HI .w 1 dadd X #x8 #x1 #xE dadd-sem) +; dadd.BW src,dst +(binary-arith32-src-dst-Prefixed QI QI .b 0 dadd X #x1 #x0 dadd-sem) +(binary-arith32-src-dst-Prefixed HI HI .w 1 dadd X #x1 #x0 dadd-sem) + +;-------------------------------------------------------------; +; addx - Add extend sign with no carry +;-------------------------------------------------------------; + +(define-pmacro (addx-sem mode src dst) + (sequence ((SI source) (SI result)) + (set source (zext SI (trunc QI src))) + (set result (add SI source dst)) + (set obit (add-oflag SI source dst 0)) + (set cbit (add-cflag SI source dst 0)) + (set-z-and-s result) + (set dst result)) +) + +; addx #imm,dst +(binary-arith32-imm-dst-defn QI SI "" 0 addx X #x8 #x1 #x1 addx-sem) +; addx src,dst +(binary-arith32-src-dst-defn QI SI "" 0 addx X #x1 #x2 addx-sem) + +;------------------------------------------------------------- +; adjnz - Add/Sub and branch if not zero +;------------------------------------------------------------- + +(define-pmacro (arith-jnz-sem mode src dst label) + (sequence ((mode result)) + (set result (add mode src dst)) + (set dst result) + (if (ne result 0) + (set pc label))) +) + +; adjnz.size #imm4,dst,label +(arith-jnz-imm4-dst adjnz (f-0-4 #xF) (f-4-3 4) #xf #x1 arith-jnz-sem) + +;------------------------------------------------------------- +; and - binary and +;------------------------------------------------------------- + +(define-pmacro (and-sem mode src1 dst) + (sequence ((mode result)) + (set result (and mode src1 dst)) + (set-z-and-s result) + (set dst result)) +) + +; and.size:G #imm,dst (m16 #1 m32 #1) +(binary-arith-imm-dst and G (f-0-4 7) (f-4-3 3) (f-8-4 2) #x8 #x3 #xF and-sem) +; and.b:S #imm8,dst3 (m16 #2) +(binary-arith16-b-S-imm8-dst3 and ".b" (f-0-4 9) (f-4-1 0) and-sem) +; and.BW:G src,dst (m16 #3 m32 #3) +(binary-arith-src-dst and G (f-0-4 #x9) (f-4-3 0) #x1 #xD and-sem) +; and.B.S src2,r0l/r0h (m16 #4) +(binary-arith16-b-S-src2 and (f-0-4 1) (f-4-1 0) and-sem) +; and.BW:S #imm,dst2 (m32 #2) +(binary-arith32-s-imm-dst QI .b 0 and #x1 #x6 and-sem) +(binary-arith32-s-imm-dst HI .w 1 and #x1 #x6 and-sem) + +;------------------------------------------------------------- +; band - bit and +;------------------------------------------------------------- + +(define-pmacro (band-sem src) + (set cbit (and src cbit)) +) +(bitsrc-insn band (f-0-4 7) (f-4-4 #xE) (f-8-4 4) #xD #x0 #x1 band-sem) + +;------------------------------------------------------------- +; bclr - bit clear +;------------------------------------------------------------- + +(define-pmacro (bclr-sem dst) + (set dst 0) +) +(bitdst-insn bclr (f-0-4 7) (f-4-4 #xE) (f-8-4 8) (f-0-2 1) (f-2-2 0) (f-4-1 0) #xD #x0 #x6 bclr-sem) + +;------------------------------------------------------------- +; bitindex - bit index +;------------------------------------------------------------- + +(define-pmacro (bitindex-sem mode dst) + (set BitIndex dst) +) +(unary-insn-defn 32 16-Unprefixed QI .b bitindex + (+ (f-0-4 #xC) (f-7-1 0) dst32-16-Unprefixed-QI (f-10-2 #x2) (f-12-4 #xE)) + bitindex-sem) +(unary-insn-defn 32 16-Unprefixed HI .w bitindex + (+ (f-0-4 #xC) (f-7-1 1) dst32-16-Unprefixed-HI (f-10-2 #x2) (f-12-4 #xE)) + bitindex-sem) + +;------------------------------------------------------------- +; bmCnd - bit move condition +;------------------------------------------------------------- + +(define-pmacro (test-condition16 cond) + (case UQI cond + ((#x00) (trunc BI cbit)) + ((#x01) (not (or cbit zbit))) + ((#x02) (trunc BI zbit)) + ((#x03) (trunc BI sbit)) + ((#x04) (or zbit (xor sbit obit))) + ((#x05) (trunc BI obit)) + ((#x06) (xor sbit obit)) + ((#xf8) (not cbit)) + ((#xf9) (or cbit zbit)) + ((#xfa) (not zbit)) + ((#xfb) (not sbit)) + ((#xfc) (not (or zbit (xor sbit obit)))) + ((#xfd) (not obit)) + ((#xfe) (not (xor sbit obit))) + (else (const BI 0)) + ) +) + +(define-pmacro (test-condition32 cond) + (case UQI cond + ((#x00) (not cbit)) + ((#x01) (or cbit zbit)) + ((#x02) (not zbit)) + ((#x03) (not sbit)) + ((#x04) (not obit)) + ((#x05) (not (or zbit (xor sbit obit)))) + ((#x06) (not (xor sbit obit))) + ((#x08) (trunc BI cbit)) + ((#x09) (not (or cbit zbit))) + ((#x0a) (trunc BI zbit)) + ((#x0b) (trunc BI sbit)) + ((#x0c) (trunc BI obit)) + ((#x0d) (or zbit (xor sbit obit))) + ((#x0e) (xor sbit obit)) + (else (const BI 0)) + ) +) + +(define-pmacro (bitcond-sem mach op cond) + (if ((.sym test-condition mach) cond) + (set op 1) + (set op 0)) +) +(bitcond-insn bm (f-0-4 7) (f-4-4 #xE) (f-8-4 2) #xD #x0 #x2 bitcond-sem) + +(dni bm16-c + "bm16 C" + ((machine 16)) + "bm$cond16c c" + (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xD) cond16c) + (bitcond-sem 16 cbit cond16c) + ()) + +(dni bm32-c + "bm32 C" + ((machine 32)) + "bm$cond32 c" + (+ (f-0-4 #xD) (f-4-4 #x9) (f-8-1 0) (f-10-3 5) cond32) + (bitcond-sem 32 cbit cond32) + ()) + +;------------------------------------------------------------- +; bnand +;------------------------------------------------------------- + +(define-pmacro (bnand-sem src) + (set cbit (and (inv src) cbit)) +) +(bitsrc-insn bnand (f-0-4 7) (f-4-4 #xE) (f-8-4 5) #xD #x0 #x3 bnand-sem) + +;------------------------------------------------------------- +; bnor +;------------------------------------------------------------- + +(define-pmacro (bnor-sem src) + (set cbit (or (inv src) cbit)) +) +(bitsrc-insn bnor (f-0-4 7) (f-4-4 #xE) (f-8-4 7) #xD #x0 #x6 bnor-sem) + +;------------------------------------------------------------- +; bnot +;------------------------------------------------------------- + +(define-pmacro (bnot-sem dst) + (set dst (inv dst)) +) +(bitdst-insn bnot (f-0-4 7) (f-4-4 #xE) (f-8-4 #xA) (f-0-2 1) (f-2-2 1) (f-4-1 0) #xD #x0 #x3 bnot-sem) + +;------------------------------------------------------------- +; bntst +;------------------------------------------------------------- + +(define-pmacro (bntst-sem src) + (set cbit (inv src)) + (set zbit (inv src)) +) +(bitsrc-insn bntst (f-0-4 7) (f-4-4 #xE) (f-8-4 3) #xD #x0 #x0 bntst-sem) + +;------------------------------------------------------------- +; bnxor +;------------------------------------------------------------- + +(define-pmacro (bnxor-sem src) + (set cbit (xor (inv src) cbit)) +) +(bitsrc-insn bnxor (f-0-4 7) (f-4-4 #xE) (f-8-4 #xD) #xD #x0 #x7 bnxor-sem) + +;------------------------------------------------------------- +; bor +;------------------------------------------------------------- + +(define-pmacro (bor-sem src) + (set cbit (or src cbit)) +) +(bitsrc-insn bor (f-0-4 7) (f-4-4 #xE) (f-8-4 #x6) #xD #x0 #x4 bor-sem) + +;------------------------------------------------------------- +; brk +;------------------------------------------------------------- + +(dni brk16 + "brk" + ((machine 16)) + "brk" + (+ (f-0-4 #x0) (f-4-4 #x0)) + (nop) + ()) + +(dni brk32 + "brk" + ((machine 32)) + "brk" + (+ (f-0-4 #x0) (f-4-4 #x0)) + (nop) + ()) + +;------------------------------------------------------------- +; brk2 +;------------------------------------------------------------- + +(dni brk232 + "brk2" + ((machine 32)) + "brk2" + (+ (f-0-4 #x0) (f-4-4 #x8)) + (nop) + ()) + +;------------------------------------------------------------- +; bset +;------------------------------------------------------------- + +(define-pmacro (bset-sem dst) + (set dst 1) +) +(bitdst-insn bset (f-0-4 7) (f-4-4 #xE) (f-8-4 9) (f-0-2 1) (f-2-2 0) (f-4-1 1) #xD #x0 #x7 bset-sem) + +;------------------------------------------------------------- +; btst +;------------------------------------------------------------- + +(define-pmacro (btst-sem dst) + (set zbit (inv dst)) + (set cbit dst) +) +(bitdst-insn btst (f-0-4 7) (f-4-4 #xE) (f-8-4 #xB) (f-0-2 1) (f-2-2 1) (f-4-1 1) #xD #x0 #x0 btst-sem) + +;------------------------------------------------------------- +; btstc +;------------------------------------------------------------- + +(define-pmacro (btstc-sem dst) + (set zbit (inv dst)) + (set cbit dst) + (set dst (const 0)) +) +(bitdstnos-insn btstc (f-0-4 7) (f-4-4 #xE) (f-8-4 #x0) #xD #x0 #x4 btstc-sem) + +;------------------------------------------------------------- +; btsts +;------------------------------------------------------------- + +(define-pmacro (btsts-sem dst) + (set zbit (inv dst)) + (set cbit dst) + (set dst (const 0)) +) +(bitdstnos-insn btsts (f-0-4 7) (f-4-4 #xE) (f-8-4 #x1) #xD #x0 #x5 btsts-sem) + +;------------------------------------------------------------- +; bxor +;------------------------------------------------------------- + +(define-pmacro (bxor-sem src) + (set cbit (xor src cbit)) +) +(bitsrc-insn bxor (f-0-4 7) (f-4-4 #xE) (f-8-4 #xC) #xD #x0 #x5 bxor-sem) + +;------------------------------------------------------------- +; clip +;------------------------------------------------------------- + +(define-pmacro (clip-sem mode imm1 imm2 dest) + (sequence () + (if (gt mode imm1 dest) + (set dest imm1)) + (if (lt mode imm2 dest) + (set dest imm2))) +) + +(insn-imm1-imm2-dst-Prefixed clip #x8 #x3 #xE clip-sem) + +;------------------------------------------------------------- +; cmp - binary compare +;------------------------------------------------------------- + +(define-pmacro (cmp-sem mode src1 dst) + (sequence ((mode result)) + (set result (sub mode dst src1)) + (set obit (sub-oflag mode dst src1 0)) + (set cbit (not (sub-cflag mode dst src1 0))) + (set-z-and-s result)) +) + +; cmp.L:G #imm32,dst (m32 #2) +(binary-arith32-imm-dst-defn SI SI .l 0 cmp G #xA #x3 #x1 cmp-sem) +; cmp.size:G #imm,dst (m16 #1 m32 #1) +(binary-arith-imm-dst cmp G (f-0-4 7) (f-4-3 3) (f-8-4 8) #x9 #x2 #xE cmp-sem) +; cmp.size:Q #imm4,dst (m16 #2 m32 #3) +(binary-arith-imm4-dst cmp (f-0-4 #xD) (f-4-3 0) #x7 #x1 cmp-sem) +; cmp.b:S #imm8,dst3 (m16 #3) +(binary-arith16-b-S-imm8-dst3 cmp ".b" (f-0-4 #xE) (f-4-1 0) cmp-sem) +; cmp.BW:G src,dst (m16 #4 m32 #5) +(binary-arith-src-dst cmp G (f-0-4 #xC) (f-4-3 0) #x1 #x6 cmp-sem) +; cmp.B.S src2,r0l/r0h (m16 #5) +(binary-arith16-b-S-src2 cmp (f-0-4 3) (f-4-1 1) cmp-sem) +; cmp.L:G src,dst (m32 #6) +(binary-arith32-src-dst-defn SI SI .l 1 cmp G #x1 #x1 cmp-sem) +; cmp.BW:S #imm,dst2 (m32 #4) +(binary-arith32-s-imm-dst QI .b 0 cmp #x1 #x3 cmp-sem) +(binary-arith32-s-imm-dst HI .w 1 cmp #x1 #x3 cmp-sem) +; cmp.BW:s src2,r0[l] (m32 #7) +(binary-arith32-S-src2 cmp QI .b 0 (f-0-2 1) (f-4-3 0) cmp-sem) +(binary-arith32-S-src2 cmp HI .w 1 (f-0-2 1) (f-4-3 0) cmp-sem) + +;------------------------------------------------------------- +; cmpx - binary compare extend sign +;------------------------------------------------------------- + +(define-pmacro (cmpx-sem mode src1 dst) + (sequence ((mode result)) + (set result (sub mode dst (ext mode src1))) + (set obit (sub-oflag mode dst (ext mode src1) 0)) + (set cbit (sub-cflag mode dst (ext mode src1) 0)) + (set-z-and-s result)) +) + +(binary-arith32-imm-dst-defn QI SI "" 0 cmpx X #xA #x1 #x1 cmpx-sem) + +;------------------------------------------------------------- +; dec - decrement +;------------------------------------------------------------- + +(define-pmacro (dec-sem mode dest) + (sequence ((mode result)) + (set result (sub mode dest 1)) + (set-z-and-s result) + (set dest result)) +) + +(dni dec16.b + "dec.b Dst16-3-S-8" + ((machine 16)) + "dec.b ${Dst16-3-S-8}" + (+ (f-0-4 #xA) (f-4-1 #x1) Dst16-3-S-8) + (dec-sem QI Dst16-3-S-8) + ()) + +(dni dec16.w + "dec.w Dst16An-S" + ((machine 16)) + "dec.w ${Dst16An-S}" + (+ (f-0-4 #xF) (f-5-3 #x2) Dst16An-S) + (dec-sem HI Dst16An-S) + ()) + +(unary32-defn QI .b 0 dec #xB #x0 #xE dec-sem) +(unary32-defn HI .w 1 dec #xB #x0 #xE dec-sem) + +;------------------------------------------------------------- +; div - divide +; divu - divide unsigned +; divx - divide extension +;------------------------------------------------------------- + +; div.BW #imm +(div-imm div div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x1) #xB #x0 #x2 #x3 div-sem) +(div-imm divu udiv umod USI 255 0 65535 0 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x0) #xB #x0 #x0 #x3 div-sem) +(div-imm divx div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x3) #xB #x2 #x2 #x3 div-sem) +; div.BW src +(div-src div div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 3) (f-8-4 #xD) #x8 #x1 #xE div-sem) +(div-src divu udiv umod USI 255 0 65535 0 (f-0-4 #x7) (f-4-3 3) (f-8-4 #xC) #x8 #x0 #xE div-sem) +(div-src divx div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 3) (f-8-4 #x9) #x9 #x1 #xE div-sem) + +(div-src-defn 32 .l div dst32-24-Prefixed-SI + (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x1) (f-20-4 #xf) dst32-24-Prefixed-SI) + div mod SI R2R0 R2R0 NoRemainder #x7fffffff (neg SI #x80000000) + div-sem) +(div-src-defn 32 .l divu dst32-24-Prefixed-SI + (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x0) (f-20-4 #xf) dst32-24-Prefixed-SI) + udiv umod USI R2R0 R2R0 NoRemainder #x80000000 0 + div-sem) +(div-src-defn 32 .l divx dst32-24-Prefixed-SI + (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x2) (f-20-4 #xf) dst32-24-Prefixed-SI) + div mod SI R2R0 R2R0 NoRemainder #x7fffffff (neg SI #x80000000) + div-sem) + +;------------------------------------------------------------- +; dsbb - decimal subtraction with borrow +; dsub - decimal subtraction +;------------------------------------------------------------- + +(define-pmacro (dsbb-sem mode src dst) + (sequence ((mode result)) + (set result (subc mode dst src (not cbit))) + (set cbit (sub-cflag mode dst src (not cbit))) + (set-z-and-s result) + (set dst result)) +) + +; dsbb for m16c +(decimal-subtraction16-insn dsbb #xF #x7) + +; dsbb.size #imm,dst +(binary-arith32-imm-dst-Prefixed QI QI .b 0 dsbb X #x9 #x0 #xE dsbb-sem) +(binary-arith32-imm-dst-Prefixed HI HI .w 1 dsbb X #x9 #x0 #xE dsbb-sem) +; dsbb.BW src,dst +(binary-arith32-src-dst-Prefixed QI QI .b 0 dsbb X #x1 #xA dsbb-sem) +(binary-arith32-src-dst-Prefixed HI HI .w 1 dsbb X #x1 #xA dsbb-sem) + +(define-pmacro (dsub-sem mode src dst) + (sequence ((mode result)) + (set result (subc mode dst src 0)) + (set cbit (sub-cflag mode dst src 0)) + (set-z-and-s result) + (set dst result)) +) + +; dsub for m16c +(decimal-subtraction16-insn dsub #xD #x5) + +; dsub.size #imm,dst +(binary-arith32-imm-dst-Prefixed QI QI .b 0 dsub X #x9 #x1 #xE dsub-sem) +(binary-arith32-imm-dst-Prefixed HI HI .w 1 dsub X #x9 #x1 #xE dsub-sem) +; dsub.BW src,dst +(binary-arith32-src-dst-Prefixed QI QI .b 0 dsub X #x1 #x2 dsub-sem) +(binary-arith32-src-dst-Prefixed HI HI .w 1 dsub X #x1 #x2 dsub-sem) + +;------------------------------------------------------------- +; sub - binary subtraction +;------------------------------------------------------------- + +(define-pmacro (sub-sem mode src1 dst) + (sequence ((mode result)) + (set result (sub mode dst src1)) + (set obit (sub-oflag mode dst src1 0)) + (set cbit (sub-cflag mode dst src1 0)) + (set dst result) + (set-z-and-s result))) + +; sub.size:G #imm,dst (m16 #1 m32 #1) +(binary-arith-imm-dst sub G (f-0-4 7) (f-4-3 3) (f-8-4 5) #x8 #x3 #xE sub-sem) +; sub.b:S #imm8,dst3 (m16 #2) +(binary-arith16-b-S-imm8-dst3 sub ".b" (f-0-4 8) (f-4-1 1) sub-sem) +; sub.BW:G src,dst (m16 #3 m32 #4) +(binary-arith-src-dst sub G (f-0-4 #xA) (f-4-3 4) #x1 #xA sub-sem) +; sub.B.S src2,r0l/r0h (m16 #4) +(binary-arith16-b-S-src2 sub (f-0-4 2) (f-4-1 1) sub-sem) +; sub.L:G #imm32,dst (m32 #2) +(binary-arith32-imm-dst-defn SI SI .l 0 sub G #x9 #x3 #x1 sub-sem) +; sub.BW:S #imm,dst2 (m32 #3) +(binary-arith32-s-imm-dst QI .b 0 sub #x0 #x7 sub-sem) +(binary-arith32-s-imm-dst HI .w 1 sub #x0 #x7 sub-sem) +; sub.L:G src,dst (m32 #5) +(binary-arith32-src-dst-defn SI SI .l 1 sub G #x1 #x0 sub-sem) + +;------------------------------------------------------------- +; enter - enter function +; exitd - exit and deallocate stack frame +;------------------------------------------------------------- + +(define-pmacro (enter16-sem mach amt) + (sequence () + (set (reg h-sp) (sub (reg h-sp) 2)) + (set (mem16 HI (reg h-sp)) (reg h-fb)) + (set (reg h-fb) (reg h-sp)) + (set (reg h-sp) (sub (reg h-sp) amt)))) + +(define-pmacro (exit16-sem mach) + (sequence ((SI newpc)) + (set (reg h-sp) (reg h-fb)) + (set (reg h-fb) (mem16 HI (reg h-sp))) + (set (reg h-sp) (add (reg h-sp) 2)) + (set newpc (mem16 HI (reg h-sp))) + (set (reg h-sp) (add (reg h-sp) 2)) + (set newpc (or newpc (sll (mem16 QI (reg h-sp)) (const 16)))) + (set (reg h-sp) (add (reg h-sp) 1)) + (set pc newpc))) + +(define-pmacro (enter32-sem mach amt) + (sequence () + (set (reg h-sp) (sub (reg h-sp) 4)) + (set (mem32 SI (reg h-sp)) (reg h-fb)) + (set (reg h-fb) (reg h-sp)) + (set (reg h-sp) (sub (reg h-sp) amt)))) + +(define-pmacro (exit32-sem mach) + (sequence ((SI newpc)) + (set (reg h-sp) (reg h-fb)) + (set (reg h-fb) (mem32 SI (reg h-sp))) + (set (reg h-sp) (add (reg h-sp) 4)) + (set newpc (mem32 SI (reg h-sp))) + (set (reg h-sp) (add (reg h-sp) 4)) + (set pc newpc))) + +(dni enter16 "enter #Imm-16-QI" ((machine 16)) + ("enter #${Dsp-16-u8}") + (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 2) Dsp-16-u8) + (enter16-sem 16 Dsp-16-u8) + ()) + +(dni exitd16 "exitd" ((machine 16)) + ("exitd") + (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 2)) + (exit16-sem 16) + ()) + +(dni enter32 "enter #Imm-8-QI" ((machine 32)) + ("enter #${Dsp-8-u8}") + (+ (f-0-4 #xE) (f-4-4 #xC) Dsp-8-u8) + (enter32-sem 32 Dsp-8-u8) + ()) + +(dni exitd32 "exitd" ((machine 32)) + ("exitd") + (+ (f-0-4 #xF) (f-4-4 #xC)) + (exit32-sem 32) + ()) + +;------------------------------------------------------------- +; fclr - flag register clear +; fset - flag register set +;------------------------------------------------------------- + +(define-pmacro (set-flags-sem flag) + (sequence ((SI tmp)) + (case DFLT flag + ((#x0) (set cbit 1)) + ((#x1) (set dbit 1)) + ((#x2) (set zbit 1)) + ((#x3) (set sbit 1)) + ((#x4) (set bbit 1)) + ((#x5) (set obit 1)) + ((#x6) (set ibit 1)) + ((#x7) (set ubit 1))) + ) + ) + +(define-pmacro (clear-flags-sem flag) + (sequence ((SI tmp)) + (case DFLT flag + ((#x0) (set cbit 0)) + ((#x1) (set dbit 0)) + ((#x2) (set zbit 0)) + ((#x3) (set sbit 0)) + ((#x4) (set bbit 0)) + ((#x5) (set obit 0)) + ((#x6) (set ibit 0)) + ((#x7) (set ubit 0))) + ) + ) + +(dni fclr16 "fclr flag" ((machine 16)) + ("fclr ${flags16}") + (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) flags16 (f-12-4 5)) + (clear-flags-sem flags16) + ()) + +(dni fset16 "fset flag" ((machine 16)) + ("fset ${flags16}") + (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) flags16 (f-12-4 4)) + (set-flags-sem flags16) + ()) + +(dni fclr "fclr" ((machine 32)) + ("fclr ${flags32}") + (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 #xE) (f-12-1 1) flags32) + (clear-flags-sem flags32) + ()) + +(dni fset "fset" ((machine 32)) + ("fset ${flags32}") + (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 #xE) (f-12-1 1) flags32) + (set-flags-sem flags32) + ()) + +;------------------------------------------------------------- +; inc - increment +;------------------------------------------------------------- + +(define-pmacro (inc-sem mode dest) + (sequence ((mode result)) + (set result (add mode dest 1)) + (set-z-and-s result) + (set dest result)) +) + +(dni inc16.b + "inc.b Dst16-3-S-8" + ((machine 16)) + "inc.b ${Dst16-3-S-8}" + (+ (f-0-4 #xA) (f-4-1 #x0) Dst16-3-S-8) + (inc-sem QI Dst16-3-S-8) + ()) + +(dni inc16.w + "inc.w Dst16An-S" + ((machine 16)) + "inc.w ${Dst16An-S}" + (+ (f-0-4 #xB) (f-5-3 #x2) Dst16An-S) + (inc-sem HI Dst16An-S) + ()) + +(unary32-defn QI .b 0 inc #xA #x0 #xE inc-sem) +(unary32-defn HI .w 1 inc #xA #x0 #xE inc-sem) + +;------------------------------------------------------------- +; freit - fast return from interrupt (m32) +; int - interrupt +; into - interrupt on overflow +;------------------------------------------------------------- + +; ??? semantics +(dni freit32 "FREIT" ((machine 32)) + ("freit") + (+ (f-0-4 9) (f-4-4 #xF)) + (nop) + ()) + +(dni int16 "int Dsp-10-u6" ((machine 16)) + ("int #${Dsp-10-u6}") + (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-2 3) Dsp-10-u6) + (c-call VOID "do_int" pc Dsp-10-u6) + ()) + +(dni into16 "into" ((machine 16)) + ("into") + (+ (f-0-4 #xF) (f-4-4 6)) + (nop) + ()) + +(dni int32 "int Dsp-8-u6" ((machine 32)) + ("int #${Dsp-8-u6}") + (+ (f-0-4 #xB) (f-4-4 #xE) Dsp-8-u6 (f-14-2 0)) + (c-call VOID "do_int" pc Dsp-8-u6) + ()) + +(dni into32 "into" ((machine 32)) + ("into") + (+ (f-0-4 #xB) (f-4-4 #xF)) + (nop) + ()) + +;------------------------------------------------------------- +; index (m32c) +;------------------------------------------------------------- + +; TODO add support to insns allowing index +(define-pmacro (indexb-sem mode d) (set SrcIndex d) (set DstIndex d)) +(define-pmacro (indexbd-sem mode d) (set SrcIndex (const 0)) (set DstIndex d)) +(define-pmacro (indexbs-sem mode d) (set SrcIndex d) (set DstIndex (const 0))) +(define-pmacro (indexw-sem mode d) + (set SrcIndex (sll d (const 2))) (set DstIndex (sll d (const 2)))) +(define-pmacro (indexwd-sem mode d) + (set SrcIndex (const 0)) (set DstIndex (sll d (const 2)))) +(define-pmacro (indexws-sem mode d) + (set SrcIndex (sll d (const 2))) (set DstIndex (const 0))) +(define-pmacro (indexl-sem mode d) + (set SrcIndex d) (set DstIndex (sll d (const 2)))) +(define-pmacro (indexld-sem mode d) + (set SrcIndex (const 0)) (set DstIndex (sll d (const 2)))) +(define-pmacro (indexls-sem mode d) + (set SrcIndex (sll d (const 2))) (set DstIndex (const 0))) + +; indexb src (index byte) +(unary32-defn QI .b 0 indexb #x8 0 #x3 indexb-sem) +(unary32-defn HI .w 0 indexb #x8 1 #x3 indexb-sem) +; indexbd src (index byte dest) +(unary32-defn QI .b 0 indexbd #xA 0 3 indexbd-sem) +(unary32-defn HI .w 0 indexbd #xA 1 3 indexbd-sem) +; indexbs src (index byte src) +(unary32-defn QI .b 0 indexbs #xC 0 3 indexbs-sem) +(unary32-defn HI .w 0 indexbs #xC 1 3 indexbs-sem) +; indexl src (index long) +(unary32-defn QI .b 0 indexl 9 2 3 indexl-sem) +(unary32-defn HI .w 0 indexl 9 3 3 indexl-sem) +; indexld src (index long dest) +(unary32-defn QI .b 0 indexld #xB 2 3 indexld-sem) +(unary32-defn HI .w 0 indexld #xB 3 3 indexld-sem) +; indexls src (index long src) +(unary32-defn QI .b 0 indexls 9 0 3 indexls-sem) +(unary32-defn HI .w 0 indexls 9 1 3 indexls-sem) +; indexw src (index word) +(unary32-defn QI .b 0 indexw 8 2 3 indexw-sem) +(unary32-defn HI .w 0 indexw 8 3 3 indexw-sem) +; indexwd src (index word dest) +(unary32-defn QI .b 0 indexwd #xA 2 3 indexwd-sem) +(unary32-defn HI .w 0 indexwd #xA 3 3 indexwd-sem) +; indexws (index word src) +(unary32-defn QI .b 0 indexws #xC 2 3 indexws-sem) +(unary32-defn HI .w 0 indexws #xC 3 3 indexws-sem) + +;------------------------------------------------------------- +; jcc - jump on condition +;------------------------------------------------------------- + +(define-pmacro (jcnd32-sem cnd label) + (sequence () + (case DFLT cnd + ((#x00) (if (not cbit) (set pc label))) ;ltu nc + ((#x01) (if (not (and cbit (not zbit))) (set pc label))) ;leu + ((#x02) (if (not zbit) (set pc label))) ;ne nz + ((#x03) (if (not sbit) (set pc label))) ;pz + ((#x04) (if (not obit) (set pc label))) ;no + ((#x05) (if (not (or zbit (xor sbit obit))) (set pc label))) ;gt + ((#x06) (if (not (xor sbit obit)) (set pc label))) ;ge + ((#x08) (if (trunc BI cbit) (set pc label))) ;geu c + ((#x09) (if (and cbit (not zbit)) (set pc label))) ;gtu + ((#x0a) (if (trunc BI zbit) (set pc label))) ;eq z + ((#x0b) (if (trunc BI sbit) (set pc label))) ;n + ((#x0c) (if (trunc BI obit) (set pc label))) ;o + ((#x0d) (if (or zbit (xor sbit obit)) (set pc label))) ;le + ((#x0e) (if (xor sbit obit) (set pc label))) ;lt + ) + ) + ) + +(define-pmacro (jcnd16-sem cnd label) + (sequence () + (case DFLT cnd + ((#x00) (if (trunc BI cbit) (set pc label))) ;geu c + ((#x01) (if (and cbit (not zbit)) (set pc label))) ;gtu + ((#x02) (if (trunc BI zbit) (set pc label))) ;eq z + ((#x03) (if (trunc BI sbit) (set pc label))) ;n + ((#x04) (if (not cbit) (set pc label))) ;ltu nc + ((#x05) (if (not (and cbit (not zbit))) (set pc label))) ;leu + ((#x06) (if (not zbit) (set pc label))) ;ne nz + ((#x07) (if (not sbit) (set pc label))) ;pz + ((#x08) (if (or zbit (xor sbit obit)) (set pc label))) ;le + ((#x09) (if (trunc BI obit) (set pc label))) ;o + ((#x0a) (if (not (xor sbit obit)) (set pc label))) ;ge + ((#x0c) (if (not (or zbit (xor sbit obit))) (set pc label))) ;gt + ((#x0d) (if (not obit) (set pc label))) ;no + ((#x0e) (if (xor sbit obit) (set pc label))) ;lt + ) + ) + ) + +(dni jcnd16-5 + "jCnd label" + (RELAXABLE (machine 16)) + "j$cond16j5 ${Lab-8-8}" + (+ (f-0-4 #x6) (f-4-1 1) cond16j5 Lab-8-8) + (jcnd16-sem cond16j5 Lab-8-8) + () +) + +(dni jcnd16 + "jCnd label" + (RELAXABLE (machine 16)) + "j$cond16j ${Lab-16-8}" + (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xC) cond16j Lab-16-8) + (jcnd16-sem cond16j Lab-16-8) + () +) + +(dni jcnd32 + "jCnd label" + (RELAXABLE (machine 32)) + "j$cond32j ${Lab-8-8}" + (+ (f-0-1 1) (f-4-3 5) cond32j Lab-8-8) + (jcnd32-sem cond32j Lab-8-8) + () +) + +;------------------------------------------------------------- +; jmp - jump +;------------------------------------------------------------- + +; jmp.s label3 (m16 #1) +(dni jmp16.s "jmp.s Lab-5-3" (RELAXABLE (machine 16)) + ("jmp.s ${Lab-5-3}") + (+ (f-0-4 6) (f-4-1 0) Lab-5-3) + (sequence () (set pc Lab-5-3)) + ()) +; jmp.b label8 (m16 #2) +(dni jmp16.b "jmp.b Lab-8-8" (RELAXABLE (machine 16)) + ("jmp.b ${Lab-8-8}") + (+ (f-0-4 #xF) (f-4-4 #xE) Lab-8-8) + (sequence () (set pc Lab-8-8)) + ()) +; jmp.w label16 (m16 #3) +(dni jmp16.w "jmp.w Lab-8-16" (RELAXABLE (machine 16)) + ("jmp.w ${Lab-8-16}") + (+ (f-0-4 #xF) (f-4-4 4) Lab-8-16) + (sequence () (set pc Lab-8-16)) + ()) +; jmp.a label24 (m16 #4) +(dni jmp16.a "jmp.a Lab-8-24" ((machine 16)) + ("jmp.a ${Lab-8-24}") + (+ (f-0-4 #xF) (f-4-4 #xC) Lab-8-24) + (sequence () (set pc Lab-8-24)) + ()) + +(define-pmacro (jmp16-sem mode dst) + (set pc (and dst #xfffff)) +) +(define-pmacro (jmp32-sem mode dst) + (set pc dst) +) +; jmpi.w dst (m16 #1 m32 #2) +(unary-insn-defn 16 16 HI .w jmpi (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 2) dst16-16-HI) jmp16-sem) +(unary-insn-defn 32 16-Unprefixed HI .w jmpi (+ (f-0-4 #xC) (f-7-1 1) dst32-16-Unprefixed-HI (f-10-2 #x0) (f-12-4 #xF)) jmp32-sem) +; jmpi.a dst (m16 #2 m32 #2) +(unary-insn-defn 16 16 SI .a jmpi (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 0) dst16-16-SI) jmp16-sem) +(unary-insn-defn 32 16-Unprefixed SI .a jmpi (+ (f-0-4 #x8) (f-7-1 0) dst32-16-Unprefixed-SI (f-10-2 #x0) (f-12-4 1)) jmp32-sem) +; jmps imm8 (m16 #1) +(dni jmps16 "jmps Imm-8-QI" ((machine 16)) + ("jmps #${Imm-8-QI}") + (+ (f-0-4 #xE) (f-4-4 #xE) Imm-8-QI) + (sequence () (set pc Imm-8-QI)) + ()) +; jmp.s label3 (m32 #1) +(dni jmp32.s + "jmp.s label" + (RELAXABLE (machine 32)) + "jmp.s ${Lab32-jmp-s}" + (+ (f-0-2 1) (f-4-3 5) Lab32-jmp-s) + (set pc Lab32-jmp-s) + () +) +; jmp.b label8 (m32 #2) +(dni jmp32.b "jmp.b Lab-8-8" (RELAXABLE (machine 32)) + ("jmp.b ${Lab-8-8}") + (+ (f-0-4 #xB) (f-4-4 #xB) Lab-8-8) + (set pc Lab-8-8) + ()) +; jmp.w label16 (m32 #3) +(dni jmp32.w "jmp.w Lab-8-16" (RELAXABLE (machine 32)) + ("jmp.w ${Lab-8-16}") + (+ (f-0-4 #xC) (f-4-4 #xE) Lab-8-16) + (set pc Lab-8-16) + ()) +; jmp.a label24 (m32 #4) +(dni jmp32.a "jmp.a Lab-8-24" ((machine 32)) + ("jmp.a ${Lab-8-24}") + (+ (f-0-4 #xC) (f-4-4 #xC) Lab-8-24) + (set pc Lab-8-24) + ()) +; jmp.s imm8 (m32 #1) +(dni jmps32 "jmps Imm-8-QI" ((machine 32)) + ("jmps #${Imm-8-QI}") + (+ (f-0-4 #xD) (f-4-4 #xC) Imm-8-QI) + (set pc Imm-8-QI) + ()) + +;------------------------------------------------------------- +; jsr jump subroutine +;------------------------------------------------------------- + +(define-pmacro (jsr16-sem length dst) + (sequence ((SI tpc)) + (set tpc (add pc length)) + (set (reg h-sp) (sub (reg h-sp) 2)) + (set (mem16 HI (reg h-sp)) (srl (and tpc #xffff00) 8)) + (set (reg h-sp) (sub (reg h-sp) 1)) + (set (mem16 QI (reg h-sp)) (and tpc #xff)) + (set pc dst) + ) +) +(define-pmacro (jsr32-sem length dst) + (sequence ((SI tpc)) + (set tpc (add pc length)) + (set (reg h-sp) (sub (reg h-sp) 2)) + (set (mem32 HI (reg h-sp)) (srl (and tpc #xffff0000) 16)) + (set (reg h-sp) (sub (reg h-sp) 2)) + (set (mem32 HI (reg h-sp)) (and tpc #xffff)) + (set pc dst) + ) +) + +; jsr.w label16 (m16 #1) +(dni jsr16.w "jsr.w Lab-8-16" (RELAXABLE (machine 16)) + ("jsr.w ${Lab-8-16}") + (+ (f-0-4 #xF) (f-4-4 5) Lab-8-16) + (jsr16-sem 3 Lab-8-16) + ()) +; jsr.a label24 (m16 #2) +(dni jsr16.a "jsr.a Lab-8-24" ((machine 16)) + ("jsr.a ${Lab-8-24}") + (+ (f-0-4 #xF) (f-4-4 #xD) Lab-8-24) + (jsr16-sem 4 Lab-8-24) + ()) +(define-pmacro (jsri-defn mode op16 op16-1 op16-2 op16-3 op16-sem + op32 op32-1 op32-2 op32-3 op32-4 op32-sem len) + (begin + (dni (.sym jsri16 mode - op16) + (.str "jsri." mode " " op16) + ((machine 16)) + (.str "jsri." mode " ${" op16 "}") + (+ op16-1 op16-2 op16-3 op16) + (op16-sem len op16) + ()) + (dni (.sym jsri32 mode - op32) + (.str "jsri." mode " " op32) + ((machine 32)) + (.str "jsri." mode " ${" op32 "}") + (+ op32-1 op32-2 op32-3 op32-4 op32) + (op32-sem len op32) + ()) + ) + ) +; jsri.w dst (m16 #1 m32 #1)) +(jsri-defn w dst16-basic-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem + dst32-basic-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 2) +(jsri-defn w dst16-16-8-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem + dst32-16-8-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 3) +(jsri-defn w dst16-16-16-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem + dst32-16-16-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4) +(dni jsri32.w "jsr.w dst32-16-24-Unprefixed-HI" ((machine 32)) + ("jsri.w ${dst32-16-24-Unprefixed-HI}") + (+ (f-0-4 #xC) (f-7-1 1) dst32-16-24-Unprefixed-HI (f-10-2 #x1) (f-12-4 #xF)) + (jsr32-sem 6 dst32-16-24-Unprefixed-HI) + ()) + +; jsri.a (m16 #2 m32 #2) +(jsri-defn a dst16-basic-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem + dst32-basic-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 2) +(jsri-defn a dst16-16-8-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem + dst32-16-8-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 3) +(jsri-defn a dst16-16-16-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem + dst32-16-16-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4) +(dni jsri32.a "jsr.w dst32-16-24-Unprefixed-HI" ((machine 32)) + ("jsri.w ${dst32-16-24-Unprefixed-SI}") + (+ (f-0-4 #x9) (f-7-1 0) dst32-16-24-Unprefixed-SI (f-10-2 #x0) (f-12-4 #x1)) + (jsr32-sem 6 dst32-16-24-Unprefixed-SI) + ()) +; jsr.w label16 (m32 #1) +(dni jsr32.w "jsr.w label" (RELAXABLE (machine 32)) + ("jsr.w ${Lab-8-16}") + (+ (f-0-4 #xC) (f-4-4 #xF) Lab-8-16) + (jsr32-sem 3 Lab-8-16) + ()) +; jsr.a label16 (m32 #2) +(dni jsr32.a "jsr.a label" ((machine 32)) + ("jsr.a ${Lab-8-24}") + (+ (f-0-4 #xC) (f-4-4 #xD) Lab-8-24) + (jsr32-sem 4 Lab-8-24) + ()) +; jsrs imm8 (m16 #1) +(dni jsrs16 "jsrs Imm-8-QI" ((machine 16)) + ("jsrs #${Imm-8-QI}") + (+ (f-0-4 #xE) (f-4-4 #xF) Imm-8-QI) + (jsr16-sem 2 Imm-8-QI) + ()) +; jsrs imm8 (m32 #1) +(dni jsrs "jsrs #Imm-8-QI" ((machine 32)) + ("jsrs #${Imm-8-QI}") + (+ (f-0-4 #xD) (f-4-4 #xD) Imm-8-QI) + (jsr32-sem 2 Imm-8-QI) + ()) + +;------------------------------------------------------------- +; ldc - load control register +; stc - store control register +;------------------------------------------------------------- + +(define-pmacro (ldc32-cr1-sem src dst) + (sequence () + (case DFLT dst + ((#x0) (set (reg h-dct0) src)) + ((#x1) (set (reg h-dct1) src)) + ((#x2) (sequence ((HI tflag)) + (set tflag src) + (if (and tflag #x1) (set cbit 1)) + (if (and tflag #x2) (set dbit 1)) + (if (and tflag #x4) (set zbit 1)) + (if (and tflag #x8) (set sbit 1)) + (if (and tflag #x10) (set bbit 1)) + (if (and tflag #x20) (set obit 1)) + (if (and tflag #x40) (set ibit 1)) + (if (and tflag #x80) (set ubit 1)))) + ((#x3) (set (reg h-svf) src)) + ((#x4) (set (reg h-drc0) src)) + ((#x5) (set (reg h-drc1) src)) + ((#x6) (set (reg h-dmd0) src)) + ((#x7) (set (reg h-dmd1) src)) + ) + ) +) +(define-pmacro (ldc32-cr2-sem src dst) + (sequence () + (case DFLT dst + ((#x0) (set (reg h-intb) src)) + ((#x1) (set (reg h-sp) src)) + ((#x2) (set (reg h-sb) src)) + ((#x3) (set (reg h-fb) src)) + ((#x4) (set (reg h-svp) src)) + ((#x5) (set (reg h-vct) src)) + ((#x7) (set (reg h-isp) src)) + ) + ) +) +(define-pmacro (ldc32-cr3-sem src dst) + (sequence () + (case DFLT dst + ((#x2) (set (reg h-dma0) src)) + ((#x3) (set (reg h-dma1) src)) + ((#x4) (set (reg h-dra0) src)) + ((#x5) (set (reg h-dra1) src)) + ((#x6) (set (reg h-dsa0) src)) + ((#x7) (set (reg h-dsa1) src)) + ) + ) +) +(define-pmacro (ldc16-sem src dst) + (sequence () + (case DFLT dst + ((#x1) (set (reg h-intb) src)) + ((#x2) (set (reg h-intb) (or (reg h-intb) (sll src (const 16))))) + ((#x3) (sequence ((HI tflag)) + (set tflag src) + (if (and tflag #x1) (set cbit 1)) + (if (and tflag #x2) (set dbit 1)) + (if (and tflag #x4) (set zbit 1)) + (if (and tflag #x8) (set sbit 1)) + (if (and tflag #x10) (set bbit 1)) + (if (and tflag #x20) (set obit 1)) + (if (and tflag #x40) (set ibit 1)) + (if (and tflag #x80) (set ubit 1)))) + ((#x4) (set (reg h-isp) src)) + ((#x5) (set (reg h-sp) src)) + ((#x6) (set (reg h-sb) src)) + ((#x7) (set (reg h-fb) src)) + ) + ) +) + +(define-pmacro (stc32-cr1-sem src dst) + (sequence () + (case DFLT src + ((#x0) (set dst (reg h-dct0))) + ((#x1) (set dst (reg h-dct1))) + ((#x2) (sequence ((HI tflag)) + (set tflag 0) + (if (eq cbit 1) (set tflag (or tflag #x1))) + (if (eq dbit 1) (set tflag (or tflag #x2))) + (if (eq zbit 1) (set tflag (or tflag #x4))) + (if (eq sbit 1) (set tflag (or tflag #x8))) + (if (eq bbit 1) (set tflag (or tflag #x10))) + (if (eq obit 1) (set tflag (or tflag #x20))) + (if (eq ibit 1) (set tflag (or tflag #x40))) + (if (eq ubit 1) (set tflag (or tflag #x80))) + (set dst tflag))) + ((#x3) (set dst (reg h-svf))) + ((#x4) (set dst (reg h-drc0))) + ((#x5) (set dst (reg h-drc1))) + ((#x6) (set dst (reg h-dmd0))) + ((#x7) (set dst (reg h-dmd1))) + ) + ) +) +(define-pmacro (stc32-cr2-sem src dst) + (sequence () + (case DFLT src + ((#x0) (set dst (reg h-intb))) + ((#x1) (set dst (reg h-sp))) + ((#x2) (set dst (reg h-sb))) + ((#x3) (set dst (reg h-fb))) + ((#x4) (set dst (reg h-svp))) + ((#x5) (set dst (reg h-vct))) + ((#x7) (set dst (reg h-isp))) + ) + ) +) +(define-pmacro (stc32-cr3-sem src dst) + (sequence () + (case DFLT src + ((#x2) (set dst (reg h-dma0))) + ((#x3) (set dst (reg h-dma1))) + ((#x4) (set dst (reg h-dra0))) + ((#x5) (set dst (reg h-dra1))) + ((#x6) (set dst (reg h-dsa0))) + ((#x7) (set dst (reg h-dsa1))) + ) + ) +) +(define-pmacro (stc16-sem src dst) + (sequence () + (case DFLT src + ((#x1) (set dst (and (reg h-intb) (const #xffff)))) + ((#x2) (set dst (srl (reg h-intb) (const 16)))) + ((#x3) (sequence ((HI tflag)) + (set tflag 0) + (if (eq cbit 1) (set tflag (or tflag #x1))) + (if (eq dbit 1) (set tflag (or tflag #x2))) + (if (eq zbit 1) (set tflag (or tflag #x4))) + (if (eq sbit 1) (set tflag (or tflag #x8))) + (if (eq bbit 1) (set tflag (or tflag #x10))) + (if (eq obit 1) (set tflag (or tflag #x20))) + (if (eq ibit 1) (set tflag (or tflag #x40))) + (if (eq ubit 1) (set tflag (or tflag #x80))) + (set dst tflag))) + ((#x4) (set dst (reg h-isp))) + ((#x5) (set dst (reg h-sp))) + ((#x6) (set dst (reg h-sb))) + ((#x7) (set dst (reg h-fb))) + ) + ) +) + +(dni ldc16.imm16 "ldc #imm,dst" ((machine 16)) + ("ldc #${Imm-16-HI},${cr16}") + (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 0) cr16 Imm-16-HI) + (ldc16-sem Imm-16-HI cr16) + ()) + +(dni ldc16.dst "ldc src,dest" ((machine 16)) + ("ldc ${dst16-16-HI},${cr16}") + (+ (f-0-4 7) (f-4-4 #xA) (f-8-1 1) cr16 dst16-16-HI) + (ldc16-sem dst16-16-HI cr16) + ()) +; ldc src,dest (m32c #4) +(dni ldc32.src-cr1 "ldc src,dst" ((machine 32)) + ("ldc ${dst32-24-Prefixed-HI},${cr1-Prefixed-32}") + (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-HI (f-15-1 1) (f-18-2 0) (f-20-1 1) cr1-Prefixed-32) + (ldc32-cr1-sem dst32-24-Prefixed-HI cr1-Prefixed-32) + ()) +; ldc src,dest (m32c #5) +(dni ldc32.src-cr2 "ldc src,dest" ((machine 32)) + ("ldc ${dst32-16-Unprefixed-SI},${cr2-32}") + (+ (f-0-4 #xD) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 0) (f-12-1 0) cr2-32) + (ldc32-cr2-sem dst32-16-Unprefixed-SI cr2-32) + ()) +; ldc src,dest (m32c #6) +(dni ldc32.src-cr3 "ldc src,dst" ((machine 32)) + ("ldc ${dst32-24-Prefixed-SI},${cr3-Prefixed-32}") + (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-SI (f-15-1 1) (f-18-2 0) (f-20-1 0) cr3-Prefixed-32) + (ldc32-cr3-sem dst32-24-Prefixed-SI cr3-Prefixed-32) + ()) +; ldc src,dest (m32c #1) +(dni ldc32.imm16-cr1 "ldc #imm,dst" ((machine 32)) + ("ldc #${Imm-16-HI},${cr1-Unprefixed-32}") + (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32 Imm-16-HI) + (ldc32-cr1-sem Imm-16-HI cr1-Unprefixed-32) + ()) +; ldc src,dest (m32c #2) +(dni ldc32.imm16-cr2 "ldc #imm,dst" ((machine 32)) + ("ldc #${Dsp-16-u24},${cr2-32}") + (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 2) (f-12-1 1) cr2-32 Dsp-16-u24) + (ldc32-cr2-sem Dsp-16-u24 cr2-32) + ()) +; ldc src,dest (m32c #3) +(dni ldc32.imm16-cr3 "ldc #imm,dst" ((machine 32)) + ("ldc #${Dsp-16-u24},${cr3-Unprefixed-32}") + (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 6) (f-12-1 1) cr3-Unprefixed-32 Dsp-16-u24) + (ldc32-cr3-sem Dsp-16-u24 cr3-Unprefixed-32) + ()) + +(dni stc16.src "stc src,dest" ((machine 16)) + ("stc ${cr16},${dst16-16-HI}") + (+ (f-0-4 7) (f-4-4 #xB) (f-8-1 1) cr16 dst16-16-HI) + (stc16-sem cr16 dst16-16-HI ) + ()) + +(dni stc16.pc "stc pc,dest" ((machine 16)) + ("stc pc,${dst16-16-HI}") + (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xC) dst16-16-HI) + (sequence () (set dst16-16-HI (reg h-pc))) + ()) + +(dni stc32.src-cr1 "stc src,dst" ((machine 32)) + ("stc ${cr1-Prefixed-32},${dst32-24-Prefixed-HI}") + (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-HI (f-15-1 1) (f-18-2 1) (f-20-1 1) cr1-Prefixed-32) + (stc32-cr1-sem cr1-Prefixed-32 dst32-24-Prefixed-HI ) + ()) + +(dni stc32.src-cr2 "stc src,dest" ((machine 32)) + ("stc ${cr2-32},${dst32-16-Unprefixed-SI}") + (+ (f-0-4 #xD) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 0) (f-12-1 2) cr2-32) + (stc32-cr2-sem cr2-32 dst32-16-Unprefixed-SI ) + ()) + +(dni stc32.src-cr3 "stc src,dst" ((machine 32)) + ("stc ${cr3-Prefixed-32},${dst32-24-Prefixed-SI}") + (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-SI (f-15-1 1) (f-18-2 1) (f-20-1 0) cr3-Prefixed-32) + (stc32-cr3-sem cr3-Prefixed-32 dst32-24-Prefixed-SI ) + ()) + +;------------------------------------------------------------- +; ldctx - load context +; stctx - store context +;------------------------------------------------------------- + +; ??? semantics +(dni ldctx16 "ldctx abs16,abs24" ((machine 16)) + ("ldctx ${Dsp-16-u16},${Dsp-32-u24}") + (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 #x0) Dsp-16-u16 Dsp-32-u24) + (nop) + ()) +(dni ldctx32 "ldctx abs16,abs24" ((machine 32)) + ("ldctx ${Dsp-16-u16},${Dsp-32-u24}") + (+ (f-0-4 #xB) (f-4-4 #x6) (f-8-4 #xC) (f-12-4 #x3) Dsp-16-u16 Dsp-32-u24) + (nop) + ()) +(dni stctx16 "stctx abs16,abs24" ((machine 16)) + ("stctx ${Dsp-16-u16},${Dsp-32-u24}") + (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 #x0) Dsp-16-u16 Dsp-32-u24) + (nop) + ()) +(dni stctx32 "stctx abs16,abs24" ((machine 32)) + ("stctx ${Dsp-16-u16},${Dsp-32-u24}") + (+ (f-0-4 #xB) (f-4-4 #x6) (f-8-4 #xD) (f-12-4 #x3) Dsp-16-u16 Dsp-32-u24) + (nop) + ()) + +;------------------------------------------------------------- +; lde - load from extra far data area (m16) +; ste - store to extra far data area (m16) +;------------------------------------------------------------- + +; A special variant of mem16 for lde and ste +(define-pmacro (extra-mem16 mode address) + (mem mode (and #xfffff address))) + +(define-pmacro (lde-sem mode src1 dst) + (set mode src1 (extra-mem16 mode dst)) +) +(lde-dst QI .b 0 lde (f-0-4 #x7) (f-4-3 2) (f-8-4 #x8) lde-sem) +(lde-dst HI .w 1 lde (f-0-4 #x7) (f-4-3 2) (f-8-4 #x8) lde-sem) + +(define-pmacro (ste-sem mode src1 dst) + (set (extra-mem16 mode dst) src1) +) +(ste-dst QI .b 0 ste (f-0-4 #x7) (f-4-3 2) (f-8-4 #x0) ste-sem) +(ste-dst HI .w 1 ste (f-0-4 #x7) (f-4-3 2) (f-8-4 #x0) ste-sem) + +;------------------------------------------------------------- +; ldipl - load interrupt permission level +;------------------------------------------------------------- + +; ??? semantics +; ldintb <==> ldc #imm,intbh ; ldc #imm,intbl +(dni ldipl16.imm "ldipl #imm" ((machine 16)) + ("ldipl #${Imm-13-u3}") + (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xA) (f-12-1 0) Imm-13-u3) + (nop) + ()) +(dni ldipl32.imm "ldipl #imm" ((machine 32)) + ("ldipl #${Imm-13-u3}") + (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 #xE) (f-12-1 1) Imm-13-u3) + (nop) + ()) + + +;------------------------------------------------------------- +; max - maximum value +;------------------------------------------------------------- + +; TODO check semantics for min -1,0 +(define-pmacro (max-sem mode src dst) + (sequence () + (if (gt mode src dst) + (set mode dst src))) +) + +; max.size:G #imm,dst +(binary-arith32-imm-dst-Prefixed QI QI .b 0 max X #x8 #x3 #xF max-sem) +(binary-arith32-imm-dst-Prefixed HI HI .w 1 max X #x8 #x3 #xF max-sem) + +; max.BW:G src,dst +(binary-arith32-src-dst-Prefixed QI QI .b 0 max X #x1 #xD max-sem) +(binary-arith32-src-dst-Prefixed HI HI .w 1 max X #x1 #xD max-sem) + +;------------------------------------------------------------- +; min - minimum value +;------------------------------------------------------------- + +(define-pmacro (min-sem mode src dst) + (sequence () + (if (lt mode src dst) + (set mode dst src))) +) + +; min.size:G #imm,dst +(binary-arith32-imm-dst-Prefixed QI QI .b 0 min X #x8 #x2 #xF min-sem) +(binary-arith32-imm-dst-Prefixed HI HI .w 1 min X #x8 #x2 #xF min-sem) + +; min.BW:G src,dst +(binary-arith32-src-dst-Prefixed QI QI .b 0 min X #x1 #xC min-sem) +(binary-arith32-src-dst-Prefixed HI HI .w 1 min X #x1 #xC min-sem) + +;------------------------------------------------------------- +; mov - move +;------------------------------------------------------------- + +(define-pmacro (mov-sem mode src1 dst) + (sequence ((mode result)) + (set result src1) + (set-z-and-s result) + (set mode dst src1)) +) + +(define-pmacro (mov-dspsp-dst-sem mach mode src1 dst) + (set dst (mem-mach mach mode (add sp src1))) +) + +(define-pmacro (mov-src-dspsp-sem mach mode src dst1) + (set (mem-mach mach mode (add sp dst1)) src) +) + +(define-pmacro (mov16-imm-an-defn size mode imm regn op1 op2) + (dni (.sym mov16. size .S-imm- regn) + (.str "mov." size ":S " imm "," regn) + ((machine 16)) + (.str "mov." size "$S #${" imm "}," regn) + (+ op1 op2 imm) + (mov-sem mode imm (reg (.sym h- regn))) + ()) +) +; mov.size:G #imm,dst (m16 #1 m32 #1) +(binary-arith-imm-dst mov G (f-0-4 7) (f-4-3 2) (f-8-4 #xC) #x9 #x2 #xF mov-sem) +; mov.L:G #imm32,dst (m32 #2) +(binary-arith32-imm-dst-defn SI SI .l 0 mov G #xB #x3 #x1 mov-sem) +; mov.BW:S #imm,dst2 (m32 #4) +(binary-arith32-s-imm-dst QI .b 0 mov #x0 #x2 mov-sem) +(binary-arith32-s-imm-dst HI .w 1 mov #x0 #x2 mov-sem) +; mov.b:S #imm8,dst3 (m16 #3) +(binary-arith16-b-S-imm8-dst3 mov ".b" (f-0-4 #xC) (f-4-1 0) mov-sem) +; mov.b:S #imm8,aN (m16 #4) +(mov16-imm-an-defn b QI Imm-8-QI a0 (f-0-4 #xE) (f-4-4 2)) +(mov16-imm-an-defn b QI Imm-8-QI a1 (f-0-4 #xE) (f-4-4 #xA)) +(mov16-imm-an-defn w HI Imm-8-HI a0 (f-0-4 #xA) (f-4-4 2)) +(mov16-imm-an-defn w HI Imm-8-HI a1 (f-0-4 #xA) (f-4-4 #xA)) +; mov.WL:S #imm,A0/A1 (m32 #5) +(define-pmacro (mov32-wl-s-defn mode sz op1 imm regn op2) + (dni (.sym mov32- sz - regn) + (.str "mov." sz ":s" imm "," regn) + ((machine 32)) + (.str "mov." sz "$S #${" imm "}," regn) + (+ (f-0-4 op1) (f-4-4 op2) imm) + (mov-sem mode imm (reg (.sym h- regn))) + ()) +) +(mov32-wl-s-defn HI w #x9 Imm-8-HI a0 #xC) +(mov32-wl-s-defn HI w #x9 Imm-8-HI a1 #xD) +(mov32-wl-s-defn SI l #xB Dsp-8-u24 a0 #xC) +(mov32-wl-s-defn SI l #xB Dsp-8-u24 a1 #xD) + +; mov.size:Q #imm4,dst (m16 #2 m32 #3) +(binary-arith16-imm4-dst-defn QI .b 0 0 mov (f-0-4 #xD) (f-4-3 4) mov-sem) +(binary-arith16-imm4-dst-defn QI .w 0 1 mov (f-0-4 #xD) (f-4-3 4) mov-sem) +(binary-arith32-imm4-dst-defn QI .b 1 0 mov #x7 #x2 mov-sem) +(binary-arith32-imm4-dst-defn HI .w 1 1 mov #x7 #x2 mov-sem) + +; mov.BW:Z #0,dst (m16 #5 m32 #6) +(dni mov16.b-Z-imm8-dst3 + "mov.b:Z #0,Dst16-3-S-8" + ((machine 16)) + "mov.b$Z #0,${Dst16-3-S-8}" + (+ (f-0-4 #xB) (f-4-1 #x0) Dst16-3-S-8) + (mov-sem QI (const 0) Dst16-3-S-8) + ()) +; (binary-arith16-b-Z-imm8-dst3 mov ".b" (f-0-4 #xB) (f-4-1 0) mov-sem) +(binary-arith32-z-imm-dst QI .b 0 mov #x0 #x1 mov-sem) +(binary-arith32-z-imm-dst HI .w 1 mov #x0 #x1 mov-sem) +; mov.BW:G src,dst (m16 #6 m32 #7) +(binary-arith-src-dst mov G (f-0-4 #x7) (f-4-3 1) #x1 #xB mov-sem) +; mov.B:S src2,a0/a1 (m16 #7) +(dni (.sym mov 16 .b.S-An) + (.str mov ".b:S src2,a[01]") + ((machine 16)) + (.str mov ".b$S ${src16-2-S},${Dst16AnQI-S}") + (+ (f-0-4 #x3) (f-4-1 0) Dst16AnQI-S src16-2-S) + (mov-sem QI src16-2-S Dst16AnQI-S) + ()) +(define-pmacro (mov16-b-s-an-defn op1 op2 op2c) + (dni (.sym mov16.b.S- op1 - op2) + (.str mov ".b:S " op1 "," op2) + ((machine 16)) + (.str mov ".b$S " op1 "," op2) + (+ (f-0-4 #x3) op2c) + (mov-sem QI (reg (.sym h- op1)) (reg (.sym h- op2))) + ()) + ) +(mov16-b-s-an-defn r0l a1 (f-4-4 #x4)) +(mov16-b-s-an-defn r0h a0 (f-4-4 #x0)) + +; mov.L:G src,dst (m32 #8) +(binary-arith32-src-dst-defn SI SI .l 1 mov G #x1 #x3 mov-sem) +; mov.B:S r0l/r0h,dst2 (m16 #8) +(dni (.sym mov 16 .b.S-Rn-An) + (.str mov ".b:S r0[lh],src2") + ((machine 16)) + (.str mov ".b$S ${Dst16RnQI-S},${src16-2-S}") + (+ (f-0-4 #x0) (f-4-1 0) Dst16RnQI-S src16-2-S) + (mov-sem QI src16-2-S Dst16RnQI-S) + ()) + +; mov.B.S src2,r0l/r0h (m16 #9) +(binary-arith16-b-S-src2 mov (f-0-4 0) (f-4-1 1) mov-sem) + +; mov.BW:S src2,r0l/r0 (m32 #9) +; mov.BW:S src2,r1l/r1 (m32 #10) +(define-pmacro (mov32-src-r sz szcode mode src dst opc1 opc2) + (begin + (dni (.sym mov32. sz - src - dst) + (.str "mov." sz "src," dst) + ((machine 32)) + (.str "mov." sz "$S ${" (.sym src - mode) "}," dst) + (+ (f-0-2 opc1) (.sym src - mode) (f-4-3 opc2) (f-7-1 szcode)) + (mov-sem mode (.sym src - mode) (reg (.sym h- dst))) + ()) + ) + ) +(mov32-src-r b 0 QI dst32-2-S-16 r0l 0 4) +(mov32-src-r w 1 HI dst32-2-S-16 r0 0 4) +(mov32-src-r b 0 QI dst32-2-S-8 r0l 0 4) +(mov32-src-r w 1 HI dst32-2-S-8 r0 0 4) +(mov32-src-r b 0 QI dst32-2-S-basic r1l 1 7) +(mov32-src-r w 1 HI dst32-2-S-basic r1l 1 7) +(mov32-src-r b 0 QI dst32-2-S-16 r1l 1 7) +(mov32-src-r w 1 HI dst32-2-S-16 r1 1 7) +(mov32-src-r b 0 QI dst32-2-S-8 r1l 1 7) +(mov32-src-r w 1 HI dst32-2-S-8 r1 1 7) + +; mov.BW:S r0l/r0,dst2 (m32 #11) +(define-pmacro (mov32-r-dest sz szcode mode src dst opc1 opc2) + (begin + (dni (.sym mov32. sz - src - dst) + (.str "mov." sz "src," dst) + ((machine 32)) + (.str "mov." sz "$S " src ",${" (.sym dst - mode) "}") + (+ (f-0-2 opc1) (.sym dst - mode) (f-4-3 opc2) (f-7-1 szcode)) + (mov-sem mode (reg (.sym h- src)) (.sym dst - mode)) + ()) + ) + ) +(mov32-r-dest b 0 QI r0l dst32-2-S-16 0 0) +(mov32-r-dest w 1 HI r0 dst32-2-S-16 0 0) +(mov32-r-dest b 0 QI r0l dst32-2-S-8 0 0) +(mov32-r-dest w 1 HI r0 dst32-2-S-8 0 0) + +; mov.L:S src,A0/A1 (m32 #12) +(define-pmacro (mov32-src-a src dst dstcode opc1 opc2) + (begin + (dni (.sym mov32. sz - src - dst) + (.str "mov." sz "src," dst) + ((machine 32)) + (.str "mov.l" "$S ${" (.sym src - SI) "}," dst) + (+ (f-0-2 opc1) (.sym src - SI) (f-4-3 opc2) (f-7-1 dstcode)) + (mov-sem SI (.sym src - SI) (reg (.sym h- dst))) + ()) + ) + ) +(mov32-src-a dst32-2-S-16 a0 0 1 4) +(mov32-src-a dst32-2-S-16 a1 1 1 4) +(mov32-src-a dst32-2-S-8 a0 0 1 4) +(mov32-src-a dst32-2-S-8 a1 1 1 4) + +; mov.BW:G dsp8[sp],dst (m16 #10 m32 #13) +; mov.BW:G src,dsp8[sp] (m16 #11 m32 #14) +(mov-dspsp-dst mov (f-0-4 #x7) (f-4-3 2) (f-8-4 #xB) #xB #x0 #xF mov-dspsp-dst-sem) +(mov-src-dspsp mov (f-0-4 #x7) (f-4-3 2) (f-8-4 #x3) #xA #x0 #xF mov-src-dspsp-sem) + +;------------------------------------------------------------- +; mova - move effective address +;------------------------------------------------------------- + +(define-pmacro (mov16a-defn dst dstop dstcode) + (dni (.sym mova16. src - dst) + (.str "mova src," dst) + ((machine 16)) + (.str "mova ${dst16-16-Mova-HI}," dst) + (+ (f-0-4 #xE) (f-4-4 #xB) dst16-16-Mova-HI (f-8-4 dstcode)) + (sequence () (set HI (reg dstop) dst16-16-Mova-HI)) + ()) +) +(mov16a-defn r0 h-r0 0) +(mov16a-defn r1 h-r1 1) +(mov16a-defn r2 h-r2 2) +(mov16a-defn r3 h-r3 3) +(mov16a-defn a0 h-a0 4) +(mov16a-defn a1 h-a1 5) + +(define-pmacro (mov32a-defn dst dstop dstcode) + (dni (.sym mova32. src - dst) + (.str "mova src," dst) + ((machine 32)) + (.str "mova ${dst32-16-Unprefixed-Mova-SI}," dst) + (+ (f-0-4 #xD) dst32-16-Unprefixed-Mova-SI (f-7-1 1) (f-10-2 1) (f-12-1 1) (f-13-3 dstcode)) + (sequence () (set SI (reg dstop) dst32-16-Unprefixed-Mova-SI)) + ()) +) +(mov32a-defn r2r0 h-r2r0 0) +(mov32a-defn r3r1 h-r3r1 1) +(mov32a-defn a0 h-a0 2) +(mov32a-defn a1 h-a1 3) + +;------------------------------------------------------------- +; movDir - move nibble +;------------------------------------------------------------- + +(define-pmacro (movdir-sem nib src dst) + (sequence ((SI tmp)) + (case DFLT nib + ((0) (set dst (or (and dst #xf0) (and src #xf)))) + ((1) (set dst (or (and dst #x0f) (sll (and src #xf) 4)))) + ((2) (set dst (or (and dst #xf0) (srl (and src #xf0) 4)))) + ((3) (set dst (or (and dst #x0f) (and src #xf0)))) + ) + ) + ) +; movDir src,dst +(define-pmacro (mov16dir-1-defn nib dircode dir) + (dni (.sym mov nib 16 ".r0l-dst") + (.str "mov" nib " r0l,dst") + ((machine 16)) + (.str "mov" nib " r0l,${dst16-16-QI}") + (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 dir) dst16-16-QI) + (movdir-sem dircode (reg h-r0l) dst16-16-QI) + ()) +) +(mov16dir-1-defn ll 0 8) +(mov16dir-1-defn lh 1 #xA) +(mov16dir-1-defn hl 2 9) +(mov16dir-1-defn hh 3 #xB) +(define-pmacro (mov16dir-2-defn nib dircode dir) + (dni (.sym mov nib 16 ".src-r0l") + (.str "mov" nib " src,r0l") + ((machine 16)) + (.str "mov" nib " ${dst16-16-QI},r0l") + (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 dir) dst16-16-QI) + (movdir-sem dircode dst16-16-QI (reg h-r0l)) + ()) +) +(mov16dir-2-defn ll 0 0) +(mov16dir-2-defn lh 1 2) +(mov16dir-2-defn hl 2 1) +(mov16dir-2-defn hh 3 3) + +(define-pmacro (mov32dir-1-defn nib o1o0) + (dni (.sym mov nib 32 ".r0l-dst") + (.str "mov" nib " r0l,dst") + ((machine 32)) + (.str "mov" nib " r0l,${dst32-24-Prefixed-QI}") + (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #xB) dst32-24-Prefixed-QI (f-15-1 0) (f-18-2 o1o0) (f-20-4 #xE)) + (movdir-sem o1o0 (reg h-r0l) dst32-24-Prefixed-QI) + ()) +) +(mov32dir-1-defn ll 0) +(mov32dir-1-defn lh 1) +(mov32dir-1-defn hl 2) +(mov32dir-1-defn hh 3) +(define-pmacro (mov32dir-2-defn nib o1o0) + (dni (.sym mov nib 32 ".src-r0l") + (.str "mov" nib " src,r0l") + ((machine 32)) + (.str "mov" nib " ${dst32-24-Prefixed-QI},r0l") + (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #xA) dst32-24-Prefixed-QI (f-15-1 0) (f-18-2 o1o0) (f-20-4 #xE)) + (movdir-sem o1o0 dst32-24-Prefixed-QI (reg h-r0l)) + ()) +) +(mov32dir-2-defn ll 0) +(mov32dir-2-defn lh 1) +(mov32dir-2-defn hl 2) +(mov32dir-2-defn hh 3) + +;------------------------------------------------------------- +; movx - move extend sign (m32) +;------------------------------------------------------------- + +(define-pmacro (movx-sem mode src dst) + (sequence ((SI source) (SI result)) + (set SI result src) + (set-z-and-s result) + (set dst result)) +) + +; movx #imm,dst +(binary-arith32-imm-dst-defn QI SI "" 0 movx X #xB #x1 #x1 movx-sem) + +;------------------------------------------------------------- +; mul - multiply +;------------------------------------------------------------- + +(define-pmacro (mul-sem mode src1 dst) + (sequence ((mode result)) + (set obit (add-oflag mode src1 dst 0)) + (set result (mul mode src1 dst)) + (set dst result)) +) + +; mul.BW #imm,dst +(binary-arith-imm-dst mul G (f-0-4 7) (f-4-3 6) (f-8-4 5) #x8 #x1 #xF mul-sem) +; mul.BW src,dst +(binary-arith-src-dst mul G (f-0-4 #x7) (f-4-3 4) #x1 #xC mul-sem) + +;------------------------------------------------------------- +; mulex - multiple extend sign (m32) +;------------------------------------------------------------- + +; mulex src,dst +; (dni mulex-absolute-indirect "mulex [src]" ((machine 32)) +; ("mulex ${dst32-24-absolute-indirect-HI}") +; (+ (f-0-4 0) (f-4-4 9) (f-8-4 #xC) dst32-24-absolute-indirect-HI (f-15-1 1) (f-18-2 3) (f-20-4 #xE)) +; (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-24-absolute-indirect-HI))) +; ()) +(dni mulex "mulex src" ((machine 32)) + ("mulex ${dst32-16-Unprefixed-Mulex-HI}") + (+ (f-0-4 #xC) dst32-16-Unprefixed-Mulex-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE)) + (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-16-Unprefixed-Mulex-HI))) + ()) +; (dni mulex-indirect "mulex [src]" ((machine 32)) +; ("mulex ${dst32-24-indirect-HI}") +; (+ (f-0-4 0) (f-4-4 9) (f-8-4 #xC) dst32-24-indirect-HI (f-15-1 1) (f-18-2 3) (f-20-4 #xE)) +; (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-24-indirect-HI))) +; ()) + +;------------------------------------------------------------- +; mulu - multiply unsigned +;------------------------------------------------------------- + +(define-pmacro (mulu-sem mode src1 dst) + (sequence ((mode result)) + (set obit (add-oflag mode src1 dst 0)) + (set result (mul mode src1 dst)) + (set dst result)) +) + +; mulu.BW #imm,dst +(binary-arith-imm-dst mulu G (f-0-4 7) (f-4-3 6) (f-8-4 4) #x8 #x0 #xF mulu-sem) +; mulu.BW src,dst +(binary-arith-src-dst mulu G (f-0-4 #x7) (f-4-3 0) #x1 #x4 mulu-sem) + +;------------------------------------------------------------- +; neg - twos complement +;------------------------------------------------------------- + +(define-pmacro (neg-sem mode dst) + (sequence ((mode result)) + (set result (neg mode dst)) + (set-z-and-s result) + (set dst result)) +) + +; neg.BW:G +(unary-insn neg (f-0-4 7) (f-4-3 2) (f-8-4 #x5) #xA #x2 #xF neg-sem) + +;------------------------------------------------------------- +; not - twos complement +;------------------------------------------------------------- + +(define-pmacro (not-sem mode dst) + (sequence ((mode result)) + (set result (not mode dst)) + (set-z-and-s result) + (set dst result)) +) + +; not.BW:G +(unary-insn not (f-0-4 7) (f-4-3 2) (f-8-4 #x7) #xA #x1 #xE not-sem) + +;------------------------------------------------------------- +; nop +;------------------------------------------------------------- + +(dni nop16 + "nop" + ((machine 16)) + "nop" + (+ (f-0-4 #x0) (f-4-4 #x4)) + (nop) + ()) + +(dni nop32 + "nop" + ((machine 32)) + "nop" + (+ (f-0-4 #xD) (f-4-4 #xE)) + (nop) + ()) + +;------------------------------------------------------------- +; or - logical or +;------------------------------------------------------------- + +(define-pmacro (or-sem mode src1 dst) + (sequence ((mode result)) + (set result (or mode src1 dst)) + (set-z-and-s result) + (set dst result)) +) + +; or.BW #imm,dst (m16 #1 m32 #1) +(binary-arith-imm-dst or G (f-0-4 7) (f-4-3 3) (f-8-4 3) #x8 #x2 #xF or-sem) +; or.b:S #imm8,dst3 (m16 #2 m32 #2) +(binary-arith16-b-S-imm8-dst3 or ".b" (f-0-4 9) (f-4-1 1) or-sem) +(binary-arith32-s-imm-dst QI .b 0 or #x1 #x2 or-sem) +(binary-arith32-s-imm-dst HI .w 1 or #x1 #x2 or-sem) +; or.BW src,dst (m16 #3 m32 #3) +(binary-arith-src-dst or G (f-0-4 #x9) (f-4-3 4) #x1 #x5 or-sem) + +;------------------------------------------------------------- +; pop - restore register/memory +;------------------------------------------------------------- + +; TODO future: split this into .b and .w semantics +(define-pmacro (pop-sem-mach mach mode dst) + (sequence ((mode b_or_w) (SI length)) + (set b_or_w -1) + (set b_or_w (srl b_or_w #x8)) + (if (eq b_or_w #x0) + (set length 1) ; .b + (set length 2)) ; .w + + (case DFLT length + ((1) (set dst (mem-mach mach QI (reg h-sp)))) + ((2) (set dst (mem-mach mach HI (reg h-sp))))) + (set (reg h-sp) (add (reg h-sp) length)) + ) +) + +(define-pmacro (pop-sem16 mode dest) (pop-sem-mach 16 mode dest)) +(define-pmacro (pop-sem32 mode dest) (pop-sem-mach 32 mode dest)) + +; pop.BW:G (m16 #1) +(unary-insn-mach 16 pop (f-0-4 7) (f-4-3 2) (f-8-4 #xD) pop-sem16) +; pop.BW:G (m32 #1) +(unary-insn-mach 32 pop #xB #x2 #xF pop-sem32) + +; pop.b:S r0l/r0h +(dni pop16.b-s-rn "pop.b:S r0[lh]" ((machine 16)) + "pop.b$S ${Rn16-push-S-anyof}" + (+ (f-0-4 #x9) Rn16-push-S-anyof (f-5-3 #x2)) + (pop-sem16 QI Rn16-push-S-anyof) + ()) +; pop.w:S a0/a1 +(dni pop16.b-s-an "pop.w:S a[01]" ((machine 16)) + "pop.w$S ${An16-push-S-anyof}" + (+ (f-0-4 #xD) An16-push-S-anyof (f-5-3 #x2)) + (pop-sem16 HI An16-push-S-anyof) + ()) + +;------------------------------------------------------------- +; popc - pop control register +; pushc - push control register +;------------------------------------------------------------- + +(define-pmacro (popc32-cr1-sem mode dst) + (sequence () + (case DFLT dst + ((#x0) (set (reg h-dct0) (mem32 mode (reg h-sp)))) + ((#x1) (set (reg h-dct1) (mem32 mode (reg h-sp)))) + ((#x2) (sequence ((HI tflag)) + (set tflag (mem32 mode (reg h-sp))) + (if (and tflag #x1) (set cbit 1)) + (if (and tflag #x2) (set dbit 1)) + (if (and tflag #x4) (set zbit 1)) + (if (and tflag #x8) (set sbit 1)) + (if (and tflag #x10) (set bbit 1)) + (if (and tflag #x20) (set obit 1)) + (if (and tflag #x40) (set ibit 1)) + (if (and tflag #x80) (set ubit 1)))) + ((#x3) (set (reg h-svf) (mem32 mode (reg h-sp)))) + ((#x4) (set (reg h-drc0) (mem32 mode (reg h-sp)))) + ((#x5) (set (reg h-drc1) (mem32 mode (reg h-sp)))) + ((#x6) (set (reg h-dmd0) (mem32 mode (reg h-sp)))) + ((#x7) (set (reg h-dmd1) (mem32 mode (reg h-sp)))) + ) + (set (reg h-sp) (add (reg h-sp) 2)) + ) +) +(define-pmacro (popc32-cr2-sem mode dst) + (sequence () + (case DFLT dst + ((#x0) (set (reg h-intb) (mem32 mode (reg h-sp)))) + ((#x1) (set (reg h-sp) (mem32 mode (reg h-sp)))) + ((#x2) (set (reg h-sb) (mem32 mode (reg h-sp)))) + ((#x3) (set (reg h-fb) (mem32 mode (reg h-sp)))) + ((#x7) (set (reg h-isp) (mem32 mode (reg h-sp)))) + ) + (set (reg h-sp) (add (reg h-sp) 4)) + ) +) +(define-pmacro (popc16-sem mode dst) + (sequence () + (case DFLT dst + ((#x1) (set (reg h-intb) (or (and (reg h-intb) #x0000) + (mem16 mode (reg h-sp))))) + ((#x2) (set (reg h-intb) (or (and (reg h-intb) #xffff0000) + (mem16 mode (reg h-sp))))) + ((#x3) (sequence ((HI tflag)) + (set tflag (mem16 mode (reg h-sp))) + (if (and tflag #x1) (set cbit 1)) + (if (and tflag #x2) (set dbit 1)) + (if (and tflag #x4) (set zbit 1)) + (if (and tflag #x8) (set sbit 1)) + (if (and tflag #x10) (set bbit 1)) + (if (and tflag #x20) (set obit 1)) + (if (and tflag #x40) (set ibit 1)) + (if (and tflag #x80) (set ubit 1)))) + ((#x4) (set (reg h-isp) (mem16 mode (reg h-sp)))) + ((#x5) (set (reg h-sp) (mem16 mode (reg h-sp)))) + ((#x6) (set (reg h-sb) (mem16 mode (reg h-sp)))) + ((#x7) (set (reg h-fb) (mem16 mode (reg h-sp)))) + ) + (set (reg h-sp) (add (reg h-sp) 2)) + ) +) +; popc dest (m16c #1) +(dni popc16.imm16 "popc dst" ((machine 16)) + ("popc ${cr16}") + (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 3) cr16) + (popc16-sem HI cr16) + ()) +; popc dest (m32c #1) +(dni popc32.imm16-cr1 "popc dst" ((machine 32)) + ("popc ${cr1-Unprefixed-32}") + (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32) + (popc32-cr1-sem HI cr1-Unprefixed-32) + ()) +; popc dest (m32c #2) +(dni popc32.imm16-cr2 "popc dst" ((machine 32)) + ("popc ${cr2-32}") + (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 2) (f-12-1 1) cr2-32) + (popc32-cr2-sem SI cr2-32) + ()) + +(define-pmacro (pushc32-cr1-sem mode dst) + (sequence () + (set (reg h-sp) (sub (reg h-sp) 2)) + (case DFLT dst + ((#x0) (set (mem32 mode (reg h-sp)) (reg h-dct0))) + ((#x1) (set (mem32 mode (reg h-sp)) (reg h-dct1))) + ((#x2) (sequence ((HI tflag)) + (set tflag 0) + (if (eq cbit 1) (set tflag (or tflag #x1))) + (if (eq dbit 1) (set tflag (or tflag #x2))) + (if (eq zbit 1) (set tflag (or tflag #x4))) + (if (eq sbit 1) (set tflag (or tflag #x8))) + (if (eq bbit 1) (set tflag (or tflag #x10))) + (if (eq obit 1) (set tflag (or tflag #x20))) + (if (eq ibit 1) (set tflag (or tflag #x40))) + (if (eq ubit 1) (set tflag (or tflag #x80))) + (set (mem32 mode (reg h-sp)) tflag))) + ((#x3) (set (mem32 mode (reg h-sp)) (reg h-svf))) + ((#x4) (set (mem32 mode (reg h-sp)) (reg h-drc0))) + ((#x5) (set (mem32 mode (reg h-sp)) (reg h-drc1))) + ((#x6) (set (mem32 mode (reg h-sp)) (reg h-dmd0))) + ((#x7) (set (mem32 mode (reg h-sp)) (reg h-dmd1))) + ) + ) +) +(define-pmacro (pushc32-cr2-sem mode dst) + (sequence () + (set (reg h-sp) (sub (reg h-sp) 4)) + (case DFLT dst + ((#x0) (set (mem32 mode (reg h-sp)) (reg h-intb))) + ((#x1) (set (mem32 mode (reg h-sp)) (reg h-sp))) + ((#x2) (set (mem32 mode (reg h-sp)) (reg h-sb))) + ((#x3) (set (mem32 mode (reg h-sp)) (reg h-fb))) + ((#x7) (set (mem32 mode (reg h-sp)) (reg h-isp))) + ) + ) +) +(define-pmacro (pushc16-sem mode dst) + (sequence () + (set (reg h-sp) (sub (reg h-sp) 2)) + (case DFLT dst + ((#x1) (set (mem16 mode (reg h-sp)) (and (reg h-intb) #xffff))) + ((#x2) (set (mem16 mode (reg h-sp)) (and (reg h-intb) #xffff0000))) + ((#x3) (sequence ((HI tflag)) + (if (eq cbit 1) (set tflag (or tflag #x1))) + (if (eq dbit 1) (set tflag (or tflag #x2))) + (if (eq zbit 1) (set tflag (or tflag #x4))) + (if (eq sbit 1) (set tflag (or tflag #x8))) + (if (eq bbit 1) (set tflag (or tflag #x10))) + (if (eq obit 1) (set tflag (or tflag #x20))) + (if (eq ibit 1) (set tflag (or tflag #x40))) + (if (eq ubit 1) (set tflag (or tflag #x80))) + (set (mem16 mode (reg h-sp)) tflag))) + + ((#x4) (set (mem16 mode (reg h-sp)) (reg h-isp))) + ((#x5) (set (mem16 mode (reg h-sp)) (reg h-sp))) + ((#x6) (set (mem16 mode (reg h-sp)) (reg h-sb))) + ((#x7) (set (mem16 mode (reg h-sp)) (reg h-fb))) + ) + ) +) +; pushc src (m16c) +(dni pushc16.imm16 "pushc dst" ((machine 16)) + ("pushc ${cr16}") + (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 2) cr16) + (pushc16-sem HI cr16) + ()) +; pushc src (m32c #1) +(dni pushc32.imm16-cr1 "pushc dst" ((machine 32)) + ("pushc ${cr1-Unprefixed-32}") + (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32) + (pushc32-cr1-sem HI cr1-Unprefixed-32) + ()) +; pushc src (m32c #2) +(dni pushc32.imm16-cr2 "pushc dst" ((machine 32)) + ("pushc ${cr2-32}") + (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 2) (f-12-1 1) cr2-32) + (pushc32-cr2-sem SI cr2-32) + ()) + +;------------------------------------------------------------- +; popm - pop multiple +; pushm - push multiple +;------------------------------------------------------------- + +(define-pmacro (popm-sem machine dst) + (sequence ((SI addrlen)) + (if (eq machine 16) + (set addrlen 2) + (set addrlen 4)) + (if (and dst 1) + (sequence () (set R0 (mem-mach machine HI (reg h-sp))) + (set (reg h-sp) (add (reg h-sp) 2)))) + (if (and dst 2) + (sequence () (set R1 (mem-mach machine HI (reg h-sp))) + (set (reg h-sp) (add (reg h-sp) 2)))) + (if (and dst 4) + (sequence () (set R2 (mem-mach machine HI (reg h-sp))) + (set (reg h-sp) (add (reg h-sp) 2)))) + (if (and dst 8) + (sequence () (set R3 (mem-mach machine HI (reg h-sp))) + (set (reg h-sp) (add (reg h-sp) 2)))) + (if (and dst 16) + (sequence () (set A0 (mem-mach machine HI (reg h-sp))) + (set (reg h-sp) (add (reg h-sp) addrlen)))) + (if (and dst 32) + (sequence () (set A1 (mem-mach machine HI (reg h-sp))) + (set (reg h-sp) (add (reg h-sp) addrlen)))) + (if (and dst 64) + (sequence () (set (reg h-sb) (mem-mach machine HI (reg h-sp))) + (set (reg h-sp) (add (reg h-sp) addrlen)))) + (if (eq dst 128) + (sequence () (set (reg h-fb) (mem-mach machine HI (reg h-sp))) + (set (reg h-sp) (add (reg h-sp) addrlen)))) + ) +) + +(define-pmacro (pushm-sem machine dst) + (sequence ((SI count) (SI addrlen)) + (if (eq machine 16) + (set addrlen 2) + (set addrlen 4)) + (if (eq dst 1) + (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen)) + (set (mem-mach machine HI (reg h-sp)) (reg h-fb)))) + (if (and dst 2) + (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen)) + (set (mem-mach machine HI (reg h-sp)) (reg h-sb)))) + (if (and dst 4) + (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen)) + (set (mem-mach machine HI (reg h-sp)) A1))) + (if (and dst 8) + (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen)) + (set (mem-mach machine HI (reg h-sp)) A0))) + (if (and dst 16) + (sequence () (set (reg h-sp) (sub (reg h-sp) 2)) + (set (mem-mach machine HI (reg h-sp)) R3))) + (if (and dst 32) + (sequence () (set (reg h-sp) (sub (reg h-sp) 2)) + (set (mem-mach machine HI (reg h-sp)) R2))) + (if (and dst 64) + (sequence () (set (reg h-sp) (sub (reg h-sp) 2)) + (set (mem-mach machine HI (reg h-sp)) R1))) + (if (and dst 128) + (sequence () (set (reg h-sp) (sub (reg h-sp) 2)) + (set (mem-mach machine HI (reg h-sp)) R0))) + ) +) + +(dni popm16 "popm regs" ((machine 16)) + ("popm ${Regsetpop}") + (+ (f-0-4 #xE) (f-4-4 #xD) Regsetpop) + (popm-sem 16 Regsetpop) + ()) +(dni pushm16 "pushm regs" ((machine 16)) + ("pushm ${Regsetpush}") + (+ (f-0-4 #xE) (f-4-4 #xC) Regsetpush) + (pushm-sem 16 Regsetpush) + ()) +(dni popm "popm regs" ((machine 32)) + ("popm ${Regsetpop}") + (+ (f-0-4 #x8) (f-4-4 #xE) Regsetpop) + (popm-sem 32 Regsetpop) + ()) +(dni pushm "pushm regs" ((machine 32)) + ("pushm ${Regsetpush}") + (+ (f-0-4 #x8) (f-4-4 #xF) Regsetpush) + (pushm-sem 32 Regsetpush) + ()) + +;------------------------------------------------------------- +; push - Save register/memory/immediate data +;------------------------------------------------------------- + +; TODO future: split this into .b and .w semantics +(define-pmacro (push-sem-mach mach mode dst) + (sequence ((mode b_or_w) (SI length)) + (set b_or_w -1) + (set b_or_w (srl b_or_w #x8)) + (if (eq b_or_w #x0) + (set length 1) ; .b + (if (eq b_or_w #xff) + (set length 2) ; .w + (set length 4))) ; .l + (set (reg h-sp) (sub (reg h-sp) length)) + (case DFLT length + ((1) (set (mem-mach mach QI (reg h-sp)) dst)) + ((2) (set (mem-mach mach HI (reg h-sp)) dst)) + ((4) (set (mem-mach mach SI (reg h-sp)) dst))) + ) + ) + +(define-pmacro (push-sem16 mode dst) (push-sem-mach 16 mode dst)) +(define-pmacro (push-sem32 mode dst) (push-sem-mach 32 mode dst)) + +; push.BW:G imm (m16 #1 m32 #1) +(dni push16.b.G-imm "push.b:G #Imm-16-QI" ((machine 16)) + ("push.b$G #${Imm-16-QI}") + (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 2) Imm-16-QI) + (push-sem16 QI Imm-16-QI) + ()) + +(dni push16.w.G-imm "push.w:G #Imm-16-HI" ((machine 16)) + ("push.w$G #${Imm-16-HI}") + (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 2) Imm-16-HI) + (push-sem16 HI Imm-16-HI) + ()) + +(dni push32.b.imm "push.w #Imm-8-QI" ((machine 32)) + ("push.b #Imm-8-QI") + (+ (f-0-4 #xA) (f-4-4 #xE) Imm-8-QI) + (push-sem32 QI Imm-8-QI) + ()) + +(dni push32.w.imm "push.w #Imm-8-HI" ((machine 32)) + ("push.w #${Imm-8-HI}") + (+ (f-0-4 #xA) (f-4-4 #xF) Imm-8-HI) + (push-sem32 HI Imm-8-HI) + ()) + +; push.BW:G src (m16 #2) +(unary-insn-mach 16 push (f-0-4 7) (f-4-3 2) (f-8-4 #x4) push-sem16) +; push.BW:G src (m32 #2) +(unary-insn-mach 32 push #xC #x0 #xE push-sem32) + + +; push.b:S r0l/r0h (m16 #3) +(dni push16.b-s-rn "push.b:S r0[lh]" ((machine 16)) + "push.b$S ${Rn16-push-S-anyof}" + (+ (f-0-4 #x8) Rn16-push-S-anyof (f-5-3 #x2)) + (push-sem16 QI Rn16-push-S-anyof) + ()) +; push.w:S a0/a1 (m16 #4) +(dni push16.b-s-an "push.w:S a[01]" ((machine 16)) + "push.w$S ${An16-push-S-anyof}" + (+ (f-0-4 #xC) An16-push-S-anyof (f-5-3 #x2)) + (push-sem16 HI An16-push-S-anyof) + ()) + +; push.l imm32 (m32 #3) +(dni push32.l.imm "push.l #Imm-16-SI" ((machine 32)) + ("push.l #${Imm-16-SI}") + (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 5) (f-12-4 3) Imm-16-SI) + (push-sem32 SI Imm-16-SI) + ()) +; push.l src (m32 #4) +(unary-insn-defn 32 16-Unprefixed SI .l push (+ (f-0-4 #xA) (f-7-1 0) dst32-16-Unprefixed-SI (f-10-2 0) (f-12-4 1)) push-sem32) + +;------------------------------------------------------------- +; pusha - push effective address +;------------------------------------------------------------ + +(define-pmacro (push16a-sem mode dst) + (sequence () + (set (reg h-sp) (sub (reg h-sp) 2)) + (set (mem16 HI (reg h-sp)) dst)) +) +(define-pmacro (push32a-sem mode dst) + (sequence () + (set (reg h-sp) (sub (reg h-sp) 4)) + (set (mem32 SI (reg h-sp)) dst)) +) +(unary-insn-defn 16 16-Mova HI "" pusha (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 9) dst16-16-Mova-HI) push16a-sem) +(unary-insn-defn 32 16-Unprefixed-Mova SI "" pusha (+ (f-0-4 #xB) (f-7-1 0) dst32-16-Unprefixed-Mova-SI (f-10-2 0) (f-12-4 1)) push32a-sem) + +;------------------------------------------------------------- +; reit - return from interrupt +;------------------------------------------------------------- + +; ??? semantics +(dni reit16 "REIT" ((machine 16)) + ("reit") + (+ (f-0-4 #xF) (f-4-4 #xB)) + (nop) + ()) +(dni reit32 "REIT" ((machine 32)) + ("reit") + (+ (f-0-4 9) (f-4-4 #xE)) + (nop) + ()) + +;------------------------------------------------------------- +; rmpa - repeat multiple and addition +;------------------------------------------------------------- + +; TODO semantics +(dni rmpa16.b "rmpa.size" ((machine 16)) + ("rmpa.b") + (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 1)) + (nop) + ()) +(dni rmpa16.w "rmpa.size" ((machine 16)) + ("rmpa.w") + (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 1)) + (nop) + ()) +(dni rmpa32.b "rmpa.size" ((machine 32)) + ("rmpa.b") + (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 4) (f-12-4 3)) + (nop) + ()) + +(dni rmpa32.w "rmpa.size" ((machine 32)) + ("rmpa.w") + (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 5) (f-12-4 3)) + (nop) + ()) + +;------------------------------------------------------------- +; rolc - rotate left with carry +;------------------------------------------------------------- + +; TODO check semantics +; TODO future: split this into .b and .w semantics +(define-pmacro (rolc-sem mode dst) + (sequence ((mode result) (SI ocbit) (mode b_or_w) (USI mask)) + (set b_or_w -1) + (set b_or_w (srl b_or_w #x8)) + (if (eq b_or_w #x0) + (set mask #x8000) ; .b + (set mask #x80000000)) ; .w + (set ocbit cbit) + (set cbit (and dst mask)) + (set result (sll mode dst 1)) + (set result (or result ocbit)) + (set-z-and-s result) + (set dst result)) +) +; rolc.BW src,dst +(unary-insn rolc (f-0-4 7) (f-4-3 3) (f-8-4 #xA) #xB #x2 #xE rolc-sem) + +;------------------------------------------------------------- +; rorc - rotate right with carry +;------------------------------------------------------------- + +; TODO check semantics +; TODO future: split this into .b and .w semantics +(define-pmacro (rorc-sem mode dst) + (sequence ((mode result) (SI ocbit) (mode b_or_w) (USI mask) (SI shamt)) + (set b_or_w -1) + (set b_or_w (srl b_or_w #x8)) + (if (eq b_or_w #x0) + (sequence () (set mask #x7fff) (set shamt 15)) ; .b + (sequence () (set mask #x7fffffff) (set shamt 31))) ; .w + (set ocbit cbit) + (set cbit (and dst #x1)) + (set result (srl mode dst (const 1))) + (set result (or (and result mask) (sll ocbit shamt))) + (set-z-and-s result) + (set dst result)) +) +; rorc.BW src,dst +(unary-insn rorc (f-0-4 7) (f-4-3 3) (f-8-4 #xB) #xA #x2 #xE rorc-sem) + +;------------------------------------------------------------- +; rot - rotate +;------------------------------------------------------------- + +; TODO future: split this into .b and .w semantics +(define-pmacro (rot-1-sem mode src1 dst) + (sequence ((mode tmp) (mode b_or_w) (USI mask) (SI shift)) + (case DFLT src1 + ((#x0) (set shift 1)) + ((#x1) (set shift 2)) + ((#x2) (set shift 3)) + ((#x3) (set shift 4)) + ((#x4) (set shift 5)) + ((#x5) (set shift 6)) + ((#x6) (set shift 7)) + ((#x7) (set shift 8)) + ((-8) (set shift -1)) + ((-7) (set shift -2)) + ((-6) (set shift -3)) + ((-5) (set shift -4)) + ((-4) (set shift -5)) + ((-3) (set shift -6)) + ((-2) (set shift -7)) + ((-1) (set shift -8)) + (else (set shift 0)) + ) + (set b_or_w -1) + (set b_or_w (srl b_or_w #x8)) + (if (eq b_or_w #x0) + (set mask #x7fff) ; .b + (set mask #x7fffffff)) ; .w + (set tmp dst) + (if (gt mode shift 0) + (sequence () + (set tmp (rol mode tmp shift)) + (set cbit (and tmp #x1))) + (sequence () + (set tmp (ror mode tmp (mul shift -1))) + (set cbit (and tmp mask)))) + (set-z-and-s tmp) + (set dst tmp)) +) +(define-pmacro (rot-2-sem mode dst) + (sequence ((mode tmp) (mode b_or_w) (USI mask)) + (set b_or_w -1) + (set b_or_w (srl b_or_w #x8)) + (if (eq b_or_w #x0) + (set mask #x7fff) ; .b + (set mask #x7fffffff)) ; .w + (set tmp dst) + (if (gt mode (reg h-r1h) 0) + (sequence () + (set tmp (rol mode tmp (reg h-r1h))) + (set cbit (and tmp #x1))) + (sequence () + (set tmp (ror mode tmp (reg h-r1h))) + (set cbit (and tmp mask)))) + (set-z-and-s tmp) + (set dst tmp)) +) + +; rot.BW #imm4,dst +(binary-arith16-shimm4-dst-defn QI .b 0 0 rot (f-0-4 #xE) (f-4-3 0) rot-1-sem) +(binary-arith16-shimm4-dst-defn HI .w 0 1 rot (f-0-4 #xE) (f-4-3 0) rot-1-sem) +(binary-arith32-shimm4-dst-defn QI .b 0 0 rot #x7 #x2 rot-1-sem) +(binary-arith32-shimm4-dst-defn HI .w 0 1 rot #x7 #x2 rot-1-sem) +; rot.BW src,dst + +(dni rot16.b-dst "rot r1h,dest" ((machine 16)) + ("rot.b r1h,${dst16-16-HI}") + (+ (f-0-4 7) (f-4-4 #x4) (f-8-4 #x6) dst16-16-HI) + (rot-2-sem QI dst16-16-HI) + ()) +(dni rot16.w-dst "rot r1h,dest" ((machine 16)) + ("rot.w r1h,${dst16-16-HI}") + (+ (f-0-4 7) (f-4-4 #x5) (f-8-4 #x6) dst16-16-HI) + (rot-2-sem HI dst16-16-HI) + ()) + +(dni rot32.b-dst "rot r1h,dest" ((machine 32)) + ("rot.b r1h,${dst32-16-Unprefixed-SI}") + (+ (f-0-4 #xA) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 3) (f-12-4 #xF)) + (rot-2-sem QI dst32-16-Unprefixed-SI) + ()) +(dni rot32.w-dst "rot r1h,dest" ((machine 32)) + ("rot.w r1h,${dst32-16-Unprefixed-SI}") + (+ (f-0-4 #xA) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 3) (f-12-4 #xF)) + (rot-2-sem HI dst32-16-Unprefixed-SI) + ()) + +;------------------------------------------------------------- +; rts - return from subroutine +;------------------------------------------------------------- + +(define-pmacro (rts16-sem) + (sequence ((SI tpc)) + (set tpc (mem16 HI (reg h-sp))) + (set (reg h-sp) (add (reg h-sp) 2)) + (set tpc (or tpc (sll (mem16 QI (reg h-sp)) 16))) + (set (reg h-sp) (add (reg h-sp) 1)) + (set pc tpc) + ) +) +(define-pmacro (rts32-sem) + (sequence ((SI tpc)) + (set tpc (mem32 HI (reg h-sp))) + (set (reg h-sp) (add (reg h-sp) 2)) + (set tpc (or tpc (sll (mem32 HI (reg h-sp)) 16))) + (set (reg h-sp) (add (reg h-sp) 2)) + (set pc tpc) + ) +) + +(dni rts16 "rts" ((machine 16)) + ("rts") + (+ (f-0-4 #xF) (f-4-4 3)) + (rts16-sem) + ()) + +(dni rts32 "rts" ((machine 32)) + ("rts") + (+ (f-0-4 #xD) (f-4-4 #xF)) + (rts32-sem) + ()) + +;------------------------------------------------------------- +; sbb - subtract with borrow +;------------------------------------------------------------- + +(define-pmacro (sbb-sem mode src dst) + (sequence ((mode result)) + (set result (subc mode dst src cbit)) + (set obit (add-oflag mode dst src cbit)) + (set cbit (add-oflag mode dst src cbit)) + (set-z-and-s result) + (set dst result)) +) + +; sbb.size:G #imm,dst +(binary-arith16-imm-dst-defn QI QI .b 0 sbb X (f-0-4 7) (f-4-3 3) (f-8-4 7) sbb-sem) +(binary-arith16-imm-dst-defn HI HI .w 1 sbb X (f-0-4 7) (f-4-3 3) (f-8-4 7) sbb-sem) +(binary-arith32-imm-dst-Prefixed QI QI .b 0 sbb X #x9 #x2 #xE sbb-sem) +(binary-arith32-imm-dst-Prefixed HI HI .w 1 sbb X #x9 #x2 #xE sbb-sem) + +; sbb.BW:G src,dst +(binary-arith16-src-dst-defn QI QI .b 0 sbb X (f-0-4 #xB) (f-4-3 4) sbb-sem) +(binary-arith16-src-dst-defn HI HI .w 1 sbb X (f-0-4 #xB) (f-4-3 4) sbb-sem) +(binary-arith32-src-dst-Prefixed QI QI .b 0 sbb X #x1 #x6 sbb-sem) +(binary-arith32-src-dst-Prefixed HI HI .w 1 sbb X #x1 #x6 sbb-sem) + +;------------------------------------------------------------- +; sbjnz - subtract then jump on not zero +;------------------------------------------------------------- + +(define-pmacro (sub-jnz-sem mode src dst label) + (sequence ((mode result)) + (set result (sub mode dst src)) + (set dst result) + (if (ne result 0) + (set pc label))) +) + +; sbjnz.size #imm4,dst,label +(arith-jnz-imm4-dst sbjnz (f-0-4 #xF) (f-4-3 4) #xf #x1 sub-jnz-sem) + +;------------------------------------------------------------- +; sccnd - store condition on condition (m32) +;------------------------------------------------------------- + +(define-pmacro (sccnd-sem cnd dst) + (sequence () + (set dst 0) + (case DFLT cnd + ((#x00) (if (not cbit) (set dst 1))) ;ltu nc + ((#x01) (if (or cbit zbit) (set dst 1))) ;leu + ((#x02) (if (not zbit) (set dst 1))) ;ne nz + ((#x03) (if (not sbit) (set dst 1))) ;pz + ((#x04) (if (not obit) (set dst 1))) ;no + ((#x05) (if (not (or zbit (xor sbit obit))) (set dst 1))) ;gt + ((#x06) (if (xor sbit obit) (set dst 1))) ;ge + ((#x08) (if (trunc BI cbit) (set dst 1))) ;geu c + ((#x09) (if (not (or cbit zbit)) (set dst 1))) ;gtu + ((#x0a) (if (trunc BI zbit) (set dst 1))) ;eq z + ((#x0b) (if (trunc BI sbit) (set dst 1))) ;n + ((#x0c) (if (trunc BI obit) (set dst 1))) ;o + ((#x0d) (if (or zbit (xor sbit obit)) (set dst 1))) ;le + ((#x0e) (if (xor sbit obit) (set dst 1))) ;lt + ) + ) + ) + +; scCND dst +(dni sccnd + "sccnd dst" + ((machine 32)) + "sc$sccond32 ${dst32-16-Unprefixed-HI}" + (+ (f-0-4 #xD) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) sccond32) + (sccnd-sem sccond32 dst32-16-Unprefixed-HI) + ()) + +;------------------------------------------------------------- +; scmpu - string compare unequal (m32) +;------------------------------------------------------------- + +; TODO semantics +(dni scmpu.b "scmpu.b" ((machine 32)) + ("scmpu.b") + (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 #xC) (f-12-4 3)) + (c-call VOID "scmpu_QI_semantics") + ()) + +(dni scmpu.w "scmpu.w" ((machine 32)) + ("scmpu.w") + (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 #xD) (f-12-4 3)) + (c-call VOID "scmpu_HI_semantics") + ()) + +;------------------------------------------------------------- +; sha - shift arithmetic +;------------------------------------------------------------- + +; TODO future: split this into .b and .w semantics +(define-pmacro (sha-sem mode src1 dst) + (sequence ((mode result)(mode shift)(mode shmode)) + (case DFLT src1 + ((#x0) (set shift 1)) + ((#x1) (set shift 2)) + ((#x2) (set shift 3)) + ((#x3) (set shift 4)) + ((#x4) (set shift 5)) + ((#x5) (set shift 6)) + ((#x6) (set shift 7)) + ((#x7) (set shift 8)) + ((-8) (set shift -1)) + ((-7) (set shift -2)) + ((-6) (set shift -3)) + ((-5) (set shift -4)) + ((-4) (set shift -5)) + ((-3) (set shift -6)) + ((-2) (set shift -7)) + ((-1) (set shift -8)) + (else (set shift 0)) + ) + (set shmode -1) + (set shmode (srl shmode #x8)) + (if (lt mode shift #x0) (set result (sra mode dst (mul shift -1)))) + (if (gt mode shift 0) (set result (sll mode dst shift))) + (if (eq shmode #x0) ; QI + (sequence + ((mode cbitamt)) + (if (lt mode shift #x0) + (set cbitamt (sub #x8 shift)) ; sra + (set cbitamt (sub shift 1))) ; sll + (set cbit (srl (and (sll dst cbitamt) #x80) #x7)) + (set obit (ne (and dst #x80) (and result #x80))) + )) + (if (eq shmode #xff) ; HI + (sequence + ((mode cbitamt)) + (if (lt mode shift #x0) + (set cbitamt (sub 16 shift)) ; sra + (set cbitamt (sub shift 1))) ; sll + (set cbit (srl (and (sll dst cbitamt) #x8000) #xf)) + (set obit (ne (and dst #x8000) (and result #x8000))) + )) + (set-z-and-s result) + (set dst result)) +) +(define-pmacro (shar1h-sem mode dst) + (sequence ((mode result)(mode shmode)) + (set shmode -1) + (set shmode (srl shmode #x8)) + (if (lt mode (reg h-r1h) 0) (set result (sra mode dst (reg h-r1h)))) + (if (gt mode (reg h-r1h) 0) (set result (sll mode dst (reg h-r1h)))) + (if (eq shmode #x0) ; QI + (sequence + ((mode cbitamt)) + (if (lt mode (reg h-r1h) #x0) + (set cbitamt (sub #x8 (reg h-r1h))) ; sra + (set cbitamt (sub (reg h-r1h) 1))) ; sll + (set cbit (srl (and (sll dst cbitamt) #x80) #x7)) + (set obit (ne (and dst #x80) (and result #x80))) + )) + (if (eq shmode #xff) ; HI + (sequence + ((mode cbitamt)) + (if (lt mode (reg h-r1h) #x0) + (set cbitamt (sub 16 (reg h-r1h))) ; sra + (set cbitamt (sub (reg h-r1h) 1))) ; sll + (set cbit (srl (and (sll dst cbitamt) #x8000) #xf)) + (set obit (ne (and dst #x8000) (and result #x8000))) + )) + (set-z-and-s result) + (set dst result)) +) +; sha.BW #imm4,dst (m16 #1 m32 #1) +(binary-arith16-shimm4-dst-defn QI .b 0 0 sha (f-0-4 #xF) (f-4-3 0) sha-sem) +(binary-arith16-shimm4-dst-defn HI .w 0 1 sha (f-0-4 #xF) (f-4-3 0) sha-sem) +(binary-arith32-shimm4-dst-defn QI .b 1 0 sha #x7 #x0 sha-sem) +(binary-arith32-shimm4-dst-defn HI .w 1 1 sha #x7 #x0 sha-sem) +; sha.BW r1h,dst (m16 #2 m32 #3) +(dni sha16.b-dst "sha.b r1h,dest" ((machine 16)) + ("sha.b r1h,${dst16-16-QI}") + (+ (f-0-4 7) (f-4-4 4) (f-8-4 #xF) dst16-16-QI) + (shar1h-sem HI dst16-16-QI) + ()) +(dni sha16.w-dst "sha.w r1h,dest" ((machine 16)) + ("sha.w r1h,${dst16-16-HI}") + (+ (f-0-4 7) (f-4-4 5) (f-8-4 #xF) dst16-16-HI) + (shar1h-sem HI dst16-16-HI) + ()) +(dni sha32.b-dst "sha.b r1h,dest" ((machine 32)) + ("sha.b r1h,${dst32-16-Unprefixed-QI}") + (+ (f-0-4 #xB) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xE)) + (shar1h-sem QI dst32-16-Unprefixed-QI) + ()) +(dni sha32.w-dst "sha.w r1h,dest" ((machine 32)) + ("sha.w r1h,${dst32-16-Unprefixed-HI}") + (+ (f-0-4 #xB) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE)) + (shar1h-sem HI dst32-16-Unprefixed-HI) + ()) +; sha.L #imm,dst (m16 #3) +(dni sha16-L-imm-r2r0 "sha.L #Imm-sh-12-s4,r2r0" ((machine 16)) + "sha.l #${Imm-sh-12-s4},r2r0" + (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #xA) Imm-sh-12-s4) + (sha-sem SI Imm-sh-12-s4 (reg h-r2r0)) + ()) +(dni sha16-L-imm-r3r1 "sha.L #Imm-sh-12-s4,r3r1" ((machine 16)) + "sha.l #${Imm-sh-12-s4},r3r1" + (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #xB) Imm-sh-12-s4) + (sha-sem SI Imm-sh-12-s4 (reg h-r3r1)) + ()) +; sha.L r1h,dst (m16 #4) +(dni sha16-L-r1h-r2r0 "sha.L r1h,r2r0" ((machine 16)) + "sha.l r1h,r2r0" + (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 2) (f-12-4 1)) + (sha-sem SI (reg h-r1h) (reg h-r2r0)) + ()) +(dni sha16-L-r1h-r3r1 "sha.L r1h,r3r1" ((machine 16)) + "sha.l r1h,r3r1" + (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 3) (f-12-4 1)) + (sha-sem SI (reg h-r1h) (reg h-r3r1)) + ()) +; sha.L #imm8,dst (m32 #2) +(binary-arith32-imm-dst-defn QI SI .l 0 sha X #xA #x2 #x1 sha-sem) +; sha.L r1h,dst (m32 #4) +(dni sha32.l-dst "sha.l r1h,dest" ((machine 32)) + ("sha.l r1h,${dst32-16-Unprefixed-SI}") + (+ (f-0-4 #xC) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 1) (f-12-4 1)) + (shar1h-sem QI dst32-16-Unprefixed-SI) + ()) + +;------------------------------------------------------------- +; shanc - shift arithmetic non carry (m32) +;------------------------------------------------------------- + +; TODO check semantics +; shanc.L #imm8,dst +(binary-arith32-imm-dst-defn QI SI .l 0 shanc X #xC #x2 #x1 sha-sem) + +;------------------------------------------------------------- +; shl - shift logical +;------------------------------------------------------------- + +; TODO future: split this into .b and .w semantics +(define-pmacro (shl-sem mode src1 dst) + (sequence ((mode result)(mode shift)(mode shmode)) + (case DFLT src1 + ((#x0) (set shift 1)) + ((#x1) (set shift 2)) + ((#x2) (set shift 3)) + ((#x3) (set shift 4)) + ((#x4) (set shift 5)) + ((#x5) (set shift 6)) + ((#x6) (set shift 7)) + ((#x7) (set shift 8)) + ((-8) (set shift -1)) + ((-7) (set shift -2)) + ((-6) (set shift -3)) + ((-5) (set shift -4)) + ((-4) (set shift -5)) + ((-3) (set shift -6)) + ((-2) (set shift -7)) + ((-1) (set shift -8)) + (else (set shift 0)) + ) + (set shmode -1) + (set shmode (srl shmode #x8)) + (if (lt mode shift #x0) (set result (srl mode dst (mul shift -1)))) + (if (gt mode shift 0) (set result (sll mode dst shift))) + (if (eq shmode #x0) ; QI + (sequence + ((mode cbitamt)) + (if (lt mode shift #x0) + (set cbitamt (sub #x8 shift)); srl + (set cbitamt (sub shift 1))) ; sll + (set cbit (srl (and (sll dst cbitamt) #x80) #x7)) + (set obit (ne (and dst #x80) (and result #x80))) + )) + (if (eq shmode #xff) ; HI + (sequence + ((mode cbitamt)) + (if (lt mode shift #x0) + (set cbitamt (sub 16 shift)) ; srl + (set cbitamt (sub shift 1))) ; sll + (set cbit (srl (and (sll dst cbitamt) #x8000) #xf)) + (set obit (ne (and dst #x8000) (and result #x8000))) + )) + (set-z-and-s result) + (set dst result)) + ) +(define-pmacro (shlr1h-sem mode dst) + (sequence ((mode result)(mode shmode)) + (set shmode -1) + (set shmode (srl shmode #x8)) + (if (lt mode (reg h-r1h) 0) (set result (srl mode dst (reg h-r1h)))) + (if (gt mode (reg h-r1h) 0) (set result (sll mode dst (reg h-r1h)))) + (if (eq shmode #x0) ; QI + (sequence + ((mode cbitamt)) + (if (lt mode (reg h-r1h) #x0) + (set cbitamt (sub #x8 (reg h-r1h))) ; srl + (set cbitamt (sub (reg h-r1h) 1))) ; sll + (set cbit (srl (and (sll dst cbitamt) #x80) #x7)) + (set obit (ne (and dst #x80) (and result #x80))) + )) + (if (eq shmode #xff) ; HI + (sequence + ((mode cbitamt)) + (if (lt mode (reg h-r1h) #x0) + (set cbitamt (sub 16 (reg h-r1h))) ; srl + (set cbitamt (sub (reg h-r1h) 1))) ; sll + (set cbit (srl (and (sll dst cbitamt) #x8000) #xf)) + (set obit (ne (and dst #x8000) (and result #x8000))) + )) + (set-z-and-s result) + (set dst result)) + ) +; shl.BW #imm4,dst (m16 #1 m32 #1) +(binary-arith16-shimm4-dst-defn QI .b 0 0 shl (f-0-4 #xE) (f-4-3 4) shl-sem) +(binary-arith16-shimm4-dst-defn HI .w 0 1 shl (f-0-4 #xE) (f-4-3 4) shl-sem) +(binary-arith32-shimm4-dst-defn QI .b 0 0 shl #x7 #x0 shl-sem) +(binary-arith32-shimm4-dst-defn HI .w 0 1 shl #x7 #x0 shl-sem) +; shl.BW r1h,dst (m16 #2 m32 #3) +(dni shl16.b-dst "shl.b r1h,dest" ((machine 16)) + ("shl.b r1h,${dst16-16-QI}") + (+ (f-0-4 7) (f-4-4 4) (f-8-4 #xE) dst16-16-QI) + (shlr1h-sem HI dst16-16-QI) + ()) +(dni shl16.w-dst "shl.w r1h,dest" ((machine 16)) + ("shl.w r1h,${dst16-16-HI}") + (+ (f-0-4 7) (f-4-4 5) (f-8-4 #xE) dst16-16-HI) + (shlr1h-sem HI dst16-16-HI) + ()) +(dni shl32.b-dst "shl.b r1h,dest" ((machine 32)) + ("shl.b r1h,${dst32-16-Unprefixed-QI}") + (+ (f-0-4 #xA) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xE)) + (shlr1h-sem QI dst32-16-Unprefixed-QI) + ()) +(dni shl32.w-dst "shl.w r1h,dest" ((machine 32)) + ("shl.w r1h,${dst32-16-Unprefixed-HI}") + (+ (f-0-4 #xA) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE)) + (shlr1h-sem HI dst32-16-Unprefixed-HI) + ()) +; shl.L #imm,dst (m16 #3) +(dni shl16-L-imm-r2r0 "shl.L #Imm-sh-12-s4,r2r0" ((machine 16)) + "shl.l #${Imm-sh-12-s4},r2r0" + (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #x8) Imm-sh-12-s4) + (shl-sem SI Imm-sh-12-s4 (reg h-r2r0)) + ()) +(dni shl16-L-imm-r3r1 "shl.L #Imm-sh-12-s4,r3r1" ((machine 16)) + "shl.l #${Imm-sh-12-s4},r3r1" + (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #x9) Imm-sh-12-s4) + (shl-sem SI Imm-sh-12-s4 (reg h-r3r1)) + ()) +; shl.L r1h,dst (m16 #4) +(dni shl16-L-r1h-r2r0 "shl.L r1h,r2r0" ((machine 16)) + "shl.l r1h,r2r0" + (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 0) (f-12-4 1)) + (shl-sem SI (reg h-r1h) (reg h-r2r0)) + ()) +(dni shl16-L-r1h-r3r1 "shl.L r1h,r3r1" ((machine 16)) + "shl.l r1h,r3r1" + (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 1) (f-12-4 1)) + (shl-sem SI (reg h-r1h) (reg h-r3r1)) + ()) +; shl.L #imm8,dst (m32 #2) +(binary-arith32-imm-dst-defn QI SI .l 0 shl X #x9 #x2 #x1 shl-sem) +; shl.L r1h,dst (m32 #4) +(dni shl32.l-dst "shl.l r1h,dest" ((machine 32)) + ("shl.l r1h,${dst32-16-Unprefixed-SI}") + (+ (f-0-4 #xC) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 0) (f-12-4 1)) + (shlr1h-sem QI dst32-16-Unprefixed-SI) + ()) + +;------------------------------------------------------------- +; shlnc - shift logical non carry +;------------------------------------------------------------- + +; TODO check semantics +; shlnc.L #imm8,dst +(binary-arith32-imm-dst-defn QI SI .l 0 shlnc X #x8 #x2 #x1 shl-sem) + +;------------------------------------------------------------- +; sin - string input (m32) +;------------------------------------------------------------- + +; TODO semantics +(dni sin32.b "sin" ((machine 32)) + ("sin.b") + (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 8) (f-12-4 3)) + (c-call VOID "sin_QI_semantics") + ()) + +(dni sin32.w "sin" ((machine 32)) + ("sin.w") + (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 9) (f-12-4 3)) + (c-call VOID "sin_HI_semantics") + ()) + +;------------------------------------------------------------- +; smovb - string move backward +;------------------------------------------------------------- + +; TODO semantics +(dni smovb16.b "smovb.b" ((machine 16)) + ("smovb.b") + (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 9)) + (c-call VOID "smovb_QI_semantics") + ()) + +(dni smovb16.w "smovb.w" ((machine 16)) + ("smovb.w") + (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 9)) + (c-call VOID "smovb_HI_semantics") + ()) + +(dni smovb32.b "smovb.b" ((machine 32)) + ("smovb.b") + (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 8) (f-12-4 3)) + (c-call VOID "smovb_QI_semantics") + ()) + +(dni smovb32.w "smovb.w" ((machine 32)) + ("smovb.w") + (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 9) (f-12-4 3)) + (c-call VOID "smovb_HI_semantics") + ()) + +;------------------------------------------------------------- +; smovf - string move forward (m32) +;------------------------------------------------------------- + +; TODO semantics +(dni smovf16.b "smovf.b" ((machine 16)) + ("smovf.b") + (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 8)) + (c-call VOID "smovf_QI_semantics") + ()) + +(dni smovf16.w "smovf.w" ((machine 16)) + ("smovf.w") + (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 8)) + (c-call VOID "smovf_HI_semantics") + ()) + +(dni smovf32.b "smovf.b" ((machine 32)) + ("smovf.b") + (+ (f-0-4 #xB) (f-4-4 0) (f-8-4 8) (f-12-4 3)) + (c-call VOID "smovf_QI_semantics") + ()) + +(dni smovf32.w "smovf.w" ((machine 32)) + ("smovf.w") + (+ (f-0-4 #xB) (f-4-4 0) (f-8-4 9) (f-12-4 3)) + (c-call VOID "smovf_HI_semantics") + ()) + +;------------------------------------------------------------- +; smovu - string move unequal (m32) +;------------------------------------------------------------- + +; TODO semantics +(dni smovu.b "smovu.b" ((machine 32)) + ("smovu.b") + (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 8) (f-12-4 3)) + (c-call VOID "smovu_QI_semantics") + ()) + +(dni smovu.w "smovu.w" ((machine 32)) + ("smovu.w") + (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 9) (f-12-4 3)) + (c-call VOID "smovu_HI_semantics") + ()) + +;------------------------------------------------------------- +; sout - string output (m32) +;------------------------------------------------------------- + +; TODO semantics +(dni sout.b "sout.b" ((machine 32)) + ("sout.b") + (+ (f-0-4 #xB) (f-4-4 4) (f-8-4 8) (f-12-4 3)) + (c-call VOID "sout_QI_semantics") + ()) + +(dni sout.w "sout" ((machine 32)) + ("sout.w") + (+ (f-0-4 #xB) (f-4-4 4) (f-8-4 9) (f-12-4 3)) + (c-call VOID "sout_HI_semantics") + ()) + +;------------------------------------------------------------- +; sstr - string store +;------------------------------------------------------------- + +; TODO semantics +(dni sstr16.b "sstr.b" ((machine 16)) + ("sstr.b") + (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 #xA)) + (c-call VOID "sstr_QI_semantics") + ()) + +(dni sstr16.w "sstr.w" ((machine 16)) + ("sstr.w") + (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 #xA)) + (c-call VOID "sstr_HI_semantics") + ()) + +(dni sstr.b "sstr" ((machine 32)) + ("sstr.b") + (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 0) (f-12-4 3)) + (c-call VOID "sstr_QI_semantics") + ()) + +(dni sstr.w "sstr" ((machine 32)) + ("sstr.w") + (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 1) (f-12-4 3)) + (c-call VOID "sstr_HI_semantics") + ()) + +;------------------------------------------------------------- +; stnz - store on not zero +;------------------------------------------------------------- + +(define-pmacro (stnz-sem mode src dst) + (sequence () + (if (ne zbit (const 1)) + (set dst src))) +) +; stnz #imm8,dst3 (m16) +(binary-arith16-b-S-imm8-dst3 stnz "" (f-0-4 #xD) (f-4-1 0) stnz-sem) +; stnz.BW #imm,dst (m32) +(binary-arith32-imm-dst-defn QI QI .b 0 stnz X #x9 #x1 #xF stnz-sem) +(binary-arith32-imm-dst-defn HI HI .w 1 stnz X #x9 #x1 #xF stnz-sem) + +;------------------------------------------------------------- +; stz - store on zero +;------------------------------------------------------------- + +(define-pmacro (stz-sem mode src dst) + (sequence () + (if (eq zbit (const 1)) + (set dst src))) +) +; stz #imm8,dst3 (m16) +(binary-arith16-b-S-imm8-dst3 stz "" (f-0-4 #xC) (f-4-1 1) stz-sem) +; stz.BW #imm,dst (m32) +(binary-arith32-imm-dst-defn QI QI .b 0 stz X #x9 #x0 #xF stz-sem) +(binary-arith32-imm-dst-defn HI HI .w 1 stz X #x9 #x0 #xF stz-sem) + +;------------------------------------------------------------- +; stzx - store on zero extention +;------------------------------------------------------------- + +(define-pmacro (stzx-sem mode src1 src2 dst) + (sequence () + (if (eq zbit (const 1)) + (set dst src1) + (set dst src2))) + ) +; stzx #imm8,dst3 (m16) +(dni stzx16-imm8-imm8-r0h "stzx #Imm8,#Imm8,r0h" ((machine 16)) + ("stzx #${Imm-8-QI},#${Imm-16-QI},r0h") + (+ (f-0-4 #xD) (f-4-4 #xB) Imm-8-QI Imm-16-QI) + (stzx-sem QI Imm-8-QI Imm-16-QI (reg h-r0h)) + ()) +(dni stzx16-imm8-imm8-r0l "stzx #Imm8,#Imm8,r0l" ((machine 16)) + ("stzx #${Imm-8-QI},#${Imm-16-QI},r0l") + (+ (f-0-4 #xD) (f-4-4 #xC) Imm-8-QI Imm-16-QI) + (stzx-sem QI Imm-8-QI Imm-16-QI (reg h-r0l)) + ()) +(dni stzx16-imm8-imm8-dsp8sb "stzx #Imm8,#Imm8,dsp8[sb]" ((machine 16)) + ("stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[sb]") + (+ (f-0-4 #xD) (f-4-4 #xD) Imm-8-QI Dsp-16-u8 Imm-24-QI) + (stzx-sem QI Imm-8-QI Imm-16-QI (mem16 QI (add (reg h-sb) Dsp-24-u8))) + ()) +(dni stzx16-imm8-imm8-dsp8fb "stzx #Imm8,#Imm8,dsp8[fb]" ((machine 16)) + ("stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[fb]") + (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-u8 Imm-24-QI) + (stzx-sem QI Imm-8-QI Imm-16-QI (mem16 QI (add (reg h-fb) Dsp-24-u8))) + ()) +(dni stzx16-imm8-imm8-abs16 "stzx #Imm8,#Imm8,abs16" ((machine 16)) + ("stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u16") + (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-u16 Imm-32-QI) + (stzx-sem QI Imm-8-QI Imm-32-QI (mem16 QI Dsp-16-u16)) + ()) +; stzx.BW #imm,dst (m32) +(insn-imm1-imm2-dst-Unprefixed stzx #x9 #x3 #xF stzx-sem) + +;------------------------------------------------------------- +; subx - subtract extend (m32) +;------------------------------------------------------------- + +(define-pmacro (subx-sem mode src1 dst) + (sequence ((mode result)) + (set result (sub mode dst (ext mode src1))) + (set obit (sub-oflag mode dst (ext mode src1) 0)) + (set cbit (sub-cflag mode dst (ext mode src1) 0)) + (set dst result) + (set-z-and-s result))) +; subx #imm8,dst +(binary-arith32-imm-dst-defn QI SI "" 0 subx G #x9 #x1 #x1 subx-sem) +; subx src,dst +(binary-arith32-src-dst-defn QI SI "" 0 subx G #x1 #x0 subx-sem) + +;------------------------------------------------------------- +; tst - test +;------------------------------------------------------------- + +(define-pmacro (tst-sem mode src1 dst) + (sequence ((mode result)) + (set result (and mode dst src1)) + (set-z-and-s result)) +) + +; tst.BW #imm,dst (m16 #1 m32 #1) +(binary-arith-imm-dst tst X (f-0-4 7) (f-4-3 3) (f-8-4 0) #x9 #x3 #xE tst-sem) +; tst.BW src,dst (m16 #2 m32 #3) +(binary-arith16-src-dst-defn QI QI .b 0 tst X (f-0-4 #x8) (f-4-3 0) tst-sem) +(binary-arith16-src-dst-defn HI HI .w 1 tst X (f-0-4 #x8) (f-4-3 0) tst-sem) +(binary-arith32-src-dst-Prefixed QI QI .b 0 tst X #x1 #x9 tst-sem) +(binary-arith32-src-dst-Prefixed HI HI .w 1 tst X #x1 #x9 tst-sem) +; tst.BW:S #imm,dst2 (m32 #2) +(binary-arith32-s-imm-dst QI .b 0 tst #x0 #x6 tst-sem) +(binary-arith32-s-imm-dst HI .w 1 tst #x0 #x6 tst-sem) + +;------------------------------------------------------------- +; und - undefined +;------------------------------------------------------------- + +(dni und16 "und" ((machine 16)) + ("und") + (+ (f-0-4 #xF) (f-4-4 #xF)) + (nop) + ()) + +(dni und32 "und" ((machine 32)) + ("und") + (+ (f-0-4 #xF) (f-4-4 #xF)) + (nop) + ()) + +;------------------------------------------------------------- +; wait +;------------------------------------------------------------- + +; ??? semantics +(dni wait16 "wait" ((machine 16)) + ("wait") + (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 3)) + (nop) + ()) + +(dni wait "wait" ((machine 32)) + ("wait") + (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 0) (f-12-4 3)) + (nop) + ()) + +;------------------------------------------------------------- +; xchg - exchange +;------------------------------------------------------------- + +(define-pmacro (xchg-sem mode src dst) + (sequence ((mode result)) + (set result src) + (set src dst) + (set dst result)) + ) +(define-pmacro (xchg16-defn mode sz szc src srcreg) + (dni (.sym xchg16 sz - srcreg) + (.str "xchg" sz "-" srcreg ",dst16-16-" mode) + ((machine 16)) + (.str "xchg." sz " " srcreg ",${dst16-16-" mode "}") + (+ (f-0-4 #x7) (f-4-3 #x5) (f-7-1 szc) (f-8-2 0) (f-10-2 src) (.sym dst16-16- mode)) + (xchg-sem mode (reg (.sym h- srcreg)) (.sym dst16-16- mode)) + ()) +) +(xchg16-defn QI b 0 0 r0l) +(xchg16-defn QI b 0 1 r0h) +(xchg16-defn QI b 0 2 r1l) +(xchg16-defn QI b 0 3 r1h) +(xchg16-defn QI w 1 0 r0) +(xchg16-defn HI w 1 1 r1) +(xchg16-defn HI w 1 2 r2) +(xchg16-defn HI w 1 3 r3) +(define-pmacro (xchg32-defn mode sz szc src srcreg) + (dni (.sym xchg32 sz - srcreg) + (.str "xchg" sz "-" srcreg ",dst32-16-Unprefixed-" mode) + ((machine 32)) + (.str "xchg." sz " " srcreg ",${dst32-16-Unprefixed-" mode "}") + (+ (f-0-4 #xD) (.sym dst32-16-Unprefixed- mode) (f-7-1 szc) (f-10-2 0) (f-12-1 1) (f-13-3 src)) + (xchg-sem mode (reg (.sym h- srcreg)) (.sym dst32-16-Unprefixed- mode)) + ()) +) +(xchg32-defn QI b 0 0 r0l) +(xchg32-defn QI b 0 1 r1l) +(xchg32-defn QI b 0 2 a0) +(xchg32-defn QI b 0 3 a1) +(xchg32-defn QI b 0 4 r0h) +(xchg32-defn QI b 0 5 r1h) +(xchg32-defn HI w 1 0 r0) +(xchg32-defn HI w 1 1 r1) +(xchg32-defn HI w 1 2 a0) +(xchg32-defn HI w 1 3 a1) +(xchg32-defn HI w 1 4 r2) +(xchg32-defn HI w 1 5 r3) + +;------------------------------------------------------------- +; xor - exclusive or +;------------------------------------------------------------- + +(define-pmacro (xor-sem mode src1 dst) + (sequence ((mode result)) + (set result (xor mode src1 dst)) + (set-z-and-s result) + (set dst result)) +) + +; xor.BW #imm,dst (m16 #1 m32 #1) +(binary-arith-imm-dst xor G (f-0-4 7) (f-4-3 3) (f-8-4 1) #x9 #x0 #xE xor-sem) +; xor.BW src,dst (m16 #3 m32 #3) +(binary-arith-src-dst xor G (f-0-4 #x8) (f-4-3 4) #x1 #x9 xor-sem) + +;------------------------------------------------------------- +; Widening +;------------------------------------------------------------- + +(define-pmacro (exts-sem smode dmode src dst) + (set dst (ext dmode (trunc smode src))) +) +(define-pmacro (extz-sem smode dmode src dst) + (set dst (zext dmode (trunc smode src))) +) + +; exts.b dst for m16c +(ext16-defn QI HI .b 0 exts (f-0-4 7) (f-4-3 6) (f-8-4 6) exts-sem) + +; exts.w r0 for m16c +(dni exts16.w-r0 + "exts.w r0" + ((machine 16)) + "exts.w r0" + (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 3)) + (exts-sem HI SI R0 R2R0) + ()) + +; exts.size dst for m32c +(ext32-defn QI HI .b 0 exts (f-0-4 #xC) (f-10-2 1) (f-12-4 #xE) exts-sem) +(ext32-defn HI SI .w 1 exts (f-0-4 #xC) (f-10-2 1) (f-12-4 #xE) exts-sem) +; exts.b src,dst for m32c +(ext32-binary-defn exts .b #x1 #x7 exts-sem) + +; extz.b src,dst for m32c +(ext32-binary-defn extz "" #x1 #xB extz-sem) + +;------------------------------------------------------------- +; Indirect +;------------------------------------------------------------- + +; TODO semantics +(dni srcind "SRC-INDIRECT" ((machine 32)) + ("src-indirect") + (+ (f-0-4 4) (f-4-4 1)) + (set (reg h-src-indirect) 1) + ()) + +(dni destind "DEST-INDIRECT" ((machine 32)) + ("dest-indirect") + (+ (f-0-4 0) (f-4-4 9)) + (set (reg h-dst-indirect) 1) + ()) + +(dni srcdestind "SRC-DEST-INDIRECT" ((machine 32)) + ("src-dest-indirect") + (+ (f-0-4 4) (f-4-4 9)) + (sequence () (set (reg h-src-indirect) 1) (set (reg h-dst-indirect) 1)) + ()) diff -uprN binutils-2.16.91.0.1/cpu/m32c.opc binutils-2.16.91.0.2/cpu/m32c.opc --- binutils-2.16.91.0.1/cpu/m32c.opc 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/cpu/m32c.opc 2005-07-20 12:27:27.662132205 -0700 @@ -0,0 +1,964 @@ +/* m32c opcode support. -*- C -*- + + Copyright 2005 Free Software Foundation, Inc. + + Contributed by Red Hat Inc; developed under contract from Renesas + + This file is part of the GNU Binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* This file is an addendum to m32c.cpu. Heavy use of C code isn't + appropriate in .cpu files, so it resides here. This especially applies + to assembly/disassembly where parsing/printing can be quite involved. + Such things aren't really part of the specification of the cpu, per se, + so .cpu files provide the general framework and .opc files handle the + nitty-gritty details as necessary. + + Each section is delimited with start and end markers. + + -opc.h additions use: "-- opc.h" + -opc.c additions use: "-- opc.c" + -asm.c additions use: "-- asm.c" + -dis.c additions use: "-- dis.c" + -ibd.h additions use: "-- ibd.h". */ + +/* -- opc.h */ + +/* Needed for RTL's 'ext' and 'trunc' operators. */ +#include "cgen-types.h" +#include "cgen-ops.h" + +/* We can't use the default hash size because many bits are used by + operands. */ +#define CGEN_DIS_HASH_SIZE 1 +#define CGEN_DIS_HASH(buf, value) 0 +#define CGEN_VERBOSE_ASSEMBLER_ERRORS +#define CGEN_VALIDATE_INSN_SUPPORTED + +extern int m32c_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); + +#define CGEN_ASM_HASH_SIZE 0xffff +#define CGEN_ASM_HASH(mnem) m32c_asm_hash ((mnem)) + +/* -- */ + +/* -- opc.c */ +static unsigned int +m32c_asm_hash (const char *mnem) +{ + unsigned int h; + + /* The length of the mnemonic for the Jcnd insns is 1. Hash jsri. */ + if (mnem[0] == 'j' && mnem[1] != 's') + return 'j'; + + /* Don't hash scCND */ + if (mnem[0] == 's' && mnem[1] == 'c') + return 's'; + + for (h = 0; *mnem && *mnem != ' ' && *mnem != ':'; ++mnem) + h += *mnem; + return h % CGEN_ASM_HASH_SIZE; +} + +/* -- asm.c */ +#include "safe-ctype.h" + +#define MACH_M32C 5 /* Must match md_begin. */ + +static int +m32c_cgen_isa_register (const char **strp) + { + int u; + const char *s = *strp; + static char * m32c_register_names [] = + { + "r0", "r1", "r2", "r3", "r0l", "r0h", "r1l", "r1h", + "a0", "a1", "r2r0", "r3r1", "sp", "fb", "dct0", "dct1", "flg", "svf", + "drc0", "drc1", "dmd0", "dmd1", "intb", "svp", "vct", "isp", "dma0", + "dma1", "dra0", "dra1", "dsa0", "dsa1", 0 + }; + + for (u = 0; m32c_register_names[u]; u++) + { + int len = strlen (m32c_register_names[u]); + + if (memcmp (m32c_register_names[u], s, len) == 0 + && (s[len] == 0 || ! ISALNUM (s[len]))) + return 1; + } + return 0; +} + +#define PARSE_UNSIGNED \ + do \ + { \ + /* Don't successfully parse literals beginning with '['. */ \ + if (**strp == '[') \ + return "Invalid literal"; /* Anything -- will not be seen. */ \ + \ + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);\ + if (errmsg) \ + return errmsg; \ + } \ + while (0) + +#define PARSE_SIGNED \ + do \ + { \ + /* Don't successfully parse literals beginning with '['. */ \ + if (**strp == '[') \ + return "Invalid literal"; /* Anything -- will not be seen. */ \ + \ + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); \ + if (errmsg) \ + return errmsg; \ + } \ + while (0) + +static const char * +parse_unsigned6 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value; + + PARSE_UNSIGNED; + + if (value > 0x3f) + return _("imm:6 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_unsigned8 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value; + long have_zero = 0; + + if (strncmp (*strp, "0x0", 3) == 0 + || (**strp == '0' && *(*strp + 1) != 'x')) + have_zero = 1; + + PARSE_UNSIGNED; + + if (value > 0xff) + return _("dsp:8 immediate is out of range"); + + /* If this field may require a relocation then use larger dsp16. */ + if (! have_zero && value == 0) + return _("dsp:8 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_signed4 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + long have_zero = 0; + + if (strncmp (*strp, "0x0", 3) == 0 + || (**strp == '0' && *(*strp + 1) != 'x')) + have_zero = 1; + + PARSE_SIGNED; + + if (value < -8 || value > 7) + return _("Immediate is out of range -8 to 7"); + + /* If this field may require a relocation then use larger dsp16. */ + if (! have_zero && value == 0) + return _("Immediate is out of range -8 to 7"); + + *valuep = value; + return 0; +} + +static const char * +parse_signed8 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + + PARSE_SIGNED; + + if (value <= 255 && value > 127) + value -= 0x100; + + if (value < -128 || value > 127) + return _("dsp:8 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_unsigned16 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value; + long have_zero = 0; + + /* Don't successfully parse literals beginning with '['. */ + if (**strp == '[') + return "Invalid literal"; /* Anything -- will not be seen. */ + + /* Don't successfully parse register names. */ + if (m32c_cgen_isa_register (strp)) + return "Invalid literal"; /* Anything -- will not be seen. */ + + if (strncmp (*strp, "0x0", 3) == 0 + || (**strp == '0' && *(*strp + 1) != 'x')) + have_zero = 1; + + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value > 0xffff) + return _("dsp:16 immediate is out of range"); + + /* If this field may require a relocation then use larger dsp24. */ + if (cd->machs == MACH_M32C && ! have_zero && value == 0 + && (strncmp (*strp, "[a", 2) == 0 + || **strp == ',' + || **strp == 0)) + return _("dsp:16 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_signed16 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + + PARSE_SIGNED; + + if (value <= 65535 && value > 32767) + value -= 0x10000; + + if (value < -32768 || value > 32767) + return _("dsp:16 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_unsigned20 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value; + + /* Don't successfully parse literals beginning with '['. */ + if (**strp == '[') + return "Invalid literal"; /* Anything -- will not be seen. */ + + /* Don't successfully parse register names. */ + if (m32c_cgen_isa_register (strp)) + return "Invalid literal"; /* Anything -- will not be seen. */ + + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value > 0xfffff) + return _("dsp:20 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_unsigned24 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value; + + /* Don't successfully parse literals beginning with '['. */ + if (**strp == '[') + return "Invalid literal"; /* Anything -- will not be seen. */ + + /* Don't successfully parse register names. */ + if (m32c_cgen_isa_register (strp)) + return "Invalid literal"; /* Anything -- will not be seen. */ + + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value > 0xffffff) + return _("dsp:24 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_signed32 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + *valuep = value; + return 0; +} + +static const char * +parse_imm1_S (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value < 1 || value > 2) + return _("immediate is out of range 1-2"); + + *valuep = value; + return 0; +} + +static const char * +parse_imm3_S (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value < 1 || value > 8) + return _("immediate is out of range 1-8"); + + *valuep = value; + return 0; +} + +static const char * +parse_lab_5_3 (CGEN_CPU_DESC cd, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + int opinfo, + enum cgen_parse_operand_result *type_addr, + unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value; + enum cgen_parse_operand_result op_res; + + errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_5_3, + opinfo, & op_res, & value); + + if (type_addr) + *type_addr = op_res; + + if (op_res == CGEN_PARSE_OPERAND_ADDRESS) + { + /* This is a hack; the field cannot handle near-zero signed + offsets that CGEN wants to put in to indicate an "empty" + operand at first. */ + *valuep = 2; + return 0; + } + if (errmsg) + return errmsg; + + if (value < 2 || value > 9) + return _("immediate is out of range 2-9"); + + *valuep = value; + return 0; +} + +static const char * +parse_Bitno16R (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value; + + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value > 15) + return _("Bit number for indexing general register is out of range 0-15"); + + *valuep = value; + return 0; +} + +static const char * +parse_unsigned_bitbase (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep, + unsigned bits) +{ + const char *errmsg = 0; + unsigned long bit; + unsigned long base; + const char *newp = *strp; + unsigned long long bitbase; + + errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & bit); + if (errmsg) + return errmsg; + + if (*newp != ',') + return "Missing base for bit,base:8"; + + ++newp; + errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & base); + if (errmsg) + return errmsg; + + bitbase = (unsigned long long) bit + ((unsigned long long) base * 8); + + if (bitbase >= (1ull << bits)) + return _("bit,base is out of range"); + + *valuep = bitbase; + *strp = newp; + return 0; +} + +static const char * +parse_signed_bitbase (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep, + unsigned bits) +{ + const char *errmsg = 0; + unsigned long bit; + signed long base; + const char *newp = *strp; + long long bitbase; + long long limit; + + errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & bit); + if (errmsg) + return errmsg; + + if (*newp != ',') + return "Missing base for bit,base:8"; + + ++newp; + errmsg = cgen_parse_signed_integer (cd, & newp, opindex, & base); + if (errmsg) + return errmsg; + + bitbase = (long long)bit + ((long long)base * 8); + + limit = 1ll << (bits - 1); + if (bitbase < -limit || bitbase >= limit) + return _("bit,base is out of range"); + + *valuep = bitbase; + *strp = newp; + return 0; +} + +static const char * +parse_unsigned_bitbase8 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + return parse_unsigned_bitbase (cd, strp, opindex, valuep, 8); +} + +static const char * +parse_unsigned_bitbase11 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + return parse_unsigned_bitbase (cd, strp, opindex, valuep, 11); +} + +static const char * +parse_unsigned_bitbase16 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + return parse_unsigned_bitbase (cd, strp, opindex, valuep, 16); +} + +static const char * +parse_unsigned_bitbase19 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + return parse_unsigned_bitbase (cd, strp, opindex, valuep, 19); +} + +static const char * +parse_unsigned_bitbase27 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + return parse_unsigned_bitbase (cd, strp, opindex, valuep, 27); +} + +static const char * +parse_signed_bitbase8 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + return parse_signed_bitbase (cd, strp, opindex, valuep, 8); +} + +static const char * +parse_signed_bitbase11 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + return parse_signed_bitbase (cd, strp, opindex, valuep, 11); +} + +static const char * +parse_signed_bitbase19 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + return parse_signed_bitbase (cd, strp, opindex, valuep, 19); +} + +/* Parse the suffix as : or as nothing followed by a whitespace. */ + +static const char * +parse_suffix (const char **strp, char suffix) +{ + const char *newp = *strp; + + if (**strp == ':' && TOLOWER (*(*strp + 1)) == suffix) + newp = *strp + 2; + + if (ISSPACE (*newp)) + { + *strp = newp; + return 0; + } + + return "Invalid suffix"; /* Anything -- will not be seen. */ +} + +static const char * +parse_S (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) +{ + return parse_suffix (strp, 's'); +} + +static const char * +parse_G (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) +{ + return parse_suffix (strp, 'g'); +} + +static const char * +parse_Q (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) +{ + return parse_suffix (strp, 'q'); +} + +static const char * +parse_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) +{ + return parse_suffix (strp, 'z'); +} + +/* Parse an empty suffix. Fail if the next char is ':'. */ + +static const char * +parse_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) +{ + if (**strp == ':') + return "Unexpected suffix"; + return 0; +} + +static const char * +parse_r0l_r0h (CGEN_CPU_DESC cd, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep) +{ + const char *errmsg; + signed long value; + signed long junk; + const char *newp = *strp; + + /* Parse r0[hl]. */ + errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0l_r0h, & value); + if (errmsg) + return errmsg; + + if (*newp != ',') + return _("not a valid r0l/r0h pair"); + ++newp; + + /* Parse the second register in the pair. */ + if (value == 0) /* r0l */ + errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0h, & junk); + else + errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0l, & junk); + if (errmsg) + return errmsg; + + *strp = newp; + *valuep = ! value; + return 0; +} + +/* Accept .b or .w in any case. */ + +static const char * +parse_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) +{ + if (**strp == '.' + && (*(*strp + 1) == 'b' || *(*strp + 1) == 'B' + || *(*strp + 1) == 'w' || *(*strp + 1) == 'W')) + { + *strp += 2; + return NULL; + } + + return _("Invalid size specifier"); +} + +/* Special check to ensure that instruction exists for given machine. */ + +int +m32c_cgen_insn_supported (CGEN_CPU_DESC cd, + const CGEN_INSN *insn) +{ + int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); + int isas = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ISA); + + /* If attributes are absent, assume no restriction. */ + if (machs == 0) + machs = ~0; + + return ((machs & cd->machs) + && (isas & cd->isas)); +} + +/* Parse a set of registers, R0,R1,A0,A1,SB,FB. */ + +static const char * +parse_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + unsigned long *valuep, + int push) +{ + const char *errmsg = 0; + int regno = 0; + + *valuep = 0; + while (**strp && **strp != ')') + { + if (**strp == 'r' || **strp == 'R') + { + ++*strp; + regno = **strp - '0'; + if (regno > 4) + errmsg = _("Register number is not valid"); + } + else if (**strp == 'a' || **strp == 'A') + { + ++*strp; + regno = **strp - '0'; + if (regno > 2) + errmsg = _("Register number is not valid"); + regno = **strp - '0' + 4; + } + + else if (strncasecmp (*strp, "sb", 2) == 0 || strncasecmp (*strp, "SB", 2) == 0) + { + regno = 6; + ++*strp; + } + + else if (strncasecmp (*strp, "fb", 2) == 0 || strncasecmp (*strp, "FB", 2) == 0) + { + regno = 7; + ++*strp; + } + + if (push) /* Mask is reversed for push. */ + *valuep |= 0x80 >> regno; + else + *valuep |= 1 << regno; + + ++*strp; + if (**strp == ',') + { + if (*(*strp + 1) == ')') + break; + ++*strp; + } + } + + if (!*strp) + errmsg = _("Register list is not valid"); + + return errmsg; +} + +#define POP 0 +#define PUSH 1 + +static const char * +parse_pop_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + unsigned long *valuep) +{ + return parse_regset (cd, strp, opindex, valuep, POP); +} + +static const char * +parse_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + unsigned long *valuep) +{ + return parse_regset (cd, strp, opindex, valuep, PUSH); +} + +/* -- dis.c */ + +#include "elf/m32c.h" +#include "elf-bfd.h" + +/* Always print the short insn format suffix as ':'. */ + +static void +print_suffix (void * dis_info, char suffix) +{ + disassemble_info *info = dis_info; + + (*info->fprintf_func) (info->stream, ":%c", suffix); +} + +static void +print_S (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_suffix (dis_info, 's'); +} + + +static void +print_G (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_suffix (dis_info, 'g'); +} + +static void +print_Q (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_suffix (dis_info, 'q'); +} + +static void +print_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_suffix (dis_info, 'z'); +} + +/* Print the empty suffix. */ + +static void +print_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + return; +} + +static void +print_r0l_r0h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = dis_info; + + if (value == 0) + (*info->fprintf_func) (info->stream, "r0h,r0l"); + else + (*info->fprintf_func) (info->stream, "r0l,r0h"); +} + +static void +print_unsigned_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + unsigned long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = dis_info; + + (*info->fprintf_func) (info->stream, "%ld,0x%lx", value & 0x7, value >> 3); +} + +static void +print_signed_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + signed long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = dis_info; + + (*info->fprintf_func) (info->stream, "%ld,%ld", value & 0x7, value >> 3); +} + +static void +print_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + /* Always print the size as '.w'. */ + disassemble_info *info = dis_info; + + (*info->fprintf_func) (info->stream, ".w"); +} + +#define POP 0 +#define PUSH 1 + +static void print_pop_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_push_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); + +/* Print a set of registers, R0,R1,A0,A1,SB,FB. */ + +static void +print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED, + int push) +{ + static char * m16c_register_names [] = + { + "r0", "r1", "r2", "r3", "a0", "a1", "sb", "fb" + }; + disassemble_info *info = dis_info; + int mask; + int index = 0; + char* comma = ""; + + if (push) + mask = 0x80; + else + mask = 1; + + if (value & mask) + { + (*info->fprintf_func) (info->stream, "%s", m16c_register_names [0]); + comma = ","; + } + + for (index = 1; index <= 7; ++index) + { + if (push) + mask >>= 1; + else + mask <<= 1; + + if (value & mask) + { + (*info->fprintf_func) (info->stream, "%s%s", comma, + m16c_register_names [index]); + comma = ","; + } + } +} + +static void +print_pop_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_regset (cd, dis_info, value, attrs, pc, length, POP); +} + +static void +print_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_regset (cd, dis_info, value, attrs, pc, length, PUSH); +} diff -uprN binutils-2.16.91.0.1/cpu/m32r.opc binutils-2.16.91.0.2/cpu/m32r.opc --- binutils-2.16.91.0.1/cpu/m32r.opc 2005-05-10 15:46:44.000000000 -0700 +++ binutils-2.16.91.0.2/cpu/m32r.opc 2005-07-20 12:27:27.664131876 -0700 @@ -24,7 +24,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ /* This file is an addendum to m32r.cpu. Heavy use of C code isn't appropriate in .cpu files, so it resides here. This especially applies @@ -55,56 +56,46 @@ : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \ : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4))) #else -#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash(buffer, value) -extern unsigned int m32r_cgen_dis_hash(const char *, CGEN_INSN_INT); +#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash (buffer, value) +extern unsigned int m32r_cgen_dis_hash (const char *, CGEN_INSN_INT); #endif /* -- */ /* -- opc.c */ unsigned int -m32r_cgen_dis_hash (buf, value) - const char * buf ATTRIBUTE_UNUSED; - CGEN_INSN_INT value; +m32r_cgen_dis_hash (const char * buf ATTRIBUTE_UNUSED, CGEN_INSN_INT value) { unsigned int x; - - if (value & 0xffff0000) /* 32bit instructions */ + + if (value & 0xffff0000) /* 32bit instructions. */ value = (value >> 16) & 0xffff; - - x = (value>>8) & 0xf0; + + x = (value >> 8) & 0xf0; if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50) return x; - + if (x == 0x70 || x == 0xf0) - return x | ((value>>8) & 0x0f); - + return x | ((value >> 8) & 0x0f); + if (x == 0x30) return x | ((value & 0x70) >> 4); else return x | ((value & 0xf0) >> 4); } - + /* -- */ /* -- asm.c */ -static const char * parse_hash - PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); -static const char * parse_hi16 - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_slo16 - PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); -static const char * parse_ulo16 - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'"); /* Handle '#' prefixes (i.e. skip over them). */ static const char * -parse_hash (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - const char **strp; - int opindex ATTRIBUTE_UNUSED; - long *valuep ATTRIBUTE_UNUSED; +parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + long *valuep ATTRIBUTE_UNUSED) { if (**strp == '#') ++*strp; @@ -114,11 +105,10 @@ parse_hash (cd, strp, opindex, valuep) /* Handle shigh(), high(). */ static const char * -parse_hi16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_hi16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -131,9 +121,9 @@ parse_hi16 (cd, strp, opindex, valuep) { *strp += 5; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_ULO, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return "missing `)'"; + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) @@ -145,9 +135,9 @@ parse_hi16 (cd, strp, opindex, valuep) { *strp += 6; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_SLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return "missing `)'"; + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) @@ -167,11 +157,10 @@ parse_hi16 (cd, strp, opindex, valuep) handles the case where low() isn't present. */ static const char * -parse_slo16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - long *valuep; +parse_slo16 (CGEN_CPU_DESC cd, + const char ** strp, + int opindex, + long * valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -184,9 +173,9 @@ parse_slo16 (cd, strp, opindex, valuep) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return "missing `)'"; + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) @@ -203,9 +192,9 @@ parse_slo16 (cd, strp, opindex, valuep) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_SDA16, - NULL, &value); + NULL, & value); if (**strp != ')') - return "missing `)'"; + return MISSING_CLOSING_PARENTHESIS; ++*strp; *valuep = value; return errmsg; @@ -219,11 +208,10 @@ parse_slo16 (cd, strp, opindex, valuep) handles the case where low() isn't present. */ static const char * -parse_ulo16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_ulo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -236,9 +224,9 @@ parse_ulo16 (cd, strp, opindex, valuep) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return "missing `)'"; + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) @@ -253,9 +241,6 @@ parse_ulo16 (cd, strp, opindex, valuep) /* -- */ /* -- dis.c */ -static void print_hash PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); -static int my_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); - /* Immediate values are prefixed with '#'. */ #define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length) \ @@ -269,15 +254,15 @@ static int my_print_insn PARAMS ((CGEN_C /* Handle '#' prefixes as operands. */ static void -print_hash (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value ATTRIBUTE_UNUSED; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; + (*info->fprintf_func) (info->stream, "#"); } @@ -285,17 +270,16 @@ print_hash (cd, dis_info, value, attrs, #define CGEN_PRINT_INSN my_print_insn static int -my_print_insn (cd, pc, info) - CGEN_CPU_DESC cd; - bfd_vma pc; - disassemble_info *info; +my_print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info) { - char buffer[CGEN_MAX_INSN_SIZE]; - char *buf = buffer; + bfd_byte buffer[CGEN_MAX_INSN_SIZE]; + bfd_byte *buf = buffer; int status; int buflen = (pc & 3) == 0 ? 4 : 2; int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; - char *x; + bfd_byte *x; /* Read the base part of the insn. */ diff -uprN binutils-2.16.91.0.1/cpu/ms1.opc binutils-2.16.91.0.2/cpu/ms1.opc --- binutils-2.16.91.0.1/cpu/ms1.opc 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/cpu/ms1.opc 2005-07-20 12:27:27.665131711 -0700 @@ -89,16 +89,6 @@ ms1_asm_hash (const char* insn) /* -- asm.c */ -static int signed_out_of_bounds (long); -static const char * parse_imm16 (CGEN_CPU_DESC, const char **, int, long *); -static const char * parse_dup (CGEN_CPU_DESC, const char **, int, long *); -static const char * parse_ball (CGEN_CPU_DESC, const char **, int, long *); -static const char * parse_xmode (CGEN_CPU_DESC, const char **, int, long *); -static const char * parse_rc (CGEN_CPU_DESC, const char **, int, long *); -static const char * parse_cbrb (CGEN_CPU_DESC, const char **, int, long *); -static const char * parse_rbbc (CGEN_CPU_DESC, const char **, int, long *); -static const char * parse_type (CGEN_CPU_DESC, const char **, int, long *); - /* Range checking for signed numbers. Returns 0 if acceptable and 1 if the value is out of bounds for a signed quantity. */ @@ -114,8 +104,9 @@ static const char * parse_imm16 (CGEN_CPU_DESC cd, const char **strp, int opindex, - long *valuep) + void *arg) { + signed long * valuep = (signed long *) arg; const char *errmsg; enum cgen_parse_operand_result result_type; bfd_reloc_code_real_type code = BFD_RELOC_NONE; @@ -218,9 +209,9 @@ parse_imm16 (CGEN_CPU_DESC cd, else { /* MS1_OPERAND_IMM16Z. Parse as an unsigned integer. */ - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) valuep); - if (opindex == (CGEN_OPERAND_TYPE)MS1_OPERAND_IMM16 + if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16 && *valuep >= 0x8000 && *valuep <= 0xffff) *valuep -= 0x10000; @@ -235,7 +226,7 @@ static const char * parse_dup (CGEN_CPU_DESC cd, const char **strp, int opindex, - long *valuep) + unsigned long *valuep) { const char *errmsg = NULL; @@ -260,7 +251,7 @@ static const char * parse_ball (CGEN_CPU_DESC cd, const char **strp, int opindex, - long *valuep) + unsigned long *valuep) { const char *errmsg = NULL; @@ -284,7 +275,7 @@ static const char * parse_xmode (CGEN_CPU_DESC cd, const char **strp, int opindex, - long *valuep) + unsigned long *valuep) { const char *errmsg = NULL; @@ -308,7 +299,7 @@ static const char * parse_rc (CGEN_CPU_DESC cd, const char **strp, int opindex, - long *valuep) + unsigned long *valuep) { const char *errmsg = NULL; @@ -332,7 +323,7 @@ static const char * parse_cbrb (CGEN_CPU_DESC cd, const char **strp, int opindex, - long *valuep) + unsigned long *valuep) { const char *errmsg = NULL; @@ -356,7 +347,7 @@ static const char * parse_rbbc (CGEN_CPU_DESC cd, const char **strp, int opindex, - long *valuep) + unsigned long *valuep) { const char *errmsg = NULL; @@ -390,7 +381,7 @@ static const char * parse_type (CGEN_CPU_DESC cd, const char **strp, int opindex, - long *valuep) + unsigned long *valuep) { const char *errmsg = NULL; @@ -431,7 +422,7 @@ print_dollarhex (CGEN_CPU_DESC cd ATTRIB { disassemble_info *info = (disassemble_info *) dis_info; - info->fprintf_func (info->stream, "$%x", value); + info->fprintf_func (info->stream, "$%lx", value); if (0) print_normal (cd, dis_info, value, attrs, pc, length); diff -uprN binutils-2.16.91.0.1/cpu/sh.opc binutils-2.16.91.0.2/cpu/sh.opc --- binutils-2.16.91.0.1/cpu/sh.opc 2005-05-10 15:46:44.000000000 -0700 +++ binutils-2.16.91.0.2/cpu/sh.opc 2005-07-20 12:27:27.665131711 -0700 @@ -1,6 +1,6 @@ /* SHmedia opcode support. -*- C -*- - Copyright 2000 Free Software Foundation, Inc. + Copyright 2000, 2005 Free Software Foundation, Inc. Contributed by Red Hat Inc; developed under contract from Hitachi Semiconductor (America) Inc. @@ -19,9 +19,9 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ -*/ /* This file is an addendum to sh-media.cpu. Heavy use of C code isn't appropriate in .cpu files, so it resides here. This especially applies to assembly/disassembly where parsing/printing can be quite involved. @@ -35,8 +35,7 @@ -opc.c additions use: "-- opc.c" -asm.c additions use: "-- asm.c" -dis.c additions use: "-- dis.c" - -ibd.h additions use: "-- ibd.h" -*/ + -ibd.h additions use: "-- ibd.h" */ /* -- opc.h */ @@ -51,27 +50,26 @@ /* -- asm.c */ static const char * -parse_fsd (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - long *valuep; +parse_fsd (CGEN_CPU_DESC cd, + const char ** strp, + int opindex, + long * valuep) { - abort(); + abort (); } /* -- dis.c */ static void -print_likely (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd; - PTR dis_info; - long value; - unsigned int attrs; - bfd_vma pc; - int length; +print_likely (CGEN_CPU_DESC cd, + void * dis_info, + long value, + unsigned int attrs, + bfd_vma pc, + int length) { disassemble_info *info = (disassemble_info *) dis_info; + (*info->fprintf_func) (info->stream, (value) ? "/l" : "/u"); } diff -uprN binutils-2.16.91.0.1/gas/ChangeLog binutils-2.16.91.0.2/gas/ChangeLog --- binutils-2.16.91.0.1/gas/ChangeLog 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/gas/ChangeLog 2005-07-20 12:27:27.678129567 -0700 @@ -1,3 +1,312 @@ +2005-07-20 Kazuhiro Inaoka + + * config/tc-m32r.c (tc_gen_reloc): Check BFD_RELOC_32_PCREL and + BFD_RELOC_16_PCREL to Support R_M32R_REL32. + +2005-07-18 Nick Clifton + + * configure.tgt: Restore alpha ordering to list of arches. + +2005-07-18 John David Anglin + + * tc-hppa.c (pa_ip): Reject match for '#' immediate if not pa20. + +2005-07-18 Jan Beulich + + * config/tc-i386.c (md_begin): Use IS_ELF. + (tc_i386_fix_adjustable): Likewise. + (md_estimate_size_before_relax): Likewise. + (md_apply_fix): Likewise. + (i386_target_format): Likewise. + (lex_got): Define to NULL when not ELF or when LEX_AT. Check IS_ELF. + (i386_immediate): Remove #ifdef LEX_AT. + (i386_displacement): Likewise. + * config/tc-i386.h (x86_cons): Prototype only when ELF and when not + LEX_AT. + +2005-07-18 Jan Beulich + + * config/tc-i386.c (reloc): Convert to ISO C90. Change first + parameter to unsigned. Parameter sign now is tristate - zero/ + positive mean unsigned/signed, negative means signedness doesn't + matter. Check field size, + signedness, and pcrel-ness are in agreement between relocated field + and relocation type. Adjust diagnostics. + (optimize_imm): And type mask of operand instead of overwriting it. + (lex_got): Convert to ISO C90. Add third parameter. Add new field to + local structure and initialize gotrel accordingly. Pass caller as + mask of types that the operator can match. + (x86_cons_fix_new): Let reloc know that signedness of relocation + doesn't matter. + (x86_pe_cons_fix_new): Likewise. + (x86_cons): Pass additional argument to lex_got. + (i386_immediate): New local variable 'types'. Pass its address as + additional argument to lex_got. Mask out operand types not supported + befoe returning. + (i386_displacement): Likewise. Set bigdisp to all types supported in + 64-bit mode, combining the previously split initialization. + +2005-07-18 Jan Beulich + + * config/tc-i386.c (parse_insn): Reject prefix if unavailable in + current mode. + +2005-07-16 John David Anglin + + * config/tc-hppa.c (pa_ip): Search entire mnemonic before considering + promoted match. + +2005-07-16 Alan Modra + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2007-07-15 H.J. Lu + + * gas/config/tc-i386.h (CpuVMX): New. + (CpuUnknownFlags): Add CpuVMX. + +2005-07-14 Jim Blandy + + Add support for the Renesas M32C. + * Makefile.am (CPU_TYPES): List m32c. + (TARGET_CPU_CFILES): List config/tc-m32c.c. + (TARGET_CPU_HFILES): List config/tc-m32c.h. + * configure.in: Add case for m32c. + * configure.tgt: Add cases for m32c and m32c-*-elf. + * configure: Regenerated. + * config/tc-m32c.c, config/tc-m32c.h: New files. + * doc/Makefile.am (CPU_DOCS): Add c-m32c.texi. + * doc/Makefile.in: Regenerated. + * doc/all.texi: Set M32C. + * doc/as.texinfo: Add text for the M32C-specific options and line + comment characters, and refer to c-m32c.texi. + * doc/c-m32c.texi: New file. + +2005-07-14 Nick Clifton + + PR 1069 + * config/tc-crx.c (reset_vars): Use strncpy to prevent overflowing + the ins_parse buffer. + +2005-07-10 Ralf Corsepius + + * configure.tgt: Remove a29k-*-rtems*, hppa*-*-rtems*,i386-go32-rtems*, + i386-*-rtemscoff*, sparc-*-rtemsaout*. + +2005-07-10 H.J. Lu + + * config/tc-i386.c (optimize_disp): Optimize signed 32bit + displacements. + +2005-07-08 Ben Elliston + + * frags.h: Remove ANSI_PROTOTYPES conditional code. + * config/obj-elf.h: Likewise. + * config/tc-h8300.h: Likewise. + * config/tc-h8500.h: Likewise. + * config/tc-i370.h: Likewise. + * config/tc-i386.h: Likewise. + * config/tc-m68hc11.h: Likewise. + * config/tc-m68k.h: Likewise. + * config/tc-ppc.h: Likewise. + * config/tc-s390.h: Likewise. + * config/tc-sh.h: Likewise. + * config/tc-sparc.h: Likewise. + * config/tc-tic30.c: Likewise. + * config/tc-w65.h: Likewise. + * config/tc-xtensa.h: Likewise. + +2005-07-08 Hans-Peter Nilsson + + PR gas/1049 + * config/tc-cris.h (MD_APPLY_SYM_VALUE): Define. + +2005-07-07 Kaveh R. Ghazi + + * config/tc-tic30.c (debug): Add format attribute. Fix format + bugs. + +2005-07-06 H.J. Lu + + * config/tc-i386.c (cpu_arch): Add sse3. + + * config/tc-i386.h (CpuSSE3): Renamed from ... + (CpuPNI): This. Defined as CpuSSE3. + + * doc/c-i386.texi: Document .sse3. + +2005-07-06 Jan Beulich + + * config/tc-ia64.c (nop): Use zero for L-unit pseudo-nop. + +2005-07-05 Nick Clifton + + * config/tc-pdp11.c (md_apply_fix): Cast first argument to + md_chars_to_numbers to an unsigned pointer in order to avoid a + compile time warning. + +2005-07-05 Paul Brook + + * config/tc-ppc.c (ppc_target_format): Add VxWorks. + +2005-07-05 Aldy Hernandez + + * config/tc-ms1.c: New. + * config/tc-ms1.h: New. + * testsuite/gas/ms1/allinsn.d: New. + * testsuite/gas/ms1/allinsn.s: New. + * testsuite/gas/ms1/badinsn.s: New. + * testsuite/gas/ms1/badinsn1.s: New. + * testsuite/gas/ms1/badoffsethigh.s: New. + * testsuite/gas/ms1/badoffsetlow.s: New. + * testsuite/gas/ms1/badorder.s: New. + * testsuite/gas/ms1/badreg.s: New. + * testsuite/gas/ms1/badsignedimmhigh.s: New. + * testsuite/gas/ms1/badsignedimmlow.s: New. + * testsuite/gas/ms1/badsyntax.s: New. + * testsuite/gas/ms1/badsyntax1.s: New. + * testsuite/gas/ms1/badunsignedimmhigh.s: New. + * testsuite/gas/ms1/badunsignedimmlow.s: New. + * testsuite/gas/ms1/errors.exp: New. + * testsuite/gas/ms1/ldst.s: New. + * testsuite/gas/ms1/misc.d: New. + * testsuite/gas/ms1/misc.s: New. + * testsuite/gas/ms1/ms1-16-003.d: New. + * testsuite/gas/ms1/ms1-16-003.s: New. + * testsuite/gas/ms1/ms1.exp: New. + * testsuite/gas/ms1/msys.d: New. + * testsuite/gas/ms1/msys.s: New. + * testsuite/gas/ms1/relocs.d: New. + * testsuite/gas/ms1/relocs.exp: New. + * testsuite/gas/ms1/relocs1.s: New. + * testsuite/gas/ms1/relocs2.s: New. + +2005-07-05 Jan Beulich + + * config/tc-i386.h (CpuSVME): New. + (CpuUnknownFlags): Include CpuSVME. + * config/tc-i386.c (cpu_arch): Add .pacifica and .svme. Add opteron + as alias of sledgehammer. + (md_assemble): Include invlpga in the check for insns with two source + operands. + (process_operands): Include SVME insns in the check for ignored + segment overrides. Adjust diagnostic. + (i386_index_check): Special-case SVME insns with memory operands. + +2005-07-04 Khem Raj + Nick Clifton + + * tc-arm.c (struct arm_it): Make operands.imm signed to match its + use an immediate value. + (parse_vfp_reg_list): Make the 2nd parameter an unsigned pointer + since the register field of the operands structure is unsigned. + (s_arm_unwind_save_vfp): Make "reg" unsigned. + (parse_operands): Make the 2ns parameter an unsigned pointer to + match its use. + (do_ldrd): When using the imm field of the operands structure as a + second register field, treat it as unsigned. + +2005-07-04 Alan Modra + + PR 1004 + * config/obj-elf.c (obj_elf_change_section): Use backend + get_sec_type_attr. + +2005-07-01 Jan Beulich + + * config/tc-ia64.c (line_separator_chars): Add '{' and '}'. + (output_spill_psprel, output_spill_psprel_p): Combine. + (output_spill_sprel, output_spill_sprel_p): Combine. + (output_spill_reg, output_spill_regp_p): Combine. + (process_one_record): Handle psp_psprel. + (parse_predicate_and_operand): New. + (convert_expr_to_ab_reg): Two new parameters. Return void. Always + initialize output values. Emit diagnostic case here. + (convert_expr_to_xy_reg): Likewise. Don't allow r0, f0, and f1. + (add_unwind_entry): New second parameter. Allow first parameter to + be NULL. Parse optional tag, emit warning about further support for + it otherwise being missing. Check end-of-line when requested. + (dot_fframe): Clear operand when wrong. Allow tag. + (dot_vframe): Likewise. + (dot_vframesp): Likewise. Rename parameter, issue warning when psp + relative. + (dot_vframepsp): Remove. + (dot_altrp): Clear operand when wrong. Allow tag. + (dot_save): Likewise. Let default case also go through + add_unwind_entry. + (dot_savemem): Likewise. + (dot_restore): Don't return when wrong operand. Allow tag. + (dot_spillreg, dot_spillreg_p): Combine. Simplify by using + parse_predicate_and_operand and the new arguments to + convert_expr_to_ab_reg and convert_expr_to_xy_reg. Don't return + when wrong operand. Allow tag. + (dot_restorereg, dot_restorereg_p): Likewise. + (dot_spillmem, dot_spillmem_p): Likewise. + (dot_saveg): Clear operand when wrong. Perform tighter operand + checks. Allow tag. + (dot_savef): Likewise. + (dot_saveb): Likewise. + (dot_savegf): Likewise. + (dot_spill): Remove end-of-line check. Combine. Simplify by using + parse_predicate_and_operand and the new arguments to + convert_expr_to_ab_reg and convert_expr_to_xy_reg. Don't return + when wrong operand. Allow tag. + (popcount): New. + (dot_label_state): Don't return when wrong operand. + (dot_copy_state): Likewise. + (dot_unwabi): Likewise. Check if in prologue. + (dot_body): Don't call demand_empty_rest_of_line. + (dot_prologue): Type of mask and grsave is unsigned. Perform tighter + operand checks. + (md_pseudo_table): Also use dot_restorereg for .restorereg.p. Also + use dot_spillreg for .spillreg.p. Also use dot_spillmem for + .spillpsp.p and .spillsp.p. Also use dot_vframesp for .vframepsp. + (parse_operand): New second parameter. Don't deal with '}' here + anymore. Don't advance past end-of-line. + (parse_operands): Pass second argument to parse_operand. + (ia64_start_line): Prevent out-of-bounds access through + input_line_pointer. Deal with '}' here. + (ia64_unrecognized_line): Don't deal with '}' here. + (dot_alias): Use ignore_rest_of_line not its deprecated alias + discard_rest_of_line. + +2005-06-30 Zack Weinberg + + * config/tc-arm.c (T_OPCODE_BRANCH, encode_arm_addr_mode_2) + (encode_arm_addr_mode_3, encode_arm_cp_address, do_blx, do_t_blx) + (do_t_branch, insns [b, bl]): Don't encode pipeline offset. + (do_branch): Always set inst.reloc.pc_rel. + (s_arm_elf_cons): Disallow use of (plt) suffix. + (do_adrl): Adjust X_add_number unconditionally. + (md_pcrel_from): Rename md_pcrel_from_section, add second segT + argument. Handle all adjustment for pipeline offset here. + (md_apply_fix): No need to undo work of md_pcrel_from. No + need to extract pre-encoded pipeline adjustments from various + branch instructions. Generally, assume instructions are already + all-bits-zero in the field being fixed up. Remove all OBJ_ELF + special cases. Handle BFD_RELOC_ARM_PLT32 like + BFD_RELOC_ARM_PCREL_BRANCH. + (tc_gen_reloc): Remove OBJ_ELF special case. + * config/tc-arm.c: Define MD_PCREL_FROM_SECTION. + +2005-06-30 Ben Elliston + + * Makefile.am (check-DEJAGNU): Don't search for expect. + * Makefile.in: Regenerate. + +2005-06-30 Ben Elliston + + * Makefile.am (EXPECT): Set to expect. + (RUNTEST): Likewise, set to runtest. + * Makefile.in: Regenerate. + +2005-06-23 Ben Elliston + + * config/m68k-parse.h: Use ISO C90. + * config/m68k-parse.y: Likewise. + * config/tc-m68k.h: Likewise. + 2005-06-20 H.J. Lu PR 1013 diff -uprN binutils-2.16.91.0.1/gas/ChangeLog-9295 binutils-2.16.91.0.2/gas/ChangeLog-9295 --- binutils-2.16.91.0.1/gas/ChangeLog-9295 2005-04-09 12:03:03.000000000 -0700 +++ binutils-2.16.91.0.2/gas/ChangeLog-9295 2005-07-20 12:27:27.703125446 -0700 @@ -4143,7 +4143,7 @@ Tue Dec 13 08:04:15 1994 Ian Lance Tayl * config/tc-mips.c (macro_build): Accept BFD_RELOC_PCREL* without requiring that the X_op_symbol be in the text_section. - (macro): Change the test for a legel expression difference to + (macro): Change the test for a legal expression difference to correspond to changes in pseudo_set in read.c. Fri Dec 9 21:04:17 1994 Ken Raeburn diff -uprN binutils-2.16.91.0.1/gas/config/m68k-parse.h binutils-2.16.91.0.2/gas/config/m68k-parse.h --- binutils-2.16.91.0.1/gas/config/m68k-parse.h 2005-05-10 15:46:44.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/m68k-parse.h 2005-07-20 12:27:27.747118191 -0700 @@ -1,6 +1,6 @@ /* m68k-parse.h -- header file for m68k assembler Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000, - 2003, 2004 Free Software Foundation, Inc. + 2003, 2004, 2005 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler. @@ -339,7 +339,7 @@ struct m68k_op /* The parsing function. */ -extern int m68k_ip_op PARAMS ((char *, struct m68k_op *)); +extern int m68k_ip_op (char *, struct m68k_op *); /* Whether register prefixes are optional. */ extern int flag_reg_prefix_optional; diff -uprN binutils-2.16.91.0.1/gas/config/m68k-parse.y binutils-2.16.91.0.2/gas/config/m68k-parse.y --- binutils-2.16.91.0.1/gas/config/m68k-parse.y 2005-05-10 15:46:44.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/m68k-parse.y 2005-07-20 12:27:27.749117861 -0700 @@ -1,5 +1,5 @@ /* m68k.y -- bison grammar for m68k operand parsing - Copyright 1995, 1996, 1997, 1998, 2001, 2003, 2004 + Copyright 1995, 1996, 1997, 1998, 2001, 2003, 2004, 2005 Free Software Foundation, Inc. Written by Ken Raeburn and Ian Lance Taylor, Cygnus Support @@ -83,9 +83,9 @@ /* Internal functions. */ -static enum m68k_register m68k_reg_parse PARAMS ((char **)); -static int yylex PARAMS ((void)); -static void yyerror PARAMS ((const char *)); +static enum m68k_register m68k_reg_parse (char **); +static int yylex (void); +static void yyerror (const char *); /* The parser sets fields pointed to by this global variable. */ static struct m68k_op *op; diff -uprN binutils-2.16.91.0.1/gas/config/obj-elf.c binutils-2.16.91.0.2/gas/config/obj-elf.c --- binutils-2.16.91.0.1/gas/config/obj-elf.c 2005-05-10 15:46:44.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/obj-elf.c 2005-07-20 12:27:27.755116872 -0700 @@ -520,6 +520,7 @@ obj_elf_change_section (const char *name asection *old_sec; segT sec; flagword flags; + const struct elf_backend_data *bed; const struct bfd_elf_special_section *ssect; #ifdef md_flush_pending_output @@ -551,7 +552,8 @@ obj_elf_change_section (const char *name else sec = subseg_force_new (name, 0); - ssect = _bfd_elf_get_sec_type_attr (stdoutput, name); + bed = get_elf_backend_data (stdoutput); + ssect = (*bed->get_sec_type_attr) (stdoutput, sec); if (ssect != NULL) { diff -uprN binutils-2.16.91.0.1/gas/config/obj-elf.h binutils-2.16.91.0.2/gas/config/obj-elf.h --- binutils-2.16.91.0.1/gas/config/obj-elf.h 2005-05-10 15:46:44.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/obj-elf.h 2005-07-20 12:27:27.756116707 -0700 @@ -241,9 +241,7 @@ extern void elf_pop_insert (void); #ifndef OBJ_MAYBE_ELF #define obj_ecoff_set_ext elf_ecoff_set_ext -#ifdef ANSI_PROTOTYPES struct ecoff_extr; -#endif extern void elf_ecoff_set_ext (symbolS *, struct ecoff_extr *); #endif diff -uprN binutils-2.16.91.0.1/gas/config/tc-arm.c binutils-2.16.91.0.2/gas/config/tc-arm.c --- binutils-2.16.91.0.1/gas/config/tc-arm.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-arm.c 2005-07-20 12:27:27.777113245 -0700 @@ -226,17 +226,17 @@ struct arm_it struct { unsigned reg; - unsigned imm; - unsigned present : 1; /* operand present */ - unsigned isreg : 1; /* operand was a register */ - unsigned immisreg : 1; /* .imm field is a second register */ - unsigned hasreloc : 1; /* operand has relocation suffix */ - unsigned writeback : 1; /* operand has trailing ! */ - unsigned preind : 1; /* preindexed address */ - unsigned postind : 1; /* postindexed address */ - unsigned negative : 1; /* index register was negated */ - unsigned shifted : 1; /* shift applied to operation */ - unsigned shift_kind : 3; /* shift operation (enum shift_kind) */ + signed int imm; + unsigned present : 1; /* Operand present. */ + unsigned isreg : 1; /* Operand was a register. */ + unsigned immisreg : 1; /* .imm field is a second register. */ + unsigned hasreloc : 1; /* Operand has relocation suffix. */ + unsigned writeback : 1; /* Operand has trailing ! */ + unsigned preind : 1; /* Preindexed address. */ + unsigned postind : 1; /* Postindexed address. */ + unsigned negative : 1; /* Index register was negated. */ + unsigned shifted : 1; /* Shift applied to operation. */ + unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ } operands[6]; }; @@ -485,7 +485,7 @@ struct asm_opcode #define T_OPCODE_PUSH 0xb400 #define T_OPCODE_POP 0xbc00 -#define T_OPCODE_BRANCH 0xe7fe +#define T_OPCODE_BRANCH 0xe000 #define THUMB_SIZE 2 /* Size of thumb instruction. */ #define THUMB_PP_PC_LR 0x0100 @@ -1035,7 +1035,7 @@ parse_reg_list (char ** strp) register. Double precision registers are matched if DP is nonzero. */ static int -parse_vfp_reg_list (char **str, int *pbase, int dp) +parse_vfp_reg_list (char **str, unsigned int *pbase, int dp) { int base_reg; int new_base; @@ -1970,8 +1970,15 @@ s_arm_elf_cons (int nbytes) reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc); int size = bfd_get_reloc_size (howto); + if (reloc == BFD_RELOC_ARM_PLT32) + { + as_bad (_("(plt) is only valid on branch targets")); + reloc = BFD_RELOC_UNUSED; + size = 0; + } + if (size > nbytes) - as_bad ("%s relocations do not fit in %d bytes", + as_bad (_("%s relocations do not fit in %d bytes"), howto->name, nbytes); else { @@ -2328,7 +2335,7 @@ static void s_arm_unwind_save_vfp (void) { int count; - int reg; + unsigned int reg; valueT op; count = parse_vfp_reg_list (&input_line_pointer, ®, 1); @@ -3239,7 +3246,7 @@ parse_address (char **str, int i) { /* [Rn], {expr} - unindexed, with option */ if (parse_immediate (&p, &inst.operands[i].imm, - 0, 255, TRUE) == FAIL) + 0, 255, TRUE) == FAIL) return FAIL; if (skip_past_char (&p, '}') == FAIL) @@ -3567,7 +3574,7 @@ enum operand_parse_code structure. Returns SUCCESS or FAIL depending on whether the specified grammar matched. */ static int -parse_operands (char *str, const char *pattern) +parse_operands (char *str, const unsigned char *pattern) { unsigned const char *upat = pattern; char *backtrack_pos = 0; @@ -4075,8 +4082,6 @@ encode_arm_addr_mode_2 (int i, bfd_boole { if (inst.reloc.type == BFD_RELOC_UNUSED) inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM; - if (inst.reloc.pc_rel) - inst.reloc.exp.X_add_number -= 8; /* pipeline offset */ } } @@ -4107,8 +4112,6 @@ encode_arm_addr_mode_3 (int i, bfd_boole inst.instruction |= HWOFFSET_IMM; if (inst.reloc.type == BFD_RELOC_UNUSED) inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8; - if (inst.reloc.pc_rel) - inst.reloc.exp.X_add_number -= 8; /* pipeline offset */ } } @@ -4161,8 +4164,6 @@ encode_arm_cp_address (int i, int wb_ok, inst.reloc.type = reloc_override; else inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM; - if (inst.reloc.pc_rel) - inst.reloc.exp.X_add_number -= 8; return SUCCESS; } @@ -4329,10 +4330,8 @@ do_adr (void) /* Frag hacking will turn this into a sub instruction if the offset turns out to be negative. */ inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE; -#ifndef TE_WINCE - inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */ -#endif inst.reloc.pc_rel = 1; + inst.reloc.exp.X_add_number -= 8; } /* This is a pseudo-op of the form "adrl rd, label" to be converted @@ -4348,11 +4347,9 @@ do_adrl (void) /* Frag hacking will turn this into a sub instruction if the offset turns out to be negative. */ inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE; -#ifndef TE_WINCE - inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */ -#endif inst.reloc.pc_rel = 1; inst.size = INSN_SIZE * 2; + inst.reloc.exp.X_add_number -= 8; } static void @@ -4432,13 +4429,12 @@ encode_branch (int default_reloc) constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32, _("the only suffix valid here is '(plt)'")); inst.reloc.type = BFD_RELOC_ARM_PLT32; - inst.reloc.pc_rel = 0; } else { inst.reloc.type = default_reloc; - inst.reloc.pc_rel = 1; } + inst.reloc.pc_rel = 1; } static void @@ -4472,7 +4468,7 @@ do_blx (void) /* Arg is an address; this instruction cannot be executed conditionally, and the opcode must be adjusted. */ constraint (inst.cond != COND_ALWAYS, BAD_COND); - inst.instruction = 0xfafffffe; + inst.instruction = 0xfa000000; encode_branch (BFD_RELOC_ARM_PCREL_BLX); } } @@ -4649,8 +4645,8 @@ do_ldrd (void) /* For an index-register load, the index register must not overlap the destination (even if not write-back). */ else if (inst.operands[2].immisreg - && (inst.operands[2].imm == inst.operands[0].reg - || inst.operands[2].imm == inst.operands[1].reg)) + && ((unsigned) inst.operands[2].imm == inst.operands[0].reg + || (unsigned) inst.operands[2].imm == inst.operands[1].reg)) as_warn (_("index register overlaps destination register")); } @@ -6128,7 +6124,7 @@ do_t_blx (void) else { /* No register. This must be BLX(1). */ - inst.instruction = 0xf7ffeffe; + inst.instruction = 0xf000e800; inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX; inst.reloc.pc_rel = 1; } @@ -6141,13 +6137,13 @@ do_t_branch (void) { if (inst.cond == COND_ALWAYS) { - inst.instruction = 0xf7ffbffe; + inst.instruction = 0xf000b000; inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25; } else { assert (inst.cond != 0xF); - inst.instruction = (inst.cond << 22) | 0xf43faffe; + inst.instruction = (inst.cond << 22) | 0xf0008000; inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20; } } @@ -6157,7 +6153,7 @@ do_t_branch (void) inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12; else { - inst.instruction = 0xd0fe | (inst.cond << 8); + inst.instruction = 0xd000 | (inst.cond << 8); inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9; } } @@ -8123,19 +8119,13 @@ static const struct asm_opcode insns[] = tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm), TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi), -#ifdef TE_WINCE - /* XXX This is the wrong place to do this. Think multi-arch. */ - TCE(b, a000000, e7fe, 1, (EXPr), branch, t_branch), - TCE(bl, b000000, f7fffffe, 1, (EXPr), branch, t_branch23), -#else - TCE(b, afffffe, e7fe, 1, (EXPr), branch, t_branch), - TCE(bl, bfffffe, f7fffffe, 1, (EXPr), branch, t_branch23), -#endif + TCE(b, a000000, e000, 1, (EXPr), branch, t_branch), + TCE(bl, b000000, f000f800, 1, (EXPr), branch, t_branch23), /* Pseudo ops. */ - TCE(adr, 28f0000, 000f, 2, (RR, EXP), adr, t_adr), - C3(adrl, 28f0000, 2, (RR, EXP), adrl), - tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop), + TCE(adr, 28f0000, 000f, 2, (RR, EXP), adr, t_adr), + C3(adrl, 28f0000, 2, (RR, EXP), adrl), + tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop), /* Thumb-compatibility pseudo ops. */ tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift), @@ -8143,7 +8133,7 @@ static const struct asm_opcode insns[] = tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift), tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift), tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift), - tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift), + tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift), tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift), tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift), tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg), @@ -8153,7 +8143,7 @@ static const struct asm_opcode insns[] = #undef THUMB_VARIANT #define THUMB_VARIANT ARM_EXT_V6 - TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), + TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy), /* V1 instructions with no Thumb analogue prior to V6T2. */ #undef THUMB_VARIANT @@ -8170,7 +8160,7 @@ static const struct asm_opcode insns[] = TC3(strbt, 4600000, f8200e00, 2, (RR, ADDR), ldstt, t_ldstt), TC3(stmdb, 9000000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), - TC3(stmfd, 9000000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), + TC3(stmfd, 9000000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm), TC3(ldmdb, 9100000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), TC3(ldmea, 9100000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm), @@ -9898,41 +9888,75 @@ tc_arm_frame_initial_instructions (void) /* MD interface: Symbol and relocation handling. */ -/* The knowledge of the PC's pipeline offset is built into the insns - themselves. */ +/* Return the address within the segment that a PC-relative fixup is + relative to. For ARM, PC-relative fixups applied to instructions + are generally relative to the location of the fixup plus 8 bytes. + Thumb branches are offset by 4, and Thumb loads relative to PC + require special handling. */ long -md_pcrel_from (fixS * fixP) +md_pcrel_from_section (fixS * fixP, segT seg) { - if (fixP->fx_addsy - && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section - && fixP->fx_subsy == NULL) - return 0; + offsetT base = fixP->fx_where + fixP->fx_frag->fr_address; + + /* If this is pc-relative and we are going to emit a relocation + then we just want to put out any pipeline compensation that the linker + will need. Otherwise we want to use the calculated base. */ + if (fixP->fx_pcrel + && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg) + || arm_force_relocation (fixP))) + base = 0; - /* PC relative addressing on the Thumb is slightly odd as the bottom - two bits of the PC are forced to zero for the calculation. This - happens *after* application of the pipeline offset. However, - Thumb adrl already adjusts for this, so we need not do it again. */ switch (fixP->fx_r_type) { + /* PC relative addressing on the Thumb is slightly odd as the + bottom two bits of the PC are forced to zero for the + calculation. This happens *after* application of the + pipeline offset. However, Thumb adrl already adjusts for + this, so we need not do it again. */ case BFD_RELOC_ARM_THUMB_ADD: - return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3; + return base & ~3; case BFD_RELOC_ARM_THUMB_OFFSET: case BFD_RELOC_ARM_T32_OFFSET_IMM: - return (fixP->fx_where + fixP->fx_frag->fr_address + 4) & ~3; + return (base + 4) & ~3; - default: - break; - } + /* Thumb branches are simply offset by +4. */ + case BFD_RELOC_THUMB_PCREL_BRANCH7: + case BFD_RELOC_THUMB_PCREL_BRANCH9: + case BFD_RELOC_THUMB_PCREL_BRANCH12: + case BFD_RELOC_THUMB_PCREL_BRANCH20: + case BFD_RELOC_THUMB_PCREL_BRANCH23: + case BFD_RELOC_THUMB_PCREL_BRANCH25: + case BFD_RELOC_THUMB_PCREL_BLX: + return base + 4; + /* ARM mode branches are offset by +8. However, the Windows CE + loader expects the relocation not to take this into account. */ + case BFD_RELOC_ARM_PCREL_BRANCH: + case BFD_RELOC_ARM_PCREL_BLX: + case BFD_RELOC_ARM_PLT32: #ifdef TE_WINCE - /* The pattern was adjusted to accommodate CE's off-by-one fixups, - so we un-adjust here to compensate for the accommodation. */ - return fixP->fx_where + fixP->fx_frag->fr_address + 8; + return base; #else - return fixP->fx_where + fixP->fx_frag->fr_address; + return base + 8; #endif + + /* ARM mode loads relative to PC are also offset by +8. Unlike + branches, the Windows CE loader *does* expect the relocation + to take this into account. */ + case BFD_RELOC_ARM_OFFSET_IMM: + case BFD_RELOC_ARM_OFFSET_IMM8: + case BFD_RELOC_ARM_HWLITERAL: + case BFD_RELOC_ARM_LITERAL: + case BFD_RELOC_ARM_CP_OFF_IMM: + return base + 8; + + + /* Other PC-relative relocations are un-offset. */ + default: + return base; + } } /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. @@ -10115,17 +10139,6 @@ md_apply_fix (fixS * fixP, if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) fixP->fx_done = 1; - /* If this symbol is in a different section then we need to leave it for - the linker to deal with. Unfortunately, md_pcrel_from can't tell, - so we have to undo its effects here. */ - if (fixP->fx_pcrel) - { - if (fixP->fx_addsy != NULL - && S_IS_DEFINED (fixP->fx_addsy) - && S_GET_SEGMENT (fixP->fx_addsy) != seg) - value += md_pcrel_from (fixP); - } - /* On a 64-bit host, silently truncate 'value' to 32 bits for consistency with the behavior on 32-bit hosts. Remember value for emit_reloc. */ @@ -10286,7 +10299,6 @@ md_apply_fix (fixS * fixP, value /= 4; newval = md_chars_to_number (buf+2, THUMB_SIZE); - newval &= 0xff00; newval |= value; md_number_to_chars (buf+2, newval, THUMB_SIZE); break; @@ -10457,7 +10469,6 @@ md_apply_fix (fixS * fixP, break; } - newval &= 0xfbff8f00; newval |= (newimm & 0x800) << 15; newval |= (newimm & 0x700) << 4; newval |= (newimm & 0x0ff); @@ -10470,7 +10481,7 @@ md_apply_fix (fixS * fixP, if (((unsigned long) value) > 0xffff) as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid smi expression")); - newval = md_chars_to_number (buf, INSN_SIZE) & 0xfff000f0; + newval = md_chars_to_number (buf, INSN_SIZE); newval |= (value & 0xf) | ((value & 0xfff0) << 4); md_number_to_chars (buf, newval, INSN_SIZE); break; @@ -10481,7 +10492,7 @@ md_apply_fix (fixS * fixP, if (((unsigned long) value) > 0xff) as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid swi expression")); - newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00; + newval = md_chars_to_number (buf, THUMB_SIZE); newval |= value; md_number_to_chars (buf, newval, THUMB_SIZE); } @@ -10490,7 +10501,7 @@ md_apply_fix (fixS * fixP, if (((unsigned long) value) > 0x00ffffff) as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid swi expression")); - newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000; + newval = md_chars_to_number (buf, INSN_SIZE); newval |= value; md_number_to_chars (buf, newval, INSN_SIZE); } @@ -10505,358 +10516,180 @@ md_apply_fix (fixS * fixP, break; case BFD_RELOC_ARM_PCREL_BRANCH: - newval = md_chars_to_number (buf, INSN_SIZE); - - /* Sign-extend a 24-bit number. */ -#define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000) - #ifdef OBJ_ELF - if (!fixP->fx_done) - value = fixP->fx_offset; + case BFD_RELOC_ARM_PLT32: #endif /* We are going to store value (shifted right by two) in the - instruction, in a 24 bit, signed field Thus we need to check - that none of the top 8 bits of the shifted value (top 7 bits of - the unshifted, unsigned value) are set, or that they are all set. */ - if ((value & ~ ((offsetT) 0x1ffffff)) != 0 - && ((value & ~ ((offsetT) 0x1ffffff)) != ~ ((offsetT) 0x1ffffff))) - { -#ifdef OBJ_ELF - /* Normally we would be stuck at this point, since we cannot store - the absolute address that is the destination of the branch in the - 24 bits of the branch instruction. If however, we happen to know - that the destination of the branch is in the same section as the - branch instruction itself, then we can compute the relocation for - ourselves and not have to bother the linker with it. - - FIXME: The test for OBJ_ELF is only here because I have not - worked out how to do this for OBJ_COFF. */ - if (fixP->fx_addsy != NULL - && S_IS_DEFINED (fixP->fx_addsy) - && S_GET_SEGMENT (fixP->fx_addsy) == seg) - { - /* Get pc relative value to go into the branch. */ - value = * valP; - - /* Permit a backward branch provided that enough bits - are set. Allow a forwards branch, provided that - enough bits are clear. */ - if ( (value & ~ ((offsetT) 0x1ffffff)) == ~ ((offsetT) 0x1ffffff) - || (value & ~ ((offsetT) 0x1ffffff)) == 0) - fixP->fx_done = 1; - } - - if (! fixP->fx_done) -#endif - as_bad_where (fixP->fx_file, fixP->fx_line, - _("GAS can't handle same-section branch dest >= 0x04000000")); - } - - value >>= 2; - value += SEXT24 (newval); - - if ( (value & ~ ((offsetT) 0xffffff)) != 0 - && ((value & ~ ((offsetT) 0xffffff)) != ~ ((offsetT) 0xffffff))) + instruction, in a 24 bit, signed field. Bits 0 and 1 must be + clear, and bits 26 through 32 either all clear or all set. */ + if (value & 0x00000003) as_bad_where (fixP->fx_file, fixP->fx_line, - _("out of range branch")); + _("misaligned branch destination")); + if ((value & (offsetT)0xfe000000) != (offsetT)0 + && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("branch out of range")); - if (seg->use_rela_p && !fixP->fx_done) + if (fixP->fx_done || !seg->use_rela_p) { - /* Must unshift the value before storing it in the addend. */ - value <<= 2; -#ifdef OBJ_ELF - fixP->fx_offset = value; -#endif - fixP->fx_addnumber = value; - newval = newval & 0xff000000; + newval = md_chars_to_number (buf, INSN_SIZE); + newval |= (value >> 2) & 0x00ffffff; + md_number_to_chars (buf, newval, INSN_SIZE); } - else - newval = (value & 0x00ffffff) | (newval & 0xff000000); - md_number_to_chars (buf, newval, INSN_SIZE); break; case BFD_RELOC_ARM_PCREL_BLX: - { - offsetT hbit; - newval = md_chars_to_number (buf, INSN_SIZE); + /* BLX allows bit 1 to be set in the branch destination, since + it targets a Thumb instruction which is only required to be + aligned modulo 2. Other constraints are as for B/BL. */ + if (value & 0x00000001) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("misaligned BLX destination")); + if ((value & (offsetT)0xfe000000) != (offsetT)0 + && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("branch out of range")); -#ifdef OBJ_ELF - if (!fixP->fx_done) - value = fixP->fx_offset; -#endif - hbit = (value >> 1) & 1; - value = (value >> 2) & 0x00ffffff; - value = (value + (newval & 0x00ffffff)) & 0x00ffffff; + if (fixP->fx_done || !seg->use_rela_p) + { + offsetT hbit; + hbit = (value >> 1) & 1; + value = (value >> 2) & 0x00ffffff; - if (seg->use_rela_p && !fixP->fx_done) - { - /* Must sign-extend and unshift the value before storing - it in the addend. */ - value = SEXT24 (value); - value = (value << 2) | hbit; -#ifdef OBJ_ELF - fixP->fx_offset = value; -#endif - fixP->fx_addnumber = value; - newval = newval & 0xfe000000; - } - else - newval = value | (newval & 0xfe000000) | (hbit << 24); - md_number_to_chars (buf, newval, INSN_SIZE); - } + newval = md_chars_to_number (buf, INSN_SIZE); + newval |= value | hbit << 24; + md_number_to_chars (buf, newval, INSN_SIZE); + } break; case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CZB */ - newval = md_chars_to_number (buf, THUMB_SIZE); - { - addressT diff = ((newval & 0x00f8) >> 2) | (newval & 0x0200) >> 3; - /* This one does not have the offset encoded in the pattern. */ - value = value + diff - 4; - /* CZB can only branch forward. */ - if (value & ~0x7e) - as_bad_where (fixP->fx_file, fixP->fx_line, - _("branch out of range")); + /* CZB can only branch forward. */ + if (value & ~0x7e) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("branch out of range")); - newval &= 0xfd07; - if (seg->use_rela_p && !fixP->fx_done) - { -#ifdef OBJ_ELF - fixP->fx_offset = value; -#endif - fixP->fx_addnumber = value; - } - else + if (fixP->fx_done || !seg->use_rela_p) + { + newval = md_chars_to_number (buf, THUMB_SIZE); newval |= ((value & 0x2e) << 2) | ((value & 0x40) << 3); - } - md_number_to_chars (buf, newval, THUMB_SIZE); + md_number_to_chars (buf, newval, THUMB_SIZE); + } break; case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */ - newval = md_chars_to_number (buf, THUMB_SIZE); - { - addressT diff = (newval & 0xff) << 1; - if (diff & 0x100) - diff |= ~0xff; + if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("branch out of range")); - value += diff; - if ((value & ~0xff) && ((value & ~0xff) != ~0xff)) - as_bad_where (fixP->fx_file, fixP->fx_line, - _("branch out of range")); - if (seg->use_rela_p && !fixP->fx_done) - { -#ifdef OBJ_ELF - fixP->fx_offset = value; -#endif - fixP->fx_addnumber = value; - newval = newval & 0xff00; - } - else - newval = (newval & 0xff00) | ((value & 0x1ff) >> 1); - } - md_number_to_chars (buf, newval, THUMB_SIZE); + if (fixP->fx_done || !seg->use_rela_p) + { + newval = md_chars_to_number (buf, THUMB_SIZE); + newval |= (value & 0x1ff) >> 1; + md_number_to_chars (buf, newval, THUMB_SIZE); + } break; case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */ - newval = md_chars_to_number (buf, THUMB_SIZE); - { - addressT diff = (newval & 0x7ff) << 1; - if (diff & 0x800) - diff |= ~0x7ff; + if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("branch out of range")); - value += diff; - if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff)) - as_bad_where (fixP->fx_file, fixP->fx_line, - _("branch out of range")); - if (seg->use_rela_p && !fixP->fx_done) - { -#ifdef OBJ_ELF - fixP->fx_offset = value; -#endif - fixP->fx_addnumber = value; - newval = newval & 0xf800; - } - else - newval = (newval & 0xf800) | ((value & 0xfff) >> 1); - } - md_number_to_chars (buf, newval, THUMB_SIZE); + if (fixP->fx_done || !seg->use_rela_p) + { + newval = md_chars_to_number (buf, THUMB_SIZE); + newval |= (value & 0xfff) >> 1; + md_number_to_chars (buf, newval, THUMB_SIZE); + } break; case BFD_RELOC_THUMB_PCREL_BRANCH20: - { - offsetT newval2; - addressT diff, S, J1, J2, lo, hi; - - newval = md_chars_to_number (buf, THUMB_SIZE); - newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); - - S = !(newval & 0x0400); /* flipped - 0=negative */ - hi = (newval & 0x003f); - J1 = (newval2 & 0x2000) >> 13; - J2 = (newval2 & 0x0800) >> 11; - lo = (newval2 & 0x07ff); - - diff = ((S << 20) | (J2 << 19) | (J1 << 18) | (hi << 12) | (lo << 1)); - diff -= (1 << 20); /* sign extend */ - value += diff; - - if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) - as_bad_where (fixP->fx_file, fixP->fx_line, - _("conditional branch out of range")); - - newval = newval & 0xfbc0; - newval2 = newval2 & 0xd000; - if (seg->use_rela_p && !fixP->fx_done) - { -#ifdef OBJ_ELF - fixP->fx_offset = value; -#endif - fixP->fx_addnumber = value; - } - else - { - S = (value & 0x00100000) >> 20; - J2 = (value & 0x00080000) >> 19; - J1 = (value & 0x00040000) >> 18; - hi = (value & 0x0003f000) >> 12; - lo = (value & 0x00000ffe) >> 1; + if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff)) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("conditional branch out of range")); - newval = newval | (S << 10) | hi; - newval2 = newval2 | (J1 << 13) | (J2 << 11) | lo; - } + if (fixP->fx_done || !seg->use_rela_p) + { + offsetT newval2; + addressT S, J1, J2, lo, hi; - md_number_to_chars (buf, newval, THUMB_SIZE); - md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); - } + S = (value & 0x00100000) >> 20; + J2 = (value & 0x00080000) >> 19; + J1 = (value & 0x00040000) >> 18; + hi = (value & 0x0003f000) >> 12; + lo = (value & 0x00000ffe) >> 1; + + newval = md_chars_to_number (buf, THUMB_SIZE); + newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); + newval |= (S << 10) | hi; + newval2 |= (J1 << 13) | (J2 << 11) | lo; + md_number_to_chars (buf, newval, THUMB_SIZE); + md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); + } break; case BFD_RELOC_THUMB_PCREL_BLX: case BFD_RELOC_THUMB_PCREL_BRANCH23: - { - offsetT newval2; - addressT diff; - - newval = md_chars_to_number (buf, THUMB_SIZE); - newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); - diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1); - if (diff & 0x400000) - diff |= ~0x3fffff; -#ifdef OBJ_ELF - if (!fixP->fx_done) - value = fixP->fx_offset; -#endif - value += diff; - - if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) - as_bad_where (fixP->fx_file, fixP->fx_line, - _("branch with link out of range")); - - if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) - /* For a BLX instruction, make sure that the relocation is rounded up - to a word boundary. This follows the semantics of the instruction - which specifies that bit 1 of the target address will come from bit - 1 of the base address. */ - value = (value + 1) & ~ 1; - - if (seg->use_rela_p && !fixP->fx_done) - { -#ifdef OBJ_ELF - fixP->fx_offset = value; -#endif - fixP->fx_addnumber = value; - newval = newval & 0xf800; - newval2 = newval2 & 0xf800; - } - else - { - newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12); - newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1); - } - md_number_to_chars (buf, newval, THUMB_SIZE); - md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); - } - break; + if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff)) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("branch out of range")); - case BFD_RELOC_8: - if (seg->use_rela_p && !fixP->fx_done) - break; - if (fixP->fx_done || fixP->fx_pcrel) - md_number_to_chars (buf, value, 1); -#ifdef OBJ_ELF - else - { - value = fixP->fx_offset; - md_number_to_chars (buf, value, 1); + if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX) + /* For a BLX instruction, make sure that the relocation is rounded up + to a word boundary. This follows the semantics of the instruction + which specifies that bit 1 of the target address will come from bit + 1 of the base address. */ + value = (value + 1) & ~ 1; + + if (fixP->fx_done || !seg->use_rela_p) + { + offsetT newval2; + + newval = md_chars_to_number (buf, THUMB_SIZE); + newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); + newval |= (value & 0x7fffff) >> 12; + newval2 |= (value & 0xfff) >> 1; + md_number_to_chars (buf, newval, THUMB_SIZE); + md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); } -#endif break; case BFD_RELOC_THUMB_PCREL_BRANCH25: - { - offsetT newval2; - addressT diff, S, I1, I2, lo, hi; - - newval = md_chars_to_number (buf, THUMB_SIZE); - newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); - - S = (newval & 0x0400) >> 10; - hi = (newval & 0x03ff); - I1 = (newval2 & 0x2000) >> 13; - I2 = (newval2 & 0x0800) >> 11; - lo = (newval2 & 0x07ff); - - I1 = !(I1 ^ S); - I2 = !(I2 ^ S); - S = !S; - - diff = ((S << 24) | (I1 << 23) | (I2 << 22) | (hi << 12) | (lo << 1)); - diff -= (1 << 24); /* sign extend */ - value += diff; - - if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) - as_bad_where (fixP->fx_file, fixP->fx_line, - _("branch out of range")); + if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff)) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("branch out of range")); - newval = newval & 0xf800; - newval2 = newval2 & 0xd000; - if (seg->use_rela_p && !fixP->fx_done) - { -#ifdef OBJ_ELF - fixP->fx_offset = value; -#endif - fixP->fx_addnumber = value; - } - else - { - S = (value & 0x01000000) >> 24; - I1 = (value & 0x00800000) >> 23; - I2 = (value & 0x00400000) >> 22; - hi = (value & 0x003ff000) >> 12; - lo = (value & 0x00000ffe) >> 1; + if (fixP->fx_done || !seg->use_rela_p) + { + offsetT newval2; + addressT S, I1, I2, lo, hi; - I1 = !(I1 ^ S); - I2 = !(I2 ^ S); + S = (value & 0x01000000) >> 24; + I1 = (value & 0x00800000) >> 23; + I2 = (value & 0x00400000) >> 22; + hi = (value & 0x003ff000) >> 12; + lo = (value & 0x00000ffe) >> 1; + + I1 = !(I1 ^ S); + I2 = !(I2 ^ S); + + newval = md_chars_to_number (buf, THUMB_SIZE); + newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE); + newval |= (S << 10) | hi; + newval2 |= (I1 << 13) | (I2 << 11) | lo; + md_number_to_chars (buf, newval, THUMB_SIZE); + md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); + } + break; - newval = newval | (S << 10) | hi; - newval2 = newval2 | (I1 << 13) | (I2 << 11) | lo; - } - md_number_to_chars (buf, newval, THUMB_SIZE); - md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE); - } + case BFD_RELOC_8: + if (fixP->fx_done || !seg->use_rela_p) + md_number_to_chars (buf, value, 1); break; case BFD_RELOC_16: - if (seg->use_rela_p && !fixP->fx_done) - break; - if (fixP->fx_done || fixP->fx_pcrel) + if (fixP->fx_done || !seg->use_rela_p) md_number_to_chars (buf, value, 2); -#ifdef OBJ_ELF - else - { - value = fixP->fx_offset; - md_number_to_chars (buf, value, 2); - } -#endif break; #ifdef OBJ_ELF @@ -10871,9 +10704,8 @@ md_apply_fix (fixS * fixP, case BFD_RELOC_ARM_GOT32: case BFD_RELOC_ARM_GOTOFF: case BFD_RELOC_ARM_TARGET2: - if (seg->use_rela_p && !fixP->fx_done) - break; - md_number_to_chars (buf, 0, 4); + if (fixP->fx_done || !seg->use_rela_p) + md_number_to_chars (buf, 0, 4); break; #endif @@ -10883,22 +10715,13 @@ md_apply_fix (fixS * fixP, case BFD_RELOC_ARM_ROSEGREL32: case BFD_RELOC_ARM_SBREL32: case BFD_RELOC_32_PCREL: - if (seg->use_rela_p && !fixP->fx_done) - break; - if (fixP->fx_done || fixP->fx_pcrel) + if (fixP->fx_done || !seg->use_rela_p) md_number_to_chars (buf, value, 4); -#ifdef OBJ_ELF - else - { - value = fixP->fx_offset; - md_number_to_chars (buf, value, 4); - } -#endif break; #ifdef OBJ_ELF case BFD_RELOC_ARM_PREL31: - if (fixP->fx_done || fixP->fx_pcrel) + if (fixP->fx_done || !seg->use_rela_p) { newval = md_chars_to_number (buf, 4) & 0x80000000; if ((value ^ (value >> 1)) & 0x40000000) @@ -10910,10 +10733,6 @@ md_apply_fix (fixS * fixP, md_number_to_chars (buf, newval, 4); } break; - - case BFD_RELOC_ARM_PLT32: - /* It appears the instruction is fully prepared at this point. */ - break; #endif case BFD_RELOC_ARM_CP_OFF_IMM: @@ -11135,15 +10954,9 @@ tc_gen_reloc (asection * section ATTRIBU *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; - /* @@ Why fx_addnumber sometimes and fx_offset other times? */ -#ifndef OBJ_ELF - if (fixp->fx_pcrel == 0) - reloc->addend = fixp->fx_offset; - else - reloc->addend = fixp->fx_offset = reloc->address; -#else /* OBJ_ELF */ + if (fixp->fx_pcrel) + fixp->fx_offset = reloc->address; reloc->addend = fixp->fx_offset; -#endif switch (fixp->fx_r_type) { diff -uprN binutils-2.16.91.0.1/gas/config/tc-arm.h binutils-2.16.91.0.2/gas/config/tc-arm.h --- binutils-2.16.91.0.1/gas/config/tc-arm.h 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-arm.h 2005-07-20 12:27:27.778113080 -0700 @@ -211,6 +211,9 @@ struct arm_segment_info_type #endif +#define MD_PCREL_FROM_SECTION(F,S) md_pcrel_from_section(F,S) + +extern long md_pcrel_from_section (struct fix *, segT); extern void arm_frag_align_code (int, int); extern void arm_validate_fix (struct fix *); extern const char * elf32_arm_target_format (void); diff -uprN binutils-2.16.91.0.1/gas/config/tc-cris.h binutils-2.16.91.0.2/gas/config/tc-cris.h --- binutils-2.16.91.0.1/gas/config/tc-cris.h 2005-05-10 15:46:44.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-cris.h 2005-07-20 12:27:27.784112091 -0700 @@ -114,6 +114,13 @@ extern int md_cris_force_relocation (str && (! IS_CRIS_PIC_RELOC ((FIX)->fx_r_type) \ || (FIX)->fx_r_type == BFD_RELOC_CRIS_32_GOTREL)) +/* FIXME: This *should* be a redundant definition, as the + TC_FORCE_RELOCATION* definitions already told about the cases where + we *don't* want the symbol value calculated. Here we seem to answer + the "are you sure" question. It certainly has very little to do with + whether the symbol value is passed to md_apply_fix. */ +#define MD_APPLY_SYM_VALUE(FIX) 0 + /* When we have fixups against constant expressions, we get a GAS-specific section symbol at no extra charge for obscure reasons in adjust_reloc_syms. Since ELF outputs section symbols, it gladly diff -uprN binutils-2.16.91.0.1/gas/config/tc-crx.c binutils-2.16.91.0.2/gas/config/tc-crx.c --- binutils-2.16.91.0.1/gas/config/tc-crx.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-crx.c 2005-07-20 12:27:27.786111761 -0700 @@ -268,7 +268,8 @@ reset_vars (char *op) memset (& output_opcode, '\0', sizeof (output_opcode)); /* Save a copy of the original OP (used in error messages). */ - strcpy (ins_parse, op); + strncpy (ins_parse, op, sizeof ins_parse - 1); + ins_parse [sizeof ins_parse - 1] = 0; } /* This macro decides whether a particular reloc is an entry in a diff -uprN binutils-2.16.91.0.1/gas/config/tc-h8300.h binutils-2.16.91.0.2/gas/config/tc-h8300.h --- binutils-2.16.91.0.1/gas/config/tc-h8300.h 2005-05-10 15:46:44.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-h8300.h 2005-07-20 12:27:27.799109618 -0700 @@ -37,10 +37,8 @@ #define FAKE_LABEL_NAME ".L0\001" #endif -#if ANSI_PROTOTYPES struct fix; struct internal_reloc; -#endif #define WORKING_DOT_WORD diff -uprN binutils-2.16.91.0.1/gas/config/tc-h8500.h binutils-2.16.91.0.2/gas/config/tc-h8500.h --- binutils-2.16.91.0.1/gas/config/tc-h8500.h 2005-05-10 15:46:44.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-h8500.h 2005-07-20 12:27:27.799109618 -0700 @@ -23,9 +23,7 @@ #define TARGET_BYTES_BIG_ENDIAN 1 -#if ANSI_PROTOTYPES struct internal_reloc; -#endif #define WORKING_DOT_WORD diff -uprN binutils-2.16.91.0.1/gas/config/tc-hppa.c binutils-2.16.91.0.2/gas/config/tc-hppa.c --- binutils-2.16.91.0.1/gas/config/tc-hppa.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-hppa.c 2005-07-20 12:27:27.816106815 -0700 @@ -1577,10 +1577,12 @@ pa_ip (str) char *s, c, *argstart, *name, *save_s; const char *args; int match = FALSE; + int need_promotion = FALSE; int comma = 0; int cmpltr, nullif, flag, cond, num; unsigned long opcode; struct pa_opcode *insn; + struct pa_opcode *promoted_insn = NULL; #ifdef OBJ_SOM /* We must have a valid space and subspace. */ @@ -3064,6 +3066,8 @@ pa_ip (str) /* Handle 14 bit immediate, shifted left three times. */ case '#': + if (bfd_get_mach (stdoutput) != pa20) + break; the_insn.field_selector = pa_chk_field_selector (&s); get_expression (s); s = expr_end; @@ -3956,8 +3960,17 @@ pa_ip (str) if (match == TRUE && bfd_get_mach (stdoutput) < insn->arch) { - if (!bfd_set_arch_mach (stdoutput, bfd_arch_hppa, insn->arch)) - as_warn (_("could not update architecture and machine")); + if (need_promotion) + { + if (!bfd_set_arch_mach (stdoutput, bfd_arch_hppa, insn->arch)) + as_warn (_("could not update architecture and machine")); + } + else + { + match = FALSE; + if (!promoted_insn) + promoted_insn = insn; + } } failed: @@ -3973,6 +3986,13 @@ pa_ip (str) } else { + if (promoted_insn) + { + insn = promoted_insn; + need_promotion = TRUE; + s = argstart; + continue; + } as_bad (_("Invalid operands %s"), error_message); return; } diff -uprN binutils-2.16.91.0.1/gas/config/tc-i370.h binutils-2.16.91.0.2/gas/config/tc-i370.h --- binutils-2.16.91.0.1/gas/config/tc-i370.h 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-i370.h 2005-07-20 12:27:27.817106650 -0700 @@ -22,9 +22,7 @@ #define TC_I370 -#ifdef ANSI_PROTOTYPES struct fix; -#endif /* Set the endianness we are using. Default to big endian. */ #ifndef TARGET_BYTES_BIG_ENDIAN diff -uprN binutils-2.16.91.0.1/gas/config/tc-i386.c binutils-2.16.91.0.2/gas/config/tc-i386.c --- binutils-2.16.91.0.1/gas/config/tc-i386.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-i386.c 2005-07-20 12:27:27.824105496 -0700 @@ -429,12 +429,16 @@ static const arch_entry cpu_arch[] = { {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow }, {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA }, {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 }, + {"opteron", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 }, {".mmx", CpuMMX }, {".sse", CpuMMX|CpuMMX2|CpuSSE }, {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 }, + {".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 }, {".3dnow", CpuMMX|Cpu3dnow }, {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA }, {".padlock", CpuPadLock }, + {".pacifica", CpuSVME }, + {".svme", CpuSVME }, {NULL, 0 } }; @@ -1017,7 +1021,7 @@ md_begin () } #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) - if (OUTPUT_FLAVOR == bfd_target_elf_flavour) + if (IS_ELF) { record_alignment (text_section, 2); record_alignment (data_section, 2); @@ -1200,23 +1204,51 @@ pt (t) #endif /* DEBUG386 */ -static bfd_reloc_code_real_type reloc - PARAMS ((int, int, int, bfd_reloc_code_real_type)); - static bfd_reloc_code_real_type -reloc (size, pcrel, sign, other) - int size; - int pcrel; - int sign; - bfd_reloc_code_real_type other; +reloc (unsigned int size, + int pcrel, + int sign, + bfd_reloc_code_real_type other) { if (other != NO_RELOC) - return other; + { + reloc_howto_type *reloc; + + if (size == 8) + switch (other) + { + case BFD_RELOC_X86_64_TPOFF32: + other = BFD_RELOC_X86_64_TPOFF64; + break; + case BFD_RELOC_X86_64_DTPOFF32: + other = BFD_RELOC_X86_64_DTPOFF64; + break; + default: + break; + } + reloc = bfd_reloc_type_lookup (stdoutput, other); + if (!reloc) + as_bad (_("unknown relocation (%u)"), other); + else if (size != bfd_get_reloc_size (reloc)) + as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), + bfd_get_reloc_size (reloc), + size); + else if (pcrel && !reloc->pc_relative) + as_bad (_("non-pc-relative relocation for pc-relative field")); + else if ((reloc->complain_on_overflow == complain_overflow_signed + && !sign) + || (reloc->complain_on_overflow == complain_overflow_unsigned + && sign > 0)) + as_bad (_("relocated field and relocation type differ in signedness")); + else + return other; + return NO_RELOC; + } if (pcrel) { if (!sign) - as_bad (_("There are no unsigned pc-relative relocations")); + as_bad (_("there are no unsigned pc-relative relocations")); switch (size) { case 1: return BFD_RELOC_8_PCREL; @@ -1224,11 +1256,11 @@ reloc (size, pcrel, sign, other) case 4: return BFD_RELOC_32_PCREL; case 8: return BFD_RELOC_64_PCREL; } - as_bad (_("can not do %d byte pc-relative relocation"), size); + as_bad (_("cannot do %u byte pc-relative relocation"), size); } else { - if (sign) + if (sign > 0) switch (size) { case 4: return BFD_RELOC_X86_64_32S; @@ -1241,8 +1273,8 @@ reloc (size, pcrel, sign, other) case 4: return BFD_RELOC_32; case 8: return BFD_RELOC_64; } - as_bad (_("can not do %s %d byte relocation"), - sign ? "signed" : "unsigned", size); + as_bad (_("cannot do %s %u byte relocation"), + sign > 0 ? "signed" : "unsigned", size); } abort (); @@ -1259,7 +1291,7 @@ tc_i386_fix_adjustable (fixP) fixS *fixP ATTRIBUTE_UNUSED; { #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) - if (OUTPUT_FLAVOR != bfd_target_elf_flavour) + if (!IS_ELF) return 1; /* Don't adjust pc-relative references to merge sections in 64-bit @@ -1403,6 +1435,7 @@ md_assemble (line) have two immediate operands. */ if (intel_syntax && i.operands > 1 && (strcmp (mnemonic, "bound") != 0) + && (strcmp (mnemonic, "invlpga") != 0) && !((i.types[0] & Imm) && (i.types[1] & Imm))) swap_operands (); @@ -1639,6 +1672,15 @@ parse_insn (line, mnemonic) && current_templates && (current_templates->start->opcode_modifier & IsPrefix)) { + if (current_templates->start->cpu_flags + & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64)) + { + as_bad ((flag_code != CODE_64BIT + ? _("`%s' is only supported in 64-bit mode") + : _("`%s' is not supported in 64-bit mode")), + current_templates->start->name); + return NULL; + } /* If we are in 16-bit mode, do not allow addr16 or data16. Similarly, in 32-bit mode, do not allow addr32 or data32. */ if ((current_templates->start->opcode_modifier & (Size16 | Size32)) @@ -2045,16 +2087,16 @@ optimize_imm () switch (guess_suffix) { case QWORD_MNEM_SUFFIX: - i.types[op] = Imm64 | Imm32S; + i.types[op] &= Imm64 | Imm32S; break; case LONG_MNEM_SUFFIX: - i.types[op] = Imm32; + i.types[op] &= Imm32; break; case WORD_MNEM_SUFFIX: - i.types[op] = Imm16; + i.types[op] &= Imm16; break; case BYTE_MNEM_SUFFIX: - i.types[op] = Imm8 | Imm8S; + i.types[op] &= Imm8 | Imm8S; break; } break; @@ -2103,7 +2145,10 @@ optimize_disp () else if (flag_code == CODE_64BIT) { if (fits_in_signed_long (disp)) - i.types[op] |= Disp32S; + { + i.types[op] &= ~Disp64; + i.types[op] |= Disp32S; + } if (fits_in_unsigned_long (disp)) i.types[op] |= Disp32; } @@ -2846,8 +2891,10 @@ process_operands () default_seg = &ds; } - if (i.tm.base_opcode == 0x8d /* lea */ && i.seg[0] && !quiet_warnings) - as_warn (_("segment override on `lea' is ineffectual")); + if ((i.tm.base_opcode == 0x8d /* lea */ + || (i.tm.cpu_flags & CpuSVME)) + && i.seg[0] && !quiet_warnings) + as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); /* If a segment was explicitly specified, and the specified segment is not the default, use an opcode prefix to select it. If we @@ -3694,9 +3741,9 @@ output_imm (insn_start_frag, insn_start_ } } -#ifndef LEX_AT -static char *lex_got PARAMS ((enum bfd_reloc_code_real *, int *)); - +#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT) +# define lex_got(reloc, adjust, types) NULL +#else /* Parse operands of the form @GOTOFF+ and similar .plt or .got references. @@ -3707,32 +3754,36 @@ static char *lex_got PARAMS ((enum bfd_r is non-null set it to the length of the string we removed from the input line. Otherwise return NULL. */ static char * -lex_got (reloc, adjust) - enum bfd_reloc_code_real *reloc; - int *adjust; +lex_got (enum bfd_reloc_code_real *reloc, + int *adjust, + unsigned int *types) { static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" }; static const struct { const char *str; const enum bfd_reloc_code_real rel[NUM_FLAG_CODE]; + const unsigned int types64; } gotrel[] = { - { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } }, - { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, BFD_RELOC_X86_64_GOTOFF64 } }, - { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } }, - { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD } }, - { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } }, - { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD } }, - { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF } }, - { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 } }, - { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } }, - { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 } }, - { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 } }, - { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 } }, - { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } } + { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 }, + { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 }, + { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 }, + { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 }, + { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 }, 0 }, + { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 }, + { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 }, + { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 }, + { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 }, 0 }, + { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 }, + { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 }, 0 }, + { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 }, 0 }, + { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32 } }; char *cp; unsigned int j; + if (!IS_ELF) + return NULL; + for (cp = input_line_pointer; *cp != '@'; cp++) if (is_end_of_line[(unsigned char) *cp]) return NULL; @@ -3753,6 +3804,14 @@ lex_got (reloc, adjust) if (adjust) *adjust = len; + if (types) + { + if (flag_code != CODE_64BIT) + *types = Imm32|Disp32; + else + *types = gotrel[j].types64; + } + if (GOT_symbol == NULL) GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); @@ -3801,7 +3860,7 @@ x86_cons_fix_new (frag, off, len, exp) unsigned int len; expressionS *exp; { - enum bfd_reloc_code_real r = reloc (len, 0, 0, got_reloc); + enum bfd_reloc_code_real r = reloc (len, 0, -1, got_reloc); got_reloc = NO_RELOC; fix_new_exp (frag, off, len, exp, 0, r); } @@ -3819,7 +3878,7 @@ x86_cons (exp, size) int adjust; save = input_line_pointer; - gotfree_input_line = lex_got (&got_reloc, &adjust); + gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); if (gotfree_input_line) input_line_pointer = gotfree_input_line; @@ -3850,7 +3909,7 @@ x86_pe_cons_fix_new (frag, off, len, exp unsigned int len; expressionS *exp; { - enum bfd_reloc_code_real r = reloc (len, 0, 0, NO_RELOC); + enum bfd_reloc_code_real r = reloc (len, 0, -1, NO_RELOC); if (exp->X_op == O_secrel) { @@ -3890,11 +3949,10 @@ i386_immediate (imm_start) char *imm_start; { char *save_input_line_pointer; -#ifndef LEX_AT char *gotfree_input_line; -#endif segT exp_seg = 0; expressionS *exp; + unsigned int types = ~0U; if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) { @@ -3911,11 +3969,9 @@ i386_immediate (imm_start) save_input_line_pointer = input_line_pointer; input_line_pointer = imm_start; -#ifndef LEX_AT - gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); + gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); if (gotfree_input_line) input_line_pointer = gotfree_input_line; -#endif exp_seg = expression (exp); @@ -3924,10 +3980,8 @@ i386_immediate (imm_start) as_bad (_("junk `%s' after expression"), input_line_pointer); input_line_pointer = save_input_line_pointer; -#ifndef LEX_AT if (gotfree_input_line) free (gotfree_input_line); -#endif if (exp->X_op == O_absent || exp->X_op == O_big) { @@ -3967,6 +4021,7 @@ i386_immediate (imm_start) determined later, depending on destination register, suffix, or the default for the section. */ i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64; + i.types[this_operand] &= types; } return 1; @@ -4033,15 +4088,14 @@ i386_displacement (disp_start, disp_end) expressionS *exp; segT exp_seg = 0; char *save_input_line_pointer; -#ifndef LEX_AT char *gotfree_input_line; -#endif int bigdisp = Disp32; + unsigned int types = Disp; if (flag_code == CODE_64BIT) { if (i.prefix[ADDR_PREFIX] == 0) - bigdisp = Disp64; + bigdisp = Disp64 | Disp32S | Disp32; } else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) bigdisp = Disp16; @@ -4098,11 +4152,9 @@ i386_displacement (disp_start, disp_end) *displacement_string_end = '0'; } #endif -#ifndef LEX_AT - gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); + gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); if (gotfree_input_line) input_line_pointer = gotfree_input_line; -#endif exp_seg = expression (exp); @@ -4114,10 +4166,8 @@ i386_displacement (disp_start, disp_end) #endif RESTORE_END_STRING (disp_end); input_line_pointer = save_input_line_pointer; -#ifndef LEX_AT if (gotfree_input_line) free (gotfree_input_line); -#endif /* We do this to make sure that the section symbol is in the symbol table. We will ultimately change the relocation @@ -4173,8 +4223,10 @@ i386_displacement (disp_start, disp_end) return 0; } #endif - else if (flag_code == CODE_64BIT) - i.types[this_operand] |= Disp32S | Disp32; + + if (!(i.types[this_operand] & ~Disp)) + i.types[this_operand] &= types; + return 1; } @@ -4194,7 +4246,30 @@ i386_index_check (operand_string) tryprefix: #endif ok = 1; - if (flag_code == CODE_64BIT) + if ((current_templates->start->cpu_flags & CpuSVME) + && current_templates->end[-1].operand_types[0] == AnyMem) + { + /* Memory operands of SVME insns are special in that they only allow + rAX as their memory address and ignore any segment override. */ + unsigned RegXX; + + /* SKINIT is even more restrictive: it always requires EAX. */ + if (strcmp (current_templates->start->name, "skinit") == 0) + RegXX = Reg32; + else if (flag_code == CODE_64BIT) + RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32; + else + RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0) + ? Reg16 + : Reg32; + if (!i.base_reg + || !(i.base_reg->reg_type & Acc) + || !(i.base_reg->reg_type & RegXX) + || i.index_reg + || (i.types[0] & Disp)) + ok = 0; + } + else if (flag_code == CODE_64BIT) { unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32); @@ -4575,7 +4650,7 @@ md_estimate_size_before_relax (fragP, se shared library. */ if (S_GET_SEGMENT (fragP->fr_symbol) != segment #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) - || (OUTPUT_FLAVOR == bfd_target_elf_flavour + || (IS_ELF && (S_IS_EXTERNAL (fragP->fr_symbol) || S_IS_WEAK (fragP->fr_symbol))) #endif @@ -4862,7 +4937,7 @@ md_apply_fix (fixP, valP, seg) subtract the current location (for partial_inplace, PC relative relocations); see more below. */ #ifndef OBJ_AOUT - if (OUTPUT_FLAVOR == bfd_target_elf_flavour + if (IS_ELF #ifdef TE_PE || OUTPUT_FLAVOR == bfd_target_coff_flavour #endif @@ -4870,7 +4945,7 @@ md_apply_fix (fixP, valP, seg) value += fixP->fx_where + fixP->fx_frag->fr_address; #endif #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) - if (OUTPUT_FLAVOR == bfd_target_elf_flavour) + if (IS_ELF) { segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); @@ -4902,8 +4977,7 @@ md_apply_fix (fixP, valP, seg) /* Fix a few things - the dynamic linker expects certain values here, and we must not disappoint it. */ #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) - if (OUTPUT_FLAVOR == bfd_target_elf_flavour - && fixP->fx_addsy) + if (IS_ELF && fixP->fx_addsy) switch (fixP->fx_r_type) { case BFD_RELOC_386_PLT32: @@ -5246,8 +5320,7 @@ i386_target_format () #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) void i386_elf_emit_arch_note () { - if (OUTPUT_FLAVOR == bfd_target_elf_flavour - && cpu_arch_name != NULL) + if (IS_ELF && cpu_arch_name != NULL) { char *p; asection *seg = now_seg; diff -uprN binutils-2.16.91.0.1/gas/config/tc-i386.h binutils-2.16.91.0.2/gas/config/tc-i386.h --- binutils-2.16.91.0.1/gas/config/tc-i386.h 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-i386.h 2005-07-20 12:27:27.825105331 -0700 @@ -27,9 +27,7 @@ #error So, do you know what you are doing? #endif -#ifdef ANSI_PROTOTYPES struct fix; -#endif #define TARGET_BYTES_BIG_ENDIAN 0 @@ -182,15 +180,20 @@ typedef struct #define CpuSSE2 0x4000 /* Streaming SIMD extensions 2 required */ #define Cpu3dnow 0x8000 /* 3dnow! support required */ #define Cpu3dnowA 0x10000 /* 3dnow!Extensions support required */ -#define CpuPNI 0x20000 /* Prescott New Instructions required */ +#define CpuSSE3 0x20000 /* Streaming SIMD extensions 3 required */ +#define CpuPNI CpuSSE3 /* Prescott New Instructions required */ #define CpuPadLock 0x40000 /* VIA PadLock required */ +#define CpuSVME 0x80000 /* AMD Secure Virtual Machine Ext-s required */ +#define CpuVMX 0x100000 /* VMX Instructions required */ /* These flags are set by gas depending on the flag_code. */ #define Cpu64 0x4000000 /* 64bit support required */ #define CpuNo64 0x8000000 /* Not supported in the 64bit mode */ /* The default value for unknown CPUs - enable all features to avoid problems. */ -#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock) +#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \ + |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|CpuVMX \ + |Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock|CpuSVME) /* the bits in opcode_modifier are used to generate the final opcode from the base_opcode. These bits also are used to detect alternate forms of @@ -388,7 +391,7 @@ arch_entry; #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_" #endif -#ifndef LEX_AT +#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined (LEX_AT) #define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES) extern void x86_cons PARAMS ((expressionS *, int)); diff -uprN binutils-2.16.91.0.1/gas/config/tc-ia64.c binutils-2.16.91.0.2/gas/config/tc-ia64.c --- binutils-2.16.91.0.1/gas/config/tc-ia64.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-ia64.c 2005-07-20 12:27:27.838103188 -0700 @@ -193,7 +193,7 @@ const char line_comment_chars[] = "#"; /* Characters which may be used to separate multiple commands on a single line. */ -const char line_separator_chars[] = ";"; +const char line_separator_chars[] = ";{}"; /* Characters which are used to indicate an exponent in a floating point number. */ @@ -593,7 +593,7 @@ static const bfd_vma nop[IA64_NUM_UNITS] 0x0008000000LL, /* M-unit nop */ 0x4000000000LL, /* B-unit nop */ 0x0008000000LL, /* F-unit nop */ - 0x0008000000LL, /* L-"unit" nop */ + 0x0000000000LL, /* L-"unit" nop immediate */ 0x0008000000LL, /* X-unit nop */ }; @@ -736,6 +736,7 @@ static struct /* TRUE if processing unwind directives in a prologue region. */ unsigned int prologue : 1; unsigned int prologue_mask : 4; + unsigned int prologue_gr : 7; unsigned int body : 1; unsigned int insn : 1; unsigned int prologue_count; /* number of .prologues seen so far */ @@ -762,11 +763,9 @@ static void dot_proc PARAMS ((int)); static void dot_fframe PARAMS ((int)); static void dot_vframe PARAMS ((int)); static void dot_vframesp PARAMS ((int)); -static void dot_vframepsp PARAMS ((int)); static void dot_save PARAMS ((int)); static void dot_restore PARAMS ((int)); static void dot_restorereg PARAMS ((int)); -static void dot_restorereg_p PARAMS ((int)); static void dot_handlerdata PARAMS ((int)); static void dot_unwentry PARAMS ((int)); static void dot_altrp PARAMS ((int)); @@ -778,8 +777,6 @@ static void dot_savegf PARAMS ((int)); static void dot_spill PARAMS ((int)); static void dot_spillreg PARAMS ((int)); static void dot_spillmem PARAMS ((int)); -static void dot_spillreg_p PARAMS ((int)); -static void dot_spillmem_p PARAMS ((int)); static void dot_label_state PARAMS ((int)); static void dot_copy_state PARAMS ((int)); static void dot_unwabi PARAMS ((int)); @@ -809,14 +806,14 @@ static void dot_serialize PARAMS ((int)) static void dot_dv_mode PARAMS ((int)); static void dot_entry PARAMS ((int)); static void dot_mem_offset PARAMS ((int)); -static void add_unwind_entry PARAMS((unw_rec_list *ptr)); +static void add_unwind_entry PARAMS((unw_rec_list *, int)); static symbolS *declare_register PARAMS ((const char *name, int regnum)); static void declare_register_set PARAMS ((const char *, int, int)); static unsigned int operand_width PARAMS ((enum ia64_opnd)); static enum operand_match_result operand_match PARAMS ((const struct ia64_opcode *idesc, int index, expressionS *e)); -static int parse_operand PARAMS ((expressionS *e)); +static int parse_operand PARAMS ((expressionS *, int)); static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *)); static void build_insn PARAMS ((struct slot *, bfd_vma *)); static void emit_one_bundle PARAMS ((void)); @@ -937,15 +934,11 @@ static unw_rec_list *output_unwabi PARAM static unw_rec_list *output_epilogue PARAMS ((unsigned long)); static unw_rec_list *output_label_state PARAMS ((unsigned long)); static unw_rec_list *output_copy_state PARAMS ((unsigned long)); -static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int)); -static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int)); -static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int, +static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int, unsigned int)); -static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int, +static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int, unsigned int)); static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int, - unsigned int)); -static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int, unsigned int, unsigned int)); static void process_one_record PARAMS ((unw_rec_list *, vbyte_func)); static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func)); @@ -956,8 +949,9 @@ static unsigned long slot_index PARAMS ( int)); static unw_rec_list *optimize_unw_records PARAMS ((unw_rec_list *)); static void fixup_unw_records PARAMS ((unw_rec_list *, int)); -static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); -static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); +static int parse_predicate_and_operand PARAMS ((expressionS *, unsigned *, const char *)); +static void convert_expr_to_ab_reg PARAMS ((const expressionS *, unsigned int *, unsigned int *, const char *, int)); +static void convert_expr_to_xy_reg PARAMS ((const expressionS *, unsigned int *, unsigned int *, const char *, int)); static unsigned int get_saved_prologue_count PARAMS ((unsigned long)); static void save_prologue_count PARAMS ((unsigned long, unsigned int)); static void free_saved_prologue_counts PARAMS ((void)); @@ -2288,39 +2282,13 @@ output_copy_state (unsigned long label) } static unw_rec_list * -output_spill_psprel (ab, reg, offset) - unsigned int ab; - unsigned int reg; - unsigned int offset; -{ - unw_rec_list *ptr = alloc_record (spill_psprel); - ptr->r.record.x.ab = ab; - ptr->r.record.x.reg = reg; - ptr->r.record.x.pspoff = ENCODED_PSP_OFFSET (offset); - return ptr; -} - -static unw_rec_list * -output_spill_sprel (ab, reg, offset) - unsigned int ab; - unsigned int reg; - unsigned int offset; -{ - unw_rec_list *ptr = alloc_record (spill_sprel); - ptr->r.record.x.ab = ab; - ptr->r.record.x.reg = reg; - ptr->r.record.x.spoff = offset / 4; - return ptr; -} - -static unw_rec_list * -output_spill_psprel_p (ab, reg, offset, predicate) +output_spill_psprel (ab, reg, offset, predicate) unsigned int ab; unsigned int reg; unsigned int offset; unsigned int predicate; { - unw_rec_list *ptr = alloc_record (spill_psprel_p); + unw_rec_list *ptr = alloc_record (predicate ? spill_psprel_p : spill_psprel); ptr->r.record.x.ab = ab; ptr->r.record.x.reg = reg; ptr->r.record.x.pspoff = ENCODED_PSP_OFFSET (offset); @@ -2329,13 +2297,13 @@ output_spill_psprel_p (ab, reg, offset, } static unw_rec_list * -output_spill_sprel_p (ab, reg, offset, predicate) +output_spill_sprel (ab, reg, offset, predicate) unsigned int ab; unsigned int reg; unsigned int offset; unsigned int predicate; { - unw_rec_list *ptr = alloc_record (spill_sprel_p); + unw_rec_list *ptr = alloc_record (predicate ? spill_sprel_p : spill_sprel); ptr->r.record.x.ab = ab; ptr->r.record.x.reg = reg; ptr->r.record.x.spoff = offset / 4; @@ -2344,29 +2312,14 @@ output_spill_sprel_p (ab, reg, offset, p } static unw_rec_list * -output_spill_reg (ab, reg, targ_reg, xy) - unsigned int ab; - unsigned int reg; - unsigned int targ_reg; - unsigned int xy; -{ - unw_rec_list *ptr = alloc_record (spill_reg); - ptr->r.record.x.ab = ab; - ptr->r.record.x.reg = reg; - ptr->r.record.x.treg = targ_reg; - ptr->r.record.x.xy = xy; - return ptr; -} - -static unw_rec_list * -output_spill_reg_p (ab, reg, targ_reg, xy, predicate) +output_spill_reg (ab, reg, targ_reg, xy, predicate) unsigned int ab; unsigned int reg; unsigned int targ_reg; unsigned int xy; unsigned int predicate; { - unw_rec_list *ptr = alloc_record (spill_reg_p); + unw_rec_list *ptr = alloc_record (predicate ? spill_reg_p : spill_reg); ptr->r.record.x.ab = ab; ptr->r.record.x.reg = reg; ptr->r.record.x.treg = targ_reg; @@ -2577,6 +2530,28 @@ calc_record_size (list) return vbyte_count; } +/* Return the number of bits set in the input value. + Perhaps this has a better place... */ +#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4) +# define popcount __builtin_popcount +#else +static int +popcount (unsigned x) +{ + static const unsigned char popcnt[16] = + { + 0, 1, 1, 2, + 1, 2, 2, 3, + 1, 2, 2, 3, + 2, 3, 3, 4 + }; + + if (x < NELEMS (popcnt)) + return popcnt[x]; + return popcnt[x % NELEMS (popcnt)] + popcount (x / NELEMS (popcnt)); +} +#endif + /* Update IMASK bitmask to reflect the fact that one or more registers of type TYPE are saved starting at instruction with index T. If N bits are set in REGMASK, it is assumed that instructions T through @@ -3000,17 +2975,43 @@ ia64_convert_frag (fragS *frag) } static int -convert_expr_to_ab_reg (e, ab, regp) - expressionS *e; +parse_predicate_and_operand (e, qp, po) + expressionS * e; + unsigned * qp; + const char * po; +{ + int sep = parse_operand (e, ','); + + *qp = e->X_add_number - REG_P; + if (e->X_op != O_register || *qp > 63) + { + as_bad ("First operand to .%s must be a predicate", po); + *qp = 0; + } + else if (*qp == 0) + as_warn ("Pointless use of p0 as first operand to .%s", po); + if (sep == ',') + sep = parse_operand (e, ','); + else + e->X_op = O_absent; + return sep; +} + +static void +convert_expr_to_ab_reg (e, ab, regp, po, n) + const expressionS *e; unsigned int *ab; unsigned int *regp; + const char * po; + int n; { - unsigned int reg; + unsigned int reg = e->X_add_number; + + *ab = *regp = 0; /* Anything valid is good here. */ if (e->X_op != O_register) - return 0; + reg = REG_GR; /* Anything invalid is good here. */ - reg = e->X_add_number; if (reg >= (REG_GR + 4) && reg <= (REG_GR + 7)) { *ab = 0; @@ -3045,31 +3046,33 @@ convert_expr_to_ab_reg (e, ab, regp) case REG_AR + AR_LC: *regp = 10; break; default: - return 0; + as_bad ("Operand %d to .%s must be a preserved register", n, po); + break; } } - return 1; } -static int -convert_expr_to_xy_reg (e, xy, regp) - expressionS *e; +static void +convert_expr_to_xy_reg (e, xy, regp, po, n) + const expressionS *e; unsigned int *xy; unsigned int *regp; + const char * po; + int n; { - unsigned int reg; + unsigned int reg = e->X_add_number; - if (e->X_op != O_register) - return 0; + *xy = *regp = 0; /* Anything valid is good here. */ - reg = e->X_add_number; + if (e->X_op != O_register) + reg = REG_GR; /* Anything invalid is good here. */ - if (/* reg >= REG_GR && */ reg <= (REG_GR + 127)) + if (reg >= (REG_GR + 1) && reg <= (REG_GR + 127)) { *xy = 0; *regp = reg - REG_GR; } - else if (reg >= REG_FR && reg <= (REG_FR + 127)) + else if (reg >= (REG_FR + 2) && reg <= (REG_FR + 127)) { *xy = 1; *regp = reg - REG_FR; @@ -3080,8 +3083,7 @@ convert_expr_to_xy_reg (e, xy, regp) *regp = reg - REG_BR; } else - return -1; - return 1; + as_bad ("Operand %d to .%s must be a writable register", n, po); } static void @@ -3210,18 +3212,48 @@ in_body (const char *directive) } static void -add_unwind_entry (ptr) +add_unwind_entry (ptr, sep) unw_rec_list *ptr; + int sep; { - if (unwind.tail) - unwind.tail->next = ptr; - else - unwind.list = ptr; - unwind.tail = ptr; + if (ptr) + { + if (unwind.tail) + unwind.tail->next = ptr; + else + unwind.list = ptr; + unwind.tail = ptr; + + /* The current entry can in fact be a chain of unwind entries. */ + if (unwind.current_entry == NULL) + unwind.current_entry = ptr; + } /* The current entry can in fact be a chain of unwind entries. */ if (unwind.current_entry == NULL) unwind.current_entry = ptr; + + if (sep == ',') + { + /* Parse a tag permitted for the current directive. */ + int ch; + + SKIP_WHITESPACE (); + ch = get_symbol_end (); + /* FIXME: For now, just issue a warning that this isn't implemented. */ + { + static int warned; + + if (!warned) + { + warned = 1; + as_warn ("Tags on unwind pseudo-ops aren't supported, yet"); + } + } + *input_line_pointer = ch; + } + if (sep != NOT_A_CHAR) + demand_empty_rest_of_line (); } static void @@ -3229,16 +3261,19 @@ dot_fframe (dummy) int dummy ATTRIBUTE_UNUSED; { expressionS e; + int sep; if (!in_prologue ("fframe")) return; - parse_operand (&e); + sep = parse_operand (&e, ','); if (e.X_op != O_constant) - as_bad ("Operand to .fframe must be a constant"); - else - add_unwind_entry (output_mem_stack_f (e.X_add_number)); + { + as_bad ("First operand to .fframe must be a constant"); + e.X_add_number = 0; + } + add_unwind_entry (output_mem_stack_f (e.X_add_number), sep); } static void @@ -3247,58 +3282,47 @@ dot_vframe (dummy) { expressionS e; unsigned reg; + int sep; if (!in_prologue ("vframe")) return; - parse_operand (&e); + sep = parse_operand (&e, ','); reg = e.X_add_number - REG_GR; - if (e.X_op == O_register && reg < 128) + if (e.X_op != O_register || reg > 127) { - add_unwind_entry (output_mem_stack_v ()); - if (! (unwind.prologue_mask & 2)) - add_unwind_entry (output_psp_gr (reg)); + as_bad ("First operand to .vframe must be a general register"); + reg = 0; } - else - as_bad ("First operand to .vframe must be a general register"); + add_unwind_entry (output_mem_stack_v (), sep); + if (! (unwind.prologue_mask & 2)) + add_unwind_entry (output_psp_gr (reg), NOT_A_CHAR); + else if (reg != unwind.prologue_gr + + (unsigned) popcount (unwind.prologue_mask & (-2 << 1))) + as_warn ("Operand of .vframe contradicts .prologue"); } static void -dot_vframesp (dummy) - int dummy ATTRIBUTE_UNUSED; +dot_vframesp (psp) + int psp; { expressionS e; + int sep; - if (!in_prologue ("vframesp")) - return; - - parse_operand (&e); - if (e.X_op == O_constant) - { - add_unwind_entry (output_mem_stack_v ()); - add_unwind_entry (output_psp_sprel (e.X_add_number)); - } - else - as_bad ("Operand to .vframesp must be a constant (sp-relative offset)"); -} - -static void -dot_vframepsp (dummy) - int dummy ATTRIBUTE_UNUSED; -{ - expressionS e; + if (psp) + as_warn (".vframepsp is meaningless, assuming .vframesp was meant"); - if (!in_prologue ("vframepsp")) + if (!in_prologue ("vframesp")) return; - parse_operand (&e); - if (e.X_op == O_constant) + sep = parse_operand (&e, ','); + if (e.X_op != O_constant) { - add_unwind_entry (output_mem_stack_v ()); - add_unwind_entry (output_psp_sprel (e.X_add_number)); + as_bad ("Operand to .vframesp must be a constant (sp-relative offset)"); + e.X_add_number = 0; } - else - as_bad ("Operand to .vframepsp must be a constant (psp-relative offset)"); + add_unwind_entry (output_mem_stack_v (), sep); + add_unwind_entry (output_psp_sprel (e.X_add_number), NOT_A_CHAR); } static void @@ -3306,106 +3330,115 @@ dot_save (dummy) int dummy ATTRIBUTE_UNUSED; { expressionS e1, e2; + unsigned reg1, reg2; int sep; - int reg1, reg2; if (!in_prologue ("save")) return; - sep = parse_operand (&e1); - if (sep != ',') - as_bad ("No second operand to .save"); - sep = parse_operand (&e2); + sep = parse_operand (&e1, ','); + if (sep == ',') + sep = parse_operand (&e2, ','); + else + e2.X_op = O_absent; reg1 = e1.X_add_number; - reg2 = e2.X_add_number - REG_GR; - /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ - if (e1.X_op == O_register) + if (e1.X_op != O_register) { - if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128) - { - switch (reg1) - { - case REG_AR + AR_BSP: - add_unwind_entry (output_bsp_when ()); - add_unwind_entry (output_bsp_gr (reg2)); - break; - case REG_AR + AR_BSPSTORE: - add_unwind_entry (output_bspstore_when ()); - add_unwind_entry (output_bspstore_gr (reg2)); - break; - case REG_AR + AR_RNAT: - add_unwind_entry (output_rnat_when ()); - add_unwind_entry (output_rnat_gr (reg2)); - break; - case REG_AR + AR_UNAT: - add_unwind_entry (output_unat_when ()); - add_unwind_entry (output_unat_gr (reg2)); - break; - case REG_AR + AR_FPSR: - add_unwind_entry (output_fpsr_when ()); - add_unwind_entry (output_fpsr_gr (reg2)); - break; - case REG_AR + AR_PFS: - add_unwind_entry (output_pfs_when ()); - if (! (unwind.prologue_mask & 4)) - add_unwind_entry (output_pfs_gr (reg2)); - break; - case REG_AR + AR_LC: - add_unwind_entry (output_lc_when ()); - add_unwind_entry (output_lc_gr (reg2)); - break; - case REG_BR: - add_unwind_entry (output_rp_when ()); - if (! (unwind.prologue_mask & 8)) - add_unwind_entry (output_rp_gr (reg2)); - break; - case REG_PR: - add_unwind_entry (output_preds_when ()); - if (! (unwind.prologue_mask & 1)) - add_unwind_entry (output_preds_gr (reg2)); - break; - case REG_PRIUNAT: - add_unwind_entry (output_priunat_when_gr ()); - add_unwind_entry (output_priunat_gr (reg2)); - break; - default: - as_bad ("First operand not a valid register"); - } - } - else - as_bad (" Second operand not a valid register"); + as_bad ("First operand to .save not a register"); + reg1 = REG_PR; /* Anything valid is good here. */ + } + reg2 = e2.X_add_number - REG_GR; + if (e2.X_op != O_register || reg2 > 127) + { + as_bad ("Second operand to .save not a valid register"); + reg2 = 0; + } + switch (reg1) + { + case REG_AR + AR_BSP: + add_unwind_entry (output_bsp_when (), sep); + add_unwind_entry (output_bsp_gr (reg2), NOT_A_CHAR); + break; + case REG_AR + AR_BSPSTORE: + add_unwind_entry (output_bspstore_when (), sep); + add_unwind_entry (output_bspstore_gr (reg2), NOT_A_CHAR); + break; + case REG_AR + AR_RNAT: + add_unwind_entry (output_rnat_when (), sep); + add_unwind_entry (output_rnat_gr (reg2), NOT_A_CHAR); + break; + case REG_AR + AR_UNAT: + add_unwind_entry (output_unat_when (), sep); + add_unwind_entry (output_unat_gr (reg2), NOT_A_CHAR); + break; + case REG_AR + AR_FPSR: + add_unwind_entry (output_fpsr_when (), sep); + add_unwind_entry (output_fpsr_gr (reg2), NOT_A_CHAR); + break; + case REG_AR + AR_PFS: + add_unwind_entry (output_pfs_when (), sep); + if (! (unwind.prologue_mask & 4)) + add_unwind_entry (output_pfs_gr (reg2), NOT_A_CHAR); + else if (reg2 != unwind.prologue_gr + + (unsigned) popcount (unwind.prologue_mask & (-4 << 1))) + as_warn ("Second operand of .save contradicts .prologue"); + break; + case REG_AR + AR_LC: + add_unwind_entry (output_lc_when (), sep); + add_unwind_entry (output_lc_gr (reg2), NOT_A_CHAR); + break; + case REG_BR: + add_unwind_entry (output_rp_when (), sep); + if (! (unwind.prologue_mask & 8)) + add_unwind_entry (output_rp_gr (reg2), NOT_A_CHAR); + else if (reg2 != unwind.prologue_gr) + as_warn ("Second operand of .save contradicts .prologue"); + break; + case REG_PR: + add_unwind_entry (output_preds_when (), sep); + if (! (unwind.prologue_mask & 1)) + add_unwind_entry (output_preds_gr (reg2), NOT_A_CHAR); + else if (reg2 != unwind.prologue_gr + + (unsigned) popcount (unwind.prologue_mask & (-1 << 1))) + as_warn ("Second operand of .save contradicts .prologue"); + break; + case REG_PRIUNAT: + add_unwind_entry (output_priunat_when_gr (), sep); + add_unwind_entry (output_priunat_gr (reg2), NOT_A_CHAR); + break; + default: + as_bad ("First operand to .save not a valid register"); + add_unwind_entry (NULL, sep); + break; } - else - as_bad ("First operand not a register"); } static void dot_restore (dummy) int dummy ATTRIBUTE_UNUSED; { - expressionS e1, e2; + expressionS e1; unsigned long ecount; /* # of _additional_ regions to pop */ int sep; if (!in_body ("restore")) return; - sep = parse_operand (&e1); + sep = parse_operand (&e1, ','); if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12) - { - as_bad ("First operand to .restore must be stack pointer (sp)"); - return; - } + as_bad ("First operand to .restore must be stack pointer (sp)"); if (sep == ',') { - parse_operand (&e2); + expressionS e2; + + sep = parse_operand (&e2, ','); if (e2.X_op != O_constant || e2.X_add_number < 0) { as_bad ("Second operand to .restore must be a constant >= 0"); - return; + e2.X_add_number = 0; } ecount = e2.X_add_number; } @@ -3416,10 +3449,10 @@ dot_restore (dummy) { as_bad ("Epilogue count of %lu exceeds number of nested prologues (%u)", ecount + 1, unwind.prologue_count); - return; + ecount = 0; } - add_unwind_entry (output_epilogue (ecount)); + add_unwind_entry (output_epilogue (ecount), sep); if (ecount < unwind.prologue_count) unwind.prologue_count -= ecount + 1; @@ -3428,58 +3461,27 @@ dot_restore (dummy) } static void -dot_restorereg (dummy) - int dummy ATTRIBUTE_UNUSED; -{ - unsigned int ab, reg; - expressionS e; - - if (!in_procedure ("restorereg")) - return; - - parse_operand (&e); - - if (!convert_expr_to_ab_reg (&e, &ab, ®)) - { - as_bad ("First operand to .restorereg must be a preserved register"); - return; - } - add_unwind_entry (output_spill_reg (ab, reg, 0, 0)); -} - -static void -dot_restorereg_p (dummy) - int dummy ATTRIBUTE_UNUSED; +dot_restorereg (pred) + int pred; { unsigned int qp, ab, reg; - expressionS e1, e2; + expressionS e; int sep; + const char * const po = pred ? "restorereg.p" : "restorereg"; - if (!in_procedure ("restorereg.p")) + if (!in_procedure (po)) return; - sep = parse_operand (&e1); - if (sep != ',') - { - as_bad ("No second operand to .restorereg.p"); - return; - } - - parse_operand (&e2); - - qp = e1.X_add_number - REG_P; - if (e1.X_op != O_register || qp > 63) + if (pred) + sep = parse_predicate_and_operand (&e, &qp, po); + else { - as_bad ("First operand to .restorereg.p must be a predicate"); - return; + sep = parse_operand (&e, ','); + qp = 0; } + convert_expr_to_ab_reg (&e, &ab, ®, po, 1 + pred); - if (!convert_expr_to_ab_reg (&e2, &ab, ®)) - { - as_bad ("Second operand to .restorereg.p must be a preserved register"); - return; - } - add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp)); + add_unwind_entry (output_spill_reg (ab, reg, 0, 0, qp), sep); } static char *special_linkonce_name[] = @@ -3607,7 +3609,7 @@ generate_unwind_image (const segT text_s /* Mark the end of the unwind info, so that we can compute the size of the last unwind region. */ - add_unwind_entry (output_endp ()); + add_unwind_entry (output_endp (), NOT_A_CHAR); /* Force out pending instructions, to make sure all unwind records have a valid slot_number field. */ @@ -3723,12 +3725,14 @@ dot_altrp (dummy) if (!in_prologue ("altrp")) return; - parse_operand (&e); + parse_operand (&e, 0); reg = e.X_add_number - REG_BR; - if (e.X_op == O_register && reg < 8) - add_unwind_entry (output_rp_br (reg)); - else - as_bad ("First operand not a valid branch register"); + if (e.X_op != O_register || reg > 7) + { + as_bad ("First operand to .altrp not a valid branch register"); + reg = 0; + } + add_unwind_entry (output_rp_br (reg), 0); } static void @@ -3738,182 +3742,210 @@ dot_savemem (psprel) expressionS e1, e2; int sep; int reg1, val; + const char * const po = psprel ? "savepsp" : "savesp"; - if (!in_prologue (psprel ? "savepsp" : "savesp")) + if (!in_prologue (po)) return; - sep = parse_operand (&e1); - if (sep != ',') - as_bad ("No second operand to .save%ssp", psprel ? "p" : ""); - sep = parse_operand (&e2); + sep = parse_operand (&e1, ','); + if (sep == ',') + sep = parse_operand (&e2, ','); + else + e2.X_op = O_absent; reg1 = e1.X_add_number; val = e2.X_add_number; /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ - if (e1.X_op == O_register) + if (e1.X_op != O_register) { - if (e2.X_op == O_constant) - { - switch (reg1) - { - case REG_AR + AR_BSP: - add_unwind_entry (output_bsp_when ()); - add_unwind_entry ((psprel - ? output_bsp_psprel - : output_bsp_sprel) (val)); - break; - case REG_AR + AR_BSPSTORE: - add_unwind_entry (output_bspstore_when ()); - add_unwind_entry ((psprel - ? output_bspstore_psprel - : output_bspstore_sprel) (val)); - break; - case REG_AR + AR_RNAT: - add_unwind_entry (output_rnat_when ()); - add_unwind_entry ((psprel - ? output_rnat_psprel - : output_rnat_sprel) (val)); - break; - case REG_AR + AR_UNAT: - add_unwind_entry (output_unat_when ()); - add_unwind_entry ((psprel - ? output_unat_psprel - : output_unat_sprel) (val)); - break; - case REG_AR + AR_FPSR: - add_unwind_entry (output_fpsr_when ()); - add_unwind_entry ((psprel - ? output_fpsr_psprel - : output_fpsr_sprel) (val)); - break; - case REG_AR + AR_PFS: - add_unwind_entry (output_pfs_when ()); - add_unwind_entry ((psprel - ? output_pfs_psprel - : output_pfs_sprel) (val)); - break; - case REG_AR + AR_LC: - add_unwind_entry (output_lc_when ()); - add_unwind_entry ((psprel - ? output_lc_psprel - : output_lc_sprel) (val)); - break; - case REG_BR: - add_unwind_entry (output_rp_when ()); - add_unwind_entry ((psprel - ? output_rp_psprel - : output_rp_sprel) (val)); - break; - case REG_PR: - add_unwind_entry (output_preds_when ()); - add_unwind_entry ((psprel - ? output_preds_psprel - : output_preds_sprel) (val)); - break; - case REG_PRIUNAT: - add_unwind_entry (output_priunat_when_mem ()); - add_unwind_entry ((psprel - ? output_priunat_psprel - : output_priunat_sprel) (val)); - break; - default: - as_bad ("First operand not a valid register"); - } - } - else - as_bad (" Second operand not a valid constant"); + as_bad ("First operand to .%s not a register", po); + reg1 = REG_PR; /* Anything valid is good here. */ + } + if (e2.X_op != O_constant) + { + as_bad ("Second operand to .%s not a constant", po); + val = 0; + } + + switch (reg1) + { + case REG_AR + AR_BSP: + add_unwind_entry (output_bsp_when (), sep); + add_unwind_entry ((psprel + ? output_bsp_psprel + : output_bsp_sprel) (val), NOT_A_CHAR); + break; + case REG_AR + AR_BSPSTORE: + add_unwind_entry (output_bspstore_when (), sep); + add_unwind_entry ((psprel + ? output_bspstore_psprel + : output_bspstore_sprel) (val), NOT_A_CHAR); + break; + case REG_AR + AR_RNAT: + add_unwind_entry (output_rnat_when (), sep); + add_unwind_entry ((psprel + ? output_rnat_psprel + : output_rnat_sprel) (val), NOT_A_CHAR); + break; + case REG_AR + AR_UNAT: + add_unwind_entry (output_unat_when (), sep); + add_unwind_entry ((psprel + ? output_unat_psprel + : output_unat_sprel) (val), NOT_A_CHAR); + break; + case REG_AR + AR_FPSR: + add_unwind_entry (output_fpsr_when (), sep); + add_unwind_entry ((psprel + ? output_fpsr_psprel + : output_fpsr_sprel) (val), NOT_A_CHAR); + break; + case REG_AR + AR_PFS: + add_unwind_entry (output_pfs_when (), sep); + add_unwind_entry ((psprel + ? output_pfs_psprel + : output_pfs_sprel) (val), NOT_A_CHAR); + break; + case REG_AR + AR_LC: + add_unwind_entry (output_lc_when (), sep); + add_unwind_entry ((psprel + ? output_lc_psprel + : output_lc_sprel) (val), NOT_A_CHAR); + break; + case REG_BR: + add_unwind_entry (output_rp_when (), sep); + add_unwind_entry ((psprel + ? output_rp_psprel + : output_rp_sprel) (val), NOT_A_CHAR); + break; + case REG_PR: + add_unwind_entry (output_preds_when (), sep); + add_unwind_entry ((psprel + ? output_preds_psprel + : output_preds_sprel) (val), NOT_A_CHAR); + break; + case REG_PRIUNAT: + add_unwind_entry (output_priunat_when_mem (), sep); + add_unwind_entry ((psprel + ? output_priunat_psprel + : output_priunat_sprel) (val), NOT_A_CHAR); + break; + default: + as_bad ("First operand to .%s not a valid register", po); + add_unwind_entry (NULL, sep); + break; } - else - as_bad ("First operand not a register"); } static void dot_saveg (dummy) int dummy ATTRIBUTE_UNUSED; { - expressionS e1, e2; + expressionS e; + unsigned grmask; int sep; if (!in_prologue ("save.g")) return; - sep = parse_operand (&e1); - if (sep == ',') - parse_operand (&e2); + sep = parse_operand (&e, ','); - if (e1.X_op != O_constant) - as_bad ("First operand to .save.g must be a constant."); - else + grmask = e.X_add_number; + if (e.X_op != O_constant + || e.X_add_number <= 0 + || e.X_add_number > 0xf) { - int grmask = e1.X_add_number; - if (sep != ',') - add_unwind_entry (output_gr_mem (grmask)); - else + as_bad ("First operand to .save.g must be a positive 4-bit constant"); + grmask = 0; + } + + if (sep == ',') + { + unsigned reg; + int n = popcount (grmask); + + parse_operand (&e, 0); + reg = e.X_add_number - REG_GR; + if (e.X_op != O_register || reg > 127) { - int reg = e2.X_add_number - REG_GR; - if (e2.X_op == O_register && reg >= 0 && reg < 128) - add_unwind_entry (output_gr_gr (grmask, reg)); - else - as_bad ("Second operand is an invalid register."); + as_bad ("Second operand to .save.g must be a general register"); + reg = 0; } + else if (reg > 128U - n) + { + as_bad ("Second operand to .save.g must be the first of %d general registers", n); + reg = 0; + } + add_unwind_entry (output_gr_gr (grmask, reg), 0); } + else + add_unwind_entry (output_gr_mem (grmask), 0); } static void dot_savef (dummy) int dummy ATTRIBUTE_UNUSED; { - expressionS e1; - int sep; + expressionS e; if (!in_prologue ("save.f")) return; - sep = parse_operand (&e1); + parse_operand (&e, 0); - if (e1.X_op != O_constant) - as_bad ("Operand to .save.f must be a constant."); - else - add_unwind_entry (output_fr_mem (e1.X_add_number)); + if (e.X_op != O_constant + || e.X_add_number <= 0 + || e.X_add_number > 0xfffff) + { + as_bad ("Operand to .save.f must be a positive 20-bit constant"); + e.X_add_number = 0; + } + add_unwind_entry (output_fr_mem (e.X_add_number), 0); } static void dot_saveb (dummy) int dummy ATTRIBUTE_UNUSED; { - expressionS e1, e2; - unsigned int reg; - unsigned char sep; - int brmask; + expressionS e; + unsigned brmask; + int sep; if (!in_prologue ("save.b")) return; - sep = parse_operand (&e1); - if (e1.X_op != O_constant) + sep = parse_operand (&e, ','); + + brmask = e.X_add_number; + if (e.X_op != O_constant + || e.X_add_number <= 0 + || e.X_add_number > 0x1f) { - as_bad ("First operand to .save.b must be a constant."); - return; + as_bad ("First operand to .save.b must be a positive 5-bit constant"); + brmask = 0; } - brmask = e1.X_add_number; if (sep == ',') { - sep = parse_operand (&e2); - reg = e2.X_add_number - REG_GR; - if (e2.X_op != O_register || reg > 127) + unsigned reg; + int n = popcount (brmask); + + parse_operand (&e, 0); + reg = e.X_add_number - REG_GR; + if (e.X_op != O_register || reg > 127) { - as_bad ("Second operand to .save.b must be a general register."); - return; + as_bad ("Second operand to .save.b must be a general register"); + reg = 0; + } + else if (reg > 128U - n) + { + as_bad ("Second operand to .save.b must be the first of %d general registers", n); + reg = 0; } - add_unwind_entry (output_br_gr (brmask, e2.X_add_number)); + add_unwind_entry (output_br_gr (brmask, reg), 0); } else - add_unwind_entry (output_br_mem (brmask)); - - if (!is_end_of_line[sep] && !is_it_end_of_statement ()) - demand_empty_rest_of_line (); + add_unwind_entry (output_br_mem (brmask), 0); } static void @@ -3921,23 +3953,38 @@ dot_savegf (dummy) int dummy ATTRIBUTE_UNUSED; { expressionS e1, e2; - int sep; if (!in_prologue ("save.gf")) return; - sep = parse_operand (&e1); - if (sep == ',') - parse_operand (&e2); - - if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant) - as_bad ("Both operands of .save.gf must be constants."); + if (parse_operand (&e1, ',') == ',') + parse_operand (&e2, 0); else - { - int grmask = e1.X_add_number; - int frmask = e2.X_add_number; - add_unwind_entry (output_frgr_mem (grmask, frmask)); - } + e2.X_op = O_absent; + + if (e1.X_op != O_constant + || e1.X_add_number < 0 + || e1.X_add_number > 0xf) + { + as_bad ("First operand to .save.gf must be a non-negative 4-bit constant"); + e1.X_op = O_absent; + e1.X_add_number = 0; + } + if (e2.X_op != O_constant + || e2.X_add_number < 0 + || e2.X_add_number > 0xfffff) + { + as_bad ("Second operand to .save.gf must be a non-negative 20-bit constant"); + e2.X_op = O_absent; + e2.X_add_number = 0; + } + if (e1.X_op == O_constant + && e2.X_op == O_constant + && e1.X_add_number == 0 + && e2.X_add_number == 0) + as_bad ("Operands to .save.gf may not be both zero"); + + add_unwind_entry (output_frgr_mem (e1.X_add_number, e2.X_add_number), 0); } static void @@ -3945,201 +3992,93 @@ dot_spill (dummy) int dummy ATTRIBUTE_UNUSED; { expressionS e; - unsigned char sep; if (!in_prologue ("spill")) return; - sep = parse_operand (&e); - if (!is_end_of_line[sep] && !is_it_end_of_statement ()) - demand_empty_rest_of_line (); + parse_operand (&e, 0); if (e.X_op != O_constant) - as_bad ("Operand to .spill must be a constant"); - else - add_unwind_entry (output_spill_base (e.X_add_number)); -} - -static void -dot_spillreg (dummy) - int dummy ATTRIBUTE_UNUSED; -{ - int sep; - unsigned int ab, xy, reg, treg; - expressionS e1, e2; - - if (!in_procedure ("spillreg")) - return; - - sep = parse_operand (&e1); - if (sep != ',') - { - as_bad ("No second operand to .spillreg"); - return; - } - - parse_operand (&e2); - - if (!convert_expr_to_ab_reg (&e1, &ab, ®)) - { - as_bad ("First operand to .spillreg must be a preserved register"); - return; - } - - if (!convert_expr_to_xy_reg (&e2, &xy, &treg)) { - as_bad ("Second operand to .spillreg must be a register"); - return; + as_bad ("Operand to .spill must be a constant"); + e.X_add_number = 0; } - - add_unwind_entry (output_spill_reg (ab, reg, treg, xy)); + add_unwind_entry (output_spill_base (e.X_add_number), 0); } static void -dot_spillmem (psprel) - int psprel; +dot_spillreg (pred) + int pred; { - expressionS e1, e2; int sep; - unsigned int ab, reg; + unsigned int qp, ab, xy, reg, treg; + expressionS e; + const char * const po = pred ? "spillreg.p" : "spillreg"; - if (!in_procedure ("spillmem")) + if (!in_procedure (po)) return; - sep = parse_operand (&e1); - if (sep != ',') - { - as_bad ("Second operand missing"); - return; - } - - parse_operand (&e2); - - if (!convert_expr_to_ab_reg (&e1, &ab, ®)) - { - as_bad ("First operand to .spill%s must be a preserved register", - psprel ? "psp" : "sp"); - return; - } - - if (e2.X_op != O_constant) - { - as_bad ("Second operand to .spill%s must be a constant", - psprel ? "psp" : "sp"); - return; - } - - if (psprel) - add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number)); + if (pred) + sep = parse_predicate_and_operand (&e, &qp, po); else - add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number)); -} - -static void -dot_spillreg_p (dummy) - int dummy ATTRIBUTE_UNUSED; -{ - int sep; - unsigned int ab, xy, reg, treg; - expressionS e1, e2, e3; - unsigned int qp; - - if (!in_procedure ("spillreg.p")) - return; - - sep = parse_operand (&e1); - if (sep != ',') - { - as_bad ("No second and third operand to .spillreg.p"); - return; - } - - sep = parse_operand (&e2); - if (sep != ',') - { - as_bad ("No third operand to .spillreg.p"); - return; - } - - parse_operand (&e3); - - qp = e1.X_add_number - REG_P; - - if (e1.X_op != O_register || qp > 63) { - as_bad ("First operand to .spillreg.p must be a predicate"); - return; + sep = parse_operand (&e, ','); + qp = 0; } + convert_expr_to_ab_reg (&e, &ab, ®, po, 1 + pred); - if (!convert_expr_to_ab_reg (&e2, &ab, ®)) - { - as_bad ("Second operand to .spillreg.p must be a preserved register"); - return; - } - - if (!convert_expr_to_xy_reg (&e3, &xy, &treg)) - { - as_bad ("Third operand to .spillreg.p must be a register"); - return; - } + if (sep == ',') + sep = parse_operand (&e, ','); + else + e.X_op = O_absent; + convert_expr_to_xy_reg (&e, &xy, &treg, po, 2 + pred); - add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp)); + add_unwind_entry (output_spill_reg (ab, reg, treg, xy, qp), sep); } static void -dot_spillmem_p (psprel) +dot_spillmem (psprel) int psprel; { - expressionS e1, e2, e3; - int sep; - unsigned int ab, reg; - unsigned int qp; - - if (!in_procedure ("spillmem.p")) - return; - - sep = parse_operand (&e1); - if (sep != ',') - { - as_bad ("Second operand missing"); - return; - } + expressionS e; + int pred = (psprel < 0), sep; + unsigned int qp, ab, reg; + const char * po; - parse_operand (&e2); - if (sep != ',') + if (pred) { - as_bad ("Second operand missing"); - return; + psprel = ~psprel; + po = psprel ? "spillpsp.p" : "spillsp.p"; } + else + po = psprel ? "spillpsp" : "spillsp"; - parse_operand (&e3); - - qp = e1.X_add_number - REG_P; - if (e1.X_op != O_register || qp > 63) - { - as_bad ("First operand to .spill%s_p must be a predicate", - psprel ? "psp" : "sp"); - return; - } + if (!in_procedure (po)) + return; - if (!convert_expr_to_ab_reg (&e2, &ab, ®)) + if (pred) + sep = parse_predicate_and_operand (&e, &qp, po); + else { - as_bad ("Second operand to .spill%s_p must be a preserved register", - psprel ? "psp" : "sp"); - return; + sep = parse_operand (&e, ','); + qp = 0; } + convert_expr_to_ab_reg (&e, &ab, ®, po, 1 + pred); - if (e3.X_op != O_constant) + if (sep == ',') + sep = parse_operand (&e, ','); + else + e.X_op = O_absent; + if (e.X_op != O_constant) { - as_bad ("Third operand to .spill%s_p must be a constant", - psprel ? "psp" : "sp"); - return; + as_bad ("Operand %d to .%s must be a constant", 2 + pred, po); + e.X_add_number = 0; } if (psprel) - add_unwind_entry (output_spill_psprel_p (ab, reg, e3.X_add_number, qp)); + add_unwind_entry (output_spill_psprel (ab, reg, e.X_add_number, qp), sep); else - add_unwind_entry (output_spill_sprel_p (ab, reg, e3.X_add_number, qp)); + add_unwind_entry (output_spill_sprel (ab, reg, e.X_add_number, qp), sep); } static unsigned int @@ -4206,14 +4145,15 @@ dot_label_state (dummy) if (!in_body ("label_state")) return; - parse_operand (&e); - if (e.X_op != O_constant) + parse_operand (&e, 0); + if (e.X_op == O_constant) + save_prologue_count (e.X_add_number, unwind.prologue_count); + else { as_bad ("Operand to .label_state must be a constant"); - return; + e.X_add_number = 0; } - add_unwind_entry (output_label_state (e.X_add_number)); - save_prologue_count (e.X_add_number, unwind.prologue_count); + add_unwind_entry (output_label_state (e.X_add_number), 0); } static void @@ -4225,14 +4165,15 @@ dot_copy_state (dummy) if (!in_body ("copy_state")) return; - parse_operand (&e); - if (e.X_op != O_constant) + parse_operand (&e, 0); + if (e.X_op == O_constant) + unwind.prologue_count = get_saved_prologue_count (e.X_add_number); + else { as_bad ("Operand to .copy_state must be a constant"); - return; + e.X_add_number = 0; } - add_unwind_entry (output_copy_state (e.X_add_number)); - unwind.prologue_count = get_saved_prologue_count (e.X_add_number); + add_unwind_entry (output_copy_state (e.X_add_number), 0); } static void @@ -4242,32 +4183,28 @@ dot_unwabi (dummy) expressionS e1, e2; unsigned char sep; - if (!in_procedure ("unwabi")) + if (!in_prologue ("unwabi")) return; - sep = parse_operand (&e1); - if (sep != ',') - { - as_bad ("Second operand to .unwabi missing"); - return; - } - sep = parse_operand (&e2); - if (!is_end_of_line[sep] && !is_it_end_of_statement ()) - demand_empty_rest_of_line (); + sep = parse_operand (&e1, ','); + if (sep == ',') + parse_operand (&e2, 0); + else + e2.X_op = O_absent; if (e1.X_op != O_constant) { as_bad ("First operand to .unwabi must be a constant"); - return; + e1.X_add_number = 0; } if (e2.X_op != O_constant) { as_bad ("Second operand to .unwabi must be a constant"); - return; + e2.X_add_number = 0; } - add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number)); + add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number), 0); } static void @@ -4374,16 +4311,14 @@ dot_body (dummy) unwind.prologue_mask = 0; unwind.body = 1; - add_unwind_entry (output_body ()); - demand_empty_rest_of_line (); + add_unwind_entry (output_body (), 0); } static void dot_prologue (dummy) int dummy ATTRIBUTE_UNUSED; { - unsigned char sep; - int mask = 0, grsave = 0; + unsigned mask = 0, grsave = 0; if (!in_procedure ("prologue")) return; @@ -4398,36 +4333,53 @@ dot_prologue (dummy) if (!is_it_end_of_statement ()) { - expressionS e1, e2; - sep = parse_operand (&e1); - if (sep != ',') - as_bad ("No second operand to .prologue"); - sep = parse_operand (&e2); - if (!is_end_of_line[sep] && !is_it_end_of_statement ()) - demand_empty_rest_of_line (); - - if (e1.X_op == O_constant) - { - mask = e1.X_add_number; + expressionS e; + int n, sep = parse_operand (&e, ','); - if (e2.X_op == O_constant) - grsave = e2.X_add_number; - else if (e2.X_op == O_register - && (grsave = e2.X_add_number - REG_GR) < 128) - ; - else - as_bad ("Second operand not a constant or general register"); + if (e.X_op != O_constant + || e.X_add_number < 0 + || e.X_add_number > 0xf) + as_bad ("First operand to .prologue must be a positive 4-bit constant"); + else if (e.X_add_number == 0) + as_warn ("Pointless use of zero first operand to .prologue"); + else + mask = e.X_add_number; + n = popcount (mask); - add_unwind_entry (output_prologue_gr (mask, grsave)); - } + if (sep == ',') + parse_operand (&e, 0); else - as_bad ("First operand not a constant"); + e.X_op = O_absent; + if (e.X_op == O_constant + && e.X_add_number >= 0 + && e.X_add_number < 128) + { + if (md.unwind_check == unwind_check_error) + as_warn ("Using a constant as second operand to .prologue is deprecated"); + grsave = e.X_add_number; + } + else if (e.X_op != O_register + || (grsave = e.X_add_number - REG_GR) > 127) + { + as_bad ("Second operand to .prologue must be a general register"); + grsave = 0; + } + else if (grsave > 128U - n) + { + as_bad ("Second operand to .prologue must be the first of %d general registers", n); + grsave = 0; + } + } + + if (mask) + add_unwind_entry (output_prologue_gr (mask, grsave), 0); else - add_unwind_entry (output_prologue ()); + add_unwind_entry (output_prologue (), 0); unwind.prologue = 1; unwind.prologue_mask = mask; + unwind.prologue_gr = grsave; unwind.body = 0; ++unwind.prologue_count; } @@ -5332,11 +5284,11 @@ const pseudo_typeS md_pseudo_table[] = { "fframe", dot_fframe, 0 }, { "vframe", dot_vframe, 0 }, { "vframesp", dot_vframesp, 0 }, - { "vframepsp", dot_vframepsp, 0 }, + { "vframepsp", dot_vframesp, 1 }, { "save", dot_save, 0 }, { "restore", dot_restore, 0 }, { "restorereg", dot_restorereg, 0 }, - { "restorereg.p", dot_restorereg_p, 0 }, + { "restorereg.p", dot_restorereg, 1 }, { "handlerdata", dot_handlerdata, 0 }, { "unwentry", dot_unwentry, 0 }, { "altrp", dot_altrp, 0 }, @@ -5350,9 +5302,9 @@ const pseudo_typeS md_pseudo_table[] = { "spillreg", dot_spillreg, 0 }, { "spillsp", dot_spillmem, 0 }, { "spillpsp", dot_spillmem, 1 }, - { "spillreg.p", dot_spillreg_p, 0 }, - { "spillsp.p", dot_spillmem_p, 0 }, - { "spillpsp.p", dot_spillmem_p, 1 }, + { "spillreg.p", dot_spillreg, 1 }, + { "spillsp.p", dot_spillmem, ~0 }, + { "spillpsp.p", dot_spillmem, ~1 }, { "label_state", dot_label_state, 0 }, { "copy_state", dot_copy_state, 0 }, { "unwabi", dot_unwabi, 0 }, @@ -6045,27 +5997,19 @@ operand_match (idesc, index, e) } static int -parse_operand (e) +parse_operand (e, more) expressionS *e; + int more; { int sep = '\0'; memset (e, 0, sizeof (*e)); e->X_op = O_absent; SKIP_WHITESPACE (); - if (*input_line_pointer != '}') - expression (e); - sep = *input_line_pointer++; - - if (sep == '}') - { - if (!md.manual_bundling) - as_warn ("Found '}' when manual bundling is off"); - else - CURR_SLOT.manual_bundling_off = 1; - md.manual_bundling = 0; - sep = '\0'; - } + expression (e); + sep = *input_line_pointer; + if (more && (sep == ',' || sep == more)) + ++input_line_pointer; return sep; } @@ -6124,7 +6068,7 @@ parse_operands (idesc) { if (i < NELEMS (CURR_SLOT.opnd)) { - sep = parse_operand (CURR_SLOT.opnd + i); + sep = parse_operand (CURR_SLOT.opnd + i, '='); if (CURR_SLOT.opnd[i].X_op == O_absent) break; } @@ -6132,7 +6076,7 @@ parse_operands (idesc) { expressionS dummy; - sep = parse_operand (&dummy); + sep = parse_operand (&dummy, '='); if (dummy.X_op == O_absent) break; } @@ -6177,7 +6121,7 @@ parse_operands (idesc) /* now we can parse the first arg: */ saved_input_pointer = input_line_pointer; input_line_pointer = first_arg; - sep = parse_operand (CURR_SLOT.opnd + 0); + sep = parse_operand (CURR_SLOT.opnd + 0, '='); if (sep != '=') --num_outputs; /* force error */ input_line_pointer = saved_input_pointer; @@ -7614,6 +7558,15 @@ ia64_end_of_source () void ia64_start_line () { + static int first; + + if (!first) { + /* Make sure we don't reference input_line_pointer[-1] when that's + not valid. */ + first = 1; + return; + } + if (md.qp.X_op == O_register) as_bad ("qualifying predicate not followed by instruction"); md.qp.X_op = O_absent; @@ -7636,38 +7589,8 @@ ia64_start_line () else insn_group_break (1, 0, 0); } -} - -/* This is a hook for ia64_frob_label, so that it can distinguish tags from - labels. */ -static int defining_tag = 0; - -int -ia64_unrecognized_line (ch) - int ch; -{ - switch (ch) + else if (input_line_pointer[-1] == '{') { - case '(': - expression (&md.qp); - if (*input_line_pointer++ != ')') - { - as_bad ("Expected ')'"); - return 0; - } - if (md.qp.X_op != O_register) - { - as_bad ("Qualifying predicate expected"); - return 0; - } - if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64) - { - as_bad ("Predicate register expected"); - return 0; - } - return 1; - - case '{': if (md.manual_bundling) as_warn ("Found '{' when manual bundling is already turned on"); else @@ -7684,9 +7607,9 @@ ia64_unrecognized_line (ch) else as_warn (_("Found '{' after explicit switch to automatic mode")); } - return 1; - - case '}': + } + else if (input_line_pointer[-1] == '}') + { if (!md.manual_bundling) as_warn ("Found '}' when manual bundling is off"); else @@ -7699,17 +7622,36 @@ ia64_unrecognized_line (ch) && !md.mode_explicitly_set && !md.default_explicit_mode) dot_dv_mode ('A'); + } +} - /* Allow '{' to follow on the same line. We also allow ";;", but that - happens automatically because ';' is an end of line marker. */ - SKIP_WHITESPACE (); - if (input_line_pointer[0] == '{') +/* This is a hook for ia64_frob_label, so that it can distinguish tags from + labels. */ +static int defining_tag = 0; + +int +ia64_unrecognized_line (ch) + int ch; +{ + switch (ch) + { + case '(': + expression (&md.qp); + if (*input_line_pointer++ != ')') { - input_line_pointer++; - return ia64_unrecognized_line ('{'); + as_bad ("Expected ')'"); + return 0; + } + if (md.qp.X_op != O_register) + { + as_bad ("Qualifying predicate expected"); + return 0; + } + if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64) + { + as_bad ("Predicate register expected"); + return 0; } - - demand_empty_rest_of_line (); return 1; case '[': @@ -11732,7 +11674,7 @@ dot_alias (int section) if (name == end_name) { as_bad (_("expected symbol name")); - discard_rest_of_line (); + ignore_rest_of_line (); return; } diff -uprN binutils-2.16.91.0.1/gas/config/tc-m32c.c binutils-2.16.91.0.2/gas/config/tc-m32c.c --- binutils-2.16.91.0.1/gas/config/tc-m32c.c 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/config/tc-m32c.c 2005-07-20 12:27:27.840102858 -0700 @@ -0,0 +1,1017 @@ +/* tc-m32c.c -- Assembler for the Renesas M32C. + Copyright (C) 2005 Free Software Foundation. + Contributed by RedHat. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include +#include "as.h" +#include "subsegs.h" +#include "symcat.h" +#include "opcodes/m32c-desc.h" +#include "opcodes/m32c-opc.h" +#include "cgen.h" +#include "elf/common.h" +#include "elf/m32c.h" +#include "libbfd.h" +#include "libiberty.h" +#include "safe-ctype.h" + +/* Structure to hold all of the different components + describing an individual instruction. */ +typedef struct +{ + const CGEN_INSN * insn; + const CGEN_INSN * orig_insn; + CGEN_FIELDS fields; +#if CGEN_INT_INSN_P + CGEN_INSN_INT buffer [1]; +#define INSN_VALUE(buf) (*(buf)) +#else + unsigned char buffer [CGEN_MAX_INSN_SIZE]; +#define INSN_VALUE(buf) (buf) +#endif + char * addr; + fragS * frag; + int num_fixups; + fixS * fixups [GAS_CGEN_MAX_FIXUPS]; + int indices [MAX_OPERAND_INSTANCES]; +} +m32c_insn; + +const char comment_chars[] = ";"; +const char line_comment_chars[] = "#"; +const char line_separator_chars[] = "|"; +const char EXP_CHARS[] = "eE"; +const char FLT_CHARS[] = "dD"; + +#define M32C_SHORTOPTS "" +const char * md_shortopts = M32C_SHORTOPTS; + +/* assembler options */ +#define OPTION_CPU_M16C (OPTION_MD_BASE) +#define OPTION_CPU_M32C (OPTION_MD_BASE + 1) + +struct option md_longopts[] = +{ + { "m16c", no_argument, NULL, OPTION_CPU_M16C }, + { "m32c", no_argument, NULL, OPTION_CPU_M32C }, + {NULL, no_argument, NULL, 0} +}; +size_t md_longopts_size = sizeof (md_longopts); + +/* Default machine */ + +#define DEFAULT_MACHINE bfd_mach_m16c +#define DEFAULT_FLAGS EF_M32C_CPU_M16C + +static unsigned long m32c_mach = bfd_mach_m16c; +static int cpu_mach = (1 << MACH_M16C); +static int insn_size; + +/* Flags to set in the elf header */ +static flagword m32c_flags = DEFAULT_FLAGS; + +static unsigned int m32c_isa = (1 << ISA_M16C); + +static void +set_isa (enum isa_attr isa_num) +{ + m32c_isa = (1 << isa_num); +} + +static void s_bss (int); + +int +md_parse_option (int c, char * arg ATTRIBUTE_UNUSED) +{ + switch (c) + { + case OPTION_CPU_M16C: + m32c_flags = (m32c_flags & ~EF_M32C_CPU_MASK) | EF_M32C_CPU_M16C; + m32c_mach = bfd_mach_m16c; + cpu_mach = (1 << MACH_M16C); + set_isa (ISA_M16C); + break; + + case OPTION_CPU_M32C: + m32c_flags = (m32c_flags & ~EF_M32C_CPU_MASK) | EF_M32C_CPU_M32C; + m32c_mach = bfd_mach_m32c; + cpu_mach = (1 << MACH_M32C); + set_isa (ISA_M32C); + break; + + default: + return 0; + } + return 1; +} + +void +md_show_usage (FILE * stream) +{ + fprintf (stream, _(" M32C specific command line options:\n")); +} + +static void +s_bss (int ignore ATTRIBUTE_UNUSED) +{ + int temp; + + temp = get_absolute_expression (); + subseg_set (bss_section, (subsegT) temp); + demand_empty_rest_of_line (); +} + +/* The target specific pseudo-ops which we support. */ +const pseudo_typeS md_pseudo_table[] = +{ + { "bss", s_bss, 0}, + { "word", cons, 4 }, + { NULL, NULL, 0 } +}; + + +void +md_begin (void) +{ + /* Initialize the `cgen' interface. */ + + /* Set the machine number and endian. */ + gas_cgen_cpu_desc = m32c_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, cpu_mach, + CGEN_CPU_OPEN_ENDIAN, + CGEN_ENDIAN_BIG, + CGEN_CPU_OPEN_ISAS, m32c_isa, + CGEN_CPU_OPEN_END); + + m32c_cgen_init_asm (gas_cgen_cpu_desc); + + /* This is a callback from cgen to gas to parse operands. */ + cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); + + /* Set the ELF flags if desired. */ + if (m32c_flags) + bfd_set_private_flags (stdoutput, m32c_flags); + + /* Set the machine type */ + bfd_default_set_arch_mach (stdoutput, bfd_arch_m32c, m32c_mach); + + insn_size = 0; +} + +void +m32c_md_end (void) +{ + int i, n_nops; + + /* Pad with nops for objdump. */ + n_nops = (32 - ((insn_size) % 32)) / 8; + for (i = 1; i <= n_nops; i++) + md_assemble ("nop"); +} + +void +m32c_start_line_hook (void) +{ +#if 0 /* not necessary....handled in the .cpu file */ + char *s = input_line_pointer; + char *sg; + + for (s = input_line_pointer ; s && s[0] != '\n'; s++) + { + if (s[0] == ':') + { + /* Remove :g suffix. Squeeze out blanks. */ + if (s[1] == 'g') + { + for (sg = s - 1; sg && sg >= input_line_pointer; sg--) + { + sg[2] = sg[0]; + } + sg[1] = ' '; + sg[2] = ' '; + input_line_pointer += 2; + } + } + } +#endif +} + +/* Process [[indirect-operands]] in instruction str. */ + +static bfd_boolean +m32c_indirect_operand (char *str) +{ + char *new_str; + char *s; + char *ns; + int ns_len; + char *ns_end; + enum indirect_type {none, relative, absolute} ; + enum indirect_type indirection [3] = { none, none, none }; + int brace_n [3] = { 0, 0, 0 }; + int operand; + + s = str; + operand = 1; + for (s = str; *s; s++) + { + if (s[0] == ',') + operand = 2; + /* [abs] where abs is not a0 or a1 */ + if (s[1] == '[' && ! (s[2] == 'a' && (s[3] == '0' || s[3] == '1')) + && (ISBLANK (s[0]) || s[0] == ',')) + indirection[operand] = absolute; + if (s[0] == ']' && s[1] == ']') + indirection[operand] = relative; + if (s[0] == '[' && s[1] == '[') + indirection[operand] = relative; + } + + if (indirection[1] == none && indirection[2] == none) + return FALSE; + + operand = 1; + ns_len = strlen (str); + new_str = (char*) xmalloc (ns_len); + ns = new_str; + ns_end = ns + ns_len; + + for (s = str; *s; s++) + { + if (s[0] == ',') + operand = 2; + + if (s[0] == '[' && ! brace_n[operand]) + { + brace_n[operand] += 1; + /* Squeeze [[ to [ if this is an indirect operand. */ + if (indirection[operand] != none) + continue; + } + + else if (s[0] == '[' && brace_n[operand]) + { + brace_n[operand] += 1; + } + else if (s[0] == ']' && s[1] == ']' && indirection[operand] == relative) + { + s += 1; /* skip one ]. */ + brace_n[operand] -= 2; /* allow for 2 [. */ + } + else if (s[0] == ']' && indirection[operand] == absolute) + { + brace_n[operand] -= 1; + continue; /* skip closing ]. */ + } + else if (s[0] == ']') + { + brace_n[operand] -= 1; + } + *ns = s[0]; + ns += 1; + if (ns >= ns_end) + return FALSE; + if (s[0] == 0) + break; + } + *ns = '\0'; + for (operand = 1; operand <= 2; operand++) + if (brace_n[operand]) + { + fprintf (stderr, "Unmatched [[operand-%d]] %d\n", operand, brace_n[operand]); + } + + if (indirection[1] != none && indirection[2] != none) + md_assemble ("src-dest-indirect"); + else if (indirection[1] != none) + md_assemble ("src-indirect"); + else if (indirection[2] != none) + md_assemble ("dest-indirect"); + + md_assemble (new_str); + free (new_str); + return TRUE; +} + +void +md_assemble (char * str) +{ + static int last_insn_had_delay_slot = 0; + m32c_insn insn; + char * errmsg; + + if (m32c_mach == bfd_mach_m32c && m32c_indirect_operand (str)) + return; + + /* Initialize GAS's cgen interface for a new instruction. */ + gas_cgen_init_parse (); + + insn.insn = m32c_cgen_assemble_insn + (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg); + + if (!insn.insn) + { + as_bad (errmsg); + return; + } + + /* Doesn't really matter what we pass for RELAX_P here. */ + gas_cgen_finish_insn (insn.insn, insn.buffer, + CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL); + + last_insn_had_delay_slot + = CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT); + insn_size = CGEN_INSN_BITSIZE(insn.insn); +} + +/* The syntax in the manual says constants begin with '#'. + We just ignore it. */ + +void +md_operand (expressionS * exp) +{ + /* In case of a syntax error, escape back to try next syntax combo. */ + if (exp->X_op == O_absent) + gas_cgen_md_operand (exp); +} + +valueT +md_section_align (segT segment, valueT size) +{ + int align = bfd_get_section_alignment (stdoutput, segment); + return ((size + (1 << align) - 1) & (-1 << align)); +} + +symbolS * +md_undefined_symbol (char * name ATTRIBUTE_UNUSED) +{ + return 0; +} + +const relax_typeS md_relax_table[] = +{ + /* The fields are: + 1) most positive reach of this state, + 2) most negative reach of this state, + 3) how many bytes this mode will have in the variable part of the frag + 4) which index into the table to try if we can't fit into this one. */ + + /* 0 */ { 0, 0, 0, 0 }, /* unused */ + /* 1 */ { 0, 0, 0, 0 }, /* marker for "don't know yet" */ + + /* 2 */ { 127, -128, 2, 3 }, /* jcnd16_5.b */ + /* 3 */ { 32767, -32768, 5, 4 }, /* jcnd16_5.w */ + /* 4 */ { 0, 0, 6, 0 }, /* jcnd16_5.a */ + + /* 5 */ { 127, -128, 2, 6 }, /* jcnd16.b */ + /* 6 */ { 32767, -32768, 5, 7 }, /* jcnd16.w */ + /* 7 */ { 0, 0, 6, 0 }, /* jcnd16.a */ + + /* 8 */ { 8, 1, 1, 9 }, /* jmp16.s */ + /* 9 */ { 127, -128, 2, 10 }, /* jmp16.b */ + /* 10 */ { 32767, -32768, 3, 11 }, /* jmp16.w */ + /* 11 */ { 0, 0, 4, 0 }, /* jmp16.a */ + + /* 12 */ { 127, -128, 2, 13 }, /* jcnd32.b */ + /* 13 */ { 32767, -32768, 5, 14 }, /* jcnd32.w */ + /* 14 */ { 0, 0, 6, 0 }, /* jcnd32.a */ + + /* 15 */ { 8, 1, 1, 16 }, /* jmp32.s */ + /* 16 */ { 127, -128, 2, 17 }, /* jmp32.b */ + /* 17 */ { 32767, -32768, 3, 18 }, /* jmp32.w */ + /* 18 */ { 0, 0, 4, 0 } /* jmp32.a */ +}; + +enum { + M32C_MACRO_JCND16_5_W, + M32C_MACRO_JCND16_5_A, + M32C_MACRO_JCND16_W, + M32C_MACRO_JCND16_A, + M32C_MACRO_JCND32_W, + M32C_MACRO_JCND32_A, +} M32C_Macros; + +static struct { + int insn; + int bytes; + int insn_for_extern; + int pcrel_aim_offset; +} subtype_mappings[] = { + /* 0 */ { 0, 0, 0, 0 }, + /* 1 */ { 0, 0, 0, 0 }, + + /* 2 */ { M32C_INSN_JCND16_5, 2, -M32C_MACRO_JCND16_5_A, 1 }, + /* 3 */ { -M32C_MACRO_JCND16_5_W, 5, -M32C_MACRO_JCND16_5_A, 4 }, + /* 4 */ { -M32C_MACRO_JCND16_5_A, 6, -M32C_MACRO_JCND16_5_A, 0 }, + + /* 5 */ { M32C_INSN_JCND16, 3, -M32C_MACRO_JCND16_A, 1 }, + /* 6 */ { -M32C_MACRO_JCND16_W, 6, -M32C_MACRO_JCND16_A, 4 }, + /* 7 */ { -M32C_MACRO_JCND16_A, 7, -M32C_MACRO_JCND16_A, 0 }, + + /* 8 */ { M32C_INSN_JMP16_S, 1, M32C_INSN_JMP16_A, 0 }, + /* 9 */ { M32C_INSN_JMP16_B, 2, M32C_INSN_JMP16_A, 1 }, + /* 10 */ { M32C_INSN_JMP16_W, 3, M32C_INSN_JMP16_A, 2 }, + /* 11 */ { M32C_INSN_JMP16_A, 4, M32C_INSN_JMP16_A, 0 }, + + /* 12 */ { M32C_INSN_JCND32, 2, -M32C_MACRO_JCND32_A, 1 }, + /* 13 */ { -M32C_MACRO_JCND32_W, 5, -M32C_MACRO_JCND32_A, 4 }, + /* 14 */ { -M32C_MACRO_JCND32_A, 6, -M32C_MACRO_JCND32_A, 0 }, + + /* 15 */ { M32C_INSN_JMP32_S, 1, M32C_INSN_JMP32_A, 0 }, + /* 16 */ { M32C_INSN_JMP32_B, 2, M32C_INSN_JMP32_A, 1 }, + /* 17 */ { M32C_INSN_JMP32_W, 3, M32C_INSN_JMP32_A, 2 }, + /* 18 */ { M32C_INSN_JMP32_A, 4, M32C_INSN_JMP32_A, 0 } +}; +#define NUM_MAPPINGS (sizeof (subtype_mappings) / sizeof (subtype_mappings[0])) + +void +m32c_prepare_relax_scan (fragS *fragP, offsetT *aim, relax_substateT this_state) +{ + symbolS *symbolP = fragP->fr_symbol; + if (symbolP && !S_IS_DEFINED (symbolP)) + *aim = 0; + /* Adjust for m32c pcrel not being relative to the next opcode. */ + *aim += subtype_mappings[this_state].pcrel_aim_offset; +} + +static int +insn_to_subtype (int insn) +{ + unsigned int i; + for (i=0; ifr_opcode - fragP->fr_literal; + + if (fragP->fr_subtype == 1) + fragP->fr_subtype = insn_to_subtype (fragP->fr_cgen.insn->base->num); + + if (S_GET_SEGMENT (fragP->fr_symbol) != segment) + { + int new_insn; + + new_insn = subtype_mappings[fragP->fr_subtype].insn_for_extern; + fragP->fr_subtype = insn_to_subtype (new_insn); + } + + if (fragP->fr_cgen.insn->base + && fragP->fr_cgen.insn->base->num + != subtype_mappings[fragP->fr_subtype].insn + && subtype_mappings[fragP->fr_subtype].insn > 0) + { + int new_insn= subtype_mappings[fragP->fr_subtype].insn; + if (new_insn >= 0) + { + fragP->fr_cgen.insn = (fragP->fr_cgen.insn + - fragP->fr_cgen.insn->base->num + + new_insn); + } + } + + return subtype_mappings[fragP->fr_subtype].bytes - (fragP->fr_fix - where); +} + +/* *fragP has been relaxed to its final size, and now needs to have + the bytes inside it modified to conform to the new size. + + Called after relaxation is finished. + fragP->fr_type == rs_machine_dependent. + fragP->fr_subtype is the subtype of what the address relaxed to. */ + +static int +target_address_for (fragS *frag) +{ + int rv = frag->fr_offset; + symbolS *sym = frag->fr_symbol; + + if (sym) + rv += S_GET_VALUE (sym); + + /*printf("target_address_for returns %d\n", rv);*/ + return rv; +} + +void +md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, + segT sec ATTRIBUTE_UNUSED, + fragS * fragP ATTRIBUTE_UNUSED) +{ + int addend; + int operand; + int new_insn; + int where = fragP->fr_opcode - fragP->fr_literal; + unsigned char *op = (unsigned char *)fragP->fr_opcode; + + addend = target_address_for (fragP) - (fragP->fr_address + where); + new_insn = subtype_mappings[fragP->fr_subtype].insn; + + fragP->fr_fix = where + subtype_mappings[fragP->fr_subtype].bytes; + + switch (subtype_mappings[fragP->fr_subtype].insn) + { + case M32C_INSN_JCND16_5: + op[1] = addend - 1; + operand = M32C_OPERAND_LAB_8_8; + break; + + case -M32C_MACRO_JCND16_5_W: + op[0] ^= 0x04; + op[1] = 4; + op[2] = 0xf4; + op[3] = addend - 3; + op[4] = (addend - 3) >> 8; + operand = M32C_OPERAND_LAB_8_16; + where += 2; + new_insn = M32C_INSN_JMP16_W; + break; + + case -M32C_MACRO_JCND16_5_A: + op[0] ^= 0x04; + op[1] = 5; + op[2] = 0xfc; + operand = M32C_OPERAND_LAB_8_24; + where += 2; + new_insn = M32C_INSN_JMP16_A; + break; + + + case M32C_INSN_JCND16: + op[2] = addend - 2; + operand = M32C_OPERAND_LAB_16_8; + break; + + case -M32C_MACRO_JCND16_W: + op[1] ^= 0x04; + op[2] = 4; + op[3] = 0xf4; + op[4] = addend - 4; + op[5] = (addend - 4) >> 8; + operand = M32C_OPERAND_LAB_8_16; + where += 3; + new_insn = M32C_INSN_JMP16_W; + break; + + case -M32C_MACRO_JCND16_A: + op[1] ^= 0x04; + op[2] = 5; + op[3] = 0xfc; + operand = M32C_OPERAND_LAB_8_24; + where += 3; + new_insn = M32C_INSN_JMP16_A; + break; + + case M32C_INSN_JMP16_S: + op[0] = 0x60 | ((addend-2) & 0x07); + operand = M32C_OPERAND_LAB_5_3; + break; + + case M32C_INSN_JMP16_B: + op[0] = 0xfe; + op[1] = addend - 1; + operand = M32C_OPERAND_LAB_8_8; + break; + + case M32C_INSN_JMP16_W: + op[0] = 0xf4; + op[1] = addend - 1; + op[2] = (addend - 1) >> 8; + operand = M32C_OPERAND_LAB_8_16; + break; + + case M32C_INSN_JMP16_A: + op[0] = 0xfc; + op[1] = 0; + op[2] = 0; + op[3] = 0; + operand = M32C_OPERAND_LAB_8_24; + break; + + case M32C_INSN_JCND32: + op[1] = addend - 1; + operand = M32C_OPERAND_LAB_8_8; + break; + + case -M32C_MACRO_JCND32_W: + op[0] ^= 0x40; + op[1] = 4; + op[2] = 0xce; + op[3] = addend - 3; + op[4] = (addend - 3) >> 8; + operand = M32C_OPERAND_LAB_8_16; + where += 2; + new_insn = M32C_INSN_JMP32_W; + break; + + case -M32C_MACRO_JCND32_A: + op[0] ^= 0x40; + op[1] = 5; + op[2] = 0xcc; + operand = M32C_OPERAND_LAB_8_24; + where += 2; + new_insn = M32C_INSN_JMP32_A; + break; + + + + case M32C_INSN_JMP32_S: + addend = ((addend-2) & 0x07); + op[0] = 0x4a | (addend & 0x01) | ((addend << 3) & 0x30); + operand = M32C_OPERAND_LAB32_JMP_S; + break; + + case M32C_INSN_JMP32_B: + op[0] = 0xbb; + op[1] = addend - 1; + operand = M32C_OPERAND_LAB_8_8; + break; + + case M32C_INSN_JMP32_W: + op[0] = 0xce; + op[1] = addend - 1; + op[2] = (addend - 1) >> 8; + operand = M32C_OPERAND_LAB_8_16; + break; + + case M32C_INSN_JMP32_A: + op[0] = 0xcc; + op[1] = 0; + op[2] = 0; + op[3] = 0; + operand = M32C_OPERAND_LAB_8_24; + break; + + + default: + printf("\nHey! Need more opcode converters! missing: %d %s\n\n", + fragP->fr_subtype, + fragP->fr_cgen.insn->base->name); + abort(); + } + + if (S_GET_SEGMENT (fragP->fr_symbol) != sec + || operand == M32C_OPERAND_LAB_8_24) + { + assert (fragP->fr_cgen.insn != 0); + gas_cgen_record_fixup (fragP, + where, + fragP->fr_cgen.insn, + (fragP->fr_fix - where) * 8, + cgen_operand_lookup_by_num (gas_cgen_cpu_desc, + operand), + fragP->fr_cgen.opinfo, + fragP->fr_symbol, fragP->fr_offset); + } +} + +/* Functions concerning relocs. */ + +/* The location from which a PC relative jump should be calculated, + given a PC relative reloc. */ + +long +md_pcrel_from_section (fixS * fixP, segT sec) +{ + if (fixP->fx_addsy != (symbolS *) NULL + && (! S_IS_DEFINED (fixP->fx_addsy) + || S_GET_SEGMENT (fixP->fx_addsy) != sec)) + /* The symbol is undefined (or is defined but not in this section). + Let the linker figure it out. */ + return 0; + + return (fixP->fx_frag->fr_address + fixP->fx_where); +} + +/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. + Returns BFD_RELOC_NONE if no reloc type can be found. + *FIXP may be modified if desired. */ + +bfd_reloc_code_real_type +md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED, + const CGEN_OPERAND * operand, + fixS * fixP ATTRIBUTE_UNUSED) +{ + static const struct op_reloc { + /* A CGEN operand type that can be a relocatable expression. */ + CGEN_OPERAND_TYPE operand; + + /* The appropriate BFD reloc type to use for that. */ + bfd_reloc_code_real_type reloc; + + /* The offset from the start of the instruction to the field to be + relocated, in bytes. */ + int offset; + } op_reloc_table[] = { + + /* Absolute relocs for 16-bit fields. */ + { M32C_OPERAND_IMM_16_HI, BFD_RELOC_16, 2 }, + { M32C_OPERAND_IMM_24_HI, BFD_RELOC_16, 3 }, + { M32C_OPERAND_IMM_32_HI, BFD_RELOC_16, 4 }, + { M32C_OPERAND_DSP_16_S16, BFD_RELOC_16, 2 }, + { M32C_OPERAND_DSP_24_S16, BFD_RELOC_16, 3 }, + { M32C_OPERAND_DSP_32_S16, BFD_RELOC_16, 4 }, + { M32C_OPERAND_DSP_40_S16, BFD_RELOC_16, 5 }, + { M32C_OPERAND_DSP_8_U16, BFD_RELOC_16, 1 }, + { M32C_OPERAND_DSP_16_U16, BFD_RELOC_16, 2 }, + { M32C_OPERAND_DSP_24_U16, BFD_RELOC_16, 3 }, + { M32C_OPERAND_DSP_32_U16, BFD_RELOC_16, 4 }, + + /* Absolute relocs for 24-bit fields. */ + { M32C_OPERAND_LAB_8_24, BFD_RELOC_24, 1 }, + { M32C_OPERAND_DSP_16_U24, BFD_RELOC_24, 2 }, + { M32C_OPERAND_DSP_24_U24, BFD_RELOC_24, 3 }, + { M32C_OPERAND_DSP_32_U24, BFD_RELOC_24, 4 }, + { M32C_OPERAND_DSP_40_U24, BFD_RELOC_24, 5 }, + { M32C_OPERAND_DSP_8_U24, BFD_RELOC_24, 1 }, + + /* Absolute relocs for 32-bit fields. */ + { M32C_OPERAND_IMM_16_SI, BFD_RELOC_32, 2 }, + { M32C_OPERAND_IMM_24_SI, BFD_RELOC_32, 3 }, + { M32C_OPERAND_IMM_32_SI, BFD_RELOC_32, 4 }, + { M32C_OPERAND_IMM_40_SI, BFD_RELOC_32, 5 }, + + }; + + int i; + + for (i = ARRAY_SIZE (op_reloc_table); --i >= 0; ) + { + const struct op_reloc *or = &op_reloc_table[i]; + + if (or->operand == operand->type) + { + fixP->fx_where += or->offset; + fixP->fx_size -= or->offset; + return or->reloc; + } + } + + fprintf + (stderr, + "Error: tc-m32c.c:md_cgen_lookup_reloc Unimplemented relocation for operand %d\n", + operand->type); + + return BFD_RELOC_NONE; +} + +/* See whether we need to force a relocation into the output file. + This is used to force out switch and PC relative relocations when + relaxing. */ + +int +m32c_force_relocation (fixS * fixp) +{ + int reloc = fixp->fx_r_type; + + if (reloc > (int)BFD_RELOC_UNUSED) + { + reloc -= (int)BFD_RELOC_UNUSED; + switch (reloc) + { + case M32C_OPERAND_DSP_32_S16: + case M32C_OPERAND_DSP_32_U16: + case M32C_OPERAND_IMM_32_HI: + case M32C_OPERAND_DSP_16_S16: + case M32C_OPERAND_DSP_16_U16: + case M32C_OPERAND_IMM_16_HI: + case M32C_OPERAND_DSP_24_S16: + case M32C_OPERAND_DSP_24_U16: + case M32C_OPERAND_IMM_24_HI: + return 1; + } + } + else + { + if (fixp->fx_r_type == BFD_RELOC_16) + return 1; + } + + return generic_force_reloc (fixp); +} + +/* Write a value out to the object file, using the appropriate endianness. */ + +void +md_number_to_chars (char * buf, valueT val, int n) +{ + number_to_chars_littleendian (buf, val, n); +} + +/* Turn a string in input_line_pointer into a floating point constant of type + type, and store the appropriate bytes in *litP. The number of LITTLENUMS + emitted is stored in *sizeP . An error message is returned, or NULL on OK. */ + +/* Equal to MAX_PRECISION in atof-ieee.c. */ +#define MAX_LITTLENUMS 6 + +char * +md_atof (int type, char * litP, int * sizeP) +{ + int i; + int prec; + LITTLENUM_TYPE words [MAX_LITTLENUMS]; + char * t; + + switch (type) + { + case 'f': + case 'F': + case 's': + case 'S': + prec = 2; + break; + + case 'd': + case 'D': + case 'r': + case 'R': + prec = 4; + break; + + /* FIXME: Some targets allow other format chars for bigger sizes here. */ + + default: + * sizeP = 0; + return _("Bad call to md_atof()"); + } + + t = atof_ieee (input_line_pointer, type, words); + if (t) + input_line_pointer = t; + * sizeP = prec * sizeof (LITTLENUM_TYPE); + + for (i = 0; i < prec; i++) + { + md_number_to_chars (litP, (valueT) words[i], + sizeof (LITTLENUM_TYPE)); + litP += sizeof (LITTLENUM_TYPE); + } + + return 0; +} + +bfd_boolean +m32c_fix_adjustable (fixS * fixP) +{ + int reloc; + if (fixP->fx_addsy == NULL) + return 1; + + /* We need the symbol name for the VTABLE entries. */ + reloc = fixP->fx_r_type; + if (reloc > (int)BFD_RELOC_UNUSED) + { + reloc -= (int)BFD_RELOC_UNUSED; + switch (reloc) + { + case M32C_OPERAND_DSP_32_S16: + case M32C_OPERAND_DSP_32_U16: + case M32C_OPERAND_IMM_32_HI: + case M32C_OPERAND_DSP_16_S16: + case M32C_OPERAND_DSP_16_U16: + case M32C_OPERAND_IMM_16_HI: + case M32C_OPERAND_DSP_24_S16: + case M32C_OPERAND_DSP_24_U16: + case M32C_OPERAND_IMM_24_HI: + return 0; + } + } + else + { + if (fixP->fx_r_type == BFD_RELOC_16) + return 0; + } + + /* Do not adjust relocations involving symbols in merged sections. + + A reloc patching in the value of some symbol S plus some addend A + can be produced in different ways: + + 1) It might simply be a reference to the data at S + A. Clearly, + if linker merging shift that data around, the value patched in + by the reloc needs to be adjusted accordingly. + + 2) Or, it might be a reference to S, with A added in as a constant + bias. For example, given code like this: + + static int S[100]; + + ... S[i - 8] ... + + it would be reasonable for the compiler to rearrange the array + reference to something like: + + ... (S-8)[i] ... + + and emit assembly code that refers to S - (8 * sizeof (int)), + so the subtraction is done entirely at compile-time. In this + case, the reloc's addend A would be -(8 * sizeof (int)), and + shifting around code or data at S + A should not affect the + reloc: the reloc isn't referring to that code or data at all. + + The linker has no way of knowing which case it has in hand. So, + to disambiguate, we have the linker always treat reloc addends as + in case 2): they're constants that should be simply added to the + symbol value, just like the reloc says. And we express case 1) + in different way: we have the compiler place a label at the real + target, and reference that label with an addend of zero. (The + compiler is unlikely to reference code using a label plus an + offset anyway, since it doesn't know the sizes of the + instructions.) + + The simplification being done by gas/write.c:adjust_reloc_syms, + however, turns the explicit-label usage into the label-plus- + offset usage, re-introducing the ambiguity the compiler avoided. + So we need to disable that simplification for symbols referring + to merged data. + + This only affects object size a little bit. */ + if (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) + return 0; + + return 1; +} + +/* Worker function for m32c_is_colon_insn(). */ +static char restore_colon PARAMS ((int)); + +static char +restore_colon (int advance_i_l_p_by) +{ + char c; + + /* Restore the colon, and advance input_line_pointer to + the end of the new symbol. */ + * input_line_pointer = ':'; + input_line_pointer += advance_i_l_p_by; + c = * input_line_pointer; + * input_line_pointer = 0; + + return c; +} + +/* Determines if the symbol starting at START and ending in + a colon that was at the location pointed to by INPUT_LINE_POINTER + (but which has now been replaced bu a NUL) is in fact an + :Z, :S, :Q, or :G suffix. + If it is, then it restores the colon, advances INPUT_LINE_POINTER + to the real end of the instruction/symbol, and returns the character + that really terminated the symbol. Otherwise it returns 0. */ +char +m32c_is_colon_insn (char *start ATTRIBUTE_UNUSED) +{ + char * i_l_p = input_line_pointer; + + /* Check to see if the text following the colon is 'G' */ + if (TOLOWER (i_l_p[1]) == 'g' && (i_l_p[2] == ' ' || i_l_p[2] == '\t')) + return restore_colon (2); + + /* Check to see if the text following the colon is 'Q' */ + if (TOLOWER (i_l_p[1]) == 'q' && (i_l_p[2] == ' ' || i_l_p[2] == '\t')) + return restore_colon (2); + + /* Check to see if the text following the colon is 'S' */ + if (TOLOWER (i_l_p[1]) == 's' && (i_l_p[2] == ' ' || i_l_p[2] == '\t')) + return restore_colon (2); + + /* Check to see if the text following the colon is 'Z' */ + if (TOLOWER (i_l_p[1]) == 'z' && (i_l_p[2] == ' ' || i_l_p[2] == '\t')) + return restore_colon (2); + + return 0; +} diff -uprN binutils-2.16.91.0.1/gas/config/tc-m32c.h binutils-2.16.91.0.2/gas/config/tc-m32c.h --- binutils-2.16.91.0.1/gas/config/tc-m32c.h 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/config/tc-m32c.h 2005-07-20 12:27:27.841102693 -0700 @@ -0,0 +1,89 @@ +/* tc-m32c.h -- Header file for tc-m32c.c. + Copyright (C) 2004 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#define TC_M32C + +#ifndef BFD_ASSEMBLER +#error M32C support requires BFD_ASSEMBLER +#endif + +#define LISTING_HEADER "M16C/M32C GAS " + +/* The target BFD architecture. */ +#define TARGET_ARCH bfd_arch_m32c + +#define TARGET_FORMAT "elf32-m32c" + +#define TARGET_BYTES_BIG_ENDIAN 1 + +#define md_end m32c_md_end +extern void m32c_md_end (void); + +#define md_start_line_hook m32c_start_line_hook +extern void m32c_start_line_hook (void); + +/* call md_pcrel_from_section, not md_pcrel_from */ +long md_pcrel_from_section PARAMS ((struct fix *, segT)); +#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC) + +/* Permit temporary numeric labels. */ +#define LOCAL_LABELS_FB 1 + +#define DIFF_EXPR_OK /* .-foo gets turned into PC relative relocs */ + +/* We don't need to handle .word strangely. */ +#define WORKING_DOT_WORD + +#define md_apply_fix gas_cgen_md_apply_fix + +#define tc_fix_adjustable(fixP) m32c_fix_adjustable (fixP) +extern bfd_boolean m32c_fix_adjustable PARAMS ((struct fix *)); + +/* When relaxing, we need to emit various relocs we otherwise wouldn't. */ +#define TC_FORCE_RELOCATION(fix) m32c_force_relocation (fix) +extern int m32c_force_relocation PARAMS ((struct fix *)); + +extern const struct relax_type md_relax_table[]; +#define TC_GENERIC_RELAX_TABLE md_relax_table + +extern void m32c_prepare_relax_scan PARAMS ((fragS *, offsetT *, relax_substateT state)); +#define md_prepare_relax_scan(FRAGP, ADDR, AIM, STATE, TYPE) \ + m32c_prepare_relax_scan(FRAGP, &AIM, STATE) + +/* Values passed to md_apply_fix don't include the symbol value. */ +#define MD_APPLY_SYM_VALUE(FIX) 0 + +#define tc_gen_reloc gas_cgen_tc_gen_reloc + +/* Call md_pcrel_from_section(), not md_pcrel_from(). */ +#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC) +extern long md_pcrel_from_section PARAMS ((struct fix *, segT)); + +/* We need a special version of the TC_START_LABEL macro so that we + allow the :Z, :S, :Q and :G suffixes to be + parsed as such. Note - in a HORRIBLE HACK, we make use of the + knowledge that this marco is only ever evaluated in one place + (read_a_source_file in read.c) where we can access the local + variable 's' - the start of the symbol that was terminated by + 'character'. Also we need to be able to change the contents of + the local variable 'c' which is passed to this macro as 'character'. */ +#define TC_START_LABEL(character, i_l_p) \ + ((character) != ':' ? 0 : (character = m32c_is_colon_insn (s)) ? 0 : ((character = ':'), 1)) +extern char m32c_is_colon_insn PARAMS ((char *)); diff -uprN binutils-2.16.91.0.1/gas/config/tc-m32r.c binutils-2.16.91.0.2/gas/config/tc-m32r.c --- binutils-2.16.91.0.1/gas/config/tc-m32r.c 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-m32r.c 2005-07-20 12:27:27.843102364 -0700 @@ -2258,6 +2258,17 @@ tc_gen_reloc (asection * section, fixS * reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; + + if (fixP->fx_pcrel) + { + if (fixP->fx_r_type == BFD_RELOC_32) + fixP->fx_r_type = BFD_RELOC_32_PCREL; + else if (fixP->fx_r_type == BFD_RELOC_16) + { + fixP->fx_r_type = BFD_RELOC_16_PCREL; + bfd_set_error (bfd_error_bad_value); + } + } code = fixP->fx_r_type; if (pic_code) @@ -2327,7 +2338,8 @@ printf(" => %s\n",reloc->howto->name); /* Use fx_offset for these cases. */ if ( fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY - || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT) + || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT + || fixP->fx_r_type == BFD_RELOC_32_PCREL) reloc->addend = fixP->fx_offset; else if ((!pic_code && code != BFD_RELOC_M32R_26_PLTREL) diff -uprN binutils-2.16.91.0.1/gas/config/tc-m68hc11.h binutils-2.16.91.0.2/gas/config/tc-m68hc11.h --- binutils-2.16.91.0.1/gas/config/tc-m68hc11.h 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-m68hc11.h 2005-07-20 12:27:27.844102199 -0700 @@ -22,9 +22,7 @@ #define TC_M68HC11 #define TC_M68HC12 -#ifdef ANSI_PROTOTYPES struct fix; -#endif /* Define TC_M68K so that we can use the MRI mode. */ #define TC_M68K diff -uprN binutils-2.16.91.0.1/gas/config/tc-m68k.h binutils-2.16.91.0.2/gas/config/tc-m68k.h --- binutils-2.16.91.0.1/gas/config/tc-m68k.h 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-m68k.h 2005-07-20 12:27:27.844102199 -0700 @@ -22,9 +22,7 @@ #define TC_M68K 1 -#ifdef ANSI_PROTOTYPES struct fix; -#endif #define TARGET_BYTES_BIG_ENDIAN 1 @@ -73,7 +71,7 @@ struct fix; #define TC_COFF_FIX2RTYPE(FIX) tc_coff_fix2rtype(FIX) #define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag) -extern int tc_coff_sizemachdep PARAMS ((struct frag *)); +extern int tc_coff_sizemachdep (struct frag *); #ifdef TE_SUN3 /* This variable contains the value to write out at the beginning of the a.out file. The 2<<16 means that this is a 68020 file instead @@ -132,19 +130,19 @@ extern const char *m68k_comment_chars; #endif #endif -extern void m68k_mri_mode_change PARAMS ((int)); +extern void m68k_mri_mode_change (int); #define MRI_MODE_CHANGE(i) m68k_mri_mode_change (i) -extern int m68k_conditional_pseudoop PARAMS ((pseudo_typeS *)); +extern int m68k_conditional_pseudoop (pseudo_typeS *); #define tc_conditional_pseudoop(pop) m68k_conditional_pseudoop (pop) -extern void m68k_frob_label PARAMS ((symbolS *)); +extern void m68k_frob_label (symbolS *); #define tc_frob_label(sym) m68k_frob_label (sym) -extern void m68k_flush_pending_output PARAMS ((void)); +extern void m68k_flush_pending_output (void); #define md_flush_pending_output() m68k_flush_pending_output () -extern void m68k_frob_symbol PARAMS ((symbolS *)); +extern void m68k_frob_symbol (symbolS *); #ifdef BFD_ASSEMBLER @@ -167,7 +165,7 @@ while (0) #ifdef OBJ_ELF #define tc_fix_adjustable(X) tc_m68k_fix_adjustable(X) -extern int tc_m68k_fix_adjustable PARAMS ((struct fix *)); +extern int tc_m68k_fix_adjustable (struct fix *); /* Target *-*-elf implies an embedded target. No shared libs. *-*-uclinux also requires special casing to prevent GAS from @@ -179,7 +177,7 @@ extern int tc_m68k_fix_adjustable PARAMS #define MD_APPLY_SYM_VALUE(FIX) 0 #define elf_tc_final_processing m68k_elf_final_processing -extern void m68k_elf_final_processing PARAMS ((void)); +extern void m68k_elf_final_processing (void); #endif #else /* ! BFD_ASSEMBLER */ @@ -198,10 +196,10 @@ extern void m68k_elf_final_processing PA #define DIFF_EXPR_OK -extern void m68k_init_after_args PARAMS ((void)); +extern void m68k_init_after_args (void); #define tc_init_after_args m68k_init_after_args -extern int m68k_parse_long_option PARAMS ((char *)); +extern int m68k_parse_long_option (char *); #define md_parse_long_option m68k_parse_long_option #define md_operand(x) diff -uprN binutils-2.16.91.0.1/gas/config/tc-ms1.c binutils-2.16.91.0.2/gas/config/tc-ms1.c --- binutils-2.16.91.0.1/gas/config/tc-ms1.c 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/config/tc-ms1.c 2005-07-20 12:27:27.846101869 -0700 @@ -0,0 +1,504 @@ +/* tc-ms1.c -- Assembler for the Morpho Technologies ms-I. + Copyright (C) 2005 Free Software Foundation. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#include +#include "as.h" +#include "dwarf2dbg.h" +#include "subsegs.h" +#include "symcat.h" +#include "opcodes/ms1-desc.h" +#include "opcodes/ms1-opc.h" +#include "cgen.h" +#include "elf/common.h" +#include "elf/ms1.h" +#include "libbfd.h" + +/* Structure to hold all of the different components + describing an individual instruction. */ +typedef struct +{ + const CGEN_INSN * insn; + const CGEN_INSN * orig_insn; + CGEN_FIELDS fields; +#if CGEN_INT_INSN_P + CGEN_INSN_INT buffer [1]; +#define INSN_VALUE(buf) (*(buf)) +#else + unsigned char buffer [CGEN_MAX_INSN_SIZE]; +#define INSN_VALUE(buf) (buf) +#endif + char * addr; + fragS * frag; + int num_fixups; + fixS * fixups [GAS_CGEN_MAX_FIXUPS]; + int indices [MAX_OPERAND_INSTANCES]; +} +ms1_insn; + + +const char comment_chars[] = ";"; +const char line_comment_chars[] = "#"; +const char line_separator_chars[] = ""; +const char EXP_CHARS[] = "eE"; +const char FLT_CHARS[] = "dD"; + +/* The target specific pseudo-ops which we support. */ +const pseudo_typeS md_pseudo_table[] = +{ + { "word", cons, 4 }, + { "file", (void (*) (int)) dwarf2_directive_file, 0 }, + { "loc", dwarf2_directive_loc, 0 }, + { NULL, NULL, 0 } +}; + + + +static int no_scheduling_restrictions = 0; + +struct option md_longopts[] = +{ +#define OPTION_NO_SCHED_REST (OPTION_MD_BASE) + { "nosched", no_argument, NULL, OPTION_NO_SCHED_REST }, +#define OPTION_MARCH (OPTION_MD_BASE + 1) + { "march", required_argument, NULL, OPTION_MARCH}, + { NULL, no_argument, NULL, 0 }, +}; +size_t md_longopts_size = sizeof (md_longopts); + +const char * md_shortopts = ""; + +/* Mach selected from command line. */ +static int ms1_mach = bfd_mach_ms1; +static unsigned ms1_mach_bitmask = 0; + +/* Flags to set in the elf header */ +static flagword ms1_flags = EF_MS1_CPU_MRISC; + +/* The architecture to use. */ +enum ms1_architectures + { + ms1_64_001, + ms1_16_002, + ms1_16_003 + }; + +/* MS1 architecture we are using for this output file. */ +static enum ms1_architectures ms1_arch = ms1_64_001; + +int +md_parse_option (int c ATTRIBUTE_UNUSED, char * arg) +{ + switch (c) + { + case OPTION_MARCH: + if (strcasecmp (arg, "MS1-64-001") == 0) + { + ms1_flags = (ms1_flags & ~EF_MS1_CPU_MASK) | EF_MS1_CPU_MRISC; + ms1_mach = bfd_mach_ms1; + ms1_mach_bitmask = 1 << MACH_MS1; + ms1_arch = ms1_64_001; + } + else if (strcasecmp (arg, "MS1-16-002") == 0) + { + ms1_flags = (ms1_flags & ~EF_MS1_CPU_MASK) | EF_MS1_CPU_MRISC; + ms1_mach = bfd_mach_ms1; + ms1_mach_bitmask = 1 << MACH_MS1; + ms1_arch = ms1_16_002; + } + else if (strcasecmp (arg, "MS1-16-003") == 0) + { + ms1_flags = (ms1_flags & ~EF_MS1_CPU_MASK) | EF_MS1_CPU_MRISC2; + ms1_mach = bfd_mach_mrisc2; + ms1_mach_bitmask = 1 << MACH_MS1_003; + ms1_arch = ms1_16_003; + } + case OPTION_NO_SCHED_REST: + no_scheduling_restrictions = 1; + break; + default: + return 0; + } + + return 1; +} + + +void +md_show_usage (FILE * stream) +{ + fprintf (stream, _("MS1 specific command line options:\n")); + fprintf (stream, _(" -march=ms1-64-001 allow ms1-64-001 instructions (default) \n")); + fprintf (stream, _(" -march=ms1-16-002 allow ms1-16-002 instructions \n")); + fprintf (stream, _(" -march=ms1-16-003 allow ms1-16-003 instructions \n")); + fprintf (stream, _(" -nosched disable scheduling restrictions \n")); +} + + +void +md_begin (void) +{ + /* Initialize the `cgen' interface. */ + + /* Set the machine number and endian. */ + gas_cgen_cpu_desc = ms1_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, ms1_mach_bitmask, + CGEN_CPU_OPEN_ENDIAN, + CGEN_ENDIAN_BIG, + CGEN_CPU_OPEN_END); + ms1_cgen_init_asm (gas_cgen_cpu_desc); + + /* This is a callback from cgen to gas to parse operands. */ + cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); + + /* Set the ELF flags if desired. */ + if (ms1_flags) + bfd_set_private_flags (stdoutput, ms1_flags); + + /* Set the machine type. */ + bfd_default_set_arch_mach (stdoutput, bfd_arch_ms1, ms1_mach); +} + +void +md_assemble (char * str) +{ + static long delayed_load_register = 0; + static int last_insn_had_delay_slot = 0; + static int last_insn_in_noncond_delay_slot = 0; + static int last_insn_has_load_delay = 0; + static int last_insn_was_memory_access = 0; + static int last_insn_was_io_insn = 0; + static int last_insn_was_arithmetic_or_logic = 0; + static int last_insn_was_branch_insn = 0; + static int last_insn_was_conditional_branch_insn = 0; + + ms1_insn insn; + char * errmsg; + + /* Initialize GAS's cgen interface for a new instruction. */ + gas_cgen_init_parse (); + + insn.insn = ms1_cgen_assemble_insn + (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg); + + if (!insn.insn) + { + as_bad ("%s", errmsg); + return; + } + + /* Doesn't really matter what we pass for RELAX_P here. */ + gas_cgen_finish_insn (insn.insn, insn.buffer, + CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL); + + + /* Handle Scheduling Restrictions. */ + if (!no_scheduling_restrictions) + { + /* Detect consecutive Memory Accesses. */ + if (last_insn_was_memory_access + && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MEMORY_ACCESS) + && ms1_mach == ms1_64_001) + as_warn (_("instruction %s may not follow another memory access instruction."), + CGEN_INSN_NAME (insn.insn)); + + /* Detect consecutive I/O Instructions. */ + else if (last_insn_was_io_insn + && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_IO_INSN)) + as_warn (_("instruction %s may not follow another I/O instruction."), + CGEN_INSN_NAME (insn.insn)); + + /* Detect consecutive branch instructions. */ + else if (last_insn_was_branch_insn + && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN)) + as_warn (_("%s may not occupy the delay slot of another branch insn."), + CGEN_INSN_NAME (insn.insn)); + + /* Detect data dependencies on delayed loads: memory and input insns. */ + if (last_insn_has_load_delay && delayed_load_register) + { + if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1) + && insn.fields.f_sr1 == delayed_load_register) + as_warn (_("operand references R%ld of previous load."), + insn.fields.f_sr1); + + if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2) + && insn.fields.f_sr2 == delayed_load_register) + as_warn (_("operand references R%ld of previous load."), + insn.fields.f_sr2); + } + + /* Detect data dependency between conditional branch instruction + and an immediately preceding arithmetic or logical instruction. */ + if (last_insn_was_arithmetic_or_logic + && !last_insn_in_noncond_delay_slot + && (delayed_load_register != 0) + && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN) + && ms1_arch == ms1_64_001) + { + if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1) + && insn.fields.f_sr1 == delayed_load_register) + as_warn (_("conditional branch or jal insn's operand references R%ld of previous arithmetic or logic insn."), + insn.fields.f_sr1); + + if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2) + && insn.fields.f_sr2 == delayed_load_register) + as_warn (_("conditional branch or jal insn's operand references R%ld of previous arithmetic or logic insn."), + insn.fields.f_sr2); + } + } + + /* Keep track of details of this insn for processing next insn. */ + last_insn_in_noncond_delay_slot = last_insn_was_branch_insn + && !last_insn_was_conditional_branch_insn; + + last_insn_had_delay_slot = + CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT); + + last_insn_has_load_delay = + CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_LOAD_DELAY); + + last_insn_was_memory_access = + CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MEMORY_ACCESS); + + last_insn_was_io_insn = + CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_IO_INSN); + + last_insn_was_arithmetic_or_logic = + CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_AL_INSN); + + last_insn_was_branch_insn = + CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN); + + last_insn_was_conditional_branch_insn = + CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN) + && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2); + + if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRDR)) + delayed_load_register = insn.fields.f_dr; + else if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRDRRR)) + delayed_load_register = insn.fields.f_drrr; + else /* Insns has no destination register. */ + delayed_load_register = 0; + + /* Generate dwarf2 line numbers. */ + dwarf2_emit_insn (4); +} + +valueT +md_section_align (segT segment, valueT size) +{ + int align = bfd_get_section_alignment (stdoutput, segment); + + return ((size + (1 << align) - 1) & (-1 << align)); +} + +symbolS * +md_undefined_symbol (char * name ATTRIBUTE_UNUSED) +{ + return NULL; +} + +int +md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED, + segT segment ATTRIBUTE_UNUSED) +{ + as_fatal (_("md_estimate_size_before_relax\n")); + return 1; +} + +/* *fragP has been relaxed to its final size, and now needs to have + the bytes inside it modified to conform to the new size. + + Called after relaxation is finished. + fragP->fr_type == rs_machine_dependent. + fragP->fr_subtype is the subtype of what the address relaxed to. */ + +void +md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, + segT sec ATTRIBUTE_UNUSED, + fragS * fragP ATTRIBUTE_UNUSED) +{ +} + + +/* Functions concerning relocs. */ + +long +md_pcrel_from_section (fixS *fixP, segT sec) +{ + if (fixP->fx_addsy != (symbolS *) NULL + && (!S_IS_DEFINED (fixP->fx_addsy) + || S_GET_SEGMENT (fixP->fx_addsy) != sec)) + /* The symbol is undefined (or is defined but not in this section). + Let the linker figure it out. */ + return 0; + + /* Return the address of the opcode - cgen adjusts for opcode size + itself, to be consistent with the disassembler, which must do + so. */ + return fixP->fx_where + fixP->fx_frag->fr_address; +} + + +/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. + Returns BFD_RELOC_NONE if no reloc type can be found. + *FIXP may be modified if desired. */ + +bfd_reloc_code_real_type +md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED, + const CGEN_OPERAND * operand, + fixS * fixP ATTRIBUTE_UNUSED) +{ + bfd_reloc_code_real_type result; + + result = BFD_RELOC_NONE; + + switch (operand->type) + { + case MS1_OPERAND_IMM16O: + result = BFD_RELOC_16_PCREL; + fixP->fx_pcrel = 1; + /* fixP->fx_no_overflow = 1; */ + break; + case MS1_OPERAND_IMM16: + case MS1_OPERAND_IMM16Z: + /* These may have been processed at parse time. */ + if (fixP->fx_cgen.opinfo != 0) + result = fixP->fx_cgen.opinfo; + fixP->fx_no_overflow = 1; + break; + default: + result = BFD_RELOC_NONE; + break; + } + + return result; +} + +/* Write a value out to the object file, using the appropriate endianness. */ + +void +md_number_to_chars (char * buf, valueT val, int n) +{ + number_to_chars_bigendian (buf, val, n); +} + +/* Turn a string in input_line_pointer into a floating point constant of type + type, and store the appropriate bytes in *litP. The number of LITTLENUMS + emitted is stored in *sizeP . An error message is returned, or NULL on OK. */ + +/* Equal to MAX_PRECISION in atof-ieee.c. */ +#define MAX_LITTLENUMS 6 + +char * +md_atof (type, litP, sizeP) + char type; + char * litP; + int * sizeP; +{ + int prec; + LITTLENUM_TYPE words [MAX_LITTLENUMS]; + LITTLENUM_TYPE * wordP; + char * t; + + switch (type) + { + case 'f': + case 'F': + case 's': + case 'S': + prec = 2; + break; + + case 'd': + case 'D': + case 'r': + case 'R': + prec = 4; + break; + + /* FIXME: Some targets allow other format chars for bigger sizes here. */ + + default: + * sizeP = 0; + return _("Bad call to md_atof()"); + } + + t = atof_ieee (input_line_pointer, type, words); + if (t) + input_line_pointer = t; + * sizeP = prec * sizeof (LITTLENUM_TYPE); + + /* This loops outputs the LITTLENUMs in REVERSE order; + in accord with the ms1 endianness. */ + for (wordP = words; prec--;) + { + md_number_to_chars (litP, (valueT) (*wordP++), sizeof (LITTLENUM_TYPE)); + litP += sizeof (LITTLENUM_TYPE); + } + + return 0; +} + +/* See whether we need to force a relocation into the output file. */ + +int +ms1_force_relocation (fixS * fixp ATTRIBUTE_UNUSED) +{ + return 0; +} + +void +ms1_apply_fix (fixS *fixP, valueT *valueP, segT seg) +{ + if ((fixP->fx_pcrel != 0) && (fixP->fx_r_type == BFD_RELOC_32)) + fixP->fx_r_type = BFD_RELOC_32_PCREL; + + gas_cgen_md_apply_fix (fixP, valueP, seg); +} + +bfd_boolean +ms1_fix_adjustable (fixS * fixP) +{ + bfd_reloc_code_real_type reloc_type; + + if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) + { + const CGEN_INSN *insn = NULL; + int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; + const CGEN_OPERAND *operand; + + operand = cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex); + reloc_type = md_cgen_lookup_reloc (insn, operand, fixP); + } + else + reloc_type = fixP->fx_r_type; + + if (fixP->fx_addsy == NULL) + return TRUE; + + /* Prevent all adjustments to global symbols. */ + if (S_IS_EXTERNAL (fixP->fx_addsy)) + return FALSE; + + if (S_IS_WEAK (fixP->fx_addsy)) + return FALSE; + + return 1; +} diff -uprN binutils-2.16.91.0.1/gas/config/tc-ms1.h binutils-2.16.91.0.2/gas/config/tc-ms1.h --- binutils-2.16.91.0.1/gas/config/tc-ms1.h 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/config/tc-ms1.h 2005-07-20 12:27:27.846101869 -0700 @@ -0,0 +1,75 @@ +/* tc-ms1.h -- Header file for tc-ms1.c. + Copyright (C) 2005 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#define TC_MS1 + +#ifndef BFD_ASSEMBLER +/* Leading space so will compile with cc. */ + #error MS1 support requires BFD_ASSEMBLER +#endif + +#define LISTING_HEADER "MS1 GAS " + +/* The target BFD architecture. */ +#define TARGET_ARCH bfd_arch_ms1 + +#define TARGET_FORMAT "elf32-ms1" + +#define TARGET_BYTES_BIG_ENDIAN 1 + +/* Permit temporary numeric labels. */ +#define LOCAL_LABELS_FB 1 + +/* .-foo gets turned into PC relative relocs. */ +#define DIFF_EXPR_OK + +/* We don't need to handle .word strangely. */ +#define WORKING_DOT_WORD + +/* All ms1 instructions are multiples of 32 bits. */ +#define DWARF2_LINE_MIN_INSN_LENGTH 4 + +#define LITERAL_PREFIXDOLLAR_HEX +#define LITERAL_PREFIXPERCENT_BIN + +#define md_apply_fix ms1_apply_fix +extern void ms1_apply_fix (struct fix *, valueT *, segT); + +/* Call md_pcrel_from_section(), not md_pcrel_from(). */ +#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC) +extern long md_pcrel_from_section (struct fix *, segT); + +#define obj_fix_adjustable(fixP) iq2000_fix_adjustable (fixP) +extern bfd_boolean ms1_fix_adjustable (struct fix *); + +/* Values passed to md_apply_fix don't include the symbol value. */ +#define MD_APPLY_SYM_VALUE(FIX) 0 + +#define tc_gen_reloc gas_cgen_tc_gen_reloc + +#define md_operand(x) gas_cgen_md_operand (x) +extern void gas_cgen_md_operand (expressionS *); + +#define TC_FORCE_RELOCATION(fixp) ms1_force_relocation (fixp) +extern int ms1_force_relocation (struct fix *); + +#define tc_fix_adjustable(fixP) ms1_fix_adjustable (fixP) +extern bfd_boolean ms1_fix_adjustable (struct fix *); + diff -uprN binutils-2.16.91.0.1/gas/config/tc-pdp11.c binutils-2.16.91.0.2/gas/config/tc-pdp11.c --- binutils-2.16.91.0.1/gas/config/tc-pdp11.c 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-pdp11.c 2005-07-20 12:27:27.852100880 -0700 @@ -243,7 +243,7 @@ md_apply_fix (fixS *fixP, buf = fixP->fx_where + fixP->fx_frag->fr_literal; size = fixP->fx_size; - code = md_chars_to_number (buf, size); + code = md_chars_to_number ((unsigned char *) buf, size); switch (fixP->fx_r_type) { diff -uprN binutils-2.16.91.0.1/gas/config/tc-ppc.c binutils-2.16.91.0.2/gas/config/tc-ppc.c --- binutils-2.16.91.0.1/gas/config/tc-ppc.c 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-ppc.c 2005-07-20 12:27:27.858099890 -0700 @@ -1216,9 +1216,13 @@ ppc_target_format () #endif #endif #ifdef OBJ_ELF +# ifdef TE_VXWORKS + return "elf32-powerpc-vxworks"; +# else return (target_big_endian ? (ppc_obj64 ? "elf64-powerpc" : "elf32-powerpc") : (ppc_obj64 ? "elf64-powerpcle" : "elf32-powerpcle")); +# endif #endif } diff -uprN binutils-2.16.91.0.1/gas/config/tc-ppc.h binutils-2.16.91.0.2/gas/config/tc-ppc.h --- binutils-2.16.91.0.1/gas/config/tc-ppc.h 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-ppc.h 2005-07-20 12:27:27.859099726 -0700 @@ -22,9 +22,7 @@ #define TC_PPC -#ifdef ANSI_PROTOTYPES struct fix; -#endif /* Set the endianness we are using. Default to big endian. */ #ifndef TARGET_BYTES_BIG_ENDIAN diff -uprN binutils-2.16.91.0.1/gas/config/tc-s390.h binutils-2.16.91.0.2/gas/config/tc-s390.h --- binutils-2.16.91.0.1/gas/config/tc-s390.h 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-s390.h 2005-07-20 12:27:27.859099726 -0700 @@ -21,9 +21,7 @@ #define TC_S390 -#ifdef ANSI_PROTOTYPES struct fix; -#endif #ifndef BFD_ASSEMBLER #error S390 support requires BFD_ASSEMBLER diff -uprN binutils-2.16.91.0.1/gas/config/tc-sh.h binutils-2.16.91.0.2/gas/config/tc-sh.h --- binutils-2.16.91.0.1/gas/config/tc-sh.h 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-sh.h 2005-07-20 12:27:27.860099561 -0700 @@ -23,7 +23,6 @@ #define TARGET_ARCH bfd_arch_sh -#if ANSI_PROTOTYPES /* The type fixS is defined (to struct fix) in write.h, but write.h uses definitions from this file. To avoid problems with including write.h after the "right" definitions, don't; just forward-declare struct fix @@ -31,7 +30,6 @@ struct fix; struct segment_info_struct; struct internal_reloc; -#endif /* Whether -relax was used. */ extern int sh_relax; diff -uprN binutils-2.16.91.0.1/gas/config/tc-sparc.h binutils-2.16.91.0.2/gas/config/tc-sparc.h --- binutils-2.16.91.0.1/gas/config/tc-sparc.h 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-sparc.h 2005-07-20 12:27:27.863099066 -0700 @@ -22,9 +22,7 @@ #ifndef TC_SPARC #define TC_SPARC 1 -#ifdef ANSI_PROTOTYPES struct frag; -#endif /* This is used to set the default value for `target_big_endian'. */ #define TARGET_BYTES_BIG_ENDIAN 1 diff -uprN binutils-2.16.91.0.1/gas/config/tc-tic30.c binutils-2.16.91.0.2/gas/config/tc-tic30.c --- binutils-2.16.91.0.1/gas/config/tc-tic30.c 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-tic30.c 2005-07-20 12:27:27.866098571 -0700 @@ -28,11 +28,7 @@ #include "as.h" #include "safe-ctype.h" #include "opcode/tic30.h" -#ifdef ANSI_PROTOTYPES #include -#else -#include -#endif /* Put here all non-digit non-letter characters that may occur in an operand. */ @@ -86,7 +82,7 @@ const pseudo_typeS md_pseudo_table[] = {0, 0, 0} }; -static int +static int ATTRIBUTE_PRINTF_1 debug (const char *string, ...) { if (flag_debug) @@ -439,9 +435,9 @@ tic30_operand (char *token) debug ("Expression type: %d\n", current_op->direct.direct_expr.X_op); - debug ("Expression addnum: %d\n", - current_op->direct.direct_expr.X_add_number); - debug ("Segment: %d\n", retval); + debug ("Expression addnum: %ld\n", + (long) current_op->direct.direct_expr.X_add_number); + debug ("Segment: %p\n", retval); input_line_pointer = save_input_line_pointer; @@ -609,9 +605,9 @@ tic30_operand (char *token) retval = expression (¤t_op->immediate.imm_expr); debug ("Expression type: %d\n", current_op->immediate.imm_expr.X_op); - debug ("Expression addnum: %d\n", - current_op->immediate.imm_expr.X_add_number); - debug ("Segment: %d\n", retval); + debug ("Expression addnum: %ld\n", + (long) current_op->immediate.imm_expr.X_add_number); + debug ("Segment: %p\n", retval); input_line_pointer = save_input_line_pointer; if (current_op->immediate.imm_expr.X_op == O_constant) @@ -1140,7 +1136,7 @@ md_apply_fix (fixS *fixP, debug ("Values in fixP\n"); debug ("fx_size = %d\n", fixP->fx_size); debug ("fx_pcrel = %d\n", fixP->fx_pcrel); - debug ("fx_where = %d\n", fixP->fx_where); + debug ("fx_where = %ld\n", fixP->fx_where); debug ("fx_offset = %d\n", (int) fixP->fx_offset); { char *buf = fixP->fx_frag->fr_literal + fixP->fx_where; @@ -1182,11 +1178,11 @@ md_undefined_symbol (char *name ATTRIBUT valueT md_section_align (segT segment, valueT size) { - debug ("In md_section_align() segment = %d and size = %d\n", - segment, size); + debug ("In md_section_align() segment = %p and size = %lu\n", + segment, (unsigned long) size); size = (size + 3) / 4; size *= 4; - debug ("New size value = %d\n", size); + debug ("New size value = %lu\n", (unsigned long) size); return size; } @@ -1196,7 +1192,7 @@ md_pcrel_from (fixS *fixP) int offset; debug ("In md_pcrel_from()\n"); - debug ("fx_where = %d\n", fixP->fx_where); + debug ("fx_where = %ld\n", fixP->fx_where); debug ("fx_size = %d\n", fixP->fx_size); /* Find the opcode that represents the current instruction in the fr_literal storage area, and check bit 21. Bit 21 contains whether the diff -uprN binutils-2.16.91.0.1/gas/config/tc-w65.h binutils-2.16.91.0.2/gas/config/tc-w65.h --- binutils-2.16.91.0.1/gas/config/tc-w65.h 2005-05-10 15:46:45.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-w65.h 2005-07-20 12:27:27.871097747 -0700 @@ -23,10 +23,8 @@ #define TARGET_BYTES_BIG_ENDIAN 0 -#if ANSI_PROTOTYPES struct internal_reloc; struct fix; -#endif #define WORKING_DOT_WORD diff -uprN binutils-2.16.91.0.1/gas/config/tc-xtensa.h binutils-2.16.91.0.2/gas/config/tc-xtensa.h --- binutils-2.16.91.0.1/gas/config/tc-xtensa.h 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config/tc-xtensa.h 2005-07-20 12:27:27.874097252 -0700 @@ -21,9 +21,7 @@ #ifndef TC_XTENSA #define TC_XTENSA 1 -#ifdef ANSI_PROTOTYPES struct fix; -#endif #ifndef BFD_ASSEMBLER #error Xtensa support requires BFD_ASSEMBLER diff -uprN binutils-2.16.91.0.1/gas/config.in binutils-2.16.91.0.2/gas/config.in --- binutils-2.16.91.0.1/gas/config.in 2005-04-09 12:03:03.000000000 -0700 +++ binutils-2.16.91.0.2/gas/config.in 2005-07-20 12:27:27.714123632 -0700 @@ -48,6 +48,9 @@ /* Define to 1 if you have the `dcgettext' function. */ #undef HAVE_DCGETTEXT +/* Is the prototype for getopt in in the expected format? */ +#undef HAVE_DECL_GETOPT + /* Define to 1 if you have the header file. */ #undef HAVE_ERRNO_H @@ -318,6 +321,3 @@ /* Define to `unsigned' if does not define. */ #undef size_t - -/* Is the prototype for getopt in in the expected format? */ -#undef HAVE_DECL_GETOPT diff -uprN binutils-2.16.91.0.1/gas/configure binutils-2.16.91.0.2/gas/configure --- binutils-2.16.91.0.1/gas/configure 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/gas/configure 2005-07-20 12:27:27.736120005 -0700 @@ -4661,6 +4661,9 @@ _ACEOF using_cgen=yes ;; + m32c) + using_cgen=yes + ;; frv) using_cgen=yes ;; diff -uprN binutils-2.16.91.0.1/gas/configure.in binutils-2.16.91.0.2/gas/configure.in --- binutils-2.16.91.0.1/gas/configure.in 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/gas/configure.in 2005-07-20 12:27:27.738119675 -0700 @@ -290,6 +290,9 @@ changequote([,])dnl using_cgen=yes ;; + m32c) + using_cgen=yes + ;; frv) using_cgen=yes ;; diff -uprN binutils-2.16.91.0.1/gas/configure.tgt binutils-2.16.91.0.2/gas/configure.tgt --- binutils-2.16.91.0.1/gas/configure.tgt 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/gas/configure.tgt 2005-07-20 12:27:27.739119510 -0700 @@ -30,8 +30,8 @@ eval `echo $targ | sed 's/^\([^-]*\)-\([ # endian and arch. # Note: This table is alpha-sorted, please try to keep it that way. case ${cpu} in - am33_2.0) cpu_type=mn10300 endian=little ;; alpha*) cpu_type=alpha ;; + am33_2.0) cpu_type=mn10300 endian=little ;; arm*be|arm*b) cpu_type=arm endian=big ;; arm*) cpu_type=arm endian=little ;; c4x*) cpu_type=tic4x ;; @@ -42,18 +42,19 @@ case ${cpu} in ia64) cpu_type=ia64 ;; ip2k) cpu_type=ip2k endian=big ;; iq2000) cpu_type=iq2000 endian=big ;; + m32c) cpu_type=m32c endian=big ;; m32r) cpu_type=m32r endian=big ;; m32rle) cpu_type=m32r endian=little ;; - m6811|m6812|m68hc12) cpu_type=m68hc11 ;; - m680[012346]0) cpu_type=m68k ;; + m5200) cpu_type=m68k ;; m68008) cpu_type=m68k ;; + m680[012346]0) cpu_type=m68k ;; + m6811|m6812|m68hc12) cpu_type=m68hc11 ;; m683??) cpu_type=m68k ;; - m5200) cpu_type=m68k ;; m8*) cpu_type=m88k ;; - ms1) cpu_type=ms1 endian=big ;; maxq) cpu_type=maxq ;; mips*el) cpu_type=mips endian=little ;; mips*) cpu_type=mips endian=big ;; + ms1) cpu_type=ms1 endian=big ;; or32*) cpu_type=or32 endian=big ;; pjl*) cpu_type=pj endian=little ;; pj*) cpu_type=pj endian=big ;; @@ -62,16 +63,16 @@ case ${cpu} in rs6000*) cpu_type=ppc ;; s390x*) cpu_type=s390 arch=s390x ;; s390*) cpu_type=s390 arch=s390 ;; - sh5*) cpu_type=sh64 endian=big ;; sh5le*) cpu_type=sh64 endian=little ;; - sh64*) cpu_type=sh64 endian=big ;; + sh5*) cpu_type=sh64 endian=big ;; sh64le*) cpu_type=sh64 endian=little ;; + sh64*) cpu_type=sh64 endian=big ;; sh*le) cpu_type=sh endian=little ;; sh*) cpu_type=sh endian=big ;; - sparclite*) cpu_type=sparc arch=sparclite ;; - sparclet*) cpu_type=sparc arch=sparclet ;; sparc64*) cpu_type=sparc arch=v9-64 ;; sparc86x*) cpu_type=sparc arch=sparc86x ;; + sparclet*) cpu_type=sparc arch=sparclet ;; + sparclite*) cpu_type=sparc arch=sparclite ;; sparc*) cpu_type=sparc arch=sparclite ;; # ??? See tc-sparc.c. strongarm*be) cpu_type=arm endian=big ;; strongarm*b) cpu_type=arm endian=big ;; @@ -93,7 +94,6 @@ case ${generic_target} in a29k-amd-udi) fmt=coff ;; a29k-amd-ebmon) fmt=coff ;; a29k-nyu-sym1) fmt=coff ;; - a29k-*-rtems*) fmt=coff ;; a29k-*-vxworks*) fmt=coff ;; alpha-*-*vms*) fmt=evax ;; @@ -151,7 +151,6 @@ case ${generic_target} in hppa-*-netbsd*) fmt=elf em=nbsd ;; hppa-*-openbsd*) fmt=elf em=hppa ;; hppa-*-osf*) fmt=som em=hppa ;; - hppa-*-rtems*) fmt=elf em=hppa ;; hppa-*-hpux11*) case ${cpu} in hppa*64*) fmt=elf em=hppa64 ;; @@ -210,10 +209,8 @@ case ${generic_target} in i386-*-sco3.2*) fmt=coff ;; i386-*-vsta) fmt=aout ;; i386-*-msdosdjgpp* \ - | i386-*-go32* \ - | i386-go32-rtems*) fmt=coff em=go32 ;; + | i386-*-go32*) fmt=coff em=go32 ;; i386-*-rtemself*) fmt=elf ;; - i386-*-rtemscoff*) fmt=coff ;; i386-*-rtems*) fmt=elf ;; i386-*-gnu*) fmt=elf ;; i386-*-mach*) fmt=aout em=mach ;; @@ -248,6 +245,8 @@ case ${generic_target} in iq2000-*-elf) fmt=elf ;; + m32c-*-elf) fmt=elf ;; + m32r-*-elf*) fmt=elf ;; m32r-*-linux*) fmt=elf em=linux;; @@ -310,6 +309,8 @@ case ${generic_target} in mn10300-*-linux*) fmt=elf em=linux ;; mn10300-*-*) fmt=elf ;; + ms1-*-elf) fmt=elf bfd_gas=yes ;; + msp430-*-*) fmt=elf ;; ns32k-pc532-mach*) fmt=aout em=pc532mach ;; @@ -363,7 +364,6 @@ case ${generic_target} in shle*-*-kaos*) fmt=elf ;; sh64-*-elf*) fmt=elf ;; - sparc-*-rtemsaout*) fmt=aout ;; sparc-*-rtemself*) fmt=elf ;; sparc-*-rtems*) fmt=elf ;; sparc-*-sunos4*) fmt=aout em=sun3 ;; diff -uprN binutils-2.16.91.0.1/gas/doc/all.texi binutils-2.16.91.0.2/gas/doc/all.texi --- binutils-2.16.91.0.1/gas/doc/all.texi 2005-04-09 12:03:10.000000000 -0700 +++ binutils-2.16.91.0.2/gas/doc/all.texi 2005-07-20 12:27:27.883095769 -0700 @@ -43,6 +43,7 @@ @set I960 @set IA64 @set IP2K +@set M32C @set M32R @set M68HC11 @set M680X0 diff -uprN binutils-2.16.91.0.1/gas/doc/as.texinfo binutils-2.16.91.0.2/gas/doc/as.texinfo --- binutils-2.16.91.0.1/gas/doc/as.texinfo 2005-05-10 15:46:46.000000000 -0700 +++ binutils-2.16.91.0.2/gas/doc/as.texinfo 2005-07-20 12:27:27.894093955 -0700 @@ -326,6 +326,11 @@ gcc(1), ld(1), and the Info entries for @emph{Target IP2K options:} [@b{-mip2022}|@b{-mip2022ext}] @end ifset +@ifset M32C + +@emph{Target M32C options:} + [@b{-m32c}|@b{-m16c}] +@end ifset @ifset M32R @emph{Target M32R options:} @@ -712,6 +717,21 @@ just the basic IP2022 ones. @end table @end ifset +@ifset M32C +The following options are available when @value{AS} is configured for the +Renesas M32C and M16C processors. + +@table @gcctabopt + +@item -m32c +Assemble M32C instructions. + +@item -m16c +Assemble M16C instructions (the default). + +@end table +@end ifset + @ifset M32R The following options are available when @value{AS} is configured for the Renesas M32R (formerly Mitsubishi M32R) series. @@ -2109,6 +2129,9 @@ is considered a comment and is ignored. @ifset IP2K @samp{#} on the ip2k; @end ifset +@ifset M32C +@samp{#} on the m32c; +@end ifset @ifset M32R @samp{#} on the m32r; @end ifset @@ -6113,6 +6136,9 @@ subject, see the hardware manufacturer's @ifset IP2K * IP2K-Dependent:: IP2K Dependent Features @end ifset +@ifset M32C +* M32C-Dependent:: M32C Dependent Features +@end ifset @ifset M32R * M32R-Dependent:: M32R Dependent Features @end ifset @@ -6261,6 +6287,10 @@ family. @include c-ip2k.texi @end ifset +@ifset M32C +@include c-m32c.texi +@end ifset + @ifset M32R @include c-m32r.texi @end ifset diff -uprN binutils-2.16.91.0.1/gas/doc/c-i386.texi binutils-2.16.91.0.2/gas/doc/c-i386.texi --- binutils-2.16.91.0.1/gas/doc/c-i386.texi 2005-04-09 12:03:10.000000000 -0700 +++ binutils-2.16.91.0.2/gas/doc/c-i386.texi 2005-07-20 12:27:27.901092801 -0700 @@ -701,7 +701,7 @@ supported on the CPU specified. The cho @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium} @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4} @item @samp{k6} @tab @samp{athlon} @samp{sledgehammer} -@item @samp{.mmx} @samp{.sse} @samp{.sse2} @samp{.3dnow} +@item @samp{.mmx} @samp{.sse} @samp{.sse2} @samp{.sse3} @samp{.3dnow} @end multitable Apart from the warning, there are only two other effects on diff -uprN binutils-2.16.91.0.1/gas/doc/c-m32c.texi binutils-2.16.91.0.2/gas/doc/c-m32c.texi --- binutils-2.16.91.0.1/gas/doc/c-m32c.texi 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/doc/c-m32c.texi 2005-07-20 12:27:27.902092636 -0700 @@ -0,0 +1,48 @@ +@c Copyright 2005 +@c Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC +@page +@node M32C-Dependent +@chapter M32C Dependent Features +@end ifset +@ifclear GENERIC +@node Machine Dependencies +@chapter M32C Dependent Features +@end ifclear + +@cindex M32C support + +@code{@value{AS}} can assemble code for several different members of +the Renesas M32C family. Normally the default is to assemble code for +the M16C microprocessor. The @code{-m32c} option may be used to +change the default to the M32C microprocessor. + +@menu +* M32C-Opts:: M32C Options +@end menu + +@node M32C-Opts +@section M32C Options + +@cindex options, M32C +@cindex M32C options + +The Renesas M32C version of @code{@value{AS}} has two +machine-dependent options: + +@table @code +@item -m32c +@cindex @samp{-m32c} option, M32C +@cindex architecture options, M32C +@cindex M32C architecture option +Assemble M32C instructions. + +@item -m16c +@cindex @samp{-m16c} option, M16C +@cindex architecture options, M16C +@cindex M16C architecture option +Assemble M16C instructions (default). + +@end table diff -uprN binutils-2.16.91.0.1/gas/doc/Makefile.am binutils-2.16.91.0.2/gas/doc/Makefile.am --- binutils-2.16.91.0.1/gas/doc/Makefile.am 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/doc/Makefile.am 2005-07-20 12:27:27.875097088 -0700 @@ -38,6 +38,7 @@ CPU_DOCS = \ c-i860.texi \ c-i960.texi \ c-ip2k.texi \ + c-m32c.texi \ c-m32r.texi \ c-m68hc11.texi \ c-m68k.texi \ diff -uprN binutils-2.16.91.0.1/gas/doc/Makefile.in binutils-2.16.91.0.2/gas/doc/Makefile.in --- binutils-2.16.91.0.1/gas/doc/Makefile.in 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/doc/Makefile.in 2005-07-20 12:27:27.876096923 -0700 @@ -229,6 +229,7 @@ CPU_DOCS = \ c-i860.texi \ c-i960.texi \ c-ip2k.texi \ + c-m32c.texi \ c-m32r.texi \ c-m68hc11.texi \ c-m68k.texi \ diff -uprN binutils-2.16.91.0.1/gas/frags.h binutils-2.16.91.0.2/gas/frags.h --- binutils-2.16.91.0.1/gas/frags.h 2005-05-10 15:46:44.000000000 -0700 +++ binutils-2.16.91.0.2/gas/frags.h 2005-07-20 12:27:27.743118851 -0700 @@ -22,9 +22,7 @@ #ifndef FRAGS_H #define FRAGS_H -#ifdef ANSI_PROTOTYPES struct obstack; -#endif /* A code fragment (frag) is some known number of chars, followed by some unknown number of chars. Typically the unknown number of chars is an diff -uprN binutils-2.16.91.0.1/gas/Makefile.am binutils-2.16.91.0.2/gas/Makefile.am --- binutils-2.16.91.0.1/gas/Makefile.am 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/gas/Makefile.am 2005-07-20 12:27:27.707124786 -0700 @@ -62,6 +62,7 @@ CPU_TYPES = \ i860 \ i960 \ ip2k \ + m32c \ m32r \ m68hc11 \ m68k \ @@ -259,6 +260,7 @@ TARGET_CPU_CFILES = \ config/tc-i860.c \ config/tc-i960.c \ config/tc-ip2k.c \ + config/tc-m32c.c \ config/tc-m32r.c \ config/tc-m68hc11.c \ config/tc-m68k.c \ @@ -312,6 +314,7 @@ TARGET_CPU_HFILES = \ config/tc-i860.h \ config/tc-i960.h \ config/tc-ip2k.h \ + config/tc-m32c.h \ config/tc-m32r.h \ config/tc-m68hc11.h \ config/tc-m68k.h \ @@ -527,13 +530,8 @@ $(OBJS): $(INCDIR)/bin-bugs.h $(INCDIR)/ as.h asintl.h bignum.h bit_fix.h config.h emul.h expr.h flonum.h \ frags.h hash.h listing.h obj.h read.h symbols.h tc.h write.h -EXPECT = `if [ -f $${rootme}/../expect/expect ] ; then \ - echo $${rootme}/../expect/expect ; \ - else echo expect ; fi` - -RUNTEST = `if [ -f $${srcdir}/../dejagnu/runtest ] ; then \ - echo $${srcdir}/../dejagnu/runtest ; else echo runtest; \ - fi` +EXPECT = expect +RUNTEST = runtest RUNTESTFLAGS= check-DEJAGNU: site.exp @@ -547,10 +545,6 @@ check-DEJAGNU: site.exp rootme=`pwd`; export rootme; \ srcdir=`cd ${srcdir}; pwd` ; export srcdir ; \ EXPECT=${EXPECT} ; export EXPECT ; \ - if [ -f $(top_builddir)/../expect/expect ]; then \ - TCL_LIBRARY=`cd $(top_srcdir)/../tcl/library && pwd`; \ - export TCL_LIBRARY; \ - fi; \ runtest=$(RUNTEST); \ cd testsuite; \ if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \ @@ -1219,6 +1213,22 @@ DEPTC_ip2k_elf = $(INCDIR)/symcat.h $(sr $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/ip2k-opc.h \ cgen.h $(INCDIR)/elf/ip2k.h $(INCDIR)/elf/reloc-macros.h \ $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h +DEPTC_m32c_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \ + $(srcdir)/config/tc-m32c.h $(INCDIR)/coff/internal.h \ + $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \ + $(srcdir)/../opcodes/m32c-desc.h $(INCDIR)/opcode/cgen.h \ + $(srcdir)/../opcodes/m32c-opc.h $(srcdir)/../opcodes/cgen-types.h \ + $(srcdir)/../opcodes/cgen-ops.h cgen.h $(INCDIR)/elf/common.h \ + $(INCDIR)/elf/m32c.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h \ + $(INCDIR)/hashtab.h $(INCDIR)/safe-ctype.h +DEPTC_m32c_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \ + subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/m32c-desc.h \ + $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/m32c-opc.h \ + $(srcdir)/../opcodes/cgen-types.h $(srcdir)/../opcodes/cgen-ops.h \ + cgen.h $(INCDIR)/elf/m32c.h $(INCDIR)/elf/reloc-macros.h \ + $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h $(INCDIR)/safe-ctype.h DEPTC_m32r_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \ $(srcdir)/config/tc-m32r.h $(INCDIR)/coff/internal.h \ $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \ @@ -1785,6 +1795,15 @@ DEPOBJ_ip2k_elf = $(INCDIR)/symcat.h $(s $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h \ $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \ struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h +DEPOBJ_m32c_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \ + $(srcdir)/config/tc-m32c.h $(INCDIR)/coff/internal.h \ + $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \ + subsegs.h +DEPOBJ_m32c_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \ + $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \ + struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h DEPOBJ_m32r_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \ $(srcdir)/config/tc-m32r.h $(INCDIR)/coff/internal.h \ $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \ @@ -2231,6 +2250,12 @@ DEP_ip2k_coff = $(srcdir)/config/obj-cof DEP_ip2k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \ $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h +DEP_m32c_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m32c.h \ + $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \ + $(INCDIR)/bfdlink.h +DEP_m32c_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h DEP_m32r_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m32r.h \ $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \ $(INCDIR)/bfdlink.h diff -uprN binutils-2.16.91.0.1/gas/Makefile.in binutils-2.16.91.0.2/gas/Makefile.in --- binutils-2.16.91.0.1/gas/Makefile.in 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/gas/Makefile.in 2005-07-20 12:27:27.712123962 -0700 @@ -291,6 +291,7 @@ CPU_TYPES = \ i860 \ i960 \ ip2k \ + m32c \ m32r \ m68hc11 \ m68k \ @@ -486,6 +487,7 @@ TARGET_CPU_CFILES = \ config/tc-i860.c \ config/tc-i960.c \ config/tc-ip2k.c \ + config/tc-m32c.c \ config/tc-m32r.c \ config/tc-m68hc11.c \ config/tc-m68k.c \ @@ -539,6 +541,7 @@ TARGET_CPU_HFILES = \ config/tc-i860.h \ config/tc-i960.h \ config/tc-ip2k.h \ + config/tc-m32c.h \ config/tc-m32r.h \ config/tc-m68hc11.h \ config/tc-m68k.h \ @@ -723,14 +726,8 @@ as_new_LDADD = $(TARG_CPU_O) $(OBJ_FORMA as_new_DEPENDENCIES = $(TARG_CPU_O) $(OBJ_FORMAT_O) $(ATOF_TARG_O) \ $(extra_objects) $(GASLIBS) $(INTLDEPS) -EXPECT = `if [ -f $${rootme}/../expect/expect ] ; then \ - echo $${rootme}/../expect/expect ; \ - else echo expect ; fi` - -RUNTEST = `if [ -f $${srcdir}/../dejagnu/runtest ] ; then \ - echo $${srcdir}/../dejagnu/runtest ; else echo runtest; \ - fi` - +EXPECT = expect +RUNTEST = runtest RUNTESTFLAGS = # The m68k operand parser. @@ -1039,6 +1036,24 @@ DEPTC_ip2k_elf = $(INCDIR)/symcat.h $(sr cgen.h $(INCDIR)/elf/ip2k.h $(INCDIR)/elf/reloc-macros.h \ $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h +DEPTC_m32c_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \ + $(srcdir)/config/tc-m32c.h $(INCDIR)/coff/internal.h \ + $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \ + $(srcdir)/../opcodes/m32c-desc.h $(INCDIR)/opcode/cgen.h \ + $(srcdir)/../opcodes/m32c-opc.h $(srcdir)/../opcodes/cgen-types.h \ + $(srcdir)/../opcodes/cgen-ops.h cgen.h $(INCDIR)/elf/common.h \ + $(INCDIR)/elf/m32c.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h \ + $(INCDIR)/hashtab.h $(INCDIR)/safe-ctype.h + +DEPTC_m32c_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \ + subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/m32c-desc.h \ + $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/m32c-opc.h \ + $(srcdir)/../opcodes/cgen-types.h $(srcdir)/../opcodes/cgen-ops.h \ + cgen.h $(INCDIR)/elf/m32c.h $(INCDIR)/elf/reloc-macros.h \ + $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h $(INCDIR)/safe-ctype.h + DEPTC_m32r_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \ $(srcdir)/config/tc-m32r.h $(INCDIR)/coff/internal.h \ $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \ @@ -1723,6 +1738,17 @@ DEPOBJ_ip2k_elf = $(INCDIR)/symcat.h $(s $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \ struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h +DEPOBJ_m32c_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \ + $(srcdir)/config/tc-m32c.h $(INCDIR)/coff/internal.h \ + $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \ + subsegs.h + +DEPOBJ_m32c_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \ + $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \ + struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h + DEPOBJ_m32r_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \ $(srcdir)/config/tc-m32r.h $(INCDIR)/coff/internal.h \ $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \ @@ -2285,6 +2311,14 @@ DEP_ip2k_elf = $(srcdir)/config/obj-elf. $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h +DEP_m32c_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m32c.h \ + $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \ + $(INCDIR)/bfdlink.h + +DEP_m32c_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h + DEP_m32r_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m32r.h \ $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \ $(INCDIR)/bfdlink.h @@ -2964,10 +2998,6 @@ check-DEJAGNU: site.exp rootme=`pwd`; export rootme; \ srcdir=`cd ${srcdir}; pwd` ; export srcdir ; \ EXPECT=${EXPECT} ; export EXPECT ; \ - if [ -f $(top_builddir)/../expect/expect ]; then \ - TCL_LIBRARY=`cd $(top_srcdir)/../tcl/library && pwd`; \ - export TCL_LIBRARY; \ - fi; \ runtest=$(RUNTEST); \ cd testsuite; \ if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \ diff -uprN binutils-2.16.91.0.1/gas/po/gas.pot binutils-2.16.91.0.2/gas/po/gas.pot --- binutils-2.16.91.0.1/gas/po/gas.pot 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/po/gas.pot 2005-07-20 12:27:27.924089009 -0700 @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2005-06-06 14:11-0700\n" +"POT-Creation-Date: 2005-07-14 17:39-0500\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -431,7 +431,7 @@ msgstr "" #. * We have a GROSS internal error. #. * This should never happen. #. -#: atof-generic.c:419 config/tc-m68k.c:3170 +#: atof-generic.c:419 config/tc-m68k.c:3185 msgid "failed sanity check" msgstr "" @@ -641,12 +641,12 @@ msgstr "" msgid "unsupported section attribute '%c'" msgstr "" -#: config/obj-coff.c:1524 config/obj-coff.c:4281 config/tc-ppc.c:4605 +#: config/obj-coff.c:1524 config/obj-coff.c:4281 config/tc-ppc.c:4609 #, c-format msgid "unknown section attribute '%c'" msgstr "" -#: config/obj-coff.c:1554 config/tc-ppc.c:4623 config/tc-tic54x.c:4287 +#: config/obj-coff.c:1554 config/tc-ppc.c:4627 config/tc-tic54x.c:4287 #: read.c:2551 #, c-format msgid "error setting flags for \"%s\": %s" @@ -736,144 +736,144 @@ msgstr "" msgid "bad .common segment %s" msgstr "" -#: config/obj-elf.c:577 +#: config/obj-elf.c:579 #, c-format msgid "setting incorrect section type for %s" msgstr "" -#: config/obj-elf.c:582 +#: config/obj-elf.c:584 #, c-format msgid "ignoring incorrect section type for %s" msgstr "" -#: config/obj-elf.c:619 +#: config/obj-elf.c:621 #, c-format msgid "setting incorrect section attributes for %s" msgstr "" -#: config/obj-elf.c:671 +#: config/obj-elf.c:673 #, c-format msgid "ignoring changed section type for %s" msgstr "" -#: config/obj-elf.c:683 +#: config/obj-elf.c:685 #, c-format msgid "ignoring changed section attributes for %s" msgstr "" -#: config/obj-elf.c:685 +#: config/obj-elf.c:687 #, c-format msgid "ignoring changed section entity size for %s" msgstr "" -#: config/obj-elf.c:738 +#: config/obj-elf.c:740 msgid "unrecognized .section attribute: want a,w,x,M,S,G,T" msgstr "" -#: config/obj-elf.c:775 +#: config/obj-elf.c:777 msgid "unrecognized section attribute" msgstr "" -#: config/obj-elf.c:803 read.c:2534 +#: config/obj-elf.c:805 read.c:2534 msgid "unrecognized section type" msgstr "" -#: config/obj-elf.c:833 +#: config/obj-elf.c:835 msgid "missing name" msgstr "" -#: config/obj-elf.c:944 +#: config/obj-elf.c:946 msgid "invalid merge entity size" msgstr "" -#: config/obj-elf.c:951 +#: config/obj-elf.c:953 msgid "entity size for SHF_MERGE not specified" msgstr "" -#: config/obj-elf.c:971 +#: config/obj-elf.c:973 msgid "group name for SHF_GROUP not specified" msgstr "" -#: config/obj-elf.c:984 +#: config/obj-elf.c:986 msgid "character following name is not '#'" msgstr "" -#: config/obj-elf.c:1099 +#: config/obj-elf.c:1101 msgid ".previous without corresponding .section; ignored" msgstr "" -#: config/obj-elf.c:1125 +#: config/obj-elf.c:1127 msgid ".popsection without corresponding .pushsection; ignored" msgstr "" -#: config/obj-elf.c:1177 +#: config/obj-elf.c:1179 msgid "expected comma after name in .symver" msgstr "" -#: config/obj-elf.c:1201 +#: config/obj-elf.c:1203 #, c-format msgid "missing version name in `%s' for symbol `%s'" msgstr "" -#: config/obj-elf.c:1212 +#: config/obj-elf.c:1214 #, c-format msgid "multiple versions [`%s'|`%s'] for symbol `%s'" msgstr "" -#: config/obj-elf.c:1442 +#: config/obj-elf.c:1444 msgid "expected quoted string" msgstr "" -#: config/obj-elf.c:1462 +#: config/obj-elf.c:1464 #, c-format msgid "expected comma after name `%s' in .size directive" msgstr "" -#: config/obj-elf.c:1471 +#: config/obj-elf.c:1473 msgid "missing expression in .size directive" msgstr "" -#: config/obj-elf.c:1558 +#: config/obj-elf.c:1560 #, c-format msgid "unrecognized symbol type \"%s\"" msgstr "" -#: config/obj-elf.c:1726 +#: config/obj-elf.c:1728 msgid ".size expression too complicated to fix up" msgstr "" -#: config/obj-elf.c:1758 +#: config/obj-elf.c:1760 #, c-format msgid "" "invalid attempt to declare external version name as default in symbol `%s'" msgstr "" -#: config/obj-elf.c:1819 ecoff.c:3598 +#: config/obj-elf.c:1821 ecoff.c:3598 #, c-format msgid "symbol `%s' can not be both weak and common" msgstr "" -#: config/obj-elf.c:1926 +#: config/obj-elf.c:1928 #, c-format msgid "assuming all members of group `%s' are COMDAT" msgstr "" -#: config/obj-elf.c:1948 +#: config/obj-elf.c:1950 #, c-format msgid "can't create group: %s" msgstr "" -#: config/obj-elf.c:2057 +#: config/obj-elf.c:2059 #, c-format msgid "failed to set up debugging information: %s" msgstr "" -#: config/obj-elf.c:2077 +#: config/obj-elf.c:2079 #, c-format msgid "can't start writing .mdebug section: %s" msgstr "" -#: config/obj-elf.c:2085 +#: config/obj-elf.c:2087 #, c-format msgid "could not write .mdebug section: %s" msgstr "" @@ -924,14 +924,14 @@ msgstr "" #: config/tc-d30v.c:490 config/tc-h8300.c:470 config/tc-h8500.c:271 #: config/tc-mcore.c:667 config/tc-mmix.c:489 config/tc-mn10200.c:1078 #: config/tc-mn10300.c:1820 config/tc-msp430.c:407 config/tc-or32.c:324 -#: config/tc-or32.c:376 config/tc-ppc.c:2377 config/tc-s390.c:1218 +#: config/tc-or32.c:376 config/tc-ppc.c:2381 config/tc-s390.c:1218 #: config/tc-sh64.c:2213 config/tc-sh.c:1240 config/tc-tic80.c:261 #: config/tc-v850.c:1952 config/tc-w65.c:206 config/tc-z8k.c:331 msgid "missing operand" msgstr "" #: config/tc-a29k.c:357 config/tc-cris.c:1493 config/tc-cris.c:1501 -#: config/tc-crx.c:2028 config/tc-dlx.c:685 config/tc-hppa.c:1617 +#: config/tc-crx.c:2029 config/tc-dlx.c:685 config/tc-hppa.c:1617 #: config/tc-i860.c:492 config/tc-i860.c:509 config/tc-i860.c:989 #: config/tc-sparc.c:1420 config/tc-sparc.c:1428 #, c-format @@ -954,7 +954,7 @@ msgid "Immediate value of %ld is too lar msgstr "" #: config/tc-a29k.c:474 config/tc-i860.c:395 config/tc-i860.c:940 -#: config/tc-m68k.c:3495 config/tc-m68k.c:3527 config/tc-sparc.c:2660 +#: config/tc-m68k.c:3510 config/tc-m68k.c:3542 config/tc-sparc.c:2660 msgid "failed sanity check." msgstr "" @@ -1141,14 +1141,14 @@ msgid "sequence number in use for !tlsgd msgstr "" #: config/tc-alpha.c:1823 config/tc-arc.c:294 config/tc-mn10200.c:889 -#: config/tc-mn10300.c:2601 config/tc-ppc.c:1471 config/tc-s390.c:612 +#: config/tc-mn10300.c:2601 config/tc-ppc.c:1475 config/tc-s390.c:612 #: config/tc-v850.c:1573 msgid "operand" msgstr "" #: config/tc-alpha.c:1926 config/tc-alpha.c:1950 config/tc-d10v.c:585 #: config/tc-d30v.c:573 config/tc-mn10200.c:1133 config/tc-mn10300.c:1893 -#: config/tc-ppc.c:2343 config/tc-ppc.c:2560 config/tc-ppc.c:2572 +#: config/tc-ppc.c:2347 config/tc-ppc.c:2564 config/tc-ppc.c:2576 #: config/tc-s390.c:1228 config/tc-s390.c:1328 config/tc-s390.c:1424 #: config/tc-v850.c:1747 config/tc-v850.c:1770 config/tc-v850.c:1973 msgid "too many fixups" @@ -1166,7 +1166,7 @@ msgstr "" msgid "can not resolve expression" msgstr "" -#: config/tc-alpha.c:3275 config/tc-ppc.c:1776 config/tc-ppc.c:4368 +#: config/tc-alpha.c:3275 config/tc-ppc.c:1780 config/tc-ppc.c:4372 #, c-format msgid ".COMMon length (%ld.) <0! Ignored." msgstr "" @@ -1175,7 +1175,7 @@ msgstr "" msgid "Ignoring attempt to re-define symbol" msgstr "" -#: config/tc-alpha.c:3313 config/tc-alpha.c:3322 config/tc-ppc.c:4405 +#: config/tc-alpha.c:3313 config/tc-alpha.c:3322 config/tc-ppc.c:4409 #: config/tc-sparc.c:3854 #, c-format msgid "Length of .comm \"%s\" is already %ld. Not changed to %ld." @@ -1370,7 +1370,7 @@ msgstr "" #: config/tc-alpha.c:5067 config/tc-h8300.c:2092 config/tc-h8500.c:1115 #: config/tc-hppa.c:4032 config/tc-i860.c:1059 config/tc-m68hc11.c:558 -#: config/tc-m68k.c:4586 config/tc-m88k.c:916 config/tc-ns32k.c:1955 +#: config/tc-m68k.c:4604 config/tc-m88k.c:916 config/tc-ns32k.c:1955 #: config/tc-or32.c:877 config/tc-sparc.c:2947 config/tc-z8k.c:1328 msgid "Bad call to MD_ATOF()" msgstr "" @@ -1437,7 +1437,7 @@ msgstr "" msgid "frame reg expected, using $%d." msgstr "" -#: config/tc-arc.c:1077 config/tc-arm.c:9363 config/tc-ip2k.c:249 +#: config/tc-arc.c:1077 config/tc-arm.c:9351 config/tc-ip2k.c:249 msgid "md_estimate_size_before_relax\n" msgstr "" @@ -1446,13 +1446,13 @@ msgid "md_convert_frag\n" msgstr "" #. We can't actually support subtracting a symbol. -#: config/tc-arc.c:1288 config/tc-arm.c:1011 config/tc-arm.c:5598 -#: config/tc-arm.c:5649 config/tc-arm.c:6313 config/tc-arm.c:6867 -#: config/tc-arm.c:6893 config/tc-arm.c:7120 config/tc-arm.c:7137 -#: config/tc-arm.c:7243 config/tc-avr.c:891 config/tc-cris.c:3928 +#: config/tc-arc.c:1288 config/tc-arm.c:1011 config/tc-arm.c:5592 +#: config/tc-arm.c:5643 config/tc-arm.c:6307 config/tc-arm.c:6861 +#: config/tc-arm.c:6887 config/tc-arm.c:7114 config/tc-arm.c:7131 +#: config/tc-arm.c:7237 config/tc-avr.c:891 config/tc-cris.c:3928 #: config/tc-d10v.c:1539 config/tc-d30v.c:1938 config/tc-mips.c:3758 #: config/tc-mips.c:4866 config/tc-mips.c:5798 config/tc-mips.c:6392 -#: config/tc-msp430.c:1871 config/tc-ppc.c:5553 config/tc-v850.c:2274 +#: config/tc-msp430.c:1871 config/tc-ppc.c:5557 config/tc-v850.c:2274 #: config/tc-xstormy16.c:484 msgid "expression too complex" msgstr "" @@ -1561,7 +1561,7 @@ msgstr "" msgid "bad segment" msgstr "" -#: config/tc-arm.c:683 config/tc-arm.c:3121 config/tc-i960.c:1310 +#: config/tc-arm.c:683 config/tc-arm.c:3126 config/tc-i960.c:1310 msgid "invalid constant" msgstr "" @@ -1599,7 +1599,7 @@ msgstr "" msgid "invalid register list" msgstr "" -#: config/tc-arm.c:1087 config/tc-arm.c:2387 config/tc-arm.c:2520 +#: config/tc-arm.c:1087 config/tc-arm.c:2392 config/tc-arm.c:2525 msgid "register list not in ascending order" msgstr "" @@ -1644,314 +1644,324 @@ msgstr "" msgid "ignoring attempt to undefine built-in register '%s'" msgstr "" -#: config/tc-arm.c:1448 +#: config/tc-arm.c:1446 msgid "selected processor does not support THUMB opcodes" msgstr "" -#: config/tc-arm.c:1462 +#: config/tc-arm.c:1460 msgid "selected processor does not support ARM opcodes" msgstr "" -#: config/tc-arm.c:1475 +#: config/tc-arm.c:1473 #, c-format msgid "invalid instruction size selected (%d)" msgstr "" -#: config/tc-arm.c:1507 +#: config/tc-arm.c:1505 #, c-format msgid "invalid operand to .code directive (%d) (expecting 16 or 32)" msgstr "" -#: config/tc-arm.c:1563 +#: config/tc-arm.c:1561 #, c-format msgid "expected comma after name \"%s\"" msgstr "" -#: config/tc-arm.c:1613 config/tc-m32r.c:589 +#: config/tc-arm.c:1611 config/tc-m32r.c:589 #, c-format msgid "symbol `%s' already defined" msgstr "" -#: config/tc-arm.c:1647 +#: config/tc-arm.c:1645 #, c-format msgid "unrecognized syntax mode \"%s\"" msgstr "" -#: config/tc-arm.c:1667 +#: config/tc-arm.c:1665 #, c-format msgid "alignment too large: %d assumed" msgstr "" -#: config/tc-arm.c:1670 +#: config/tc-arm.c:1668 msgid "alignment negative. 0 assumed." msgstr "" -#: config/tc-arm.c:1808 +#: config/tc-arm.c:1806 msgid "literal pool overflow" msgstr "" -#: config/tc-arm.c:1964 config/tc-arm.c:3729 +#: config/tc-arm.c:1962 config/tc-arm.c:3734 msgid "unrecognized relocation suffix" msgstr "" -#: config/tc-arm.c:2024 +#: config/tc-arm.c:1975 +msgid "(plt) is only valid on branch targets" +msgstr "" + +#: config/tc-arm.c:1981 config/tc-s390.c:1126 config/tc-s390.c:1707 +#: config/tc-xtensa.c:1626 +#, c-format +msgid "%s relocations do not fit in %d bytes" +msgstr "" + +#: config/tc-arm.c:2029 msgid "expected 0 or 1" msgstr "" -#: config/tc-arm.c:2028 +#: config/tc-arm.c:2033 msgid "missing comma" msgstr "" -#: config/tc-arm.c:2083 +#: config/tc-arm.c:2088 msgid "dupicate .handlerdata directive" msgstr "" -#: config/tc-arm.c:2154 +#: config/tc-arm.c:2159 msgid "personality routine specified for cantunwind frame" msgstr "" -#: config/tc-arm.c:2168 +#: config/tc-arm.c:2173 msgid "duplicate .personalityindex directive" msgstr "" -#: config/tc-arm.c:2175 +#: config/tc-arm.c:2180 msgid "bad personality routine number" msgstr "" -#: config/tc-arm.c:2194 +#: config/tc-arm.c:2199 msgid "duplicate .personality directive" msgstr "" -#: config/tc-arm.c:2217 config/tc-arm.c:2339 +#: config/tc-arm.c:2222 config/tc-arm.c:2344 msgid "expected register list" msgstr "" -#: config/tc-arm.c:2295 +#: config/tc-arm.c:2300 msgid "expected , " msgstr "" -#: config/tc-arm.c:2304 +#: config/tc-arm.c:2309 msgid "number of registers must be in the range [1:4]" msgstr "" -#: config/tc-arm.c:2401 config/tc-arm.c:2534 +#: config/tc-arm.c:2406 config/tc-arm.c:2539 msgid "bad register range" msgstr "" -#: config/tc-arm.c:2587 +#: config/tc-arm.c:2592 msgid "register expected" msgstr "" -#: config/tc-arm.c:2597 +#: config/tc-arm.c:2602 msgid "FPA .unwind_save does not take a register list" msgstr "" -#: config/tc-arm.c:2610 +#: config/tc-arm.c:2615 msgid ".unwind_save does not support this kind of register" msgstr "" -#: config/tc-arm.c:2635 +#: config/tc-arm.c:2640 msgid "SP and PC not permitted in .unwind_movsp directive" msgstr "" -#: config/tc-arm.c:2640 +#: config/tc-arm.c:2645 msgid "unexpected .unwind_movsp directive" msgstr "" -#: config/tc-arm.c:2664 +#: config/tc-arm.c:2669 msgid "stack increment must be multiple of 4" msgstr "" -#: config/tc-arm.c:2693 +#: config/tc-arm.c:2698 msgid "expected , " msgstr "" -#: config/tc-arm.c:2711 +#: config/tc-arm.c:2716 msgid "register must be either sp or set by a previousunwind_movsp directive" msgstr "" -#: config/tc-arm.c:2747 +#: config/tc-arm.c:2752 msgid "expected , " msgstr "" -#: config/tc-arm.c:2759 +#: config/tc-arm.c:2764 msgid "unwind opcode too long" msgstr "" -#: config/tc-arm.c:2764 +#: config/tc-arm.c:2769 msgid "invalid unwind opcode" msgstr "" -#: config/tc-arm.c:2848 +#: config/tc-arm.c:2853 msgid "constant expression required" msgstr "" -#: config/tc-arm.c:2854 config/tc-arm.c:6176 config/tc-arm.c:11041 -#: config/tc-arm.c:11066 config/tc-arm.c:11074 config/tc-z8k.c:1125 +#: config/tc-arm.c:2859 config/tc-arm.c:6170 config/tc-arm.c:10861 +#: config/tc-arm.c:10886 config/tc-arm.c:10894 config/tc-z8k.c:1125 #: config/tc-z8k.c:1137 msgid "immediate value out of range" msgstr "" -#: config/tc-arm.c:2949 +#: config/tc-arm.c:2954 msgid "invalid FPA immediate expression" msgstr "" -#: config/tc-arm.c:2999 config/tc-arm.c:3007 +#: config/tc-arm.c:3004 config/tc-arm.c:3012 msgid "shift expression expected" msgstr "" -#: config/tc-arm.c:3021 +#: config/tc-arm.c:3026 msgid "'LSL' or 'ASR' required" msgstr "" -#: config/tc-arm.c:3029 +#: config/tc-arm.c:3034 msgid "'LSL' required" msgstr "" -#: config/tc-arm.c:3037 +#: config/tc-arm.c:3042 msgid "'ASR' required" msgstr "" -#: config/tc-arm.c:3109 config/tc-arm.c:4190 config/tc-v850.c:1844 +#: config/tc-arm.c:3114 config/tc-arm.c:4189 config/tc-v850.c:1844 #: config/tc-v850.c:1865 msgid "constant expression expected" msgstr "" -#: config/tc-arm.c:3116 +#: config/tc-arm.c:3121 msgid "invalid rotation" msgstr "" -#: config/tc-arm.c:3231 +#: config/tc-arm.c:3236 msgid "']' expected" msgstr "" -#: config/tc-arm.c:3249 +#: config/tc-arm.c:3254 msgid "'}' expected at end of 'option' field" msgstr "" -#: config/tc-arm.c:3254 +#: config/tc-arm.c:3259 msgid "cannot combine index with option" msgstr "" -#: config/tc-arm.c:3267 +#: config/tc-arm.c:3272 msgid "cannot combine pre- and post-indexing" msgstr "" -#: config/tc-arm.c:3363 +#: config/tc-arm.c:3368 msgid "flag for {c}psr instruction expected" msgstr "" -#: config/tc-arm.c:3388 +#: config/tc-arm.c:3393 msgid "unrecognized CPS flag" msgstr "" -#: config/tc-arm.c:3395 +#: config/tc-arm.c:3400 msgid "missing CPS flags" msgstr "" -#: config/tc-arm.c:3418 config/tc-arm.c:3424 +#: config/tc-arm.c:3423 config/tc-arm.c:3429 msgid "valid endian specifiers are be or le" msgstr "" -#: config/tc-arm.c:3446 +#: config/tc-arm.c:3451 msgid "missing rotation field after comma" msgstr "" -#: config/tc-arm.c:3461 +#: config/tc-arm.c:3466 msgid "rotation can only be 0, 8, 16, or 24" msgstr "" -#: config/tc-arm.c:3481 +#: config/tc-arm.c:3486 msgid "condition required" msgstr "" -#: config/tc-arm.c:3770 +#: config/tc-arm.c:3775 msgid "iWMMXt data or control register expected" msgstr "" -#: config/tc-arm.c:3888 +#: config/tc-arm.c:3893 msgid "garbage following instruction" msgstr "" -#: config/tc-arm.c:4022 +#: config/tc-arm.c:4027 msgid "instruction does not accept preindexed addressing" msgstr "" #. unindexed - only for coprocessor -#: config/tc-arm.c:4038 config/tc-arm.c:5691 +#: config/tc-arm.c:4043 config/tc-arm.c:5685 msgid "instruction does not accept unindexed addressing" msgstr "" -#: config/tc-arm.c:4046 +#: config/tc-arm.c:4051 msgid "destination register same as write-back base" msgstr "" -#: config/tc-arm.c:4047 +#: config/tc-arm.c:4052 msgid "source register same as write-back base" msgstr "" -#: config/tc-arm.c:4095 +#: config/tc-arm.c:4098 msgid "instruction does not accept scaled register index" msgstr "" -#: config/tc-arm.c:4136 +#: config/tc-arm.c:4137 msgid "instruction does not support unindexed addressing" msgstr "" -#: config/tc-arm.c:4151 +#: config/tc-arm.c:4152 msgid "pc may not be used with write-back" msgstr "" -#: config/tc-arm.c:4156 +#: config/tc-arm.c:4157 msgid "instruction does not support writeback" msgstr "" -#: config/tc-arm.c:4185 +#: config/tc-arm.c:4184 msgid "invalid pseudo operation" msgstr "" -#: config/tc-arm.c:4231 +#: config/tc-arm.c:4230 msgid "literal pool insertion failed" msgstr "" -#: config/tc-arm.c:4374 config/tc-arm.c:4393 config/tc-arm.c:4406 -#: config/tc-arm.c:6072 config/tc-arm.c:6092 config/tc-arm.c:6106 +#: config/tc-arm.c:4369 config/tc-arm.c:4388 config/tc-arm.c:4401 +#: config/tc-arm.c:6066 config/tc-arm.c:6086 config/tc-arm.c:6100 msgid "bit-field extends past end of register" msgstr "" -#: config/tc-arm.c:4435 +#: config/tc-arm.c:4430 msgid "the only suffix valid here is '(plt)'" msgstr "" -#: config/tc-arm.c:4468 +#: config/tc-arm.c:4462 msgid "use of r15 in blx in ARM mode is not really useful" msgstr "" -#: config/tc-arm.c:4486 +#: config/tc-arm.c:4480 msgid "use of r15 in bx in ARM mode is not really useful" msgstr "" -#: config/tc-arm.c:4498 config/tc-arm.c:6212 +#: config/tc-arm.c:4492 config/tc-arm.c:6206 msgid "use of r15 in bxj is not really useful" msgstr "" -#: config/tc-arm.c:4602 config/tc-arm.c:4611 +#: config/tc-arm.c:4596 config/tc-arm.c:4605 msgid "writeback of base register is UNPREDICTABLE" msgstr "" -#: config/tc-arm.c:4605 +#: config/tc-arm.c:4599 msgid "writeback of base register when in register list is UNPREDICTABLE" msgstr "" -#: config/tc-arm.c:4615 +#: config/tc-arm.c:4609 msgid "if writeback register is in list, it must be the lowest reg in the list" msgstr "" -#: config/tc-arm.c:4630 +#: config/tc-arm.c:4624 msgid "first destination register must be even" msgstr "" -#: config/tc-arm.c:4633 config/tc-arm.c:4690 +#: config/tc-arm.c:4627 config/tc-arm.c:4684 msgid "can only load two consecutive registers" msgstr "" @@ -1959,820 +1969,817 @@ msgstr "" #. have been called in the first place. #. If op 2 were present and equal to PC, this function wouldn't #. have been called in the first place. -#: config/tc-arm.c:4634 config/tc-arm.c:4693 config/tc-arm.c:5140 -#: config/tc-arm.c:6539 +#: config/tc-arm.c:4628 config/tc-arm.c:4687 config/tc-arm.c:5134 +#: config/tc-arm.c:6533 msgid "r14 not allowed here" msgstr "" -#: config/tc-arm.c:4635 +#: config/tc-arm.c:4629 msgid "'[' expected" msgstr "" -#: config/tc-arm.c:4648 +#: config/tc-arm.c:4642 msgid "base register written back, and overlaps second destination register" msgstr "" -#: config/tc-arm.c:4656 +#: config/tc-arm.c:4650 msgid "index register overlaps destination register" msgstr "" -#: config/tc-arm.c:4670 config/tc-arm.c:5113 config/tc-arm.c:6405 -#: config/tc-arm.c:7165 +#: config/tc-arm.c:4664 config/tc-arm.c:5107 config/tc-arm.c:6399 +#: config/tc-arm.c:7159 msgid "instruction does not accept this addressing mode" msgstr "" -#: config/tc-arm.c:4676 config/tc-arm.c:5122 +#: config/tc-arm.c:4670 config/tc-arm.c:5116 msgid "offset must be zero in ARM encoding" msgstr "" -#: config/tc-arm.c:4687 config/tc-arm.c:5134 +#: config/tc-arm.c:4681 config/tc-arm.c:5128 msgid "even register required" msgstr "" -#: config/tc-arm.c:4718 config/tc-arm.c:4749 +#: config/tc-arm.c:4712 config/tc-arm.c:4743 msgid "this instruction requires a post-indexed address" msgstr "" -#: config/tc-arm.c:4776 +#: config/tc-arm.c:4770 msgid "rd and rm should be different in mla" msgstr "" -#: config/tc-arm.c:4808 config/tc-arm.c:6741 +#: config/tc-arm.c:4802 config/tc-arm.c:6735 msgid "'CPSR' or 'SPSR' expected" msgstr "" -#: config/tc-arm.c:4841 +#: config/tc-arm.c:4835 msgid "rd and rm should be different in mul" msgstr "" -#: config/tc-arm.c:4862 +#: config/tc-arm.c:4856 msgid "rdhi, rdlo and rm must all be different" msgstr "" -#: config/tc-arm.c:4924 +#: config/tc-arm.c:4918 msgid "'[' expected after PLD mnemonic" msgstr "" -#: config/tc-arm.c:4926 +#: config/tc-arm.c:4920 msgid "post-indexed expression used in preload instruction" msgstr "" -#: config/tc-arm.c:4928 +#: config/tc-arm.c:4922 msgid "writeback used in preload instruction" msgstr "" -#: config/tc-arm.c:4930 +#: config/tc-arm.c:4924 msgid "unindexed addressing used in preload instruction" msgstr "" -#: config/tc-arm.c:5029 config/tc-arm.c:7076 +#: config/tc-arm.c:5023 config/tc-arm.c:7070 msgid "source1 and dest must be same register" msgstr "" -#: config/tc-arm.c:5079 config/tc-arm.c:6798 +#: config/tc-arm.c:5073 config/tc-arm.c:6792 msgid "rdhi and rdlo must be different" msgstr "" -#: config/tc-arm.c:5137 +#: config/tc-arm.c:5131 msgid "can only store two consecutive registers" msgstr "" -#: config/tc-arm.c:5232 config/tc-arm.c:5249 +#: config/tc-arm.c:5226 config/tc-arm.c:5243 msgid "only two consecutive VFP SP registers allowed here" msgstr "" -#: config/tc-arm.c:5277 config/tc-arm.c:5292 +#: config/tc-arm.c:5271 config/tc-arm.c:5286 msgid "this addressing mode requires base-register writeback" msgstr "" -#: config/tc-arm.c:5370 +#: config/tc-arm.c:5364 msgid "this instruction does not support indexing" msgstr "" -#: config/tc-arm.c:5393 +#: config/tc-arm.c:5387 msgid "only r15 allowed here" msgstr "" -#: config/tc-arm.c:5603 config/tc-arm.c:10418 +#: config/tc-arm.c:5597 config/tc-arm.c:10428 msgid "shift expression is too large" msgstr "" -#: config/tc-arm.c:5629 +#: config/tc-arm.c:5623 msgid "Thumb does not support the ldr =N pseudo-operation" msgstr "" -#: config/tc-arm.c:5634 +#: config/tc-arm.c:5628 msgid "cannot use register index with PC-relative addressing" msgstr "" -#: config/tc-arm.c:5635 +#: config/tc-arm.c:5629 msgid "cannot use register index with this instruction" msgstr "" -#: config/tc-arm.c:5637 +#: config/tc-arm.c:5631 msgid "Thumb does not support negative register indexing" msgstr "" -#: config/tc-arm.c:5639 +#: config/tc-arm.c:5633 msgid "Thumb does not support register post-indexing" msgstr "" -#: config/tc-arm.c:5641 +#: config/tc-arm.c:5635 msgid "Thumb does not support register indexing with writeback" msgstr "" -#: config/tc-arm.c:5643 +#: config/tc-arm.c:5637 msgid "Thumb supports only LSL in shifted register indexing" msgstr "" -#: config/tc-arm.c:5651 +#: config/tc-arm.c:5645 msgid "shift out of range" msgstr "" -#: config/tc-arm.c:5659 +#: config/tc-arm.c:5653 msgid "cannot use writeback with PC-relative addressing" msgstr "" -#: config/tc-arm.c:5661 +#: config/tc-arm.c:5655 msgid "cannot use writeback with this instruction" msgstr "" -#: config/tc-arm.c:5681 +#: config/tc-arm.c:5675 msgid "cannot use post-indexing with PC-relative addressing" msgstr "" -#: config/tc-arm.c:5682 +#: config/tc-arm.c:5676 msgid "cannot use post-indexing with this instruction" msgstr "" -#: config/tc-arm.c:5849 config/tc-arm.c:5958 config/tc-arm.c:6038 -#: config/tc-arm.c:6712 +#: config/tc-arm.c:5843 config/tc-arm.c:5952 config/tc-arm.c:6032 +#: config/tc-arm.c:6706 msgid "shift must be constant" msgstr "" -#: config/tc-arm.c:5876 config/tc-arm.c:5973 config/tc-arm.c:6053 -#: config/tc-arm.c:6725 +#: config/tc-arm.c:5870 config/tc-arm.c:5967 config/tc-arm.c:6047 +#: config/tc-arm.c:6719 msgid "unshifted register required" msgstr "" -#: config/tc-arm.c:5891 config/tc-arm.c:6064 config/tc-arm.c:6785 +#: config/tc-arm.c:5885 config/tc-arm.c:6058 config/tc-arm.c:6779 msgid "dest must overlap one source register" msgstr "" -#: config/tc-arm.c:5976 +#: config/tc-arm.c:5970 msgid "dest and source1 must be the same register" msgstr "" -#: config/tc-arm.c:6241 +#: config/tc-arm.c:6235 msgid "Thumb does not support the 2-argument form of this instruction" msgstr "" -#: config/tc-arm.c:6315 +#: config/tc-arm.c:6309 msgid "Thumb load/store multiple does not support {reglist}^" msgstr "" -#: config/tc-arm.c:6332 config/tc-arm.c:6348 config/tc-arm.c:6379 +#: config/tc-arm.c:6326 config/tc-arm.c:6342 config/tc-arm.c:6373 #, c-format msgid "value stored for r%d is UNPREDICTABLE" msgstr "" -#: config/tc-arm.c:6342 config/tc-arm.c:6909 +#: config/tc-arm.c:6336 config/tc-arm.c:6903 msgid "SP should not be in register list" msgstr "" -#: config/tc-arm.c:6346 config/tc-arm.c:6913 +#: config/tc-arm.c:6340 config/tc-arm.c:6907 msgid "PC should not be in register list" msgstr "" -#: config/tc-arm.c:6355 config/tc-arm.c:6919 +#: config/tc-arm.c:6349 config/tc-arm.c:6913 msgid "LR and PC should not both be in register list" msgstr "" -#: config/tc-arm.c:6358 +#: config/tc-arm.c:6352 msgid "base register should not be in register list when written back" msgstr "" -#: config/tc-arm.c:6376 config/tc-arm.c:6386 +#: config/tc-arm.c:6370 config/tc-arm.c:6380 msgid "this instruction will write back the base register" msgstr "" -#: config/tc-arm.c:6389 +#: config/tc-arm.c:6383 msgid "this instruction will not write back the base register" msgstr "" -#: config/tc-arm.c:6418 +#: config/tc-arm.c:6412 msgid "r14 not allowed as first register when second register is omitted" msgstr "" -#: config/tc-arm.c:6462 config/tc-arm.c:6475 config/tc-arm.c:6511 +#: config/tc-arm.c:6456 config/tc-arm.c:6469 config/tc-arm.c:6505 msgid "Thumb does not support this addressing mode" msgstr "" -#: config/tc-arm.c:6479 +#: config/tc-arm.c:6473 msgid "byte or halfword not valid for base register" msgstr "" -#: config/tc-arm.c:6482 +#: config/tc-arm.c:6476 msgid "r15 based store not allowed" msgstr "" -#: config/tc-arm.c:6484 +#: config/tc-arm.c:6478 msgid "invalid base register for register offset" msgstr "" -#: config/tc-arm.c:6661 +#: config/tc-arm.c:6655 msgid "only lo regs allowed with immediate" msgstr "" -#: config/tc-arm.c:6750 +#: config/tc-arm.c:6744 msgid "Thumb encoding does not support an immediate here" msgstr "" -#: config/tc-arm.c:6820 +#: config/tc-arm.c:6814 msgid "Thumb does not support NOP with hints" msgstr "" -#: config/tc-arm.c:6891 +#: config/tc-arm.c:6885 msgid "push/pop do not support {reglist}^" msgstr "" -#: config/tc-arm.c:6926 +#: config/tc-arm.c:6920 msgid "invalid register list to push/pop instruction" msgstr "" -#: config/tc-arm.c:7097 +#: config/tc-arm.c:7091 msgid "ror #imm not supported" msgstr "" -#: config/tc-arm.c:7222 +#: config/tc-arm.c:7216 msgid "Thumb encoding does not support rotation" msgstr "" -#: config/tc-arm.c:7465 config/tc-arm.c:7532 +#: config/tc-arm.c:7459 config/tc-arm.c:7526 msgid "conditional infixes are deprecated in unified syntax" msgstr "" -#: config/tc-arm.c:7564 +#: config/tc-arm.c:7558 #, c-format msgid "bad instruction `%s'" msgstr "" -#: config/tc-arm.c:7574 config/tc-arm.c:7606 +#: config/tc-arm.c:7568 config/tc-arm.c:7600 #, c-format msgid "selected processor does not support `%s'" msgstr "" -#: config/tc-arm.c:7580 +#: config/tc-arm.c:7574 msgid "Thumb does not support conditional execution" msgstr "" -#: config/tc-arm.c:7596 +#: config/tc-arm.c:7590 #, c-format msgid "cannot honor width suffix -- `%s'" msgstr "" -#: config/tc-arm.c:7611 +#: config/tc-arm.c:7605 #, c-format msgid "width suffixes are invalid in ARM mode -- `%s'" msgstr "" -#: config/tc-arm.c:9454 +#: config/tc-arm.c:9442 msgid "alignments greater than 32 bytes not supported in .text sections." msgstr "" -#: config/tc-arm.c:9748 +#: config/tc-arm.c:9736 msgid "handerdata in cantunwind frame" msgstr "" -#: config/tc-arm.c:9765 +#: config/tc-arm.c:9753 msgid "too many unwind opcodes for personality routine 0" msgstr "" -#: config/tc-arm.c:9797 +#: config/tc-arm.c:9785 msgid "too many unwind opcodes" msgstr "" -#: config/tc-arm.c:10163 config/tc-arm.c:10442 +#: config/tc-arm.c:10174 config/tc-arm.c:10452 #, c-format msgid "undefined symbol %s used as an immediate value" msgstr "" -#: config/tc-arm.c:10177 config/tc-arm.c:10457 +#: config/tc-arm.c:10188 config/tc-arm.c:10467 #, c-format msgid "invalid constant (%lx) after fixup" msgstr "" -#: config/tc-arm.c:10214 +#: config/tc-arm.c:10225 #, c-format msgid "unable to compute ADRL instructions for PC offset of 0x%lx" msgstr "" -#: config/tc-arm.c:10246 config/tc-arm.c:10271 +#: config/tc-arm.c:10257 config/tc-arm.c:10282 msgid "invalid literal constant: pool needs to be closer" msgstr "" -#: config/tc-arm.c:10249 config/tc-arm.c:10287 +#: config/tc-arm.c:10260 config/tc-arm.c:10298 #, c-format msgid "bad immediate value for offset (%ld)" msgstr "" -#: config/tc-arm.c:10273 +#: config/tc-arm.c:10284 #, c-format msgid "bad immediate value for half-word offset (%ld)" msgstr "" -#: config/tc-arm.c:10329 +#: config/tc-arm.c:10339 msgid "offset not a multiple of 4" msgstr "" -#: config/tc-arm.c:10336 config/tc-arm.c:10351 config/tc-arm.c:10366 -#: config/tc-arm.c:10377 config/tc-arm.c:10400 config/tc-pj.c:499 +#: config/tc-arm.c:10346 config/tc-arm.c:10361 config/tc-arm.c:10376 +#: config/tc-arm.c:10387 config/tc-arm.c:10410 config/tc-pj.c:499 #: config/tc-sh.c:4111 msgid "offset out of range" msgstr "" -#: config/tc-arm.c:10474 +#: config/tc-arm.c:10483 msgid "invalid smi expression" msgstr "" -#: config/tc-arm.c:10485 config/tc-arm.c:10494 +#: config/tc-arm.c:10494 config/tc-arm.c:10503 msgid "invalid swi expression" msgstr "" -#: config/tc-arm.c:10504 +#: config/tc-arm.c:10513 msgid "invalid expression in load/store multiple" msgstr "" -#: config/tc-arm.c:10554 -msgid "GAS can't handle same-section branch dest >= 0x04000000" -msgstr "" - -#: config/tc-arm.c:10563 -msgid "out of range branch" +#: config/tc-arm.c:10528 +msgid "misaligned branch destination" msgstr "" -#: config/tc-arm.c:10619 config/tc-arm.c:10645 config/tc-arm.c:10670 -#: config/tc-arm.c:10817 +#: config/tc-arm.c:10532 config/tc-arm.c:10552 config/tc-arm.c:10570 +#: config/tc-arm.c:10583 config/tc-arm.c:10596 config/tc-arm.c:10635 +#: config/tc-arm.c:10660 msgid "branch out of range" msgstr "" -#: config/tc-arm.c:10705 -msgid "conditional branch out of range" +#: config/tc-arm.c:10548 +msgid "misaligned BLX destination" msgstr "" -#: config/tc-arm.c:10751 -msgid "branch with link out of range" +#: config/tc-arm.c:10609 +msgid "conditional branch out of range" msgstr "" -#: config/tc-arm.c:10906 +#: config/tc-arm.c:10730 msgid "rel31 relocation overflow" msgstr "" -#: config/tc-arm.c:10921 config/tc-arm.c:10936 +#: config/tc-arm.c:10741 config/tc-arm.c:10756 msgid "co-processor offset out of range" msgstr "" -#: config/tc-arm.c:10952 +#: config/tc-arm.c:10772 #, c-format msgid "invalid offset, target not word aligned (0x%08lX)" msgstr "" -#: config/tc-arm.c:10958 config/tc-arm.c:10967 config/tc-arm.c:10975 -#: config/tc-arm.c:10983 config/tc-arm.c:10991 +#: config/tc-arm.c:10778 config/tc-arm.c:10787 config/tc-arm.c:10795 +#: config/tc-arm.c:10803 config/tc-arm.c:10811 #, c-format msgid "invalid offset, value too big (0x%08lX)" msgstr "" -#: config/tc-arm.c:11032 +#: config/tc-arm.c:10852 msgid "invalid Hi register with immediate" msgstr "" -#: config/tc-arm.c:11048 +#: config/tc-arm.c:10868 msgid "invalid immediate for stack address calculation" msgstr "" -#: config/tc-arm.c:11056 +#: config/tc-arm.c:10876 #, c-format msgid "invalid immediate for address calculation (value = 0x%08lX)" msgstr "" -#: config/tc-arm.c:11086 +#: config/tc-arm.c:10906 #, c-format msgid "invalid immediate: %ld is too large" msgstr "" -#: config/tc-arm.c:11098 +#: config/tc-arm.c:10918 #, c-format msgid "invalid shift value: %ld" msgstr "" -#: config/tc-arm.c:11117 +#: config/tc-arm.c:10937 #, c-format msgid "bad relocation fixup type (%d)" msgstr "" -#: config/tc-arm.c:11191 +#: config/tc-arm.c:11005 msgid "literal referenced across section boundary" msgstr "" -#: config/tc-arm.c:11221 +#: config/tc-arm.c:11035 msgid "internal relocation (type: IMMEDIATE) not fixed up" msgstr "" -#: config/tc-arm.c:11226 +#: config/tc-arm.c:11040 msgid "ADRL used for a symbol not defined in the same file" msgstr "" -#: config/tc-arm.c:11235 +#: config/tc-arm.c:11049 #, c-format msgid "undefined local label `%s'" msgstr "" -#: config/tc-arm.c:11241 +#: config/tc-arm.c:11055 msgid "internal_relocation (type: OFFSET_IMM) not fixed up" msgstr "" -#: config/tc-arm.c:11261 config/tc-cris.c:3869 config/tc-mcore.c:1997 +#: config/tc-arm.c:11075 config/tc-cris.c:3869 config/tc-mcore.c:1997 #: config/tc-mmix.c:2888 config/tc-ns32k.c:2304 msgid "" msgstr "" -#: config/tc-arm.c:11264 config/tc-arm.c:11285 +#: config/tc-arm.c:11078 config/tc-arm.c:11099 #, c-format msgid "cannot represent %s relocation in this object file format" msgstr "" -#: config/tc-arm.c:11505 +#: config/tc-arm.c:11312 #, c-format msgid "%s: unexpected function type: %d" msgstr "" -#: config/tc-arm.c:11582 +#: config/tc-arm.c:11389 msgid "virtual memory exhausted" msgstr "" -#: config/tc-arm.c:11608 +#: config/tc-arm.c:11415 msgid "use of old and new-style options to set CPU type" msgstr "" -#: config/tc-arm.c:11618 +#: config/tc-arm.c:11425 msgid "use of old and new-style options to set FPU type" msgstr "" -#: config/tc-arm.c:11680 +#: config/tc-arm.c:11487 msgid "hard-float conflicts with specified fpu" msgstr "" -#: config/tc-arm.c:11872 +#: config/tc-arm.c:11679 msgid "generate PIC code" msgstr "" -#: config/tc-arm.c:11873 +#: config/tc-arm.c:11680 msgid "assemble Thumb code" msgstr "" -#: config/tc-arm.c:11874 +#: config/tc-arm.c:11681 msgid "support ARM/Thumb interworking" msgstr "" -#: config/tc-arm.c:11876 +#: config/tc-arm.c:11683 msgid "code uses 32-bit program counter" msgstr "" -#: config/tc-arm.c:11877 +#: config/tc-arm.c:11684 msgid "code uses 26-bit program counter" msgstr "" -#: config/tc-arm.c:11878 +#: config/tc-arm.c:11685 msgid "floating point args are in fp regs" msgstr "" -#: config/tc-arm.c:11880 +#: config/tc-arm.c:11687 msgid "re-entrant code" msgstr "" -#: config/tc-arm.c:11881 +#: config/tc-arm.c:11688 msgid "code is ATPCS conformant" msgstr "" -#: config/tc-arm.c:11882 +#: config/tc-arm.c:11689 msgid "assemble for big-endian" msgstr "" -#: config/tc-arm.c:11883 +#: config/tc-arm.c:11690 msgid "assemble for little-endian" msgstr "" #. These are recognized by the assembler, but have no affect on code. -#: config/tc-arm.c:11887 +#: config/tc-arm.c:11694 msgid "use frame pointer" msgstr "" -#: config/tc-arm.c:11888 +#: config/tc-arm.c:11695 msgid "use stack size checking" msgstr "" #. DON'T add any new processors to this list -- we want the whole list #. to go away... Add them to the processors table instead. -#: config/tc-arm.c:11892 config/tc-arm.c:11893 +#: config/tc-arm.c:11699 config/tc-arm.c:11700 msgid "use -mcpu=arm1" msgstr "" -#: config/tc-arm.c:11894 config/tc-arm.c:11895 +#: config/tc-arm.c:11701 config/tc-arm.c:11702 msgid "use -mcpu=arm2" msgstr "" -#: config/tc-arm.c:11896 config/tc-arm.c:11897 +#: config/tc-arm.c:11703 config/tc-arm.c:11704 msgid "use -mcpu=arm250" msgstr "" -#: config/tc-arm.c:11898 config/tc-arm.c:11899 +#: config/tc-arm.c:11705 config/tc-arm.c:11706 msgid "use -mcpu=arm3" msgstr "" -#: config/tc-arm.c:11900 config/tc-arm.c:11901 +#: config/tc-arm.c:11707 config/tc-arm.c:11708 msgid "use -mcpu=arm6" msgstr "" -#: config/tc-arm.c:11902 config/tc-arm.c:11903 +#: config/tc-arm.c:11709 config/tc-arm.c:11710 msgid "use -mcpu=arm600" msgstr "" -#: config/tc-arm.c:11904 config/tc-arm.c:11905 +#: config/tc-arm.c:11711 config/tc-arm.c:11712 msgid "use -mcpu=arm610" msgstr "" -#: config/tc-arm.c:11906 config/tc-arm.c:11907 +#: config/tc-arm.c:11713 config/tc-arm.c:11714 msgid "use -mcpu=arm620" msgstr "" -#: config/tc-arm.c:11908 config/tc-arm.c:11909 +#: config/tc-arm.c:11715 config/tc-arm.c:11716 msgid "use -mcpu=arm7" msgstr "" -#: config/tc-arm.c:11910 config/tc-arm.c:11911 +#: config/tc-arm.c:11717 config/tc-arm.c:11718 msgid "use -mcpu=arm70" msgstr "" -#: config/tc-arm.c:11912 config/tc-arm.c:11913 +#: config/tc-arm.c:11719 config/tc-arm.c:11720 msgid "use -mcpu=arm700" msgstr "" -#: config/tc-arm.c:11914 config/tc-arm.c:11915 +#: config/tc-arm.c:11721 config/tc-arm.c:11722 msgid "use -mcpu=arm700i" msgstr "" -#: config/tc-arm.c:11916 config/tc-arm.c:11917 +#: config/tc-arm.c:11723 config/tc-arm.c:11724 msgid "use -mcpu=arm710" msgstr "" -#: config/tc-arm.c:11918 config/tc-arm.c:11919 +#: config/tc-arm.c:11725 config/tc-arm.c:11726 msgid "use -mcpu=arm710c" msgstr "" -#: config/tc-arm.c:11920 config/tc-arm.c:11921 +#: config/tc-arm.c:11727 config/tc-arm.c:11728 msgid "use -mcpu=arm720" msgstr "" -#: config/tc-arm.c:11922 config/tc-arm.c:11923 +#: config/tc-arm.c:11729 config/tc-arm.c:11730 msgid "use -mcpu=arm7d" msgstr "" -#: config/tc-arm.c:11924 config/tc-arm.c:11925 +#: config/tc-arm.c:11731 config/tc-arm.c:11732 msgid "use -mcpu=arm7di" msgstr "" -#: config/tc-arm.c:11926 config/tc-arm.c:11927 +#: config/tc-arm.c:11733 config/tc-arm.c:11734 msgid "use -mcpu=arm7m" msgstr "" -#: config/tc-arm.c:11928 config/tc-arm.c:11929 +#: config/tc-arm.c:11735 config/tc-arm.c:11736 msgid "use -mcpu=arm7dm" msgstr "" -#: config/tc-arm.c:11930 config/tc-arm.c:11931 +#: config/tc-arm.c:11737 config/tc-arm.c:11738 msgid "use -mcpu=arm7dmi" msgstr "" -#: config/tc-arm.c:11932 config/tc-arm.c:11933 +#: config/tc-arm.c:11739 config/tc-arm.c:11740 msgid "use -mcpu=arm7100" msgstr "" -#: config/tc-arm.c:11934 config/tc-arm.c:11935 +#: config/tc-arm.c:11741 config/tc-arm.c:11742 msgid "use -mcpu=arm7500" msgstr "" -#: config/tc-arm.c:11936 config/tc-arm.c:11937 +#: config/tc-arm.c:11743 config/tc-arm.c:11744 msgid "use -mcpu=arm7500fe" msgstr "" -#: config/tc-arm.c:11938 config/tc-arm.c:11939 config/tc-arm.c:11940 -#: config/tc-arm.c:11941 +#: config/tc-arm.c:11745 config/tc-arm.c:11746 config/tc-arm.c:11747 +#: config/tc-arm.c:11748 msgid "use -mcpu=arm7tdmi" msgstr "" -#: config/tc-arm.c:11942 config/tc-arm.c:11943 +#: config/tc-arm.c:11749 config/tc-arm.c:11750 msgid "use -mcpu=arm710t" msgstr "" -#: config/tc-arm.c:11944 config/tc-arm.c:11945 +#: config/tc-arm.c:11751 config/tc-arm.c:11752 msgid "use -mcpu=arm720t" msgstr "" -#: config/tc-arm.c:11946 config/tc-arm.c:11947 +#: config/tc-arm.c:11753 config/tc-arm.c:11754 msgid "use -mcpu=arm740t" msgstr "" -#: config/tc-arm.c:11948 config/tc-arm.c:11949 +#: config/tc-arm.c:11755 config/tc-arm.c:11756 msgid "use -mcpu=arm8" msgstr "" -#: config/tc-arm.c:11950 config/tc-arm.c:11951 +#: config/tc-arm.c:11757 config/tc-arm.c:11758 msgid "use -mcpu=arm810" msgstr "" -#: config/tc-arm.c:11952 config/tc-arm.c:11953 +#: config/tc-arm.c:11759 config/tc-arm.c:11760 msgid "use -mcpu=arm9" msgstr "" -#: config/tc-arm.c:11954 config/tc-arm.c:11955 +#: config/tc-arm.c:11761 config/tc-arm.c:11762 msgid "use -mcpu=arm9tdmi" msgstr "" -#: config/tc-arm.c:11956 config/tc-arm.c:11957 +#: config/tc-arm.c:11763 config/tc-arm.c:11764 msgid "use -mcpu=arm920" msgstr "" -#: config/tc-arm.c:11958 config/tc-arm.c:11959 +#: config/tc-arm.c:11765 config/tc-arm.c:11766 msgid "use -mcpu=arm940" msgstr "" -#: config/tc-arm.c:11960 +#: config/tc-arm.c:11767 msgid "use -mcpu=strongarm" msgstr "" -#: config/tc-arm.c:11962 +#: config/tc-arm.c:11769 msgid "use -mcpu=strongarm110" msgstr "" -#: config/tc-arm.c:11964 +#: config/tc-arm.c:11771 msgid "use -mcpu=strongarm1100" msgstr "" -#: config/tc-arm.c:11966 +#: config/tc-arm.c:11773 msgid "use -mcpu=strongarm1110" msgstr "" -#: config/tc-arm.c:11967 +#: config/tc-arm.c:11774 msgid "use -mcpu=xscale" msgstr "" -#: config/tc-arm.c:11968 +#: config/tc-arm.c:11775 msgid "use -mcpu=iwmmxt" msgstr "" -#: config/tc-arm.c:11969 +#: config/tc-arm.c:11776 msgid "use -mcpu=all" msgstr "" #. Architecture variants -- don't add any more to this list either. -#: config/tc-arm.c:11972 config/tc-arm.c:11973 +#: config/tc-arm.c:11779 config/tc-arm.c:11780 msgid "use -march=armv2" msgstr "" -#: config/tc-arm.c:11974 config/tc-arm.c:11975 +#: config/tc-arm.c:11781 config/tc-arm.c:11782 msgid "use -march=armv2a" msgstr "" -#: config/tc-arm.c:11976 config/tc-arm.c:11977 +#: config/tc-arm.c:11783 config/tc-arm.c:11784 msgid "use -march=armv3" msgstr "" -#: config/tc-arm.c:11978 config/tc-arm.c:11979 +#: config/tc-arm.c:11785 config/tc-arm.c:11786 msgid "use -march=armv3m" msgstr "" -#: config/tc-arm.c:11980 config/tc-arm.c:11981 +#: config/tc-arm.c:11787 config/tc-arm.c:11788 msgid "use -march=armv4" msgstr "" -#: config/tc-arm.c:11982 config/tc-arm.c:11983 +#: config/tc-arm.c:11789 config/tc-arm.c:11790 msgid "use -march=armv4t" msgstr "" -#: config/tc-arm.c:11984 config/tc-arm.c:11985 +#: config/tc-arm.c:11791 config/tc-arm.c:11792 msgid "use -march=armv5" msgstr "" -#: config/tc-arm.c:11986 config/tc-arm.c:11987 +#: config/tc-arm.c:11793 config/tc-arm.c:11794 msgid "use -march=armv5t" msgstr "" -#: config/tc-arm.c:11988 config/tc-arm.c:11989 +#: config/tc-arm.c:11795 config/tc-arm.c:11796 msgid "use -march=armv5te" msgstr "" #. Floating point variants -- don't add any more to this list either. -#: config/tc-arm.c:11992 +#: config/tc-arm.c:11799 msgid "use -mfpu=fpe" msgstr "" -#: config/tc-arm.c:11993 +#: config/tc-arm.c:11800 msgid "use -mfpu=fpa10" msgstr "" -#: config/tc-arm.c:11994 +#: config/tc-arm.c:11801 msgid "use -mfpu=fpa11" msgstr "" -#: config/tc-arm.c:11996 +#: config/tc-arm.c:11803 msgid "use either -mfpu=softfpa or -mfpu=softvfp" msgstr "" -#: config/tc-arm.c:12215 +#: config/tc-arm.c:12022 msgid "invalid architectural extension" msgstr "" -#: config/tc-arm.c:12229 +#: config/tc-arm.c:12036 msgid "missing architectural extension" msgstr "" -#: config/tc-arm.c:12242 +#: config/tc-arm.c:12049 #, c-format msgid "unknown architectural extnsion `%s'" msgstr "" -#: config/tc-arm.c:12266 +#: config/tc-arm.c:12073 #, c-format msgid "missing cpu name `%s'" msgstr "" -#: config/tc-arm.c:12282 +#: config/tc-arm.c:12089 #, c-format msgid "unknown cpu `%s'" msgstr "" -#: config/tc-arm.c:12300 +#: config/tc-arm.c:12107 #, c-format msgid "missing architecture name `%s'" msgstr "" -#: config/tc-arm.c:12317 +#: config/tc-arm.c:12124 #, c-format msgid "unknown architecture `%s'\n" msgstr "" -#: config/tc-arm.c:12333 +#: config/tc-arm.c:12140 #, c-format msgid "unknown floating point format `%s'\n" msgstr "" -#: config/tc-arm.c:12349 +#: config/tc-arm.c:12156 #, c-format msgid "unknown floating point abi `%s'\n" msgstr "" -#: config/tc-arm.c:12365 +#: config/tc-arm.c:12172 #, c-format msgid "unknown EABI `%s'\n" msgstr "" -#: config/tc-arm.c:12372 +#: config/tc-arm.c:12179 msgid "\t assemble for CPU " msgstr "" -#: config/tc-arm.c:12374 +#: config/tc-arm.c:12181 msgid "\t assemble for architecture " msgstr "" -#: config/tc-arm.c:12376 +#: config/tc-arm.c:12183 msgid "\t assemble for FPU architecture " msgstr "" -#: config/tc-arm.c:12378 +#: config/tc-arm.c:12185 msgid "\t assemble for floating point ABI " msgstr "" -#: config/tc-arm.c:12381 +#: config/tc-arm.c:12188 msgid "\t assemble for eabi version " msgstr "" -#: config/tc-arm.c:12422 config/tc-arm.c:12444 +#: config/tc-arm.c:12229 config/tc-arm.c:12251 #, c-format msgid "option `-%c%s' is deprecated: %s" msgstr "" -#: config/tc-arm.c:12465 +#: config/tc-arm.c:12272 #, c-format msgid " ARM-specific assembler options:\n" msgstr "" -#: config/tc-arm.c:12476 +#: config/tc-arm.c:12283 #, c-format msgid " -EB assemble code for a big-endian cpu\n" msgstr "" -#: config/tc-arm.c:12481 +#: config/tc-arm.c:12288 #, c-format msgid " -EL assemble code for a little-endian cpu\n" msgstr "" @@ -2820,10 +2827,10 @@ msgstr "" msgid "redefinition of mcu type `%s' to `%s'" msgstr "" -#: config/tc-avr.c:402 config/tc-crx.c:490 config/tc-d10v.c:278 +#: config/tc-avr.c:402 config/tc-crx.c:491 config/tc-d10v.c:278 #: config/tc-d30v.c:312 config/tc-mips.c:9925 config/tc-mmix.c:2264 #: config/tc-mn10200.c:342 config/tc-msp430.c:805 config/tc-pj.c:342 -#: config/tc-ppc.c:5202 config/tc-sh.c:2972 config/tc-v850.c:1199 +#: config/tc-ppc.c:5206 config/tc-sh.c:2972 config/tc-v850.c:1199 msgid "bad call to md_atof" msgstr "" @@ -2928,7 +2935,7 @@ msgstr "" #: config/tc-avr.c:1115 config/tc-d10v.c:1494 config/tc-d30v.c:1804 #: config/tc-mn10200.c:814 config/tc-mn10300.c:2308 config/tc-msp430.c:1986 -#: config/tc-or32.c:1505 config/tc-ppc.c:6048 config/tc-v850.c:2190 +#: config/tc-or32.c:1505 config/tc-ppc.c:6052 config/tc-v850.c:2190 #, c-format msgid "reloc %d not supported by object file format" msgstr "" @@ -3015,17 +3022,17 @@ msgid "" "common_v10_v32" msgstr "" -#: config/tc-cris.c:1148 config/tc-crx.c:581 config/tc-crx.c:608 -#: config/tc-crx.c:626 +#: config/tc-cris.c:1148 config/tc-crx.c:582 config/tc-crx.c:609 +#: config/tc-crx.c:627 msgid "Virtual memory exhausted" msgstr "" -#: config/tc-cris.c:1182 config/tc-crx.c:591 +#: config/tc-cris.c:1182 config/tc-crx.c:592 #, c-format msgid "Can't hash `%s': %s\n" msgstr "" -#: config/tc-cris.c:1183 config/tc-crx.c:592 +#: config/tc-cris.c:1183 config/tc-crx.c:593 msgid "(unknown reason)" msgstr "" @@ -3273,180 +3280,180 @@ msgstr "" msgid ".arch requires a matching --march=... option" msgstr "" -#: config/tc-crx.c:343 config/tc-mn10200.c:801 write.c:2654 +#: config/tc-crx.c:344 config/tc-mn10200.c:801 write.c:2654 #, c-format msgid "can't resolve `%s' {%s section} - `%s' {%s section}" msgstr "" -#: config/tc-crx.c:359 +#: config/tc-crx.c:360 #, c-format msgid "internal error: reloc %d (`%s') not supported by object file format" msgstr "" -#: config/tc-crx.c:618 config/tc-crx.c:636 config/tc-i386.c:938 -#: config/tc-i386.c:961 config/tc-m68k.c:4203 +#: config/tc-crx.c:619 config/tc-crx.c:637 config/tc-i386.c:942 +#: config/tc-i386.c:965 config/tc-m68k.c:4221 #, c-format msgid "Internal Error: Can't hash %s: %s" msgstr "" #. Missing or bad expr becomes absolute 0. -#: config/tc-crx.c:664 config/tc-i386.c:4132 +#: config/tc-crx.c:665 config/tc-i386.c:4164 #, c-format msgid "missing or invalid displacement expression `%s' taken as 0" msgstr "" -#: config/tc-crx.c:802 config/tc-crx.c:822 config/tc-crx.c:837 +#: config/tc-crx.c:803 config/tc-crx.c:823 config/tc-crx.c:838 #, c-format msgid "Illegal register `%s' in Instruction `%s'" msgstr "" -#: config/tc-crx.c:865 +#: config/tc-crx.c:866 #, c-format msgid "Illegal Scale - `%d'" msgstr "" -#: config/tc-crx.c:981 +#: config/tc-crx.c:982 #, c-format msgid "Illegal operands (whitespace): `%s'" msgstr "" -#: config/tc-crx.c:993 config/tc-crx.c:1000 config/tc-crx.c:1017 -#: config/tc-crx.c:1803 +#: config/tc-crx.c:994 config/tc-crx.c:1001 config/tc-crx.c:1018 +#: config/tc-crx.c:1804 #, c-format msgid "Missing matching brackets : `%s'" msgstr "" -#: config/tc-crx.c:1043 +#: config/tc-crx.c:1044 #, c-format msgid "Unknown exception: `%s'" msgstr "" -#: config/tc-crx.c:1139 +#: config/tc-crx.c:1140 #, c-format msgid "Illegal `cinv' parameter: `%c'" msgstr "" -#: config/tc-crx.c:1172 +#: config/tc-crx.c:1173 #, c-format msgid "Unknown register: `%d'" msgstr "" #. Issue a error message when register is illegal. -#: config/tc-crx.c:1180 +#: config/tc-crx.c:1181 #, c-format msgid "Illegal register (`%s') in Instruction: `%s'" msgstr "" -#: config/tc-crx.c:1309 +#: config/tc-crx.c:1310 #, c-format msgid "Illegal Co-processor register in Instruction `%s' " msgstr "" -#: config/tc-crx.c:1316 +#: config/tc-crx.c:1317 #, c-format msgid "Illegal Co-processor special register in Instruction `%s' " msgstr "" -#: config/tc-crx.c:1615 +#: config/tc-crx.c:1616 msgid "Incorrect number of operands" msgstr "" -#: config/tc-crx.c:1617 +#: config/tc-crx.c:1618 #, c-format msgid "Illegal type of operand (arg %d)" msgstr "" -#: config/tc-crx.c:1623 +#: config/tc-crx.c:1624 #, c-format msgid "Operand out of range (arg %d)" msgstr "" -#: config/tc-crx.c:1626 +#: config/tc-crx.c:1627 #, c-format msgid "Operand has odd displacement (arg %d)" msgstr "" -#: config/tc-crx.c:1629 +#: config/tc-crx.c:1630 #, c-format msgid "Invalid DISPU4 operand value (arg %d)" msgstr "" -#: config/tc-crx.c:1632 +#: config/tc-crx.c:1633 #, c-format msgid "Invalid CST4 operand value (arg %d)" msgstr "" -#: config/tc-crx.c:1635 +#: config/tc-crx.c:1636 #, c-format msgid "Operand value is not within upper 64 KB (arg %d)" msgstr "" -#: config/tc-crx.c:1639 config/tc-crx.c:1670 +#: config/tc-crx.c:1640 config/tc-crx.c:1671 #, c-format msgid "Illegal operand (arg %d)" msgstr "" -#: config/tc-crx.c:1701 config/tc-crx.c:1718 +#: config/tc-crx.c:1702 config/tc-crx.c:1719 #, c-format msgid "Same src/dest register is used (`r%d'), result is undefined" msgstr "" -#: config/tc-crx.c:1710 +#: config/tc-crx.c:1711 #, c-format msgid "`%s' has undefined result" msgstr "" -#: config/tc-crx.c:1772 +#: config/tc-crx.c:1773 msgid "Invalid Register in Register List" msgstr "" -#: config/tc-crx.c:1826 +#: config/tc-crx.c:1827 #, c-format msgid "Illegal register `%s' in cop-register list" msgstr "" -#: config/tc-crx.c:1834 +#: config/tc-crx.c:1835 #, c-format msgid "Illegal register `%s' in cop-special-register list" msgstr "" -#: config/tc-crx.c:1853 +#: config/tc-crx.c:1854 #, c-format msgid "Illegal register `%s' in user register list" msgstr "" -#: config/tc-crx.c:1872 +#: config/tc-crx.c:1873 #, c-format msgid "Illegal register `%s' in register list" msgstr "" -#: config/tc-crx.c:1878 +#: config/tc-crx.c:1879 #, c-format msgid "Maximum %d bits may be set in `mask16' operand" msgstr "" -#: config/tc-crx.c:1887 +#: config/tc-crx.c:1888 #, c-format msgid "rest of line ignored; first ignored character is `%c'" msgstr "" -#: config/tc-crx.c:1895 +#: config/tc-crx.c:1896 #, c-format msgid "Illegal `mask16' operand, operation is undefined - `%s'" msgstr "" #. HI can't be specified without LO (and vise-versa). -#: config/tc-crx.c:1901 +#: config/tc-crx.c:1902 msgid "HI/LO registers should be specified together" msgstr "" -#: config/tc-crx.c:1907 +#: config/tc-crx.c:1908 msgid "HI/LO registers should be specified without additional registers" msgstr "" #. Give an error if a frag containing code is not aligned to a 2-byte #. boundary. -#: config/tc-crx.c:1992 config/tc-crx.h:78 +#: config/tc-crx.c:1993 config/tc-crx.h:78 msgid "instruction address is not a multiple of 2" msgstr "" @@ -3462,7 +3469,7 @@ msgid "" msgstr "" #: config/tc-d10v.c:496 config/tc-d30v.c:488 config/tc-mn10200.c:1075 -#: config/tc-mn10300.c:1817 config/tc-ppc.c:2375 config/tc-s390.c:1216 +#: config/tc-mn10300.c:1817 config/tc-ppc.c:2379 config/tc-s390.c:1216 #: config/tc-tic80.c:259 config/tc-v850.c:1949 msgid "illegal operand" msgstr "" @@ -3554,7 +3561,7 @@ msgstr "" msgid "bad opcode or operands" msgstr "" -#: config/tc-d10v.c:1296 config/tc-m68k.c:4689 +#: config/tc-d10v.c:1296 config/tc-m68k.c:4707 msgid "value out of range" msgstr "" @@ -3792,8 +3799,8 @@ msgid "Instruction %s not allowed in a d msgstr "" #: config/tc-fr30.c:358 config/tc-frv.c:1600 config/tc-i960.c:1764 -#: config/tc-ip2k.c:371 config/tc-m32r.c:2143 config/tc-openrisc.c:376 -#: config/tc-xstormy16.c:631 +#: config/tc-ip2k.c:371 config/tc-m32c.c:869 config/tc-m32r.c:2143 +#: config/tc-openrisc.c:376 config/tc-xstormy16.c:631 msgid "Bad call to md_atof()" msgstr "" @@ -3931,8 +3938,8 @@ msgstr "" #: config/tc-h8300.c:82 config/tc-h8300.c:93 config/tc-h8300.c:105 #: config/tc-h8300.c:117 config/tc-h8300.c:129 config/tc-h8300.c:142 -#: config/tc-h8300.c:213 config/tc-hppa.c:1441 config/tc-hppa.c:6930 -#: config/tc-hppa.c:6936 config/tc-hppa.c:6942 config/tc-hppa.c:6948 +#: config/tc-h8300.c:213 config/tc-hppa.c:1441 config/tc-hppa.c:6917 +#: config/tc-hppa.c:6923 config/tc-hppa.c:6929 config/tc-hppa.c:6935 #: config/tc-mn10300.c:1223 config/tc-mn10300.c:1228 config/tc-mn10300.c:2726 msgid "could not set architecture and machine" msgstr "" @@ -4203,11 +4210,11 @@ msgstr "" msgid "internal error: losing opcode: `%s' \"%s\"\n" msgstr "" -#: config/tc-hppa.c:1542 config/tc-hppa.c:7069 config/tc-hppa.c:7126 +#: config/tc-hppa.c:1542 config/tc-hppa.c:7056 config/tc-hppa.c:7113 msgid "Missing function name for .PROC (corrupted label chain)" msgstr "" -#: config/tc-hppa.c:1545 config/tc-hppa.c:7129 +#: config/tc-hppa.c:1545 config/tc-hppa.c:7116 msgid "Missing function name for .PROC" msgstr "" @@ -4381,384 +4388,384 @@ msgstr "" msgid "Invalid Nullification: (%c)" msgstr "" -#: config/tc-hppa.c:5954 +#: config/tc-hppa.c:5951 msgid "Argument to .BLOCK/.BLOCKZ must be between 0 and 0x3fffffff" msgstr "" -#: config/tc-hppa.c:6080 +#: config/tc-hppa.c:6067 #, c-format msgid "Invalid .CALL argument: %s" msgstr "" -#: config/tc-hppa.c:6202 +#: config/tc-hppa.c:6189 msgid ".callinfo is not within a procedure definition" msgstr "" -#: config/tc-hppa.c:6222 +#: config/tc-hppa.c:6209 #, c-format msgid "FRAME parameter must be a multiple of 8: %d\n" msgstr "" -#: config/tc-hppa.c:6241 +#: config/tc-hppa.c:6228 msgid "Value for ENTRY_GR must be in the range 3..18\n" msgstr "" -#: config/tc-hppa.c:6253 +#: config/tc-hppa.c:6240 msgid "Value for ENTRY_FR must be in the range 12..21\n" msgstr "" -#: config/tc-hppa.c:6263 +#: config/tc-hppa.c:6250 msgid "Value for ENTRY_SR must be 3\n" msgstr "" -#: config/tc-hppa.c:6319 +#: config/tc-hppa.c:6306 #, c-format msgid "Invalid .CALLINFO argument: %s" msgstr "" -#: config/tc-hppa.c:6431 +#: config/tc-hppa.c:6418 msgid "The .ENTER pseudo-op is not supported" msgstr "" -#: config/tc-hppa.c:6447 +#: config/tc-hppa.c:6434 msgid "Misplaced .entry. Ignored." msgstr "" -#: config/tc-hppa.c:6451 +#: config/tc-hppa.c:6438 msgid "Missing .callinfo." msgstr "" -#: config/tc-hppa.c:6517 +#: config/tc-hppa.c:6504 msgid ".REG expression must be a register" msgstr "" -#: config/tc-hppa.c:6533 +#: config/tc-hppa.c:6520 msgid "bad or irreducible absolute expression; zero assumed" msgstr "" -#: config/tc-hppa.c:6544 +#: config/tc-hppa.c:6531 msgid ".REG must use a label" msgstr "" -#: config/tc-hppa.c:6546 +#: config/tc-hppa.c:6533 msgid ".EQU must use a label" msgstr "" -#: config/tc-hppa.c:6599 +#: config/tc-hppa.c:6586 msgid ".EXIT must appear within a procedure" msgstr "" -#: config/tc-hppa.c:6603 +#: config/tc-hppa.c:6590 msgid "Missing .callinfo" msgstr "" -#: config/tc-hppa.c:6607 +#: config/tc-hppa.c:6594 msgid "No .ENTRY for this .EXIT" msgstr "" -#: config/tc-hppa.c:6634 +#: config/tc-hppa.c:6621 #, c-format msgid "Cannot define export symbol: %s\n" msgstr "" -#: config/tc-hppa.c:6692 +#: config/tc-hppa.c:6679 #, c-format msgid "Using ENTRY rather than CODE in export directive for %s" msgstr "" -#: config/tc-hppa.c:6809 +#: config/tc-hppa.c:6796 #, c-format msgid "Undefined .EXPORT/.IMPORT argument (ignored): %s" msgstr "" -#: config/tc-hppa.c:6891 +#: config/tc-hppa.c:6878 msgid "Missing label name on .LABEL" msgstr "" -#: config/tc-hppa.c:6896 +#: config/tc-hppa.c:6883 msgid "extra .LABEL arguments ignored." msgstr "" -#: config/tc-hppa.c:6913 +#: config/tc-hppa.c:6900 msgid "The .LEAVE pseudo-op is not supported" msgstr "" -#: config/tc-hppa.c:6952 +#: config/tc-hppa.c:6939 msgid "Unrecognized .LEVEL argument\n" msgstr "" -#: config/tc-hppa.c:6988 +#: config/tc-hppa.c:6975 #, c-format msgid "Cannot define static symbol: %s\n" msgstr "" -#: config/tc-hppa.c:7023 +#: config/tc-hppa.c:7010 msgid "Nested procedures" msgstr "" -#: config/tc-hppa.c:7033 +#: config/tc-hppa.c:7020 msgid "Cannot allocate unwind descriptor\n" msgstr "" -#: config/tc-hppa.c:7133 +#: config/tc-hppa.c:7120 msgid "misplaced .procend" msgstr "" -#: config/tc-hppa.c:7136 +#: config/tc-hppa.c:7123 msgid "Missing .callinfo for this procedure" msgstr "" -#: config/tc-hppa.c:7139 +#: config/tc-hppa.c:7126 msgid "Missing .EXIT for a .ENTRY" msgstr "" -#: config/tc-hppa.c:7177 +#: config/tc-hppa.c:7164 msgid "Not in a space.\n" msgstr "" -#: config/tc-hppa.c:7180 +#: config/tc-hppa.c:7167 msgid "Not in a subspace.\n" msgstr "" -#: config/tc-hppa.c:7271 +#: config/tc-hppa.c:7258 msgid "Invalid .SPACE argument" msgstr "" -#: config/tc-hppa.c:7318 +#: config/tc-hppa.c:7305 msgid "Can't change spaces within a procedure definition. Ignored" msgstr "" -#: config/tc-hppa.c:7447 +#: config/tc-hppa.c:7434 #, c-format msgid "Undefined space: '%s' Assuming space number = 0." msgstr "" -#: config/tc-hppa.c:7471 +#: config/tc-hppa.c:7458 msgid "Must be in a space before changing or declaring subspaces.\n" msgstr "" -#: config/tc-hppa.c:7475 +#: config/tc-hppa.c:7462 msgid "Can't change subspaces within a procedure definition. Ignored" msgstr "" -#: config/tc-hppa.c:7511 +#: config/tc-hppa.c:7498 msgid "Parameters of an existing subspace can't be modified" msgstr "" -#: config/tc-hppa.c:7563 +#: config/tc-hppa.c:7550 msgid "Alignment must be a power of 2" msgstr "" -#: config/tc-hppa.c:7610 +#: config/tc-hppa.c:7597 msgid "FIRST not supported as a .SUBSPACE argument" msgstr "" -#: config/tc-hppa.c:7612 +#: config/tc-hppa.c:7599 msgid "Invalid .SUBSPACE argument" msgstr "" -#: config/tc-hppa.c:7801 +#: config/tc-hppa.c:7788 #, c-format msgid "Internal error: Unable to find containing space for %s." msgstr "" -#: config/tc-hppa.c:7841 +#: config/tc-hppa.c:7828 #, c-format msgid "Out of memory: could not allocate new space chain entry: %s\n" msgstr "" -#: config/tc-hppa.c:7930 +#: config/tc-hppa.c:7917 #, c-format msgid "Out of memory: could not allocate new subspace chain entry: %s\n" msgstr "" -#: config/tc-hppa.c:8666 +#: config/tc-hppa.c:8653 #, c-format msgid "Symbol '%s' could not be created." msgstr "" -#: config/tc-hppa.c:8670 +#: config/tc-hppa.c:8657 msgid "No memory for symbol name." msgstr "" -#: config/tc-i386.c:706 +#: config/tc-i386.c:710 #, c-format msgid "%s shortened to %s" msgstr "" -#: config/tc-i386.c:762 +#: config/tc-i386.c:766 msgid "same type of prefix used twice" msgstr "" -#: config/tc-i386.c:780 +#: config/tc-i386.c:784 msgid "64bit mode not supported on this CPU." msgstr "" -#: config/tc-i386.c:784 +#: config/tc-i386.c:788 msgid "32bit mode not supported on this CPU." msgstr "" -#: config/tc-i386.c:817 +#: config/tc-i386.c:821 msgid "bad argument to syntax directive." msgstr "" -#: config/tc-i386.c:869 +#: config/tc-i386.c:873 #, c-format msgid "no such architecture: `%s'" msgstr "" -#: config/tc-i386.c:874 +#: config/tc-i386.c:878 msgid "missing cpu architecture" msgstr "" -#: config/tc-i386.c:888 +#: config/tc-i386.c:892 #, c-format msgid "no such architecture modifier: `%s'" msgstr "" -#: config/tc-i386.c:904 config/tc-i386.c:5191 +#: config/tc-i386.c:908 config/tc-i386.c:5252 msgid "Unknown architecture" msgstr "" -#: config/tc-i386.c:1219 +#: config/tc-i386.c:1223 msgid "There are no unsigned pc-relative relocations" msgstr "" -#: config/tc-i386.c:1226 config/tc-i386.c:5411 +#: config/tc-i386.c:1231 config/tc-i386.c:5476 #, c-format msgid "can not do %d byte pc-relative relocation" msgstr "" -#: config/tc-i386.c:1243 +#: config/tc-i386.c:1248 #, c-format msgid "can not do %s %d byte relocation" msgstr "" -#: config/tc-i386.c:1439 config/tc-i386.c:2436 +#: config/tc-i386.c:1452 config/tc-i386.c:2460 #, c-format msgid "ambiguous operand size for `%s'" msgstr "" -#: config/tc-i386.c:1487 +#: config/tc-i386.c:1500 #, c-format msgid "can't use register '%%%s' as operand %d in '%s'." msgstr "" #. UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. -#: config/tc-i386.c:1516 +#: config/tc-i386.c:1529 #, c-format msgid "translating to `%sp'" msgstr "" -#: config/tc-i386.c:1561 +#: config/tc-i386.c:1574 #, c-format msgid "can't encode register '%%%s' in an instruction requiring REX prefix." msgstr "" -#: config/tc-i386.c:1602 config/tc-i386.c:1701 +#: config/tc-i386.c:1615 config/tc-i386.c:1714 #, c-format msgid "no such instruction: `%s'" msgstr "" -#: config/tc-i386.c:1613 config/tc-i386.c:1733 +#: config/tc-i386.c:1626 config/tc-i386.c:1746 #, c-format msgid "invalid character %s in mnemonic" msgstr "" -#: config/tc-i386.c:1620 +#: config/tc-i386.c:1633 msgid "expecting prefix; got nothing" msgstr "" -#: config/tc-i386.c:1622 +#: config/tc-i386.c:1635 msgid "expecting mnemonic; got nothing" msgstr "" -#: config/tc-i386.c:1641 +#: config/tc-i386.c:1654 #, c-format msgid "redundant %s prefix" msgstr "" -#: config/tc-i386.c:1751 +#: config/tc-i386.c:1764 #, c-format msgid "`%s' is not supported in 64-bit mode" msgstr "" -#: config/tc-i386.c:1752 +#: config/tc-i386.c:1765 #, c-format msgid "`%s' is only supported in 64-bit mode" msgstr "" -#: config/tc-i386.c:1758 +#: config/tc-i386.c:1771 #, c-format msgid "`%s' is not supported on `%s%s'" msgstr "" -#: config/tc-i386.c:1765 +#: config/tc-i386.c:1778 msgid "use .code16 to ensure correct addressing mode" msgstr "" -#: config/tc-i386.c:1778 +#: config/tc-i386.c:1791 #, c-format msgid "expecting string instruction after `%s'" msgstr "" -#: config/tc-i386.c:1812 +#: config/tc-i386.c:1825 #, c-format msgid "invalid character %s before operand %d" msgstr "" -#: config/tc-i386.c:1826 +#: config/tc-i386.c:1839 #, c-format msgid "unbalanced parenthesis in operand %d." msgstr "" -#: config/tc-i386.c:1829 +#: config/tc-i386.c:1842 #, c-format msgid "unbalanced brackets in operand %d." msgstr "" -#: config/tc-i386.c:1838 +#: config/tc-i386.c:1851 #, c-format msgid "invalid character %s in operand %d" msgstr "" -#: config/tc-i386.c:1865 +#: config/tc-i386.c:1878 #, c-format msgid "spurious operands; (%d operands/instruction max)" msgstr "" -#: config/tc-i386.c:1888 +#: config/tc-i386.c:1901 msgid "expecting operand after ','; got nothing" msgstr "" -#: config/tc-i386.c:1893 +#: config/tc-i386.c:1906 msgid "expecting operand before ','; got nothing" msgstr "" #. We found no match. -#: config/tc-i386.c:2245 +#: config/tc-i386.c:2269 #, c-format msgid "suffix or operands invalid for `%s'" msgstr "" -#: config/tc-i386.c:2256 +#: config/tc-i386.c:2280 #, c-format msgid "indirect %s without `*'" msgstr "" #. Warn them that a data or address size prefix doesn't #. affect assembly of the next line of code. -#: config/tc-i386.c:2264 +#: config/tc-i386.c:2288 #, c-format msgid "stand-alone `%s' prefix" msgstr "" -#: config/tc-i386.c:2293 config/tc-i386.c:2308 +#: config/tc-i386.c:2317 config/tc-i386.c:2332 #, c-format msgid "`%s' operand %d must use `%%es' segment" msgstr "" -#: config/tc-i386.c:2418 +#: config/tc-i386.c:2442 msgid "" "no instruction mnemonic suffix given and no register operands; can't size " "instruction" @@ -4766,181 +4773,181 @@ msgstr "" #. Prohibit these changes in the 64bit mode, since the #. lowering is more complicated. -#: config/tc-i386.c:2519 config/tc-i386.c:2578 config/tc-i386.c:2595 -#: config/tc-i386.c:2627 config/tc-i386.c:2660 +#: config/tc-i386.c:2543 config/tc-i386.c:2602 config/tc-i386.c:2619 +#: config/tc-i386.c:2651 config/tc-i386.c:2684 #, c-format msgid "Incorrect register `%%%s' used with `%c' suffix" msgstr "" -#: config/tc-i386.c:2527 config/tc-i386.c:2585 config/tc-i386.c:2667 +#: config/tc-i386.c:2551 config/tc-i386.c:2609 config/tc-i386.c:2691 #, c-format msgid "using `%%%s' instead of `%%%s' due to `%c' suffix" msgstr "" -#: config/tc-i386.c:2542 config/tc-i386.c:2563 config/tc-i386.c:2614 -#: config/tc-i386.c:2645 +#: config/tc-i386.c:2566 config/tc-i386.c:2587 config/tc-i386.c:2638 +#: config/tc-i386.c:2669 #, c-format msgid "`%%%s' not allowed with `%s%c'" msgstr "" -#: config/tc-i386.c:2708 +#: config/tc-i386.c:2732 msgid "no instruction mnemonic suffix given; can't determine immediate size" msgstr "" -#: config/tc-i386.c:2741 +#: config/tc-i386.c:2765 #, c-format msgid "" "no instruction mnemonic suffix given; can't determine immediate size %x %c" msgstr "" #. Reversed arguments on faddp, fsubp, etc. -#: config/tc-i386.c:2790 +#: config/tc-i386.c:2814 #, c-format msgid "translating to `%s %%%s,%%%s'" msgstr "" #. Extraneous `l' suffix on fp insn. -#: config/tc-i386.c:2797 +#: config/tc-i386.c:2821 #, c-format msgid "translating to `%s %%%s'" msgstr "" -#: config/tc-i386.c:2815 +#: config/tc-i386.c:2839 #, c-format msgid "you can't `pop %%cs'" msgstr "" -#. lea -#: config/tc-i386.c:2834 -msgid "segment override on `lea' is ineffectual" +#: config/tc-i386.c:2860 +#, c-format +msgid "segment override on `%s' is ineffectual" msgstr "" -#: config/tc-i386.c:3143 config/tc-i386.c:3237 config/tc-i386.c:3282 +#: config/tc-i386.c:3169 config/tc-i386.c:3263 config/tc-i386.c:3308 msgid "skipping prefixes on this instruction" msgstr "" -#: config/tc-i386.c:3302 +#: config/tc-i386.c:3328 msgid "16-bit jump out of range" msgstr "" -#: config/tc-i386.c:3311 +#: config/tc-i386.c:3337 #, c-format msgid "can't handle non absolute segment in `%s'" msgstr "" -#: config/tc-i386.c:3764 +#: config/tc-i386.c:3793 #, c-format msgid "@%s reloc is not supported in %s bit mode" msgstr "" -#: config/tc-i386.c:3882 +#: config/tc-i386.c:3911 msgid "only 1 or 2 immediate operands are allowed" msgstr "" -#: config/tc-i386.c:3905 config/tc-i386.c:4092 +#: config/tc-i386.c:3934 config/tc-i386.c:4121 #, c-format msgid "junk `%s' after expression" msgstr "" #. Missing or bad expr becomes absolute 0. -#: config/tc-i386.c:3916 +#: config/tc-i386.c:3945 #, c-format msgid "missing or invalid immediate expression `%s' taken as 0" msgstr "" -#: config/tc-i386.c:3941 config/tc-i386.c:4150 +#: config/tc-i386.c:3970 config/tc-i386.c:4182 #, c-format msgid "unimplemented segment %s in operand" msgstr "" -#: config/tc-i386.c:3987 +#: config/tc-i386.c:4016 #, c-format msgid "expecting scale factor of 1, 2, 4, or 8: got `%s'" msgstr "" -#: config/tc-i386.c:3996 +#: config/tc-i386.c:4025 #, c-format msgid "scale factor of %d without an index register" msgstr "" -#: config/tc-i386.c:4111 +#: config/tc-i386.c:4141 #, c-format msgid "bad expression used with @%s" msgstr "" -#: config/tc-i386.c:4234 +#: config/tc-i386.c:4289 #, c-format msgid "`%s' is not a valid base/index expression" msgstr "" -#: config/tc-i386.c:4238 +#: config/tc-i386.c:4293 #, c-format msgid "`%s' is not a valid %s bit base/index expression" msgstr "" -#: config/tc-i386.c:4312 +#: config/tc-i386.c:4367 #, c-format msgid "bad memory operand `%s'" msgstr "" -#: config/tc-i386.c:4327 +#: config/tc-i386.c:4382 #, c-format msgid "junk `%s' after register" msgstr "" -#: config/tc-i386.c:4336 config/tc-i386.c:4451 config/tc-i386.c:4489 +#: config/tc-i386.c:4391 config/tc-i386.c:4506 config/tc-i386.c:4544 #, c-format msgid "bad register name `%s'" msgstr "" -#: config/tc-i386.c:4344 +#: config/tc-i386.c:4399 msgid "immediate operand illegal with absolute jump" msgstr "" -#: config/tc-i386.c:4366 +#: config/tc-i386.c:4421 #, c-format msgid "too many memory references for `%s'" msgstr "" -#: config/tc-i386.c:4444 +#: config/tc-i386.c:4499 #, c-format msgid "expecting `,' or `)' after index register in `%s'" msgstr "" -#: config/tc-i386.c:4468 +#: config/tc-i386.c:4523 #, c-format msgid "expecting `)' after scale factor in `%s'" msgstr "" -#: config/tc-i386.c:4475 +#: config/tc-i386.c:4530 #, c-format msgid "expecting index register or scale factor after `,'; got '%c'" msgstr "" -#: config/tc-i386.c:4482 +#: config/tc-i386.c:4537 #, c-format msgid "expecting `,' or `)' after base register in `%s'" msgstr "" #. It's not a memory operand; argh! -#: config/tc-i386.c:4523 +#: config/tc-i386.c:4578 #, c-format msgid "invalid char %s beginning operand %d `%s'" msgstr "" -#: config/tc-i386.c:4698 +#: config/tc-i386.c:4753 msgid "long jump required" msgstr "" -#: config/tc-i386.c:4976 +#: config/tc-i386.c:5037 msgid "Bad call to md_atof ()" msgstr "" -#: config/tc-i386.c:5143 +#: config/tc-i386.c:5204 msgid "No compiled in support for x86_64" msgstr "" -#: config/tc-i386.c:5164 +#: config/tc-i386.c:5225 #, c-format msgid "" " -Q ignored\n" @@ -4951,106 +4958,106 @@ msgid "" " -s ignored\n" msgstr "" -#: config/tc-i386.c:5172 +#: config/tc-i386.c:5233 #, c-format msgid "" " -n Do not optimize code alignment\n" " -q quieten some warnings\n" msgstr "" -#: config/tc-i386.c:5272 config/tc-s390.c:1826 +#: config/tc-i386.c:5333 config/tc-s390.c:1826 msgid "GOT already in symbol table" msgstr "" -#: config/tc-i386.c:5426 +#: config/tc-i386.c:5494 #, c-format msgid "can not do %d byte relocation" msgstr "" -#: config/tc-i386.c:5495 config/tc-s390.c:2272 +#: config/tc-i386.c:5563 config/tc-s390.c:2272 #, c-format msgid "cannot represent relocation type %s" msgstr "" -#: config/tc-i386.c:5750 +#: config/tc-i386.c:5818 #, c-format msgid "invalid operand for '%s' ('%s' unexpected)" msgstr "" -#: config/tc-i386.c:5762 +#: config/tc-i386.c:5830 #, c-format msgid "too many memory references for '%s'" msgstr "" #. See the comments in intel_bracket_expr. -#: config/tc-i386.c:5773 +#: config/tc-i386.c:5841 #, c-format msgid "Treating `%s' as memory reference" msgstr "" -#: config/tc-i386.c:6085 +#: config/tc-i386.c:6153 #, c-format msgid "Unknown operand modifier `%s'" msgstr "" -#: config/tc-i386.c:6095 +#: config/tc-i386.c:6163 msgid "Conflicting operand modifiers" msgstr "" -#: config/tc-i386.c:6144 +#: config/tc-i386.c:6212 msgid "Invalid operand to `OFFSET'" msgstr "" -#: config/tc-i386.c:6212 +#: config/tc-i386.c:6280 #, c-format msgid "`[%.*s]' taken to mean just `%.*s'" msgstr "" -#: config/tc-i386.c:6309 +#: config/tc-i386.c:6377 #, c-format msgid "`%s' is not a valid segment register" msgstr "" -#: config/tc-i386.c:6313 +#: config/tc-i386.c:6381 msgid "Extra segment override ignored" msgstr "" -#: config/tc-i386.c:6347 config/tc-i386.c:6516 +#: config/tc-i386.c:6415 config/tc-i386.c:6584 msgid "Register scaling only allowed in memory operands" msgstr "" -#: config/tc-i386.c:6369 config/tc-i386.c:6493 +#: config/tc-i386.c:6437 config/tc-i386.c:6561 #, c-format msgid "Syntax error: Expecting a constant, got `%s'" msgstr "" -#: config/tc-i386.c:6397 +#: config/tc-i386.c:6465 msgid "Too many register references in memory operand" msgstr "" -#: config/tc-i386.c:6408 +#: config/tc-i386.c:6476 msgid "Using register names in OFFSET expressions is deprecated" msgstr "" -#: config/tc-i386.c:6421 +#: config/tc-i386.c:6489 msgid "Invalid use of register" msgstr "" -#: config/tc-i386.c:6566 +#: config/tc-i386.c:6634 #, c-format msgid "Unrecognized token '%s'" msgstr "" -#: config/tc-i386.c:6583 +#: config/tc-i386.c:6651 #, c-format msgid "Unexpected token `%s'" msgstr "" -#: config/tc-i386.c:6745 +#: config/tc-i386.c:6813 msgid "`:' expected" msgstr "" -#: config/tc-i386.c:6770 +#: config/tc-i386.c:6838 #, c-format msgid "Unrecognized token `%s'" msgstr "" @@ -5227,7 +5234,7 @@ msgstr "" msgid "architecture of opcode conflicts with that of earlier instruction(s)" msgstr "" -#: config/tc-i960.c:1433 config/tc-xtensa.c:11298 +#: config/tc-i960.c:1433 config/tc-xtensa.c:11300 msgid "too many operands" msgstr "" @@ -5332,99 +5339,99 @@ msgstr "" msgid "option --link-relax is only supported in b.out format" msgstr "" -#: config/tc-ia64.c:1011 +#: config/tc-ia64.c:1005 msgid "Bad .section directive: want a,o,s,w,x,M,S,G,T in string" msgstr "" -#: config/tc-ia64.c:1148 +#: config/tc-ia64.c:1142 msgid "Unwind directive not followed by an instruction." msgstr "" -#: config/tc-ia64.c:4962 +#: config/tc-ia64.c:4934 msgid "Register name expected" msgstr "" -#: config/tc-ia64.c:4967 config/tc-ia64.c:5283 +#: config/tc-ia64.c:4939 config/tc-ia64.c:5255 msgid "Comma expected" msgstr "" -#: config/tc-ia64.c:4975 +#: config/tc-ia64.c:4947 msgid "Register value annotation ignored" msgstr "" -#: config/tc-ia64.c:5016 +#: config/tc-ia64.c:4988 msgid "Directive invalid within a bundle" msgstr "" -#: config/tc-ia64.c:5109 +#: config/tc-ia64.c:5081 msgid "Missing predicate relation type" msgstr "" -#: config/tc-ia64.c:5115 +#: config/tc-ia64.c:5087 msgid "Unrecognized predicate relation type" msgstr "" -#: config/tc-ia64.c:5162 +#: config/tc-ia64.c:5134 msgid "Bad register range" msgstr "" -#: config/tc-ia64.c:5171 +#: config/tc-ia64.c:5143 msgid "Predicate register expected" msgstr "" -#: config/tc-ia64.c:5176 +#: config/tc-ia64.c:5148 msgid "Duplicate predicate register ignored" msgstr "" -#: config/tc-ia64.c:5194 +#: config/tc-ia64.c:5166 msgid "Predicate source and target required" msgstr "" -#: config/tc-ia64.c:5196 config/tc-ia64.c:5208 +#: config/tc-ia64.c:5168 config/tc-ia64.c:5180 msgid "Use of p0 is not valid in this context" msgstr "" -#: config/tc-ia64.c:5203 +#: config/tc-ia64.c:5175 msgid "At least two PR arguments expected" msgstr "" -#: config/tc-ia64.c:5217 +#: config/tc-ia64.c:5189 msgid "At least one PR argument expected" msgstr "" -#: config/tc-ia64.c:5253 +#: config/tc-ia64.c:5225 #, c-format msgid "Inserting \"%s\" into entry hint table failed: %s" msgstr "" #. FIXME -- need 62-bit relocation type -#: config/tc-ia64.c:5729 +#: config/tc-ia64.c:5701 msgid "62-bit relocation not yet implemented" msgstr "" #. XXX technically, this is wrong: we should not be issuing warning #. messages until we're sure this instruction pattern is going to #. be used! -#: config/tc-ia64.c:5802 +#: config/tc-ia64.c:5774 msgid "lower 16 bits of mask ignored" msgstr "" -#: config/tc-ia64.c:6421 +#: config/tc-ia64.c:6385 msgid "Value truncated to 62 bits" msgstr "" #. Give an error if a frag containing code is not aligned to a 16 byte #. boundary. -#: config/tc-ia64.c:6558 config/tc-ia64.h:171 +#: config/tc-ia64.c:6522 config/tc-ia64.h:171 msgid "instruction address is not a multiple of 16" msgstr "" -#: config/tc-ia64.c:7094 +#: config/tc-ia64.c:7058 #, c-format msgid "Unrecognized option '-x%s'" msgstr "" -#: config/tc-ia64.c:7122 +#: config/tc-ia64.c:7086 msgid "" "IA-64 options:\n" " --mconstant-gp\t mark output file as using the constant-GP model\n" @@ -5450,79 +5457,79 @@ msgid "" "\t\t\t dependency violation checking\n" msgstr "" -#: config/tc-ia64.c:7152 +#: config/tc-ia64.c:7116 msgid "--gstabs is not supported for ia64" msgstr "" -#: config/tc-ia64.c:7496 config/tc-mips.c:1383 +#: config/tc-ia64.c:7460 config/tc-mips.c:1383 msgid "Could not set architecture and machine" msgstr "" -#: config/tc-ia64.c:7613 +#: config/tc-ia64.c:7586 msgid "Explicit stops are ignored in auto mode" msgstr "" -#: config/tc-ia64.c:7665 +#: config/tc-ia64.c:7608 msgid "Found '{' after explicit switch to automatic mode" msgstr "" -#: config/tc-ia64.c:8235 +#: config/tc-ia64.c:8197 #, c-format msgid "Unhandled dependency %s for %s (%s), note %d" msgstr "" -#: config/tc-ia64.c:9510 +#: config/tc-ia64.c:9472 #, c-format msgid "Unrecognized dependency specifier %d\n" msgstr "" -#: config/tc-ia64.c:10404 +#: config/tc-ia64.c:10366 msgid "Only the first path encountering the conflict is reported" msgstr "" -#: config/tc-ia64.c:10407 +#: config/tc-ia64.c:10369 msgid "This is the location of the conflicting usage" msgstr "" -#: config/tc-ia64.c:11614 +#: config/tc-ia64.c:11576 msgid "Can't add stop bit to mark end of instruction group" msgstr "" -#: config/tc-ia64.c:11714 read.c:1438 read.c:2204 read.c:2828 +#: config/tc-ia64.c:11676 read.c:1438 read.c:2204 read.c:2828 msgid "expected symbol name" msgstr "" -#: config/tc-ia64.c:11724 read.c:2214 read.c:2838 stabs.c:470 +#: config/tc-ia64.c:11686 read.c:2214 read.c:2838 stabs.c:470 #, c-format msgid "expected comma after \"%s\"" msgstr "" -#: config/tc-ia64.c:11766 +#: config/tc-ia64.c:11728 #, c-format msgid "`%s' is already the alias of %s `%s'" msgstr "" -#: config/tc-ia64.c:11776 +#: config/tc-ia64.c:11738 #, c-format msgid "%s `%s' already has an alias `%s'" msgstr "" -#: config/tc-ia64.c:11787 +#: config/tc-ia64.c:11749 #, c-format msgid "inserting \"%s\" into %s alias hash table failed: %s" msgstr "" -#: config/tc-ia64.c:11795 +#: config/tc-ia64.c:11757 #, c-format msgid "inserting \"%s\" into %s name hash table failed: %s" msgstr "" -#: config/tc-ia64.c:11814 +#: config/tc-ia64.c:11776 #, c-format msgid "symbol `%s' aliased to `%s' is not used" msgstr "" -#: config/tc-ia64.c:11836 +#: config/tc-ia64.c:11798 #, c-format msgid "section `%s' aliased to `%s' is not used" msgstr "" @@ -5546,6 +5553,11 @@ msgstr "" msgid "md_pcrel_from\n" msgstr "" +#: config/tc-m32c.c:128 +#, c-format +msgid " M32C specific command line options:\n" +msgstr "" + #. Pretend that we do not recognise this option. #: config/tc-m32r.c:332 msgid "Unrecognised option: -hidden" @@ -5762,7 +5774,7 @@ msgid "" "is this intentional ?" msgstr "" -#: config/tc-m32r.c:1493 config/tc-ppc.c:1768 config/tc-ppc.c:4360 +#: config/tc-m32r.c:1493 config/tc-ppc.c:1772 config/tc-ppc.c:4364 msgid "Expected comma after symbol-name: rest of line ignored." msgstr "" @@ -5771,16 +5783,16 @@ msgstr "" msgid ".SCOMMon length (%ld.) <0! Ignored." msgstr "" -#: config/tc-m32r.c:1517 config/tc-ppc.c:1790 config/tc-ppc.c:2947 -#: config/tc-ppc.c:4384 +#: config/tc-m32r.c:1517 config/tc-ppc.c:1794 config/tc-ppc.c:2951 +#: config/tc-ppc.c:4388 msgid "ignoring bad alignment" msgstr "" -#: config/tc-m32r.c:1529 config/tc-ppc.c:1827 config/tc-v850.c:323 +#: config/tc-m32r.c:1529 config/tc-ppc.c:1831 config/tc-v850.c:323 msgid "Common alignment not a power of 2" msgstr "" -#: config/tc-m32r.c:1544 config/tc-ppc.c:1801 config/tc-ppc.c:4396 +#: config/tc-m32r.c:1544 config/tc-ppc.c:1805 config/tc-ppc.c:4400 #, c-format msgid "Ignoring attempt to re-define symbol `%s'." msgstr "" @@ -6156,11 +6168,11 @@ msgstr "" msgid ", or aliases" msgstr "" -#: config/tc-m68k.c:758 config/tc-m68k.c:4775 config/tc-m68k.c:5166 +#: config/tc-m68k.c:758 config/tc-m68k.c:4793 config/tc-m68k.c:5184 msgid "Tried to convert PC relative branch to absolute jump" msgstr "" -#: config/tc-m68k.c:765 config/tc-m68k.c:4765 +#: config/tc-m68k.c:765 config/tc-m68k.c:4783 msgid "Tried to convert PC relative BSR to absolute JSR" msgstr "" @@ -6198,348 +6210,348 @@ msgstr "" msgid "Cannot make %s relocation PC relative" msgstr "" -#: config/tc-m68k.c:1112 config/tc-tahoe.c:1398 config/tc-vax.c:1952 +#: config/tc-m68k.c:1113 config/tc-tahoe.c:1398 config/tc-vax.c:1952 msgid "No operator" msgstr "" -#: config/tc-m68k.c:1142 config/tc-tahoe.c:1415 config/tc-vax.c:1969 +#: config/tc-m68k.c:1143 config/tc-tahoe.c:1415 config/tc-vax.c:1969 msgid "Unknown operator" msgstr "" -#: config/tc-m68k.c:1992 +#: config/tc-m68k.c:2007 msgid "invalid instruction for this architecture; needs " msgstr "" -#: config/tc-m68k.c:1998 +#: config/tc-m68k.c:2013 msgid "ColdFire ISA_A" msgstr "" -#: config/tc-m68k.c:2006 +#: config/tc-m68k.c:2021 msgid "ColdFire hardware divide" msgstr "" -#: config/tc-m68k.c:2014 +#: config/tc-m68k.c:2029 msgid "ColdFire ISA_A+" msgstr "" -#: config/tc-m68k.c:2022 +#: config/tc-m68k.c:2037 msgid "ColdFire ISA_B" msgstr "" -#: config/tc-m68k.c:2030 +#: config/tc-m68k.c:2045 msgid "ColdFire fpu" msgstr "" -#: config/tc-m68k.c:2037 +#: config/tc-m68k.c:2052 msgid "fpu (68040, 68060 or 68881/68882)" msgstr "" -#: config/tc-m68k.c:2040 +#: config/tc-m68k.c:2055 msgid "mmu (68030 or 68851)" msgstr "" -#: config/tc-m68k.c:2043 +#: config/tc-m68k.c:2058 msgid "68020 or higher" msgstr "" -#: config/tc-m68k.c:2046 +#: config/tc-m68k.c:2061 msgid "68000 or higher" msgstr "" -#: config/tc-m68k.c:2049 +#: config/tc-m68k.c:2064 msgid "68010 or higher" msgstr "" -#: config/tc-m68k.c:2077 +#: config/tc-m68k.c:2092 msgid "operands mismatch" msgstr "" -#: config/tc-m68k.c:2138 config/tc-m68k.c:2144 config/tc-m68k.c:2150 +#: config/tc-m68k.c:2153 config/tc-m68k.c:2159 config/tc-m68k.c:2165 #: config/tc-mmix.c:2488 config/tc-mmix.c:2512 msgid "operand out of range" msgstr "" -#: config/tc-m68k.c:2207 +#: config/tc-m68k.c:2222 #, c-format msgid "Bignum too big for %c format; truncated" msgstr "" -#: config/tc-m68k.c:2288 +#: config/tc-m68k.c:2303 msgid "displacement too large for this architecture; needs 68020 or higher" msgstr "" -#: config/tc-m68k.c:2399 +#: config/tc-m68k.c:2414 msgid "" "scale factor invalid on this architecture; needs cpu32 or 68020 or higher" msgstr "" -#: config/tc-m68k.c:2404 +#: config/tc-m68k.c:2419 msgid "invalid index size for coldfire" msgstr "" -#: config/tc-m68k.c:2457 +#: config/tc-m68k.c:2472 msgid "Forcing byte displacement" msgstr "" -#: config/tc-m68k.c:2459 +#: config/tc-m68k.c:2474 msgid "byte displacement out of range" msgstr "" -#: config/tc-m68k.c:2507 config/tc-m68k.c:2545 +#: config/tc-m68k.c:2522 config/tc-m68k.c:2560 msgid "invalid operand mode for this architecture; needs 68020 or higher" msgstr "" -#: config/tc-m68k.c:2531 config/tc-m68k.c:2565 +#: config/tc-m68k.c:2546 config/tc-m68k.c:2580 msgid ":b not permitted; defaulting to :w" msgstr "" -#: config/tc-m68k.c:2642 +#: config/tc-m68k.c:2657 msgid "unsupported byte value; use a different suffix" msgstr "" -#: config/tc-m68k.c:2657 +#: config/tc-m68k.c:2672 msgid "unknown/incorrect operand" msgstr "" -#: config/tc-m68k.c:2700 config/tc-m68k.c:2708 config/tc-m68k.c:2715 -#: config/tc-m68k.c:2722 +#: config/tc-m68k.c:2715 config/tc-m68k.c:2723 config/tc-m68k.c:2730 +#: config/tc-m68k.c:2737 msgid "out of range" msgstr "" -#: config/tc-m68k.c:2768 +#: config/tc-m68k.c:2783 msgid "Can't use long branches on 68000/68010/5200" msgstr "" -#: config/tc-m68k.c:2885 +#: config/tc-m68k.c:2900 msgid "Expression out of range, using 0" msgstr "" -#: config/tc-m68k.c:3066 config/tc-m68k.c:3082 +#: config/tc-m68k.c:3081 config/tc-m68k.c:3097 msgid "Floating point register in register list" msgstr "" -#: config/tc-m68k.c:3072 +#: config/tc-m68k.c:3087 msgid "Wrong register in floating-point reglist" msgstr "" -#: config/tc-m68k.c:3088 +#: config/tc-m68k.c:3103 msgid "incorrect register in reglist" msgstr "" -#: config/tc-m68k.c:3094 +#: config/tc-m68k.c:3109 msgid "wrong register in floating-point reglist" msgstr "" #. ERROR. -#: config/tc-m68k.c:3557 +#: config/tc-m68k.c:3572 msgid "Extra )" msgstr "" #. ERROR. -#: config/tc-m68k.c:3568 +#: config/tc-m68k.c:3583 msgid "Missing )" msgstr "" -#: config/tc-m68k.c:3585 +#: config/tc-m68k.c:3600 msgid "Missing operand" msgstr "" -#: config/tc-m68k.c:3947 +#: config/tc-m68k.c:3962 #, c-format msgid "%s -- statement `%s' ignored" msgstr "" -#: config/tc-m68k.c:3996 +#: config/tc-m68k.c:4011 #, c-format msgid "Don't know how to figure width of %c in md_assemble()" msgstr "" -#: config/tc-m68k.c:4162 +#: config/tc-m68k.c:4180 #, c-format msgid "Internal Error: Can't allocate m68k_sorted_opcodes of size %d" msgstr "" -#: config/tc-m68k.c:4213 config/tc-m68k.c:4252 +#: config/tc-m68k.c:4231 config/tc-m68k.c:4270 #, c-format msgid "Internal Error: Can't find %s in hash table" msgstr "" -#: config/tc-m68k.c:4216 config/tc-m68k.c:4255 +#: config/tc-m68k.c:4234 config/tc-m68k.c:4273 #, c-format msgid "Internal Error: Can't hash %s: %s" msgstr "" -#: config/tc-m68k.c:4336 +#: config/tc-m68k.c:4354 msgid "architecture not yet selected: defaulting to 68020" msgstr "" -#: config/tc-m68k.c:4396 +#: config/tc-m68k.c:4414 #, c-format msgid "unrecognized default cpu `%s' ???" msgstr "" -#: config/tc-m68k.c:4407 +#: config/tc-m68k.c:4425 msgid "68040 and 68851 specified; mmu instructions may assemble incorrectly" msgstr "" -#: config/tc-m68k.c:4424 +#: config/tc-m68k.c:4442 msgid "options for 68881 and no-68881 both given" msgstr "" -#: config/tc-m68k.c:4427 +#: config/tc-m68k.c:4445 msgid "options for 68851 and no-68851 both given" msgstr "" -#: config/tc-m68k.c:4496 +#: config/tc-m68k.c:4514 #, c-format msgid "text label `%s' aligned to odd boundary" msgstr "" -#: config/tc-m68k.c:4705 +#: config/tc-m68k.c:4723 msgid "invalid byte branch offset" msgstr "" -#: config/tc-m68k.c:4741 +#: config/tc-m68k.c:4759 msgid "short branch with zero offset: use :w" msgstr "" -#: config/tc-m68k.c:4791 config/tc-m68k.c:4850 config/tc-m68k.c:4914 +#: config/tc-m68k.c:4809 config/tc-m68k.c:4868 config/tc-m68k.c:4932 msgid "Tried to convert PC relative conditional branch to absolute jump" msgstr "" -#: config/tc-m68k.c:4831 +#: config/tc-m68k.c:4849 msgid "Tried to convert DBcc to absolute jump" msgstr "" -#: config/tc-m68k.c:5210 config/tc-m68k.c:5221 config/tc-m68k.c:5261 +#: config/tc-m68k.c:5228 config/tc-m68k.c:5239 config/tc-m68k.c:5279 msgid "expression out of range: defaulting to 1" msgstr "" -#: config/tc-m68k.c:5253 +#: config/tc-m68k.c:5271 msgid "expression out of range: defaulting to 0" msgstr "" -#: config/tc-m68k.c:5294 config/tc-m68k.c:5306 +#: config/tc-m68k.c:5312 config/tc-m68k.c:5324 #, c-format msgid "Can't deal with expression; defaulting to %ld" msgstr "" -#: config/tc-m68k.c:5320 +#: config/tc-m68k.c:5338 msgid "expression doesn't fit in BYTE" msgstr "" -#: config/tc-m68k.c:5324 +#: config/tc-m68k.c:5342 msgid "expression doesn't fit in WORD" msgstr "" -#: config/tc-m68k.c:5411 +#: config/tc-m68k.c:5429 #, c-format msgid "%s: unrecognized processor name" msgstr "" -#: config/tc-m68k.c:5475 +#: config/tc-m68k.c:5493 msgid "bad coprocessor id" msgstr "" -#: config/tc-m68k.c:5481 +#: config/tc-m68k.c:5499 msgid "unrecognized fopt option" msgstr "" -#: config/tc-m68k.c:5614 +#: config/tc-m68k.c:5632 #, c-format msgid "option `%s' may not be negated" msgstr "" -#: config/tc-m68k.c:5625 +#: config/tc-m68k.c:5643 #, c-format msgid "option `%s' not recognized" msgstr "" -#: config/tc-m68k.c:5654 +#: config/tc-m68k.c:5672 msgid "bad format of OPT NEST=depth" msgstr "" -#: config/tc-m68k.c:5710 +#: config/tc-m68k.c:5728 msgid "missing label" msgstr "" -#: config/tc-m68k.c:5734 config/tc-m68k.c:5763 +#: config/tc-m68k.c:5752 config/tc-m68k.c:5781 msgid "bad register list" msgstr "" -#: config/tc-m68k.c:5736 +#: config/tc-m68k.c:5754 #, c-format msgid "bad register list: %s" msgstr "" -#: config/tc-m68k.c:5834 +#: config/tc-m68k.c:5852 msgid "restore without save" msgstr "" -#: config/tc-m68k.c:5988 config/tc-m68k.c:6358 +#: config/tc-m68k.c:6006 config/tc-m68k.c:6376 msgid "syntax error in structured control directive" msgstr "" -#: config/tc-m68k.c:6033 +#: config/tc-m68k.c:6051 msgid "missing condition code in structured control directive" msgstr "" -#: config/tc-m68k.c:6104 +#: config/tc-m68k.c:6122 #, c-format msgid "" "Condition <%c%c> in structured control directive can not be encoded correctly" msgstr "" -#: config/tc-m68k.c:6400 +#: config/tc-m68k.c:6418 msgid "missing then" msgstr "" -#: config/tc-m68k.c:6481 +#: config/tc-m68k.c:6499 msgid "else without matching if" msgstr "" -#: config/tc-m68k.c:6514 +#: config/tc-m68k.c:6532 msgid "endi without matching if" msgstr "" -#: config/tc-m68k.c:6554 +#: config/tc-m68k.c:6572 msgid "break outside of structured loop" msgstr "" -#: config/tc-m68k.c:6592 +#: config/tc-m68k.c:6610 msgid "next outside of structured loop" msgstr "" -#: config/tc-m68k.c:6643 +#: config/tc-m68k.c:6661 msgid "missing =" msgstr "" -#: config/tc-m68k.c:6681 +#: config/tc-m68k.c:6699 msgid "missing to or downto" msgstr "" -#: config/tc-m68k.c:6717 config/tc-m68k.c:6751 config/tc-m68k.c:6965 +#: config/tc-m68k.c:6735 config/tc-m68k.c:6769 config/tc-m68k.c:6983 msgid "missing do" msgstr "" -#: config/tc-m68k.c:6852 +#: config/tc-m68k.c:6870 msgid "endf without for" msgstr "" -#: config/tc-m68k.c:6906 +#: config/tc-m68k.c:6924 msgid "until without repeat" msgstr "" -#: config/tc-m68k.c:7000 +#: config/tc-m68k.c:7018 msgid "endw without while" msgstr "" -#: config/tc-m68k.c:7162 +#: config/tc-m68k.c:7180 #, c-format msgid "unrecognized architecture specification `%s'" msgstr "" -#: config/tc-m68k.c:7255 +#: config/tc-m68k.c:7273 #, c-format msgid "" "680X0 options:\n" @@ -6554,7 +6566,7 @@ msgid "" "\t\t\t[default yes for 68020, 68030, and cpu32]\n" msgstr "" -#: config/tc-m68k.c:7267 +#: config/tc-m68k.c:7285 #, c-format msgid "" "-m68851 | -mno-68851\n" @@ -6568,7 +6580,7 @@ msgid "" "--bitwise-or\t\tdo not treat `|' as a comment character\n" msgstr "" -#: config/tc-m68k.c:7277 +#: config/tc-m68k.c:7295 #, c-format msgid "" "--base-size-default-16\tbase reg without size is 16 bits\n" @@ -6577,12 +6589,12 @@ msgid "" "--disp-size-default-32\tdisplacement with unknown size is 32 bits (default)\n" msgstr "" -#: config/tc-m68k.c:7312 +#: config/tc-m68k.c:7330 #, c-format msgid "Error %s in %s\n" msgstr "" -#: config/tc-m68k.c:7316 +#: config/tc-m68k.c:7334 #, c-format msgid "Opcode(%d.%s): " msgstr "" @@ -7439,7 +7451,7 @@ msgstr "" msgid "Bad .mask/.fmask directive" msgstr "" -#: config/tc-mips.c:13952 +#: config/tc-mips.c:13959 #, c-format msgid "" "MIPS options:\n" @@ -7450,7 +7462,7 @@ msgid "" "\t\t\timplicitly with the gp register [default 8]\n" msgstr "" -#: config/tc-mips.c:13959 +#: config/tc-mips.c:13966 #, c-format msgid "" "-mips1\t\t\tgenerate MIPS ISA I instructions\n" @@ -7465,7 +7477,7 @@ msgid "" "-march=CPU/-mtune=CPU\tgenerate code/schedule for CPU, where CPU is one of:\n" msgstr "" -#: config/tc-mips.c:13978 +#: config/tc-mips.c:13985 #, c-format msgid "" "-mCPU\t\t\tequivalent to -march=CPU -mtune=CPU. Deprecated.\n" @@ -7473,14 +7485,14 @@ msgid "" "\t\t\tFor -mCPU and -no-mCPU, CPU must be one of:\n" msgstr "" -#: config/tc-mips.c:13991 +#: config/tc-mips.c:13998 #, c-format msgid "" "-mips16\t\t\tgenerate mips16 instructions\n" "-no-mips16\t\tdo not generate mips16 instructions\n" msgstr "" -#: config/tc-mips.c:13994 +#: config/tc-mips.c:14001 #, c-format msgid "" "-mfix-vr4120\t\twork around certain VR4120 errata\n" @@ -7496,7 +7508,7 @@ msgid "" "--break, --no-trap\tbreak exception on div by 0 and mult overflow\n" msgstr "" -#: config/tc-mips.c:14007 +#: config/tc-mips.c:14014 #, c-format msgid "" "-KPIC, -call_shared\tgenerate SVR4 position independent code\n" @@ -7508,7 +7520,7 @@ msgid "" "-mabi=ABI\t\tcreate ABI conformant object file for:\n" msgstr "" -#: config/tc-mips.c:14026 +#: config/tc-mips.c:14033 #, c-format msgid "" "-32\t\t\tcreate o32 ABI object file (default)\n" @@ -7775,13 +7787,13 @@ msgid "" "none yet\n" msgstr "" -#: config/tc-mn10200.c:931 config/tc-mn10300.c:1392 config/tc-ppc.c:2130 +#: config/tc-mn10200.c:931 config/tc-mn10300.c:1392 config/tc-ppc.c:2134 #: config/tc-s390.c:1522 config/tc-v850.c:1621 #, c-format msgid "Unrecognized opcode: `%s'" msgstr "" -#: config/tc-mn10200.c:1174 config/tc-mn10300.c:1965 config/tc-ppc.c:2609 +#: config/tc-mn10200.c:1174 config/tc-mn10300.c:1965 config/tc-ppc.c:2613 #: config/tc-s390.c:1437 config/tc-v850.c:2026 #, c-format msgid "junk at end of line: `%s'" @@ -8343,237 +8355,237 @@ msgstr "" msgid "Neither Power nor PowerPC opcodes were selected." msgstr "" -#: config/tc-ppc.c:1280 config/tc-s390.c:517 +#: config/tc-ppc.c:1284 config/tc-s390.c:517 #, c-format msgid "Internal assembler error for instruction %s" msgstr "" -#: config/tc-ppc.c:1304 +#: config/tc-ppc.c:1308 #, c-format msgid "Internal assembler error for macro %s" msgstr "" -#: config/tc-ppc.c:1635 +#: config/tc-ppc.c:1639 msgid "identifier+constant@got means identifier@got+constant" msgstr "" -#: config/tc-ppc.c:1702 +#: config/tc-ppc.c:1706 #, c-format msgid "%s relocations do not fit in %d bytes\n" msgstr "" -#: config/tc-ppc.c:1809 +#: config/tc-ppc.c:1813 #, c-format msgid "Length of .lcomm \"%s\" is already %ld. Not changed to %ld." msgstr "" -#: config/tc-ppc.c:1891 +#: config/tc-ppc.c:1895 msgid "Relocation cannot be done when using -mrelocatable" msgstr "" -#: config/tc-ppc.c:1940 +#: config/tc-ppc.c:1944 msgid "TOC section size exceeds 64k" msgstr "" -#: config/tc-ppc.c:2022 +#: config/tc-ppc.c:2026 #, c-format msgid "syntax error: invalid toc specifier `%s'" msgstr "" -#: config/tc-ppc.c:2036 +#: config/tc-ppc.c:2040 #, c-format msgid "syntax error: expected `]', found `%c'" msgstr "" -#: config/tc-ppc.c:2315 +#: config/tc-ppc.c:2319 msgid "[tocv] symbol is not a toc symbol" msgstr "" -#: config/tc-ppc.c:2326 +#: config/tc-ppc.c:2330 msgid "Unimplemented toc32 expression modifier" msgstr "" -#: config/tc-ppc.c:2331 +#: config/tc-ppc.c:2335 msgid "Unimplemented toc64 expression modifier" msgstr "" -#: config/tc-ppc.c:2335 +#: config/tc-ppc.c:2339 #, c-format msgid "Unexpected return value [%d] from parse_toc_entry!\n" msgstr "" -#: config/tc-ppc.c:2553 +#: config/tc-ppc.c:2557 msgid "unsupported relocation for DS offset field" msgstr "" -#: config/tc-ppc.c:2597 +#: config/tc-ppc.c:2601 #, c-format msgid "syntax error; found `%c' but expected `%c'" msgstr "" -#: config/tc-ppc.c:2640 config/tc-ppc.h:117 +#: config/tc-ppc.c:2644 config/tc-ppc.h:115 msgid "instruction address is not a multiple of 4" msgstr "" -#: config/tc-ppc.c:2751 +#: config/tc-ppc.c:2755 msgid "wrong number of operands" msgstr "" -#: config/tc-ppc.c:2807 +#: config/tc-ppc.c:2811 msgid "Bad .section directive: want a,e,w,x,M,S,G,T in string" msgstr "" -#: config/tc-ppc.c:2922 +#: config/tc-ppc.c:2926 msgid "missing size" msgstr "" -#: config/tc-ppc.c:2931 +#: config/tc-ppc.c:2935 msgid "negative size" msgstr "" -#: config/tc-ppc.c:2968 +#: config/tc-ppc.c:2972 msgid "missing real symbol name" msgstr "" -#: config/tc-ppc.c:2989 +#: config/tc-ppc.c:2993 msgid "attempt to redefine symbol" msgstr "" -#: config/tc-ppc.c:3236 +#: config/tc-ppc.c:3240 msgid "The XCOFF file format does not support arbitrary sections" msgstr "" -#: config/tc-ppc.c:3313 +#: config/tc-ppc.c:3317 msgid "missing rename string" msgstr "" -#: config/tc-ppc.c:3344 config/tc-ppc.c:3899 read.c:3042 +#: config/tc-ppc.c:3348 config/tc-ppc.c:3903 read.c:3042 msgid "missing value" msgstr "" -#: config/tc-ppc.c:3362 +#: config/tc-ppc.c:3366 msgid "illegal .stabx expression; zero assumed" msgstr "" -#: config/tc-ppc.c:3394 +#: config/tc-ppc.c:3398 msgid "missing class" msgstr "" -#: config/tc-ppc.c:3403 +#: config/tc-ppc.c:3407 msgid "missing type" msgstr "" -#: config/tc-ppc.c:3484 +#: config/tc-ppc.c:3488 msgid "missing symbol name" msgstr "" -#: config/tc-ppc.c:3678 +#: config/tc-ppc.c:3682 msgid "nested .bs blocks" msgstr "" -#: config/tc-ppc.c:3711 +#: config/tc-ppc.c:3715 msgid ".es without preceding .bs" msgstr "" -#: config/tc-ppc.c:3891 +#: config/tc-ppc.c:3895 msgid "non-constant byte count" msgstr "" -#: config/tc-ppc.c:3939 +#: config/tc-ppc.c:3943 msgid ".tc not in .toc section" msgstr "" -#: config/tc-ppc.c:3958 +#: config/tc-ppc.c:3962 msgid ".tc with no label" msgstr "" -#: config/tc-ppc.c:4050 +#: config/tc-ppc.c:4054 msgid ".machine stack overflow" msgstr "" -#: config/tc-ppc.c:4057 +#: config/tc-ppc.c:4061 msgid ".machine stack underflow" msgstr "" -#: config/tc-ppc.c:4064 +#: config/tc-ppc.c:4068 #, c-format msgid "invalid machine `%s'" msgstr "" -#: config/tc-ppc.c:4118 +#: config/tc-ppc.c:4122 msgid "No previous section to return to. Directive ignored." msgstr "" #. Section Contents #. unknown -#: config/tc-ppc.c:4535 +#: config/tc-ppc.c:4539 msgid "Unsupported section attribute -- 'a'" msgstr "" -#: config/tc-ppc.c:4724 +#: config/tc-ppc.c:4728 msgid "bad symbol suffix" msgstr "" -#: config/tc-ppc.c:4817 +#: config/tc-ppc.c:4821 msgid "Unrecognized symbol suffix" msgstr "" -#: config/tc-ppc.c:4903 +#: config/tc-ppc.c:4907 msgid "two .function pseudo-ops with no intervening .ef" msgstr "" -#: config/tc-ppc.c:4916 +#: config/tc-ppc.c:4920 msgid ".ef with no preceding .function" msgstr "" -#: config/tc-ppc.c:5044 +#: config/tc-ppc.c:5048 #, c-format msgid "warning: symbol %s has no csect" msgstr "" -#: config/tc-ppc.c:5348 +#: config/tc-ppc.c:5352 msgid "symbol in .toc does not match any .tc" msgstr "" -#: config/tc-ppc.c:5677 config/tc-s390.c:2057 config/tc-v850.c:2314 +#: config/tc-ppc.c:5681 config/tc-s390.c:2057 config/tc-v850.c:2314 #: config/tc-xstormy16.c:538 msgid "unresolved expression that must be resolved" msgstr "" -#: config/tc-ppc.c:5680 +#: config/tc-ppc.c:5684 #, c-format msgid "unsupported relocation against %s" msgstr "" -#: config/tc-ppc.c:5753 +#: config/tc-ppc.c:5757 #, c-format msgid "cannot emit PC relative %s relocation against %s" msgstr "" -#: config/tc-ppc.c:5758 +#: config/tc-ppc.c:5762 #, c-format msgid "cannot emit PC relative %s relocation" msgstr "" -#: config/tc-ppc.c:5940 +#: config/tc-ppc.c:5944 #, c-format msgid "Unable to handle reference to symbol %s" msgstr "" -#: config/tc-ppc.c:5943 +#: config/tc-ppc.c:5947 msgid "Unable to resolve expression" msgstr "" -#: config/tc-ppc.c:5970 +#: config/tc-ppc.c:5974 msgid "must branch to an address a multiple of 4" msgstr "" -#: config/tc-ppc.c:5974 +#: config/tc-ppc.c:5978 #, c-format msgid "@local or @plt branch destination is too far away, %ld bytes" msgstr "" -#: config/tc-ppc.c:6005 +#: config/tc-ppc.c:6009 #, c-format msgid "Gas failure, reloc value %d\n" msgstr "" @@ -8618,11 +8630,6 @@ msgstr "" msgid "Big number is too big" msgstr "" -#: config/tc-s390.c:1126 config/tc-s390.c:1707 config/tc-xtensa.c:1626 -#, c-format -msgid "%s relocations do not fit in %d bytes" -msgstr "" - #: config/tc-s390.c:1136 msgid "relocation not applicable" msgstr "" @@ -9518,11 +9525,11 @@ msgstr "" msgid "Illegal operands: garbage after %%r_%s%d()" msgstr "" -#: config/tc-sparc.h:48 +#: config/tc-sparc.h:46 msgid "sparc convert_frag\n" msgstr "" -#: config/tc-sparc.h:50 +#: config/tc-sparc.h:48 msgid "estimate_size_before_relax called" msgstr "" @@ -11031,250 +11038,250 @@ msgstr "" msgid "unhandled local relocation fix %s" msgstr "" -#: config/tc-xtensa.c:5977 +#: config/tc-xtensa.c:5979 msgid "couldn't find a valid instruction format" msgstr "" -#: config/tc-xtensa.c:5978 +#: config/tc-xtensa.c:5980 #, c-format msgid " ops were: " msgstr "" -#: config/tc-xtensa.c:5980 +#: config/tc-xtensa.c:5982 #, c-format msgid " %s;" msgstr "" -#: config/tc-xtensa.c:5983 +#: config/tc-xtensa.c:5985 #, c-format msgid "\n" msgstr "" -#: config/tc-xtensa.c:5991 +#: config/tc-xtensa.c:5993 #, c-format msgid "format '%s' allows %d slots, but there are %d opcodes" msgstr "" -#: config/tc-xtensa.c:6002 config/tc-xtensa.c:6100 +#: config/tc-xtensa.c:6004 config/tc-xtensa.c:6102 msgid "illegal resource usage in bundle" msgstr "" -#: config/tc-xtensa.c:6187 +#: config/tc-xtensa.c:6189 #, c-format msgid "opcodes '%s' (slot %d) and '%s' (slot %d) write the same register" msgstr "" -#: config/tc-xtensa.c:6192 +#: config/tc-xtensa.c:6194 #, c-format msgid "opcodes '%s' (slot %d) and '%s' (slot %d) write the same state" msgstr "" -#: config/tc-xtensa.c:6197 +#: config/tc-xtensa.c:6199 #, c-format msgid "opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue" msgstr "" -#: config/tc-xtensa.c:6202 +#: config/tc-xtensa.c:6204 #, c-format msgid "" "opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses" msgstr "" -#: config/tc-xtensa.c:6218 +#: config/tc-xtensa.c:6220 msgid "multiple branches or jumps in the same bundle" msgstr "" -#: config/tc-xtensa.c:6672 +#: config/tc-xtensa.c:6674 msgid "cannot assemble into a literal fragment" msgstr "" -#: config/tc-xtensa.c:6674 +#: config/tc-xtensa.c:6676 msgid "..." msgstr "" -#: config/tc-xtensa.c:7178 +#: config/tc-xtensa.c:7180 msgid "" "instruction sequence (write a0, branch, retw) may trigger hardware errata" msgstr "" -#: config/tc-xtensa.c:7288 +#: config/tc-xtensa.c:7290 msgid "branching or jumping to a loop end may trigger hardware errata" msgstr "" -#: config/tc-xtensa.c:7387 +#: config/tc-xtensa.c:7389 msgid "loop end too close to another loop end may trigger hardware errata" msgstr "" -#: config/tc-xtensa.c:7396 +#: config/tc-xtensa.c:7398 #, c-format msgid "fr_var %lu < length %d" msgstr "" -#: config/tc-xtensa.c:7567 +#: config/tc-xtensa.c:7569 msgid "" "loop containing less than three instructions may trigger hardware errata" msgstr "" -#: config/tc-xtensa.c:7639 +#: config/tc-xtensa.c:7641 msgid "undecodable instruction in instruction frag" msgstr "" -#: config/tc-xtensa.c:7748 +#: config/tc-xtensa.c:7750 msgid "invalid empty loop" msgstr "" -#: config/tc-xtensa.c:7753 +#: config/tc-xtensa.c:7755 msgid "loop target does not follow loop instruction in section" msgstr "" -#: config/tc-xtensa.c:8290 +#: config/tc-xtensa.c:8292 msgid "bad relaxation state" msgstr "" -#: config/tc-xtensa.c:8348 +#: config/tc-xtensa.c:8350 #, c-format msgid "fr_var (%ld) < length (%d)" msgstr "" -#: config/tc-xtensa.c:8849 +#: config/tc-xtensa.c:8851 msgid "internal error: relaxation failed" msgstr "" -#: config/tc-xtensa.c:8855 +#: config/tc-xtensa.c:8857 msgid "internal error: relaxation requires too many steps" msgstr "" -#: config/tc-xtensa.c:9030 +#: config/tc-xtensa.c:9032 msgid "invalid relaxation fragment result" msgstr "" -#: config/tc-xtensa.c:9110 +#: config/tc-xtensa.c:9112 msgid "unable to widen instruction" msgstr "" -#: config/tc-xtensa.c:9253 +#: config/tc-xtensa.c:9255 msgid "multiple literals in expansion" msgstr "" -#: config/tc-xtensa.c:9257 +#: config/tc-xtensa.c:9259 msgid "no registered fragment for literal" msgstr "" -#: config/tc-xtensa.c:9259 +#: config/tc-xtensa.c:9261 msgid "number of literal tokens != 1" msgstr "" -#: config/tc-xtensa.c:9403 config/tc-xtensa.c:9409 +#: config/tc-xtensa.c:9405 config/tc-xtensa.c:9411 #, c-format msgid "unresolved loop target symbol: %s" msgstr "" -#: config/tc-xtensa.c:9515 +#: config/tc-xtensa.c:9517 #, c-format msgid "invalid expression evaluation type %d" msgstr "" -#: config/tc-xtensa.c:9537 +#: config/tc-xtensa.c:9539 msgid "loop too long for LOOP instruction" msgstr "" -#: config/tc-xtensa.c:9808 +#: config/tc-xtensa.c:9810 #, c-format msgid "fixes not all moved from %s" msgstr "" -#: config/tc-xtensa.c:9950 +#: config/tc-xtensa.c:9952 msgid "" "literal pool location required for text-section-literals; specify with ." "literal_position" msgstr "" -#: config/tc-xtensa.c:10459 +#: config/tc-xtensa.c:10461 #, c-format msgid "could not create section %s" msgstr "" -#: config/tc-xtensa.c:10461 +#: config/tc-xtensa.c:10463 #, c-format msgid "invalid flag combination on section %s" msgstr "" -#: config/tc-xtensa.c:10847 +#: config/tc-xtensa.c:10849 msgid "too many operands in instruction" msgstr "" -#: config/tc-xtensa.c:11081 +#: config/tc-xtensa.c:11083 #, c-format msgid "invalid symbolic operand %d on '%s'" msgstr "" -#: config/tc-xtensa.c:11150 config/tc-xtensa.c:11224 +#: config/tc-xtensa.c:11152 config/tc-xtensa.c:11226 msgid "operand number mismatch" msgstr "" -#: config/tc-xtensa.c:11153 +#: config/tc-xtensa.c:11155 msgid "cannot encode opcode" msgstr "" -#: config/tc-xtensa.c:11228 +#: config/tc-xtensa.c:11230 #, c-format msgid "cannot encode opcode \"%s\" in the given format \"%s\"" msgstr "" -#: config/tc-xtensa.c:11253 +#: config/tc-xtensa.c:11255 #, c-format msgid "xtensa-isa failure: %s" msgstr "" -#: config/tc-xtensa.c:11286 +#: config/tc-xtensa.c:11288 msgid "invalid opcode" msgstr "" -#: config/tc-xtensa.c:11292 +#: config/tc-xtensa.c:11294 msgid "too few operands" msgstr "" -#: config/tc-xtensa.c:11419 config/tc-xtensa.c:11427 +#: config/tc-xtensa.c:11421 config/tc-xtensa.c:11429 msgid "out of memory" msgstr "" -#: config/tc-xtensa.c:11539 +#: config/tc-xtensa.c:11541 msgid "instruction with constant operands does not fit" msgstr "" -#: config/tc-xtensa.c:11548 config/tc-xtensa.c:11569 +#: config/tc-xtensa.c:11550 config/tc-xtensa.c:11571 #, c-format msgid "invalid operand %d on '%s'" msgstr "" -#: config/tc-xtensa.c:11560 +#: config/tc-xtensa.c:11562 msgid "invalid subtract operand" msgstr "" -#: config/tc-xtensa.c:11574 +#: config/tc-xtensa.c:11576 #, c-format msgid "invalid expression for operand %d on '%s'" msgstr "" -#: config/tc-xtensa.c:11604 +#: config/tc-xtensa.c:11606 msgid "cannot decode instruction format" msgstr "" -#: config/tc-xtensa.c:11763 +#: config/tc-xtensa.c:11765 msgid "ignoring extra '-rename-section' delimiter ':'" msgstr "" -#: config/tc-xtensa.c:11768 +#: config/tc-xtensa.c:11770 #, c-format msgid "ignoring invalid '-rename-section' specification: '%s'" msgstr "" -#: config/tc-xtensa.c:11779 +#: config/tc-xtensa.c:11781 #, c-format msgid "section %s renamed multiple times" msgstr "" -#: config/tc-xtensa.c:11781 +#: config/tc-xtensa.c:11783 #, c-format msgid "multiple sections remapped to output section %s" msgstr "" diff -uprN binutils-2.16.91.0.1/gas/po/POTFILES.in binutils-2.16.91.0.2/gas/po/POTFILES.in --- binutils-2.16.91.0.1/gas/po/POTFILES.in 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/po/POTFILES.in 2005-07-20 12:27:27.908091647 -0700 @@ -74,6 +74,8 @@ config/tc-ia64.c config/tc-ia64.h config/tc-ip2k.c config/tc-ip2k.h +config/tc-m32c.c +config/tc-m32c.h config/tc-m32r.c config/tc-m32r.h config/tc-m68hc11.c diff -uprN binutils-2.16.91.0.1/gas/testsuite/ChangeLog binutils-2.16.91.0.2/gas/testsuite/ChangeLog --- binutils-2.16.91.0.1/gas/testsuite/ChangeLog 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/ChangeLog 2005-07-20 12:27:27.928088349 -0700 @@ -1,8 +1,163 @@ +2005-07-20 Kazuhiro Inaoka + + * gas/m32r/rel32.exp: New file. + * gas/m32r/rel32.s: New file. + * gas/m32r/rel32.d: New file. + * gas/m32r/rel32-pic.s: New file. + * gas/m32r/rel32-pic.d: New file. + * gas/m32r/rel32-err.s: New file. + * gas/m32r/error.exp: Added rel32-err. + +2005-07-18 H.J. Lu + + * gas/i386/i386.exp: Add suffix. + + * gas/i386/suffix.d: New file. + * gas/i386/suffix.s: Likewise. + +2005-07-18 John David Anglin + + * gas/hppa/basic/fp_comp.s: Add level 1.1 directive. + * gas/hppa/basic/special.s, gas/hppa/basic/system.s: Likewise. + +2005-07-18 Jan Beulich + + * gas/i386/reloc32.[sdl]: New. + * gas/i386/reloc64.[sdl]: New. + * gas/i386/i386.exp: Run new tests. + +2007-07-15 H.J. Lu + + * gas/i386/i386.exp: Add vmx and x86-64-vmx. + + * gas/i386/vmx.d: New file. + * gas/i386/vmx.s: Likewise. + * gas/i386/x86-64-vmx.d: Likewise. + * gas/i386/x86-64-vmx.s: Likewise. + +2005-07-14 Nick Clifton + + PR 1063 + * gas/crx/gas-segfault.d: New file. + * gas/crx/gas-segfault.s: New file. + +2005-07-12 Hans-Peter Nilsson + + * gas/mmix/relax1-n.d, gas/mmix/relax1-rn.d: Avoid "# FIXME: " + first on a line, adjusting for testsuite framework change. + +2005-07-10 H.J. Lu + + * i386/x86_64.s: Add absolute siged 32bit addressing tests for + mov. + * i386/x86_64.d: Updated. + +2005-07-08 Hans-Peter Nilsson + + PR gas/1049 + * gas/cris/rd-pic-2.d, gas/cris/rd-pic-2.s: New test. + * gas/cris/rd-abs32-1.d: Tweak for not emitting reloc-related + garbage for global symbols. + +2005-07-07 Nick Clifton + + * gas/arm/vfp1xD.d: Adjust expected fadds disassemblies now that + the dissassembler has been fixed. + +2005-05-07 Paul Brook + + * gas/ppc/altivec.d: Match all powerpc target vecs. + * gas/ppc/booke.d: Ditto. + * gas/ppc/e500.d: Ditto. + +2005-07-05 Aldy Hernandez + + * gas/ms1: New directory. + * gas/ms1/allinsn.d: New. + * gas/ms1/allinsn.s: New. + * gas/ms1/badinsn.s: New. + * gas/ms1/badinsn1.s: New. + * gas/ms1/badoffsethigh.s: New. + * gas/ms1/badoffsetlow.s: New. + * gas/ms1/badorder.s: New. + * gas/ms1/badreg.s: New. + * gas/ms1/badsignedimmhigh.s: New. + * gas/ms1/badsignedimmlow.s: New. + * gas/ms1/badsyntax.s: New. + * gas/ms1/badsyntax1.s: New. + * gas/ms1/badunsignedimmhigh.s: New. + * gas/ms1/badunsignedimmlow.s: New. + * gas/ms1/errors.exp: New. + * gas/ms1/ldst.s: New. + * gas/ms1/misc.d: New. + * gas/ms1/misc.s: New. + * gas/ms1/ms1-16-003.d: New. + * gas/ms1/ms1-16-003.s: New. + * gas/ms1/ms1.exp: New. + * gas/ms1/msys.d: New. + * gas/ms1/msys.s: New. + * gas/ms1/relocs.d: New. + * gas/ms1/relocs.exp: New. + * testsuite/gas/ms1/relocs1.s: New. + * testsuite/gas/ms1/relocs2.s: New. + +2005-07-05 Jan Beulich + + * gas/i386/svme.d: New. + * gas/i386/svme.s: New. + * gas/i386/svme64.d: New. + * gas/i386/i386.exp: Run new tests. + +2005-07-04 Zack Weinberg + + * lib/gas-defs.exp (run_dump_tests): New proc. + (run_dump_test): Add support for new options: target, not-target, + skip, not-skip, error-output. Document stderr. Tidy a + little. + (slurp_options): If a line doesn't match the option regexp, but + does begin with #, ignore it; don't stop parsing options. + * gas/arm/arm.exp: Remove most code. Use run_dump_tests. + + * gas/arm/archv6t2-bad.d, gas/arm/armv1.d, gas/arm/iwmmxt-bad.d + * gas/arm/r15-bad.d, gas/arm/req.d, gas/arm/t16-bad.d + * gas/arm/undefined.d, gas/arm/undefined_coff.d, gas/arm/vfp-bad.d: + New files. + * gas/arm/bignum1.d, gas/arm/mapping.d, gas/arm/pic.d: + Only run on ELF targets. + * gas/arm/tls.d, gas/arm/unwind.d: Only run on ELF targets. + Skip on VxWorks. + * gas/arm/tls_vxworks.d, gas/arm/unwind_vxworks.d: New files. + * gas/arm/thumb.d, gas/arm/thumb32.d: Don't run on aout or pe. + * gas/arm/le-fpconst.d: Only run on *-*-pe. + * gas/arm/inst.d: Skip on WinCE. + * gas/arm/wince_inst.d: Skip unless WinCE. + * gas/arm/el_segundo.d: Mark up for actual use; adjust + expectations. + * gas/arm/el_segundo.s: Remove irrelevant junk. Add padding + for a.out's sake. + +2005-07-01 Jan Beulich + + * gas/ia64/group-2.s: Use register as second operand of .prologue. + * gas/ia64/unwind-err.s: Add check for .vframesp. + * gas/ia64/unwind-err.l: Adjust. + * gas/ia64/strange.[sd]: New. + * gas/ia64/unwind-bad.[sl]: New. + * gas/ia64/unwind-ok.[sd]: New. + * gas/ia64/ia64.exp: Run new tests. + +2005-06-30 Zack Weinberg + + * gas/arm/arm.exp: Don't special case ldconst, arm7t, or copro + for *-wince-*. + * gas/arm/wince_arm7t.d, gas/arm/wince_copro.d + * gas/arm/wince_ldconst.d: Delete. + 2005-06-20 H.J. Lu PR 1013 * i386/x86_64.s: Add absolute 64bit addressing tests for mov. - * i386/x86_64.s: Updated. + * i386/x86_64.d: Updated. 2005-06-17 Jan Beulich diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/archv6t2-bad.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/archv6t2-bad.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/archv6t2-bad.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/archv6t2-bad.d 2005-07-20 12:27:27.928088349 -0700 @@ -0,0 +1,3 @@ +#name: Invalid V6T2 instructions +#as: -march=armv6t2 +#error-output: archv6t2-bad.l diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/arm.exp binutils-2.16.91.0.2/gas/testsuite/gas/arm/arm.exp --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/arm.exp 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/arm.exp 2005-07-20 12:27:27.929088185 -0700 @@ -1,94 +1,7 @@ # # Some ARM tests # -proc run_errors_test { name opts tname} { - global srcdir subdir - set testname "$tname" - set file $srcdir/$subdir/$name - gas_run ${name}.s $opts ">&${name}.out" - if { [regexp_diff "${name}.out" "${file}.l"] } then { - fail $testname - verbose "output is [file_contents "${name}.out"]" 2 - return - } - pass $testname -} - -if {[istarget *arm*-*-*] || [istarget "xscale-*-*"]} then { - - if {[istarget *-wince-*]} then { - run_dump_test "wince_inst" - run_dump_test "wince_ldconst" - run_dump_test "wince_arm7t" - run_dump_test "wince_copro" - } else { - run_dump_test "inst" - run_dump_test "ldconst" - run_dump_test "arm7t" - run_dump_test "copro" - } - - run_dump_test "arm3" - run_dump_test "arm6" - run_dump_test "arm7dm" - run_dump_test "arch4t" - run_dump_test "immed" - run_dump_test "float" - run_dump_test "offset" - run_dump_test "armv1" - run_dump_test "arch5tej" - run_dump_test "fpa-monadic" - run_dump_test "fpa-dyadic" - run_dump_test "fpa-mem" - run_dump_test "vfp1xD" - run_dump_test "vfp1" - run_dump_test "vfp2" - run_dump_test "xscale" - run_dump_test "adrl" - run_dump_test "reg-alias" - run_dump_test "maverick" - run_dump_test "archv6" - run_dump_test "archv6t2" - run_dump_test "thumbv6" - run_dump_test "thumbv6k" - run_dump_test "arch6zk" - run_dump_test "tcompat" - run_dump_test "tcompat2" - run_dump_test "iwmmxt" - run_dump_test "macro1" - - run_errors_test "vfp-bad" "-mfpu=vfp" "VFP errors" - run_errors_test "req" "-mcpu=arm7m" ".req errors" - run_errors_test "armv1-bad" "-mcpu=arm7m" "ARM v1 errors" - run_errors_test "r15-bad" "" "Invalid use of r15 errors" - run_errors_test "archv6t2-bad" "-march=armv6t2" "Invalid V6T2 instructions" - run_errors_test "t16-bad" "-march=armv6k" "Valid ARM, invalid Thumb" - run_errors_test "iwmmxt-bad" "-mcpu=iwmmxt" "iWMMXt errors" - - if {[istarget *-*-*coff] || [istarget *-*-pe] || [istarget *-*-wince] || - [istarget *-*-*aout*] || [istarget *-*-netbsd] || [istarget *-*-riscix*]} then { - # COFF and aout based ports use a different naming convention for local labels. - run_errors_test "undefined_coff" "" "Undefined local label error" - } else { - # For ELF based ports we can run some additional tests as well. - run_errors_test "undefined" "" "Undefined local label error" - - run_dump_test "pic" - run_dump_test "mapping" - run_dump_test "bignum1" - run_dump_test "unwind" - run_dump_test "tls" - } - - # The arm-aout port does not support Thumb branch relocations. - if {! [istarget arm*-*-aout] && ![istarget arm-*-pe]} then { - run_dump_test "thumb" - run_dump_test "thumb32" - } - # Not all arm targets are bi-endian, so only run this test on ones - # we know that are. FIXME: We should probably also key off armeb/armel. - if [istarget *-*-pe] { - run_dump_test "le-fpconst" - } +if {[istarget *arm*-*-*] || [istarget *xscale*-*-*]} { + run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]] } diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/armv1-bad.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/armv1-bad.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/armv1-bad.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/armv1-bad.d 2005-07-20 12:27:27.929088185 -0700 @@ -0,0 +1,3 @@ +#name: ARM v1 errors +#as: -mcpu=arm7m +#error-output: armv1-bad.l diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/bignum1.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/bignum1.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/bignum1.d 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/bignum1.d 2005-07-20 12:27:27.930088020 -0700 @@ -1,6 +1,8 @@ # name: bignums # as: # objdump: --full-contents +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* .*: +file format .*arm.* diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/el_segundo.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/el_segundo.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/el_segundo.d 2000-12-21 16:35:16.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/el_segundo.d 2005-07-20 12:27:27.936087030 -0700 @@ -1,33 +1,34 @@ +# name: El Segundo instructions +# objdump: -dr --prefix-addresses --show-raw-insn -el_segundo.o: file format elf32-littlearm +.*: +file format .*arm.* -Disassembly of section .text: - -00000000
: - 0: c1003281 smlabbgt r0, r1, r2, r3 - 4: e1003281 smlabb r0, r1, r2, r3 - 8: e10032a1 smlatb r0, r1, r2, r3 - c: e10032c1 smlabt r0, r1, r2, r3 - 10: e10032e1 smlatt r0, r1, r2, r3 - 14: c1203281 smlawbgt r0, r1, r2, r3 - 18: e1203281 smlawb r0, r1, r2, r3 - 1c: e12032c1 smlawt r0, r1, r2, r3 - 20: c1410382 smlalbbgt r0, r1, r2, r3 - 24: e1410382 smlalbb r0, r1, r2, r3 - 28: e14103a2 smlaltb r0, r1, r2, r3 - 2c: e14103c2 smlalbt r0, r1, r2, r3 - 30: e14103e2 smlaltt r0, r1, r2, r3 - 34: c1600281 smulbbgt r0, r1, r2 - 38: e1600281 smulbb r0, r1, r2 - 3c: e16002a1 smultb r0, r1, r2 - 40: e16002c1 smulbt r0, r1, r2 - 44: e16002e1 smultt r0, r1, r2 - 48: c12002a1 smulwbgt r0, r1, r2 - 4c: e12002a1 smulwb r0, r1, r2 - 50: e12002e1 smulwt r0, r1, r2 - 54: c1020051 qaddgt r0, r1, r2 - 58: e1020051 qadd r0, r1, r2 - 5c: e1420051 qdadd r0, r1, r2 - 60: e1220051 qsub r0, r1, r2 - 64: e1620051 qdsub r0, r1, r2 - 68: e1220051 qsub r0, r1, r2 +Disassembly of section \.text: +0+00 <[^>]+> c1003281 smlabbgt r0, r1, r2, r3 +0+04 <[^>]+> e1003281 smlabb r0, r1, r2, r3 +0+08 <[^>]+> e10032a1 smlatb r0, r1, r2, r3 +0+0c <[^>]+> e10032c1 smlabt r0, r1, r2, r3 +0+10 <[^>]+> e10032e1 smlatt r0, r1, r2, r3 +0+14 <[^>]+> c1203281 smlawbgt r0, r1, r2, r3 +0+18 <[^>]+> e1203281 smlawb r0, r1, r2, r3 +0+1c <[^>]+> e12032c1 smlawt r0, r1, r2, r3 +0+20 <[^>]+> c1410382 smlalbbgt r0, r1, r2, r3 +0+24 <[^>]+> e1410382 smlalbb r0, r1, r2, r3 +0+28 <[^>]+> e14103a2 smlaltb r0, r1, r2, r3 +0+2c <[^>]+> e14103c2 smlalbt r0, r1, r2, r3 +0+30 <[^>]+> e14103e2 smlaltt r0, r1, r2, r3 +0+34 <[^>]+> c1600281 smulbbgt r0, r1, r2 +0+38 <[^>]+> e1600281 smulbb r0, r1, r2 +0+3c <[^>]+> e16002a1 smultb r0, r1, r2 +0+40 <[^>]+> e16002c1 smulbt r0, r1, r2 +0+44 <[^>]+> e16002e1 smultt r0, r1, r2 +0+48 <[^>]+> c12002a1 smulwbgt r0, r1, r2 +0+4c <[^>]+> e12002a1 smulwb r0, r1, r2 +0+50 <[^>]+> e12002e1 smulwt r0, r1, r2 +0+54 <[^>]+> c1020051 qaddgt r0, r1, r2 +0+58 <[^>]+> e1020051 qadd r0, r1, r2 +0+5c <[^>]+> e1420051 qdadd r0, r1, r2 +0+60 <[^>]+> e1220051 qsub r0, r1, r2 +0+64 <[^>]+> e1620051 qdsub r0, r1, r2 +0+68 <[^>]+> e1220051 qsub r0, r1, r2 +0+6c <[^>]+> e1a00000 nop \(mov r0,r0\) diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/el_segundo.s binutils-2.16.91.0.2/gas/testsuite/gas/arm/el_segundo.s --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/el_segundo.s 2000-12-21 16:35:16.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/el_segundo.s 2005-07-20 12:27:27.936087030 -0700 @@ -1,23 +1,9 @@ # el_segundo.s # # Tests that we generate the right code for v5e instructions. -# This is not a functional test, although it can be linked. -# (The section at the rear is non-Coyanosa stuff for comparison.) -# To verify a compiler, do: -# /gcc/as el_segundo.s -o _temp.o -# /binutils/objdump -dr _temp.o >! _temp.d -# diff _temp.d el_segundo.d - - .section .rdata - .align 0 -.LC0: - .ascii "some data\000" - .text .global main -# .type main,function .align 0 - main: smlabbgt r0,r1,r2,r3 smlabb r0,r1,r2,r3 @@ -52,3 +38,6 @@ main: qsub r0,r1,r2 qdsub r0,r1,r2 qsub r0,r1,r2 + + @ padding for a.out's sake + nop diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/inst.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/inst.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/inst.d 2005-04-09 12:03:12.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/inst.d 2005-07-20 12:27:27.940086371 -0700 @@ -1,6 +1,8 @@ #objdump: -dr --prefix-addresses --show-raw-insn #name: ARM basic instructions #as: -mcpu=arm7m -EL +# WinCE has its own version of this test. +#skip: *-wince-* # Test the standard ARM instructions: diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/iwmmxt-bad.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/iwmmxt-bad.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/iwmmxt-bad.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/iwmmxt-bad.d 2005-07-20 12:27:27.941086206 -0700 @@ -0,0 +1,3 @@ +#name: iWMMXt errors +#as: -mcpu=iwmmxt +#error-output: iwmmxt-bad.l diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/le-fpconst.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/le-fpconst.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/le-fpconst.d 2002-02-03 11:22:32.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/le-fpconst.d 2005-07-20 12:27:27.941086206 -0700 @@ -1,6 +1,9 @@ #objdump: -s --section=.text #as: -EL #name: arm little-endian fpconst +# Not all arm targets are bi-endian, so only run this test on ones +# we know that are. FIXME We should probably also key off armeb/armel. +#target: *-*-pe .*: +file format .*arm.* diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/mapping.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/mapping.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/mapping.d 2005-04-09 12:03:12.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/mapping.d 2005-07-20 12:27:27.955083898 -0700 @@ -1,5 +1,7 @@ #objdump: --syms --special-syms #name: ARM Mapping Symbols +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* # Test the generation of ARM ELF Mapping Symbols diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/pic.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/pic.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/pic.d 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/pic.d 2005-07-20 12:27:27.965082249 -0700 @@ -1,5 +1,7 @@ #objdump: -dr --prefix-addresses --show-raw-insn #name: PIC +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* # Test generation of PIC @@ -8,7 +10,7 @@ Disassembly of section .text: 00+0 <[^>]*> eb...... bl 00+. <[^>]*> 0: R_ARM_PC24 foo.* -00+4 <[^>]*> ebfffffe bl 0[0123456789abcdef]+ <[^>]*> +00+4 <[^>]*> eb...... bl 0[0123456789abcdef]+ <[^>]*> 4: R_ARM_PLT32 foo \.\.\. 8: R_ARM_ABS32 sym diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/r15-bad.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/r15-bad.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/r15-bad.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/r15-bad.d 2005-07-20 12:27:27.965082249 -0700 @@ -0,0 +1,2 @@ +#name: Invalid use of r15 errors +#error-output: r15-bad.l diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/req.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/req.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/req.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/req.d 2005-07-20 12:27:27.966082084 -0700 @@ -0,0 +1,3 @@ +#name: .req errors +#as: -mcpu=arm7m +#error-output: req.l diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/t16-bad.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/t16-bad.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/t16-bad.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/t16-bad.d 2005-07-20 12:27:27.966082084 -0700 @@ -0,0 +1,3 @@ +#name: Valid ARM, invalid Thumb +#as: -march=armv6k +#error-output: t16-bad.l diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/thumb32.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/thumb32.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/thumb32.d 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/thumb32.d 2005-07-20 12:27:27.968081755 -0700 @@ -1,6 +1,8 @@ # name: 32-bit Thumb instructions # as: -march=armv6kt2 # objdump: -dr --prefix-addresses --show-raw-insn +# The arm-aout and arm-pe ports do not support Thumb branch relocations. +# not-target: *-*-*aout* *-*-pe .*: +file format .*arm.* diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/thumb.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/thumb.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/thumb.d 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/thumb.d 2005-07-20 12:27:27.967081919 -0700 @@ -1,6 +1,8 @@ # name: Thumb instructions # as: -mcpu=arm7t # objdump: -dr --prefix-addresses --show-raw-insn +# The arm-aout and arm-pe ports do not support Thumb branch relocations. +# not-target: *-*-*aout* *-*-pe .*: +file format .*arm.* diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/tls.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/tls.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/tls.d 2005-04-09 12:03:12.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/tls.d 2005-07-20 12:27:27.969081590 -0700 @@ -1,5 +1,9 @@ #objdump: -dr #name: TLS +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +# VxWorks needs a special variant of this file. +#skip: *-*-vxworks* # Test generation of TLS relocations diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/tls_vxworks.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/tls_vxworks.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/tls_vxworks.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/tls_vxworks.d 2005-07-20 12:27:27.969081590 -0700 @@ -0,0 +1,30 @@ +#objdump: -dr +#name: TLS +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +# This is the VxWorks variant of this file. +#source: tls.s +#not-skip: *-*-vxworks* + +# Test generation of TLS relocations + +.*: +file format .*arm.* + +Disassembly of section .text: + +00+0
: + 0: e1a00000 nop \(mov r0,r0\) + 4: e1a00000 nop \(mov r0,r0\) + 8: e1a0f00e mov pc, lr + c: 00000000 andeq r0, r0, r0 + c: R_ARM_TLS_GD32 a +# ??? The addend is appearing in both the RELA field and the +# contents. Shouldn't it be just one? bfd_install_relocation +# appears to write the addend into the contents unconditionally, +# yet somehow this does not happen for the majority of relocations. + 10: 00000004 andeq r0, r0, r4 + 10: R_ARM_TLS_LDM32 b\+0x4 + 14: 00000008 andeq r0, r0, r8 + 14: R_ARM_TLS_IE32 c\+0x8 + 18: 00000000 andeq r0, r0, r0 + 18: R_ARM_TLS_LE32 d diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/undefined_coff.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/undefined_coff.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/undefined_coff.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/undefined_coff.d 2005-07-20 12:27:27.969081590 -0700 @@ -0,0 +1,4 @@ +#name: Undefined local label error +# COFF and aout based ports use a different naming convention for local labels. +#not-skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: undefined_coff.l diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/undefined.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/undefined.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/undefined.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/undefined.d 2005-07-20 12:27:27.969081590 -0700 @@ -0,0 +1,4 @@ +#name: Undefined local label error +# COFF and aout based ports use a different naming convention for local labels. +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: undefined.l diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/unwind.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/unwind.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/unwind.d 2005-04-09 12:03:12.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/unwind.d 2005-07-20 12:27:27.970081425 -0700 @@ -1,5 +1,9 @@ #objdump: -sr #name: Unwind table generation +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +# VxWorks needs a special variant of this file. +#skip: *-*-vxworks* .*: file format.* diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/unwind_vxworks.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/unwind_vxworks.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/unwind_vxworks.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/unwind_vxworks.d 2005-07-20 12:27:27.970081425 -0700 @@ -0,0 +1,40 @@ +#objdump: -sr +#name: Unwind table generation +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +# This is the VxWorks variant of this file. +#source: unwind.s +#not-skip: *-*-vxworks* + +.*: file format.* + +RELOCATION RECORDS FOR \[.ARM.extab\]: +OFFSET TYPE VALUE +0000000c R_ARM_PREL31 .text\+0x0+c + + +RELOCATION RECORDS FOR \[.ARM.exidx\]: +OFFSET TYPE VALUE +00000000 R_ARM_PREL31 .text +00000000 R_ARM_NONE __aeabi_unwind_cpp_pr0 +00000008 R_ARM_PREL31 .text.* +00000008 R_ARM_NONE __aeabi_unwind_cpp_pr1\+0x0+8 +0000000c R_ARM_PREL31 .ARM.extab\+0x0+c +00000010 R_ARM_PREL31 .text.* +00000014 R_ARM_PREL31 .ARM.extab.* +00000018 R_ARM_PREL31 .text.* +0000001c R_ARM_PREL31 .ARM.extab.* +00000020 R_ARM_PREL31 .text.* + + +Contents of section .text: + 0000 (0000a0e3 0100a0e3 0200a0e3 0300a0e3|e3a00000 e3a00001 e3a00002 e3a00003) .* + 0010 (0420|2004) .* +Contents of section .ARM.extab: + 0000 (449b0181 b0b08086|81019b44 8680b0b0) 00000000 00000000 .* + 0010 (8402b101 b0b0b005 2a000000 00c60181|01b10284 05b0b0b0 0000002a 8101c600) .* + 0020 (b0b0c1c1|c1c1b0b0) 00000000 .* +Contents of section .ARM.exidx: + 0000 00000000 (b0b0a880 00000000|80a8b0b0 00000000) 00000000 .* + 0010 00000000 00000000 00000000 00000000 .* + 0020 (00000000 08849780|00000000 80978408) .* diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/vfp1xD.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/vfp1xD.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/vfp1xD.d 2004-01-14 13:07:46.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/vfp1xD.d 2005-07-20 12:27:27.989078292 -0700 @@ -82,16 +82,16 @@ Disassembly of section .text: 0+120 <[^>]*> eeb11a40 fnegs s2, s0 0+124 <[^>]*> eef1fa40 fnegs s31, s0 0+128 <[^>]*> eeb16a6a fnegs s12, s21 -0+12c <[^>]*> ee300a20 fadds s0, s0, s0 -0+130 <[^>]*> ee300a01 fadds s0, s0, s0 -0+134 <[^>]*> ee300a2f fadds s0, s0, s0 +0+12c <[^>]*> ee300a20 fadds s0, s0, s1 +0+130 <[^>]*> ee300a01 fadds s0, s0, s2 +0+134 <[^>]*> ee300a2f fadds s0, s0, s31 0+138 <[^>]*> ee300a80 fadds s0, s1, s0 0+13c <[^>]*> ee310a00 fadds s0, s2, s0 0+140 <[^>]*> ee3f0a80 fadds s0, s31, s0 -0+144 <[^>]*> ee700a00 fadds s1, s0, s1 -0+148 <[^>]*> ee301a00 fadds s2, s0, s2 -0+14c <[^>]*> ee70fa00 fadds s31, s0, s31 -0+150 <[^>]*> ee3a6aa2 fadds s12, s21, s12 +0+144 <[^>]*> ee700a00 fadds s1, s0, s0 +0+148 <[^>]*> ee301a00 fadds s2, s0, s0 +0+14c <[^>]*> ee70fa00 fadds s31, s0, s0 +0+150 <[^>]*> ee3a6aa2 fadds s12, s21, s5 0+154 <[^>]*> eeb80ae0 fsitos s0, s1 0+158 <[^>]*> eeb80ac1 fsitos s0, s2 0+15c <[^>]*> eeb80aef fsitos s0, s31 @@ -194,7 +194,7 @@ Disassembly of section .text: 0+2e0 <[^>]*> 0ef0fa69 fcpyseq s31, s19 0+2e4 <[^>]*> 0eb1aa44 fnegseq s20, s8 0+2e8 <[^>]*> 0ef12ae3 fsqrtseq s5, s7 -0+2ec <[^>]*> 0e323a82 faddseq s6, s5, s6 +0+2ec <[^>]*> 0e323a82 faddseq s6, s5, s4 0+2f0 <[^>]*> 0ec11a20 fdivseq s3, s2, s1 0+2f4 <[^>]*> 0e4ffa2e fmacseq s31, s30, s29 0+2f8 <[^>]*> 0e1dea8d fmscseq s28, s27, s26 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/vfp-bad.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/vfp-bad.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/vfp-bad.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/vfp-bad.d 2005-07-20 12:27:27.970081425 -0700 @@ -0,0 +1,3 @@ +#name: VFP errors +#as: -mfpu=vfp +#error-output: vfp-bad.l diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/wince_arm7t.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/wince_arm7t.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/wince_arm7t.d 2004-01-14 13:07:46.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/wince_arm7t.d 1969-12-31 16:00:00.000000000 -0800 @@ -1,75 +0,0 @@ -#objdump: -Dr --prefix-addresses --show-raw-insn -#name: ARM arm7t (WinCE version) -#as: -mcpu=arm7t -EL -#source: arm7t.s - -# This file is the same as arm7t.d except that the PC-relative -# LDR[S]H instructions have not had a -8 bias inserted. - - -# Test the halfword and signextend memory transfers: - -.*: +file format .*arm.* - -Disassembly of section .text: -0+00 <[^>]*> e1d100b0 ? ldrh r0, \[r1\] -0+04 <[^>]*> e1f100b0 ? ldrh r0, \[r1\]! -0+08 <[^>]*> e19100b2 ? ldrh r0, \[r1, r2\] -0+0c <[^>]*> e1b100b2 ? ldrh r0, \[r1, r2\]! -0+10 <[^>]*> e1d100bc ? ldrh r0, \[r1, #12\] -0+14 <[^>]*> e1f100bc ? ldrh r0, \[r1, #12\]! -0+18 <[^>]*> e15100bc ? ldrh r0, \[r1, #-12\] -0+1c <[^>]*> e09100b2 ? ldrh r0, \[r1\], r2 -0+20 <[^>]*> e3a00cff ? mov r0, #65280 ; 0xff00 -0+24 <[^>]*> e1df0abc ? ldrh r0, \[pc, #172\] ; 0+d8 <[^>]*> -0+28 <[^>]*> e1df0abc ? ldrh r0, \[pc, #172\] ; 0+dc <[^>]*> -0+2c <[^>]*> e1c100b0 ? strh r0, \[r1\] -0+30 <[^>]*> e1e100b0 ? strh r0, \[r1\]! -0+34 <[^>]*> e18100b2 ? strh r0, \[r1, r2\] -0+38 <[^>]*> e1a100b2 ? strh r0, \[r1, r2\]! -0+3c <[^>]*> e1c100bc ? strh r0, \[r1, #12\] -0+40 <[^>]*> e1e100bc ? strh r0, \[r1, #12\]! -0+44 <[^>]*> e14100bc ? strh r0, \[r1, #-12\] -0+48 <[^>]*> e08100b2 ? strh r0, \[r1\], r2 -0+4c <[^>]*> e1cf08b8 ? strh r0, \[pc, #136\] ; 0+dc <[^>]*> -0+50 <[^>]*> e1d100d0 ? ldrsb r0, \[r1\] -0+54 <[^>]*> e1f100d0 ? ldrsb r0, \[r1\]! -0+58 <[^>]*> e19100d2 ? ldrsb r0, \[r1, r2\] -0+5c <[^>]*> e1b100d2 ? ldrsb r0, \[r1, r2\]! -0+60 <[^>]*> e1d100dc ? ldrsb r0, \[r1, #12\] -0+64 <[^>]*> e1f100dc ? ldrsb r0, \[r1, #12\]! -0+68 <[^>]*> e15100dc ? ldrsb r0, \[r1, #-12\] -0+6c <[^>]*> e09100d2 ? ldrsb r0, \[r1\], r2 -0+70 <[^>]*> e3a000de ? mov r0, #222 ; 0xde -0+74 <[^>]*> e1df06d0 ? ldrsb r0, \[pc, #96\] ; 0+dc <[^>]*> -0+78 <[^>]*> e1d100f0 ? ldrsh r0, \[r1\] -0+7c <[^>]*> e1f100f0 ? ldrsh r0, \[r1\]! -0+80 <[^>]*> e19100f2 ? ldrsh r0, \[r1, r2\] -0+84 <[^>]*> e1b100f2 ? ldrsh r0, \[r1, r2\]! -0+88 <[^>]*> e1d100fc ? ldrsh r0, \[r1, #12\] -0+8c <[^>]*> e1f100fc ? ldrsh r0, \[r1, #12\]! -0+90 <[^>]*> e15100fc ? ldrsh r0, \[r1, #-12\] -0+94 <[^>]*> e09100f2 ? ldrsh r0, \[r1\], r2 -0+98 <[^>]*> e3a00cff ? mov r0, #65280 ; 0xff00 -0+9c <[^>]*> e1df03f4 ? ldrsh r0, \[pc, #52\] ; 0+d8 <[^>]*> -0+a0 <[^>]*> e1df03f4 ? ldrsh r0, \[pc, #52\] ; 0+dc <[^>]*> -0+a4 <[^>]*> e19100b2 ? ldrh r0, \[r1, r2\] -0+a8 <[^>]*> 119100b2 ? ldrneh r0, \[r1, r2\] -0+ac <[^>]*> 819100b2 ? ldrhih r0, \[r1, r2\] -0+b0 <[^>]*> b19100b2 ? ldrlth r0, \[r1, r2\] -0+b4 <[^>]*> e19100f2 ? ldrsh r0, \[r1, r2\] -0+b8 <[^>]*> 119100f2 ? ldrnesh r0, \[r1, r2\] -0+bc <[^>]*> 819100f2 ? ldrhish r0, \[r1, r2\] -0+c0 <[^>]*> b19100f2 ? ldrltsh r0, \[r1, r2\] -0+c4 <[^>]*> e19100d2 ? ldrsb r0, \[r1, r2\] -0+c8 <[^>]*> 119100d2 ? ldrnesb r0, \[r1, r2\] -0+cc <[^>]*> 819100d2 ? ldrhisb r0, \[r1, r2\] -0+d0 <[^>]*> b19100d2 ? ldrltsb r0, \[r1, r2\] -0+d4 <[^>]*> e15f00f4 ? ldrsh r0, \[pc, #-4\] ; 0+d8 <[^>]*> -0+d8 <[^>]*> e15f00f4 ? ldrsh r0, \[pc, #-4\] ; 0+dc <[^>]*> -0+dc <[^>]*> 00000000 ? andeq r0, r0, r0 -[ ]*dc:.*fred -0+e0 <[^>]*> 0000c0de ? .* -0+e4 <[^>]*> 0000dead ? .* -0+e8 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) -0+ec <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/wince_copro.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/wince_copro.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/wince_copro.d 2004-01-14 13:07:46.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/wince_copro.d 1969-12-31 16:00:00.000000000 -0800 @@ -1,45 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn --architecture=armv5te -#name: ARM CoProcessor Instructions (WinCE version) -#as: -march=armv5te -EL -#source: copro.s - -# This file is the same as copro.d except that the PC-relative -# LDC and STFS instructions have not had a -8 bias inserted. - -# Test the standard ARM co-processor instructions: - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]*> ee421103 dvfs f1, f2, f3 -0+004 <[^>]*> 0e3414a5 cfadddeq mvd1, mvd4, mvd5 -0+008 <[^>]*> ed939500 cfldr32 mvfx9, \[r3\] -0+00c <[^>]*> edd1e108 ldfp f6, \[r1, #32\] -0+010 <[^>]*> 4db200ff ldcmi 0, cr0, \[r2, #1020\]! -0+014 <[^>]*> 5cf31710 ldcpll 7, cr1, \[r3\], #64 -0+018 <[^>]*> ed1f8003 ldc 0, cr8, \[pc, #-12\] -0+01c <[^>]*> ed830500 cfstr32 mvfx0, \[r3\] -0+020 <[^>]*> edc0f302 stcl 3, cr15, \[r0, #8\] -0+024 <[^>]*> 0da2c419 cfstrseq mvf12, \[r2, #100\]! -0+028 <[^>]*> 3ca4860c stccc 6, cr8, \[r4\], #48 -0+02c <[^>]*> ed0f7103 stfs f7, \[pc, #-12\] -0+030 <[^>]*> ee715212 mrc 2, 3, r5, cr1, cr2, \{0\} -0+034 <[^>]*> aeb1f4f2 mrcge 4, 5, pc, cr1, cr2, \{7\} -0+038 <[^>]*> ee21f711 mcr 7, 1, pc, cr1, cr1, \{0\} -0+03c <[^>]*> be228519 cfsh64lt mvdx8, mvdx2, #9 -0+040 <[^>]*> ec907300 ldc 3, cr7, \[r0\], \{0\} -0+044 <[^>]*> ec816e01 stc 14, cr6, \[r1\], \{1\} -0+048 <[^>]*> fc925502 ldc2 5, cr5, \[r2\], \{2\} -0+04c <[^>]*> fc834603 stc2 6, cr4, \[r3\], \{3\} -0+050 <[^>]*> ecd43704 ldcl 7, cr3, \[r4\], \{4\} -0+054 <[^>]*> ecc52805 stcl 8, cr2, \[r5\], \{5\} -0+058 <[^>]*> fcd61906 ldc2l 9, cr1, \[r6\], \{6\} -0+05c <[^>]*> fcc70a07 stc2l 10, cr0, \[r7\], \{7\} -0+060 <[^>]*> ecd88bff ldcl 11, cr8, \[r8\], \{255\} -0+064 <[^>]*> ecc99cfe stcl 12, cr9, \[r9\], \{254\} -0+068 <[^>]*> ec507d04 mrrc 13, 0, r7, r0, cr4 -0+06c <[^>]*> ec407e05 mcrr 14, 0, r7, r0, cr5 -0+070 <[^>]*> ec507fff mrrc 15, 15, r7, r0, cr15 -0+074 <[^>]*> ec407efe mcrr 14, 15, r7, r0, cr14 -0+078 <[^>]*> e1a00000 nop \(mov r0,r0\) -0+07c <[^>]*> e1a00000 nop \(mov r0,r0\) diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/wince_inst.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/wince_inst.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/wince_inst.d 2004-01-14 13:07:46.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/wince_inst.d 2005-07-20 12:27:27.991077962 -0700 @@ -2,6 +2,8 @@ #name: ARM basic instructions (WinCE version) #as: -mcpu=arm7m -EL #source: inst.s +# inst.d is used for non-WinCE targets. +#not-skip: *-wince-* # This file is the same as inst.d except that the BL # instructions have not had a -8 bias inserted. diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/arm/wince_ldconst.d binutils-2.16.91.0.2/gas/testsuite/gas/arm/wince_ldconst.d --- binutils-2.16.91.0.1/gas/testsuite/gas/arm/wince_ldconst.d 2004-01-14 13:07:46.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/arm/wince_ldconst.d 1969-12-31 16:00:00.000000000 -0800 @@ -1,31 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: ARM ldr with immediate constant (WinCE version) -#as: -mcpu=arm7m -EL -#source: ldconst.s - -# This file is the same as ldconst.d except that the PC- -# relative LDR instructions have not had a -8 bias inserted. - -.*: +file format .*arm.* - -Disassembly of section .text: -0+00 <[^>]*> e3a00000 ? mov r0, #0 ; 0x0 -0+04 <[^>]*> e3a004ff ? mov r0, #-16777216 ; 0xff000000 -0+08 <[^>]*> e3e00000 ? mvn r0, #0 ; 0x0 -0+0c <[^>]*> e51f000c ? ldr r0, \[pc, #-12\] ; 0+08 <[^>]*> -0+10 <[^>]*> 0fff0000 ? .* -0+14 <[^>]*> e3a0e000 ? mov lr, #0 ; 0x0 -0+18 <[^>]*> e3a0e8ff ? mov lr, #16711680 ; 0xff0000 -0+1c <[^>]*> e3e0e8ff ? mvn lr, #16711680 ; 0xff0000 -0+20 <[^>]*> e51fe00c ? ldr lr, \[pc, #-12\] ; 0+1c <[^>]*> -0+24 <[^>]*> 00fff000 ? .* -0+28 <[^>]*> 03a00000 ? moveq r0, #0 ; 0x0 -0+2c <[^>]*> 03a00cff ? moveq r0, #65280 ; 0xff00 -0+30 <[^>]*> 03e00cff ? mvneq r0, #65280 ; 0xff00 -0+34 <[^>]*> 051f000c ? ldreq r0, \[pc, #-12\] ; 0+30 <[^>]*> -0+38 <[^>]*> 000fff00 ? .* -0+3c <[^>]*> 43a0b000 ? movmi fp, #0 ; 0x0 -0+40 <[^>]*> 43a0b0ff ? movmi fp, #255 ; 0xff -0+44 <[^>]*> 43e0b0ff ? mvnmi fp, #255 ; 0xff -0+48 <[^>]*> 451fb00c ? ldrmi fp, \[pc, #-12\] ; 0+44 <[^>]*> -0+4c <[^>]*> 0000fff0 ? .* diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/cris/rd-abs32-1.d binutils-2.16.91.0.2/gas/testsuite/gas/cris/rd-abs32-1.d --- binutils-2.16.91.0.1/gas/testsuite/gas/cris/rd-abs32-1.d 2004-11-22 12:33:32.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/cris/rd-abs32-1.d 2005-07-20 12:27:27.994077468 -0700 @@ -16,9 +16,9 @@ Disassembly of section \.text: 2: 0f05 nop 4: 3f0d 0200 0000 jump 2 6: R_CRIS_32 \.text\+0x2 - a: 3f0d 0200 0000 jump 2 + a: 3f0d 0000 0000 jump 0 c: R_CRIS_32 locsym2 - 10: 3f0d 7400 0000 jump 74 + 10: 3f0d 0000 0000 jump 0 12: R_CRIS_32 locsym3 16: 3f0d 7400 0000 jump 74 18: R_CRIS_32 \.text\+0x74 @@ -26,9 +26,9 @@ Disassembly of section \.text: 1e: R_CRIS_32 extsym 22: 3fbd 0200 0000 jsr 2 24: R_CRIS_32 \.text\+0x2 - 28: 3fbd 0200 0000 jsr 2 + 28: 3fbd 0000 0000 jsr 0 2a: R_CRIS_32 locsym2 - 2e: 3fbd 7400 0000 jsr 74 + 2e: 3fbd 0000 0000 jsr 0 30: R_CRIS_32 locsym3 34: 3fbd 7400 0000 jsr 74 36: R_CRIS_32 \.text\+0x74 @@ -38,11 +38,11 @@ Disassembly of section \.text: 42: R_CRIS_32 \.text\+0x2 46: 0000 bcc \.\+2 48: 0000 bcc \.\+2 - 4a: 3f3d 0200 0000 jsrc 2 + 4a: 3f3d 0000 0000 jsrc 0 4c: R_CRIS_32 locsym2 50: 0000 bcc \.\+2 52: 0000 bcc \.\+2 - 54: 3f3d 7400 0000 jsrc 74 + 54: 3f3d 0000 0000 jsrc 0 56: R_CRIS_32 locsym3 5a: 0000 bcc \.\+2 5c: 0000 bcc \.\+2 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/cris/rd-pic-2.d binutils-2.16.91.0.2/gas/testsuite/gas/cris/rd-pic-2.d --- binutils-2.16.91.0.1/gas/testsuite/gas/cris/rd-pic-2.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/cris/rd-pic-2.d 2005-07-20 12:27:27.995077303 -0700 @@ -0,0 +1,19 @@ +#objdump: -dr +#as: --em=criself --pic + +# Check that 16-bit PIC relocs aren't overflowing. +# PR gas/1049. + +.*: file format .*-cris + +Disassembly of section \.text: +0+ : + 0: 7f9c 0000 movs\.w 0,r9 + 2: R_CRIS_16_GOT y + 4: 7f9c 0000 movs\.w 0,r9 + 6: R_CRIS_16_GOTPLT z + \.\.\. +0+10008 : + 10008: 0f05 nop +0+1000a : + \.\.\. diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/cris/rd-pic-2.s binutils-2.16.91.0.2/gas/testsuite/gas/cris/rd-pic-2.s --- binutils-2.16.91.0.1/gas/testsuite/gas/cris/rd-pic-2.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/cris/rd-pic-2.s 2005-07-20 12:27:27.995077303 -0700 @@ -0,0 +1,11 @@ +; GAS mustn't error on the larger-than-16-bit offsets here. + + .global y + .global z +a: + movs.w y:GOT16,$r9 + movs.w z:GOTPLT16,$r9 + .space 65536,0 +y: + nop +z: diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/crx/gas-segfault.d binutils-2.16.91.0.2/gas/testsuite/gas/crx/gas-segfault.d --- binutils-2.16.91.0.1/gas/testsuite/gas/crx/gas-segfault.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/crx/gas-segfault.d 2005-07-20 12:27:27.995077303 -0700 @@ -0,0 +1,17 @@ +#as: +#objdump: -dr +#name: GAS segmentation fault + +.*: +file format .* + +Disassembly of section .text: + +00000000 <__Z1flllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllc>: + 0: ee ba jump r14 + ... + +00000004 <_main>: + 4: 6f 34 00 40 push r15, {r14} + 8: 7e 30 00 00 bal r14, 0x8 <_main\+0x4> + 8: R_CRX_REL16 __Z1flllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllc + c: 6f 32 00 40 popret r15, {r14} diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/crx/gas-segfault.s binutils-2.16.91.0.2/gas/testsuite/gas/crx/gas-segfault.s --- binutils-2.16.91.0.1/gas/testsuite/gas/crx/gas-segfault.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/crx/gas-segfault.s 2005-07-20 12:27:27.996077138 -0700 @@ -0,0 +1,20 @@ + # PR 1063 + # This source file used to make GAS crash with a seg fault + .section .text + .align 4 + .globl __Z1flllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllc + .type __Z1flllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllc,@function +__Z1flllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllc: + jump ra + + .size __Z1flllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllc,.-__Z1flllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllc + .align 4 + .globl _main + .type _main, @function +_main: + push sp, { ra } + bal ra, __Z1flllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllc + popret sp, { ra } + .size _main, .-_main + + diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/hppa/basic/fp_comp.s binutils-2.16.91.0.2/gas/testsuite/gas/hppa/basic/fp_comp.s --- binutils-2.16.91.0.1/gas/testsuite/gas/hppa/basic/fp_comp.s 1999-08-31 10:12:29.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/hppa/basic/fp_comp.s 2005-07-20 12:27:28.003075984 -0700 @@ -1,3 +1,4 @@ + .level 1.1 .code .align 4 ; Basic immediate instruction tests. diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/hppa/basic/special.s binutils-2.16.91.0.2/gas/testsuite/gas/hppa/basic/special.s --- binutils-2.16.91.0.1/gas/testsuite/gas/hppa/basic/special.s 1999-08-31 10:12:29.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/hppa/basic/special.s 2005-07-20 12:27:28.004075819 -0700 @@ -1,3 +1,4 @@ + .level 1.1 .code .align 4 gfw %r4(%sr0,%r5) diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/hppa/basic/system.s binutils-2.16.91.0.2/gas/testsuite/gas/hppa/basic/system.s --- binutils-2.16.91.0.1/gas/testsuite/gas/hppa/basic/system.s 1999-08-31 10:12:29.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/hppa/basic/system.s 2005-07-20 12:27:28.004075819 -0700 @@ -1,3 +1,4 @@ + .level 1.1 .code .align 4 ; Basic immediate instruction tests. diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/i386/i386.exp binutils-2.16.91.0.2/gas/testsuite/gas/i386/i386.exp --- binutils-2.16.91.0.1/gas/testsuite/gas/i386/i386.exp 2005-05-10 15:46:46.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/i386/i386.exp 2005-07-20 12:27:28.008075160 -0700 @@ -60,6 +60,8 @@ if [expr ([istarget "i*86-*-*"] || [ist run_dump_test "sub" run_dump_test "prescott" run_dump_test "sib" + run_dump_test "vmx" + run_dump_test "suffix" if {![istarget "*-*-aix*"] && (![is_elf_format] || [istarget "*-*-linux*"] @@ -74,6 +76,7 @@ if [expr ([istarget "i*86-*-*"] || [ist run_dump_test "padlock" run_dump_test "crx" run_list_test "cr-err" "" + run_dump_test "svme" # These tests require support for 8 and 16 bit relocs, # so we only run them for ELF and COFF targets. @@ -101,6 +104,8 @@ if [expr ([istarget "i*86-*-*"] || [ist run_dump_test "tlspic" run_dump_test "tlsnopic" run_dump_test "bss" + run_dump_test "reloc32" + run_list_test "reloc32" "--defsym _bad_=1" } # This is a PE specific test. @@ -128,6 +133,8 @@ if [expr ([istarget "i*86-*-*"] || [ista run_list_test "x86-64-segment" "-al" run_list_test "x86-64-inval-seg" "-al" run_dump_test "x86-64-branch" + run_dump_test "svme64" + run_dump_test "x86-64-vmx" # For ELF targets verify that @unwind works. if { ([istarget "*-*-elf*"] || [istarget "*-*-linux*"] @@ -137,5 +144,11 @@ if [expr ([istarget "i*86-*-*"] || [ista run_dump_test "x86-64-unwind" } + # ELF specific tests + if [is_elf_format] then { + run_dump_test "reloc64" + run_list_test "reloc64" "--defsym _bad_=1" + } + set ASFLAGS "$old_ASFLAGS" } diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/i386/reloc32.d binutils-2.16.91.0.2/gas/testsuite/gas/i386/reloc32.d --- binutils-2.16.91.0.1/gas/testsuite/gas/i386/reloc32.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/i386/reloc32.d 2005-07-20 12:27:28.009074995 -0700 @@ -0,0 +1,67 @@ +#objdump: -Drw +#name: i386 relocs + +.*: +file format .*i386.* + +Disassembly of section \.text: +#... +.*[ ]+R_386_32[ ]+xtrn +.*[ ]+R_386_16[ ]+xtrn +.*[ ]+R_386_8[ ]+xtrn +.*[ ]+R_386_32[ ]+xtrn +.*[ ]+R_386_16[ ]+xtrn +.*[ ]+R_386_PC32[ ]+xtrn +.*[ ]+R_386_PC16[ ]+xtrn +.*[ ]+R_386_PC8[ ]+xtrn +.*[ ]+R_386_PC32[ ]+xtrn +.*[ ]+R_386_PC16[ ]+xtrn +.*[ ]+R_386_PC32[ ]+xtrn +.*[ ]+R_386_PC8[ ]+xtrn +.*[ ]+R_386_GOT32[ ]+xtrn +.*[ ]+R_386_GOT32[ ]+xtrn +.*[ ]+R_386_GOTOFF[ ]+xtrn +.*[ ]+R_386_GOTOFF[ ]+xtrn +.*[ ]+R_386_GOTPC[ ]+_GLOBAL_OFFSET_TABLE_ +.*[ ]+R_386_GOTPC[ ]+_GLOBAL_OFFSET_TABLE_ +.*[ ]+R_386_PLT32[ ]+xtrn +.*[ ]+R_386_PLT32[ ]+xtrn +.*[ ]+R_386_PLT32[ ]+xtrn +.*[ ]+R_386_TLS_GD[ ]+xtrn +.*[ ]+R_386_TLS_GD[ ]+xtrn +.*[ ]+R_386_TLS_GOTIE[ ]+xtrn +.*[ ]+R_386_TLS_GOTIE[ ]+xtrn +.*[ ]+R_386_TLS_IE[ ]+xtrn +.*[ ]+R_386_TLS_IE[ ]+xtrn +.*[ ]+R_386_TLS_IE_32[ ]+xtrn +.*[ ]+R_386_TLS_IE_32[ ]+xtrn +.*[ ]+R_386_TLS_LDM[ ]+xtrn +.*[ ]+R_386_TLS_LDM[ ]+xtrn +.*[ ]+R_386_TLS_LDO_32[ ]+xtrn +.*[ ]+R_386_TLS_LDO_32[ ]+xtrn +.*[ ]+R_386_TLS_LE[ ]+xtrn +.*[ ]+R_386_TLS_LE[ ]+xtrn +.*[ ]+R_386_TLS_LE_32[ ]+xtrn +.*[ ]+R_386_TLS_LE_32[ ]+xtrn +Disassembly of section \.data: +#... +.*[ ]+R_386_32[ ]+xtrn +.*[ ]+R_386_PC32[ ]+xtrn +.*[ ]+R_386_GOT32[ ]+xtrn +.*[ ]+R_386_GOTOFF[ ]+xtrn +.*[ ]+R_386_GOTPC[ ]+_GLOBAL_OFFSET_TABLE_ +.*[ ]+R_386_GOTPC[ ]+_GLOBAL_OFFSET_TABLE_ +.*[ ]+R_386_PLT32[ ]+xtrn +#... +.*[ ]+R_386_TLS_GD[ ]+xtrn +#... +.*[ ]+R_386_TLS_GOTIE[ ]+xtrn +.*[ ]+R_386_TLS_IE[ ]+xtrn +.*[ ]+R_386_TLS_IE_32[ ]+xtrn +.*[ ]+R_386_TLS_LDM[ ]+xtrn +.*[ ]+R_386_TLS_LDO_32[ ]+xtrn +.*[ ]+R_386_TLS_LE[ ]+xtrn +.*[ ]+R_386_TLS_LE_32[ ]+xtrn +.*[ ]+R_386_16[ ]+xtrn +.*[ ]+R_386_PC16[ ]+xtrn +.*[ ]+R_386_8[ ]+xtrn +.*[ ]+R_386_PC8[ ]+xtrn diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/i386/reloc32.l binutils-2.16.91.0.2/gas/testsuite/gas/i386/reloc32.l --- binutils-2.16.91.0.1/gas/testsuite/gas/i386/reloc32.l 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/i386/reloc32.l 2005-07-20 12:27:28.009074995 -0700 @@ -0,0 +1,67 @@ +.*: Assembler messages: +.*:30: Error: .* +.*:31: Error: .* +.*:33: Error: .* +.*:34: Error: .* +.*:37: Error: .* +.*:38: Error: .* +.*:40: Error: .* +.*:41: Error: .* +.*:51: Error: .* +.*:52: Error: .* +.*:54: Error: .* +.*:56: Error: .* +.*:59: Error: .* +.*:60: Error: .* +.*:62: Error: .* +.*:63: Error: .* +.*:66: Error: .* +.*:67: Error: .* +.*:69: Error: .* +.*:70: Error: .* +.*:73: Error: .* +.*:74: Error: .* +.*:76: Error: .* +.*:77: Error: .* +.*:80: Error: .* +.*:81: Error: .* +.*:83: Error: .* +.*:84: Error: .* +.*:87: Error: .* +.*:88: Error: .* +.*:90: Error: .* +.*:91: Error: .* +.*:94: Error: .* +.*:95: Error: .* +.*:97: Error: .* +.*:98: Error: .* +.*:101: Error: .* +.*:102: Error: .* +.*:104: Error: .* +.*:105: Error: .* +.*:108: Error: .* +.*:109: Error: .* +.*:111: Error: .* +.*:112: Error: .* +.*:133: Error: .* +.*:134: Error: .* +.*:137: Error: .* +.*:138: Error: .* +.*:139: Error: .* +.*:140: Error: .* +.*:141: Error: .* +.*:142: Error: .* +.*:143: Error: .* +.*:144: Error: .* +.*:145: Error: .* +.*:149: Error: .* +.*:150: Error: .* +.*:153: Error: .* +.*:154: Error: .* +.*:155: Error: .* +.*:156: Error: .* +.*:157: Error: .* +.*:158: Error: .* +.*:159: Error: .* +.*:160: Error: .* +.*:161: Error: .* diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/i386/reloc32.s binutils-2.16.91.0.2/gas/testsuite/gas/i386/reloc32.s --- binutils-2.16.91.0.1/gas/testsuite/gas/i386/reloc32.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/i386/reloc32.s 2005-07-20 12:27:28.009074995 -0700 @@ -0,0 +1,161 @@ + .macro bad args:vararg + .ifdef _bad_ + \args + .endif + .endm + + .macro ill args:vararg + # This is used to mark entries that aren't handled consistently, + # and thus shouldn't currently be checked for. + # \args + .endm + + .text +_start: + mov $xtrn, %eax + mov $xtrn, %ax + mov $xtrn, %al + mov xtrn(%ebx), %eax + mov xtrn(%bx), %eax + + mov $(xtrn - .), %eax + mov $(xtrn - .), %ax + mov $(xtrn - .), %al + mov xtrn - .(%ebx), %eax + mov xtrn - .(%bx), %eax + call xtrn + jecxz xtrn + + mov $xtrn@got, %eax +bad mov $xtrn@got, %ax +bad mov $xtrn@got, %al + mov xtrn@got(%ebx), %eax +bad mov xtrn@got(%bx), %eax +bad call xtrn@got + + mov $xtrn@gotoff, %eax +bad mov $xtrn@gotoff, %ax +bad mov $xtrn@gotoff, %al + mov xtrn@gotoff(%ebx), %eax +bad mov xtrn@gotoff(%bx), %eax +bad call xtrn@gotoff + + add $_GLOBAL_OFFSET_TABLE_, %eax +ill add $_GLOBAL_OFFSET_TABLE_, %ax +ill add $_GLOBAL_OFFSET_TABLE_, %al + add $(_GLOBAL_OFFSET_TABLE_ - .), %eax +ill add $(_GLOBAL_OFFSET_TABLE_ - .), %ax +ill add $(_GLOBAL_OFFSET_TABLE_ - .), %al + + mov $xtrn@plt, %eax +bad mov $xtrn@plt, %ax +bad mov $xtrn@plt, %al + mov xtrn@plt(%ebx), %eax +bad mov xtrn@plt(%bx), %eax + call xtrn@plt +bad jecxz xtrn@plt + + mov $xtrn@tlsgd, %eax +bad mov $xtrn@tlsgd, %ax +bad mov $xtrn@tlsgd, %al + mov xtrn@tlsgd(%ebx), %eax +bad mov xtrn@tlsgd(%bx), %eax +bad call xtrn@tlsgd + + mov $xtrn@gotntpoff, %eax +bad mov $xtrn@gotntpoff, %ax +bad mov $xtrn@gotntpoff, %al + mov xtrn@gotntpoff(%ebx), %eax +bad mov xtrn@gotntpoff(%bx), %eax +bad call xtrn@gotntpoff + + mov $xtrn@indntpoff, %eax +bad mov $xtrn@indntpoff, %ax +bad mov $xtrn@indntpoff, %al + mov xtrn@indntpoff(%ebx), %eax +bad mov xtrn@indntpoff(%bx), %eax +bad call xtrn@indntpoff + + mov $xtrn@gottpoff, %eax +bad mov $xtrn@gottpoff, %ax +bad mov $xtrn@gottpoff, %al + mov xtrn@gottpoff(%ebx), %eax +bad mov xtrn@gottpoff(%bx), %eax +bad call xtrn@gottpoff + + mov $xtrn@tlsldm, %eax +bad mov $xtrn@tlsldm, %ax +bad mov $xtrn@tlsldm, %al + mov xtrn@tlsldm(%ebx), %eax +bad mov xtrn@tlsldm(%bx), %eax +bad call xtrn@tlsldm + + mov $xtrn@dtpoff, %eax +bad mov $xtrn@dtpoff, %ax +bad mov $xtrn@dtpoff, %al + mov xtrn@dtpoff(%ebx), %eax +bad mov xtrn@dtpoff(%bx), %eax +bad call xtrn@dtpoff + + mov $xtrn@ntpoff, %eax +bad mov $xtrn@ntpoff, %ax +bad mov $xtrn@ntpoff, %al + mov xtrn@ntpoff(%ebx), %eax +bad mov xtrn@ntpoff(%bx), %eax +bad call xtrn@ntpoff + + mov $xtrn@tpoff, %eax +bad mov $xtrn@tpoff, %ax +bad mov $xtrn@tpoff, %al + mov xtrn@tpoff(%ebx), %eax +bad mov xtrn@tpoff(%bx), %eax +bad call xtrn@tpoff + + .data + .long xtrn + .long xtrn - . + .long xtrn@got + .long xtrn@gotoff + .long _GLOBAL_OFFSET_TABLE_ + .long _GLOBAL_OFFSET_TABLE_ - . + .long xtrn@plt + .long xtrn@tlsgd + .long xtrn@gotntpoff + .long xtrn@indntpoff + .long xtrn@gottpoff + .long xtrn@tlsldm + .long xtrn@dtpoff + .long xtrn@ntpoff + .long xtrn@tpoff + + .word xtrn + .word xtrn - . +bad .word xtrn@got +bad .word xtrn@gotoff +ill .word _GLOBAL_OFFSET_TABLE_ +ill .word _GLOBAL_OFFSET_TABLE_ - . +bad .word xtrn@plt +bad .word xtrn@tlsgd +bad .word xtrn@gotntpoff +bad .word xtrn@indntpoff +bad .word xtrn@gottpoff +bad .word xtrn@tlsldm +bad .word xtrn@dtpoff +bad .word xtrn@ntpoff +bad .word xtrn@tpoff + + .byte xtrn + .byte xtrn - . +bad .byte xtrn@got +bad .byte xtrn@gotoff +ill .byte _GLOBAL_OFFSET_TABLE_ +ill .byte _GLOBAL_OFFSET_TABLE_ - . +bad .byte xtrn@plt +bad .byte xtrn@tlsgd +bad .byte xtrn@gotntpoff +bad .byte xtrn@indntpoff +bad .byte xtrn@gottpoff +bad .byte xtrn@tlsldm +bad .byte xtrn@dtpoff +bad .byte xtrn@ntpoff +bad .byte xtrn@tpoff diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/i386/reloc64.d binutils-2.16.91.0.2/gas/testsuite/gas/i386/reloc64.d --- binutils-2.16.91.0.1/gas/testsuite/gas/i386/reloc64.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/i386/reloc64.d 2005-07-20 12:27:28.010074830 -0700 @@ -0,0 +1,71 @@ +#objdump: -Drw +#name: x86-64 relocs + +.*: +file format .*x86-64.* + +Disassembly of section \.text: +#... +.*[ ]+R_X86_64_64[ ]+xtrn +.*[ ]+R_X86_64_32S[ ]+xtrn +.*[ ]+R_X86_64_32[ ]+xtrn +.*[ ]+R_X86_64_16[ ]+xtrn +.*[ ]+R_X86_64_8[ ]+xtrn +.*[ ]+R_X86_64_32S[ ]+xtrn +.*[ ]+R_X86_64_32[ ]+xtrn +.*[ ]+R_X86_64_PC64[ ]+xtrn\+0x0*2 +.*[ ]+R_X86_64_PC32[ ]+xtrn\+0x0*2 +.*[ ]+R_X86_64_PC16[ ]+xtrn\+0x0*2 +.*[ ]+R_X86_64_PC8[ ]+xtrn\+0x0*1 +.*[ ]+R_X86_64_PC32[ ]+xtrn\+0xf+c +.*[ ]+R_X86_64_PC32[ ]+xtrn\+0xf+c +.*[ ]+R_X86_64_PC8[ ]+xtrn\+0xf+f +.*[ ]+R_X86_64_GOT32[ ]+xtrn +.*[ ]+R_X86_64_GOT32[ ]+xtrn +.*[ ]+R_X86_64_GOTOFF64[ ]+xtrn +.*[ ]+R_X86_64_GOTPCREL[ ]+xtrn +.*[ ]+R_X86_64_GOTPCREL[ ]+xtrn +.*[ ]+R_X86_64_GOTPCREL[ ]+xtrn\+0xf+c +.*[ ]+R_X86_64_GOTPC32[ ]+_GLOBAL_OFFSET_TABLE_\+0x0*2 +.*[ ]+R_X86_64_GOTPC32[ ]+_GLOBAL_OFFSET_TABLE_\+0xf+f +.*[ ]+R_X86_64_GOTPC32[ ]+_GLOBAL_OFFSET_TABLE_\+0x0*2 +.*[ ]+R_X86_64_PLT32[ ]+xtrn +.*[ ]+R_X86_64_PLT32[ ]+xtrn +.*[ ]+R_X86_64_PLT32[ ]+xtrn\+0xf+c +.*[ ]+R_X86_64_TLSGD[ ]+xtrn +.*[ ]+R_X86_64_TLSGD[ ]+xtrn +.*[ ]+R_X86_64_TLSGD[ ]+xtrn\+0xf+c +.*[ ]+R_X86_64_GOTTPOFF[ ]+xtrn +.*[ ]+R_X86_64_GOTTPOFF[ ]+xtrn +.*[ ]+R_X86_64_GOTTPOFF[ ]+xtrn\+0xf+c +.*[ ]+R_X86_64_TLSLD[ ]+xtrn +.*[ ]+R_X86_64_TLSLD[ ]+xtrn +.*[ ]+R_X86_64_TLSLD[ ]+xtrn\+0xf+c +.*[ ]+R_X86_64_DTPOFF64[ ]+xtrn +.*[ ]+R_X86_64_DTPOFF32[ ]+xtrn +.*[ ]+R_X86_64_DTPOFF32[ ]+xtrn +.*[ ]+R_X86_64_TPOFF64[ ]+xtrn +.*[ ]+R_X86_64_TPOFF32[ ]+xtrn +.*[ ]+R_X86_64_TPOFF32[ ]+xtrn +Disassembly of section \.data: +#... +.*[ ]+R_X86_64_64[ ]+xtrn +.*[ ]+R_X86_64_PC64[ ]+xtrn +.*[ ]+R_X86_64_GOTOFF64[ ]+xtrn +.*[ ]+R_X86_64_DTPOFF64[ ]+xtrn +.*[ ]+R_X86_64_TPOFF64[ ]+xtrn +.*[ ]+R_X86_64_32[ ]+xtrn +.*[ ]+R_X86_64_PC32[ ]+xtrn +.*[ ]+R_X86_64_GOT32[ ]+xtrn +.*[ ]+R_X86_64_GOTPCREL[ ]+xtrn +.*[ ]+R_X86_64_GOTPC32[ ]+_GLOBAL_OFFSET_TABLE_ +.*[ ]+R_X86_64_GOTPC32[ ]+_GLOBAL_OFFSET_TABLE_ +.*[ ]+R_X86_64_PLT32[ ]+xtrn +.*[ ]+R_X86_64_TLSGD[ ]+xtrn +.*[ ]+R_X86_64_GOTTPOFF[ ]+xtrn +.*[ ]+R_X86_64_TLSLD[ ]+xtrn +.*[ ]+R_X86_64_DTPOFF32[ ]+xtrn +.*[ ]+R_X86_64_TPOFF32[ ]+xtrn +.*[ ]+R_X86_64_16[ ]+xtrn +.*[ ]+R_X86_64_PC16[ ]+xtrn +.*[ ]+R_X86_64_8[ ]+xtrn +.*[ ]+R_X86_64_PC8[ ]+xtrn diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/i386/reloc64.l binutils-2.16.91.0.2/gas/testsuite/gas/i386/reloc64.l --- binutils-2.16.91.0.1/gas/testsuite/gas/i386/reloc64.l 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/i386/reloc64.l 2005-07-20 12:27:28.010074830 -0700 @@ -0,0 +1,77 @@ +.*: Assembler messages: +.*:29: Error: .* +.*:33: Error: .* +.*:35: Error: .* +.*:36: Error: .* +.*:37: Error: .* +.*:39: Error: .* +.*:40: Error: .* +.*:43: Error: .* +.*:44: Error: .* +.*:45: Error: .* +.*:46: Error: .* +.*:47: Error: .* +.*:48: Error: .* +.*:49: Error: .* +.*:51: Error: .* +.*:53: Error: .* +.*:54: Error: .* +.*:55: Error: .* +.*:57: Error: .* +.*:66: Error: .* +.*:73: Error: .* +.*:75: Error: .* +.*:76: Error: .* +.*:77: Error: .* +.*:79: Error: .* +.*:81: Error: .* +.*:83: Error: .* +.*:85: Error: .* +.*:86: Error: .* +.*:87: Error: .* +.*:89: Error: .* +.*:92: Error: .* +.*:94: Error: .* +.*:95: Error: .* +.*:96: Error: .* +.*:98: Error: .* +.*:101: Error: .* +.*:103: Error: .* +.*:104: Error: .* +.*:105: Error: .* +.*:107: Error: .* +.*:112: Error: .* +.*:113: Error: .* +.*:114: Error: .* +.*:116: Error: .* +.*:117: Error: .* +.*:121: Error: .* +.*:122: Error: .* +.*:123: Error: .* +.*:125: Error: .* +.*:126: Error: .* +.*:131: Error: .* +.*:133: Error: .* +.*:136: Error: .* +.*:137: Error: .* +.*:138: Error: .* +.*:139: Error: .* +.*:146: Error: .* +.*:159: Error: .* +.*:160: Error: .* +.*:161: Error: .* +.*:164: Error: .* +.*:165: Error: .* +.*:166: Error: .* +.*:167: Error: .* +.*:168: Error: .* +.*:169: Error: .* +.*:173: Error: .* +.*:174: Error: .* +.*:175: Error: .* +.*:178: Error: .* +.*:179: Error: .* +.*:180: Error: .* +.*:181: Error: .* +.*:182: Error: .* +.*:183: Error: .* diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/i386/reloc64.s binutils-2.16.91.0.2/gas/testsuite/gas/i386/reloc64.s --- binutils-2.16.91.0.1/gas/testsuite/gas/i386/reloc64.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/i386/reloc64.s 2005-07-20 12:27:28.010074830 -0700 @@ -0,0 +1,183 @@ + .macro bad args:vararg + .ifdef _bad_ + \args + .endif + .endm + + .macro ill args:vararg + # This is used to mark entries that aren't handled consistently, + # and thus shouldn't currently be checked for. + # \args + .endm + + .text +_start: + movabs $xtrn, %rax + add $xtrn, %rax + mov $xtrn, %eax + mov $xtrn, %ax + mov $xtrn, %al + mov xtrn(%rbx), %eax + mov xtrn(%ebx), %eax + + movabs $(xtrn - .), %rax + add $(xtrn - .), %rax +ill mov $(xtrn - .), %eax + mov $(xtrn - .), %ax + mov $(xtrn - .), %al + mov xtrn(%rip), %eax +bad mov xtrn(%eip), %eax + call xtrn + jrcxz xtrn + +bad movabs $xtrn@got, %rax + add $xtrn@got, %rax +bad mov $xtrn@got, %eax +bad mov $xtrn@got, %ax +bad mov $xtrn@got, %al + mov xtrn@got(%rbx), %eax +bad mov xtrn@got(%ebx), %eax +bad call xtrn@got + + movabs $xtrn@gotoff, %rax +bad add $xtrn@gotoff, %rax +bad mov $xtrn@gotoff, %eax +bad mov $xtrn@gotoff, %ax +bad mov $xtrn@gotoff, %al +bad mov xtrn@gotoff(%rbx), %eax +bad mov xtrn@gotoff(%ebx), %eax +bad call xtrn@gotoff + +bad movabs $xtrn@gotpcrel, %rax + add $xtrn@gotpcrel, %rax +bad mov $xtrn@gotpcrel, %eax +bad mov $xtrn@gotpcrel, %ax +bad mov $xtrn@gotpcrel, %al + mov xtrn@gotpcrel(%rbx), %eax +bad mov xtrn@gotpcrel(%ebx), %eax + call xtrn@gotpcrel + +ill movabs $_GLOBAL_OFFSET_TABLE_, %rax + add $_GLOBAL_OFFSET_TABLE_, %rax +ill add $_GLOBAL_OFFSET_TABLE_, %eax +ill add $_GLOBAL_OFFSET_TABLE_, %ax +ill add $_GLOBAL_OFFSET_TABLE_, %al + lea _GLOBAL_OFFSET_TABLE_(%rip), %rax #??? +bad lea _GLOBAL_OFFSET_TABLE_(%eip), %rax +ill movabs $(_GLOBAL_OFFSET_TABLE_ - .), %rax + add $(_GLOBAL_OFFSET_TABLE_ - .), %rax +ill add $(_GLOBAL_OFFSET_TABLE_ - .), %eax +ill add $(_GLOBAL_OFFSET_TABLE_ - .), %ax +ill add $(_GLOBAL_OFFSET_TABLE_ - .), %al + +bad movabs $xtrn@plt, %rax + add $xtrn@plt, %rax +bad mov $xtrn@plt, %eax +bad mov $xtrn@plt, %ax +bad mov $xtrn@plt, %al + mov xtrn@plt(%rbx), %eax +bad mov xtrn@plt(%ebx), %eax + call xtrn@plt +bad jrcxz xtrn@plt + +bad movabs $xtrn@tlsgd, %rax + add $xtrn@tlsgd, %rax +bad mov $xtrn@tlsgd, %eax +bad mov $xtrn@tlsgd, %ax +bad mov $xtrn@tlsgd, %al + mov xtrn@tlsgd(%rbx), %eax +bad mov xtrn@tlsgd(%ebx), %eax + call xtrn@tlsgd + +bad movabs $xtrn@gottpoff, %rax + add $xtrn@gottpoff, %rax +bad mov $xtrn@gottpoff, %eax +bad mov $xtrn@gottpoff, %ax +bad mov $xtrn@gottpoff, %al + mov xtrn@gottpoff(%rbx), %eax +bad mov xtrn@gottpoff(%ebx), %eax + call xtrn@gottpoff + +bad movabs $xtrn@tlsld, %rax + add $xtrn@tlsld, %rax +bad mov $xtrn@tlsld, %eax +bad mov $xtrn@tlsld, %ax +bad mov $xtrn@tlsld, %al + mov xtrn@tlsld(%rbx), %eax +bad mov xtrn@tlsld(%ebx), %eax + call xtrn@tlsld + + movabs $xtrn@dtpoff, %rax + add $xtrn@dtpoff, %rax +bad mov $xtrn@dtpoff, %eax +bad mov $xtrn@dtpoff, %ax +bad mov $xtrn@dtpoff, %al + mov xtrn@dtpoff(%rbx), %eax +bad mov xtrn@dtpoff(%ebx), %eax +bad call xtrn@dtpoff + + movabs $xtrn@tpoff, %rax + add $xtrn@tpoff, %rax +bad mov $xtrn@tpoff, %eax +bad mov $xtrn@tpoff, %ax +bad mov $xtrn@tpoff, %al + mov xtrn@tpoff(%rbx), %eax +bad mov xtrn@tpoff(%ebx), %eax +bad call xtrn@tpoff + + .data + .quad xtrn + .quad xtrn - . +bad .quad xtrn@got + .quad xtrn@gotoff +bad .quad xtrn@gotpcrel +ill .quad _GLOBAL_OFFSET_TABLE_ +ill .quad _GLOBAL_OFFSET_TABLE_ - . +bad .quad xtrn@plt +bad .quad xtrn@tlsgd +bad .quad xtrn@gottpoff +bad .quad xtrn@tlsld + .quad xtrn@dtpoff + .quad xtrn@tpoff + + .long xtrn + .long xtrn - . + .long xtrn@got +bad .long xtrn@gotoff + .long xtrn@gotpcrel + .long _GLOBAL_OFFSET_TABLE_ + .long _GLOBAL_OFFSET_TABLE_ - . + .long xtrn@plt + .long xtrn@tlsgd + .long xtrn@gottpoff + .long xtrn@tlsld + .long xtrn@dtpoff + .long xtrn@tpoff + + .word xtrn + .word xtrn - . +bad .word xtrn@got +bad .word xtrn@gotoff +bad .word xtrn@gotpcrel +ill .word _GLOBAL_OFFSET_TABLE_ +ill .word _GLOBAL_OFFSET_TABLE_ - . +bad .word xtrn@plt +bad .word xtrn@tlsgd +bad .word xtrn@gottpoff +bad .word xtrn@tlsld +bad .word xtrn@dtpoff +bad .word xtrn@tpoff + + .byte xtrn + .byte xtrn - . +bad .byte xtrn@got +bad .byte xtrn@gotoff +bad .byte xtrn@gotpcrel +ill .byte _GLOBAL_OFFSET_TABLE_ +ill .byte _GLOBAL_OFFSET_TABLE_ - . +bad .byte xtrn@plt +bad .byte xtrn@tlsgd +bad .byte xtrn@gottpoff +bad .byte xtrn@tlsld +bad .byte xtrn@dtpoff +bad .byte xtrn@tpoff diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/i386/suffix.d binutils-2.16.91.0.2/gas/testsuite/gas/i386/suffix.d --- binutils-2.16.91.0.1/gas/testsuite/gas/i386/suffix.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/i386/suffix.d 2005-07-20 12:27:28.011074665 -0700 @@ -0,0 +1,15 @@ +#objdump: -dw -Msuffix +#name: i386 suffix + +.*: +file format .* + +Disassembly of section .text: + +0+000 : + 0: 0f 01 c8 [ ]*monitor %eax,%ecx,%edx + 3: 0f 01 c9 [ ]*mwait %eax,%ecx + 6: 0f 01 c1 [ ]*vmcall + 9: 0f 01 c2 [ ]*vmlaunch + c: 0f 01 c3 [ ]*vmresume + f: 0f 01 c4 [ ]*vmxoff + ... diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/i386/suffix.s binutils-2.16.91.0.2/gas/testsuite/gas/i386/suffix.s --- binutils-2.16.91.0.1/gas/testsuite/gas/i386/suffix.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/i386/suffix.s 2005-07-20 12:27:28.011074665 -0700 @@ -0,0 +1,13 @@ +# Disassembling with -Msuffix. + + .text +foo: + monitor + mwait + + vmcall + vmlaunch + vmresume + vmxoff + + .p2align 4,0 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/i386/svme64.d binutils-2.16.91.0.2/gas/testsuite/gas/i386/svme64.d --- binutils-2.16.91.0.1/gas/testsuite/gas/i386/svme64.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/i386/svme64.d 2005-07-20 12:27:28.012074500 -0700 @@ -0,0 +1,41 @@ +#as: --defsym __amd64__=1 +#objdump: -dw +#name: 64-bit SVME +#source: svme.s + +.*: +file format .* + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+0f 01 dd[ ]+clgi[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 df[ ]+invlpga[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 de[ ]+skinit[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 dc[ ]+stgi[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 da[ ]+vmload[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 d9[ ]+vmmcall[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 d8[ ]+vmrun[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 db[ ]+vmsave[ ]* +[0-9a-f]+ : +[ ]*[0-9a-f]+:[ ]+0f 01 df[ ]+invlpga[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 da[ ]+vmload[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 d8[ ]+vmrun[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 db[ ]+vmsave[ ]* +[0-9a-f]+ : +[ ]*[0-9a-f]+:[ ]+0f 01 de[ ]+skinit[ ]* +[ ]*[0-9a-f]+:[ ]+67 0f 01 df[ ]+(addr32 )?invlpga[ ]*\(%eax\),[ ]*%ecx +[ ]*[0-9a-f]+:[ ]+67 0f 01 da[ ]+(addr32 )?vmload[ ]*\(%eax\) +[ ]*[0-9a-f]+:[ ]+67 0f 01 d8[ ]+(addr32 )?vmrun[ ]*\(%eax\) +[ ]*[0-9a-f]+:[ ]+67 0f 01 db[ ]+(addr32 )?vmsave[ ]*\(%eax\) +[0-9a-f]+ : +[ ]*[0-9a-f]+:[ ]+0f 01 df[ ]+invlpga[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 da[ ]+vmload[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 d8[ ]+vmrun[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 db[ ]+vmsave[ ]* +[0-9a-f]+ : +[ ]*[0-9a-f]+:[ ]+0f 01 de[ ]+skinit[ ]* +[ ]*[0-9a-f]+:[ ]+67 0f 01 df[ ]+(addr32 )?invlpga[ ]*\(%eax\),[ ]*%ecx +[ ]*[0-9a-f]+:[ ]+67 0f 01 da[ ]+(addr32 )?vmload[ ]*\(%eax\) +[ ]*[0-9a-f]+:[ ]+67 0f 01 d8[ ]+(addr32 )?vmrun[ ]*\(%eax\) +[ ]*[0-9a-f]+:[ ]+67 0f 01 db[ ]+(addr32 )?vmsave[ ]*\(%eax\) +#pass diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/i386/svme.d binutils-2.16.91.0.2/gas/testsuite/gas/i386/svme.d --- binutils-2.16.91.0.1/gas/testsuite/gas/i386/svme.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/i386/svme.d 2005-07-20 12:27:28.011074665 -0700 @@ -0,0 +1,29 @@ +#objdump: -dw +#name: 32-bit SVME + +.*: +file format .* + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+0f 01 dd[ ]+clgi[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 df[ ]+invlpga[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 de[ ]+skinit[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 dc[ ]+stgi[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 da[ ]+vmload[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 d9[ ]+vmmcall[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 d8[ ]+vmrun[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 db[ ]+vmsave[ ]* +[0-9a-f]+ : +[ ]*[0-9a-f]+:[ ]+0f 01 de[ ]+skinit[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 df[ ]+invlpga[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 da[ ]+vmload[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 d8[ ]+vmrun[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 db[ ]+vmsave[ ]* +[0-9a-f]+ : +[ ]*[0-9a-f]+:[ ]+0f 01 de[ ]+skinit[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 df[ ]+invlpga[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 da[ ]+vmload[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 d8[ ]+vmrun[ ]* +[ ]*[0-9a-f]+:[ ]+0f 01 db[ ]+vmsave[ ]* +#pass diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/i386/svme.s binutils-2.16.91.0.2/gas/testsuite/gas/i386/svme.s --- binutils-2.16.91.0.1/gas/testsuite/gas/i386/svme.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/i386/svme.s 2005-07-20 12:27:28.011074665 -0700 @@ -0,0 +1,36 @@ + .text +common: + clgi + invlpga + skinit + stgi + vmload + vmmcall + vmrun + vmsave + +.macro do_args arg1, arg2 + invlpga \arg1, \arg2 + vmload \arg1 + vmrun \arg1 + vmsave \arg1 +.endm + +.ifdef __amd64__ +att64: + do_args (%rax), %ecx +.endif +att32: + skinit (%eax) + do_args (%eax), %ecx + +.intel_syntax noprefix +.ifdef __amd64__ +intel64: + do_args [rax], ecx +.endif +intel32: + skinit [eax] + do_args [eax], ecx + + .p2align 4,0 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/i386/vmx.d binutils-2.16.91.0.2/gas/testsuite/gas/i386/vmx.d --- binutils-2.16.91.0.1/gas/testsuite/gas/i386/vmx.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/i386/vmx.d 2005-07-20 12:27:28.012074500 -0700 @@ -0,0 +1,25 @@ +#objdump: -dw +#name: i386 VMX + +.*: +file format .* + +Disassembly of section .text: + +0+000 : + 0: 0f 01 c1 [ ]*vmcall + 3: 0f 01 c2 [ ]*vmlaunch + 6: 0f 01 c3 [ ]*vmresume + 9: 0f 01 c4 [ ]*vmxoff + c: 66 0f c7 30 [ ]*vmclear \(%eax\) + 10: 0f c7 30 [ ]*vmptrld \(%eax\) + 13: 0f c7 38 [ ]*vmptrst \(%eax\) + 16: f3 0f c7 30 [ ]*vmxon \(%eax\) + 1a: 0f 78 c3 [ ]*vmread %eax,%ebx + 1d: 0f 78 c3 [ ]*vmread %eax,%ebx + 20: 0f 78 03 [ ]*vmread %eax,\(%ebx\) + 23: 0f 78 03 [ ]*vmread %eax,\(%ebx\) + 26: 0f 79 d8 [ ]*vmwrite %eax,%ebx + 29: 0f 79 d8 [ ]*vmwrite %eax,%ebx + 2c: 0f 79 18 [ ]*vmwrite \(%eax\),%ebx + 2f: 0f 79 18 [ ]*vmwrite \(%eax\),%ebx + ... diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/i386/vmx.s binutils-2.16.91.0.2/gas/testsuite/gas/i386/vmx.s --- binutils-2.16.91.0.1/gas/testsuite/gas/i386/vmx.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/i386/vmx.s 2005-07-20 12:27:28.012074500 -0700 @@ -0,0 +1,21 @@ +# VMX Instructions + + .text +foo: + vmcall + vmlaunch + vmresume + vmxoff + vmclear (%eax) + vmptrld (%eax) + vmptrst (%eax) + vmxon (%eax) + vmread %eax,%ebx + vmreadl %eax,%ebx + vmread %eax,(%ebx) + vmreadl %eax,(%ebx) + vmwrite %eax,%ebx + vmwritel %eax,%ebx + vmwrite (%eax),%ebx + vmwritel (%eax),%ebx + .p2align 4,0 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/i386/x86_64.d binutils-2.16.91.0.2/gas/testsuite/gas/i386/x86_64.d --- binutils-2.16.91.0.1/gas/testsuite/gas/i386/x86_64.d 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/i386/x86_64.d 2005-07-20 12:27:28.013074335 -0700 @@ -140,4 +140,20 @@ Disassembly of section .text: 27e: 66 a3 11 22 33 44 55 66 77 88 mov[ ]+%ax,0x8877665544332211 288: a3 11 22 33 44 55 66 77 88 mov[ ]+%eax,0x8877665544332211 291: 48 a3 11 22 33 44 55 66 77 88 mov[ ]+%rax,0x8877665544332211 + 29b: 8a 04 25 11 22 33 ff mov[ ]+0xffffffffff332211,%al + 2a2: 66 8b 04 25 11 22 33 ff mov[ ]+0xffffffffff332211,%ax + 2aa: 8b 04 25 11 22 33 ff mov[ ]+0xffffffffff332211,%eax + 2b1: 48 8b 04 25 11 22 33 ff mov[ ]+0xffffffffff332211,%rax + 2b9: 88 04 25 11 22 33 ff mov[ ]+%al,0xffffffffff332211 + 2c0: 66 89 04 25 11 22 33 ff mov[ ]+%ax,0xffffffffff332211 + 2c8: 89 04 25 11 22 33 ff mov[ ]+%eax,0xffffffffff332211 + 2cf: 48 89 04 25 11 22 33 ff mov[ ]+%rax,0xffffffffff332211 + 2d7: 8a 04 25 11 22 33 ff mov[ ]+0xffffffffff332211,%al + 2de: 66 8b 04 25 11 22 33 ff mov[ ]+0xffffffffff332211,%ax + 2e6: 8b 04 25 11 22 33 ff mov[ ]+0xffffffffff332211,%eax + 2ed: 48 8b 04 25 11 22 33 ff mov[ ]+0xffffffffff332211,%rax + 2f5: 88 04 25 11 22 33 ff mov[ ]+%al,0xffffffffff332211 + 2fc: 66 89 04 25 11 22 33 ff mov[ ]+%ax,0xffffffffff332211 + 304: 89 04 25 11 22 33 ff mov[ ]+%eax,0xffffffffff332211 + 30b: 48 89 04 25 11 22 33 ff mov[ ]+%rax,0xffffffffff332211 #pass diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/i386/x86_64.s binutils-2.16.91.0.2/gas/testsuite/gas/i386/x86_64.s --- binutils-2.16.91.0.1/gas/testsuite/gas/i386/x86_64.s 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/i386/x86_64.s 2005-07-20 12:27:28.014074170 -0700 @@ -170,5 +170,23 @@ movw %ax,0x8877665544332211 movl %eax,0x8877665544332211 movq %rax,0x8877665544332211 +#absolute signed 32bit addressing +mov 0xffffffffff332211,%al +mov 0xffffffffff332211,%ax +mov 0xffffffffff332211,%eax +mov 0xffffffffff332211,%rax +mov %al,0xffffffffff332211 +mov %ax,0xffffffffff332211 +mov %eax,0xffffffffff332211 +mov %rax,0xffffffffff332211 +movb 0xffffffffff332211,%al +movw 0xffffffffff332211,%ax +movl 0xffffffffff332211,%eax +movq 0xffffffffff332211,%rax +movb %al,0xffffffffff332211 +movw %ax,0xffffffffff332211 +movl %eax,0xffffffffff332211 +movq %rax,0xffffffffff332211 + # Get a good alignment. .p2align 4,0 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/i386/x86-64-vmx.d binutils-2.16.91.0.2/gas/testsuite/gas/i386/x86-64-vmx.d --- binutils-2.16.91.0.1/gas/testsuite/gas/i386/x86-64-vmx.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/i386/x86-64-vmx.d 2005-07-20 12:27:28.013074335 -0700 @@ -0,0 +1,25 @@ +#objdump: -dw +#name: 64bit VMX + +.*: +file format .* + +Disassembly of section .text: + +0+000 : + 0: 0f 01 c1 [ ]*vmcall + 3: 0f 01 c2 [ ]*vmlaunch + 6: 0f 01 c3 [ ]*vmresume + 9: 0f 01 c4 [ ]*vmxoff + c: 66 0f c7 30 [ ]*vmclear \(%rax\) + 10: 0f c7 30 [ ]*vmptrld \(%rax\) + 13: 0f c7 38 [ ]*vmptrst \(%rax\) + 16: f3 0f c7 30 [ ]*vmxon \(%rax\) + 1a: 0f 78 c3 [ ]*vmread %rax,%rbx + 1d: 0f 78 c3 [ ]*vmread %rax,%rbx + 20: 0f 78 03 [ ]*vmread %rax,\(%rbx\) + 23: 0f 78 03 [ ]*vmread %rax,\(%rbx\) + 26: 0f 79 d8 [ ]*vmwrite %rax,%rbx + 29: 0f 79 d8 [ ]*vmwrite %rax,%rbx + 2c: 0f 79 18 [ ]*vmwrite \(%rax\),%rbx + 2f: 0f 79 18 [ ]*vmwrite \(%rax\),%rbx + ... diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/i386/x86-64-vmx.s binutils-2.16.91.0.2/gas/testsuite/gas/i386/x86-64-vmx.s --- binutils-2.16.91.0.1/gas/testsuite/gas/i386/x86-64-vmx.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/i386/x86-64-vmx.s 2005-07-20 12:27:28.013074335 -0700 @@ -0,0 +1,21 @@ +# VMX Instructions + + .text +foo: + vmcall + vmlaunch + vmresume + vmxoff + vmclear (%rax) + vmptrld (%rax) + vmptrst (%rax) + vmxon (%rax) + vmread %rax,%rbx + vmreadq %rax,%rbx + vmread %rax,(%rbx) + vmreadq %rax,(%rbx) + vmwrite %rax,%rbx + vmwriteq %rax,%rbx + vmwrite (%rax),%rbx + vmwriteq (%rax),%rbx + .p2align 4,0 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ia64/group-2.s binutils-2.16.91.0.2/gas/testsuite/gas/ia64/group-2.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ia64/group-2.s 2005-05-10 15:46:46.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ia64/group-2.s 2005-07-20 12:27:28.022072851 -0700 @@ -1,6 +1,6 @@ .section .gnu.linkonce.t.foo,"axG",@progbits,foo,comdat .proc foo# foo: - .prologue 12, 33 + .prologue 12, r33 ;; .endp foo# diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ia64/ia64.exp binutils-2.16.91.0.2/gas/testsuite/gas/ia64/ia64.exp --- binutils-2.16.91.0.1/gas/testsuite/gas/ia64/ia64.exp 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ia64/ia64.exp 2005-07-20 12:27:28.023072687 -0700 @@ -84,7 +84,10 @@ if [istarget "ia64-*"] then { run_list_test "proc" "-munwind-check=error" run_list_test "radix" "" run_list_test "slot2" "" + run_dump_test "strange" + run_list_test "unwind-bad" "" run_list_test "unwind-err" "-munwind-check=error" + run_dump_test "unwind-ok" run_dump_test "operand-or" run_list_test "hint.b-err" "" run_list_test "hint.b-warn" "-mhint.b=warning" diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ia64/strange.d binutils-2.16.91.0.2/gas/testsuite/gas/ia64/strange.d --- binutils-2.16.91.0.1/gas/testsuite/gas/ia64/strange.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ia64/strange.d 2005-07-20 12:27:28.023072687 -0700 @@ -0,0 +1,19 @@ +#objdump: -s +#name: ia64 strange + +.*: +file format .* + +Contents of section .text: + 0000 0c000000 01001000 00020000 00000400 .* + 0010 04000000 01000000 00000020 00000400 .* + 0020 0c000000 01002000 00020000 00000400 .* + 0030 04000000 01000000 00000040 00000400 .* + 0040 1c000000 01003000 00020000 00000020 .* + 0050 04000000 01000000 00000080 00000400 .* + 0060 04000000 01000000 000000a0 00000400 .* + 0070 04000000 01000000 000000c0 00000400 .* + 0080 04000000 01000000 000000e0 00000400 .* + 0090 0e000000 01000000 00020000 01000400 .* + 00a0 1d000000 01009000 00020080 00008400 .* +Contents of section .data: + 0000 ffffff .* diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ia64/strange.s binutils-2.16.91.0.2/gas/testsuite/gas/ia64/strange.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ia64/strange.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ia64/strange.s 2005-07-20 12:27:28.023072687 -0700 @@ -0,0 +1,18 @@ +.explicit +.text +_start: +{.mfi + nop.f 1 } nop.x 1 +{.mfi + nop.f 2 +} nop.x 2 +{.mfb + nop.f 3 +.xdata1 .data, -1 } .xdata1 .data, -1 + nop.x 4 { nop.x 5 +} { nop.x 6 } + nop.x 7 {.mmf + nop.f 8 +} .xdata1 .data, -1 { .mfb + nop.f 9 + br.ret.sptk rp } diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ia64/unwind-bad.l binutils-2.16.91.0.2/gas/testsuite/gas/ia64/unwind-bad.l --- binutils-2.16.91.0.1/gas/testsuite/gas/ia64/unwind-bad.l 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ia64/unwind-bad.l 2005-07-20 12:27:28.024072522 -0700 @@ -0,0 +1,51 @@ +.*: Assembler messages: +.*:8: Error: First operand to \.save\.g must be a positive 4-bit constant +.*:10: Error: First operand to \.save\.g must be a positive 4-bit constant +.*:12: Error: First operand to \.save\.g must be a positive 4-bit constant +#FIXME .*:16: Error: Previous spill incomplete +#FIXME .*:18: Error: Register r4 was already saved +.*:20: Error: Operand to \.save\.f must be a positive 20-bit constant +.*:22: Error: Operand to \.save\.f must be a positive 20-bit constant +.*:24: Error: Operand to \.save\.f must be a positive 20-bit constant +#FIXME .*:28: Error: Previous spill incomplete +#FIXME .*:30: Error: Register f2 was already saved +.*:32: Error: First operand to \.save\.b must be a positive 5-bit constant +.*:34: Error: First operand to \.save\.b must be a positive 5-bit constant +.*:36: Error: First operand to \.save\.b must be a positive 5-bit constant +#FIXME .*:40: Error: Previous spill incomplete +#FIXME .*:42: Error: Register b1 was already saved +.*:44: Error: Operand 2 to \.spillreg must be a writable register +.*:46: Error: Operand 1 to \.spillreg must be a preserved register +.*:48: Error: Operand 1 to \.spillreg must be a preserved register +.*:50: Error: Operand 1 to \.spillreg must be a preserved register +.*:52: Error: Operand 2 to \.spillreg must be a writable register +.*:54: Error: Operand 2 to \.spillreg must be a writable register +.*:56: Error: Operand 1 to \.spillreg must be a preserved register +#FIXME .*:58: Error: Floating point register cannot be spilled to general register +#FIXME .*:60: Error: Floating point register cannot be spilled to branch register +.*:62: Warning: Pointless use of p0 as first operand to \.spillreg\.p +.*:64: Error: Operand 3 to \.spillreg.p must be a writable register +.*:66: Error: Operand 3 to \.spillreg.p must be a writable register +.*:68: Warning: Pointless use of p0 as first operand to \.restorereg\.p +.*:78: Error: Operands to \.save\.gf may not be both zero +.*:80: Error: First operand to \.save\.gf must be a non-negative 4-bit constant +.*:82: Error: Second operand to \.save\.gf must be a non-negative 20-bit constant +.*:84: Error: First operand to \.save\.gf must be a non-negative 4-bit constant +.*:86: Error: Second operand to \.save\.gf must be a non-negative 20-bit constant +#FIXME .*:90: Error: Previous spill incomplete +#FIXME .*:92: Error: Register r4 was already saved +#FIXME .*:94: Error: Register f2 was already saved +.*:98: Error: Epilogue count of 2 exceeds number of nested prologues \(1\) +.*:100: Error: Missing \.label_state 2 +.*:108: Error: First operand to \.save\.g must be a positive 4-bit constant +#FIXME .*:110: Error: Second operand to \.save\.g must be a writable general registers +.*:112: Error: Second operand to \.save\.g must be the first of 2 general registers +.*:115: Error: First operand to \.save\.b must be a positive 5-bit constant +#FIXME .*:117: Error: Second operand to \.save\.b must be a writable general registers +.*:119: Error: Second operand to \.save\.b must be the first of 2 general registers +.*:128: Error: First operand to \.prologue must be a positive 4-bit constant +.*:134: Warning: Pointless use of zero first operand to \.prologue +.*:140: Error: First operand to \.prologue must be a positive 4-bit constant +#FIXME .*:141: Error: Operand to \.vframe must be a writable general registers +#FIXME .*:147: Error: Second operand to \.prologue must be a writable general registers +.*:153: Error: Second operand to \.prologue must be the first of 2 general registers diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ia64/unwind-bad.s binutils-2.16.91.0.2/gas/testsuite/gas/ia64/unwind-bad.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ia64/unwind-bad.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ia64/unwind-bad.s 2005-07-20 12:27:28.024072522 -0700 @@ -0,0 +1,155 @@ +.text + +.proc full1 +full1: + +.prologue +.spill 0 +.save.g 0 + nop 0 +.save.g 0x10 + nop 0 +.save.g -1 + nop 0 +.save.g 0x3 + nop 0 +.save.g 0x4 + nop 0 +.save.g 0x1 + nop 0 +.save.f 0 + nop 0 +.save.f 0x100000 + nop 0 +.save.f -1 + nop 0 +.save.f 0x3 + nop 0 +.save.f 0x4 + nop 0 +.save.f 0x1 + nop 0 +.save.b 0 + nop 0 +.save.b 0x20 + nop 0 +.save.b -1 + nop 0 +.save.b 0x3 + nop 0 +.save.b 0x4 + nop 0 +.save.b 0x1 + nop 0 +.spillreg r4, r0 + nop 0 +.spillreg r3, r2 + nop 0 +.spillreg r8, r9 + nop 0 +.spillreg b6, r10 + nop 0 +.spillreg f2, f0 + nop 0 +.spillreg f3, f1 + nop 0 +.spillreg f6, f7 + nop 0 +.spillreg f4, r11 + nop 0 +.spillreg f5, b0 + nop 0 +.spillreg.p p0, r4, r3 + nop 0 +.spillreg.p p1, r4, r0 + nop 0 +.spillreg.p p1, f16, f0 + nop 0 +.restorereg.p p0, r4 + nop 0 +.body + br.ret.sptk rp +.endp full1 + +.proc full2 +full2: +.prologue +.spill 0 +.save.gf 0, 0 + nop 0 +.save.gf 0x10, 0 + nop 0 +.save.gf 0, 0x100000 + nop 0 +.save.gf ~0, 0 + nop 0 +.save.gf 0, ~0 + nop 0 +.save.gf 1, 1 + nop 0 +.save.gf 2, 0 + nop 0 +.save.gf 1, 0 + nop 0 +.save.gf 0, 1 + nop 0 +.body +.label_state 1 +.restore sp, 1 + nop.x 0 +.copy_state 2 + br.ret.sptk rp +.endp full2 + +.proc full3 +full3: +.prologue +.spill 0 +.save.g 0x10, r16 + nop 0 +.save.g 0x01, r0 + nop 0 +.save.g 0x06, r127 + nop 0 + nop 0 +.save.b 0x20, r16 + nop 0 +.save.b 0x01, r0 + nop 0 +.save.b 0x18, r127 + nop 0 + nop 0 +.body + br.ret.sptk rp +.endp full3 + +.proc simple1 +simple1: +.prologue 0x10, r2 + br.ret.sptk rp +.endp simple1 + +.proc simple2 +simple2: +.prologue 0, r2 + br.ret.sptk rp +.endp simple2 + +.proc simple3 +simple3: +.prologue -1, r2 +.vframe r0 + br.ret.sptk rp +.endp simple3 + +.proc simple4 +simple4: +.prologue 0x1, r0 + br.ret.sptk rp +.endp simple4 + +.proc simple5 +simple5: +.prologue 0xc, r127 + br.ret.sptk rp +.endp simple5 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ia64/unwind-err.l binutils-2.16.91.0.2/gas/testsuite/gas/ia64/unwind-err.l --- binutils-2.16.91.0.1/gas/testsuite/gas/ia64/unwind-err.l 2005-04-09 12:03:14.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ia64/unwind-err.l 2005-07-20 12:27:28.028071862 -0700 @@ -8,27 +8,28 @@ .*:7: Error: .body outside of procedure .*:8: Error: .spillreg outside of procedure .*:9: Error: .spillreg.p outside of procedure -.*:10: Error: .spillmem outside of procedure -.*:11: Error: .spillmem.p outside of procedure -.*:12: Error: .spillmem outside of procedure -.*:13: Error: .spillmem.p outside of procedure +.*:10: Error: .spillsp outside of procedure +.*:11: Error: .spillsp.p outside of procedure +.*:12: Error: .spillpsp outside of procedure +.*:13: Error: .spillpsp.p outside of procedure .*:14: Error: .restorereg outside of procedure .*:15: Error: .restorereg.p outside of procedure .*:24: Error: .label_state outside of body region .*:25: Error: .copy_state outside of body region .*:26: Error: .fframe outside of prologue .*:27: Error: .vframe outside of prologue -.*:28: Error: .spill outside of prologue -.*:29: Error: .restore outside of body region -.*:30: Error: .save outside of prologue -.*:31: Error: .savesp outside of prologue -.*:32: Error: .savepsp outside of prologue -.*:33: Error: .save.g outside of prologue -.*:34: Error: .save.gf outside of prologue -.*:35: Error: .save.f outside of prologue -.*:36: Error: .save.b outside of prologue -.*:37: Error: .altrp outside of prologue -.*:42: Error: .prologue within prologue -.*:50: Error: .body outside of procedure -.*:57: Warning: Initial .prologue.* -.*:64: Warning: Initial .body.* +.*:28: Error: .vframesp outside of prologue +.*:29: Error: .spill outside of prologue +.*:30: Error: .restore outside of body region +.*:31: Error: .save outside of prologue +.*:32: Error: .savesp outside of prologue +.*:33: Error: .savepsp outside of prologue +.*:34: Error: .save.g outside of prologue +.*:35: Error: .save.gf outside of prologue +.*:36: Error: .save.f outside of prologue +.*:37: Error: .save.b outside of prologue +.*:38: Error: .altrp outside of prologue +.*:43: Error: .prologue within prologue +.*:51: Error: .body outside of procedure +.*:58: Warning: Initial .prologue.* +.*:65: Warning: Initial .body.* diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ia64/unwind-err.s binutils-2.16.91.0.2/gas/testsuite/gas/ia64/unwind-err.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ia64/unwind-err.s 2005-04-09 12:03:14.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ia64/unwind-err.s 2005-07-20 12:27:28.029071697 -0700 @@ -25,6 +25,7 @@ start: .copy_state 1 .fframe 0 .vframe r0 +.vframesp 0 .spill 0 .restore sp .save rp, r0 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ia64/unwind-ok.d binutils-2.16.91.0.2/gas/testsuite/gas/ia64/unwind-ok.d --- binutils-2.16.91.0.1/gas/testsuite/gas/ia64/unwind-ok.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ia64/unwind-ok.d 2005-07-20 12:27:28.030071532 -0700 @@ -0,0 +1,224 @@ +#readelf: -u +#name: ia64 unwind descriptors + +Unwind section '\.IA_64\.unwind' at offset 0x[[:xdigit:]]+ contains 8 entries: + +: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*[08] +[[:space:]]*v[[:digit:]]+, flags=0x3 \( ?ehandler uhandler\), len=[[:digit:]]+ bytes +[[:space:]]*R1:prologue\(rlen=8\) +[[:space:]]*P6:fr_mem\(frmask=\[f2,f5\]\) +[[:space:]]*P6:gr_mem\(grmask=\[r4,r7\]\) +[[:space:]]*P1:br_mem\(brmask=\[b1,b5\]\) +[[:space:]]*P4:spill_mask\(imask=\[rfb,rfb,--\]\) +[[:space:]]*P7:spill_base\(pspoff=0x10-0x10\) +[[:space:]]*P3:rp_br\(reg=b7\) +[[:space:]]*P10:unwabi\(abi=@svr4,context=0x00\) +[[:space:]]*R1:body\(rlen=[[:digit:]]+\) +[[:space:]]*X2:spill_reg\(t=0,reg=r4,treg=r2\) +[[:space:]]*X4:spill_reg_p\(qp=p1,t=1,reg=r7,treg=r31\) +[[:space:]]*X1:spill_sprel\(reg=b1,t=2,spoff=0x8\) +[[:space:]]*X3:spill_sprel_p\(qp=p2,t=3,reg=b5,spoff=0x10\) +[[:space:]]*X1:spill_psprel\(reg=f2,t=4,pspoff=0x10-0x28\) +[[:space:]]*X3:spill_psprel_p\(qp=p4,t=5,reg=f5,pspoff=0x10-0x30\) +[[:space:]]*X2:restore\(t=6,reg=f16\) +[[:space:]]*X4:restore_p\(qp=p8,t=7,reg=f31\) +[[:space:]]*X2:spill_reg\(t=8,reg=ar\.bsp,treg=r16\) +[[:space:]]*X2:spill_reg\(t=9,reg=ar\.bspstore,treg=r17\) +[[:space:]]*X2:spill_reg\(t=10,reg=ar\.fpsr,treg=r18\) +[[:space:]]*X2:spill_reg\(t=11,reg=ar\.lc,treg=r19\) +[[:space:]]*X2:spill_reg\(t=12,reg=ar\.pfs,treg=r20\) +[[:space:]]*X2:spill_reg\(t=13,reg=ar\.rnat,treg=r21\) +[[:space:]]*X2:spill_reg\(t=14,reg=ar\.unat,treg=r22\) +[[:space:]]*X2:spill_reg\(t=15,reg=psp,treg=r23\) +[[:space:]]*X2:spill_reg\(t=16,reg=pr,treg=r24\) +[[:space:]]*X2:spill_reg\(t=17,reg=rp,treg=r25\) +[[:space:]]*X2:spill_reg\(t=18,reg=@priunat,treg=r26\) +[[:space:]]*B1:label_state\(label=1\) +[[:space:]]*B2:epilogue\(t=4,ecount=0\) +[[:space:]]*B1:copy_state\(label=1\) +#... +: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*[08] +[[:space:]]*v[[:digit:]]+, flags=0x0( \(\))?, len=[[:digit:]]+ bytes +[[:space:]]*R2:prologue_gr\(mask=\[rp,psp,pr\],grsave=r8,rlen=14\) +[[:space:]]*P5:frgr_mem\(grmask=\[r4,r7\],frmask=\[f2,f31\]\) +[[:space:]]*P4:spill_mask\(imask=\[b-b,bb-,---,---,--\]\) +[[:space:]]*P7:spill_base\(pspoff=0x10-0x10\) +[[:space:]]*P2:br_gr\(brmask=\[b1,b5\],gr=r32\) +[[:space:]]*X2:spill_reg\(t=6,reg=f31,treg=f31\) +[[:space:]]*X4:spill_reg_p\(qp=p63,t=7,reg=f16,treg=f0\) +[[:space:]]*X1:spill_sprel\(reg=f5,t=8,spoff=0x20\) +[[:space:]]*X3:spill_sprel_p\(qp=p31,t=9,reg=f2,spoff=0x18\) +[[:space:]]*X1:spill_psprel\(reg=b5,t=10,pspoff=0x10-0x20\) +[[:space:]]*X3:spill_psprel_p\(qp=p15,t=11,reg=b1,pspoff=0x10-0x18\) +[[:space:]]*X2:restore\(t=12,reg=r7\) +[[:space:]]*X4:restore_p\(qp=p7,t=13,reg=r4\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=0\) +[[:space:]]*R1:prologue\(rlen=0\) +[[:space:]]*R1:body\(rlen=7\) +[[:space:]]*B4:label_state\(label=32\) +[[:space:]]*B3:epilogue\(t=4,ecount=32\) +[[:space:]]*B4:copy_state\(label=32\) +#... +: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*[08] +[[:space:]]*v[[:digit:]]+, flags=0x0( \(\))?, len=[[:digit:]]+ bytes +[[:space:]]*R3:prologue\(rlen=33\) +[[:space:]]*P4:spill_mask\(imask=\[rrb,brr,bb-,---,---,---,---,---,---,---,---\]\) +[[:space:]]*P7:spill_base\(pspoff=0x10-0x10\) +[[:space:]]*P9:gr_gr\(grmask=\[r4,r5\],r32\) +[[:space:]]*P2:br_gr\(brmask=\[b1,b2\],gr=r34\) +[[:space:]]*P9:gr_gr\(grmask=\[r6,r7\],r124\) +[[:space:]]*P2:br_gr\(brmask=\[b4,b5\],gr=r126\) +[[:space:]]*R3:body\(rlen=33\) +#... +: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*[08] +[[:space:]]*v[[:digit:]]+, flags=0x0( \(\))?, len=[[:digit:]]+ bytes +[[:space:]]*R1:prologue\(rlen=1\) +[[:space:]]*P7:mem_stack_f\(t=0,size=0\) +[[:space:]]*R1:body\(rlen=2\) +#... +: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*[08] +[[:space:]]*v[[:digit:]]+, flags=0x0( \(\))?, len=[[:digit:]]+ bytes +[[:space:]]*R1:prologue\(rlen=11\) +[[:space:]]*P7:mem_stack_v\(t=0\) +[[:space:]]*P3:psp_gr\(reg=r16\) +[[:space:]]*P8:bsp_when\(t=1\) +[[:space:]]*P3:bsp_gr\(reg=r17\) +[[:space:]]*P8:bspstore_when\(t=2\) +[[:space:]]*P3:bspstore_gr\(reg=r18\) +[[:space:]]*P7:fpsr_when\(t=3\) +[[:space:]]*P3:fpsr_gr\(reg=r19\) +[[:space:]]*P7:lc_when\(t=4\) +[[:space:]]*P3:lc_gr\(reg=r20\) +[[:space:]]*P7:pfs_when\(t=5\) +[[:space:]]*P3:pfs_gr\(reg=r21\) +[[:space:]]*P8:rnat_when\(t=6\) +[[:space:]]*P3:rnat_gr\(reg=r22\) +[[:space:]]*P7:unat_when\(t=7\) +[[:space:]]*P3:unat_gr\(reg=r23\) +[[:space:]]*P7:pr_when\(t=8\) +[[:space:]]*P3:pr_gr\(reg=r24\) +[[:space:]]*P8:priunat_when_gr\(t=9\) +[[:space:]]*P3:priunat_gr\(reg=r25\) +[[:space:]]*P7:rp_when\(t=10\) +[[:space:]]*P3:rp_gr\(reg=r26\) +[[:space:]]*R1:body\(rlen=1\) +#... +: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*[08] +[[:space:]]*v[[:digit:]]+, flags=0x0( \(\))?, len=[[:digit:]]+ bytes +[[:space:]]*R1:prologue\(rlen=11\) +[[:space:]]*P7:mem_stack_v\(t=0\) +[[:space:]]*P7:psp_sprel\(spoff=0x0\) +[[:space:]]*P8:bsp_when\(t=1\) +[[:space:]]*P8:bsp_sprel\(spoff=0x8\) +[[:space:]]*P8:bspstore_when\(t=2\) +[[:space:]]*P8:bspstore_sprel\(spoff=0x10\) +[[:space:]]*P7:fpsr_when\(t=3\) +[[:space:]]*P8:fpsr_sprel\(spoff=0x18\) +[[:space:]]*P7:lc_when\(t=4\) +[[:space:]]*P8:lc_sprel\(spoff=0x20\) +[[:space:]]*P7:pfs_when\(t=5\) +[[:space:]]*P8:pfs_sprel\(spoff=0x28\) +[[:space:]]*P8:rnat_when\(t=6\) +[[:space:]]*P8:rnat_sprel\(spoff=0x30\) +[[:space:]]*P7:unat_when\(t=7\) +[[:space:]]*P8:unat_sprel\(spoff=0x38\) +[[:space:]]*P7:pr_when\(t=8\) +[[:space:]]*P8:pr_sprel\(spoff=0x40\) +[[:space:]]*P8:priunat_when_mem\(t=9\) +[[:space:]]*P8:priunat_sprel\(spoff=0x48\) +[[:space:]]*P7:rp_when\(t=10\) +[[:space:]]*P8:rp_sprel\(spoff=0x50\) +[[:space:]]*R1:body\(rlen=1\) +#... +: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*[08] +[[:space:]]*v[[:digit:]]+, flags=0x0( \(\))?, len=[[:digit:]]+ bytes +[[:space:]]*R1:prologue\(rlen=11\) +[[:space:]]*P7:mem_stack_v\(t=0\) +[[:space:]]*P7:psp_sprel\(spoff=0x0\) +[[:space:]]*P8:bsp_when\(t=1\) +[[:space:]]*P8:bsp_psprel\(pspoff=0x10-0x18\) +[[:space:]]*P8:bspstore_when\(t=2\) +[[:space:]]*P8:bspstore_psprel\(pspoff=0x10-0x20\) +[[:space:]]*P7:fpsr_when\(t=3\) +[[:space:]]*P7:fpsr_psprel\(pspoff=0x10-0x28\) +[[:space:]]*P7:lc_when\(t=4\) +[[:space:]]*P7:lc_psprel\(pspoff=0x10-0x30\) +[[:space:]]*P7:pfs_when\(t=5\) +[[:space:]]*P7:pfs_psprel\(pspoff=0x10-0x38\) +[[:space:]]*P8:rnat_when\(t=6\) +[[:space:]]*P8:rnat_psprel\(pspoff=0x10-0x40\) +[[:space:]]*P7:unat_when\(t=7\) +[[:space:]]*P7:unat_psprel\(pspoff=0x10-0x48\) +[[:space:]]*P7:pr_when\(t=8\) +[[:space:]]*P7:pr_psprel\(pspoff=0x10-0x50\) +[[:space:]]*P8:priunat_when_mem\(t=9\) +[[:space:]]*P8:priunat_psprel\(pspoff=0x10-0x58\) +[[:space:]]*P7:rp_when\(t=10\) +[[:space:]]*P7:rp_psprel\(pspoff=0x10-0x60\) +[[:space:]]*R1:body\(rlen=1\) +#... +: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*[08] +[[:space:]]*v[[:digit:]]+, flags=0x0( \(\))?, len=[[:digit:]]+ bytes +#pass diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ia64/unwind-ok.s binutils-2.16.91.0.2/gas/testsuite/gas/ia64/unwind-ok.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ia64/unwind-ok.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ia64/unwind-ok.s 2005-07-20 12:27:28.030071532 -0700 @@ -0,0 +1,272 @@ +.text +.proc personality +personality: + br.ret.sptk rp +.endp personality + +.proc full1 +full1: + +.prologue +.spill 0 +.save.g 0x1 + nop 0 +.save.f 0x1 + nop 0 +.save.b 0x01 + nop 0 +.save.g 0x8 + nop 0 +.save.f 0x8 + nop 0 +.save.b 0x10 + nop 0 +.altrp b7 + nop 0 +.unwabi @svr4, 0 + nop 0 + +.body +.spillreg r4, r2 + nop 0 +.spillreg.p p1, r7, r127 + nop 0 +.spillsp b1, 0x08 + nop 0 +.spillsp.p p2, b5, 0x10 + nop 0 +.spillpsp f2, 0x18 + nop 0 +.spillpsp.p p4, f5, 0x20 + nop 0 +.restorereg f16 + nop 0 +.restorereg.p p8, f31 + nop 0 + +.spillreg ar.bsp, r16 + nop 0 +.spillreg ar.bspstore, r17 + nop 0 +.spillreg ar.fpsr, r18 + nop 0 +.spillreg ar.lc, r19 + nop 0 +.spillreg ar.pfs, r20 + nop 0 +.spillreg ar.rnat, r21 + nop 0 +.spillreg ar.unat, r22 + nop 0 +.spillreg psp, r23 + nop 0 +.spillreg pr, r24 + nop 0 +.spillreg rp, r25 + nop 0 +.spillreg @priunat, r26 + nop 0 + +.label_state 1 + nop 0 +.restore sp + nop.x 0 +.copy_state 1 + br.ret.sptk rp + +.personality personality +.handlerdata + data4 -1 + data4 0 + +.endp full1 + +.proc full2 +full2: + +.prologue 0xb, r8 +.spill 0 +.save.gf 0x1, 0x00001 + nop 0 + nop 0 +.save.b 0x11, r32 + nop 0 + nop 0 +.save.gf 0x8, 0x80000 + nop 0 + nop 0 +.spillreg f31, f127 + nop 0 +.spillreg.p p63, f16, f32 + nop 0 +.spillsp f5, 0x20 + nop 0 +.spillsp.p p31, f2, 0x18 + nop 0 +.spillpsp b5, 0x10 + nop 0 +.spillpsp.p p15, b1, 0x08 + nop 0 +.restorereg r7 + nop 0 +.restorereg.p p7, r4 + nop 0 + +.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue +.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue +.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue +.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue +.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue +.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue +.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue +.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue + +.body +.label_state 32 + nop 0 +.restore sp, 32 + nop.x 0 +.copy_state 32 + br.ret.sptk rp +.endp full2 + +.proc full3 +full3: + +.prologue +.spill 0 +.save.g 0x3, r32 + nop 0 + nop 0 +.save.b 0x03, r34 + nop 0 + nop 0 +.save.g 0xc, r124 + nop 0 + nop 0 +.save.b 0x18, r126 + nop 0 + nop 0 + nop.x 0 + nop.x 0 + nop.x 0 + nop.x 0 + nop.x 0 + nop.x 0 + nop.x 0 + nop.x 0 +.body + nop.x 0 + nop.x 0 + nop.x 0 + nop.x 0 + nop.x 0 + nop.x 0 + nop.x 0 + nop.x 0 + nop.x 0 + nop.x 0 + br.ret.sptk rp +.endp full3 + +.proc fframe +fframe: +.prologue +.fframe 0 + nop 0 +.body + br.ret.sptk rp +.endp fframe + +.proc vframe +vframe: +.prologue +.vframe r16 + nop 0 +.save ar.bsp, r17 + nop 0 +.save ar.bspstore, r18 + nop 0 +.save ar.fpsr, r19 + nop 0 +.save ar.lc, r20 + nop 0 +.save ar.pfs, r21 + nop 0 +.save ar.rnat, r22 + nop 0 +.save ar.unat, r23 + nop 0 +.save pr, r24 + nop 0 +.save @priunat, r25 + nop 0 +.save rp, r26 + nop 0 +.body + br.ret.sptk rp +.endp vframe + +.proc vframesp +vframesp: +.prologue +.vframesp 0 + nop 0 +.savesp ar.bsp, 0x08 + nop 0 +.savesp ar.bspstore, 0x10 + nop 0 +.savesp ar.fpsr, 0x18 + nop 0 +.savesp ar.lc, 0x20 + nop 0 +.savesp ar.pfs, 0x28 + nop 0 +.savesp ar.rnat, 0x30 + nop 0 +.savesp ar.unat, 0x38 + nop 0 +.savesp pr, 0x40 + nop 0 +.savesp @priunat, 0x48 + nop 0 +.savesp rp, 0x50 + nop 0 +.body + br.ret.sptk rp +.endp vframesp + +.proc psp +psp: +.prologue +.vframesp 0 + nop 0 +.savepsp ar.bsp, 0x08 + nop 0 +.savepsp ar.bspstore, 0x10 + nop 0 +.savepsp ar.fpsr, 0x18 + nop 0 +.savepsp ar.lc, 0x20 + nop 0 +.savepsp ar.pfs, 0x28 + nop 0 +.savepsp ar.rnat, 0x30 + nop 0 +.savepsp ar.unat, 0x38 + nop 0 +.savepsp pr, 0x40 + nop 0 +.savepsp @priunat, 0x48 + nop 0 +.savepsp rp, 0x50 + nop 0 +.body + br.ret.sptk rp +.endp psp + +.proc simple +simple: +.unwentry + br.ret.sptk rp +.endp simple diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/m32r/error.exp binutils-2.16.91.0.2/gas/testsuite/gas/m32r/error.exp --- binutils-2.16.91.0.1/gas/testsuite/gas/m32r/error.exp 2004-01-14 13:07:47.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/m32r/error.exp 2005-07-20 12:27:28.037070378 -0700 @@ -10,6 +10,7 @@ if [istarget m32r-*-*] { dg-runtest "$srcdir/$subdir/interfere.s" "" "" dg-runtest "$srcdir/$subdir/outofrange.s" "" "" dg-runtest "$srcdir/$subdir/parallel.s" "" "" + dg-runtest "$srcdir/$subdir/rel32-err.s" "" "" dg-finish diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/m32r/rel32.d binutils-2.16.91.0.2/gas/testsuite/gas/m32r/rel32.d --- binutils-2.16.91.0.1/gas/testsuite/gas/m32r/rel32.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/m32r/rel32.d 2005-07-20 12:27:28.038070214 -0700 @@ -0,0 +1,13 @@ +#as: +#objdump: -r +#name: rel32 + +.*: +file format .* + +RELOCATION RECORDS FOR \[.text2\]: +OFFSET TYPE VALUE +00000000 R_M32R_REL32 .text\+0x00000004 +00000008 R_M32R_REL32 .text\+0x00000008 +0000000c R_M32R_REL32 .text + + diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/m32r/rel32-err.s binutils-2.16.91.0.2/gas/testsuite/gas/m32r/rel32-err.s --- binutils-2.16.91.0.1/gas/testsuite/gas/m32r/rel32-err.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/m32r/rel32-err.s 2005-07-20 12:27:28.037070378 -0700 @@ -0,0 +1,10 @@ + +; { dg-do assemble { target m32r-*-* } } + + .text + nop + nop +bar: + .section .text2 + .2byte bar - . ; { dg-error "can't export reloc type 11" } + .byte bar - . ; { dg-error "can\'t export reloc type 7" } diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/m32r/rel32.exp binutils-2.16.91.0.2/gas/testsuite/gas/m32r/rel32.exp --- binutils-2.16.91.0.1/gas/testsuite/gas/m32r/rel32.exp 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/m32r/rel32.exp 2005-07-20 12:27:28.039070049 -0700 @@ -0,0 +1,6 @@ +# M32R R_M32R_REL32 testcases + +if [istarget m32r*-*-*] { + run_dump_test "rel32" + run_dump_test "rel32-pic" +} diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/m32r/rel32-pic.d binutils-2.16.91.0.2/gas/testsuite/gas/m32r/rel32-pic.d --- binutils-2.16.91.0.1/gas/testsuite/gas/m32r/rel32-pic.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/m32r/rel32-pic.d 2005-07-20 12:27:28.038070214 -0700 @@ -0,0 +1,13 @@ +#as: -KPIC +#objdump: -r +#name: rel32-pic + +.*: +file format .* + +RELOCATION RECORDS FOR \[.text2\]: +OFFSET TYPE VALUE +00000000 R_M32R_REL32 .text\+0x00000004 +00000008 R_M32R_REL32 .text\+0x00000008 +0000000c R_M32R_REL32 .text + + diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/m32r/rel32-pic.s binutils-2.16.91.0.2/gas/testsuite/gas/m32r/rel32-pic.s --- binutils-2.16.91.0.1/gas/testsuite/gas/m32r/rel32-pic.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/m32r/rel32-pic.s 2005-07-20 12:27:28.038070214 -0700 @@ -0,0 +1,12 @@ + .text + nop + nop +bar: + .section .text2 + .4byte bar - . +label: + nop + nop + .4byte bar - label + .4byte bar - label2 +label2: diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/m32r/rel32.s binutils-2.16.91.0.2/gas/testsuite/gas/m32r/rel32.s --- binutils-2.16.91.0.1/gas/testsuite/gas/m32r/rel32.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/m32r/rel32.s 2005-07-20 12:27:28.039070049 -0700 @@ -0,0 +1,12 @@ + .text + nop + nop +bar: + .section .text2 + .4byte bar - . +label: + nop + nop + .4byte bar - label + .4byte bar - label2 +label2: diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/mmix/relax1-n.d binutils-2.16.91.0.2/gas/testsuite/gas/mmix/relax1-n.d --- binutils-2.16.91.0.1/gas/testsuite/gas/mmix/relax1-n.d 2001-11-16 14:05:52.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/mmix/relax1-n.d 2005-07-20 12:27:28.046068895 -0700 @@ -2,8 +2,8 @@ #as: -no-expand -x #source: relax1.s # -# FIXME: This test-case assumes that out-of-range errors cause relocs to -# be emitted, rather than errors emitted. +# This test-case assumes that out-of-range errors cause relocs to +# be emitted, rather than errors emitted. FIXME. .*: file format elf64-mmix diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/mmix/relax1-rn.d binutils-2.16.91.0.2/gas/testsuite/gas/mmix/relax1-rn.d --- binutils-2.16.91.0.1/gas/testsuite/gas/mmix/relax1-rn.d 2001-11-16 14:05:52.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/mmix/relax1-rn.d 2005-07-20 12:27:28.046068895 -0700 @@ -2,8 +2,8 @@ #as: -linkrelax -no-expand -x #source: relax1.s # -# FIXME: This test-case assumes that out-of-range errors (still) cause -# relocs to be emitted, rather than errors emitted. +# This test-case assumes that out-of-range errors (still) cause +# relocs to be emitted, rather than errors emitted. FIXME. .*: file format elf64-mmix diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/allinsn.d binutils-2.16.91.0.2/gas/testsuite/gas/ms1/allinsn.d --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/allinsn.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/allinsn.d 2005-07-20 12:27:28.047068730 -0700 @@ -0,0 +1,130 @@ +#as: -nosched +#objdump: -dr +#name: allinsn + +.*: +file format .* + +Disassembly of section .text: + +00000000 : + 0: 00 00 00 00 add R0,R0,R0 + +00000004 : + 4: 02 00 00 00 addu R0,R0,R0 + +00000008 : + 8: 01 00 00 00 addi R0,R0,#\$0 + +0000000c : + c: 03 00 00 00 addui R0,R0,#\$0 + +00000010 : + 10: 04 00 00 00 sub R0,R0,R0 + +00000014 : + 14: 06 00 00 00 subu R0,R0,R0 + +00000018 : + 18: 05 00 00 00 subi R0,R0,#\$0 + +0000001c : + 1c: 07 00 00 00 subui R0,R0,#\$0 + +00000020 : + 20: 10 00 00 00 and R0,R0,R0 + +00000024 : + 24: 11 00 00 00 andi R0,R0,#\$0 + +00000028 : + 28: 12 01 00 00 or R0,R0,R1 + +0000002c : + 2c: 13 00 00 00 ori R0,R0,#\$0 + +00000030 : + 30: 14 00 00 00 xor R0,R0,R0 + +00000034 : + 34: 15 00 00 00 xori R0,R0,#\$0 + +00000038 : + 38: 16 00 00 00 nand R0,R0,R0 + +0000003c : + 3c: 17 00 00 00 nandi R0,R0,#\$0 + +00000040 : + 40: 18 00 00 00 nor R0,R0,R0 + +00000044 : + 44: 19 00 00 00 nori R0,R0,#\$0 + +00000048 : + 48: 1a 00 00 00 xnor R0,R0,R0 + +0000004c : + 4c: 1b 00 00 00 xnori R0,R0,#\$0 + +00000050 : + 50: 1d 00 00 00 ldui R0,#\$0 + +00000054 : + 54: 20 00 00 00 lsl R0,R0,R0 + +00000058 : + 58: 21 00 00 00 lsli R0,R0,#\$0 + +0000005c : + 5c: 22 00 00 00 lsr R0,R0,R0 + +00000060 : + 60: 23 00 00 00 lsri R0,R0,#\$0 + +00000064 : + 64: 24 00 00 00 asr R0,R0,R0 + +00000068 : + 68: 25 00 00 00 asri R0,R0,#\$0 + +0000006c : + 6c: 31 00 00 00 brlt R0,R0,\$0 + +00000070 : + 70: 33 00 00 00 brle R0,R0,\$0 + +00000074 : + 74: 35 00 00 00 breq R0,R0,\$0 + +00000078 : + 78: 37 00 00 00 jmp \$0 + +0000007c : + 7c: 38 00 00 00 jal R0,R0 + +00000080 : + 80: 60 00 00 00 ei + +00000084 : + 84: 62 00 00 00 di + +00000088 : + 88: 66 00 00 00 reti R0 + +0000008c : + 8c: 41 00 00 00 ldw R0,R0,#\$0 + +00000090 : + 90: 43 00 00 00 stw R0,R0,#\$0 + +00000094 : + 94: 64 00 00 00 si R0 + +00000098 : + 98: 3b 00 00 00 brne R0,R0,\$0 + +0000009c : + 9c: 68 00 00 00 break + +000000a0 : + a0: 12 00 00 00 nop diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/allinsn.s binutils-2.16.91.0.2/gas/testsuite/gas/ms1/allinsn.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/allinsn.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/allinsn.s 2005-07-20 12:27:28.047068730 -0700 @@ -0,0 +1,166 @@ + .data +foodata: .word 42 + .text +footext: + .text + .global add +add: + add R0,R0,R0 + .text + .global addu +addu: + addu R0,R0,R0 + .text + .global addi +addi: + addi R0,R0,#0 + .text + .global addui +addui: + addui R0,R0,#0 + .text + .global sub +sub: + sub R0,R0,R0 + .text + .global subu +subu: + subu R0,R0,R0 + .text + .global subi +subi: + subi R0,R0,#0 + .text + .global subui +subui: + subui R0,R0,#0 + .text + .global and +and: + and R0,R0,R0 + .text + .global andi +andi: + andi R0,R0,#0 + .text + .global or +or: + or R0,R0,R1 + .text + .global ori +ori: + ori R0,R0,#0 + .text + .global xor +xor: + xor R0,R0,R0 + .text + .global xori +xori: + xori R0,R0,#0 + .text + .global nand +nand: + nand R0,R0,R0 + .text + .global nandi +nandi: + nandi R0,R0,#0 + .text + .global nor +nor: + nor R0,R0,R0 + .text + .global nori +nori: + nori R0,R0,#0 + .text + .global xnor +xnor: + xnor R0,R0,R0 + .text + .global xnori +xnori: + xnori R0,R0,#0 + .text + .global ldui +ldui: + ldui R0,#0 + .text + .global lsl +lsl: + lsl R0,R0,R0 + .text + .global lsli +lsli: + lsli R0,R0,#0 + .text + .global lsr +lsr: + lsr R0,R0,R0 + .text + .global lsri +lsri: + lsri R0,R0,#0 + .text + .global asr +asr: + asr R0,R0,R0 + .text + .global asri +asri: + asri R0,R0,#0 + .text + .global brlt +brlt: + brlt R0,R0,0 + .text + .global brle +brle: + brle R0,R0,0 + .text + .global breq +breq: + breq R0,R0,0 + .text + .global jmp +jmp: + jmp 0 + .text + .global jal +jal: + jal R0,R0 + .text + .global ei +ei: + ei + .text + .global di +di: + di + .text + .global reti +reti: + reti R0 + .text + .global ldw +ldw: + ldw R0,R0,#0 + .text + .global stw +stw: + stw R0,R0,#0 + .text + .global si +si: + si R0 + .global brne +brne: + brne R0,R0,0 + .global break +break: + break + .text + .global nop +nop: + nop diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badinsn1.s binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badinsn1.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badinsn1.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badinsn1.s 2005-07-20 12:27:28.048068565 -0700 @@ -0,0 +1,3 @@ +; Extra operand should generate and error message. + +add R1,R2,R3,R4 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badinsn.s binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badinsn.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badinsn.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badinsn.s 2005-07-20 12:27:28.048068565 -0700 @@ -0,0 +1,3 @@ +; Bogus instruction mnemonic should generate an error. + +addcrap R1,R2,R3 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badoffsethigh.s binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badoffsethigh.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badoffsethigh.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badoffsethigh.s 2005-07-20 12:27:28.048068565 -0700 @@ -0,0 +1,4 @@ +; Offset greater than #32767 should cause an error since the offset is +; a signed quantity. + +brlt R1,R2,$32768 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badoffsetlow.s binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badoffsetlow.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badoffsetlow.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badoffsetlow.s 2005-07-20 12:27:28.048068565 -0700 @@ -0,0 +1,6 @@ +; Offset less than #-32786 should cause an error since the offset is +; a signed quantity. Also tests expression parsing. + +label1: add R1,R2,R3 +label2: add R4,R5,R6 + brlt R7,R8, ((label1-label2)-32765) ; evaluates to -32769 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badorder.s binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badorder.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badorder.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badorder.s 2005-07-20 12:27:28.049068400 -0700 @@ -0,0 +1,3 @@ +; Good operands in the wrong order should generate an error. + +addui R1, #32 R2 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badreg.s binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badreg.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badreg.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badreg.s 2005-07-20 12:27:28.049068400 -0700 @@ -0,0 +1,3 @@ +; Bad register name should generate an error. + +add R16,R10,R9 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badsignedimmhigh.s binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badsignedimmhigh.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badsignedimmhigh.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badsignedimmhigh.s 2005-07-20 12:27:28.049068400 -0700 @@ -0,0 +1,3 @@ +; Offset greater than #32767 should cause an error. + +addi R1,R2,#32768 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badsignedimmlow.s binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badsignedimmlow.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badsignedimmlow.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badsignedimmlow.s 2005-07-20 12:27:28.049068400 -0700 @@ -0,0 +1,3 @@ +; Immediate lower than #-32769 should cause an error. + +addi R1,R2,#-32769 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badsyntax1.s binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badsyntax1.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badsyntax1.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badsyntax1.s 2005-07-20 12:27:28.050068235 -0700 @@ -0,0 +1,3 @@ +; Good mnemonic with too few operands should generate an error. + +add R1,R2 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badsyntax.s binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badsyntax.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badsyntax.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badsyntax.s 2005-07-20 12:27:28.050068235 -0700 @@ -0,0 +1,3 @@ +; Good mnemonic with wrong operands should generate an error. + +add R1,R2,#0 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badunsignedimmhigh.s binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badunsignedimmhigh.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badunsignedimmhigh.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badunsignedimmhigh.s 2005-07-20 12:27:28.050068235 -0700 @@ -0,0 +1,3 @@ +; Offset greater than #$FFFF should cause an error. + +andi R1,R2,#$10000 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badunsignedimmlow.s binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badunsignedimmlow.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/badunsignedimmlow.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/badunsignedimmlow.s 2005-07-20 12:27:28.050068235 -0700 @@ -0,0 +1,3 @@ +; Offset less than #0 should cause an error. + +andi R1,R2,#-1 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/errors.exp binutils-2.16.91.0.2/gas/testsuite/gas/ms1/errors.exp --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/errors.exp 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/errors.exp 2005-07-20 12:27:28.051068070 -0700 @@ -0,0 +1,79 @@ +# Test for error messages when a bad register name, an out of range operand, or +# invalid syntax is used. Adapted from Ben Elliston's load-hazard testcase. + +# Run GAS and check that it emits the desired error for the test case. +# Arguments: +# file -- name of the test case to assemble. +# testname -- a string describing the test. +# warnpattern -- a regular expression, suitable for use by the Tcl +# regexp command, to decide if the warning string was emitted by +# the assembler to stderr. + +proc mrisc1_error_test { file testname {warnpattern ""} } { + global comp_output + + gas_run $file "" ">/dev/null" + verbose "output was $comp_output" 2 + + if {$warnpattern == ""} { + if {$comp_output == ""} { pass $testname } else { fail $testname } + return + } + + if {[regexp "Error: $warnpattern" $comp_output]} { + pass $testname + } else { + fail $testname + } +} + +if [istarget mrisc1*-*-*] { + foreach file [glob -nocomplain -- $srcdir/$subdir/bad*.s] { + set file [file tail $file] + switch -- $file { + "badreg.s" { + set warnpattern "unrecognized keyword/register name *" + } + "badorder.s" { + set warnpattern "unrecognized form of instruction*" + } + "badsyntax.s" { + set warnpattern "unrecognized keyword/register name *" + } + "badsyntax1.s" { + set warnpattern "unrecognized form of instruction*" + } + "badoffsethigh.s" { + set warnpattern "Operand out of range. Must be between -32768 and 32767.*" + } + "badoffsetlow.s" { + set warnpattern "Operand out of range. Must be between -32768 and 32767.*" + } + "badunsignedimmhigh.s" { + set warnpattern "operand out of range (65536 not between 0 and 65535)*" + } + "badunsignedimmlow.s" { + set warnpattern "operand out of range (65536 not between 0 and 65535)*" + } + "badsignedimmhigh.s" { + set warnpattern "operand out of range.*" + } + "badsignedimmlow.s" { + set warnpattern "operand out of range.*" + } + "badinsn.s" { + set warnpattern "unrecognized instruction *" + } + "badinsn1.s" { + set warnpattern "junk at end of line *" + } + default { + error "no expected result specified for $file" + return + + } + } + mrisc1_error_test $file "assembler emits error for $file" $warnpattern + } + +} diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/ldst.s binutils-2.16.91.0.2/gas/testsuite/gas/ms1/ldst.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/ldst.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/ldst.s 2005-07-20 12:27:28.051068070 -0700 @@ -0,0 +1,28 @@ +; load/store tests + + .data + +ldw_data: + .word 0xbabeface + + .text + +ld_text: + ld r4, r3 + ld r3, #8 + ld r5, #ld_text + ldh r6, #ldh_text + ldh r4, #4000 + ldh r5, #0x8000 + ldh r5, #-5 + ldh r5, #-0x8000 + ldh r0, #0xffff +ldh_text: + ldw r9, #30233000 + ldw r3, #ldw_data + ldb r3, @[r9+r2] + ldb @[r9+r3], r5 ; store + ldb r3, @[r8+6] + ldb @[r8+7], r3 ; store + ldw r9, @[r14+23] + ldw @[r14+10], r9 ; store diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/misc.d binutils-2.16.91.0.2/gas/testsuite/gas/ms1/misc.d --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/misc.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/misc.d 2005-07-20 12:27:28.056067246 -0700 @@ -0,0 +1,21 @@ +#as: +#objdump: -dr +#name: misc + +.*: +file format .* + +Disassembly of section .text: + +00000000 <.text>: + 0: 00 12 00 00 add R0,R1,R2 + 4: 00 12 00 00 add R0,R1,R2 + 8: 00 23 10 00 add R1,R2,R3 + c: 00 33 10 00 add R1,R3,R3 + 10: 00 56 40 00 add R4,R5,R6 + 14: 00 89 70 00 add R7,R8,R9 + 18: 00 bc a0 00 add R10,R11,R12 + 1c: 00 ef d0 00 add R13,R14,R15 + 20: 03 dc 00 01 addui R12,R13,#\$1 + 24: 03 fe 00 01 addui R14,R15,#\$1 + 28: 03 10 00 00 addui R0,R1,#\$0 + 2c: 03 10 ff ff addui R0,R1,#\$ffff diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/misc.s binutils-2.16.91.0.2/gas/testsuite/gas/ms1/misc.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/misc.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/misc.s 2005-07-20 12:27:28.057067081 -0700 @@ -0,0 +1,21 @@ +; Check that register names, both upper and lower case work and that +; the spacing between the operands doesn't matter. + +add R0,R1,R2 +add r0,r1,r2 +add R1,R2,r3 +add R1, R3, r3 +add R4,R5,R6 +add R7,R8,R9 +add R10,R11,R12 +add R13,R14,R15 +addui fp,sp,#1 +addui ra,ira,#1 + +; Check that the range of legal operand values is accepted. + +addui R0,R1,#0 +addui R0,R1,#$FFFF + + + diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/ms1-16-003.d binutils-2.16.91.0.2/gas/testsuite/gas/ms1/ms1-16-003.d --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/ms1-16-003.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/ms1-16-003.d 2005-07-20 12:27:28.057067081 -0700 @@ -0,0 +1,33 @@ +#as: -march=ms1-16-003 +#objdump: -dr +#name: ms1-16-003 + +.*: +file format .* + +Disassembly of section .text: + +00000000 : + 0: 6a 00 00 00 iflush +00000004 : + 4: 08 00 00 00 mul R0,R0,R0 +00000008 : + 8: 09 00 00 00 muli R0,R0,#\$0 +0000000c : + c: 3d 00 00 00 dbnz R0,\$0 +[ ]*c: R_MS1_PC16 dbnz +00000010 : + 10: f0 00 00 00 fbcbincs #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 +00000014 : + 14: f4 00 00 00 mfbcbincs R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 +00000018 : + 18: f8 00 00 00 fbcbincrs R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 +0000001c : + 1c: fc 00 00 00 mfbcbincrs R0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 +00000020 : + 20: e0 00 00 00 wfbinc #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 +00000024 : + 24: e4 00 00 00 mwfbinc R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 +00000028 : + 28: e8 00 00 00 wfbincr R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 +0000002c : + 2c: ec 00 00 00 mwfbincr R0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/ms1-16-003.s binutils-2.16.91.0.2/gas/testsuite/gas/ms1/ms1-16-003.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/ms1-16-003.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/ms1-16-003.s 2005-07-20 12:27:28.057067081 -0700 @@ -0,0 +1,54 @@ + .text + .global iflush +iflush: + iflush + + .global mul +mul: + mul R0, R0, R0 + + .global muli +muli: + muli R0, R0, #0 + + .global dbnz +dbnz: + dbnz r0, dbnz + + .global fbcbincs +fbcbincs: + fbcbincs #0, #0, #0, #0, #0, #0, #0, #0, #0, #0 + + .global mfbcbincs +mfbcbincs: + mfbcbincs r0, #0, #0, #0, #0, #0, #0, #0, #0 + + + .global fbcbincrs +fbcbincrs: + fbcbincrs r0, #0, #0, #0, #0, #0, #0, #0, #0, #0 + + .global mfbcbincrs +mfbcbincrs: + mfbcbincrs r0, r0, #0, #0, #0, #0, #0, #0, #0 + + + .global wfbinc +wfbinc: +# Documentation error. +# wfbinc #0, r0, #0, #0, #0, #0, #0, #0, #0, #0 + wfbinc #0, #0, #0, #0, #0, #0, #0, #0, #0, #0 + + .global mwfbinc +mwfbinc: +# Documentation error. +# mwfbinc r0, #0, #0, r0, #0, #0, #0, #0, #0 + mwfbinc r0, #0, #0, #0, #0, #0, #0, #0, #0 + + .global wfbincr +wfbincr: + wfbincr r0, #0, #0, #0, #0, #0, #0, #0, #0, #0 + + .global mwfbincr +mwfbincr: + mwfbincr r0, r0, #0, #0, #0, #0, #0, #0, #0 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/ms1.exp binutils-2.16.91.0.2/gas/testsuite/gas/ms1/ms1.exp --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/ms1.exp 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/ms1.exp 2005-07-20 12:27:28.058066916 -0700 @@ -0,0 +1,10 @@ +# MRISC1 assembler testsuite. + +if { [istarget mrisc1*-*-*] || [istarget ms1-*-*]} then { + # + run_dump_test "allinsn" + run_dump_test "misc" + run_dump_test "msys" + run_dump_test "ms1-16-003" + # +} diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/msys.d binutils-2.16.91.0.2/gas/testsuite/gas/ms1/msys.d --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/msys.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/msys.d 2005-07-20 12:27:28.058066916 -0700 @@ -0,0 +1,78 @@ +#as: -nosched +#objdump: -dr +#name: msys + +.*: +file format .* + +Disassembly of section .text: + +00000000 <.text>: + 0: 80 00 00 00 ldctxt R0,R0,#\$0,#\$0,#\$0 + 4: 84 00 00 00 ldfb R0,R0,#\$0 + 8: 88 00 00 00 stfb R0,R0,#\$0 + c: 8c 00 00 00 fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 10: 90 00 00 00 mfbcb R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0 + 14: 94 00 00 00 fbcci R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 18: 98 00 00 00 fbrci R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 1c: 9c 00 00 00 fbcri R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 20: a0 00 00 00 fbrri R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 24: a4 00 00 00 mfbcci R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0 + 28: a8 00 00 00 mfbrci R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0 + 2c: ac 00 00 00 mfbcri R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0 + 30: b0 00 00 00 mfbrri R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0 + 34: b4 00 00 00 fbcbdr R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 38: b8 00 00 00 rcfbcb #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 3c: bc 00 00 00 mrcfbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 40: c0 00 00 00 cbcast #\$0,#\$0,#\$0 + 44: c4 00 00 00 dupcbcast #\$0,#\$0,#\$0,#\$0 + 48: c8 00 00 00 wfbi #\$0,#\$0,#\$0,#\$0,#\$0 + 4c: cc 00 00 00 wfb R0,R0,#\$0,#\$0,#\$0 + 50: d0 00 00 00 rcrisc R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 54: d4 00 00 00 fbcbinc R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 58: d8 00 00 00 rcxmode R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 5c: 64 00 e0 00 si R14 + 60: b4 00 00 40 fbcbdr R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$1,#\$0 + 64: b4 00 00 00 fbcbdr R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 68: b4 00 00 40 fbcbdr R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$1,#\$0 + 6c: b4 00 00 00 fbcbdr R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 70: 64 00 e0 00 si R14 + 74: b8 08 00 00 rcfbcb #\$0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 78: b8 00 00 00 rcfbcb #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 7c: b8 08 00 00 rcfbcb #\$0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 80: b8 00 00 00 rcfbcb #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 84: 64 00 e0 00 si R14 + 88: bc 20 00 00 mrcfbcb R0,#\$0,#\$2,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 8c: bc 10 00 00 mrcfbcb R0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 90: bc 00 00 00 mrcfbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 94: bc 20 00 00 mrcfbcb R0,#\$0,#\$2,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 98: bc 10 00 00 mrcfbcb R0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 9c: bc 00 00 00 mrcfbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + a0: 64 00 e0 00 si R14 + a4: d8 80 00 00 rcxmode R0,#\$0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0 + a8: d8 00 00 00 rcxmode R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + ac: d8 80 00 00 rcxmode R0,#\$0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0 + b0: d8 00 00 00 rcxmode R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + b4: 64 00 e0 00 si R14 + b8: 80 00 80 00 ldctxt R0,R0,#\$1,#\$0,#\$0 + bc: 80 00 00 00 ldctxt R0,R0,#\$0,#\$0,#\$0 + c0: 80 00 80 00 ldctxt R0,R0,#\$1,#\$0,#\$0 + c4: 80 00 00 00 ldctxt R0,R0,#\$0,#\$0,#\$0 + c8: 8c 00 08 00 fbcb R0,#\$0,#\$0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0 + cc: 8c 00 00 00 fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + d0: c0 00 00 40 cbcast #\$0,#\$1,#\$0 + d4: c0 00 00 00 cbcast #\$0,#\$0,#\$0 + d8: 64 00 e0 00 si R14 + dc: 8c 00 04 00 fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$1,#\$0,#\$0,#\$0 + e0: 8c 00 00 00 fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + e4: 8c 00 04 00 fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$1,#\$0,#\$0,#\$0 + e8: 8c 00 00 00 fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + ec: 64 00 e0 00 si R14 + f0: 8f 00 00 00 fbcb R0,#\$3,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + f4: 8e 00 00 00 fbcb R0,#\$2,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + f8: 8d 00 00 00 fbcb R0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + fc: 8c 00 00 00 fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 100: 8f 00 00 00 fbcb R0,#\$3,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 104: 8e 00 00 00 fbcb R0,#\$2,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 108: 8d 00 00 00 fbcb R0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 10c: 8c 00 00 00 fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0 + 110: dc 00 00 00 intlvr R0,#\$0,R0,#\$0,#\$0 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/msys.s binutils-2.16.91.0.2/gas/testsuite/gas/ms1/msys.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/msys.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/msys.s 2005-07-20 12:27:28.059066751 -0700 @@ -0,0 +1,95 @@ +;; This file is a set of tests for the MorphoySys instructions. + +; Make sure that each mnemonic gives the proper opcode. Use R0 and #0 +; for all operands so that everything but the opcode will be 0 in the +; assembled instructions. + + ldctxt R0,R0,#0,#0,#0 + ldfb R0,R0,#0 + stfb R0, R0, #0 + fbcb R0,#0,#0,#0,#0,#0,#0,#0,#0 + mfbcb R0,#0,R0,#0,#0,#0,#0,#0 + fbcci R0,#0,#0,#0,#0,#0,#0,#0 + fbrci R0,#0,#0,#0,#0,#0,#0,#0 + fbcri R0,#0,#0,#0,#0,#0,#0,#0 + fbrri R0,#0,#0,#0,#0,#0,#0,#0 + mfbcci R0,#0,R0,#0,#0,#0,#0 + mfbrci R0,#0,R0,#0,#0,#0,#0 + mfbcri R0,#0,R0,#0,#0,#0,#0 + mfbrri R0,#0,R0,#0,#0,#0,#0 + fbcbdr R0,#0,R0,#0,#0,#0,#0,#0,#0,#0 + rcfbcb #0,#0,#0,#0,#0,#0,#0,#0,#0,#0 + mrcfbcb R0,#0,#0,#0,#0,#0,#0,#0,#0 + cbcast #0,#0,#0 + dupcbcast #0,#0,#0,#0 + wfbi #0,#0,#0,#0,#0 + wfb R0,R0,#0,#0,#0 + rcrisc R0,#0,R0,#0,#0,#0,#0,#0,#0 + fbcbinc R0, #0, #0, #0, #0, #0, #0, #0 + rcxmode R0, #0, #0, #0, #0, #0, #0, #0, #0 + +; Check to make sure that the parse routines that allow predifined +; symbols (uppaer and lower case) to be used for some of the operands. + +; dup operand: dup, xx + si R14 + fbcbdr R0,#0,R0,#0,#0,#0,#0,#0,#dup,#0 ; dup = 1 + fbcbdr R0,#0,R0,#0,#0,#0,#0,#0,#xx,#0 ; xx = 0 + fbcbdr R0,#0,R0,#0,#0,#0,#0,#0,#DUP,#0 + fbcbdr R0,#0,R0,#0,#0,#0,#0,#0,#XX,#0 + +; ball operand: all, one + si R14 + rcfbcb #0,#0,#all,#0,#0,#0,#0,#0,#0,#0 ; all = 1 + rcfbcb #0,#0,#one,#0,#0,#0,#0,#0,#0,#0 ; one = 0 + rcfbcb #0,#0,#ALL,#0,#0,#0,#0,#0,#0,#0 + rcfbcb #0,#0,#ONE,#0,#0,#0,#0,#0,#0,#0 + +; type operand: odd, even, oe + si R14 + mrcfbcb R0,#0,#oe,#0,#0,#0,#0,#0,#0 ; oe = 2 + mrcfbcb R0,#0,#even,#0,#0,#0,#0,#0,#0 ; even = 1 + mrcfbcb R0,#0,#odd,#0,#0,#0,#0,#0,#0 ; odd = 0 + mrcfbcb R0,#0,#OE,#0,#0,#0,#0,#0,#0 + mrcfbcb R0,#0,#EVEN,#0,#0,#0,#0,#0,#0 + mrcfbcb R0,#0,#ODD,#0,#0,#0,#0,#0,#0 + +; xmode operand: pm, xm + si R14 + rcxmode R0, #0, #0, #pm, #0, #0, #0, #0, #0 ; pm = 1 + rcxmode R0, #0, #0, #xm, #0, #0, #0, #0, #0 ; xm = 0 + rcxmode R0, #0, #0, #PM, #0, #0, #0, #0, #0 + rcxmode R0, #0, #0, #XM, #0, #0, #0, #0, #0 + +; rc, rc1, rc2 operands: r,c + si R14 + ldctxt R0,R0,#r,#0,#0 ; rc operand. r = 1 + ldctxt R0,R0,#c,#0,#0 ; rc operand. c = 0 + ldctxt R0,R0,#R,#0,#0 + ldctxt R0,R0,#C,#0,#0 + + fbcb R0,#0,#0,#0,#r,#0,#0,#0,#0 ; rc1 operand. r = 1 + fbcb R0,#0,#0,#0,#c,#0,#0,#0,#0 ; rc1 operand. c = 0 + + cbcast #0,#r,#0 ; rc2 operand. r = 1 + cbcast #0,#c,#0 ; rc2 opearnd. c = 0 + +; cbrb operand: cb, rb + si R14 + fbcb R0,#0,#0,#0,#0,#rb,#0,#0,#0 ; rb = 1 + fbcb R0,#0,#0,#0,#0,#cb,#0,#0,#0 ; cb = 0 + fbcb R0,#0,#0,#0,#0,#RB,#0,#0,#0 + fbcb R0,#0,#0,#0,#0,#CB,#0,#0,#0 + +; rbbc operand: rt, br1, br2, cs + si R14 + fbcb R0,#cs,#0,#0,#0,#0,#0,#0,#0 ; cs = 3 + fbcb R0,#br2,#0,#0,#0,#0,#0,#0,#0 ; br2 = 2 + fbcb R0,#br1,#0,#0,#0,#0,#0,#0,#0 ; br1 = 1 + fbcb R0,#rt,#0,#0,#0,#cb,#0,#0,#0 ; rt = 0 + fbcb R0,#CS,#0,#0,#0,#0,#0,#0,#0 + fbcb R0,#BR2,#0,#0,#0,#0,#0,#0,#0 + fbcb R0,#BR1,#0,#0,#0,#0,#0,#0,#0 + fbcb R0,#RT,#0,#0,#0,#cb,#0,#0,#0 + + intlvr R0, #0, R0, #0, #0 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/relocs1.s binutils-2.16.91.0.2/gas/testsuite/gas/ms1/relocs1.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/relocs1.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/relocs1.s 2005-07-20 12:27:28.060066586 -0700 @@ -0,0 +1,31 @@ +;; This test is meant to exercise every unusual reloc supported +;; by the mrisc port. (Ok, so there's only one so far. :P) + + .text +text: + .global _start +_start: + add R1,R1,R3 + +; Make sure local fixups work. +local: + jmp (dummy2-dummy1) + +; Test the PC16 reloc. +none: + or R0,R0,R0 ;nop to conform to scheduling restrictions + jmp local + +; Test the %hi16 and %lo16 relocs +addui R1,R2,#%hi16(d2) +addui R1,R2,#%lo16(d2) +addui R1,R2,#%hi16(65536) +addui R1,R2,#%lo16(65536) +addui R1,R2,#%hi16($FFFFEEEE) +addui R1,R2,#%lo16($FFFFEEEE) + +dummy1: addui R1, R2, #5 +dummy2: addui R1, R2, #6 + + .data +d1: .byte $f diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/relocs2.s binutils-2.16.91.0.2/gas/testsuite/gas/ms1/relocs2.s --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/relocs2.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/relocs2.s 2005-07-20 12:27:28.060066586 -0700 @@ -0,0 +1,22 @@ + .text + ;; Put code near the top of the address space +text: + .global i2 +i2: + + add R5, R6, R7 + + .data + ;; Note that the .org that follows is more or less equivalent + ;; to a .space, since the amount specified will be treated like + ;; padding to be added between the .data section in relocs1.s + ;; and this one. + ;; Note also that the two test variables (d2 & d3) are intentionally + ;; roughly $100 apart, so that the FR9 relocation processing in + ;; bfd/elf32-ip2k.c (ip2k_final_link_relocate) is tested a little more. + .org $e0 + .global d2 +d2: .byte 2 + .space $100 + .global d3 +d3: .byte 3 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/relocs.d binutils-2.16.91.0.2/gas/testsuite/gas/ms1/relocs.d --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/relocs.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/relocs.d 2005-07-20 12:27:28.059066751 -0700 @@ -0,0 +1,67 @@ + +relocs.x: file format elf32-mrisc1 + +Contents of section .text: + 2000 00131000 37000004 12000000 3700fff8 ....7.......7... + 2010 03210000 03212215 03210001 03210000 .!...!"..!...!.. + 2020 0321ffff 0321eeee 03210005 03210006 .!...!...!...!.. + 2030 00675000 .gP. +Contents of section .data: + 2134 0f000000 00000000 00000000 00000000 ................ + 2144 00000000 00000000 00000000 00000000 ................ + 2154 00000000 00000000 00000000 00000000 ................ + 2164 00000000 00000000 00000000 00000000 ................ + 2174 00000000 00000000 00000000 00000000 ................ + 2184 00000000 00000000 00000000 00000000 ................ + 2194 00000000 00000000 00000000 00000000 ................ + 21a4 00000000 00000000 00000000 00000000 ................ + 21b4 00000000 00000000 00000000 00000000 ................ + 21c4 00000000 00000000 00000000 00000000 ................ + 21d4 00000000 00000000 00000000 00000000 ................ + 21e4 00000000 00000000 00000000 00000000 ................ + 21f4 00000000 00000000 00000000 00000000 ................ + 2204 00000000 00000000 00000000 00000000 ................ + 2214 00020000 00000000 00000000 00000000 ................ + 2224 00000000 00000000 00000000 00000000 ................ + 2234 00000000 00000000 00000000 00000000 ................ + 2244 00000000 00000000 00000000 00000000 ................ + 2254 00000000 00000000 00000000 00000000 ................ + 2264 00000000 00000000 00000000 00000000 ................ + 2274 00000000 00000000 00000000 00000000 ................ + 2284 00000000 00000000 00000000 00000000 ................ + 2294 00000000 00000000 00000000 00000000 ................ + 22a4 00000000 00000000 00000000 00000000 ................ + 22b4 00000000 00000000 00000000 00000000 ................ + 22c4 00000000 00000000 00000000 00000000 ................ + 22d4 00000000 00000000 00000000 00000000 ................ + 22e4 00000000 00000000 00000000 00000000 ................ + 22f4 00000000 00000000 00000000 00000000 ................ + 2304 00000000 00000000 00000000 00000000 ................ + 2314 000003 ... +Contents of section .sbss: +Disassembly of section .text: + +00002000 <_start>: + 2000: 00 13 10 00 add R1,R1,R3 + +00002004 : + 2004: 37 00 00 04 jmp \$4 + +00002008 : + 2008: 12 00 00 00 or R0,R0,R0 + 200c: 37 00 ff f8 jmp \$fffffff8 + 2010: 03 21 00 00 addui R1,R2,#\$0 + 2014: 03 21 22 15 addui R1,R2,#\$2215 + 2018: 03 21 00 01 addui R1,R2,#\$1 + 201c: 03 21 00 00 addui R1,R2,#\$0 + 2020: 03 21 ff ff addui R1,R2,#\$ffff + 2024: 03 21 ee ee addui R1,R2,#\$eeee + +00002028 : + 2028: 03 21 00 05 addui R1,R2,#\$5 + +0000202c : + 202c: 03 21 00 06 addui R1,R2,#\$6 + +00002030 : + 2030: 00 67 50 00 add R5,R6,R7 diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ms1/relocs.exp binutils-2.16.91.0.2/gas/testsuite/gas/ms1/relocs.exp --- binutils-2.16.91.0.1/gas/testsuite/gas/ms1/relocs.exp 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ms1/relocs.exp 2005-07-20 12:27:28.059066751 -0700 @@ -0,0 +1,35 @@ +# Relocation test. +# This test is special because it exercises the linker's + +proc ld_test { objects ldflags dest test } { + set ld_output [target_link $objects $dest $ldflags] + if [string match "" $ld_output] then { pass $test } else { fail $test } +} + + +proc objdump_test { exec flags dest test } { + set objcopy [find_binutils_prog objdump] + verbose -log "$objcopy $flags $exec > $dest" + catch "exec $objcopy $flags $exec > $dest" objdump_output + if [string match "" $objdump_output] then { pass $test } else { fail $test } +} + +proc regexp_test { file1 file2 test } { + if [regexp_diff $file1 $file2] then { fail $test } else { pass $test } +} + + +global srcdir subdir +if [istarget mrisc1*-*-* || istarget ms1-*] { + gas_test "relocs1.s" {-o relocs1.o} {} {assembling relocs1} + + # gas_test "relocs2.s" {-o relocs2.o} {} {assembling relocs2} + # ld_test {relocs1.o relocs2.o} {} {relocs.x} {linking relocs.x} + # objdump_test {relocs.x} {-ds} {relocs.dump} {disassembling relocs.x} + # regexp_test {relocs.dump} "$srcdir/$subdir/relocs.d" {matching disassembly} + + gas_test "relocs2.s" {-o relocs2.o} {} {assembling relocs2} + ld_test {relocs1.o relocs2.o} {} {relocs.x} {linking relocs.x} + objdump_test {relocs.x} {-ds} {relocs.dump} {disassembling relocs.x} + regexp_test {relocs.dump} "$srcdir/$subdir/relocs.d" {matching disassembly} +} diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ppc/altivec.d binutils-2.16.91.0.2/gas/testsuite/gas/ppc/altivec.d --- binutils-2.16.91.0.1/gas/testsuite/gas/ppc/altivec.d 2004-04-12 12:56:35.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ppc/altivec.d 2005-07-20 12:27:28.065065762 -0700 @@ -2,7 +2,7 @@ #objdump: -dr #name: AltiVec tests -.*: +file format elf32-powerpc +.*: +file format elf32-powerpc.* Disassembly of section \.text: diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ppc/booke.d binutils-2.16.91.0.2/gas/testsuite/gas/ppc/booke.d --- binutils-2.16.91.0.1/gas/testsuite/gas/ppc/booke.d 2005-04-09 12:03:14.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ppc/booke.d 2005-07-20 12:27:28.068065267 -0700 @@ -2,7 +2,7 @@ #objdump: -dr -Mbooke #name: BookE tests -.*: +file format elf(32)?(64)?-powerpc +.*: +file format elf(32)?(64)?-powerpc.* Disassembly of section \.text: diff -uprN binutils-2.16.91.0.1/gas/testsuite/gas/ppc/e500.d binutils-2.16.91.0.2/gas/testsuite/gas/ppc/e500.d --- binutils-2.16.91.0.1/gas/testsuite/gas/ppc/e500.d 2005-04-09 12:03:14.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/gas/ppc/e500.d 2005-07-20 12:27:28.068065267 -0700 @@ -2,7 +2,7 @@ #objdump: -dr -Me500 #name: e500 tests -.*: +file format elf(32)?(64)?-powerpc +.*: +file format elf(32)?(64)?-powerpc.* Disassembly of section \.text: diff -uprN binutils-2.16.91.0.1/gas/testsuite/lib/gas-defs.exp binutils-2.16.91.0.2/gas/testsuite/lib/gas-defs.exp --- binutils-2.16.91.0.1/gas/testsuite/lib/gas-defs.exp 2005-05-10 15:46:47.000000000 -0700 +++ binutils-2.16.91.0.2/gas/testsuite/lib/gas-defs.exp 2005-07-20 12:27:28.075064113 -0700 @@ -233,6 +233,24 @@ proc is_elf_format {} { return 1 } +# run_dump_tests TESTCASES EXTRA_OPTIONS +# Wrapper for run_dump_test, which is suitable for invoking as +# run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]] +# EXTRA_OPTIONS are passed down to run_dump_test. Honors runtest_file_p. +# Body cribbed from dg-runtest. + +proc run_dump_tests { testcases {extra_options {}} } { + global runtests + + foreach testcase $testcases { + # If testing specific files and this isn't one of them, skip it. + if ![runtest_file_p $runtests $testcase] { + continue + } + run_dump_test [file rootname [file tail $testcase]] $extra_options + } +} + # run_dump_test FILE (optional:) EXTRA_OPTIONS # @@ -255,8 +273,10 @@ proc is_elf_format {} { # OPTION is the name of some option, like "name" or "objdump", and # VALUE is OPTION's value. The valid options are described below. # Whitespace is ignored everywhere, except within VALUE. The option -# list ends with the first line that doesn't match the above syntax -# (hmm, not great for error detection). +# list ends with the first line that doesn't match the above syntax. +# However, a line within the options that begins with a #, but doesn't +# have a recognizable option name followed by a colon, is considered a +# comment and entirely ignored. # # The optional EXTRA_OPTIONS argument to `run_dump_test' is a list of # two-element lists. The first element of each is an option name, and @@ -292,6 +312,27 @@ proc is_elf_format {} { # Assemble the file SOURCE.s. If omitted, this defaults to FILE.s. # This is useful if several .d files want to share a .s file. # +# target: GLOBS... +# Run this test only on a specified list of targets. More precisely, +# each glob in the space-separated list is passed to "istarget"; if +# it evaluates true for any of them, the test will be run, otherwise +# it will be marked unsupported. +# +# not-target: GLOBS... +# Do not run this test on a specified list of targets. Again, +# the each glob in the space-separated list is passed to +# "istarget", and the test is run if it evaluates *false* for +# *all* of them. Otherwise it will be marked unsupported. +# +# skip: GLOBS... +# not-skip: GLOBS... +# These are exactly the same as "not-target" and "target", +# respectively, except that they do nothing at all if the check +# fails. They should only be used in groups, to construct a single +# test which is run on all targets but with variant options or +# expected output on some targets. (For example, see +# gas/arm/inst.d and gas/arm/wince_inst.d.) +# # error: REGEX # An error with message matching REGEX must be emitted for the test # to pass. The PROG, objdump, nm and objcopy options have no @@ -301,6 +342,16 @@ proc is_elf_format {} { # Expect a gas warning matching REGEX. It is an error to issue # both "error" and "warning". # +# stderr: FILE +# FILE contains regexp lines to be matched against the diagnostic +# output of the assembler. This does not preclude the use of +# PROG, nm, objdump, or objcopy. +# +# error-output: FILE +# Means the same as 'stderr', but also indicates that the assembler +# is expected to exit unsuccessfully (therefore PROG, objdump, nm, +# and objcopy have no meaning and should not be supplied). +# # Each option may occur at most once. # # After the option lines come regexp lines. `run_dump_test' calls @@ -337,7 +388,12 @@ proc run_dump_test { name {extra_options set opts(source) {} set opts(stderr) {} set opts(error) {} + set opts(error-output) {} set opts(warning) {} + set opts(target) {} + set opts(not-target) {} + set opts(skip) {} + set opts(not-skip) {} foreach i $opt_array { set opt_name [lindex $i 0] @@ -371,16 +427,30 @@ proc run_dump_test { name {extra_options append opts($opt_name) $opt_val } + if { $opts(name) == "" } { + set testname "$subdir/$name" + } else { + set testname $opts(name) + } + verbose "Testing $testname" + if { (($opts(warning) != "") && ($opts(error) != "")) \ - || (($opts(warning) != "") && ($opts(stderr) != "")) } { - perror "$testname: bad mix of stderr, error and warning test-directives" + || (($opts(warning) != "") && ($opts(stderr) != "")) \ + || (($opts(error-output) != "") && ($opts(stderr) != "")) \ + || (($opts(error-output) != "") && ($opts(error) != "")) \ + || (($opts(error-output) != "") && ($opts(warning) != "")) } { + perror "$testname: bad mix of stderr, error-output, error, and warning test-directives" + unresolved $testname return } + if { $opts(error-output) != "" } then { + set opts(stderr) $opts(error-output) + } set program "" # It's meaningless to require an output-testing method when we # expect an error. - if { $opts(error) == "" } { + if { $opts(error) == "" && $opts(error-output) == "" } { if {$opts(PROG) != ""} { switch -- $opts(PROG) { objdump { set program objdump } @@ -389,7 +459,7 @@ proc run_dump_test { name {extra_options readelf { set program readelf } default { perror "unrecognized program option $opts(PROG) in $file.d" - unresolved $subdir/$name + unresolved $testname return } } } else { @@ -398,7 +468,7 @@ proc run_dump_test { name {extra_options if {$opts($p) != ""} { if {$program != ""} { perror "ambiguous dump program in $file.d" - unresolved $subdir/$name + unresolved $testname return } else { set program $p @@ -408,17 +478,62 @@ proc run_dump_test { name {extra_options } if { $program == "" && $opts(warning) == "" } { perror "dump program unspecified in $file.d" - unresolved $subdir/$name + unresolved $testname return } } - if { $opts(name) == "" } { - set testname "$subdir/$name" - } else { - set testname $opts(name) + # Handle skipping the test on specified targets. + # You can have both skip/not-skip and target/not-target, but you can't + # have both skip and not-skip, or target and not-target, in the same file. + if { $opts(skip) != "" } then { + if { $opts(not-skip) != "" } then { + perror "$testname: mixing skip and not-skip directives is invalid" + unresolved $testname + return + } + foreach glob $opts(skip) { + if {[istarget $glob]} { return } + } + } + if { $opts(not-skip) != "" } then { + set skip 1 + foreach glob $opts(not-skip) { + if {[istarget $glob]} { + set skip 0 + break + } + } + if {$skip} { return } + } + if { $opts(target) != "" } then { + if { $opts(not-target) != "" } then { + perror "$testname: mixing target and not-target directives is invalid" + unresolved $testname + return + } + set skip 1 + foreach glob $opts(target) { + if {[istarget $glob]} { + set skip 0 + break + } + } + if {$skip} { + unsupported $testname + return + } + } + if { $opts(not-target) != "" } then { + foreach glob $opts(not-target) { + if {[istarget $glob]} { + unsupported $testname + return + } + } } + if { $opts(source) == "" } { set sourcefile ${file}.s } else { @@ -449,10 +564,9 @@ proc run_dump_test { name {extra_options set exitstat "succeeded" if { $cmdret != 0 } { set exitstat "failed" } + send_log "$comp_output\n" + verbose "$comp_output" 3 if { $opts(stderr) == "" } then { - send_log "$comp_output\n" - verbose "$comp_output" 3 - if { [regexp $expmsg $comp_output] \ && (($cmdret == 0) == ($opts(warning) != "")) } { # We have the expected output from gas. @@ -478,7 +592,6 @@ proc run_dump_test { name {extra_options return } set stderrfile $srcdir/$subdir/$opts(stderr) - send_log "wrote pruned stderr to dump.stderr\n" verbose "wrote pruned stderr to dump.stderr" 3 if { [regexp_diff "dump.stderr" "$stderrfile"] } then { if { $opts(error) != "" } { @@ -491,6 +604,9 @@ proc run_dump_test { name {extra_options fail $testname verbose "pruned stderr is [file_contents "dump.stderr"]" 2 return + } elseif { $opts(error-output) != "" } then { + pass $testname + return } } } @@ -557,15 +673,15 @@ proc slurp_options { file } { set ws {[ ]*} set nws {[^ ]*} # whitespace is ignored anywhere except within the options list; - # option names are alphabetic only - set pat "^#${ws}(\[a-zA-Z\]*)$ws:${ws}(.*)$ws\$" + # option names are alphabetic plus dash + set pat "^#${ws}(\[a-zA-Z-\]*)$ws:${ws}(.*)$ws\$" while { [gets $f line] != -1 } { set line [string trim $line] # Whitespace here is space-tab. if [regexp $pat $line xxx opt_name opt_val] { # match! lappend opt_array [list $opt_name $opt_val] - } else { + } elseif {![regexp "^#" $line ]} { break } } diff -uprN binutils-2.16.91.0.1/include/ansidecl.h binutils-2.16.91.0.2/include/ansidecl.h --- binutils-2.16.91.0.1/include/ansidecl.h 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/include/ansidecl.h 2005-07-20 12:27:28.079063454 -0700 @@ -352,6 +352,15 @@ So instead we use the macro below and te # endif /* GNUC >= 3.5 */ #endif /* ATTRIBUTE_SENTINEL */ + +#ifndef ATTRIBUTE_ALIGNED_ALIGNOF +# if (GCC_VERSION >= 3000) +# define ATTRIBUTE_ALIGNED_ALIGNOF(m) __attribute__ ((__aligned__ (__alignof__ (m)))) +# else +# define ATTRIBUTE_ALIGNED_ALIGNOF(m) +# endif /* GNUC >= 3.0 */ +#endif /* ATTRIBUTE_ALIGNED_ALIGNOF */ + /* We use __extension__ in some places to suppress -pedantic warnings about GCC extensions. This feature didn't work properly before gcc 2.8. */ diff -uprN binutils-2.16.91.0.1/include/ChangeLog binutils-2.16.91.0.2/include/ChangeLog --- binutils-2.16.91.0.1/include/ChangeLog 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/include/ChangeLog 2005-07-20 12:27:28.078063619 -0700 @@ -1,3 +1,28 @@ +2005-07-14 Jim Blandy + + * dis-asm.h (print_insn_m32c): New declaration. + +2005-07-12 Ben Elliston + + * xregex2.h (regexec): Qualify this prototype with __extension__ + when compiling with GNU C. + +2005-07-07 Kaveh R. Ghazi + + * dis-asm.h (fprintf_ftype): Add format attribute. + +2005-07-03 Steve Ellcey + + PR other/13906 + * ansidecl.h (ATTRIBUTE_ALIGNED_ALIGNOF): New. + * md5.h (md5_uintptr): New. + (md5_ctx): Align buffer field. + +2005-06-30 Daniel Berlin + + * hashtab.h (HTAB_DELETED_ENTRY): New macro. + (HTAB_EMPTY_ENTRY): New macro. + 2005-06-20 Geoffrey Keating * libiberty.h (strverscmp): Prototype. diff -uprN binutils-2.16.91.0.1/include/coff/alpha.h binutils-2.16.91.0.2/include/coff/alpha.h --- binutils-2.16.91.0.1/include/coff/alpha.h 2005-05-10 15:46:50.000000000 -0700 +++ binutils-2.16.91.0.2/include/coff/alpha.h 2005-07-20 12:27:28.095060816 -0700 @@ -1,7 +1,7 @@ /* ECOFF support on Alpha machines. coff/ecoff.h must be included before this file. - Copyright 2001 Free Software Foundation, Inc. + Copyright 2001, 2005 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -34,6 +34,9 @@ struct external_filehdr #define ALPHA_ECOFF_BADMAG(x) \ ((x).f_magic != ALPHA_MAGIC && (x).f_magic != ALPHA_MAGIC_BSD) +#define ALPHA_ECOFF_COMPRESSEDMAG(x) \ + ((x).f_magic == ALPHA_MAGIC_COMPRESSED) + /* The object type is encoded in the f_flags. */ #define F_ALPHA_OBJECT_TYPE_MASK 0x3000 #define F_ALPHA_NO_SHARED 0x1000 diff -uprN binutils-2.16.91.0.1/include/coff/ChangeLog binutils-2.16.91.0.2/include/coff/ChangeLog --- binutils-2.16.91.0.1/include/coff/ChangeLog 2005-05-10 15:46:50.000000000 -0700 +++ binutils-2.16.91.0.2/include/coff/ChangeLog 2005-07-20 12:27:28.094060981 -0700 @@ -1,3 +1,8 @@ +2005-07-14 Daniel Marques + + * alpha.h (ALPHA_ECOFF_COMPRESSEDMAG): Define. + * ecoff.h (ALPHA_MAGIC_COMPRESSED): Define. + 2005-05-10 Nick Clifton * Update the address and phone number of the FSF organization in diff -uprN binutils-2.16.91.0.1/include/coff/ecoff.h binutils-2.16.91.0.2/include/coff/ecoff.h --- binutils-2.16.91.0.1/include/coff/ecoff.h 2005-05-10 15:46:50.000000000 -0700 +++ binutils-2.16.91.0.2/include/coff/ecoff.h 2005-07-20 12:27:28.096060651 -0700 @@ -2,7 +2,7 @@ This does not include symbol information, found in sym.h and symconst.h. - Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc. + Copyright 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -41,6 +41,8 @@ /* Alpha magic numbers used in filehdr. */ #define ALPHA_MAGIC 0x183 #define ALPHA_MAGIC_BSD 0x185 +/* A compressed version of an ALPHA_MAGIC file created by DEC's tools. */ +#define ALPHA_MAGIC_COMPRESSED 0x188 /* Magic numbers used in a.out header. */ #define ECOFF_AOUT_OMAGIC 0407 /* not demand paged (ld -N). */ diff -uprN binutils-2.16.91.0.1/include/dis-asm.h binutils-2.16.91.0.2/include/dis-asm.h --- binutils-2.16.91.0.1/include/dis-asm.h 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/include/dis-asm.h 2005-07-20 12:27:28.080063289 -0700 @@ -35,7 +35,7 @@ extern "C" { #include #include "bfd.h" -typedef int (*fprintf_ftype) (void *, const char*, ...); +typedef int (*fprintf_ftype) (void *, const char*, ...) ATTRIBUTE_FPTR_PRINTF_2; enum dis_insn_type { dis_noninsn, /* Not a valid instruction */ @@ -264,6 +264,7 @@ extern int print_insn_sh64 (bfd_vma, di extern int print_insn_sh64x_media (bfd_vma, disassemble_info *); extern int print_insn_frv (bfd_vma, disassemble_info *); extern int print_insn_iq2000 (bfd_vma, disassemble_info *); +extern int print_insn_m32c (bfd_vma, disassemble_info *); extern disassembler_ftype arc_get_disassembler (void *); extern disassembler_ftype cris_get_disassembler (bfd *); diff -uprN binutils-2.16.91.0.1/include/elf/ChangeLog binutils-2.16.91.0.2/include/elf/ChangeLog --- binutils-2.16.91.0.1/include/elf/ChangeLog 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/include/elf/ChangeLog 2005-07-20 12:27:28.097060486 -0700 @@ -1,3 +1,18 @@ +2005-07-20 Kazuhiro Inaoka + + * m32r.h (R_M32R_REL32): Added. + +2005-07-18 Ben Elliston + + * dwarf2.h (enum dwarf_type): Remove DW_AT_GNU_decimal_float. + Replace with DW_ATE_decimal_float (now in DWARF 3). + +2005-07-14 Jim Blandy + + Add support for Renesas M32C and M16C. + * common.h (EM_M32C): New machine number. + * m32c.h: New file. + 2005-06-17 Jan Beulich * x86-64.h (elf_x86_64_reloc_type): Adjust comment for diff -uprN binutils-2.16.91.0.1/include/elf/common.h binutils-2.16.91.0.2/include/elf/common.h --- binutils-2.16.91.0.1/include/elf/common.h 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/include/elf/common.h 2005-07-20 12:27:28.098060321 -0700 @@ -211,6 +211,9 @@ /* (Deprecated) Temporary number for the OpenRISC processor. */ #define EM_OR32 0x8472 +/* Renesas M32C and M16C. */ +#define EM_M32C 0xFEB0 + /* Cygnus M32R ELF backend. Written in the absence of an ABI. */ #define EM_CYGNUS_M32R 0x9041 diff -uprN binutils-2.16.91.0.1/include/elf/dwarf2.h binutils-2.16.91.0.2/include/elf/dwarf2.h --- binutils-2.16.91.0.1/include/elf/dwarf2.h 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/include/elf/dwarf2.h 2005-07-20 12:27:28.099060156 -0700 @@ -547,6 +547,7 @@ enum dwarf_type DW_ATE_unsigned_char = 0x8, /* DWARF 3. */ DW_ATE_imaginary_float = 0x9, + DW_ATE_decimal_float = 0xf, /* HP extensions. */ DW_ATE_HP_float80 = 0x80, /* Floating-point (80 bit). */ DW_ATE_HP_complex_float80 = 0x81, /* Complex floating-point (80 bit). */ @@ -554,9 +555,7 @@ enum dwarf_type DW_ATE_HP_complex_float128 = 0x83, /* Complex floating-point (128 bit). */ DW_ATE_HP_floathpintel = 0x84, /* Floating-point (82 bit IA64). */ DW_ATE_HP_imaginary_float80 = 0x85, - DW_ATE_HP_imaginary_float128 = 0x86, - /* GNU extensions. */ - DW_ATE_GNU_decimal_float = 0x87 /* Pending DWARF working group. */ + DW_ATE_HP_imaginary_float128 = 0x86 }; #define DW_ATE_lo_user 0x80 diff -uprN binutils-2.16.91.0.1/include/elf/m32c.h binutils-2.16.91.0.2/include/elf/m32c.h --- binutils-2.16.91.0.1/include/elf/m32c.h 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/include/elf/m32c.h 2005-07-20 12:27:28.099060156 -0700 @@ -0,0 +1,49 @@ +/* M32C ELF support for BFD. + Copyright (C) 2004 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_M32C_H +#define _ELF_M32C_H + +#include "elf/reloc-macros.h" + + /* Relocations. */ + START_RELOC_NUMBERS (elf_m32c_reloc_type) + RELOC_NUMBER (R_M32C_NONE, 0) + RELOC_NUMBER (R_M32C_16, 1) + RELOC_NUMBER (R_M32C_24, 2) + RELOC_NUMBER (R_M32C_32, 3) + RELOC_NUMBER (R_M32C_8_PCREL, 4) + RELOC_NUMBER (R_M32C_16_PCREL, 5) + END_RELOC_NUMBERS (R_M32C_max) + +#define EF_M32C_CPU_M16C 0x00000075 /* default */ +#define EF_M32C_CPU_M32C 0x00000078 /* m32c */ +#define EF_M32C_CPU_MASK 0x0000007F /* specific cpu bits */ +#define EF_M32C_ALL_FLAGS (EF_M32C_CPU_MASK) + +/* Define the data & instruction memory discriminator. In a linked + executable, an symbol should be deemed to point to an instruction + if ((address & M16C_INSN_MASK) == M16C_INSN_VALUE), and similarly + for the data space. See also `ld/emulparams/elf32m32c.sh'. */ +#define M32C_DATA_MASK 0xffc00000 +#define M32C_DATA_VALUE 0x00000000 +#define M32C_INSN_MASK 0xffc00000 +#define M32C_INSN_VALUE 0x00400000 + +#endif /* _ELF_M32C_H */ diff -uprN binutils-2.16.91.0.1/include/elf/m32r.h binutils-2.16.91.0.2/include/elf/m32r.h --- binutils-2.16.91.0.1/include/elf/m32r.h 2005-05-10 15:46:52.000000000 -0700 +++ binutils-2.16.91.0.2/include/elf/m32r.h 2005-07-20 12:27:28.109058508 -0700 @@ -52,6 +52,8 @@ START_RELOC_NUMBERS (elf_m32r_reloc_type RELOC_NUMBER (R_M32R_SDA16_RELA, 42) RELOC_NUMBER (R_M32R_RELA_GNU_VTINHERIT, 43) RELOC_NUMBER (R_M32R_RELA_GNU_VTENTRY, 44) + + RELOC_NUMBER (R_M32R_REL32, 45) RELOC_NUMBER (R_M32R_GOT24, 48) RELOC_NUMBER (R_M32R_26_PLTREL, 49) @@ -70,6 +72,7 @@ START_RELOC_NUMBERS (elf_m32r_reloc_type RELOC_NUMBER (R_M32R_GOTOFF_HI_ULO, 62) RELOC_NUMBER (R_M32R_GOTOFF_HI_SLO, 63) RELOC_NUMBER (R_M32R_GOTOFF_LO, 64) + END_RELOC_NUMBERS (R_M32R_max) /* Processor specific section indices. These sections do not actually diff -uprN binutils-2.16.91.0.1/include/gdb/callback.h binutils-2.16.91.0.2/include/gdb/callback.h --- binutils-2.16.91.0.1/include/gdb/callback.h 2005-04-09 12:03:17.000000000 -0700 +++ binutils-2.16.91.0.2/include/gdb/callback.h 2005-07-20 12:27:28.112058013 -0700 @@ -50,11 +50,7 @@ Foundation, Inc., 59 Temple Place - Suit #ifndef va_start #include -#ifdef ANSI_PROTOTYPES #include -#else -#include -#endif #endif /* Needed for enum bfd_endian. */ #include "bfd.h" diff -uprN binutils-2.16.91.0.1/include/gdb/ChangeLog binutils-2.16.91.0.2/include/gdb/ChangeLog --- binutils-2.16.91.0.1/include/gdb/ChangeLog 2005-04-09 12:03:17.000000000 -0700 +++ binutils-2.16.91.0.2/include/gdb/ChangeLog 2005-07-20 12:27:28.112058013 -0700 @@ -1,3 +1,7 @@ +2005-07-08 Ben Elliston + + * callback.h: Remove ANSI_PROTOTYPES conditional code. + 2005-01-28 Hans-Peter Nilsson * callback.h (struct host_callback_struct): New members pipe, diff -uprN binutils-2.16.91.0.1/include/gdb/sim-m32c.h binutils-2.16.91.0.2/include/gdb/sim-m32c.h --- binutils-2.16.91.0.1/include/gdb/sim-m32c.h 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/include/gdb/sim-m32c.h 2005-07-20 12:27:28.113057848 -0700 @@ -0,0 +1,63 @@ +/* This file defines the interface between the m32c simulator and gdb. + Copyright (C) 2005 Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef SIM_M32C_H +#define SIM_M32C_H + +enum m32c_sim_reg { + m32c_sim_reg_r0_bank0, + m32c_sim_reg_r1_bank0, + m32c_sim_reg_r2_bank0, + m32c_sim_reg_r3_bank0, + m32c_sim_reg_a0_bank0, + m32c_sim_reg_a1_bank0, + m32c_sim_reg_fb_bank0, + m32c_sim_reg_sb_bank0, + m32c_sim_reg_r0_bank1, + m32c_sim_reg_r1_bank1, + m32c_sim_reg_r2_bank1, + m32c_sim_reg_r3_bank1, + m32c_sim_reg_a0_bank1, + m32c_sim_reg_a1_bank1, + m32c_sim_reg_fb_bank1, + m32c_sim_reg_sb_bank1, + m32c_sim_reg_usp, + m32c_sim_reg_isp, + m32c_sim_reg_pc, + m32c_sim_reg_intb, + m32c_sim_reg_flg, + m32c_sim_reg_svf, + m32c_sim_reg_svp, + m32c_sim_reg_vct, + m32c_sim_reg_dmd0, + m32c_sim_reg_dmd1, + m32c_sim_reg_dct0, + m32c_sim_reg_dct1, + m32c_sim_reg_drc0, + m32c_sim_reg_drc1, + m32c_sim_reg_dma0, + m32c_sim_reg_dma1, + m32c_sim_reg_dsa0, + m32c_sim_reg_dsa1, + m32c_sim_reg_dra0, + m32c_sim_reg_dra1, + m32c_sim_reg_num_regs +}; + +#endif /* SIM_M32C_H */ diff -uprN binutils-2.16.91.0.1/include/hashtab.h binutils-2.16.91.0.2/include/hashtab.h --- binutils-2.16.91.0.1/include/hashtab.h 2005-05-10 15:46:48.000000000 -0700 +++ binutils-2.16.91.0.2/include/hashtab.h 2005-07-20 12:27:28.080063289 -0700 @@ -81,6 +81,15 @@ typedef void (*htab_free) (void *); typedef void *(*htab_alloc_with_arg) (void *, size_t, size_t); typedef void (*htab_free_with_arg) (void *, void *); +/* This macro defines reserved value for empty table entry. */ + +#define HTAB_EMPTY_ENTRY ((PTR) 0) + +/* This macro defines reserved value for table entry which contained + a deleted element. */ + +#define HTAB_DELETED_ENTRY ((PTR) 1) + /* Hash tables are of the following type. The structure (implementation) of this type is not needed for using the hash tables. All work with hash table should be executed only through diff -uprN binutils-2.16.91.0.1/include/md5.h binutils-2.16.91.0.2/include/md5.h --- binutils-2.16.91.0.1/include/md5.h 2005-05-10 15:46:48.000000000 -0700 +++ binutils-2.16.91.0.2/include/md5.h 2005-07-20 12:27:28.081063124 -0700 @@ -37,6 +37,7 @@ #ifdef _LIBC # include typedef u_int32_t md5_uint32; +typedef uintptr_t md5_uintptr; #else # define INT_MAX_32_BITS 2147483647 @@ -64,6 +65,9 @@ typedef u_int32_t md5_uint32; # endif # endif # endif +/* We have to make a guess about the integer type equivalent in size + to pointers which should always be correct. */ +typedef unsigned long int md5_uintptr; #endif /* Structure to save state of computation between the single steps. */ @@ -76,7 +80,7 @@ struct md5_ctx md5_uint32 total[2]; md5_uint32 buflen; - char buffer[128]; + char buffer[128] ATTRIBUTE_ALIGNED_ALIGNOF(md5_uint32); }; /* diff -uprN binutils-2.16.91.0.1/include/opcode/ChangeLog binutils-2.16.91.0.2/include/opcode/ChangeLog --- binutils-2.16.91.0.1/include/opcode/ChangeLog 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/include/opcode/ChangeLog 2005-07-20 12:27:28.114057683 -0700 @@ -1,3 +1,34 @@ +2005-07-18 John David Anglin + + * hppa.h: Fix punctuation in comment. + + * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for + implicit space-register addressing. Set space-register bits on opcodes + using implicit space-register addressing. Add various missing pa20 + long-immediate opcodes. Remove various opcodes using implicit 3-bit + space-register addressing. Use "fE" instead of "fe" in various + fstw opcodes. + +2005-07-18 Jan Beulich + + * i386.h (i386_optab): Operands of aam and aad are unsigned. + +2007-07-15 H.J. Lu + + * i386.h (i386_optab): Support Intel VMX Instructions. + +2005-07-10 John David Anglin + + * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores. + +2005-07-05 Jan Beulich + + * i386.h (i386_optab): Add new insns. + +2005-07-01 Nick Clifton + + * sparc.h: Add typedefs to structure declarations. + 2005-06-20 H.J. Lu PR 1013 diff -uprN binutils-2.16.91.0.1/include/opcode/hppa.h binutils-2.16.91.0.2/include/opcode/hppa.h --- binutils-2.16.91.0.1/include/opcode/hppa.h 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/include/opcode/hppa.h 2005-07-20 12:27:28.118057024 -0700 @@ -48,7 +48,12 @@ struct pa_opcode char flags; }; -/* Enable/disable strict syntax checking. */ +/* Enable/disable strict syntax checking. When strict syntax checking + is not used, out-of-range immediate fields can result in an error, + depending on the specific immediate range being matched. An immediate + value of zero is also accepted as equivalent to index register 0. + As a result, non-strict opcode entries must be ordered from largest + to smallest immediate range. */ #define FLAG_STRICT 0x1 /* @@ -279,11 +284,32 @@ static const char *const completer_chars /* The order of the opcodes in this table is significant: - * The assembler requires that all instances of the same mnemonic must be - consecutive. If they aren't, the assembler will bomb at runtime. + * The assembler requires that all instances of the same mnemonic be + consecutive. If they aren't, the assembler will bomb at runtime. - * The disassembler should not care about the order of the opcodes. */ + * The disassembler does not care about the order of the opcodes + except in cases where implicit addressing is used. + Strict syntax (FLAG_STRICT) should be used for pa11 opcodes + and later. + + Here are the rules for ordering the opcodes of a mnemonic: + + 1) Opcodes with FLAG_STRICT precede opcodes without FLAG_STRICT, + + 2) Opcodes with FLAG_STRICT should be ordered as follows: + register index opcodes, short immediate opcodes, and finally + long immediate opcodes. Where there are opcodes for more + than one architecture in any of these groups, the opcodes + for the higher architecture should come first, + + 3) Where implicit addressing is available for an opcode, the + implicit opcode should precede the explicit opcode, and + + 4) Opcodes without FLAG_STRICT should be order as follows: long + immediate opcodes, short immediate opcodes and finally register + index opcodes. */ + static const struct pa_opcode pa_opcodes[] = { @@ -320,189 +346,189 @@ static const struct pa_opcode pa_opcodes /* Loads and Stores for integer registers. */ -{ "ldd", 0x0c0010e0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, -{ "ldd", 0x0c0010e0, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0000c0, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT}, { "ldd", 0x0c0000c0, 0xfc0013c0, "cxccx(s,b),t", pa20, FLAG_STRICT}, -{ "ldd", 0x0c0000c0, 0xfc0013c0, "cxccx(b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0010e0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0010e0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0010c0, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT}, { "ldd", 0x0c0010c0, 0xfc0013c0, "cmcc5(s,b),t", pa20, FLAG_STRICT}, -{ "ldd", 0x0c0010c0, 0xfc0013c0, "cmcc5(b),t", pa20, FLAG_STRICT}, { "ldd", 0x50000000, 0xfc000002, "cq&(b),x", pa20w, FLAG_STRICT}, -{ "ldd", 0x50000000, 0xfc000002, "cq#(b),x", pa20, FLAG_STRICT}, -{ "ldw", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT}, -{ "ldw", 0x0c000080, 0xfc001fc0, "cXx(b),t", pa10, FLAG_STRICT}, +{ "ldd", 0x50000000, 0xfc00c002, "cq#(b),x", pa20, FLAG_STRICT}, +{ "ldd", 0x50000000, 0xfc000002, "cq#(s,b),x", pa20, FLAG_STRICT}, +{ "ldw", 0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, { "ldw", 0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT}, -{ "ldw", 0x0c000080, 0xfc0013c0, "cxccx(b),t", pa11, FLAG_STRICT}, -{ "ldw", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, -{ "ldw", 0x0c001080, 0xfc001fc0, "cM5(b),t", pa10, FLAG_STRICT}, -{ "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(b),t", pa11, FLAG_STRICT}, +{ "ldw", 0x0c0010a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, { "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, -{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldw", 0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, +{ "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, { "ldw", 0x4c000000, 0xfc000000, "ce<(b),x", pa20w, FLAG_STRICT}, -{ "ldw", 0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, FLAG_STRICT}, -{ "ldw", 0x4c000000, 0xfc000000, "ceJ(b),x", pa10, FLAG_STRICT}, { "ldw", 0x5c000004, 0xfc000006, "ce>(b),x", pa20w, FLAG_STRICT}, -{ "ldw", 0x5c000004, 0xfc000006, "ceK(s,b),x", pa20, FLAG_STRICT}, -{ "ldw", 0x5c000004, 0xfc000006, "ceK(b),x", pa20, FLAG_STRICT}, { "ldw", 0x48000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, +{ "ldw", 0x5c000004, 0xfc00c006, "ceK(b),x", pa20, FLAG_STRICT}, +{ "ldw", 0x5c000004, 0xfc000006, "ceK(s,b),x", pa20, FLAG_STRICT}, +{ "ldw", 0x4c000000, 0xfc00c000, "ceJ(b),x", pa10, 0}, +{ "ldw", 0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, 0}, +{ "ldw", 0x48000000, 0xfc00c000, "j(b),x", pa10, 0}, { "ldw", 0x48000000, 0xfc000000, "j(s,b),x", pa10, 0}, -{ "ldw", 0x48000000, 0xfc000000, "j(b),x", pa10, 0}, -{ "ldh", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT}, -{ "ldh", 0x0c000040, 0xfc001fc0, "cXx(b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, 0}, +{ "ldw", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldw", 0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, 0}, +{ "ldw", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldh", 0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, { "ldh", 0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT}, -{ "ldh", 0x0c000040, 0xfc0013c0, "cxccx(b),t", pa11, FLAG_STRICT}, -{ "ldh", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, -{ "ldh", 0x0c001040, 0xfc001fc0, "cM5(b),t", pa10, FLAG_STRICT}, -{ "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(b),t", pa11, FLAG_STRICT}, +{ "ldh", 0x0c001060, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, { "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, -{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldh", 0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, +{ "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, { "ldh", 0x44000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, +{ "ldh", 0x44000000, 0xfc00c000, "j(b),x", pa10, 0}, { "ldh", 0x44000000, 0xfc000000, "j(s,b),x", pa10, 0}, -{ "ldh", 0x44000000, 0xfc000000, "j(b),x", pa10, 0}, -{ "ldb", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT}, -{ "ldb", 0x0c000000, 0xfc001fc0, "cXx(b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, 0}, +{ "ldh", 0x0c001040, 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FLAG_STRICT}, -{ "ldcd", 0x0c000140, 0xfc0013c0, "cxcdx(b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c001140, 0xfc00d3c0, "cmcd5(b),t", pa20, FLAG_STRICT}, { "ldcd", 0x0c001140, 0xfc0013c0, "cmcd5(s,b),t", pa20, FLAG_STRICT}, -{ "ldcd", 0x0c001140, 0xfc0013c0, "cmcd5(b),t", pa20, FLAG_STRICT}, -{ "stda", 0x0c0013e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, -{ "stda", 0x0c0013e0, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, -{ "stda", 0x0c0013c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT}, -{ "stda", 0x0c0013c0, 0xfc0013c0, "cmcCx,V(b)", pa20, FLAG_STRICT}, -{ "ldwax", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT}, +{ "stda", 0x0c0013e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stda", 0x0c0013c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT}, { "ldwax", 0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT}, -{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT}, -{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(b),t", pa10, FLAG_STRICT}, +{ "ldwax", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, 0}, +{ "ldcwx", 0x0c0001c0, 0xfc00d3c0, "cxcdx(b),t", pa11, FLAG_STRICT}, { "ldcwx", 0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa11, FLAG_STRICT}, -{ "ldcwx", 0x0c0001c0, 0xfc0013c0, "cxcdx(b),t", pa11, FLAG_STRICT}, -{ "ldws", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, -{ "ldws", 0x0c001080, 0xfc001fc0, "cM5(b),t", pa10, FLAG_STRICT}, +{ "ldcwx", 0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, 0}, +{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldws", 0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, { "ldws", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "ldws", 0x0c001080, 0xfc0013c0, "cmcc5(b),t", pa11, FLAG_STRICT}, -{ "ldhs", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, -{ "ldhs", 0x0c001040, 0xfc001fc0, "cM5(b),t", pa10, FLAG_STRICT}, +{ "ldws", 0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, 0}, +{ "ldws", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldhs", 0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, { "ldhs", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "ldhs", 0x0c001040, 0xfc0013c0, "cmcc5(b),t", pa11, FLAG_STRICT}, -{ "ldbs", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, -{ "ldbs", 0x0c001000, 0xfc001fc0, "cM5(b),t", pa10, FLAG_STRICT}, +{ "ldhs", 0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, 0}, +{ "ldhs", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldbs", 0x0c001000, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, { "ldbs", 0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "ldbs", 0x0c001000, 0xfc0013c0, "cmcc5(b),t", pa11, FLAG_STRICT}, -{ "ldwas", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT}, +{ "ldbs", 0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, 0}, +{ "ldbs", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, { "ldwas", 0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT}, -{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT}, -{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(b),t", pa10, FLAG_STRICT}, +{ "ldwas", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, 0}, +{ "ldcws", 0x0c0011c0, 0xfc00d3c0, "cmcd5(b),t", pa11, FLAG_STRICT}, { "ldcws", 0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa11, FLAG_STRICT}, -{ "ldcws", 0x0c0011c0, 0xfc0013c0, "cmcd5(b),t", pa11, FLAG_STRICT}, -{ "stws", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT}, -{ "stws", 0x0c001280, 0xfc001fc0, "cMx,V(b)", pa10, FLAG_STRICT}, +{ "ldcws", 0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, 0}, +{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "stws", 0x0c001280, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, { "stws", 0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, -{ "stws", 0x0c001280, 0xfc0013c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, -{ "sths", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT}, -{ "sths", 0x0c001240, 0xfc001fc0, "cMx,V(b)", pa10, FLAG_STRICT}, +{ "stws", 0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, +{ "stws", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, +{ "sths", 0x0c001240, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, { "sths", 0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, -{ "sths", 0x0c001240, 0xfc0013c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, -{ "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT}, -{ "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(b)", pa10, FLAG_STRICT}, +{ "sths", 0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, +{ "sths", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, +{ "stbs", 0x0c001200, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, { "stbs", 0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT}, -{ "stbs", 0x0c001200, 0xfc0013c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, -{ "stwas", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT}, +{ "stbs", 0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, +{ "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, { "stwas", 0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT}, +{ "stwas", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, +{ "stdby", 0x0c001340, 0xfc00d3c0, "cscCx,V(b)", pa20, FLAG_STRICT}, { "stdby", 0x0c001340, 0xfc0013c0, "cscCx,V(s,b)", pa20, FLAG_STRICT}, -{ "stdby", 0x0c001340, 0xfc0013c0, "cscCx,V(b)", pa20, FLAG_STRICT}, -{ "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, FLAG_STRICT}, -{ "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(b)", pa10, FLAG_STRICT}, +{ "stbys", 0x0c001300, 0xfc00d3c0, "cscCx,V(b)", pa11, FLAG_STRICT}, { "stbys", 0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa11, FLAG_STRICT}, -{ "stbys", 0x0c001300, 0xfc0013c0, "cscCx,V(b)", pa11, FLAG_STRICT}, +{ "stbys", 0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, 0}, +{ "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, 0}, /* Immediate instructions. */ { "ldo", 0x34000000, 0xfc000000, "l(b),x", pa20w, 0}, @@ -541,10 +567,10 @@ static const struct pa_opcode pa_opcodes { "addbf", 0xa8000000, 0xfc000000, "?dnx,b,w", pa10, 0}, { "addibt", 0xa4000000, 0xfc000000, "?dn5,b,w", pa10, 0}, { "addibf", 0xac000000, 0xfc000000, "?dn5,b,w", pa10, 0}, -{ "bb", 0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT}, -{ "bb", 0xc4004000, 0xfc004000, "?bnx,Q,w", pa10, 0}, { "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT}, { "bb", 0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT}, +{ "bb", 0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT}, +{ "bb", 0xc4004000, 0xfc004000, "?bnx,Q,w", pa10, 0}, { "bvb", 0xc0004000, 0xffe04000, "?bnx,w", pa10, 0}, { "clrbts", 0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT}, { "popbts", 0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT}, @@ -678,8 +704,8 @@ static const struct pa_opcode pa_opcodes { "rsm", 0x00000e60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT}, { "rsm", 0x00000e60, 0xffe0ffe0, "R,t", pa10, 0}, { "mtsm", 0x00001860, 0xffe0ffff, "x", pa10, 0}, +{ "ldsid", 0x000010a0, 0xfc1fffe0, "(b),t", pa10, 0}, { "ldsid", 0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10, 0}, -{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(b),t", pa10, 0}, { "mtsp", 0x00001820, 0xffe01fff, "x,S", pa10, 0}, { "mtctl", 0x00001840, 0xfc00ffff, "x,^", pa10, 0}, { "mtsarcm", 0x016018C0, 0xffe0ffff, "x", pa20, FLAG_STRICT}, @@ -689,54 +715,47 @@ static const struct pa_opcode pa_opcodes { "mfctl", 0x000008a0, 0xfc1fffe0, "^,t", pa10, 0}, { "sync", 0x00000400, 0xffffffff, "", pa10, 0}, { "syncdma", 0x00100400, 0xffffffff, "", pa10, 0}, +{ "probe", 0x04001180, 0xfc00ffa0, "cw(b),x,t", pa10, FLAG_STRICT}, { "probe", 0x04001180, 0xfc003fa0, "cw(s,b),x,t", pa10, FLAG_STRICT}, -{ "probe", 0x04001180, 0xfc003fa0, "cw(b),x,t", pa10, FLAG_STRICT}, +{ "probei", 0x04003180, 0xfc00ffa0, "cw(b),R,t", pa10, FLAG_STRICT}, { "probei", 0x04003180, 0xfc003fa0, "cw(s,b),R,t", pa10, FLAG_STRICT}, -{ "probei", 0x04003180, 0xfc003fa0, "cw(b),R,t", pa10, FLAG_STRICT}, +{ "prober", 0x04001180, 0xfc00ffe0, "(b),x,t", pa10, 0}, { "prober", 0x04001180, 0xfc003fe0, "(s,b),x,t", pa10, 0}, -{ "prober", 0x04001180, 0xfc003fe0, "(b),x,t", pa10, 0}, +{ "proberi", 0x04003180, 0xfc00ffe0, "(b),R,t", pa10, 0}, { "proberi", 0x04003180, 0xfc003fe0, "(s,b),R,t", pa10, 0}, -{ "proberi", 0x04003180, 0xfc003fe0, "(b),R,t", pa10, 0}, +{ "probew", 0x040011c0, 0xfc00ffe0, "(b),x,t", pa10, 0}, { "probew", 0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10, 0}, -{ "probew", 0x040011c0, 0xfc003fe0, "(b),x,t", pa10, 0}, +{ "probewi", 0x040031c0, 0xfc00ffe0, "(b),R,t", pa10, 0}, { "probewi", 0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10, 0}, -{ "probewi", 0x040031c0, 0xfc003fe0, "(b),R,t", pa10, 0}, +{ "lpa", 0x04001340, 0xfc00ffc0, "cZx(b),t", pa10, 0}, { "lpa", 0x04001340, 0xfc003fc0, "cZx(s,b),t", pa10, 0}, -{ "lpa", 0x04001340, 0xfc003fc0, "cZx(b),t", pa10, 0}, +{ "lha", 0x04001300, 0xfc00ffc0, "cZx(b),t", pa10, 0}, { "lha", 0x04001300, 0xfc003fc0, "cZx(s,b),t", pa10, 0}, -{ "lha", 0x04001300, 0xfc003fc0, "cZx(b),t", pa10, 0}, +{ "lci", 0x04001300, 0xfc00ffe0, "x(b),t", pa10, 0}, { "lci", 0x04001300, 0xfc003fe0, "x(s,b),t", pa10, 0}, -{ "lci", 0x04001300, 0xfc003fe0, "x(b),t", pa10, 0}, +{ "pdtlb", 0x04001600, 0xfc00ffdf, "cLcZx(b)", pa20, FLAG_STRICT}, { "pdtlb", 0x04001600, 0xfc003fdf, "cLcZx(s,b)", pa20, FLAG_STRICT}, -{ "pdtlb", 0x04001600, 0xfc003fdf, "cLcZx(b)", pa20, FLAG_STRICT}, +{ "pdtlb", 0x04001200, 0xfc00ffdf, "cZx(b)", pa10, 0}, { "pdtlb", 0x04001200, 0xfc003fdf, "cZx(s,b)", pa10, 0}, -{ "pdtlb", 0x04001200, 0xfc003fdf, "cZx(b)", pa10, 0}, { "pitlb", 0x04000600, 0xfc001fdf, "cLcZx(S,b)", pa20, FLAG_STRICT}, -{ "pitlb", 0x04000600, 0xfc001fdf, "cLcZx(b)", pa20, FLAG_STRICT}, { "pitlb", 0x04000200, 0xfc001fdf, "cZx(S,b)", pa10, 0}, -{ "pitlb", 0x04000200, 0xfc001fdf, "cZx(b)", pa10, 0}, +{ "pdtlbe", 0x04001240, 0xfc00ffdf, "cZx(b)", pa10, 0}, { "pdtlbe", 0x04001240, 0xfc003fdf, "cZx(s,b)", pa10, 0}, -{ "pdtlbe", 0x04001240, 0xfc003fdf, "cZx(b)", pa10, 0}, { "pitlbe", 0x04000240, 0xfc001fdf, "cZx(S,b)", pa10, 0}, -{ "pitlbe", 0x04000240, 0xfc001fdf, "cZx(b)", pa10, 0}, +{ "idtlba", 0x04001040, 0xfc00ffff, "x,(b)", pa10, 0}, { "idtlba", 0x04001040, 0xfc003fff, "x,(s,b)", pa10, 0}, -{ "idtlba", 0x04001040, 0xfc003fff, "x,(b)", pa10, 0}, { "iitlba", 0x04000040, 0xfc001fff, "x,(S,b)", pa10, 0}, -{ "iitlba", 0x04000040, 0xfc001fff, "x,(b)", pa10, 0}, +{ "idtlbp", 0x04001000, 0xfc00ffff, "x,(b)", pa10, 0}, { "idtlbp", 0x04001000, 0xfc003fff, "x,(s,b)", pa10, 0}, -{ "idtlbp", 0x04001000, 0xfc003fff, "x,(b)", pa10, 0}, { "iitlbp", 0x04000000, 0xfc001fff, "x,(S,b)", pa10, 0}, -{ "iitlbp", 0x04000000, 0xfc001fff, "x,(b)", pa10, 0}, +{ "pdc", 0x04001380, 0xfc00ffdf, "cZx(b)", pa10, 0}, { "pdc", 0x04001380, 0xfc003fdf, "cZx(s,b)", pa10, 0}, -{ "pdc", 0x04001380, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "fdc", 0x04001280, 0xfc00ffdf, "cZx(b)", pa10, 0}, { "fdc", 0x04001280, 0xfc003fdf, "cZx(s,b)", pa10, 0}, -{ "fdc", 0x04001280, 0xfc003fdf, "cZx(b)", pa10, 0}, { "fic", 0x04000280, 0xfc001fdf, "cZx(S,b)", pa10, 0}, -{ "fic", 0x04000280, 0xfc001fdf, "cZx(b)", pa10, 0}, +{ "fdce", 0x040012c0, 0xfc00ffdf, "cZx(b)", pa10, 0}, { "fdce", 0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10, 0}, -{ "fdce", 0x040012c0, 0xfc003fdf, "cZx(b)", pa10, 0}, { "fice", 0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10, 0}, -{ "fice", 0x040002c0, 0xfc001fdf, "cZx(b)", pa10, 0}, { "diag", 0x14000000, 0xfc000000, "D", pa10, 0}, { "idtlbt", 0x04001800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, { "iitlbt", 0x04000800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, @@ -753,101 +772,107 @@ static const struct pa_opcode pa_opcodes /* gfw and gfr are not in the HP PA 1.1 manual, but they are in either the Timex FPU or the Mustang ERS (not sure which) manual. */ +{ "gfw", 0x04001680, 0xfc00ffdf, "cZx(b)", pa11, 0}, { "gfw", 0x04001680, 0xfc003fdf, "cZx(s,b)", pa11, 0}, -{ "gfw", 0x04001680, 0xfc003fdf, "cZx(b)", pa11, 0}, +{ "gfr", 0x04001a80, 0xfc00ffdf, "cZx(b)", pa11, 0}, { "gfr", 0x04001a80, 0xfc003fdf, "cZx(s,b)", pa11, 0}, -{ "gfr", 0x04001a80, 0xfc003fdf, "cZx(b)", pa11, 0}, /* Floating Point Coprocessor Instructions. */ -{ "fldw", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, FLAG_STRICT}, -{ "fldw", 0x24000000, 0xfc001f80, "cXx(b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24000000, 0xfc00d380, "cxccx(b),fT", pa11, FLAG_STRICT}, { "fldw", 0x24000000, 0xfc001380, "cxccx(s,b),fT", pa11, FLAG_STRICT}, -{ "fldw", 0x24000000, 0xfc001380, "cxccx(b),fT", pa11, FLAG_STRICT}, -{ "fldw", 0x24001000, 0xfc001f80, "cM5(s,b),fT", pa10, FLAG_STRICT}, -{ "fldw", 0x24001000, 0xfc001f80, "cM5(b),fT", pa10, FLAG_STRICT}, -{ "fldw", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa11, FLAG_STRICT}, -{ "fldw", 0x24001000, 0xfc001380, "cmcc5(b),fT", pa11, FLAG_STRICT}, +{ "fldw", 0x24001020, 0xfc1ff3a0, "cocc@(b),fT", pa20, FLAG_STRICT}, { "fldw", 0x24001020, 0xfc1f33a0, "cocc@(s,b),fT", pa20, FLAG_STRICT}, -{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(b),fT", pa20, FLAG_STRICT}, +{ "fldw", 0x24001000, 0xfc00d380, "cmcc5(b),fT", pa11, FLAG_STRICT}, +{ "fldw", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa11, FLAG_STRICT}, { "fldw", 0x5c000000, 0xfc000004, "y(b),fe", pa20w, FLAG_STRICT}, { "fldw", 0x58000000, 0xfc000000, "cJy(b),fe", pa20w, FLAG_STRICT}, -{ "fldw", 0x5c000000, 0xfc000004, "d(b),fe", pa20, FLAG_STRICT}, -{ "fldw", 0x58000000, 0xfc000000, "cJd(b),fe", pa20, FLAG_STRICT}, -{ "fldd", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, FLAG_STRICT}, -{ "fldd", 0x2c000000, 0xfc001fc0, "cXx(b),ft", pa10, FLAG_STRICT}, +{ "fldw", 0x5c000000, 0xfc00c004, "d(b),fe", pa20, FLAG_STRICT}, +{ "fldw", 0x5c000000, 0xfc000004, "d(s,b),fe", pa20, FLAG_STRICT}, +{ "fldw", 0x58000000, 0xfc00c000, "cJd(b),fe", pa20, FLAG_STRICT}, +{ "fldw", 0x58000000, 0xfc000000, "cJd(s,b),fe", pa20, FLAG_STRICT}, +{ "fldw", 0x24001000, 0xfc00df80, "cM5(b),fT", pa10, 0}, +{ "fldw", 0x24001000, 0xfc001f80, "cM5(s,b),fT", pa10, 0}, +{ "fldw", 0x24000000, 0xfc00df80, "cXx(b),fT", pa10, 0}, +{ "fldw", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, 0}, +{ "fldd", 0x2c000000, 0xfc00d3c0, "cxccx(b),ft", pa11, FLAG_STRICT}, { "fldd", 0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa11, FLAG_STRICT}, -{ "fldd", 0x2c000000, 0xfc0013c0, "cxccx(b),ft", pa11, FLAG_STRICT}, -{ "fldd", 0x2c001000, 0xfc001fc0, "cM5(s,b),ft", pa10, FLAG_STRICT}, -{ "fldd", 0x2c001000, 0xfc001fc0, "cM5(b),ft", pa10, FLAG_STRICT}, -{ "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa11, FLAG_STRICT}, -{ "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(b),ft", pa11, FLAG_STRICT}, +{ "fldd", 0x2c001020, 0xfc1ff3e0, "cocc@(b),ft", pa20, FLAG_STRICT}, { "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(s,b),ft", pa20, FLAG_STRICT}, -{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(b),ft", pa20, FLAG_STRICT}, +{ "fldd", 0x2c001000, 0xfc00d3c0, "cmcc5(b),ft", pa11, FLAG_STRICT}, +{ "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa11, FLAG_STRICT}, { "fldd", 0x50000002, 0xfc000002, "cq&(b),fx", pa20w, FLAG_STRICT}, -{ "fldd", 0x50000002, 0xfc000002, "cq#(b),fx", pa20, FLAG_STRICT}, -{ "fstw", 0x24000200, 0xfc001f80, "cXfT,x(s,b)", pa10, FLAG_STRICT}, -{ "fstw", 0x24000200, 0xfc001f80, "cXfT,x(b)", pa10, FLAG_STRICT}, +{ "fldd", 0x50000002, 0xfc00c002, "cq#(b),fx", pa20, FLAG_STRICT}, +{ "fldd", 0x50000002, 0xfc000002, "cq#(s,b),fx", pa20, FLAG_STRICT}, +{ "fldd", 0x2c001000, 0xfc00dfc0, "cM5(b),ft", pa10, 0}, +{ "fldd", 0x2c001000, 0xfc001fc0, "cM5(s,b),ft", pa10, 0}, +{ "fldd", 0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, 0}, +{ "fldd", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, 0}, +{ "fstw", 0x24000200, 0xfc00d380, "cxcCfT,x(b)", pa11, FLAG_STRICT}, { "fstw", 0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa11, FLAG_STRICT}, -{ "fstw", 0x24000200, 0xfc001380, "cxcCfT,x(b)", pa11, FLAG_STRICT}, -{ "fstw", 0x24001200, 0xfc001f80, "cMfT,5(s,b)", pa10, FLAG_STRICT}, -{ "fstw", 0x24001200, 0xfc001f80, "cMfT,5(b)", pa10, FLAG_STRICT}, -{ "fstw", 0x24001200, 0xfc001380, "cmcCfT,5(s,b)", pa11, FLAG_STRICT}, -{ "fstw", 0x24001200, 0xfc001380, "cmcCfT,5(b)", pa11, FLAG_STRICT}, +{ "fstw", 0x24001220, 0xfc1ff3a0, "cocCfT,@(b)", pa20, FLAG_STRICT}, { "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(s,b)", pa20, FLAG_STRICT}, -{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(b)", pa20, FLAG_STRICT}, +{ "fstw", 0x24001200, 0xfc00df80, "cMfT,5(b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001200, 0xfc001f80, "cMfT,5(s,b)", pa10, FLAG_STRICT}, { "fstw", 0x7c000000, 0xfc000004, "fE,y(b)", pa20w, FLAG_STRICT}, -{ "fstw", 0x78000000, 0xfc000000, "cJfe,y(b)", pa20w, FLAG_STRICT}, -{ "fstw", 0x7c000000, 0xfc000004, "fe,d(b)", pa20, FLAG_STRICT}, -{ "fstw", 0x78000000, 0xfc000000, "cJfe,d(b)", pa20, FLAG_STRICT}, -{ "fstd", 0x2c000200, 0xfc001fc0, "cXft,x(s,b)", pa10, FLAG_STRICT}, -{ "fstd", 0x2c000200, 0xfc001fc0, "cXft,x(b)", pa10, FLAG_STRICT}, +{ "fstw", 0x78000000, 0xfc000000, "cJfE,y(b)", pa20w, FLAG_STRICT}, +{ "fstw", 0x7c000000, 0xfc00c004, "fE,d(b)", pa20, FLAG_STRICT}, +{ "fstw", 0x7c000000, 0xfc000004, "fE,d(s,b)", pa20, FLAG_STRICT}, +{ "fstw", 0x78000000, 0xfc00c000, "cJfE,d(b)", pa20, FLAG_STRICT}, +{ "fstw", 0x78000000, 0xfc000000, "cJfE,d(s,b)", pa20, FLAG_STRICT}, +{ "fstw", 0x24001200, 0xfc00df80, "cMfT,5(b)", pa10, 0}, +{ "fstw", 0x24001200, 0xfc001f80, "cMfT,5(s,b)", pa10, 0}, +{ "fstw", 0x24000200, 0xfc00df80, "cXfT,x(b)", pa10, 0}, +{ "fstw", 0x24000200, 0xfc001f80, "cXfT,x(s,b)", pa10, 0}, +{ "fstd", 0x2c000200, 0xfc00d3c0, "cxcCft,x(b)", pa11, FLAG_STRICT}, { "fstd", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa11, FLAG_STRICT}, -{ "fstd", 0x2c000200, 0xfc0013c0, "cxcCft,x(b)", pa11, FLAG_STRICT}, -{ "fstd", 0x2c001200, 0xfc001fc0, "cMft,5(s,b)", pa10, FLAG_STRICT}, -{ "fstd", 0x2c001200, 0xfc001fc0, "cMft,5(b)", pa10, FLAG_STRICT}, -{ "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa11, FLAG_STRICT}, -{ "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(b)", pa11, FLAG_STRICT}, +{ "fstd", 0x2c001220, 0xfc1ff3e0, "cocCft,@(b)", pa20, FLAG_STRICT}, { "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(s,b)", pa20, FLAG_STRICT}, -{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(b)", pa20, FLAG_STRICT}, +{ "fstd", 0x2c001200, 0xfc00d3c0, "cmcCft,5(b)", pa11, FLAG_STRICT}, +{ "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa11, FLAG_STRICT}, { "fstd", 0x70000002, 0xfc000002, "cqfx,&(b)", pa20w, FLAG_STRICT}, -{ "fstd", 0x70000002, 0xfc000002, "cqfx,#(b)", pa20, FLAG_STRICT}, -{ "fldwx", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, FLAG_STRICT}, -{ "fldwx", 0x24000000, 0xfc001f80, "cXx(b),fT", pa10, FLAG_STRICT}, +{ "fstd", 0x70000002, 0xfc00c002, "cqfx,#(b)", pa20, FLAG_STRICT}, +{ "fstd", 0x70000002, 0xfc000002, "cqfx,#(s,b)", pa20, FLAG_STRICT}, +{ "fstd", 0x2c001200, 0xfc00dfc0, "cMft,5(b)", pa10, 0}, +{ "fstd", 0x2c001200, 0xfc001fc0, "cMft,5(s,b)", pa10, 0}, +{ "fstd", 0x2c000200, 0xfc00dfc0, "cXft,x(b)", pa10, 0}, +{ "fstd", 0x2c000200, 0xfc001fc0, "cXft,x(s,b)", pa10, 0}, +{ "fldwx", 0x24000000, 0xfc00d380, "cxccx(b),fT", pa11, FLAG_STRICT}, { "fldwx", 0x24000000, 0xfc001380, "cxccx(s,b),fT", pa11, FLAG_STRICT}, -{ "fldwx", 0x24000000, 0xfc001380, "cxccx(b),fT", pa11, FLAG_STRICT}, -{ "flddx", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, FLAG_STRICT}, -{ "flddx", 0x2c000000, 0xfc001fc0, "cXx(b),ft", pa10, FLAG_STRICT}, +{ "fldwx", 0x24000000, 0xfc00df80, "cXx(b),fT", pa10, 0}, +{ "fldwx", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, 0}, +{ "flddx", 0x2c000000, 0xfc00d3c0, "cxccx(b),ft", pa11, FLAG_STRICT}, { "flddx", 0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa11, FLAG_STRICT}, -{ "flddx", 0x2c000000, 0xfc0013c0, "cxccx(b),ft", pa11, FLAG_STRICT}, -{ "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, FLAG_STRICT}, -{ "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(b)", pa10, FLAG_STRICT}, +{ "flddx", 0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, 0}, +{ "flddx", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, 0}, +{ "fstwx", 0x24000200, 0xfc00d380, "cxcCfT,x(b)", pa11, FLAG_STRICT}, { "fstwx", 0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa11, FLAG_STRICT}, -{ "fstwx", 0x24000200, 0xfc001380, "cxcCfT,x(b)", pa11, FLAG_STRICT}, -{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, FLAG_STRICT}, -{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(b)", pa10, FLAG_STRICT}, +{ "fstwx", 0x24000200, 0xfc00df80, "cxfT,x(b)", pa10, 0}, +{ "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, 0}, +{ "fstdx", 0x2c000200, 0xfc00d3c0, "cxcCft,x(b)", pa11, FLAG_STRICT}, { "fstdx", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa11, FLAG_STRICT}, -{ "fstdx", 0x2c000200, 0xfc0013c0, "cxcCft,x(b)", pa11, FLAG_STRICT}, +{ "fstdx", 0x2c000200, 0xfc00dfc0, "cxft,x(b)", pa10, 0}, +{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0}, +{ "fstqx", 0x3c000200, 0xfc00dfc0, "cxft,x(b)", pa10, 0}, { "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0}, -{ "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(b)", pa10, 0}, -{ "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, FLAG_STRICT}, -{ "fldws", 0x24001000, 0xfc001f80, "cm5(b),fT", pa10, FLAG_STRICT}, +{ "fldws", 0x24001000, 0xfc00d380, "cmcc5(b),fT", pa11, FLAG_STRICT}, { "fldws", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa11, FLAG_STRICT}, -{ "fldws", 0x24001000, 0xfc001380, "cmcc5(b),fT", pa11, FLAG_STRICT}, -{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, FLAG_STRICT}, -{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(b),ft", pa10, FLAG_STRICT}, +{ "fldws", 0x24001000, 0xfc00df80, "cm5(b),fT", pa10, 0}, +{ "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, 0}, +{ "fldds", 0x2c001000, 0xfc00d3c0, "cmcc5(b),ft", pa11, FLAG_STRICT}, { "fldds", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa11, FLAG_STRICT}, -{ "fldds", 0x2c001000, 0xfc0013c0, "cmcc5(b),ft", pa11, FLAG_STRICT}, -{ "fstws", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, FLAG_STRICT}, -{ "fstws", 0x24001200, 0xfc001f80, "cmfT,5(b)", pa10, FLAG_STRICT}, +{ "fldds", 0x2c001000, 0xfc00dfc0, "cm5(b),ft", pa10, 0}, +{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, 0}, +{ "fstws", 0x24001200, 0xfc00d380, "cmcCfT,5(b)", pa11, FLAG_STRICT}, { "fstws", 0x24001200, 0xfc001380, "cmcCfT,5(s,b)", pa11, FLAG_STRICT}, -{ "fstws", 0x24001200, 0xfc001380, "cmcCfT,5(b)", pa11, FLAG_STRICT}, -{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, FLAG_STRICT}, -{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(b)", pa10, FLAG_STRICT}, +{ "fstws", 0x24001200, 0xfc00df80, "cmfT,5(b)", pa10, 0}, +{ "fstws", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, 0}, +{ "fstds", 0x2c001200, 0xfc00d3c0, "cmcCft,5(b)", pa11, FLAG_STRICT}, { "fstds", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa11, FLAG_STRICT}, -{ "fstds", 0x2c001200, 0xfc0013c0, "cmcCft,5(b)", pa11, FLAG_STRICT}, +{ "fstds", 0x2c001200, 0xfc00dfc0, "cmft,5(b)", pa10, 0}, +{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0}, +{ "fstqs", 0x3c001200, 0xfc00dfc0, "cmft,5(b)", pa10, 0}, { "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0}, -{ "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(b)", pa10, 0}, { "fadd", 0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, { "fadd", 0x38000600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, { "fsub", 0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, @@ -906,78 +931,78 @@ static const struct pa_opcode pa_opcodes { "spop2", 0x10000400, 0xfc000600, "v,1Nb", pa10, 0}, { "spop3", 0x10000600, 0xfc000600, "v,0Nx,b", pa10, 0}, { "copr", 0x30000000, 0xfc000000, "u,2N", pa10, 0}, -{ "cldw", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT}, -{ "cldw", 0x24000000, 0xfc001e00, "ucXx(b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT}, { "cldw", 0x24000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT}, -{ "cldw", 0x24000000, 0xfc001200, "ucxccx(b),t", pa11, FLAG_STRICT}, -{ "cldw", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT}, -{ "cldw", 0x24001000, 0xfc001e00, "ucM5(b),t", pa10, FLAG_STRICT}, -{ "cldw", 0x24001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "cldw", 0x24001000, 0xfc001200, "ucmcc5(b),t", pa11, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc00d200, "ucocc@(b),t", pa20, FLAG_STRICT}, { "cldw", 0x24001000, 0xfc001200, "ucocc@(s,b),t", pa20, FLAG_STRICT}, -{ "cldw", 0x24001000, 0xfc001200, "ucocc@(b),t", pa20, FLAG_STRICT}, -{ "cldd", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT}, -{ "cldd", 0x2c000000, 0xfc001e00, "ucXx(b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc00de00, "ucM5(b),t", pa10, 0}, +{ "cldw", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0}, +{ "cldw", 0x24000000, 0xfc00de00, "ucXx(b),t", pa10, 0}, +{ "cldw", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0}, +{ "cldd", 0x2c000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT}, { "cldd", 0x2c000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT}, -{ "cldd", 0x2c000000, 0xfc001200, "ucxccx(b),t", pa11, FLAG_STRICT}, -{ "cldd", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT}, -{ "cldd", 0x2c001000, 0xfc001e00, "ucM5(b),t", pa10, FLAG_STRICT}, -{ "cldd", 0x2c001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "cldd", 0x2c001000, 0xfc001200, "ucmcc5(b),t", pa11, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc00d200, "ucocc@(b),t", pa20, FLAG_STRICT}, { "cldd", 0x2c001000, 0xfc001200, "ucocc@(s,b),t", pa20, FLAG_STRICT}, -{ "cldd", 0x2c001000, 0xfc001200, "ucocc@(b),t", pa20, FLAG_STRICT}, -{ "cstw", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT}, -{ "cstw", 0x24000200, 0xfc001e00, "ucXt,x(b)", pa10, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, 0}, +{ "cldd", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0}, +{ "cldd", 0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, 0}, +{ "cldd", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0}, +{ "cstw", 0x24000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT}, { "cstw", 0x24000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT}, -{ "cstw", 0x24000200, 0xfc001200, "ucxcCt,x(b)", pa11, FLAG_STRICT}, -{ "cstw", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT}, -{ "cstw", 0x24001200, 0xfc001e00, "ucMt,5(b)", pa10, FLAG_STRICT}, -{ "cstw", 0x24001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT}, -{ "cstw", 0x24001200, 0xfc001200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc00d200, "ucocCt,@(b)", pa20, FLAG_STRICT}, { "cstw", 0x24001200, 0xfc001200, "ucocCt,@(s,b)", pa20, FLAG_STRICT}, -{ "cstw", 0x24001200, 0xfc001200, "ucocCt,@(b)", pa20, FLAG_STRICT}, -{ "cstd", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT}, -{ "cstd", 0x2c000200, 0xfc001e00, "ucXt,x(b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, 0}, +{ "cstw", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0}, +{ "cstw", 0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, 0}, +{ "cstw", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0}, +{ "cstd", 0x2c000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT}, { "cstd", 0x2c000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT}, -{ "cstd", 0x2c000200, 0xfc001200, "ucxcCt,x(b)", pa11, FLAG_STRICT}, -{ "cstd", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT}, -{ "cstd", 0x2c001200, 0xfc001e00, "ucMt,5(b)", pa10, FLAG_STRICT}, -{ "cstd", 0x2c001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT}, -{ "cstd", 0x2c001200, 0xfc001200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc00d200, "ucocCt,@(b)", pa20, FLAG_STRICT}, { "cstd", 0x2c001200, 0xfc001200, "ucocCt,@(s,b)", pa20, FLAG_STRICT}, -{ "cstd", 0x2c001200, 0xfc001200, "ucocCt,@(b)", pa20, FLAG_STRICT}, -{ "cldwx", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT}, -{ "cldwx", 0x24000000, 0xfc001e00, "ucXx(b),t", pa10, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, 0}, +{ "cstd", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0}, +{ "cstd", 0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, 0}, +{ "cstd", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0}, +{ "cldwx", 0x24000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT}, { "cldwx", 0x24000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT}, -{ "cldwx", 0x24000000, 0xfc001200, "ucxccx(b),t", pa11, FLAG_STRICT}, -{ "clddx", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT}, -{ "clddx", 0x2c000000, 0xfc001e00, "ucXx(b),t", pa10, FLAG_STRICT}, +{ "cldwx", 0x24000000, 0xfc00de00, "ucXx(b),t", pa10, 0}, +{ "cldwx", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0}, +{ "clddx", 0x2c000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT}, { "clddx", 0x2c000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT}, -{ "clddx", 0x2c000000, 0xfc001200, "ucxccx(b),t", pa11, FLAG_STRICT}, -{ "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT}, -{ "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(b)", pa10, FLAG_STRICT}, +{ "clddx", 0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, 0}, +{ "clddx", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0}, +{ "cstwx", 0x24000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT}, { "cstwx", 0x24000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT}, -{ "cstwx", 0x24000200, 0xfc001200, "ucxcCt,x(b)", pa11, FLAG_STRICT}, -{ "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT}, -{ "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(b)", pa10, FLAG_STRICT}, -{ "cstdx", 0x2c001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT}, -{ "cstdx", 0x2c001200, 0xfc001200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, -{ "cldws", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT}, -{ "cldws", 0x24001000, 0xfc001e00, "ucM5(b),t", pa10, FLAG_STRICT}, +{ "cstwx", 0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, 0}, +{ "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0}, +{ "cstdx", 0x2c000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT}, +{ "cstdx", 0x2c000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT}, +{ "cstdx", 0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, 0}, +{ "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0}, +{ "cldws", 0x24001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT}, { "cldws", 0x24001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "cldws", 0x24001000, 0xfc001200, "ucmcc5(b),t", pa11, FLAG_STRICT}, -{ "cldds", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT}, -{ "cldds", 0x2c001000, 0xfc001e00, "ucM5(b),t", pa10, FLAG_STRICT}, +{ "cldws", 0x24001000, 0xfc00de00, "ucM5(b),t", pa10, 0}, +{ "cldws", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0}, +{ "cldds", 0x2c001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT}, { "cldds", 0x2c001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT}, -{ "cldds", 0x2c001000, 0xfc001200, "ucmcc5(b),t", pa11, FLAG_STRICT}, -{ "cstws", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT}, -{ "cstws", 0x24001200, 0xfc001e00, "ucMt,5(b)", pa10, FLAG_STRICT}, +{ "cldds", 0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, 0}, +{ "cldds", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0}, +{ "cstws", 0x24001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, { "cstws", 0x24001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT}, -{ "cstws", 0x24001200, 0xfc001200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, -{ "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT}, -{ "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(b)", pa10, FLAG_STRICT}, +{ "cstws", 0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, 0}, +{ "cstws", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0}, +{ "cstds", 0x2c001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, { "cstds", 0x2c001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT}, -{ "cstds", 0x2c001200, 0xfc001200, "ucmcCt,5(b)", pa11, FLAG_STRICT}, +{ "cstds", 0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, 0}, +{ "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0}, /* More pseudo instructions which must follow the main table. */ { "call", 0xe800f000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT}, diff -uprN binutils-2.16.91.0.1/include/opcode/i386.h binutils-2.16.91.0.2/include/opcode/i386.h --- binutils-2.16.91.0.1/include/opcode/i386.h 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/include/opcode/i386.h 2005-07-20 12:27:28.121056529 -0700 @@ -295,9 +295,9 @@ static const template i386_optab[] = {"daa", 0, 0x27, X, CpuNo64, NoSuf, { 0, 0, 0} }, {"das", 0, 0x2f, X, CpuNo64, NoSuf, { 0, 0, 0} }, {"aad", 0, 0xd50a, X, CpuNo64, NoSuf, { 0, 0, 0} }, -{"aad", 1, 0xd5, X, CpuNo64, NoSuf, { Imm8S, 0, 0} }, +{"aad", 1, 0xd5, X, CpuNo64, NoSuf, { Imm8, 0, 0} }, {"aam", 0, 0xd40a, X, CpuNo64, NoSuf, { 0, 0, 0} }, -{"aam", 1, 0xd4, X, CpuNo64, NoSuf, { Imm8S, 0, 0} }, +{"aam", 1, 0xd4, X, CpuNo64, NoSuf, { Imm8, 0, 0} }, /* Conversion insns. */ /* Intel naming */ @@ -1347,6 +1347,20 @@ static const template i386_optab[] = /* Need to ensure only "mwait %eax,%ecx" is accepted. */ {"mwait", 2, 0x0f01, 0xc9, CpuPNI, NoSuf|ImmExt, { Reg32, Reg32, 0} }, +/* VMX instructions. */ +{"vmcall", 0, 0x0f01, 0xc1, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} }, +{"vmclear", 1, 0x660fc7, 6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} }, +{"vmlaunch", 0, 0x0f01, 0xc2, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} }, +{"vmresume", 0, 0x0f01, 0xc3, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} }, +{"vmptrld", 1, 0x0fc7, 6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} }, +{"vmptrst", 1, 0x0fc7, 7, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} }, +{"vmread", 2, 0x0f78, X, CpuVMX|CpuNo64, l_Suf|Modrm,{ Reg32, Reg32|LongMem, 0} }, +{"vmread", 2, 0x0f78, X, CpuVMX|Cpu64, q_Suf|Modrm|NoRex64,{ Reg64, Reg64|LLongMem, 0} }, +{"vmwrite", 2, 0x0f79, X, CpuVMX|CpuNo64, l_Suf|Modrm,{ Reg32|LongMem, Reg32, 0} }, +{"vmwrite", 2, 0x0f79, X, CpuVMX|Cpu64, q_Suf|Modrm|NoRex64,{ Reg64|LLongMem, Reg64, 0} }, +{"vmxoff", 0, 0x0f01, 0xc4, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} }, +{"vmxon", 1, 0xf30fc7, 6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} }, + /* AMD 3DNow! instructions. */ {"prefetch", 1, 0x0f0d, 0, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } }, @@ -1383,6 +1397,22 @@ static const template i386_optab[] = {"swapgs", 0, 0x0f01, 0xf8, Cpu64, NoSuf|ImmExt, { 0, 0, 0} }, {"rdtscp", 0, 0x0f01, 0xf9, CpuSledgehammer,NoSuf|ImmExt, { 0, 0, 0} }, +/* AMD Pacifica additions. */ +{"clgi", 0, 0x0f01, 0xdd, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, +{"invlpga", 0, 0x0f01, 0xdf, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, +/* Need to ensure only "invlpga ...,%ecx" is accepted. */ +{"invlpga", 2, 0x0f01, 0xdf, CpuSVME, NoSuf|ImmExt, { AnyMem, Reg32, 0 } }, +{"skinit", 0, 0x0f01, 0xde, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, +{"skinit", 1, 0x0f01, 0xde, CpuSVME, NoSuf|ImmExt, { AnyMem, 0, 0 } }, +{"stgi", 0, 0x0f01, 0xdc, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, +{"vmload", 0, 0x0f01, 0xda, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, +{"vmload", 1, 0x0f01, 0xda, CpuSVME, NoSuf|ImmExt, { AnyMem, 0, 0 } }, +{"vmmcall", 0, 0x0f01, 0xd9, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, +{"vmrun", 0, 0x0f01, 0xd8, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, +{"vmrun", 1, 0x0f01, 0xd8, CpuSVME, NoSuf|ImmExt, { AnyMem, 0, 0 } }, +{"vmsave", 0, 0x0f01, 0xdb, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, +{"vmsave", 1, 0x0f01, 0xdb, CpuSVME, NoSuf|ImmExt, { AnyMem, 0, 0 } }, + /* VIA PadLock extensions. */ {"xstore-rng",0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, {"xcrypt-ecb",0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, diff -uprN binutils-2.16.91.0.1/include/opcode/sparc.h binutils-2.16.91.0.2/include/opcode/sparc.h --- binutils-2.16.91.0.1/include/opcode/sparc.h 2005-05-10 15:46:53.000000000 -0700 +++ binutils-2.16.91.0.2/include/opcode/sparc.h 2005-07-20 12:27:28.130055045 -0700 @@ -1,24 +1,24 @@ /* Definitions for opcode table for the sparc. Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002, - 2003 Free Software Foundation, Inc. + 2003, 2005 Free Software Foundation, Inc. -This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and -the GNU Binutils. + This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and + the GNU Binutils. -GAS/GDB is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GAS/GDB is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GAS or GDB; see the file COPYING. If not, write to -the Free Software Foundation, 51 Franklin Street - Fifth Floor, -Boston, MA 02110-1301, USA. */ + GAS/GDB is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS/GDB is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS or GDB; see the file COPYING. If not, write to + the Free Software Foundation, 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ #include "ansidecl.h" @@ -37,17 +37,18 @@ Boston, MA 02110-1301, USA. */ The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. Don't change this without updating sparc-opc.c. */ -enum sparc_opcode_arch_val { +enum sparc_opcode_arch_val +{ SPARC_OPCODE_ARCH_V6 = 0, SPARC_OPCODE_ARCH_V7, SPARC_OPCODE_ARCH_V8, SPARC_OPCODE_ARCH_SPARCLET, SPARC_OPCODE_ARCH_SPARCLITE, - /* v9 variants must appear last */ + /* V9 variants must appear last. */ SPARC_OPCODE_ARCH_V9, - SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */ - SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */ - SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */ + SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */ + SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */ + SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */ }; /* The highest architecture in the table. */ @@ -62,14 +63,15 @@ enum sparc_opcode_arch_val { /* Table of cpu variants. */ -struct sparc_opcode_arch { +typedef struct sparc_opcode_arch +{ const char *name; /* Mask of sparc_opcode_arch_val's supported. EG: For v7 this would be (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). These are short's because sparc_opcode.architecture is. */ short supported; -}; +} sparc_opcode_arch; extern const struct sparc_opcode_arch sparc_opcode_archs[]; @@ -82,44 +84,43 @@ extern enum sparc_opcode_arch_val sparc_ /* Non-zero if ARCH1 conflicts with ARCH2. IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */ #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \ -(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ - != SPARC_OPCODE_SUPPORTED (ARCH1)) \ - && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ + (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ + != SPARC_OPCODE_SUPPORTED (ARCH1)) \ + && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ != SPARC_OPCODE_SUPPORTED (ARCH2))) /* Structure of an opcode table entry. */ -struct sparc_opcode { +typedef struct sparc_opcode +{ const char *name; - unsigned long match; /* Bits that must be set. */ - unsigned long lose; /* Bits that must not be set. */ + unsigned long match; /* Bits that must be set. */ + unsigned long lose; /* Bits that must not be set. */ const char *args; - /* This was called "delayed" in versions before the flags. */ + /* This was called "delayed" in versions before the flags. */ char flags; short architecture; /* Bitmask of sparc_opcode_arch_val's. */ -}; +} sparc_opcode; -#define F_DELAYED 1 /* Delayed branch */ -#define F_ALIAS 2 /* Alias for a "real" instruction */ -#define F_UNBR 4 /* Unconditional branch */ -#define F_CONDBR 8 /* Conditional branch */ -#define F_JSR 16 /* Subroutine call */ -#define F_FLOAT 32 /* Floating point instruction (not a branch) */ -#define F_FBR 64 /* Floating point branch */ +#define F_DELAYED 1 /* Delayed branch. */ +#define F_ALIAS 2 /* Alias for a "real" instruction. */ +#define F_UNBR 4 /* Unconditional branch. */ +#define F_CONDBR 8 /* Conditional branch. */ +#define F_JSR 16 /* Subroutine call. */ +#define F_FLOAT 32 /* Floating point instruction (not a branch). */ +#define F_FBR 64 /* Floating point branch. */ /* FIXME: Add F_ANACHRONISTIC flag for v9. */ -/* +/* All sparc opcodes are 32 bits, except for the `set' instruction (really a + macro), which is 64 bits. It is handled as a special case. -All sparc opcodes are 32 bits, except for the `set' instruction (really a -macro), which is 64 bits. It is handled as a special case. + The match component is a mask saying which bits must match a particular + opcode in order for an instruction to be an instance of that opcode. -The match component is a mask saying which bits must match a particular -opcode in order for an instruction to be an instance of that opcode. + The args component is a string containing one character for each operand of the + instruction. -The args component is a string containing one character for each operand of the -instruction. - -Kinds of operands: + Kinds of operands: # Number used by optimizer. It is ignored. 1 rs1 register. 2 rs2 register. @@ -187,37 +188,35 @@ Kinds of operands: _ Ancillary state register in rd (v9a) / Ancillary state register in rs1 (v9a) -The following chars are unused: (note: ,[] are used as punctuation) -[45] - -*/ + The following chars are unused: (note: ,[] are used as punctuation) + [45]. */ -#define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */ -#define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */ -#define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */ -#define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */ -#define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */ -#define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */ -#define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */ -#define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */ -#define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */ -#define F1(x) (OP(x)) -#define DISP30(x) ((x)&0x3fffffff) -#define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */ -#define RS2(x) ((x)&0x1f) /* rs2 field */ -#define SIMM13(x) ((x)&0x1fff) /* simm13 field */ -#define RD(x) (((x)&0x1f) << 25) /* destination register field */ -#define RS1(x) (((x)&0x1f) << 14) /* rs1 field */ -#define ASI_RS2(x) (SIMM13(x)) -#define MEMBAR(x) ((x)&0x7f) -#define SLCPOP(x) (((x)&0x7f) << 6) /* sparclet cpop */ - -#define ANNUL (1<<29) -#define BPRED (1<<19) /* v9 */ -#define IMMED F3I(1) -#define RD_G0 RD(~0) -#define RS1_G0 RS1(~0) -#define RS2_G0 RS2(~0) +#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ +#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */ +#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */ +#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */ +#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */ +#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */ +#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */ +#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */ +#define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */ +#define F1(x) (OP (x)) +#define DISP30(x) ((x) & 0x3fffffff) +#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */ +#define RS2(x) ((x) & 0x1f) /* Rs2 field. */ +#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */ +#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */ +#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */ +#define ASI_RS2(x) (SIMM13 (x)) +#define MEMBAR(x) ((x) & 0x7f) +#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */ + +#define ANNUL (1 << 29) +#define BPRED (1 << 19) /* V9. */ +#define IMMED F3I (1) +#define RD_G0 RD (~0) +#define RS1_G0 RS1 (~0) +#define RS2_G0 RS2 (~0) extern const struct sparc_opcode sparc_opcodes[]; extern const int sparc_num_opcodes; @@ -231,11 +230,8 @@ extern const char *sparc_decode_prefetch extern int sparc_encode_sparclet_cpreg (const char *); extern const char *sparc_decode_sparclet_cpreg (int); -/* - * Local Variables: - * fill-column: 131 - * comment-column: 0 - * End: - */ +/* Local Variables: + fill-column: 131 + comment-column: 0 + End: */ -/* end of sparc.h */ diff -uprN binutils-2.16.91.0.1/include/xregex2.h binutils-2.16.91.0.2/include/xregex2.h --- binutils-2.16.91.0.1/include/xregex2.h 2005-05-10 15:46:49.000000000 -0700 +++ binutils-2.16.91.0.2/include/xregex2.h 2005-07-20 12:27:28.082062959 -0700 @@ -1,6 +1,9 @@ /* Definitions for data structures and routines for the regular expression library, version 0.12. - Copyright (C) 1985,1989-1993,1995-1998, 2000 Free Software Foundation, Inc. + + Copyright (C) 1985, 1989, 1990, 1991, 1992, 1993, 1995, 1996, 1997, + 1998, 2000, 2005 Free Software Foundation, Inc. + This file is part of the GNU C Library. Its master source is NOT part of the C library, however. The master source lives in /gd/gnu/lib. @@ -533,6 +536,9 @@ extern int regcomp (regex_t *__restrict const char *__restrict __pattern, int __cflags); +#if (__GNUC__) +__extension__ +#endif extern int regexec (const regex_t *__restrict __preg, const char *__restrict __string, size_t __nmatch, regmatch_t __pmatch[__restrict_arr], diff -uprN binutils-2.16.91.0.1/install-sh binutils-2.16.91.0.2/install-sh --- binutils-2.16.91.0.1/install-sh 2005-04-09 12:02:55.000000000 -0700 +++ binutils-2.16.91.0.2/install-sh 2005-07-20 12:27:26.824270368 -0700 @@ -1,7 +1,7 @@ #!/bin/sh # install - install a program, script, or datafile -scriptversion=2004-12-17.09 +scriptversion=2005-05-14.22 # This originates from X11R5 (mit/util/scripts/install.sh), which was # later released in X11R6 (xc/config/util/install.sh) with the @@ -109,7 +109,7 @@ while test -n "$1"; do shift continue;; - --help) echo "$usage"; exit 0;; + --help) echo "$usage"; exit $?;; -m) chmodcmd="$chmodprog $2" shift @@ -134,7 +134,7 @@ while test -n "$1"; do shift continue;; - --version) echo "$0 $scriptversion"; exit 0;; + --version) echo "$0 $scriptversion"; exit $?;; *) # When -d is used, all remaining arguments are directories to create. # When -t is used, the destination is already specified. diff -uprN binutils-2.16.91.0.1/ld/ChangeLog binutils-2.16.91.0.2/ld/ChangeLog --- binutils-2.16.91.0.1/ld/ChangeLog 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/ChangeLog 2005-07-20 12:27:28.134054386 -0700 @@ -1,3 +1,143 @@ +2005-07-19 H.J. Lu + + * ldmain.c (main): Reindent. + +2005-07-19 Paul Brook + + * configure.host (HOSTING_CRT0): Parse output of gcc --help --verbose + to determine dynamic linker name. + +2005-07-18 Nick Clifton + + * configure.tgt: Restore alpha ordering to list of arches. + +2005-07-16 Alan Modra + + * emultempl/elf32.em (gld*_provide_init_fini_syms): Prototype. + (gld*_before_allocation): Call ldemul_do_assignments rather than + gld*_provide_init_fini_syms directly. + * emultempl/ppc32elf.em (gld*_after_allocation): Delete. + (ppc_do_assignments): New function. + (LDEMUL_AFTER_ALLOCATION): Don't define. + (LDEMUL_DO_ASSIGNMENTS): Define. + +2005-07-16 Alan Modra + + * Makefile.am: Run "make dep-am". + (emipsidt.c, emipsidtl.c): Depend on generic.em. + * Makefile.in: Regenerate. + +2005-07-15 Alan Modra + + * ldemul.c (ldemul_do_assignments): New function. + (do_assignments_default): New function. + * ldemul.h (ldemul_do_assignments): Declare. + (do_assignments_default): Declare. + (struct ld_emulation_xfer_struct): Add do_assignments. + * ldlang.c (lang_do_assignments) Call ldemul_do_assignments. + * emultempl/aix.em (ld_*_emulation): Init do_assignments field. + * emultempl/armcoff.em: Likewise. + * emultempl/beos.em: Likewise. + * emultempl/generic.em: Likewise. + * emultempl/gld960.em: Likewise. + * emultempl/gld960c.em: Likewise. + * emultempl/linux.em: Likewise. + * emultempl/lnk960.em: Likewise. + * emultempl/m68kcoff.em: Likewise. + * emultempl/pe.em: Likewise. + * emultempl/sunos.em: Likewise. + * emultempl/ticoff.em: Likewise. + * emultempl/vanilla.em: Likewise. + * emultempl/elf32.em: Likewise, to call gld*_provide_init_fini_syms. + (gld*_find_exp_assignment): Adjust bfd_elf_record_link_assignment call. + +2005-07-14 Jim Blandy + + Add support for the Renesas M32C and M16C. + * Makefile.am (ALL_EMULATIONS): Add eelf32m32c.o. + (eelf32m32c.c): New target. + * Makefile.in: Regenerated. + * configure.tgt: Add case for m32c-*-elf. + * emulparams/elf32m32c.sh: New file. + +2005-07-14 Alan Modra + + * ldlang.c (strip_excluded_output_sections): Don't call + bfd_gc_sections. + * emultempl/elf32.em (gld*_provide_bound_symbols): Move. + (gld*_provide_init_fini_syms): Move. + (gld*_before_allocation): Call the above from here.. + (gld*_finish): ..not here. Call _bfd_elf_fix_excluded_sec_syms. + * emultempl/hppaelf.em (hppaelf_finish): Likewise. + * emultempl/ppc64elf.em (ppc_finish): Likewise. + +2005-07-10 Ralf Corsepius + + * configure.tgt: Remove sparc*-*-rtemsaout*, i[3-7]86-go32-rtems*, + i[3-7]86-*-rtemscoff*, hppa*-*-rtems*, mips*el-*-rtems*, + powerpcle-*-rtems*. + +2005-07-09 Christopher Faylor + + * emultempl/pe.em (gld_${EMULATION_NAME}_before_parse): Enable runtime + relocation by default. + (compute_dll_image_base): Avoid linking into cygwin dll address space. + +2005-07-08 Alan Modra + + * ldlang.c (wild_sort): Formatting. + (strip_excluded_output_sections): Strip zero size sections here. + * emultempl/elf32.em (gld*_strip_empty_sections): Delete. + (gld*_finish): Don't call the above. + * emultempl/hppaelf.em (hppaelf_finish): Likewise. + * emultempl/ppc64elf.em (ppc_finish): Likewise. + +2005-07-05 Paul Brook + + * Makefile.am (ALL_EMULATIONS): Add eelf32ppcvxworks.o. + (eelf32ppcvxworks.o): Add dependencies. + * Makefile.in: Regenerate. + * configure.tgt: Add entry for powerpc-vxworks. + * emulparams/elf32-ppc.c: Mention elf32ppcvxworks.sh in comment. + * emulparams/elf32ppcvxworks.sh: New file. + * emultempl/ppc32elf.em (bfd_elf32_powerpc_vxworks_vec): Declare. + (is_ppc_elf32_vec): New function. + (ppc_after_open, ppc_before_allocation, + gld${EMULATION_NAME}_after_allocation): Use it. + +2005-07-05 Peter S. Mazinger" + + * emulparams/elf32bmip.sh (GENERATE_PIE_SCRIPT): Define as "yes". + * emulparams/elf32bmipn32-defs.sh (GENERATE_PIE_SCRIPT): Define as "yes". + +2005-07-04 Mike Frysinger + + * emulparams/hppalinux.sh (GENERATE_PIE_SCRIPT): Fix typo in + name. + +2005-07-04 Kazuhiro Inaoka + + * emulparams/m32relf_linux.sh (GENERATE_PIE_SCRIPT): Set to yes. + +2005-07-04 Aurelien Jarno + + * emultempl/elf32.em: Enable use of ld.so.conf for *-*-k*bsd-*. + +2005-07-01 Alan Modra + + * scripttempl/elf.sc (.gcc_except_table): Don't KEEP. + +2005-06-30 Ben Elliston + + * Makefile.am (check-DEJAGNU): Don't search for expect. + * Makefile.in: Regenerate. + +2005-06-30 Ben Elliston + + * Makefile.am (EXPECT): Set to expect. + (RUNTEST): Likewise, set to runtest. + * Makefile.in: Regenerate. + 2005-06-16 Alexander Klimov * emultempl/armelf.em: Add quotes to avoid a null test diff -uprN binutils-2.16.91.0.1/ld/configure.host binutils-2.16.91.0.2/ld/configure.host --- binutils-2.16.91.0.1/ld/configure.host 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/configure.host 2005-07-20 12:27:28.155050924 -0700 @@ -33,7 +33,7 @@ case "${host}" in ;; *-*-linux*) - HOSTING_CRT0='-dynamic-linker `specs=\`${CC} --print-file-name=specs\`; { if [ x"$specs" = xspecs ]; then ${CC} -dumpspecs; else cat "$specs"; fi; } | egrep "ld[^ ]*\.so" | sed -e "s,.*-dynamic-linker[ ][ ]*\(.*/ld[^ ]*\.so..\).*,\1,"` `${CC} --print-file-name=crt1.o` `${CC} --print-file-name=crti.o` `if [ -f ../gcc/crtbegin.o ]; then echo ../gcc/crtbegin.o; else ${CC} --print-file-name=crtbegin.o; fi`' + HOSTING_CRT0='-dynamic-linker `${CC} --help --verbose 2>&1 | egrep "ld[^ ]*\.so" | sed -e "s,.*-dynamic-linker[ ][ ]*\(.*/ld[^ ]*\.so..\).*,\1,"` `${CC} --print-file-name=crt1.o` `${CC} --print-file-name=crti.o` `if [ -f ../gcc/crtbegin.o ]; then echo ../gcc/crtbegin.o; else ${CC} --print-file-name=crtbegin.o; fi`' HOSTING_LIBS='-L`dirname \`${CC} --print-file-name=libc.so\`` '"$HOSTING_LIBS"' `if [ -f ../gcc/crtend.o ]; then echo ../gcc/crtend.o; else ${CC} --print-file-name=crtend.o; fi` `${CC} --print-file-name=crtn.o`' ;; diff -uprN binutils-2.16.91.0.1/ld/configure.tgt binutils-2.16.91.0.2/ld/configure.tgt --- binutils-2.16.91.0.1/ld/configure.tgt 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/configure.tgt 2005-07-20 12:27:28.158050429 -0700 @@ -15,18 +15,80 @@ targ_extra_emuls= targ_extra_ofiles= +# Please try to keep this table in alphabetic order - it makes it +# much easier to lookup a specific archictecture. Naturally any +# architecture variants should be kept together even if their names +# break the alpha sorting. case "${targ}" in -am33_2.0-*-linux*) targ_emul=elf32am33lin ;; -arm-epoc-pe) targ_emul=arm_epoc_pe ; - targ_extra_ofiles="deffilep.o pe-dll.o" ;; -arm-*-wince) targ_emul=armpe ; +a29k-*-udi) targ_emul=sa29200 ;; +a29k-*-ebmon) targ_emul=ebmon29k ;; +a29k-*-*) targ_emul=a29k + ;; +alpha*-*-freebsd* | alpha*-*-kfreebsd*-gnu) + targ_emul=elf64alpha_fbsd + targ_extra_emuls="elf64alpha alpha" + tdir_alpha=`echo ${targ_alias} | sed -e 's/freebsd/freebsdecoff/'` ;; +alpha*-*-linuxecoff*) targ_emul=alpha targ_extra_emuls=elf64alpha + tdir_elf64alpha=`echo ${targ_alias} | sed -e 's/ecoff//'` ;; +alpha*-*-linux-*) targ_emul=elf64alpha targ_extra_emuls=alpha + tdir_alpha=`echo ${targ_alias} | sed -e 's/linux/linuxecoff/'` ;; +alpha*-*-osf*) targ_emul=alpha ;; +alpha*-*-gnu*) targ_emul=elf64alpha ;; +alpha*-*-netware*) targ_emul=alpha ;; +alpha*-*-netbsd*) targ_emul=elf64alpha_nbsd ;; +alpha*-*-openbsd*) targ_emul=elf64alpha + ;; +arc-*-elf*) targ_emul=arcelf + ;; +arm-epoc-pe) targ_emul=arm_epoc_pe ; targ_extra_ofiles="deffilep.o pe-dll.o" ;; +arm-*-wince) targ_emul=armpe ; targ_extra_ofiles="deffilep.o pe-dll.o" ;; +arm-*-pe) targ_emul=armpe ; targ_extra_ofiles="deffilep.o pe-dll.o" ;; +arm-*-aout | armel-*-aout) targ_emul=armaoutl ;; +armeb-*-aout) targ_emul=armaoutb ;; +arm-*-coff) targ_emul=armcoff ;; +arm-*-freebsd* | arm-*-kfreebsd*-gnu) + targ_emul=armelf_fbsd + targ_extra_emuls="armelf" ;; +armeb-*-netbsdelf*) targ_emul=armelfb_nbsd; + targ_extra_emuls="armelf_nbsd armelf armnbsd" ;; +arm-*-netbsdelf*) targ_emul=armelf_nbsd; + targ_extra_emuls="armelfb_nbsd armelf armnbsd" ;; +arm-*-netbsd*) targ_emul=armnbsd; + targ_extra_emuls="armelf armelf_nbsd armelfb_nbsd" ;; +arm-*-nto*) targ_emul=armnto ;; +arm-*-openbsd*) targ_emul=armnbsd ;; +arm-*-rtems*) targ_emul=armelf ;; +armeb-*-elf) targ_emul=armelfb ;; +arm-*-elf | arm*-*-eabi*) + targ_emul=armelf ;; +arm*-*-symbianelf*) targ_emul=armsymbian;; +arm-*-kaos*) targ_emul=armelf ;; +arm9e-*-elf) targ_emul=armelf ;; +arm*b-*-linux-gnueabi) targ_emul=armelfb_linux_eabi ;; +arm*b-*-linux-*) targ_emul=armelfb_linux; targ_extra_emuls=armelfb ;; +arm*-*-linux-gnueabi) targ_emul=armelf_linux_eabi ;; +arm*-*-linux-*) targ_emul=armelf_linux; targ_extra_emuls=armelf ;; +arm*-*-uclinux*) targ_emul=armelf_linux; targ_extra_emuls=armelf ;; +arm-*-vxworks) targ_emul=armelf_vxworks ;; +arm*-*-conix*) targ_emul=armelf ;; +thumb-*-linux-* | thumb-*-uclinux*) targ_emul=armelf_linux; targ_extra_emuls=armelf ;; +strongarm-*-coff) targ_emul=armcoff ;; +strongarm-*-elf) targ_emul=armelf ;; +strongarm-*-kaos*) targ_emul=armelf ;; +thumb-*-coff) targ_emul=armcoff ;; +thumb-*-elf) targ_emul=armelf ;; +thumb-epoc-pe) targ_emul=arm_epoc_pe ; targ_extra_ofiles="deffilep.o pe-dll.o" ;; -arm-*-pe) targ_emul=armpe ; +thumb-*-pe) targ_emul=armpe ; targ_extra_ofiles="deffilep.o pe-dll.o" ;; -arc-*-elf*) targ_emul=arcelf ;; +xscale-*-coff) targ_emul=armcoff ;; +xscale-*-elf) targ_emul=armelf + ;; avr-*-*) targ_emul=avr2 - targ_extra_emuls="avr1 avr3 avr4 avr5" ;; -cr16c-*-elf*) targ_emul=elf32cr16c ;; + targ_extra_emuls="avr1 avr3 avr4 avr5" + ;; +cr16c-*-elf*) targ_emul=elf32cr16c + ;; cris-*-*aout*) targ_emul=crisaout targ_extra_emuls="criself crislinux" targ_extra_libpath=$targ_extra_emuls ;; @@ -34,108 +96,43 @@ cris-*-linux-* | crisv32-*-linux-*) targ_emul=crislinux ;; cris-*-* | crisv32-*-*) targ_emul=criself targ_extra_emuls="crisaout crislinux" - targ_extra_libpath=$targ_extra_emuls ;; -crx-*-elf*) targ_emul=elf32crx ;; + targ_extra_libpath=$targ_extra_emuls + ;; +crx-*-elf*) targ_emul=elf32crx + ;; d10v-*-*) targ_emul=d10velf ;; d30v-*-*ext*) targ_emul=d30v_e; targ_extra_emuls="d30velf d30v_o" ;; d30v-*-*onchip*) targ_emul=d30v_o; targ_extra_emuls="d30velf d30v_e" ;; -d30v-*-*) targ_emul=d30velf; targ_extra_emuls="d30v_e d30v_o" ;; -dlx-*-elf*) targ_emul=elf32_dlx ;; -ms1-*elf) targ_emul=elf32ms1 ;; -sparc64-*-aout*) targ_emul=sparcaout ;; -sparc64-*-elf*) targ_emul=elf64_sparc ;; -sparc-sun-sunos4*) targ_emul=sun4 ;; -sparclite*-*-elf) targ_emul=elf32_sparc ;; -sparclite*-*-coff) targ_emul=coff_sparc ;; -sparclite*-fujitsu-*) targ_emul=sparcaout ;; -sparc*-*-aout) targ_emul=sparcaout ;; -sparc*-*-coff) targ_emul=coff_sparc ;; -sparc*-*-elf) targ_emul=elf32_sparc ;; -sparc*-*-sysv4*) targ_emul=elf32_sparc ;; -sparc64-*-freebsd* | sparcv9-*-freebsd* | sparc64-*-kfreebsd*-gnu | sparcv9-*-kfreebsd*-gnu) - targ_emul=elf64_sparc_fbsd - targ_extra_emuls="elf64_sparc elf32_sparc" - targ_extra_libpath=$targ_extra_emuls - tdir_elf32_sparc=`echo ${targ_alias} | sed -e 's/64//'` +d30v-*-*) targ_emul=d30velf; targ_extra_emuls="d30v_e d30v_o" ;; -sparc*-*-linux*aout*) targ_emul=sparclinux - targ_extra_emuls="elf32_sparc sun4" - tdir_elf32_sparc=`echo ${targ_alias} | sed -e 's/aout//'` - tdir_sun4=sparc-sun-sunos4 +dlx-*-elf*) targ_emul=elf32_dlx ;; -sparc64-*-linux-*) targ_emul=elf64_sparc - targ_extra_emuls="elf32_sparc sparclinux sun4" - targ_extra_libpath=elf32_sparc - tdir_elf32_sparc=`echo ${targ_alias} | sed -e 's/64//'` - tdir_sparclinux=${tdir_elf32_sparc}aout - tdir_sun4=sparc-sun-sunos4 +fr30-*-*) targ_emul=elf32fr30 ;; -sparc*-*-linux-*) targ_emul=elf32_sparc - targ_extra_emuls="sparclinux elf64_sparc sun4" - targ_extra_libpath=elf64_sparc - tdir_sparclinux=${targ_alias}aout - tdir_elf64_sparc=`echo ${targ_alias} | sed -e 's/32//'` - tdir_sun4=sparc-sun-sunos4 +frv-*-*linux*) targ_emul=elf32frvfd ;; +frv-*-*) targ_emul=elf32frv ; targ_extra_emuls="elf32frvfd" ;; -sparc64-*-netbsd* | sparc64-*-openbsd*) - targ_emul=elf64_sparc - targ_extra_emuls="elf32_sparc" +h8300-*-hms* | h8300-*-coff* | h8300-*-rtemscoff*) + targ_emul=h8300; targ_extra_emuls="h8300h h8300s h8300hn h8300sn h8300sx h8300sxn" ;; +h8300-*-elf* | h8300-*-rtems*) + targ_emul=h8300elf; + targ_extra_emuls="h8300helf h8300self h8300hnelf h8300snelf h8300sxelf h8300sxnelf" ;; +h8500-*-hms* | h8500-*-coff* | h8500-*-rtems*) + targ_emul=h8500 + targ_extra_emuls="h8500s h8500b h8500m h8500c" ;; -sparc*-*-netbsd*elf*) targ_emul=elf32_sparc ;; -sparc*-*-netbsd*) targ_emul=sparcnbsd ;; -sparc-*-solaris2.[0-6] | sparc-*-solaris2.[0-6].*) - targ_emul=elf32_sparc ;; -sparc-*-solaris2*) targ_emul=elf32_sparc - targ_extra_emuls="elf64_sparc" - targ_extra_libpath=$targ_extra_emuls - tdir_elf64_sparc=`echo ${targ_alias} | sed -e 's/32//'` +hppa*64*-*-linux-*) targ_emul=hppa64linux ;; +hppa*64*-*) targ_emul=elf64hppa ;; +hppa*-*-linux-*) targ_emul=hppalinux ;; +hppa*-*-*elf*) targ_emul=hppaelf ;; +hppa*-*-lites*) targ_emul=hppaelf ;; +hppa*-*-netbsd*) targ_emul=hppanbsd ;; +hppa*-*-openbsd*) targ_emul=hppaobsd ;; -sparcv9-*-solaris2* | sparc64-*-solaris2*) - targ_emul=elf64_sparc - targ_extra_emuls="elf32_sparc" - targ_extra_libpath=$targ_extra_emuls - tdir_elf32_sparc=`echo ${targ_alias} | sed -e 's/64//'` +i370-*-elf* | i370-*-linux-*) targ_emul=elf32i370 ;; -sparc*-*-solaris2*) targ_emul=elf32_sparc ;; -sparc*-wrs-vxworks*) targ_emul=sparcaout ;; -sparc*-*-rtemsaout*) targ_emul=sparcaout ;; -sparc*-*-rtemself*) targ_emul=elf32_sparc ;; -sparc*-*-rtems*) targ_emul=elf32_sparc ;; -i860-*-coff) targ_emul=coff_i860 ;; -i860-stardent-sysv4* | i860-stardent-elf*) - targ_emul=elf32_i860 ;; -i960-wrs-vxworks5.0*) targ_emul=gld960 ;; -i960-wrs-vxworks5*) targ_emul=gld960coff ;; -i960-wrs-vxworks*) targ_emul=gld960 ;; -i960-*-coff) targ_emul=gld960coff ;; -i960-intel-nindy) targ_emul=gld960 ;; -i960-*-rtems*) targ_emul=gld960coff ;; -i960-*-elf*) targ_emul=elf32_i960 ;; -ia64-*-elf*) targ_emul=elf64_ia64 ;; -ia64-*-freebsd* | ia64-*-kfreebsd*-gnu) - targ_emul=elf64_ia64_fbsd - targ_extra_emuls="elf64_ia64" ;; -ia64-*-netbsd*) targ_emul=elf64_ia64 ;; -ia64-*-linux*) targ_emul=elf64_ia64 ;; -ia64-*-aix*) targ_emul=elf64_aix ;; -m32r*le-*-elf*) targ_emul=m32rlelf ;; -m32r*-*-elf*) targ_emul=m32relf ;; -m32r*le-*-linux-*) targ_emul=m32rlelf_linux ;; -m32r*-*-linux-*) targ_emul=m32relf_linux ;; -m68hc11-*-*|m6811-*-*) targ_emul=m68hc11elf - targ_extra_emuls="m68hc11elfb m68hc12elf m68hc12elfb" ;; -m68hc12-*-*|m6812-*-*) targ_emul=m68hc12elf - targ_extra_emuls="m68hc12elfb m68hc11elf m68hc11elfb" ;; -m68*-sun-sunos[34]*) targ_emul=sun3 ;; -m68*-wrs-vxworks*) targ_emul=sun3 ;; -m68*-ericsson-ose) targ_emul=sun3 ;; -m68*-apple-aux*) targ_emul=m68kaux ;; -maxq-*-coff) targ_emul=maxqcoff;; -*-tandem-none) targ_emul=st2000 ;; -i370-*-elf* | i370-*-linux-*) targ_emul=elf32i370 ;; i[3-7]86-*-nto-qnx*) targ_emul=i386nto ;; i[3-7]86-*-vsta) targ_emul=vsta ;; -i[3-7]86-go32-rtems*) targ_emul=i386go32 ;; i[3-7]86-*-go32) targ_emul=i386go32 ;; i[3-7]86-*-msdosdjgpp*) targ_emul=i386go32 ;; i[3-7]86-*-aix*) targ_emul=i386coff ;; @@ -143,7 +140,6 @@ i[3-7]86-*-sco*) targ_emul=i386coff ;; i[3-7]86-*-isc*) targ_emul=i386coff ;; i[3-7]86-*-lynxos*) targ_emul=i386lynx ;; i[3-7]86-*-coff) targ_emul=i386coff ;; -i[3-7]86-*-rtemscoff*) targ_emul=i386coff ;; i[3-7]86-*-rtemself*) targ_emul=elf_i386 ;; i[3-7]86-*-rtems*) targ_emul=elf_i386 ;; i[3-7]86-*-aros*) targ_emul=elf_i386 ;; @@ -153,22 +149,19 @@ i[3-7]86-*-bsdi*) targ_emul=i386bsd ;; i[3-7]86-*-aout) targ_emul=i386aout ;; i[3-7]86-*-linux*aout*) targ_emul=i386linux targ_extra_emuls=elf_i386 - tdir_elf_i386=`echo ${targ_alias} | sed -e 's/aout//'` - ;; + tdir_elf_i386=`echo ${targ_alias} | sed -e 's/aout//'` ;; i[3-7]86-*-linux*oldld) targ_emul=i386linux; targ_extra_emuls=elf_i386 ;; i[3-7]86-*-linux-*) targ_emul=elf_i386 targ_extra_emuls=i386linux if test x${want64} = xtrue; then targ_extra_emuls="$targ_extra_emuls elf_x86_64" fi - tdir_i386linux=${targ_alias}aout - ;; + tdir_i386linux=${targ_alias}aout ;; x86_64-*-linux-*) targ_emul=elf_x86_64 targ_extra_emuls="elf_i386 i386linux" targ_extra_libpath=elf_i386 tdir_i386linux=`echo ${targ_alias}aout | sed -e 's/x86_64/i386/'` - tdir_elf_i386=`echo ${targ_alias} | sed -e 's/x86_64/i386/'` - ;; + tdir_elf_i386=`echo ${targ_alias} | sed -e 's/x86_64/i386/'` ;; i[3-7]86-*-sysv[45]*) targ_emul=elf_i386 ;; i[3-7]86-*-solaris2*) targ_emul=elf_i386_ldso targ_extra_emuls="elf_i386 elf_x86_64" @@ -181,30 +174,23 @@ i[3-7]86-*-netbsdelf* | \ i[3-7]86-*-netbsd*-gnu* | \ i[3-7]86-*-knetbsd*-gnu) targ_emul=elf_i386 - targ_extra_emuls=i386nbsd - ;; + targ_extra_emuls=i386nbsd ;; i[3-7]86-*-netbsdpe*) targ_emul=i386pe - targ_extra_ofiles="deffilep.o pe-dll.o" - ;; + targ_extra_ofiles="deffilep.o pe-dll.o" ;; i[3-7]86-*-netbsd*) targ_emul=i386nbsd - targ_extra_emuls=elf_i386 - ;; + targ_extra_emuls=elf_i386 ;; x86_64-*-netbsd*) targ_emul=elf_x86_64 targ_extra_emuls="elf_i386 i386nbsd" tdir_elf_i386=`echo ${targ_alias} | \ sed -e 's/x86_64/i386/'` case "${tdir_elf_i386}" in - *-netbsdelf*) ;; - *) - tdir_elf_i386=`echo ${tdir_elf_i386} | \ - sed -e 's/netbsd/netbsdelf/'` - ;; - esac - ;; + *-netbsdelf*) ;; + *) tdir_elf_i386=`echo ${tdir_elf_i386} | \ + sed -e 's/netbsd/netbsdelf/'`;; + esac ;; i[3-7]86-*-netware) targ_emul=i386nw ;; i[3-7]86-*-elf*) targ_emul=elf_i386 ;; -x86_64-*-elf*) - targ_emul=elf_x86_64 +x86_64-*-elf*) targ_emul=elf_x86_64 targ_extra_emuls=elf_i386 ;; i[3-7]86-*-kaos*) targ_emul=elf_i386 ;; @@ -217,8 +203,7 @@ x86_64-*-freebsd* | x86_64-*-kfreebsd*-g targ_emul=elf_x86_64_fbsd targ_extra_emuls="elf_i386_fbsd elf_x86_64 elf_i386" tdir_elf_i386=`echo ${targ_alias} \ - | sed -e 's/x86_64/i386/'` - ;; + | sed -e 's/x86_64/i386/'` ;; i[3-7]86-*-sysv*) targ_emul=i386coff ;; i[3-7]86-*-ptx*) targ_emul=i386coff ;; i[3-7]86-*-mach*) targ_emul=i386mach ;; @@ -239,133 +224,47 @@ i[3-7]86-*-interix*) targ_emul=i386pe_po i[3-7]86-*-beospe*) targ_emul=i386beos ;; i[3-7]86-*-beos*) targ_emul=elf_i386_be ;; i[3-7]86-*-vxworks*) targ_emul=elf_i386_vxworks ;; -i[3-7]86-*-chaos) targ_emul=elf_i386_chaos ;; -m8*-*-*) targ_emul=m88kbcs ;; -a29k-*-udi) targ_emul=sa29200 ;; -a29k-*-ebmon) targ_emul=ebmon29k ;; -a29k-*-*) targ_emul=a29k ;; -# arm-*-riscix*) targ_emul=riscix ;; -arm-*-aout | armel-*-aout) targ_emul=armaoutl ;; -armeb-*-aout) targ_emul=armaoutb ;; -arm-*-coff) targ_emul=armcoff ;; -arm-*-freebsd* | arm-*-kfreebsd*-gnu) - targ_emul=armelf_fbsd - targ_extra_emuls="armelf" ;; -armeb-*-netbsdelf*) targ_emul=armelfb_nbsd; - targ_extra_emuls="armelf_nbsd armelf armnbsd" ;; -arm-*-netbsdelf*) targ_emul=armelf_nbsd; - targ_extra_emuls="armelfb_nbsd armelf armnbsd" ;; -arm-*-netbsd*) targ_emul=armnbsd; - targ_extra_emuls="armelf armelf_nbsd armelfb_nbsd" ;; -arm-*-nto*) targ_emul=armnto ;; -arm-*-openbsd*) targ_emul=armnbsd ;; -arm-*-rtems*) targ_emul=armelf ;; -armeb-*-elf) targ_emul=armelfb ;; -arm-*-elf | arm*-*-eabi*) - targ_emul=armelf ;; -arm*-*-symbianelf*) targ_emul=armsymbian;; -arm-*-kaos*) targ_emul=armelf ;; -arm9e-*-elf) targ_emul=armelf ;; -arm*b-*-linux-gnueabi) targ_emul=armelfb_linux_eabi ;; -arm*b-*-linux-*) targ_emul=armelfb_linux; targ_extra_emuls=armelfb ;; -arm*-*-linux-gnueabi) targ_emul=armelf_linux_eabi ;; -arm*-*-linux-*) targ_emul=armelf_linux; targ_extra_emuls=armelf ;; -arm*-*-uclinux*) targ_emul=armelf_linux; targ_extra_emuls=armelf ;; -arm-*-vxworks) targ_emul=armelf_vxworks ;; -arm*-*-conix*) targ_emul=armelf ;; -thumb-*-linux-* | thumb-*-uclinux*) targ_emul=armelf_linux; targ_extra_emuls=armelf ;; -strongarm-*-coff) targ_emul=armcoff ;; -strongarm-*-elf) targ_emul=armelf ;; -strongarm-*-kaos*) targ_emul=armelf ;; -thumb-*-coff) targ_emul=armcoff ;; -thumb-*-elf) targ_emul=armelf ;; -thumb-epoc-pe) targ_emul=arm_epoc_pe ; - targ_extra_ofiles="deffilep.o pe-dll.o" ;; -thumb-*-pe) targ_emul=armpe ; - targ_extra_ofiles="deffilep.o pe-dll.o" ;; -xscale-*-coff) targ_emul=armcoff ;; -xscale-*-elf) targ_emul=armelf ;; -h8300-*-hms* | h8300-*-coff* | h8300-*-rtemscoff*) - targ_emul=h8300; targ_extra_emuls="h8300h h8300s h8300hn h8300sn h8300sx h8300sxn" - ;; -h8300-*-elf* | h8300-*-rtems*) - targ_emul=h8300elf; - targ_extra_emuls="h8300helf h8300self h8300hnelf h8300snelf h8300sxelf h8300sxnelf" +i[3-7]86-*-chaos) targ_emul=elf_i386_chaos ;; -h8500-*-hms* | h8500-*-coff* | h8500-*-rtems*) - targ_emul=h8500 - targ_extra_emuls="h8500s h8500b h8500m h8500c" - ;; -sh-*-linux*) - targ_emul=shlelf_linux - targ_extra_emuls=shelf_linux - targ_extra_libpath=shelf_linux - ;; -sh64eb-*-linux*) targ_emul=shelf32_linux - targ_extra_emuls="shlelf32_linux" - ;; -sh64-*-linux*) targ_emul=shlelf32_linux - targ_extra_emuls="shelf32_linux" - targ_extra_libpath=shelf32_linux - ;; -sh*eb-*-linux*) - targ_emul=shelf_linux - ;; -sh*-*-linux*) - targ_emul=shlelf_linux - ;; -sh5le-*-netbsd*) - targ_emul=shlelf32_nbsd - targ_extra_emuls="shelf32_nbsd shelf64_nbsd shlelf64_nbsd shelf_nbsd shlelf_nbsd" - ;; -sh5-*-netbsd*) - targ_emul=shelf32_nbsd - targ_extra_emuls="shlelf32_nbsd shelf64_nbsd shlelf64_nbsd shelf_nbsd shlelf_nbsd" - ;; -sh64le-*-netbsd*) - targ_emul=shlelf64_nbsd - targ_extra_emuls="shelf64_nbsd shelf32_nbsd shlelf32_nbsd shelf_nbsd shlelf_nbsd" - ;; -sh64-*-netbsd*) - targ_emul=shelf64_nbsd - targ_extra_emuls="shlelf64_nbsd shelf32_nbsd shlelf32_nbsd shelf_nbsd shlelf_nbsd" - ;; -sh*l*-*-netbsdelf*) - targ_emul=shlelf_nbsd - targ_extra_emuls=shelf_nbsd - ;; -sh*-*-netbsdelf*) - targ_emul=shelf_nbsd - targ_extra_emuls=shlelf_nbsd +i860-*-coff) targ_emul=coff_i860 ;; +i860-stardent-sysv4* | i860-stardent-elf*) + targ_emul=elf32_i860 ;; -sh*-*-symbianelf*) - targ_emul=shlsymbian +i960-wrs-vxworks5.0*) targ_emul=gld960 ;; +i960-wrs-vxworks5*) targ_emul=gld960coff ;; +i960-wrs-vxworks*) targ_emul=gld960 ;; +i960-*-coff) targ_emul=gld960coff ;; +i960-intel-nindy) targ_emul=gld960 ;; +i960-*-rtems*) targ_emul=gld960coff ;; +i960-*-elf*) targ_emul=elf32_i960 ;; -shle*-*-elf* | sh[1234]*le*-*-elf | shle*-*-kaos*) - targ_emul=shlelf - targ_extra_emuls="shelf shl sh" +ia64-*-elf*) targ_emul=elf64_ia64 ;; +ia64-*-freebsd* | ia64-*-kfreebsd*-gnu) + targ_emul=elf64_ia64_fbsd + targ_extra_emuls="elf64_ia64" ;; +ia64-*-netbsd*) targ_emul=elf64_ia64 ;; +ia64-*-linux*) targ_emul=elf64_ia64 ;; +ia64-*-aix*) targ_emul=elf64_aix ;; -sh-*-rtemscoff*) targ_emul=sh; targ_extra_emuls=shl ;; -sh-*-elf* | sh[1234]*-*-elf | sh-*-rtems* | sh-*-kaos* | sh-*-vxworks) - targ_emul=shelf - targ_extra_emuls="shlelf sh shl" +ip2k-*-elf) targ_emul=elf32ip2k ;; -sh-*-nto*) targ_emul=shelf_nto - targ_extra_emuls=shlelf_nto +iq2000-*-elf) targ_emul=elf32iq2000 ; targ_extra_emuls="elf32iq10" ;; -sh-*-pe) targ_emul=shpe ; - targ_extra_ofiles="deffilep.o pe-dll.o" ;; -sh-*-*) targ_emul=sh; targ_extra_emuls=shl ;; -sh64le-*-elf*) - targ_emul=shlelf - targ_extra_emuls="shelf shlelf32 shelf32 shlelf64 shelf64" - targ_extra_libpath=$targ_extra_emuls +m32c-*-elf) targ_emul=elf32m32c ;; -sh64-*-elf*) - targ_emul=shelf - targ_extra_emuls="shlelf shelf32 shlelf32 shelf64 shlelf64" - targ_extra_libpath=$targ_extra_emuls +m32r*le-*-elf*) targ_emul=m32rlelf ;; +m32r*-*-elf*) targ_emul=m32relf ;; +m32r*le-*-linux-*) targ_emul=m32rlelf_linux ;; +m32r*-*-linux-*) targ_emul=m32relf_linux ;; +m68hc11-*-*|m6811-*-*) targ_emul=m68hc11elf + targ_extra_emuls="m68hc11elfb m68hc12elf m68hc12elfb" ;; +m68hc12-*-*|m6812-*-*) targ_emul=m68hc12elf + targ_extra_emuls="m68hc12elfb m68hc11elf m68hc11elfb" ;; +m68*-sun-sunos[34]*) targ_emul=sun3 ;; +m68*-wrs-vxworks*) targ_emul=sun3 ;; +m68*-ericsson-ose) targ_emul=sun3 ;; +m68*-apple-aux*) targ_emul=m68kaux ;; m68k-sony-*) targ_emul=news ;; m68k-hp-bsd*) targ_emul=hp300bsd ;; m68*-motorola-sysv*) targ_emul=delta68 ;; @@ -375,12 +274,10 @@ m68*-*-elf) targ_emul=m68kelf ;; m68*-*-hpux*) targ_emul=hp3hpux ;; m68k-*-linux*aout*) targ_emul=m68klinux targ_extra_emuls=m68kelf - tdir_m68kelf=`echo ${targ_alias} | sed -e 's/aout//'` - ;; + tdir_m68kelf=`echo ${targ_alias} | sed -e 's/aout//'` ;; m68k-*-linux-*) targ_emul=m68kelf targ_extra_emuls=m68klinux - tdir_m68klinux=`echo ${targ_alias} | sed -e 's/linux/linuxaout/'` - ;; + tdir_m68klinux=`echo ${targ_alias} | sed -e 's/linux/linuxaout/'` ;; m68k-*-uclinux*) targ_emul=m68kelf ;; m68*-*-gnu*) targ_emul=m68kelf ;; m68*-*-netbsd*4k*) targ_emul=m68k4knbsd @@ -392,22 +289,16 @@ m68*-*-netbsdaout* | m68*-*-netbsd*) targ_extra_emuls="m68kelfnbsd m68k4knbsd" ;; m68*-*-psos*) targ_emul=m68kpsos ;; m68*-*-rtemscoff*) targ_emul=m68kcoff ;; -m68*-*-rtems*) targ_emul=m68kelf ;; -hppa*64*-*-linux-*) targ_emul=hppa64linux ;; -hppa*64*-*) targ_emul=elf64hppa ;; -hppa*-*-linux-*) targ_emul=hppalinux ;; -hppa*-*-*elf*) targ_emul=hppaelf ;; -hppa*-*-lites*) targ_emul=hppaelf ;; -hppa*-*-netbsd*) targ_emul=hppanbsd ;; -hppa*-*-openbsd*) targ_emul=hppaobsd ;; -hppa*-*-rtems*) targ_emul=hppaelf ;; -vax-dec-ultrix* | vax-dec-bsd*) targ_emul=vax ;; -vax-*-netbsdelf*) targ_emul=elf32vax - targ_extra_emuls=vaxnbsd ;; -vax-*-netbsdaout* | vax-*-netbsd*) - targ_emul=vaxnbsd - targ_extra_emuls=elf32vax ;; -vax-*-linux-*) targ_emul=elf32vax ;; +m68*-*-rtems*) targ_emul=m68kelf + ;; +m8*-*-*) targ_emul=m88kbcs + ;; +maxq-*-coff) targ_emul=maxqcoff + ;; +mcore-*-pe) targ_emul=mcorepe ; + targ_extra_ofiles="deffilep.o pe-dll.o" ;; +mcore-*-elf) targ_emul=elf32mcore + ;; mips*-*-pe) targ_emul=mipspe ; targ_extra_ofiles="deffilep.o pe-dll.o" ;; mips*-dec-ultrix*) targ_emul=mipslit ;; @@ -415,17 +306,14 @@ mips*-dec-osf*) targ_emul=mipslit ;; mips*-sgi-irix5*) targ_emul=elf32bsmip ;; mips*-sgi-irix6*) targ_emul=elf32bmipn32 targ_extra_emuls="elf32bsmip elf64bmip" - targ_extra_libpath=$targ_extra_emuls - ;; + targ_extra_libpath=$targ_extra_emuls ;; mips*-sgi-irix*) targ_emul=mipsbig ;; mips*el-*-ecoff*) targ_emul=mipsidtl ;; mips*-*-ecoff*) targ_emul=mipsidt ;; mips*el-*-netbsd*) targ_emul=elf32lmip - targ_extra_emuls="elf32bmip" - ;; + targ_extra_emuls="elf32bmip" ;; mips*-*-netbsd*) targ_emul=elf32bmip - targ_extra_emuls="elf32lmip" - ;; + targ_extra_emuls="elf32lmip" ;; mips*-*-bsd*) targ_emul=mipsbig ;; mips*vr4300el-*-elf*) targ_emul=elf32l4300 ;; mips*vr4300-*-elf*) targ_emul=elf32b4300 ;; @@ -435,7 +323,6 @@ mips*vr5000el-*-elf*) targ_emul=elf32l43 mips*vr5000-*-elf*) targ_emul=elf32b4300 ;; mips*el-*-elf*) targ_emul=elf32elmip ;; mips*-*-elf*) targ_emul=elf32ebmip ;; -mips*el-*-rtems*) targ_emul=elf32elmip ;; mips*-*-rtems*) targ_emul=elf32ebmip ;; mips*el-*-vxworks*) targ_emul=elf32elmip ;; mips*-*-vxworks*) targ_emul=elf32ebmip @@ -443,100 +330,91 @@ mips*-*-vxworks*) targ_emul=elf32ebmip mips*-*-windiss) targ_emul=elf32mipswindiss ;; mips64*el-*-linux-*) targ_emul=elf32ltsmipn32 targ_extra_emuls="elf32btsmipn32 elf32ltsmip elf32btsmip elf64ltsmip elf64btsmip" - targ_extra_libpath="elf32ltsmip elf64ltsmip" - ;; + targ_extra_libpath="elf32ltsmip elf64ltsmip" ;; mips64*-*-linux-*) targ_emul=elf32btsmipn32 targ_extra_emuls="elf32ltsmipn32 elf32btsmip elf32ltsmip elf64btsmip elf64ltsmip" - targ_extra_libpath="elf32btsmip elf64btsmip" - ;; + targ_extra_libpath="elf32btsmip elf64btsmip" ;; mips*el-*-linux-*) targ_emul=elf32ltsmip - targ_extra_emuls="elf32btsmip elf32ltsmipn32 elf64ltsmip elf32btsmipn32 elf64btsmip" - ;; + targ_extra_emuls="elf32btsmip elf32ltsmipn32 elf64ltsmip elf32btsmipn32 elf64btsmip" ;; mips*-*-linux-*) targ_emul=elf32btsmip - targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" - ;; + targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;; mips*-*-lnews*) targ_emul=mipslnews ;; -mips*-*-sysv4*) targ_emul=elf32btsmip ;; +mips*-*-sysv4*) targ_emul=elf32btsmip + ;; mmix-*-*) targ_emul=mmo targ_extra_emuls=elf64mmix ;; +am33_2.0-*-linux*) targ_emul=elf32am33lin ;; mn10200-*-*) targ_emul=mn10200 ;; -mn10300-*-*) targ_emul=mn10300 ;; -msp430-*-*) targ_emul=msp430x110 - targ_extra_emuls="msp430x112 msp430x1101 msp430x1111 msp430x1121 msp430x1122 msp430x1132 msp430x122 msp430x123 msp430x1222 msp430x1232 msp430x133 msp430x135 msp430x1331 msp430x1351 msp430x147 msp430x148 msp430x149 msp430x155 msp430x156 msp430x157 msp430x167 msp430x168 msp430x169 msp430x1610 msp430x1611 msp430x1612 msp430x311 msp430x312 msp430x313 msp430x314 msp430x315 msp430x323 msp430x325 msp430x336 msp430x337 msp430x412 msp430x413 msp430x415 msp430x417 msp430xE423 msp430xE425 msp430xE427 msp430xW423 msp430xW425 msp430xW427 msp430xG437 msp430xG438 msp430xG439 msp430x435 msp430x436 msp430x437 msp430x447 msp430x448 msp430x449" ;; -alpha*-*-freebsd* | alpha*-*-kfreebsd*-gnu) - targ_emul=elf64alpha_fbsd - targ_extra_emuls="elf64alpha alpha" - tdir_alpha=`echo ${targ_alias} | sed -e 's/freebsd/freebsdecoff/'` +mn10300-*-*) targ_emul=mn10300 ;; -alpha*-*-linuxecoff*) targ_emul=alpha targ_extra_emuls=elf64alpha - tdir_elf64alpha=`echo ${targ_alias} | sed -e 's/ecoff//'` +ms1-*elf) targ_emul=elf32ms1 ;; -alpha*-*-linux-*) targ_emul=elf64alpha targ_extra_emuls=alpha - tdir_alpha=`echo ${targ_alias} | sed -e 's/linux/linuxecoff/'` +msp430-*-*) targ_emul=msp430x110 + targ_extra_emuls="msp430x112 msp430x1101 msp430x1111 msp430x1121 msp430x1122 msp430x1132 msp430x122 msp430x123 msp430x1222 msp430x1232 msp430x133 msp430x135 msp430x1331 msp430x1351 msp430x147 msp430x148 msp430x149 msp430x155 msp430x156 msp430x157 msp430x167 msp430x168 msp430x169 msp430x1610 msp430x1611 msp430x1612 msp430x311 msp430x312 msp430x313 msp430x314 msp430x315 msp430x323 msp430x325 msp430x336 msp430x337 msp430x412 msp430x413 msp430x415 msp430x417 msp430xE423 msp430xE425 msp430xE427 msp430xW423 msp430xW425 msp430xW427 msp430xG437 msp430xG438 msp430xG439 msp430x435 msp430x436 msp430x437 msp430x447 msp430x448 msp430x449" + ;; +ns32k-pc532-mach* | ns32k-pc532-ux*) targ_emul=pc532macha ;; +ns32k-*-netbsd* | ns32k-pc532-lites*) targ_emul=ns32knbsd ;; -alpha*-*-osf*) targ_emul=alpha ;; -alpha*-*-gnu*) targ_emul=elf64alpha ;; -alpha*-*-netware*) targ_emul=alpha ;; -alpha*-*-netbsd*) targ_emul=elf64alpha_nbsd ;; -alpha*-*-openbsd*) targ_emul=elf64alpha ;; -z8k-*-coff) targ_emul=z8002; targ_extra_emuls=z8001 ;; -ns32k-pc532-mach* | ns32k-pc532-ux*) targ_emul=pc532macha ;; -ns32k-*-netbsd* | ns32k-pc532-lites*) targ_emul=ns32knbsd ;; openrisc-*-*) targ_emul=elf32openrisc ;; or32-*-coff) targ_emul=or32 ;; or32-*-elf) targ_emul=or32elf ;; -or32-*-rtems*) targ_emul=or32elf ;; -pdp11-*-*) targ_emul=pdp11 ;; +or32-*-rtems*) targ_emul=or32elf + ;; +pdp11-*-*) targ_emul=pdp11 + ;; pjl*-*-*) targ_emul=pjlelf ; targ_extra_emuls="elf_i386" ;; -pj*-*-*) targ_emul=pjelf ;; +pj*-*-*) targ_emul=pjelf + ;; powerpc-*-freebsd* | powerpc-*-kfreebsd*-gnu) targ_emul=elf32ppc_fbsd; targ_extra_emuls="elf32ppc elf32ppcsim"; targ_extra_libpath=elf32ppc; - tdir_elf32ppcsim=`echo ${targ_alias} | sed -e 's/ppc/ppcsim/'` - ;; -powerpc*-*-linux*) - case "${targ}" in - *64*) targ_emul=elf64ppc - targ_extra_emuls="elf32ppclinux elf32ppc elf32ppcsim" - targ_extra_libpath="elf32ppclinux elf32ppc" - tdir_elf32ppc=`echo "${targ_alias}" | sed -e 's/64//'` - tdir_elf32ppclinux=$tdir_elf32ppc - tdir_elf32ppcsim=$tdir_elf32ppc ;; - *) targ_emul=elf32ppclinux - targ_extra_emuls="elf32ppc elf32ppcsim" - targ_extra_libpath=elf32ppc - if test "${want64}" = "true"; then - targ_extra_emuls="$targ_extra_emuls elf64ppc" - targ_extra_libpath="$targ_extra_libpath elf64ppc" - fi - ;; - esac ;; + tdir_elf32ppcsim=`echo ${targ_alias} | sed -e 's/ppc/ppcsim/'` ;; +powerpc*-*-linux*) case "${targ}" in + *64*) targ_emul=elf64ppc + targ_extra_emuls="elf32ppclinux elf32ppc elf32ppcsim" + targ_extra_libpath="elf32ppclinux elf32ppc" + tdir_elf32ppc=`echo "${targ_alias}" | sed -e 's/64//'` + tdir_elf32ppclinux=$tdir_elf32ppc + tdir_elf32ppcsim=$tdir_elf32ppc + ;; + *) targ_emul=elf32ppclinux + targ_extra_emuls="elf32ppc elf32ppcsim" + targ_extra_libpath=elf32ppc + if test "${want64}" = "true"; then + targ_extra_emuls="$targ_extra_emuls elf64ppc" + targ_extra_libpath="$targ_extra_libpath elf64ppc" + fi ;; + esac ;; powerpc*le-*-elf* | powerpc*le-*-eabi* | powerpc*le-*-solaris* \ | powerpc*le-*-sysv* | powerpc*le-*-vxworks*) - case "${targ}" in - *64*) targ_emul=elf64lppc - targ_extra_emuls="elf32lppc elf32lppcsim" - tdir_elf32lppc=`echo "${targ_alias}" | sed -e 's/64//'` - tdir_elf32lppcsim=$tdir_elf32lppc ;; - *) targ_emul=elf32lppc - targ_extra_emuls="elf32ppcsim" ;; - esac ;; + case "${targ}" in + *64*) targ_emul=elf64lppc + targ_extra_emuls="elf32lppc elf32lppcsim" + tdir_elf32lppc=`echo "${targ_alias}" | sed -e 's/64//'` + tdir_elf32lppcsim=$tdir_elf32lppc + ;; + *) targ_emul=elf32lppc + targ_extra_emuls="elf32ppcsim" ;; + esac ;; powerpc*-*-elf* | powerpc*-*-eabi* | powerpc*-*-sysv* \ - | powerpc*-*-netbsd* | powerpc-*-openbsd* | powerpc*-*-vxworks* | powerpc*-*-kaos*) - case "${targ}" in - *64*) targ_emul=elf64ppc - targ_extra_emuls="elf32ppc elf32ppclinux elf32ppcsim" - tdir_elf32ppc=`echo "${targ_alias}" | sed -e 's/64//'` - tdir_elf32ppclinux=$tdir_elf32ppc - tdir_elf32ppcsim=$tdir_elf32ppc ;; - *) targ_emul=elf32ppc - targ_extra_emuls="elf32ppclinux elf32ppcsim" ;; - esac ;; + | powerpc*-*-netbsd* | powerpc-*-openbsd* | powerpc*-*-kaos*) + case "${targ}" in + *64*) targ_emul=elf64ppc + targ_extra_emuls="elf32ppc elf32ppclinux elf32ppcsim" + tdir_elf32ppc=`echo "${targ_alias}" | sed -e 's/64//'` + tdir_elf32ppclinux=$tdir_elf32ppc + tdir_elf32ppcsim=$tdir_elf32ppc + ;; + *) targ_emul=elf32ppc + targ_extra_emuls="elf32ppclinux elf32ppcsim" ;; + esac ;; +powerpc-*-vxworks*) + targ_emul=elf32ppcvxworks + targ_extra_emuls="elf32ppc elf32ppclinux elf32ppcsim" ;; powerpc-*-nto*) targ_emul=elf32ppcnto ;; powerpcle-*-nto*) targ_emul=elf32lppcnto ;; -powerpcle-*-rtems*) targ_emul=elf32leppc ;; powerpc-*-rtems*) targ_emul=elf32ppc ;; powerpc-*-macos*) targ_emul=ppcmacos ;; powerpc-*-netware*) targ_emul=ppcnw ;; @@ -549,25 +427,8 @@ powerpc-*-beos*) targ_emul=aixppc ;; powerpc-*-windiss*) targ_emul=elf32ppcwindiss ;; powerpc-*-lynxos*) targ_emul=ppclynx ;; rs6000-*-aix5*) targ_emul=aix5rs6 ;; -rs6000-*-aix*) targ_emul=aixrs6 ;; -tic30-*-*aout*) targ_emul=tic30aout ;; -tic30-*-*coff*) targ_emul=tic30coff ;; -tic4x-*-* | c4x-*-*) targ_emul=tic4xcoff ; targ_extra_emuls="tic3xcoff tic3xcoff_onchip" ;; -tic54x-*-* | c54x*-*-*) targ_emul=tic54xcoff ;; -tic80-*-*) targ_emul=tic80coff ;; -v850-*-*) targ_emul=v850 ;; -v850e-*-*) targ_emul=v850 ;; -v850ea-*-*) targ_emul=v850 ;; -iq2000-*-elf) targ_emul=elf32iq2000 ; targ_extra_emuls="elf32iq10" ;; -frv-*-*linux*) targ_emul=elf32frvfd ;; -frv-*-*) targ_emul=elf32frv ; targ_extra_emuls="elf32frvfd" ;; -w65-*-*) targ_emul=w65 ;; -xstormy16-*-*) targ_emul=elf32xstormy16 ;; -xtensa-*-*) targ_emul=elf32xtensa;; -fr30-*-*) targ_emul=elf32fr30 ;; -mcore-*-pe) targ_emul=mcorepe ; - targ_extra_ofiles="deffilep.o pe-dll.o" ;; -mcore-*-elf) targ_emul=elf32mcore ;; +rs6000-*-aix*) targ_emul=aixrs6 + ;; s390x-*-linux*) targ_emul=elf64_s390 targ_extra_emuls=elf_s390 targ_extra_libpath=$targ_extra_emuls @@ -579,10 +440,131 @@ s390-*-linux*) targ_emul=elf_s3 targ_extra_emuls=elf64_s390 targ_extra_libpath=$targ_extra_emuls tdir_elf64_s390=`echo ${targ_alias} | sed -e 's/s390/s390x/'` - fi ;; -*-*-ieee*) targ_emul=vanilla ;; -ip2k-*-elf) targ_emul=elf32ip2k ;; - + fi + ;; +sh-*-linux*) targ_emul=shlelf_linux + targ_extra_emuls=shelf_linux + targ_extra_libpath=shelf_linux ;; +sh64eb-*-linux*) targ_emul=shelf32_linux + targ_extra_emuls="shlelf32_linux" ;; +sh64-*-linux*) targ_emul=shlelf32_linux + targ_extra_emuls="shelf32_linux" + targ_extra_libpath=shelf32_linux ;; +sh*eb-*-linux*) targ_emul=shelf_linux ;; +sh*-*-linux*) targ_emul=shlelf_linux ;; +sh5le-*-netbsd*) targ_emul=shlelf32_nbsd + targ_extra_emuls="shelf32_nbsd shelf64_nbsd shlelf64_nbsd shelf_nbsd shlelf_nbsd" ;; +sh5-*-netbsd*) targ_emul=shelf32_nbsd + targ_extra_emuls="shlelf32_nbsd shelf64_nbsd shlelf64_nbsd shelf_nbsd shlelf_nbsd" ;; +sh64le-*-netbsd*) targ_emul=shlelf64_nbsd + targ_extra_emuls="shelf64_nbsd shelf32_nbsd shlelf32_nbsd shelf_nbsd shlelf_nbsd" ;; +sh64-*-netbsd*) targ_emul=shelf64_nbsd + targ_extra_emuls="shlelf64_nbsd shelf32_nbsd shlelf32_nbsd shelf_nbsd shlelf_nbsd" ;; +sh*l*-*-netbsdelf*) targ_emul=shlelf_nbsd + targ_extra_emuls=shelf_nbsd ;; +sh*-*-netbsdelf*) targ_emul=shelf_nbsd + targ_extra_emuls=shlelf_nbsd ;; +sh*-*-symbianelf*) targ_emul=shlsymbian ;; +shle*-*-elf* | sh[1234]*le*-*-elf | shle*-*-kaos*) + targ_emul=shlelf + targ_extra_emuls="shelf shl sh" ;; +sh-*-rtemscoff*) targ_emul=sh; targ_extra_emuls=shl ;; +sh-*-elf* | sh[1234]*-*-elf | sh-*-rtems* | sh-*-kaos* | sh-*-vxworks) + targ_emul=shelf + targ_extra_emuls="shlelf sh shl" ;; +sh-*-nto*) targ_emul=shelf_nto + targ_extra_emuls=shlelf_nto ;; +sh-*-pe) targ_emul=shpe ; + targ_extra_ofiles="deffilep.o pe-dll.o" ;; +sh-*-*) targ_emul=sh; targ_extra_emuls=shl ;; +sh64le-*-elf*) targ_emul=shlelf + targ_extra_emuls="shelf shlelf32 shelf32 shlelf64 shelf64" + targ_extra_libpath=$targ_extra_emuls ;; +sh64-*-elf*) targ_emul=shelf + targ_extra_emuls="shlelf shelf32 shlelf32 shelf64 shlelf64" + targ_extra_libpath=$targ_extra_emuls ;; +sparc64-*-aout*) targ_emul=sparcaout ;; +sparc64-*-elf*) targ_emul=elf64_sparc ;; +sparc-sun-sunos4*) targ_emul=sun4 ;; +sparclite*-*-elf) targ_emul=elf32_sparc ;; +sparclite*-*-coff) targ_emul=coff_sparc ;; +sparclite*-fujitsu-*) targ_emul=sparcaout ;; +sparc*-*-aout) targ_emul=sparcaout ;; +sparc*-*-coff) targ_emul=coff_sparc ;; +sparc*-*-elf) targ_emul=elf32_sparc ;; +sparc*-*-sysv4*) targ_emul=elf32_sparc ;; +sparc64-*-freebsd* | sparcv9-*-freebsd* | sparc64-*-kfreebsd*-gnu | sparcv9-*-kfreebsd*-gnu) + targ_emul=elf64_sparc_fbsd + targ_extra_emuls="elf64_sparc elf32_sparc" + targ_extra_libpath=$targ_extra_emuls + tdir_elf32_sparc=`echo ${targ_alias} | sed -e 's/64//'` ;; +sparc*-*-linux*aout*) targ_emul=sparclinux + targ_extra_emuls="elf32_sparc sun4" + tdir_elf32_sparc=`echo ${targ_alias} | sed -e 's/aout//'` + tdir_sun4=sparc-sun-sunos4 ;; +sparc64-*-linux-*) targ_emul=elf64_sparc + targ_extra_emuls="elf32_sparc sparclinux sun4" + targ_extra_libpath=elf32_sparc + tdir_elf32_sparc=`echo ${targ_alias} | sed -e 's/64//'` + tdir_sparclinux=${tdir_elf32_sparc}aout + tdir_sun4=sparc-sun-sunos4 ;; +sparc*-*-linux-*) targ_emul=elf32_sparc + targ_extra_emuls="sparclinux elf64_sparc sun4" + targ_extra_libpath=elf64_sparc + tdir_sparclinux=${targ_alias}aout + tdir_elf64_sparc=`echo ${targ_alias} | sed -e 's/32//'` + tdir_sun4=sparc-sun-sunos4 ;; +sparc64-*-netbsd* | sparc64-*-openbsd*) + targ_emul=elf64_sparc + targ_extra_emuls="elf32_sparc" ;; +sparc*-*-netbsd*elf*) targ_emul=elf32_sparc ;; +sparc*-*-netbsd*) targ_emul=sparcnbsd ;; +sparc-*-solaris2.[0-6] | sparc-*-solaris2.[0-6].*) + targ_emul=elf32_sparc ;; +sparc-*-solaris2*) targ_emul=elf32_sparc + targ_extra_emuls="elf64_sparc" + targ_extra_libpath=$targ_extra_emuls + tdir_elf64_sparc=`echo ${targ_alias} | sed -e 's/32//'` ;; +sparcv9-*-solaris2* | sparc64-*-solaris2*) + targ_emul=elf64_sparc + targ_extra_emuls="elf32_sparc" + targ_extra_libpath=$targ_extra_emuls + tdir_elf32_sparc=`echo ${targ_alias} | sed -e 's/64//'` ;; +sparc*-*-solaris2*) targ_emul=elf32_sparc ;; +sparc*-wrs-vxworks*) targ_emul=sparcaout ;; +sparc*-*-rtemself*) targ_emul=elf32_sparc ;; +sparc*-*-rtems*) targ_emul=elf32_sparc + ;; +tic30-*-*aout*) targ_emul=tic30aout ;; +tic30-*-*coff*) targ_emul=tic30coff ;; +tic4x-*-* | c4x-*-*) targ_emul=tic4xcoff ; targ_extra_emuls="tic3xcoff tic3xcoff_onchip" ;; +tic54x-*-* | c54x*-*-*) targ_emul=tic54xcoff ;; +tic80-*-*) targ_emul=tic80coff + ;; +v850-*-*) targ_emul=v850 ;; +v850e-*-*) targ_emul=v850 ;; +v850ea-*-*) targ_emul=v850 + ;; +vax-dec-ultrix* | vax-dec-bsd*) targ_emul=vax ;; +vax-*-netbsdelf*) targ_emul=elf32vax + targ_extra_emuls=vaxnbsd ;; +vax-*-netbsdaout* | vax-*-netbsd*) + targ_emul=vaxnbsd + targ_extra_emuls=elf32vax ;; +vax-*-linux-*) targ_emul=elf32vax + ;; +w65-*-*) targ_emul=w65 + ;; +xstormy16-*-*) targ_emul=elf32xstormy16 + ;; +xtensa-*-*) targ_emul=elf32xtensa + ;; +z8k-*-coff) targ_emul=z8002; targ_extra_emuls=z8001 + ;; +*-*-ieee*) targ_emul=vanilla + ;; +*-tandem-none) targ_emul=st2000 + ;; *) echo 2>&1 "*** ld does not support target ${targ}" echo 2>&1 "*** see ld/configure.tgt for supported targets" diff -uprN binutils-2.16.91.0.1/ld/emulparams/elf32bmipn32-defs.sh binutils-2.16.91.0.2/ld/emulparams/elf32bmipn32-defs.sh --- binutils-2.16.91.0.1/ld/emulparams/elf32bmipn32-defs.sh 2005-04-09 12:03:23.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emulparams/elf32bmipn32-defs.sh 2005-07-20 12:27:28.182046472 -0700 @@ -30,6 +30,7 @@ fi LIBPATH_SUFFIX=$ELFSIZE GENERATE_SHLIB_SCRIPT=yes +GENERATE_PIE_SCRIPT=yes TEXT_START_ADDR=0x10000000 MAXPAGESIZE=0x100000 diff -uprN binutils-2.16.91.0.1/ld/emulparams/elf32bmip.sh binutils-2.16.91.0.2/ld/emulparams/elf32bmip.sh --- binutils-2.16.91.0.1/ld/emulparams/elf32bmip.sh 2005-04-09 12:03:23.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emulparams/elf32bmip.sh 2005-07-20 12:27:28.181046637 -0700 @@ -39,3 +39,4 @@ ARCH=mips MACHINE= TEMPLATE_NAME=elf32 GENERATE_SHLIB_SCRIPT=yes +GENERATE_PIE_SCRIPT=yes diff -uprN binutils-2.16.91.0.1/ld/emulparams/elf32m32c.sh binutils-2.16.91.0.2/ld/emulparams/elf32m32c.sh --- binutils-2.16.91.0.1/ld/emulparams/elf32m32c.sh 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/ld/emulparams/elf32m32c.sh 2005-07-20 12:27:28.182046472 -0700 @@ -0,0 +1,24 @@ +MACHINE= +SCRIPT_NAME=elf +OUTPUT_FORMAT="elf32-m32c" +# See also `include/elf/m32c.h' +TEXT_START_ADDR=0x2000 +ARCH=m32c +ENTRY=_start +EMBEDDED=yes +ELFSIZE=32 +MAXPAGESIZE=256 +# This is like setting STACK_ADDR to 0x0073FFFF0, except that the setting can +# be overridden, e.g. --defsym _stack=0x0f00, and that we put an extra +# sentinal value at the bottom. +# N.B. We can't use PROVIDE to set the default value in a symbol because +# the address is needed to place the .stack section, which in turn is needed +# to hold the sentinel value(s). +test -z "$CREATE_SHLIB" && OTHER_SECTIONS=" .stack ${RELOCATING-0}${RELOCATING+(DEFINED(__stack) ? __stack : 0x7fc)} : + { + ${RELOCATING+__stack = .;} + *(.stack) + LONG(0xdeaddead) + }" +# We do not need .stack for shared library. +test -n "$CREATE_SHLIB" && OTHER_SECTIONS="" diff -uprN binutils-2.16.91.0.1/ld/emulparams/elf32ppc.sh binutils-2.16.91.0.2/ld/emulparams/elf32ppc.sh --- binutils-2.16.91.0.1/ld/emulparams/elf32ppc.sh 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emulparams/elf32ppc.sh 2005-07-20 12:27:28.186045812 -0700 @@ -1,5 +1,5 @@ # If you change this file, please also look at files which source this one: -# elf32lppc.sh elf32ppclinux.sh elf32ppcsim.sh +# elf32lppc.sh elf32ppclinux.sh elf32ppcsim.sh elf32ppcvxworks.sh TEMPLATE_NAME=elf32 EXTRA_EM_FILE=ppc32elf diff -uprN binutils-2.16.91.0.1/ld/emulparams/elf32ppcvxworks.sh binutils-2.16.91.0.2/ld/emulparams/elf32ppcvxworks.sh --- binutils-2.16.91.0.1/ld/emulparams/elf32ppcvxworks.sh 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/ld/emulparams/elf32ppcvxworks.sh 2005-07-20 12:27:28.186045812 -0700 @@ -0,0 +1,4 @@ +. ${srcdir}/emulparams/elf32ppc.sh +OUTPUT_FORMAT="elf32-powerpc-vxworks" +unset BSS_PLT +. ${srcdir}/emulparams/vxworks.sh diff -uprN binutils-2.16.91.0.1/ld/emulparams/hppalinux.sh binutils-2.16.91.0.2/ld/emulparams/hppalinux.sh --- binutils-2.16.91.0.1/ld/emulparams/hppalinux.sh 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emulparams/hppalinux.sh 2005-07-20 12:27:28.187045648 -0700 @@ -17,6 +17,6 @@ DATA_START_SYMBOLS='PROVIDE ($global$ = DATA_PLT= PLT_BEFORE_GOT= GENERATE_SHLIB_SCRIPT=yes -oGENERATE_PIE_SCRIPT=yes +GENERATE_PIE_SCRIPT=yes TEMPLATE_NAME=elf32 EXTRA_EM_FILE=hppaelf diff -uprN binutils-2.16.91.0.1/ld/emulparams/m32relf_linux.sh binutils-2.16.91.0.2/ld/emulparams/m32relf_linux.sh --- binutils-2.16.91.0.1/ld/emulparams/m32relf_linux.sh 2004-01-14 13:07:52.000000000 -0800 +++ binutils-2.16.91.0.2/ld/emulparams/m32relf_linux.sh 2005-07-20 12:27:28.194044493 -0700 @@ -11,3 +11,4 @@ MAXPAGESIZE=0x1000 # top of simulator memory (32MB). OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = 0x2000000);' GENERATE_SHLIB_SCRIPT=yes +GENERATE_PIE_SCRIPT=yes diff -uprN binutils-2.16.91.0.1/ld/emultempl/aix.em binutils-2.16.91.0.2/ld/emultempl/aix.em --- binutils-2.16.91.0.1/ld/emultempl/aix.em 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emultempl/aix.em 2005-07-20 12:27:28.195044329 -0700 @@ -1340,6 +1340,7 @@ struct ld_emulation_xfer_struct ld_${EMU gld${EMULATION_NAME}_set_output_arch, gld${EMULATION_NAME}_choose_target, gld${EMULATION_NAME}_before_allocation, + do_assignments_default, gld${EMULATION_NAME}_get_script, "${EMULATION_NAME}", "${OUTPUT_FORMAT}", diff -uprN binutils-2.16.91.0.1/ld/emultempl/armcoff.em binutils-2.16.91.0.2/ld/emultempl/armcoff.em --- binutils-2.16.91.0.1/ld/emultempl/armcoff.em 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emultempl/armcoff.em 2005-07-20 12:27:28.196044164 -0700 @@ -260,6 +260,7 @@ struct ld_emulation_xfer_struct ld_${EMU set_output_arch_default, ldemul_default_target, gld${EMULATION_NAME}_before_allocation, + do_assignments_default, gld${EMULATION_NAME}_get_script, "${EMULATION_NAME}", "${OUTPUT_FORMAT}", diff -uprN binutils-2.16.91.0.1/ld/emultempl/beos.em binutils-2.16.91.0.2/ld/emultempl/beos.em --- binutils-2.16.91.0.1/ld/emultempl/beos.em 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emultempl/beos.em 2005-07-20 12:27:28.197043999 -0700 @@ -767,6 +767,7 @@ struct ld_emulation_xfer_struct ld_${EMU set_output_arch_default, ldemul_default_target, gld_${EMULATION_NAME}_before_allocation, + do_assignments_default, gld_${EMULATION_NAME}_get_script, "${EMULATION_NAME}", "${OUTPUT_FORMAT}", diff -uprN binutils-2.16.91.0.1/ld/emultempl/elf32.em binutils-2.16.91.0.2/ld/emultempl/elf32.em --- binutils-2.16.91.0.1/ld/emultempl/elf32.em 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emultempl/elf32.em 2005-07-20 12:27:28.200043504 -0700 @@ -57,19 +57,18 @@ Foundation, Inc., 51 Franklin Street - F /* Declare functions used by various EXTRA_EM_FILEs. */ static void gld${EMULATION_NAME}_before_parse (void); static void gld${EMULATION_NAME}_after_open (void); +static void gld${EMULATION_NAME}_provide_init_fini_syms (void); static void gld${EMULATION_NAME}_before_allocation (void); static bfd_boolean gld${EMULATION_NAME}_place_orphan (lang_input_statement_type *file, asection *s); static void gld${EMULATION_NAME}_layout_sections_again (void); -static void gld${EMULATION_NAME}_strip_empty_sections (void); -static void gld${EMULATION_NAME}_provide_init_fini_syms (void); static void gld${EMULATION_NAME}_finish (void) ATTRIBUTE_UNUSED; EOF if [ "x${USE_LIBPATH}" = xyes ] ; then case ${target} in - *-*-linux-*) + *-*-linux-* | *-*-k*bsd*-*) cat >>e${EMULATION_NAME}.c < @@ -354,7 +353,7 @@ gld${EMULATION_NAME}_try_needed (struct EOF case ${target} in - *-*-linux-*) + *-*-linux-* | *-*-k*bsd*-*) cat >>e${EMULATION_NAME}.c <>e${EMULATION_NAME}.c <>e${EMULATION_NAME}.c <>e${EMULATION_NAME}.c <name, force)) break; @@ -983,8 +982,8 @@ gld${EMULATION_NAME}_find_exp_assignment will do no harm. */ if (strcmp (exp->assign.dst, ".") != 0) { - if (!bfd_elf_record_link_assignment (output_bfd, &link_info, - exp->assign.dst, provide)) + if (!bfd_elf_record_link_assignment (&link_info, exp->assign.dst, + provide)) einfo ("%P%F: failed to record assignment to %s: %E\n", exp->assign.dst); } @@ -1041,6 +1040,47 @@ if test x"$LDEMUL_BEFORE_ALLOCATION" != fi cat >>e${EMULATION_NAME}.c <>e${EMULATION_NAME}.c <output_section_statement; - os != NULL; - os = os->next) - { - asection *s; - - if (os == abs_output_section || os->constraint == -1) - continue; - s = os->bfd_section; - if (s != NULL - && s->size == 0 - && (s->flags & SEC_KEEP) == 0 - && !bfd_section_removed_from_list (output_bfd, s)) - { - bfd_section_list_remove (output_bfd, s); - output_bfd->section_count--; - } - } - } -} - -static void gld${EMULATION_NAME}_finish (void) { if (bfd_elf_discard_info (output_bfd, &link_info)) gld${EMULATION_NAME}_layout_sections_again (); - gld${EMULATION_NAME}_strip_empty_sections (); - gld${EMULATION_NAME}_provide_init_fini_syms (); + _bfd_elf_fix_excluded_sec_syms (output_bfd, &link_info); } EOF fi @@ -1912,6 +1882,7 @@ struct ld_emulation_xfer_struct ld_${EMU ${LDEMUL_SET_OUTPUT_ARCH-set_output_arch_default}, ${LDEMUL_CHOOSE_TARGET-ldemul_default_target}, ${LDEMUL_BEFORE_ALLOCATION-gld${EMULATION_NAME}_before_allocation}, + ${LDEMUL_DO_ASSIGNMENTS-gld${EMULATION_NAME}_provide_init_fini_syms}, ${LDEMUL_GET_SCRIPT-gld${EMULATION_NAME}_get_script}, "${EMULATION_NAME}", "${OUTPUT_FORMAT}", diff -uprN binutils-2.16.91.0.1/ld/emultempl/generic.em binutils-2.16.91.0.2/ld/emultempl/generic.em --- binutils-2.16.91.0.1/ld/emultempl/generic.em 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emultempl/generic.em 2005-07-20 12:27:28.201043339 -0700 @@ -128,6 +128,7 @@ struct ld_emulation_xfer_struct ld_${EMU ${LDEMUL_SET_OUTPUT_ARCH-set_output_arch_default}, ${LDEMUL_CHOOSE_TARGET-ldemul_default_target}, ${LDEMUL_BEFORE_ALLOCATION-before_allocation_default}, + ${LDEMUL_DO_ASSIGNMENTS-do_assignments_default}, ${LDEMUL_GET_SCRIPT-gld${EMULATION_NAME}_get_script}, "${EMULATION_NAME}", "${OUTPUT_FORMAT}", diff -uprN binutils-2.16.91.0.1/ld/emultempl/gld960c.em binutils-2.16.91.0.2/ld/emultempl/gld960c.em --- binutils-2.16.91.0.1/ld/emultempl/gld960c.em 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emultempl/gld960c.em 2005-07-20 12:27:28.203043010 -0700 @@ -149,6 +149,7 @@ struct ld_emulation_xfer_struct ld_gld96 gld960_set_output_arch, gld960_choose_target, before_allocation_default, + do_assignments_default, gld960_get_script, "960coff", "", diff -uprN binutils-2.16.91.0.1/ld/emultempl/gld960.em binutils-2.16.91.0.2/ld/emultempl/gld960.em --- binutils-2.16.91.0.1/ld/emultempl/gld960.em 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emultempl/gld960.em 2005-07-20 12:27:28.202043175 -0700 @@ -134,6 +134,7 @@ struct ld_emulation_xfer_struct ld_gld96 gld960_set_output_arch, gld960_choose_target, before_allocation_default, + do_assignments_default, gld960_get_script, "960", "", diff -uprN binutils-2.16.91.0.1/ld/emultempl/hppaelf.em binutils-2.16.91.0.2/ld/emultempl/hppaelf.em --- binutils-2.16.91.0.1/ld/emultempl/hppaelf.em 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emultempl/hppaelf.em 2005-07-20 12:27:28.204042845 -0700 @@ -305,8 +305,7 @@ hppaelf_finish (void) } } - gld${EMULATION_NAME}_strip_empty_sections (); - gld${EMULATION_NAME}_provide_init_fini_syms (); + _bfd_elf_fix_excluded_sec_syms (output_bfd, &link_info); } diff -uprN binutils-2.16.91.0.1/ld/emultempl/linux.em binutils-2.16.91.0.2/ld/emultempl/linux.em --- binutils-2.16.91.0.1/ld/emultempl/linux.em 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emultempl/linux.em 2005-07-20 12:27:28.205042680 -0700 @@ -189,6 +189,7 @@ struct ld_emulation_xfer_struct ld_${EMU set_output_arch_default, ldemul_default_target, gld${EMULATION_NAME}_before_allocation, + do_assignments_default, gld${EMULATION_NAME}_get_script, "${EMULATION_NAME}", "${OUTPUT_FORMAT}", diff -uprN binutils-2.16.91.0.1/ld/emultempl/lnk960.em binutils-2.16.91.0.2/ld/emultempl/lnk960.em --- binutils-2.16.91.0.1/ld/emultempl/lnk960.em 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emultempl/lnk960.em 2005-07-20 12:27:28.206042515 -0700 @@ -269,6 +269,7 @@ struct ld_emulation_xfer_struct ld_lnk96 lnk960_set_output_arch, lnk960_choose_target, before_allocation_default, + do_assignments_default, lnk960_get_script, "lnk960", "", diff -uprN binutils-2.16.91.0.1/ld/emultempl/m68kcoff.em binutils-2.16.91.0.2/ld/emultempl/m68kcoff.em --- binutils-2.16.91.0.1/ld/emultempl/m68kcoff.em 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emultempl/m68kcoff.em 2005-07-20 12:27:28.207042350 -0700 @@ -222,6 +222,7 @@ struct ld_emulation_xfer_struct ld_${EMU set_output_arch_default, ldemul_default_target, before_allocation_default, + do_assignments_default, gld${EMULATION_NAME}_get_script, "${EMULATION_NAME}", "${OUTPUT_FORMAT}", diff -uprN binutils-2.16.91.0.1/ld/emultempl/pe.em binutils-2.16.91.0.2/ld/emultempl/pe.em --- binutils-2.16.91.0.1/ld/emultempl/pe.em 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emultempl/pe.em 2005-07-20 12:27:28.212041526 -0700 @@ -135,7 +135,7 @@ gld_${EMULATION_NAME}_before_parse (void config.dynamic_link = TRUE; config.has_shared = 1; link_info.pei386_auto_import = -1; - link_info.pei386_runtime_pseudo_reloc = FALSE; + link_info.pei386_runtime_pseudo_reloc = -1; #if (PE_DEF_SUBSYSTEM == 9) || (PE_DEF_SUBSYSTEM == 2) #if defined TARGET_IS_mipspe || defined TARGET_IS_armpe @@ -667,7 +667,7 @@ static unsigned long compute_dll_image_base (const char *ofile) { unsigned long hash = strhash (ofile); - return 0x60000000 | ((hash << 16) & 0x0FFC0000); + return 0x61300000 + ((hash << 16) & 0x0FFC0000); } #endif @@ -1822,6 +1822,7 @@ struct ld_emulation_xfer_struct ld_${EMU set_output_arch_default, ldemul_default_target, gld_${EMULATION_NAME}_before_allocation, + do_assignments_default, gld_${EMULATION_NAME}_get_script, "${EMULATION_NAME}", "${OUTPUT_FORMAT}", diff -uprN binutils-2.16.91.0.1/ld/emultempl/ppc32elf.em binutils-2.16.91.0.2/ld/emultempl/ppc32elf.em --- binutils-2.16.91.0.1/ld/emultempl/ppc32elf.em 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emultempl/ppc32elf.em 2005-07-20 12:27:28.213041361 -0700 @@ -28,6 +28,15 @@ cat >>e${EMULATION_NAME}.c <creator == &bfd_elf32_powerpc_vec - || link_info.hash->creator == &bfd_elf32_powerpcle_vec) + if (is_ppc_elf32_vec (link_info.hash->creator)) { int new_plt; int keep_new; @@ -95,8 +103,7 @@ ppc_after_open (void) static void ppc_before_allocation (void) { - if (link_info.hash->creator == &bfd_elf32_powerpc_vec - || link_info.hash->creator == &bfd_elf32_powerpcle_vec) + if (is_ppc_elf32_vec (link_info.hash->creator)) { if (ppc_elf_tls_setup (output_bfd, &link_info) && !notlsopt) { @@ -111,15 +118,20 @@ ppc_before_allocation (void) } static void -gld${EMULATION_NAME}_after_allocation (void) +ppc_do_assignments (void) { - if ((link_info.hash->creator == &bfd_elf32_powerpc_vec - || link_info.hash->creator == &bfd_elf32_powerpcle_vec) - && !link_info.relocatable) - { - if (!ppc_elf_set_sdata_syms (output_bfd, &link_info)) - einfo ("%X%P: cannot set sdata syms %E\n"); - } + asection *s; + + if (is_ppc_elf32_vec (link_info.hash->creator)) + ppc_elf_set_sdata_syms (output_bfd, &link_info); + + s = bfd_get_section_by_name (output_bfd, ".sbss"); + _bfd_elf_provide_section_bound_symbols (&link_info, s, + "__sbss_start", "__sbss_end"); + _bfd_elf_provide_section_bound_symbols (&link_info, s, + "___sbss_start", "___sbss_end"); + + gld${EMULATION_NAME}_provide_init_fini_syms (); } EOF @@ -165,4 +177,4 @@ PARSE_AND_LIST_ARGS_CASES=' # LDEMUL_AFTER_OPEN=ppc_after_open LDEMUL_BEFORE_ALLOCATION=ppc_before_allocation -LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation +LDEMUL_DO_ASSIGNMENTS=ppc_do_assignments diff -uprN binutils-2.16.91.0.1/ld/emultempl/ppc64elf.em binutils-2.16.91.0.2/ld/emultempl/ppc64elf.em --- binutils-2.16.91.0.1/ld/emultempl/ppc64elf.em 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emultempl/ppc64elf.em 2005-07-20 12:27:28.215041031 -0700 @@ -379,8 +379,7 @@ ppc_finish (void) } ppc64_elf_restore_symbols (&link_info); - gld${EMULATION_NAME}_strip_empty_sections (); - gld${EMULATION_NAME}_provide_init_fini_syms (); + _bfd_elf_fix_excluded_sec_syms (output_bfd, &link_info); } diff -uprN binutils-2.16.91.0.1/ld/emultempl/sunos.em binutils-2.16.91.0.2/ld/emultempl/sunos.em --- binutils-2.16.91.0.1/ld/emultempl/sunos.em 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emultempl/sunos.em 2005-07-20 12:27:28.216040866 -0700 @@ -1013,6 +1013,7 @@ struct ld_emulation_xfer_struct ld_${EMU set_output_arch_default, ldemul_default_target, gld${EMULATION_NAME}_before_allocation, + do_assignments_default, gld${EMULATION_NAME}_get_script, "${EMULATION_NAME}", "${OUTPUT_FORMAT}", diff -uprN binutils-2.16.91.0.1/ld/emultempl/ticoff.em binutils-2.16.91.0.2/ld/emultempl/ticoff.em --- binutils-2.16.91.0.1/ld/emultempl/ticoff.em 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emultempl/ticoff.em 2005-07-20 12:27:28.216040866 -0700 @@ -162,6 +162,7 @@ struct ld_emulation_xfer_struct ld_${EMU set_output_arch_default, ldemul_default_target, before_allocation_default, + do_assignments_default, gld_${EMULATION_NAME}_get_script, "${EMULATION_NAME}", "${OUTPUT_FORMAT}", diff -uprN binutils-2.16.91.0.1/ld/emultempl/vanilla.em binutils-2.16.91.0.2/ld/emultempl/vanilla.em --- binutils-2.16.91.0.1/ld/emultempl/vanilla.em 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/emultempl/vanilla.em 2005-07-20 12:27:28.217040701 -0700 @@ -65,6 +65,7 @@ struct ld_emulation_xfer_struct ld_vanil vanilla_set_output_arch, ldemul_default_target, before_allocation_default, + do_assignments_default, vanilla_get_script, "vanilla", "a.out-sunos-big", diff -uprN binutils-2.16.91.0.1/ld/ldemul.c binutils-2.16.91.0.2/ld/ldemul.c --- binutils-2.16.91.0.1/ld/ldemul.c 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/ldemul.c 2005-07-20 12:27:28.162049769 -0700 @@ -80,6 +80,12 @@ ldemul_before_allocation (void) } void +ldemul_do_assignments (void) +{ + ld_emulation->do_assignments (); +} + +void ldemul_set_output_arch (void) { ld_emulation->set_output_arch (); @@ -217,6 +223,11 @@ before_allocation_default (void) } void +do_assignments_default (void) +{ +} + +void set_output_arch_default (void) { /* Set the output architecture and machine if possible. */ diff -uprN binutils-2.16.91.0.1/ld/ldemul.h binutils-2.16.91.0.2/ld/ldemul.h --- binutils-2.16.91.0.1/ld/ldemul.h 2005-04-09 12:03:20.000000000 -0700 +++ binutils-2.16.91.0.2/ld/ldemul.h 2005-07-20 12:27:28.165049275 -0700 @@ -1,6 +1,6 @@ /* ld-emul.h - Linker emulation header file Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2001, - 2002, 2003, 2004 + 2002, 2003, 2004, 2005 Free Software Foundation, Inc. This file is part of GLD, the Gnu Linker. @@ -35,6 +35,8 @@ extern void ldemul_after_allocation (void); extern void ldemul_before_allocation (void); +extern void ldemul_do_assignments + (void); extern void ldemul_set_output_arch (void); extern char *ldemul_choose_target @@ -77,6 +79,8 @@ extern void after_allocation_default (void); extern void before_allocation_default (void); +extern void do_assignments_default + (void); extern void set_output_arch_default (void); extern void syslib_default @@ -117,6 +121,9 @@ typedef struct ld_emulation_xfer_struct /* Run before allocating output sections. */ void (*before_allocation) (void); + /* Run to set special symbols at the same time as link script syms. */ + void (*do_assignments) (void); + /* Return the appropriate linker script. */ char * (*get_script) (int *isfile); diff -uprN binutils-2.16.91.0.1/ld/ldlang.c binutils-2.16.91.0.2/ld/ldlang.c --- binutils-2.16.91.0.1/ld/ldlang.c 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/ldlang.c 2005-07-20 12:27:28.178047131 -0700 @@ -1960,11 +1960,8 @@ wild_sort (lang_wild_statement_type *wil looking at the sections for this file. */ if (sec != NULL && sec->spec.sorted != none) - { - if (compare_section (sec->spec.sorted, section, - ls->section) < 0) - break; - } + if (compare_section (sec->spec.sorted, section, ls->section) < 0) + break; } return l; @@ -3052,7 +3049,6 @@ void strip_excluded_output_sections (void) { lang_output_section_statement_type *os; - unsigned int gc_sections; /* Run lang_size_sections (if not already done) to ensure that all symbols defined in the linker script are put in the bfd hash @@ -3065,13 +3061,6 @@ strip_excluded_output_sections (void) lang_reset_memory_regions (); } - /* Now call into bfd_gc_sections to mark all sections defining global - symbols with SEC_KEEP. */ - gc_sections = link_info.gc_sections; - link_info.gc_sections = 0; - bfd_gc_sections (output_bfd, &link_info); - link_info.gc_sections = gc_sections; - for (os = &lang_output_section_statement.head->output_section_statement; os != NULL; os = os->next) @@ -3086,39 +3075,40 @@ strip_excluded_output_sections (void) if (output_section == NULL) continue; - exclude = TRUE; - if (output_section->map_head.s != NULL) + exclude = (output_section->rawsize == 0 + && (output_section->flags & SEC_KEEP) == 0 + && !bfd_section_removed_from_list (output_bfd, + output_section)); + + /* Some sections have not yet been sized, notably .gnu.version, + .dynsym, .dynstr and .hash. These all have SEC_LINKER_CREATED + input sections, so don't drop output sections that have such + input sections unless they are also marked SEC_EXCLUDE. */ + if (exclude && output_section->map_head.s != NULL) { asection *s; - for (s = output_section->map_head.s; s != NULL; - s = s->map_head.s) - if ((s->flags & SEC_EXCLUDE) == 0) + for (s = output_section->map_head.s; s != NULL; s = s->map_head.s) + if ((s->flags & SEC_LINKER_CREATED) != 0 + && (s->flags & SEC_EXCLUDE) == 0) { exclude = FALSE; break; } - - output_section->map_head.link_order = NULL; - output_section->map_tail.link_order = NULL; } - if (exclude - && (output_section->flags & SEC_KEEP) == 0 - && output_section->rawsize == 0 - && !bfd_is_abs_section (output_section)) + /* TODO: Don't just junk map_head.s, turn them into link_orders. */ + output_section->map_head.link_order = NULL; + output_section->map_tail.link_order = NULL; + + if (exclude) { /* We don't set bfd_section to NULL since bfd_section of the removed output section statement may still be used. */ os->ignored = TRUE; output_section->flags |= SEC_EXCLUDE; - - if (!bfd_section_removed_from_list (output_bfd, - output_section)) - { - bfd_section_list_remove (output_bfd, output_section); - output_bfd->section_count--; - } + bfd_section_list_remove (output_bfd, output_section); + output_bfd->section_count--; } } @@ -4595,6 +4585,7 @@ lang_do_assignments (void) { lang_statement_iteration++; lang_do_assignments_1 (statement_list.head, abs_output_section, NULL, 0); + ldemul_do_assignments (); } /* Fix any .startof. or .sizeof. symbols. When the assemblers see the diff -uprN binutils-2.16.91.0.1/ld/ldmain.c binutils-2.16.91.0.2/ld/ldmain.c --- binutils-2.16.91.0.1/ld/ldmain.c 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/ldmain.c 2005-07-20 12:27:28.180046802 -0700 @@ -345,8 +345,8 @@ main (int argc, char **argv) einfo (_("%P%F: -r and -shared may not be used together\n")); } - if (!config.dynamic_link && link_info.shared) - einfo (_("%P%F: -static and -shared may not be used together\n")); + if (!config.dynamic_link && link_info.shared) + einfo (_("%P%F: -static and -shared may not be used together\n")); if (! link_info.shared) { diff -uprN binutils-2.16.91.0.1/ld/Makefile.am binutils-2.16.91.0.2/ld/Makefile.am --- binutils-2.16.91.0.1/ld/Makefile.am 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/Makefile.am 2005-07-20 12:27:28.148052078 -0700 @@ -57,14 +57,8 @@ HOSTING_LIBS = @HOSTING_LIBS@ HOSTING_EMU = -m $(EMUL) # Setup the testing framework, if you have one -EXPECT = `if [ -f $$r/../expect/expect ] ; \ - then echo $$r/../expect/expect ; \ - else echo expect ; fi` - -RUNTEST = `if [ -f $${srcroot}/../dejagnu/runtest ] ; \ - then echo $${srcroot}/../dejagnu/runtest ; \ - else echo runtest ; fi` - +EXPECT = expect +RUNTEST = runtest RUNTESTFLAGS = CC_FOR_TARGET = ` \ @@ -177,6 +171,7 @@ ALL_EMULATIONS = \ eelf32lppc.o \ eelf32lppcnto.o \ eelf32lppcsim.o \ + eelf32m32c.o \ eelf32mcore.o \ eelf32mipswindiss.o \ eelf32ms1.o \ @@ -187,6 +182,7 @@ ALL_EMULATIONS = \ eelf32ppcnto.o \ eelf32ppcsim.o \ eelf32ppcwindiss.o \ + eelf32ppcvxworks.o \ eelf32vax.o \ eelf32xstormy16.o \ eelf32xtensa.o \ @@ -373,7 +369,7 @@ ALL_EMULATIONS = \ evsta.o \ ew65.o \ ez8001.o \ - eelf32frvfd.o \ + eelf32frvfd.o \ ez8002.o ALL_64_EMULATIONS = \ @@ -751,6 +747,9 @@ eelf32ppcnto.c: $(srcdir)/emulparams/elf eelf32ppcwindiss.c: $(srcdir)/emulparams/elf32ppcwindiss.sh \ $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ${GENSCRIPTS} elf32ppcwindiss "$(tdir_elf32ppcwindiss)" +eelf32ppcvxworks.c: $(srcdir)/emulparams/elf32ppcvxworks.sh \ + $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + ${GENSCRIPTS} elf32ppcvxworks "$(tdir_elf32ppcvxworks)" eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \ $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \ $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} @@ -1089,10 +1088,12 @@ emipsbsd.c: $(srcdir)/emulparams/mipsbsd $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/mipsbsd.sc ${GEN_DEPENDS} ${GENSCRIPTS} mipsbsd emipsidt.c: $(srcdir)/emulparams/mipsidt.sh \ - $(srcdir)/emultempl/mipsecoff.em $(srcdir)/scripttempl/mips.sc ${GEN_DEPENDS} + $(srcdir)/emultempl/mipsecoff.em $(srcdir)/emultempl/generic.em \ + $(srcdir)/scripttempl/mips.sc ${GEN_DEPENDS} ${GENSCRIPTS} mipsidt "$(tdir_mipsidt)" emipsidtl.c: $(srcdir)/emulparams/mipsidtl.sh \ - $(srcdir)/emultempl/mipsecoff.em $(srcdir)/scripttempl/mips.sc ${GEN_DEPENDS} + $(srcdir)/emultempl/mipsecoff.em $(srcdir)/emultempl/generic.em \ + $(srcdir)/scripttempl/mips.sc ${GEN_DEPENDS} ${GENSCRIPTS} mipsidtl "$(tdir_mipsidtl)" emipslit.c: $(srcdir)/emulparams/mipslit.sh \ $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/mips.sc ${GEN_DEPENDS} @@ -1533,6 +1534,9 @@ eelf32frvfd.c: $(srcdir)/emulparams/elf3 $(srcdir)/emulparams/elf32frv.sh \ $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ${GENSCRIPTS} elf32frvfd "$(tdir_frv)" +eelf32m32c.c: $(srcdir)/emulparams/elf32m32c.sh \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + ${GENSCRIPTS} elf32m32c "$(tdir_m32c)" eelf32ms1.c: $(srcdir)/emulparams/elf32ms1.sh \ $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ${GENSCRIPTS} elf32ms1 "$(tdir_ms1)" @@ -1558,10 +1562,6 @@ check-DEJAGNU: site.exp r=`pwd`; export r; \ LC_COLLATE=; LC_ALL=; LANG=; export LC_COLLATE LC_ALL LANG; \ EXPECT=$(EXPECT); export EXPECT; \ - if [ -f $(top_builddir)/../expect/expect ]; then \ - TCL_LIBRARY=`cd $(top_srcdir)/../tcl/library && pwd`; \ - export TCL_LIBRARY; \ - fi; \ runtest=$(RUNTEST); \ if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \ $$runtest --tool $(DEJATOOL) --srcdir $${srcroot}/testsuite \ @@ -1765,8 +1765,8 @@ ldctor.o: ldctor.c ../bfd/bfd.h $(INCDIR ldexp.h ldlang.h ldmisc.h ldgram.h ldmain.h ldctor.h ldemul.o: ldemul.c config.h ../bfd/bfd.h $(INCDIR)/ansidecl.h \ $(INCDIR)/symcat.h sysdep.h $(INCDIR)/fopen-same.h \ - ld.h $(INCDIR)/bin-bugs.h ldmisc.h ldexp.h ldlang.h \ - ldfile.h ldemul.h ldmain.h ldemul-list.h + $(INCDIR)/bfdlink.h ld.h $(INCDIR)/bin-bugs.h ldmisc.h \ + ldexp.h ldlang.h ldfile.h ldemul.h ldmain.h ldemul-list.h ldexp.o: ldexp.c ../bfd/bfd.h $(INCDIR)/ansidecl.h \ $(INCDIR)/symcat.h sysdep.h config.h $(INCDIR)/fopen-same.h \ $(INCDIR)/bfdlink.h ld.h $(INCDIR)/bin-bugs.h ldmain.h \ diff -uprN binutils-2.16.91.0.1/ld/Makefile.in binutils-2.16.91.0.2/ld/Makefile.in --- binutils-2.16.91.0.1/ld/Makefile.in 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/Makefile.in 2005-07-20 12:27:28.152051418 -0700 @@ -286,14 +286,8 @@ POD2MAN = pod2man --center="GNU Developm HOSTING_EMU = -m $(EMUL) # Setup the testing framework, if you have one -EXPECT = `if [ -f $$r/../expect/expect ] ; \ - then echo $$r/../expect/expect ; \ - else echo expect ; fi` - -RUNTEST = `if [ -f $${srcroot}/../dejagnu/runtest ] ; \ - then echo $${srcroot}/../dejagnu/runtest ; \ - else echo runtest ; fi` - +EXPECT = expect +RUNTEST = runtest RUNTESTFLAGS = CC_FOR_TARGET = ` \ if [ -f $$r/../gcc/xgcc ] ; then \ @@ -400,6 +394,7 @@ ALL_EMULATIONS = \ eelf32lppc.o \ eelf32lppcnto.o \ eelf32lppcsim.o \ + eelf32m32c.o \ eelf32mcore.o \ eelf32mipswindiss.o \ eelf32ms1.o \ @@ -410,6 +405,7 @@ ALL_EMULATIONS = \ eelf32ppcnto.o \ eelf32ppcsim.o \ eelf32ppcwindiss.o \ + eelf32ppcvxworks.o \ eelf32vax.o \ eelf32xstormy16.o \ eelf32xtensa.o \ @@ -596,7 +592,7 @@ ALL_EMULATIONS = \ evsta.o \ ew65.o \ ez8001.o \ - eelf32frvfd.o \ + eelf32frvfd.o \ ez8002.o ALL_64_EMULATIONS = \ @@ -1555,6 +1551,9 @@ eelf32ppcnto.c: $(srcdir)/emulparams/elf eelf32ppcwindiss.c: $(srcdir)/emulparams/elf32ppcwindiss.sh \ $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ${GENSCRIPTS} elf32ppcwindiss "$(tdir_elf32ppcwindiss)" +eelf32ppcvxworks.c: $(srcdir)/emulparams/elf32ppcvxworks.sh \ + $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + ${GENSCRIPTS} elf32ppcvxworks "$(tdir_elf32ppcvxworks)" eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \ $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \ $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} @@ -1893,10 +1892,12 @@ emipsbsd.c: $(srcdir)/emulparams/mipsbsd $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/mipsbsd.sc ${GEN_DEPENDS} ${GENSCRIPTS} mipsbsd emipsidt.c: $(srcdir)/emulparams/mipsidt.sh \ - $(srcdir)/emultempl/mipsecoff.em $(srcdir)/scripttempl/mips.sc ${GEN_DEPENDS} + $(srcdir)/emultempl/mipsecoff.em $(srcdir)/emultempl/generic.em \ + $(srcdir)/scripttempl/mips.sc ${GEN_DEPENDS} ${GENSCRIPTS} mipsidt "$(tdir_mipsidt)" emipsidtl.c: $(srcdir)/emulparams/mipsidtl.sh \ - $(srcdir)/emultempl/mipsecoff.em $(srcdir)/scripttempl/mips.sc ${GEN_DEPENDS} + $(srcdir)/emultempl/mipsecoff.em $(srcdir)/emultempl/generic.em \ + $(srcdir)/scripttempl/mips.sc ${GEN_DEPENDS} ${GENSCRIPTS} mipsidtl "$(tdir_mipsidtl)" emipslit.c: $(srcdir)/emulparams/mipslit.sh \ $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/mips.sc ${GEN_DEPENDS} @@ -2337,6 +2338,9 @@ eelf32frvfd.c: $(srcdir)/emulparams/elf3 $(srcdir)/emulparams/elf32frv.sh \ $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ${GENSCRIPTS} elf32frvfd "$(tdir_frv)" +eelf32m32c.c: $(srcdir)/emulparams/elf32m32c.sh \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + ${GENSCRIPTS} elf32m32c "$(tdir_m32c)" eelf32ms1.c: $(srcdir)/emulparams/elf32ms1.sh \ $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ${GENSCRIPTS} elf32ms1 "$(tdir_ms1)" @@ -2351,10 +2355,6 @@ check-DEJAGNU: site.exp r=`pwd`; export r; \ LC_COLLATE=; LC_ALL=; LANG=; export LC_COLLATE LC_ALL LANG; \ EXPECT=$(EXPECT); export EXPECT; \ - if [ -f $(top_builddir)/../expect/expect ]; then \ - TCL_LIBRARY=`cd $(top_srcdir)/../tcl/library && pwd`; \ - export TCL_LIBRARY; \ - fi; \ runtest=$(RUNTEST); \ if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \ $$runtest --tool $(DEJATOOL) --srcdir $${srcroot}/testsuite \ @@ -2541,8 +2541,8 @@ ldctor.o: ldctor.c ../bfd/bfd.h $(INCDIR ldexp.h ldlang.h ldmisc.h ldgram.h ldmain.h ldctor.h ldemul.o: ldemul.c config.h ../bfd/bfd.h $(INCDIR)/ansidecl.h \ $(INCDIR)/symcat.h sysdep.h $(INCDIR)/fopen-same.h \ - ld.h $(INCDIR)/bin-bugs.h ldmisc.h ldexp.h ldlang.h \ - ldfile.h ldemul.h ldmain.h ldemul-list.h + $(INCDIR)/bfdlink.h ld.h $(INCDIR)/bin-bugs.h ldmisc.h \ + ldexp.h ldlang.h ldfile.h ldemul.h ldmain.h ldemul-list.h ldexp.o: ldexp.c ../bfd/bfd.h $(INCDIR)/ansidecl.h \ $(INCDIR)/symcat.h sysdep.h config.h $(INCDIR)/fopen-same.h \ $(INCDIR)/bfdlink.h ld.h $(INCDIR)/bin-bugs.h ldmain.h \ diff -uprN binutils-2.16.91.0.1/ld/po/ld.pot binutils-2.16.91.0.2/ld/po/ld.pot --- binutils-2.16.91.0.1/ld/po/ld.pot 2005-04-09 12:03:25.000000000 -0700 +++ binutils-2.16.91.0.2/ld/po/ld.pot 2005-07-20 12:27:28.227039053 -0700 @@ -8,7 +8,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" "Report-Msgid-Bugs-To: \n" -"POT-Creation-Date: 2005-03-03 21:05+1030\n" +"POT-Creation-Date: 2005-07-14 17:39-0500\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -31,11 +31,11 @@ msgstr "" msgid "Errors encountered processing file %s" msgstr "" -#: emultempl/armcoff.em:188 emultempl/pe.em:1455 +#: emultempl/armcoff.em:191 emultempl/pe.em:1458 msgid "%P: warning: '--thumb-entry %s' is overriding '-e %s'\n" msgstr "" -#: emultempl/armcoff.em:193 emultempl/pe.em:1460 +#: emultempl/armcoff.em:196 emultempl/pe.em:1463 msgid "%P: warning: connot find thumb start symbol %s\n" msgstr "" @@ -333,8 +333,8 @@ msgstr "" msgid "Errors encountered processing file %s for interworking" msgstr "" -#: emultempl/pe.em:1340 ldexp.c:570 ldlang.c:2408 ldlang.c:5135 ldlang.c:5166 -#: ldmain.c:1161 +#: emultempl/pe.em:1343 ldexp.c:522 ldlang.c:2811 ldlang.c:5671 ldlang.c:5702 +#: ldmain.c:1163 msgid "%P%F: bfd_link_hash_lookup failed: %E\n" msgstr "" @@ -372,7 +372,7 @@ msgstr "" msgid "%B%F: could not read symbols; %E\n" msgstr "" -#: ldcref.c:363 ldcref.c:482 ldmain.c:1226 ldmain.c:1230 +#: ldcref.c:363 ldcref.c:482 ldmain.c:1228 ldmain.c:1232 msgid "%B%F: could not read symbols: %E\n" msgstr "" @@ -380,7 +380,7 @@ msgstr "" msgid "%P: symbol `%T' missing from main hash table\n" msgstr "" -#: ldcref.c:547 ldcref.c:554 ldmain.c:1273 ldmain.c:1280 +#: ldcref.c:547 ldcref.c:554 ldmain.c:1275 ldmain.c:1282 msgid "%B%F: could not read relocs: %E\n" msgstr "" @@ -415,83 +415,83 @@ msgid "" "\n" msgstr "" -#: ldemul.c:227 +#: ldemul.c:230 #, c-format msgid "%S SYSLIB ignored\n" msgstr "" -#: ldemul.c:233 +#: ldemul.c:236 #, c-format msgid "%S HLL ignored\n" msgstr "" -#: ldemul.c:253 +#: ldemul.c:256 msgid "%P: unrecognised emulation mode: %s\n" msgstr "" -#: ldemul.c:254 +#: ldemul.c:257 msgid "Supported emulations: " msgstr "" -#: ldemul.c:296 +#: ldemul.c:299 #, c-format msgid " no emulation specific options.\n" msgstr "" -#: ldexp.c:379 +#: ldexp.c:338 #, c-format msgid "%F%S %% by zero\n" msgstr "" -#: ldexp.c:386 +#: ldexp.c:346 #, c-format msgid "%F%S / by zero\n" msgstr "" -#: ldexp.c:583 +#: ldexp.c:536 #, c-format msgid "%X%S: unresolvable symbol `%s' referenced in expression\n" msgstr "" -#: ldexp.c:604 +#: ldexp.c:547 #, c-format msgid "%F%S: undefined symbol `%s' referenced in expression\n" msgstr "" -#: ldexp.c:665 ldexp.c:678 +#: ldexp.c:606 ldexp.c:619 #, c-format msgid "%F%S: undefined MEMORY region `%s' referenced in expression\n" msgstr "" -#: ldexp.c:757 +#: ldexp.c:688 #, c-format msgid "%F%S can not PROVIDE assignment to location counter\n" msgstr "" -#: ldexp.c:770 +#: ldexp.c:702 #, c-format msgid "%F%S invalid assignment to location counter\n" msgstr "" -#: ldexp.c:774 +#: ldexp.c:705 #, c-format msgid "%F%S assignment to location counter invalid outside of SECTION\n" msgstr "" -#: ldexp.c:783 +#: ldexp.c:714 msgid "%F%S cannot move location counter backwards (from %V to %V)\n" msgstr "" -#: ldexp.c:810 +#: ldexp.c:753 msgid "%P%F:%s: hash creation failed\n" msgstr "" -#: ldexp.c:1077 ldexp.c:1109 +#: ldexp.c:1004 ldexp.c:1029 #, c-format msgid "%F%S nonconstant expression for %s\n" msgstr "" -#: ldexp.c:1163 +#: ldexp.c:1086 #, c-format msgid "%F%S non constant expression for %s\n" msgstr "" @@ -552,42 +552,42 @@ msgstr "" msgid "%P%F: cannot represent machine `%s'\n" msgstr "" -#: ldlang.c:511 +#: ldlang.c:900 msgid "%P%F: out of memory during initialization" msgstr "" -#: ldlang.c:551 +#: ldlang.c:937 msgid "%P:%S: warning: redeclaration of memory region '%s'\n" msgstr "" -#: ldlang.c:557 +#: ldlang.c:943 msgid "%P:%S: warning: memory region %s not declared\n" msgstr "" -#: ldlang.c:1073 +#: ldlang.c:1464 msgid "" "\n" "Memory Configuration\n" "\n" msgstr "" -#: ldlang.c:1075 +#: ldlang.c:1466 msgid "Name" msgstr "" -#: ldlang.c:1075 +#: ldlang.c:1466 msgid "Origin" msgstr "" -#: ldlang.c:1075 +#: ldlang.c:1466 msgid "Length" msgstr "" -#: ldlang.c:1075 +#: ldlang.c:1466 msgid "Attributes" msgstr "" -#: ldlang.c:1115 +#: ldlang.c:1506 #, c-format msgid "" "\n" @@ -595,468 +595,464 @@ msgid "" "\n" msgstr "" -#: ldlang.c:1183 +#: ldlang.c:1572 msgid "%P%F: Illegal use of `%s' section\n" msgstr "" -#: ldlang.c:1193 +#: ldlang.c:1579 msgid "%P%F: output format %s cannot represent section called %s\n" msgstr "" -#: ldlang.c:1775 +#: ldlang.c:2178 msgid "%B: file not recognized: %E\n" msgstr "" -#: ldlang.c:1776 +#: ldlang.c:2179 msgid "%B: matching formats:" msgstr "" -#: ldlang.c:1783 +#: ldlang.c:2186 msgid "%F%B: file not recognized: %E\n" msgstr "" -#: ldlang.c:1847 +#: ldlang.c:2250 msgid "%F%B: member %B in archive is not an object\n" msgstr "" -#: ldlang.c:1858 ldlang.c:1872 +#: ldlang.c:2261 ldlang.c:2275 msgid "%F%B: could not read symbols: %E\n" msgstr "" -#: ldlang.c:2127 +#: ldlang.c:2530 msgid "" "%P: warning: could not find any targets that match endianness requirement\n" msgstr "" -#: ldlang.c:2141 +#: ldlang.c:2544 msgid "%P%F: target %s not found\n" msgstr "" -#: ldlang.c:2143 +#: ldlang.c:2546 msgid "%P%F: cannot open output file %s: %E\n" msgstr "" -#: ldlang.c:2149 +#: ldlang.c:2552 msgid "%P%F:%s: can not make object file: %E\n" msgstr "" -#: ldlang.c:2153 +#: ldlang.c:2556 msgid "%P%F:%s: can not set architecture: %E\n" msgstr "" -#: ldlang.c:2157 +#: ldlang.c:2560 msgid "%P%F: can not create link hash table: %E\n" msgstr "" -#: ldlang.c:2301 +#: ldlang.c:2704 msgid "%P%F: bfd_hash_lookup failed creating symbol %s\n" msgstr "" -#: ldlang.c:2319 +#: ldlang.c:2722 msgid "%P%F: bfd_hash_allocate failed creating symbol %s\n" msgstr "" -#: ldlang.c:2710 +#: ldlang.c:3155 msgid " load address 0x%V" msgstr "" -#: ldlang.c:2874 +#: ldlang.c:3395 msgid "%W (size before relaxing)\n" msgstr "" -#: ldlang.c:2961 +#: ldlang.c:3482 #, c-format msgid "Address of section %s set to " msgstr "" -#: ldlang.c:3114 +#: ldlang.c:3635 #, c-format msgid "Fail with %d\n" msgstr "" -#: ldlang.c:3351 +#: ldlang.c:3906 msgid "%X%P: section %s [%V -> %V] overlaps section %s [%V -> %V]\n" msgstr "" -#: ldlang.c:3379 +#: ldlang.c:3931 msgid "%X%P: address 0x%v of %B section %s is not within region %s\n" msgstr "" -#: ldlang.c:3388 +#: ldlang.c:3940 msgid "%X%P: region %s is full (%B section %s)\n" msgstr "" -#: ldlang.c:3439 +#: ldlang.c:3991 msgid "%P%X: Internal error on COFF shared library section %s\n" msgstr "" -#: ldlang.c:3493 +#: ldlang.c:4046 msgid "%P%F: error: no memory region specified for loadable section `%s'\n" msgstr "" -#: ldlang.c:3498 +#: ldlang.c:4051 msgid "%P: warning: no memory region specified for loadable section `%s'\n" msgstr "" -#: ldlang.c:3515 -msgid "%P: warning: changing start of section %s by %u bytes\n" +#: ldlang.c:4068 +msgid "%P: warning: changing start of section %s by %lu bytes\n" msgstr "" -#: ldlang.c:3532 +#: ldlang.c:4083 #, c-format msgid "" "%F%S: non constant or forward reference address expression for section %s\n" msgstr "" -#: ldlang.c:3703 +#: ldlang.c:4255 msgid "%P%F: can't relax section: %E\n" msgstr "" -#: ldlang.c:3960 +#: ldlang.c:4503 msgid "%F%P: invalid data statement\n" msgstr "" -#: ldlang.c:3999 +#: ldlang.c:4536 msgid "%F%P: invalid reloc statement\n" msgstr "" -#: ldlang.c:4141 +#: ldlang.c:4669 msgid "%P%F:%s: can't set start address\n" msgstr "" -#: ldlang.c:4154 ldlang.c:4173 +#: ldlang.c:4682 ldlang.c:4701 msgid "%P%F: can't set start address\n" msgstr "" -#: ldlang.c:4166 +#: ldlang.c:4694 msgid "%P: warning: cannot find entry symbol %s; defaulting to %V\n" msgstr "" -#: ldlang.c:4178 +#: ldlang.c:4706 msgid "%P: warning: cannot find entry symbol %s; not setting start address\n" msgstr "" -#: ldlang.c:4227 +#: ldlang.c:4755 msgid "" "%P%F: Relocatable linking with relocations from format %s (%B) to format %s " "(%B) is not supported\n" msgstr "" -#: ldlang.c:4237 +#: ldlang.c:4765 msgid "" "%P: warning: %s architecture of input file `%B' is incompatible with %s " "output\n" msgstr "" -#: ldlang.c:4259 +#: ldlang.c:4787 msgid "%P%X: failed to merge target specific data of file %B\n" msgstr "" -#: ldlang.c:4343 +#: ldlang.c:4871 msgid "" "\n" "Allocating common symbols\n" msgstr "" -#: ldlang.c:4344 +#: ldlang.c:4872 msgid "" "Common symbol size file\n" "\n" msgstr "" -#: ldlang.c:4470 +#: ldlang.c:4998 msgid "%P%F: invalid syntax in flags\n" msgstr "" -#: ldlang.c:4740 +#: ldlang.c:5274 msgid "%P%F: Failed to create hash table\n" msgstr "" -#: ldlang.c:5057 +#: ldlang.c:5593 msgid "%P%Fmultiple STARTUP files\n" msgstr "" -#: ldlang.c:5105 +#: ldlang.c:5641 msgid "%X%P:%S: section has both a load address and a load region\n" msgstr "" -#: ldlang.c:5345 +#: ldlang.c:5878 msgid "%F%P: bfd_record_phdr failed: %E\n" msgstr "" -#: ldlang.c:5365 +#: ldlang.c:5898 msgid "%X%P: section `%s' assigned to non-existent phdr `%s'\n" msgstr "" -#: ldlang.c:5751 +#: ldlang.c:6284 msgid "%X%P: unknown language `%s' in version information\n" msgstr "" -#: ldlang.c:5893 +#: ldlang.c:6426 msgid "" "%X%P: anonymous version tag cannot be combined with other version tags\n" msgstr "" -#: ldlang.c:5902 +#: ldlang.c:6435 msgid "%X%P: duplicate version tag `%s'\n" msgstr "" -#: ldlang.c:5922 ldlang.c:5931 ldlang.c:5948 ldlang.c:5958 +#: ldlang.c:6455 ldlang.c:6464 ldlang.c:6481 ldlang.c:6491 msgid "%X%P: duplicate expression `%s' in version information\n" msgstr "" -#: ldlang.c:5998 +#: ldlang.c:6531 msgid "%X%P: unable to find version dependency `%s'\n" msgstr "" -#: ldlang.c:6020 +#: ldlang.c:6553 msgid "%X%P: unable to read .exports section contents\n" msgstr "" -#: ldmain.c:229 +#: ldmain.c:230 msgid "%X%P: can't set BFD default target to `%s': %E\n" msgstr "" -#: ldmain.c:341 +#: ldmain.c:343 msgid "%P%F: --relax and -r may not be used together\n" msgstr "" -#: ldmain.c:343 +#: ldmain.c:345 msgid "%P%F: -r and -shared may not be used together\n" msgstr "" -#: ldmain.c:347 +#: ldmain.c:349 msgid "%P%F: -static and -shared may not be used together\n" msgstr "" -#: ldmain.c:352 +#: ldmain.c:354 msgid "%P%F: -F may not be used without -shared\n" msgstr "" -#: ldmain.c:354 +#: ldmain.c:356 msgid "%P%F: -f may not be used without -shared\n" msgstr "" -#: ldmain.c:396 +#: ldmain.c:398 msgid "using external linker script:" msgstr "" -#: ldmain.c:398 +#: ldmain.c:400 msgid "using internal linker script:" msgstr "" -#: ldmain.c:432 +#: ldmain.c:434 msgid "%P%F: no input files\n" msgstr "" -#: ldmain.c:436 +#: ldmain.c:438 msgid "%P: mode %s\n" msgstr "" -#: ldmain.c:452 +#: ldmain.c:454 msgid "%P%F: cannot open map file %s: %E\n" msgstr "" -#: ldmain.c:482 +#: ldmain.c:484 msgid "%P: link errors found, deleting executable `%s'\n" msgstr "" -#: ldmain.c:491 +#: ldmain.c:493 msgid "%F%B: final close failed: %E\n" msgstr "" -#: ldmain.c:517 +#: ldmain.c:519 msgid "%X%P: unable to open for source of copy `%s'\n" msgstr "" -#: ldmain.c:520 +#: ldmain.c:522 msgid "%X%P: unable to open for destination of copy `%s'\n" msgstr "" -#: ldmain.c:527 +#: ldmain.c:529 msgid "%P: Error writing file `%s'\n" msgstr "" -#: ldmain.c:532 pe-dll.c:1447 +#: ldmain.c:534 pe-dll.c:1447 #, c-format msgid "%P: Error closing file `%s'\n" msgstr "" -#: ldmain.c:548 +#: ldmain.c:550 #, c-format msgid "%s: total time in link: %ld.%06ld\n" msgstr "" -#: ldmain.c:551 +#: ldmain.c:553 #, c-format msgid "%s: data size %ld\n" msgstr "" -#: ldmain.c:634 +#: ldmain.c:636 msgid "%P%F: missing argument to -m\n" msgstr "" -#: ldmain.c:780 ldmain.c:798 ldmain.c:828 +#: ldmain.c:782 ldmain.c:800 ldmain.c:830 msgid "%P%F: bfd_hash_table_init failed: %E\n" msgstr "" -#: ldmain.c:784 ldmain.c:802 +#: ldmain.c:786 ldmain.c:804 msgid "%P%F: bfd_hash_lookup failed: %E\n" msgstr "" -#: ldmain.c:816 +#: ldmain.c:818 msgid "%X%P: error: duplicate retain-symbols-file\n" msgstr "" -#: ldmain.c:858 +#: ldmain.c:860 msgid "%P%F: bfd_hash_lookup for insertion failed: %E\n" msgstr "" -#: ldmain.c:863 +#: ldmain.c:865 msgid "%P: `-retain-symbols-file' overrides `-s' and `-S'\n" msgstr "" -#: ldmain.c:938 +#: ldmain.c:940 #, c-format msgid "" "Archive member included because of file (symbol)\n" "\n" msgstr "" -#: ldmain.c:1008 +#: ldmain.c:1010 msgid "%X%C: multiple definition of `%T'\n" msgstr "" -#: ldmain.c:1011 +#: ldmain.c:1013 msgid "%D: first defined here\n" msgstr "" -#: ldmain.c:1015 +#: ldmain.c:1017 msgid "%P: Disabling relaxation: it will not work with multiple definitions\n" msgstr "" -#: ldmain.c:1045 +#: ldmain.c:1047 msgid "%B: warning: definition of `%T' overriding common\n" msgstr "" -#: ldmain.c:1048 +#: ldmain.c:1050 msgid "%B: warning: common is here\n" msgstr "" -#: ldmain.c:1055 +#: ldmain.c:1057 msgid "%B: warning: common of `%T' overridden by definition\n" msgstr "" -#: ldmain.c:1058 +#: ldmain.c:1060 msgid "%B: warning: defined here\n" msgstr "" -#: ldmain.c:1065 +#: ldmain.c:1067 msgid "%B: warning: common of `%T' overridden by larger common\n" msgstr "" -#: ldmain.c:1068 +#: ldmain.c:1070 msgid "%B: warning: larger common is here\n" msgstr "" -#: ldmain.c:1072 +#: ldmain.c:1074 msgid "%B: warning: common of `%T' overriding smaller common\n" msgstr "" -#: ldmain.c:1075 +#: ldmain.c:1077 msgid "%B: warning: smaller common is here\n" msgstr "" -#: ldmain.c:1079 +#: ldmain.c:1081 msgid "%B: warning: multiple common of `%T'\n" msgstr "" -#: ldmain.c:1081 +#: ldmain.c:1083 msgid "%B: warning: previous common is here\n" msgstr "" -#: ldmain.c:1101 ldmain.c:1139 +#: ldmain.c:1103 ldmain.c:1141 msgid "%P: warning: global constructor %s used\n" msgstr "" -#: ldmain.c:1149 +#: ldmain.c:1151 msgid "%P%F: BFD backend error: BFD_RELOC_CTOR unsupported\n" msgstr "" #. We found a reloc for the symbol we are looking for. -#: ldmain.c:1203 ldmain.c:1205 ldmain.c:1207 ldmain.c:1245 ldmain.c:1293 +#: ldmain.c:1205 ldmain.c:1207 ldmain.c:1209 ldmain.c:1247 ldmain.c:1295 msgid "warning: " msgstr "" -#: ldmain.c:1327 +#: ldmain.c:1329 msgid "%F%P: bfd_hash_table_init failed: %E\n" msgstr "" -#: ldmain.c:1334 +#: ldmain.c:1336 msgid "%F%P: bfd_hash_lookup failed: %E\n" msgstr "" -#: ldmain.c:1355 +#: ldmain.c:1357 msgid "%X%C: undefined reference to `%T'\n" msgstr "" -#: ldmain.c:1358 +#: ldmain.c:1360 msgid "%C: warning: undefined reference to `%T'\n" msgstr "" -#: ldmain.c:1364 +#: ldmain.c:1366 msgid "%X%D: more undefined references to `%T' follow\n" msgstr "" -#: ldmain.c:1367 +#: ldmain.c:1369 msgid "%D: warning: more undefined references to `%T' follow\n" msgstr "" -#: ldmain.c:1378 +#: ldmain.c:1380 msgid "%X%B: undefined reference to `%T'\n" msgstr "" -#: ldmain.c:1381 +#: ldmain.c:1383 msgid "%B: warning: undefined reference to `%T'\n" msgstr "" -#: ldmain.c:1387 +#: ldmain.c:1389 msgid "%X%B: more undefined references to `%T' follow\n" msgstr "" -#: ldmain.c:1390 +#: ldmain.c:1392 msgid "%B: warning: more undefined references to `%T' follow\n" msgstr "" -#: ldmain.c:1425 ldmain.c:1478 ldmain.c:1496 -msgid "%P%X: generated" -msgstr "" - -#: ldmain.c:1432 +#: ldmain.c:1431 msgid " additional relocation overflows omitted from the output\n" msgstr "" -#: ldmain.c:1445 +#: ldmain.c:1444 msgid " relocation truncated to fit: %s against undefined symbol `%T'" msgstr "" -#: ldmain.c:1450 +#: ldmain.c:1449 msgid "" " relocation truncated to fit: %s against symbol `%T' defined in %A section " "in %B" msgstr "" -#: ldmain.c:1460 +#: ldmain.c:1461 msgid " relocation truncated to fit: %s against `%T'" msgstr "" -#: ldmain.c:1481 +#: ldmain.c:1478 #, c-format -msgid "dangerous relocation: %s\n" +msgid "%X%C: dangerous relocation: %s\n" msgstr "" -#: ldmain.c:1499 -msgid " reloc refers to symbol `%T' which is not being output\n" +#: ldmain.c:1493 +msgid "%X%C: reloc refers to symbol `%T' which is not being output\n" msgstr "" #: ldmisc.c:149 @@ -1069,27 +1065,27 @@ msgstr "" msgid "built in linker script:%u" msgstr "" -#: ldmisc.c:289 ldmisc.c:293 +#: ldmisc.c:296 ldmisc.c:300 msgid "%B%F: could not read symbols\n" msgstr "" -#: ldmisc.c:329 +#: ldmisc.c:342 msgid "%B: In function `%T':\n" msgstr "" -#: ldmisc.c:480 +#: ldmisc.c:493 msgid "%F%P: internal error %s %d\n" msgstr "" -#: ldmisc.c:526 +#: ldmisc.c:539 msgid "%P: internal error: aborting at %s line %d in %s\n" msgstr "" -#: ldmisc.c:529 +#: ldmisc.c:542 msgid "%P: internal error: aborting at %s line %d\n" msgstr "" -#: ldmisc.c:531 +#: ldmisc.c:544 msgid "%P%F: please report this bug\n" msgstr "" @@ -1137,616 +1133,616 @@ msgstr "" msgid "%F%P: final link failed: %E\n" msgstr "" -#: lexsup.c:195 lexsup.c:327 +#: lexsup.c:196 lexsup.c:328 msgid "KEYWORD" msgstr "" -#: lexsup.c:195 +#: lexsup.c:196 msgid "Shared library control for HP/UX compatibility" msgstr "" -#: lexsup.c:198 +#: lexsup.c:199 msgid "ARCH" msgstr "" -#: lexsup.c:198 +#: lexsup.c:199 msgid "Set architecture" msgstr "" -#: lexsup.c:200 lexsup.c:421 +#: lexsup.c:201 lexsup.c:422 msgid "TARGET" msgstr "" -#: lexsup.c:200 +#: lexsup.c:201 msgid "Specify target for following input files" msgstr "" -#: lexsup.c:203 lexsup.c:252 lexsup.c:264 lexsup.c:277 lexsup.c:380 -#: lexsup.c:433 lexsup.c:490 +#: lexsup.c:204 lexsup.c:253 lexsup.c:265 lexsup.c:278 lexsup.c:381 +#: lexsup.c:434 lexsup.c:491 msgid "FILE" msgstr "" -#: lexsup.c:203 +#: lexsup.c:204 msgid "Read MRI format linker script" msgstr "" -#: lexsup.c:205 +#: lexsup.c:206 msgid "Force common symbols to be defined" msgstr "" -#: lexsup.c:209 lexsup.c:475 lexsup.c:477 lexsup.c:479 +#: lexsup.c:210 lexsup.c:476 lexsup.c:478 lexsup.c:480 msgid "ADDRESS" msgstr "" -#: lexsup.c:209 +#: lexsup.c:210 msgid "Set start address" msgstr "" -#: lexsup.c:211 +#: lexsup.c:212 msgid "Export all dynamic symbols" msgstr "" -#: lexsup.c:213 +#: lexsup.c:214 msgid "Link big-endian objects" msgstr "" -#: lexsup.c:215 +#: lexsup.c:216 msgid "Link little-endian objects" msgstr "" -#: lexsup.c:217 lexsup.c:220 +#: lexsup.c:218 lexsup.c:221 msgid "SHLIB" msgstr "" -#: lexsup.c:217 +#: lexsup.c:218 msgid "Auxiliary filter for shared object symbol table" msgstr "" -#: lexsup.c:220 +#: lexsup.c:221 msgid "Filter for shared object symbol table" msgstr "" -#: lexsup.c:223 +#: lexsup.c:224 msgid "Ignored" msgstr "" -#: lexsup.c:225 +#: lexsup.c:226 msgid "SIZE" msgstr "" -#: lexsup.c:225 +#: lexsup.c:226 msgid "Small data size (if no size, same as --shared)" msgstr "" -#: lexsup.c:228 +#: lexsup.c:229 msgid "FILENAME" msgstr "" -#: lexsup.c:228 +#: lexsup.c:229 msgid "Set internal name of shared library" msgstr "" -#: lexsup.c:230 +#: lexsup.c:231 msgid "PROGRAM" msgstr "" -#: lexsup.c:230 +#: lexsup.c:231 msgid "Set PROGRAM as the dynamic linker to use" msgstr "" -#: lexsup.c:233 +#: lexsup.c:234 msgid "LIBNAME" msgstr "" -#: lexsup.c:233 +#: lexsup.c:234 msgid "Search for library LIBNAME" msgstr "" -#: lexsup.c:235 +#: lexsup.c:236 msgid "DIRECTORY" msgstr "" -#: lexsup.c:235 +#: lexsup.c:236 msgid "Add DIRECTORY to library search path" msgstr "" -#: lexsup.c:238 +#: lexsup.c:239 msgid "Override the default sysroot location" msgstr "" -#: lexsup.c:240 +#: lexsup.c:241 msgid "EMULATION" msgstr "" -#: lexsup.c:240 +#: lexsup.c:241 msgid "Set emulation" msgstr "" -#: lexsup.c:242 +#: lexsup.c:243 msgid "Print map file on standard output" msgstr "" -#: lexsup.c:244 +#: lexsup.c:245 msgid "Do not page align data" msgstr "" -#: lexsup.c:246 +#: lexsup.c:247 msgid "Do not page align data, do not make text readonly" msgstr "" -#: lexsup.c:249 +#: lexsup.c:250 msgid "Page align data, make text readonly" msgstr "" -#: lexsup.c:252 +#: lexsup.c:253 msgid "Set output file name" msgstr "" -#: lexsup.c:254 +#: lexsup.c:255 msgid "Optimize output file" msgstr "" -#: lexsup.c:256 +#: lexsup.c:257 msgid "Ignored for SVR4 compatibility" msgstr "" -#: lexsup.c:260 +#: lexsup.c:261 msgid "Generate relocatable output" msgstr "" -#: lexsup.c:264 +#: lexsup.c:265 msgid "Just link symbols (if directory, same as --rpath)" msgstr "" -#: lexsup.c:267 +#: lexsup.c:268 msgid "Strip all symbols" msgstr "" -#: lexsup.c:269 +#: lexsup.c:270 msgid "Strip debugging symbols" msgstr "" -#: lexsup.c:271 +#: lexsup.c:272 msgid "Strip symbols in discarded sections" msgstr "" -#: lexsup.c:273 +#: lexsup.c:274 msgid "Do not strip symbols in discarded sections" msgstr "" -#: lexsup.c:275 +#: lexsup.c:276 msgid "Trace file opens" msgstr "" -#: lexsup.c:277 +#: lexsup.c:278 msgid "Read linker script" msgstr "" -#: lexsup.c:279 lexsup.c:297 lexsup.c:363 lexsup.c:378 lexsup.c:468 -#: lexsup.c:493 lexsup.c:520 +#: lexsup.c:280 lexsup.c:298 lexsup.c:364 lexsup.c:379 lexsup.c:469 +#: lexsup.c:494 lexsup.c:521 msgid "SYMBOL" msgstr "" -#: lexsup.c:279 +#: lexsup.c:280 msgid "Start with undefined reference to SYMBOL" msgstr "" -#: lexsup.c:282 +#: lexsup.c:283 msgid "[=SECTION]" msgstr "" -#: lexsup.c:283 +#: lexsup.c:284 msgid "Don't merge input [SECTION | orphan] sections" msgstr "" -#: lexsup.c:285 +#: lexsup.c:286 msgid "Build global constructor/destructor tables" msgstr "" -#: lexsup.c:287 +#: lexsup.c:288 msgid "Print version information" msgstr "" -#: lexsup.c:289 +#: lexsup.c:290 msgid "Print version and emulation information" msgstr "" -#: lexsup.c:291 +#: lexsup.c:292 msgid "Discard all local symbols" msgstr "" -#: lexsup.c:293 +#: lexsup.c:294 msgid "Discard temporary local symbols (default)" msgstr "" -#: lexsup.c:295 +#: lexsup.c:296 msgid "Don't discard any local symbols" msgstr "" -#: lexsup.c:297 +#: lexsup.c:298 msgid "Trace mentions of SYMBOL" msgstr "" -#: lexsup.c:299 lexsup.c:435 lexsup.c:437 +#: lexsup.c:300 lexsup.c:436 lexsup.c:438 msgid "PATH" msgstr "" -#: lexsup.c:299 +#: lexsup.c:300 msgid "Default search path for Solaris compatibility" msgstr "" -#: lexsup.c:302 +#: lexsup.c:303 msgid "Start a group" msgstr "" -#: lexsup.c:304 +#: lexsup.c:305 msgid "End a group" msgstr "" -#: lexsup.c:308 +#: lexsup.c:309 msgid "Accept input files whose architecture cannot be determined" msgstr "" -#: lexsup.c:312 +#: lexsup.c:313 msgid "Reject input files whose architecture is unknown" msgstr "" -#: lexsup.c:315 +#: lexsup.c:316 msgid "" "Set DT_NEEDED tags for DT_NEEDED entries in\n" "\t\t\t\tfollowing dynamic libs" msgstr "" -#: lexsup.c:318 +#: lexsup.c:319 msgid "" "Do not set DT_NEEDED tags for DT_NEEDED entries\n" "\t\t\t\tin following dynamic libs" msgstr "" -#: lexsup.c:321 +#: lexsup.c:322 msgid "Only set DT_NEEDED for following dynamic libs if used" msgstr "" -#: lexsup.c:324 +#: lexsup.c:325 msgid "Always set DT_NEEDED for following dynamic libs" msgstr "" -#: lexsup.c:327 +#: lexsup.c:328 msgid "Ignored for SunOS compatibility" msgstr "" -#: lexsup.c:329 +#: lexsup.c:330 msgid "Link against shared libraries" msgstr "" -#: lexsup.c:335 +#: lexsup.c:336 msgid "Do not link against shared libraries" msgstr "" -#: lexsup.c:343 +#: lexsup.c:344 msgid "Bind global references locally" msgstr "" -#: lexsup.c:345 +#: lexsup.c:346 msgid "Check section addresses for overlaps (default)" msgstr "" -#: lexsup.c:348 +#: lexsup.c:349 msgid "Do not check section addresses for overlaps" msgstr "" -#: lexsup.c:351 +#: lexsup.c:352 msgid "Output cross reference table" msgstr "" -#: lexsup.c:353 +#: lexsup.c:354 msgid "SYMBOL=EXPRESSION" msgstr "" -#: lexsup.c:353 +#: lexsup.c:354 msgid "Define a symbol" msgstr "" -#: lexsup.c:355 +#: lexsup.c:356 msgid "[=STYLE]" msgstr "" -#: lexsup.c:355 +#: lexsup.c:356 msgid "Demangle symbol names [using STYLE]" msgstr "" -#: lexsup.c:358 +#: lexsup.c:359 msgid "Generate embedded relocs" msgstr "" -#: lexsup.c:360 +#: lexsup.c:361 msgid "Treat warnings as errors" msgstr "" -#: lexsup.c:363 +#: lexsup.c:364 msgid "Call SYMBOL at unload-time" msgstr "" -#: lexsup.c:365 +#: lexsup.c:366 msgid "Force generation of file with .exe suffix" msgstr "" -#: lexsup.c:367 +#: lexsup.c:368 msgid "Remove unused sections (on some targets)" msgstr "" -#: lexsup.c:370 +#: lexsup.c:371 msgid "Don't remove unused sections (default)" msgstr "" -#: lexsup.c:373 +#: lexsup.c:374 msgid "Set default hash table size close to " msgstr "" -#: lexsup.c:376 +#: lexsup.c:377 msgid "Print option help" msgstr "" -#: lexsup.c:378 +#: lexsup.c:379 msgid "Call SYMBOL at load-time" msgstr "" -#: lexsup.c:380 +#: lexsup.c:381 msgid "Write a map file" msgstr "" -#: lexsup.c:382 +#: lexsup.c:383 msgid "Do not define Common storage" msgstr "" -#: lexsup.c:384 +#: lexsup.c:385 msgid "Do not demangle symbol names" msgstr "" -#: lexsup.c:386 +#: lexsup.c:387 msgid "Use less memory and more disk I/O" msgstr "" -#: lexsup.c:388 +#: lexsup.c:389 msgid "Do not allow unresolved references in object files" msgstr "" -#: lexsup.c:391 +#: lexsup.c:392 msgid "Allow unresolved references in shared libaries" msgstr "" -#: lexsup.c:395 +#: lexsup.c:396 msgid "Do not allow unresolved references in shared libs" msgstr "" -#: lexsup.c:399 +#: lexsup.c:400 msgid "Allow multiple definitions" msgstr "" -#: lexsup.c:401 +#: lexsup.c:402 msgid "Disallow undefined version" msgstr "" -#: lexsup.c:403 +#: lexsup.c:404 msgid "Create default symbol version" msgstr "" -#: lexsup.c:406 +#: lexsup.c:407 msgid "Create default symbol version for imported symbols" msgstr "" -#: lexsup.c:409 +#: lexsup.c:410 msgid "Don't warn about mismatched input files" msgstr "" -#: lexsup.c:411 +#: lexsup.c:412 msgid "Turn off --whole-archive" msgstr "" -#: lexsup.c:413 +#: lexsup.c:414 msgid "Create an output file even if errors occur" msgstr "" -#: lexsup.c:418 +#: lexsup.c:419 msgid "" "Only use library directories specified on\n" "\t\t\t\tthe command line" msgstr "" -#: lexsup.c:421 +#: lexsup.c:422 msgid "Specify target of output file" msgstr "" -#: lexsup.c:424 +#: lexsup.c:425 msgid "Ignored for Linux compatibility" msgstr "" -#: lexsup.c:427 +#: lexsup.c:428 msgid "Reduce memory overheads, possibly taking much longer" msgstr "" -#: lexsup.c:430 +#: lexsup.c:431 msgid "Relax branches on certain targets" msgstr "" -#: lexsup.c:433 +#: lexsup.c:434 msgid "Keep only symbols listed in FILE" msgstr "" -#: lexsup.c:435 +#: lexsup.c:436 msgid "Set runtime shared library search path" msgstr "" -#: lexsup.c:437 +#: lexsup.c:438 msgid "Set link time shared library search path" msgstr "" -#: lexsup.c:440 +#: lexsup.c:441 msgid "Create a shared library" msgstr "" -#: lexsup.c:444 +#: lexsup.c:445 msgid "Create a position independent executable" msgstr "" -#: lexsup.c:448 +#: lexsup.c:449 msgid "Sort common symbols by size" msgstr "" -#: lexsup.c:452 +#: lexsup.c:453 msgid "name|alignment" msgstr "" -#: lexsup.c:453 +#: lexsup.c:454 msgid "Sort sections by name or maximum alignment" msgstr "" -#: lexsup.c:455 +#: lexsup.c:456 msgid "COUNT" msgstr "" -#: lexsup.c:455 +#: lexsup.c:456 msgid "How many tags to reserve in .dynamic section" msgstr "" -#: lexsup.c:458 +#: lexsup.c:459 msgid "[=SIZE]" msgstr "" -#: lexsup.c:458 +#: lexsup.c:459 msgid "Split output sections every SIZE octets" msgstr "" -#: lexsup.c:461 +#: lexsup.c:462 msgid "[=COUNT]" msgstr "" -#: lexsup.c:461 +#: lexsup.c:462 msgid "Split output sections every COUNT relocs" msgstr "" -#: lexsup.c:464 +#: lexsup.c:465 msgid "Print memory usage statistics" msgstr "" -#: lexsup.c:466 +#: lexsup.c:467 msgid "Display target specific options" msgstr "" -#: lexsup.c:468 +#: lexsup.c:469 msgid "Do task level linking" msgstr "" -#: lexsup.c:470 +#: lexsup.c:471 msgid "Use same format as native linker" msgstr "" -#: lexsup.c:472 +#: lexsup.c:473 msgid "SECTION=ADDRESS" msgstr "" -#: lexsup.c:472 +#: lexsup.c:473 msgid "Set address of named section" msgstr "" -#: lexsup.c:475 +#: lexsup.c:476 msgid "Set address of .bss section" msgstr "" -#: lexsup.c:477 +#: lexsup.c:478 msgid "Set address of .data section" msgstr "" -#: lexsup.c:479 +#: lexsup.c:480 msgid "Set address of .text section" msgstr "" -#: lexsup.c:482 +#: lexsup.c:483 msgid "" "How to handle unresolved symbols. is:\n" "\t\t\t\tignore-all, report-all, ignore-in-object-files,\n" "\t\t\t\tignore-in-shared-libs" msgstr "" -#: lexsup.c:486 +#: lexsup.c:487 msgid "Output lots of information during link" msgstr "" -#: lexsup.c:490 +#: lexsup.c:491 msgid "Read version information script" msgstr "" -#: lexsup.c:493 +#: lexsup.c:494 msgid "" "Take export symbols list from .exports, using\n" "\t\t\t\tSYMBOL as the version." msgstr "" -#: lexsup.c:496 +#: lexsup.c:497 msgid "Warn about duplicate common symbols" msgstr "" -#: lexsup.c:498 +#: lexsup.c:499 msgid "Warn if global constructors/destructors are seen" msgstr "" -#: lexsup.c:501 +#: lexsup.c:502 msgid "Warn if the multiple GP values are used" msgstr "" -#: lexsup.c:503 +#: lexsup.c:504 msgid "Warn only once per undefined symbol" msgstr "" -#: lexsup.c:505 +#: lexsup.c:506 msgid "Warn if start of section changes due to alignment" msgstr "" -#: lexsup.c:508 +#: lexsup.c:509 msgid "Warn if shared object has DT_TEXTREL" msgstr "" -#: lexsup.c:512 +#: lexsup.c:513 msgid "Report unresolved symbols as warnings" msgstr "" -#: lexsup.c:515 +#: lexsup.c:516 msgid "Report unresolved symbols as errors" msgstr "" -#: lexsup.c:517 +#: lexsup.c:518 msgid "Include all objects from following archives" msgstr "" -#: lexsup.c:520 +#: lexsup.c:521 msgid "Use wrapper functions for SYMBOL" msgstr "" -#: lexsup.c:667 +#: lexsup.c:668 msgid "%P: unrecognized option '%s'\n" msgstr "" -#: lexsup.c:669 +#: lexsup.c:670 msgid "%P%F: use the --help option for usage information\n" msgstr "" -#: lexsup.c:687 +#: lexsup.c:688 msgid "%P%F: unrecognized -a option `%s'\n" msgstr "" -#: lexsup.c:700 +#: lexsup.c:701 msgid "%P%F: unrecognized -assert option `%s'\n" msgstr "" -#: lexsup.c:743 +#: lexsup.c:744 msgid "%F%P: unknown demangling style `%s'" msgstr "" -#: lexsup.c:805 +#: lexsup.c:806 msgid "%P%F: invalid number `%s'\n" msgstr "" -#: lexsup.c:897 +#: lexsup.c:898 msgid "%P%F: bad --unresolved-symbols option: %s\n" msgstr "" @@ -1758,82 +1754,82 @@ msgstr "" #. an error message here. We cannot just make this a warning, #. increment optind, and continue because getopt is too confused #. and will seg-fault the next time around. -#: lexsup.c:968 +#: lexsup.c:969 msgid "%P%F: bad -rpath option\n" msgstr "" -#: lexsup.c:1080 +#: lexsup.c:1081 msgid "%P%F: -shared not supported\n" msgstr "" -#: lexsup.c:1089 +#: lexsup.c:1090 msgid "%P%F: -pie not supported\n" msgstr "" -#: lexsup.c:1099 +#: lexsup.c:1100 msgid "name" msgstr "" -#: lexsup.c:1101 +#: lexsup.c:1102 msgid "alignment" msgstr "" -#: lexsup.c:1104 +#: lexsup.c:1105 msgid "%P%F: invalid section sorting option: %s\n" msgstr "" -#: lexsup.c:1130 +#: lexsup.c:1131 msgid "%P%F: invalid argument to option \"--section-start\"\n" msgstr "" -#: lexsup.c:1137 +#: lexsup.c:1138 msgid "%P%F: missing argument(s) to option \"--section-start\"\n" msgstr "" -#: lexsup.c:1311 +#: lexsup.c:1312 msgid "%P%F: may not nest groups (--help for usage)\n" msgstr "" -#: lexsup.c:1318 +#: lexsup.c:1319 msgid "%P%F: group ended before it began (--help for usage)\n" msgstr "" -#: lexsup.c:1346 +#: lexsup.c:1347 msgid "%P%X: --hash-size needs a numeric argument\n" msgstr "" -#: lexsup.c:1397 lexsup.c:1410 +#: lexsup.c:1398 lexsup.c:1411 msgid "%P%F: invalid hex number `%s'\n" msgstr "" -#: lexsup.c:1445 +#: lexsup.c:1446 #, c-format msgid "Usage: %s [options] file...\n" msgstr "" -#: lexsup.c:1447 +#: lexsup.c:1448 #, c-format msgid "Options:\n" msgstr "" #. Note: Various tools (such as libtool) depend upon the #. format of the listings below - do not change them. -#: lexsup.c:1530 +#: lexsup.c:1531 #, c-format msgid "%s: supported targets:" msgstr "" -#: lexsup.c:1538 +#: lexsup.c:1539 #, c-format msgid "%s: supported emulations: " msgstr "" -#: lexsup.c:1543 +#: lexsup.c:1544 #, c-format msgid "%s: emulation specific options:\n" msgstr "" -#: lexsup.c:1547 +#: lexsup.c:1548 #, c-format msgid "Report bugs to %s\n" msgstr "" diff -uprN binutils-2.16.91.0.1/ld/scripttempl/elf.sc binutils-2.16.91.0.2/ld/scripttempl/elf.sc --- binutils-2.16.91.0.1/ld/scripttempl/elf.sc 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/scripttempl/elf.sc 2005-07-20 12:27:28.228038888 -0700 @@ -329,7 +329,7 @@ cat < + + * ld-i386/abs.s, ld-i386/zero.s, ld-i386/abs.d, ld-x86-64/abs.d, + ld-i386/pcrel16.s, ld-i386/pcrel16.d, ld-x86-64/pcrel16.d, + ld-i386/pcrel8.s, ld-i386/pcrel8.d, ld-x86-64/pcrel8.d: New. + * ld-i386/i386.exp, ld-x86-64/x86-64.exp: Run new tests. + +2005-07-14 H.J. Lu + + * lib/ld-lib.exp (run_ld_link_exec_tests): Ignore assembler + warnings. + +2005-07-14 H.J. Lu + + * lib/ld-lib.exp (run_ld_link_exec_tests): Update comments. + +2005-07-14 H.J. Lu + + * ld-elf/elf.exp (array_tests): New. + Call run_ld_link_exec_tests with array_tests. + + * ld-elf/fini.c: New file. + * ld-elf/fini.out: Likewise. + * ld-elf/init.c: Likewise. + * ld-elf/init.out: Likewise. + * ld-elf/preinit.c: Likewise. + * ld-elf/preinit.out: Likewise. + + * lib/ld-lib.exp (run_ld_link_exec_tests): New. + +2005-07-12 Alan Modra + + * ld-powerpc/sdalib.s (lib_var): Size it. + +2005-07-08 H.J. Lu + + * ld-ia64/tlsbin.rd: Update for empty section removal change. + * ld-ia64/tlsbin.sd: Likewise. + * ld-ia64/tlspic.dd: Likewise. + * ld-ia64/tlspic.rd: Likewise. + * ld-ia64/tlspic.sd: Likewise. + * ld-x86-64/tlspic.dd: Likewise. + * ld-x86-64/tlspic.rd: Likewise. + +2005-07-08 Alan Modra + + * ld-cris/pv32.s: Give expobj a size. + * ld-cris/pv32-1.d: Update. + * ld-alpha/tlsbin.dd: Update for empty section removal change. + * ld-alpha/tlsbin.sd: Likewise. + * ld-alpha/tlsbin.td: Likewise. + * ld-alpha/tlsbinr.dd: Likewise. + * ld-alpha/tlsbinr.rd: Likewise. + * ld-alpha/tlspic.dd: Likewise. + * ld-alpha/tlspic.rd: Likewise. + * ld-alpha/tlspic.sd: Likewise. + * ld-alpha/tlspic.td: Likewise. + * ld-arm/tls-lib.d: Likewise. + * ld-arm/tls-lib.r: Likewise. + * ld-cris/gotplt2.d: Likewise. + * ld-cris/gotplt3.d: Likewise. + * ld-cris/hiddef1.d: Likewise. + * ld-cris/libdso-10.d: Likewise. + * ld-cris/libdso-11.d: Likewise. + * ld-cris/libdso-12.d: Likewise. + * ld-cris/libdso-14.d: Likewise. + * ld-cris/libdso-2.d: Likewise. + * ld-i386/tlsnopic.dd: Likewise. + * ld-i386/tlsnopic.rd: Likewise. + * ld-i386/tlsnopic.sd: Likewise. + * ld-i386/tlspic.rd: Likewise. + * ld-mmix/bpo-10.d: Likewise. + * ld-mmix/bpo-22.d: Likewise. + * ld-mmix/sec-7m.d: Likewise. + * ld-powerpc/tlsexe.r: Likewise. + * ld-powerpc/tlsexetoc.r: Likewise. + * ld-powerpc/tlsso.g: Likewise. + * ld-powerpc/tlsso.r: Likewise. + * ld-powerpc/tlsso32.d: Likewise. + * ld-powerpc/tlsso32.g: Likewise. + * ld-powerpc/tlsso32.r: Likewise. + * ld-powerpc/tlstocso.g: Likewise. + * ld-powerpc/tlstocso.r: Likewise. + +2005-06-23 Andreas Schwab + + * ld-elfweak/size_foo.c (foo): Fix warning about implicit return + type. + 2005-06-10 Alan Modra * ld-cris/libdso-10.d: Adjust for elf.sc .bss change. diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-alpha/tlsbin.dd binutils-2.16.91.0.2/ld/testsuite/ld-alpha/tlsbin.dd --- binutils-2.16.91.0.1/ld/testsuite/ld-alpha/tlsbin.dd 2005-04-09 12:03:25.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-alpha/tlsbin.dd 2005-07-20 12:27:28.241036745 -0700 @@ -12,30 +12,30 @@ Disassembly of section \.text: 0+120001000 : 120001000: 02 00 bb 27 ldah gp,2\(t12\) - 120001004: 00 a0 bd 23 lda gp,-24576\(gp\) + 120001004: c0 82 bd 23 lda gp,-32064\(gp\) 120001008: 3e 15 c2 43 subq sp,0x10,sp 12000100c: 00 00 5e b7 stq ra,0\(sp\) 120001010: 18 80 1d 22 lda a0,-32744\(gp\) 120001014: 08 80 7d a7 ldq t12,-32760\(gp\) 120001018: 00 40 5b 6b jsr ra,\(t12\),12000101c <.*> 12000101c: 02 00 ba 27 ldah gp,2\(ra\) - 120001020: e4 9f bd 23 lda gp,-24604\(gp\) + 120001020: a4 82 bd 23 lda gp,-32092\(gp\) 120001024: 38 80 1d 22 lda a0,-32712\(gp\) 120001028: 08 80 7d a7 ldq t12,-32760\(gp\) 12000102c: 00 40 5b 6b jsr ra,\(t12\),120001030 <.*> 120001030: 02 00 ba 27 ldah gp,2\(ra\) - 120001034: d0 9f bd 23 lda gp,-24624\(gp\) + 120001034: 90 82 bd 23 lda gp,-32112\(gp\) 120001038: 28 80 1d 22 lda a0,-32728\(gp\) 12000103c: 08 80 7d a7 ldq t12,-32760\(gp\) 120001040: 00 40 5b 6b jsr ra,\(t12\),120001044 <.*> 120001044: 02 00 ba 27 ldah gp,2\(ra\) - 120001048: bc 9f bd 23 lda gp,-24644\(gp\) + 120001048: 7c 82 bd 23 lda gp,-32132\(gp\) 12000104c: 21 00 20 20 lda t0,33\(v0\) 120001050: 28 80 1d 22 lda a0,-32728\(gp\) 120001054: 08 80 7d a7 ldq t12,-32760\(gp\) 120001058: 00 40 5b 6b jsr ra,\(t12\),12000105c <.*> 12000105c: 02 00 ba 27 ldah gp,2\(ra\) - 120001060: a4 9f bd 23 lda gp,-24668\(gp\) + 120001060: 64 82 bd 23 lda gp,-32156\(gp\) 120001064: 40 00 20 20 lda t0,64\(v0\) 120001068: 46 00 20 20 lda t0,70\(v0\) 12000106c: 00 00 20 24 ldah t0,0\(v0\) diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-alpha/tlsbinr.dd binutils-2.16.91.0.2/ld/testsuite/ld-alpha/tlsbinr.dd --- binutils-2.16.91.0.1/ld/testsuite/ld-alpha/tlsbinr.dd 2005-04-09 12:03:25.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-alpha/tlsbinr.dd 2005-07-20 12:27:28.248035590 -0700 @@ -12,7 +12,7 @@ Disassembly of section \.text: 0+120001000 : 120001000: 02 00 bb 27 ldah gp,2\(t12\) - 120001004: 00 a0 bd 23 lda gp,-24576\(gp\) + 120001004: 90 82 bd 23 lda gp,-32112\(gp\) 120001008: 3e 15 c2 43 subq sp,0x10,sp 12000100c: 00 00 5e b7 stq ra,0\(sp\) 120001010: 08 80 1d a6 ldq a0,-32760\(gp\) @@ -25,13 +25,13 @@ Disassembly of section \.text: 12000102c: 9e 00 00 00 rduniq 120001030: 00 04 00 42 addq a0,v0,v0 120001034: 00 00 fe 2f unop - 120001038: 00 00 1f 22 lda a0,0 + 120001038: 10 00 1f 22 lda a0,16 12000103c: 00 00 fe 2f unop 120001040: 9e 00 00 00 rduniq 120001044: 00 04 00 42 addq a0,v0,v0 120001048: 00 00 fe 2f unop 12000104c: 21 00 20 20 lda t0,33\(v0\) - 120001050: 00 00 1f 22 lda a0,0 + 120001050: 10 00 1f 22 lda a0,16 120001054: 00 00 fe 2f unop 120001058: 9e 00 00 00 rduniq 12000105c: 00 04 00 42 addq a0,v0,v0 diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-alpha/tlsbinr.rd binutils-2.16.91.0.2/ld/testsuite/ld-alpha/tlsbinr.rd --- binutils-2.16.91.0.1/ld/testsuite/ld-alpha/tlsbinr.rd 2005-04-09 12:03:25.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-alpha/tlsbinr.rd 2005-07-20 12:27:28.249035426 -0700 @@ -11,21 +11,22 @@ There are [0-9]+ section headers, starti Section Headers: +\[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al +\[ 0\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0 - +\[ 1\] .interp +.* - +\[ 2\] .hash +.* - +\[ 3\] .dynsym +.* - +\[ 4\] .dynstr +.* - +\[ 5\] .rela.dyn +.* - +\[ 6\] .text +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ +AX +0 +0 4096 - +\[ 7\] .eh_frame +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00 +A +0 +0 +8 - +\[ 8\] .tdata +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ WAT +0 +0 +4 - +\[ 9\] .tbss +NOBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ WAT +0 +0 +1 - +\[10\] .dynamic +DYNAMIC +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 10 +WA +4 +0 +8 - +\[11\] .plt +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ WAX +0 +0 +8 - +\[12\] .got +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ +WA +0 +0 +8 - +\[13\] .shstrtab +.* - +\[14\] .symtab +.* - +\[15\] .strtab +.* + +\[ 1\] \.interp +.* + +\[ 2\] \.hash +.* + +\[ 3\] \.dynsym +.* + +\[ 4\] \.dynstr +.* + +\[ 5\] \.rela\.dyn +.* + +\[ 6\] \.rela\.plt +.* + +\[ 7\] \.text +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ +AX +0 +0 4096 + +\[ 8\] \.eh_frame +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00 +A +0 +0 +8 + +\[ 9\] \.tdata +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ WAT +0 +0 +4 + +\[10\] \.tbss +NOBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ WAT +0 +0 +1 + +\[11\] \.dynamic +DYNAMIC +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 10 +WA +4 +0 +8 + +\[12\] \.plt +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ WAX +0 +0 +16 + +\[13\] \.got +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ +WA +0 +0 +8 + +\[14\] \.shstrtab +.* + +\[15\] \.symtab +.* + +\[16\] \.strtab +.* #... Elf file type is EXEC \(Executable file\) @@ -61,7 +62,7 @@ Symbol table '.dynsym' contains 10 entri +8: [0-9a-f]+ +0 OBJECT +GLOBAL DEFAULT +ABS _GLOBAL_OFFSET_TABLE_ +9: [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS _end -Symbol table '.symtab' contains 67 entries: +Symbol table '.symtab' contains [0-9]+ entries: +Num: +Value +Size Type +Bind +Vis +Ndx Name +0: [0-9a-f]+ +0 NOTYPE +LOCAL +DEFAULT +UND +1: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +1 @@ -79,54 +80,55 @@ Symbol table '.symtab' contains 67 entri +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +13 +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +14 +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +15 - +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +8 sl1 - +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +8 sl2 - +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +8 sl3 - +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +8 sl4 - +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +8 sl5 - +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +8 sl6 - +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +8 sl7 - +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +8 sl8 - +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 bl1 - +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 bl2 - +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 bl3 - +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 bl4 - +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 bl5 - +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 bl6 - +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 bl7 - +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 bl8 - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg8 - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 bg8 - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 bg6 - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 bg3 + +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +16 + +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl1 + +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl2 + +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl3 + +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl4 + +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl5 + +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl6 + +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl7 + +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl8 + +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl1 + +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl2 + +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl3 + +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl4 + +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl5 + +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl6 + +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl7 + +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl8 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg8 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg8 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg6 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg3 +[0-9]+: [0-9a-f]+ +0 OBJECT +GLOBAL DEFAULT +ABS _DYNAMIC - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg3 - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +8 sh3 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg3 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh3 +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +UND sG2 - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg4 - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg5 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg4 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg5 +[0-9]+: [0-9a-f]+ +0 OBJECT +GLOBAL DEFAULT +ABS _PROCEDURE_LINKAGE_TABLE_ - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 bg5 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg5 +[0-9]+: [0-9a-f]+ +4 FUNC +GLOBAL DEFAULT +UND __tls_get_addr - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +8 sh7 - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +8 sh8 - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg1 - +[0-9]+: [0-9a-f]+ +52 FUNC +GLOBAL DEFAULT +6 _start - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +8 sh4 - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 bg7 - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +8 sh5 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh7 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh8 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg1 + +[0-9]+: [0-9a-f]+ +52 FUNC +GLOBAL DEFAULT +7 _start + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh4 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg7 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh5 +[0-9]+: [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS __bss_start - +[0-9]+: [0-9a-f]+ +136 FUNC +GLOBAL DEFAULT +6 fn2 - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg2 + +[0-9]+: [0-9a-f]+ +136 FUNC +GLOBAL DEFAULT +7 fn2 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg2 +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +UND sG1 - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +8 sh1 - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg6 - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg7 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh1 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg6 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg7 +[0-9]+: [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS _edata +[0-9]+: [0-9a-f]+ +0 OBJECT +GLOBAL DEFAULT +ABS _GLOBAL_OFFSET_TABLE_ +[0-9]+: [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS _end - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +8 sh2 - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +8 sh6 - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 bg2 - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 bg1 - +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 bg4 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh2 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh6 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg2 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg1 + +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg4 diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-alpha/tlsbin.sd binutils-2.16.91.0.2/ld/testsuite/ld-alpha/tlsbin.sd --- binutils-2.16.91.0.1/ld/testsuite/ld-alpha/tlsbin.sd 2005-04-09 12:03:25.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-alpha/tlsbin.sd 2005-07-20 12:27:28.242036580 -0700 @@ -9,7 +9,7 @@ .*: +file format elf64-alpha Contents of section .got: - [0-9a-f]+ 00000000 00000000 c0210120 01000000 .* + [0-9a-f]+ 00000000 00000000 b0120120 01000000 .* [0-9a-f]+ 56000000 00000000 00000000 00000000 .* [0-9a-f]+ 00000000 00000000 01000000 00000000 .* [0-9a-f]+ 00000000 00000000 01000000 00000000 .* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-alpha/tlsbin.td binutils-2.16.91.0.2/ld/testsuite/ld-alpha/tlsbin.td --- binutils-2.16.91.0.1/ld/testsuite/ld-alpha/tlsbin.td 2003-03-19 09:19:17.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-alpha/tlsbin.td 2005-07-20 12:27:28.248035590 -0700 @@ -9,9 +9,9 @@ .*: +file format elf64-alpha Contents of section .tdata: - 1?20012000 11000000 12000000 13000000 14000000 .* - 1?20012010 15000000 16000000 17000000 18000000 .* - 1?20012020 41000000 42000000 43000000 44000000 .* - 1?20012030 45000000 46000000 47000000 48000000 .* - 1?20012040 01010000 02010000 03010000 04010000 .* - 1?20012050 05010000 06010000 07010000 08010000 .* + 1?200110f0 11000000 12000000 13000000 14000000 .* + 1?20011100 15000000 16000000 17000000 18000000 .* + 1?20011110 41000000 42000000 43000000 44000000 .* + 1?20011120 45000000 46000000 47000000 48000000 .* + 1?20011130 01010000 02010000 03010000 04010000 .* + 1?20011140 05010000 06010000 07010000 08010000 .* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-alpha/tlspic.dd binutils-2.16.91.0.2/ld/testsuite/ld-alpha/tlspic.dd --- binutils-2.16.91.0.1/ld/testsuite/ld-alpha/tlspic.dd 2005-04-09 12:03:25.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-alpha/tlspic.dd 2005-07-20 12:27:28.250035261 -0700 @@ -12,7 +12,7 @@ Disassembly of section .text: 0+1000 : 1000: 02 00 bb 27 ldah gp,2\(t12\) - 1004: 00 a0 bd 23 lda gp,-24576\(gp\) + 1004: a0 82 bd 23 lda gp,-32096\(gp\) 1008: 3e 15 c2 43 subq sp,0x10,sp 100c: 00 00 5e b7 stq ra,0\(sp\) 1010: 08 00 3e b5 stq s0,8\(sp\) @@ -22,23 +22,23 @@ Disassembly of section .text: 1020: 00 80 7d a7 ldq t12,-32768\(gp\) 1024: 00 40 5b 6b jsr ra,\(t12\),1028 <.*> 1028: 02 00 ba 27 ldah gp,2\(ra\) - 102c: d8 9f bd 23 lda gp,-24616\(gp\) + 102c: 78 82 bd 23 lda gp,-32136\(gp\) 1030: 30 80 1d 22 lda a0,-32720\(gp\) 1034: 00 80 7d a7 ldq t12,-32768\(gp\) 1038: 00 40 5b 6b jsr ra,\(t12\),103c <.*> 103c: 02 00 ba 27 ldah gp,2\(ra\) - 1040: c4 9f bd 23 lda gp,-24636\(gp\) + 1040: 64 82 bd 23 lda gp,-32156\(gp\) 1044: 40 80 1d 22 lda a0,-32704\(gp\) 1048: 00 80 7d a7 ldq t12,-32768\(gp\) 104c: 00 40 5b 6b jsr ra,\(t12\),1050 <.*> 1050: 02 00 ba 27 ldah gp,2\(ra\) - 1054: b0 9f bd 23 lda gp,-24656\(gp\) + 1054: 50 82 bd 23 lda gp,-32176\(gp\) 1058: 21 00 20 20 lda t0,33\(v0\) 105c: 40 80 1d 22 lda a0,-32704\(gp\) 1060: 00 80 7d a7 ldq t12,-32768\(gp\) 1064: 00 40 5b 6b jsr ra,\(t12\),1068 <.*> 1068: 02 00 ba 27 ldah gp,2\(ra\) - 106c: 98 9f bd 23 lda gp,-24680\(gp\) + 106c: 38 82 bd 23 lda gp,-32200\(gp\) 1070: 40 00 20 20 lda t0,64\(v0\) 1074: 62 00 20 20 lda t0,98\(v0\) 1078: 00 00 20 24 ldah t0,0\(v0\) diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-alpha/tlspic.rd binutils-2.16.91.0.2/ld/testsuite/ld-alpha/tlspic.rd --- binutils-2.16.91.0.1/ld/testsuite/ld-alpha/tlspic.rd 2005-04-09 12:03:25.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-alpha/tlspic.rd 2005-07-20 12:27:28.250035261 -0700 @@ -37,7 +37,7 @@ Program Headers: +LOAD +0x0+ 0x0+ 0x0+ 0x[0-9a-f]+ 0x[0-9a-f]+ R E 0x10000 +LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RWE 0x10000 +DYNAMIC +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RW +0x8 - +TLS +0x0+2000 0x0+12000 0x0+12000 0x0+60 0x0+80 R +0x4 + +TLS +0x0+10e0 0x0+110e0 0x0+110e0 0x0+60 0x0+80 R +0x4 #... Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 7 entries: @@ -61,8 +61,6 @@ Symbol table '.dynsym' contains [0-9]+ e .* [0-9a-f]+ 0 SECTION LOCAL DEFAULT 7 .* [0-9a-f]+ 0 SECTION LOCAL DEFAULT 8 .* [0-9a-f]+ 0 SECTION LOCAL DEFAULT 9 -.* [0-9a-f]+ 0 NOTYPE LOCAL DEFAULT UND -.* [0-9a-f]+ 0 NOTYPE LOCAL DEFAULT UND .* [0-9a-f]+ 0 TLS GLOBAL DEFAULT 8 sg8 .* [0-9a-f]+ 0 OBJECT GLOBAL DEFAULT ABS _DYNAMIC .* [0-9a-f]+ 0 TLS GLOBAL DEFAULT 8 sg3 diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-alpha/tlspic.sd binutils-2.16.91.0.2/ld/testsuite/ld-alpha/tlspic.sd --- binutils-2.16.91.0.1/ld/testsuite/ld-alpha/tlspic.sd 2005-04-09 12:03:25.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-alpha/tlspic.sd 2005-07-20 12:27:28.251035096 -0700 @@ -9,9 +9,9 @@ .*: +file format elf64-alpha Contents of section .got: - 13000 b0210100 00000000 00000000 00000000 .* - 13010 00000000 00000000 71000000 00000000 .* - 13020 00000000 00000000 00000000 00000000 .* - 13030 00000000 00000000 44000000 00000000 .* - 13040 00000000 00000000 00000000 00000000 .* - 13050 00000000 00000000 .* + 112a0 90120100 00000000 00000000 00000000 .* + 112b0 00000000 00000000 71000000 00000000 .* + 112c0 00000000 00000000 00000000 00000000 .* + 112d0 00000000 00000000 44000000 00000000 .* + 112e0 00000000 00000000 00000000 00000000 .* + 112f0 00000000 00000000 .* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-alpha/tlspic.td binutils-2.16.91.0.2/ld/testsuite/ld-alpha/tlspic.td --- binutils-2.16.91.0.1/ld/testsuite/ld-alpha/tlspic.td 2003-03-19 09:19:17.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-alpha/tlspic.td 2005-07-20 12:27:28.262033282 -0700 @@ -9,9 +9,9 @@ .*: +file format elf64-alpha Contents of section .tdata: - 12000 11000000 12000000 13000000 14000000 .* - 12010 15000000 16000000 17000000 18000000 .* - 12020 41000000 42000000 43000000 44000000 .* - 12030 45000000 46000000 47000000 48000000 .* - 12040 01010000 02010000 03010000 04010000 .* - 12050 05010000 06010000 07010000 08010000 .* + 110e0 11000000 12000000 13000000 14000000 .* + 110f0 15000000 16000000 17000000 18000000 .* + 11100 41000000 42000000 43000000 44000000 .* + 11110 45000000 46000000 47000000 48000000 .* + 11120 01010000 02010000 03010000 04010000 .* + 11130 05010000 06010000 07010000 08010000 .* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-arm/tls-lib.d binutils-2.16.91.0.2/ld/testsuite/ld-arm/tls-lib.d --- binutils-2.16.91.0.1/ld/testsuite/ld-arm/tls-lib.d 2005-04-09 12:03:25.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-arm/tls-lib.d 2005-07-20 12:27:28.269032128 -0700 @@ -6,10 +6,10 @@ start address 0x.* Disassembly of section .text: -00000328 : - 328: e1a00000 nop \(mov r0,r0\) - 32c: e1a00000 nop \(mov r0,r0\) - 330: e1a0f00e mov pc, lr - 334: 00008098 muleq r0, r8, r0 - 338: 0000808c andeq r8, r0, ip, lsl #1 - 33c: 00000004 andeq r0, r0, r4 +00000314 : + 314: e1a00000 nop \(mov r0,r0\) + 318: e1a00000 nop \(mov r0,r0\) + 31c: e1a0f00e mov pc, lr + 320: 00008098 muleq r0, r8, r0 + 324: 0000808c andeq r8, r0, ip, lsl #1 + 328: 00000004 andeq r0, r0, r4 diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-arm/tls-lib.r binutils-2.16.91.0.2/ld/testsuite/ld-arm/tls-lib.r --- binutils-2.16.91.0.1/ld/testsuite/ld-arm/tls-lib.r 2005-04-09 12:03:25.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-arm/tls-lib.r 2005-07-20 12:27:28.269032128 -0700 @@ -3,8 +3,8 @@ DYNAMIC RELOCATION RECORDS OFFSET TYPE VALUE -000083c4 R_ARM_TLS_DTPMOD32 \*ABS\* -000083cc R_ARM_TLS_DTPMOD32 lib_gd -000083d0 R_ARM_TLS_DTPOFF32 lib_gd +000083b0 R_ARM_TLS_DTPMOD32 \*ABS\* +000083b8 R_ARM_TLS_DTPMOD32 lib_gd +000083bc R_ARM_TLS_DTPOFF32 lib_gd diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-cris/gotplt2.d binutils-2.16.91.0.2/ld/testsuite/ld-cris/gotplt2.d --- binutils-2.16.91.0.1/ld/testsuite/ld-cris/gotplt2.d 2005-04-09 12:03:26.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-cris/gotplt2.d 2005-07-20 12:27:28.273031469 -0700 @@ -16,22 +16,22 @@ DYNAMIC RELOCATION RECORDS OFFSET TYPE VALUE -00002274 R_CRIS_GLOB_DAT dsofn +0000224c R_CRIS_GLOB_DAT dsofn Contents of section .* #... Contents of section \.rela\.got: - 01cc 74220000 0a0b0000 00000000 .* + 01a4 4c220000 0a090000 00000000 .* Contents of section \.text: - 01d8 5f1d0c00 30096f1d 0c000000 30090000 .* - 01e8 6f0d0c00 0000611a 6f3e88df ffff0000 .* + 01b0 5f1d0c00 30096f1d 0c000000 30090000 .* + 01c0 6f0d0c00 0000611a 6f3e88df ffff0000 .* Contents of section \.dynamic: - 21f8 04000000 94000000 05000000 98010000 .* - 2208 06000000 d8000000 0a000000 33000000 .* - 2218 0b000000 10000000 07000000 cc010000 .* - 2228 08000000 0c000000 09000000 0c000000 .* - 2238 00000000 00000000 00000000 00000000 .* - 2248 00000000 00000000 00000000 00000000 .* - 2258 00000000 00000000 00000000 00000000 .* + 21d0 04000000 94000000 05000000 70010000 .* + 21e0 06000000 d0000000 0a000000 33000000 .* + 21f0 0b000000 10000000 07000000 a4010000 .* + 2200 08000000 0c000000 09000000 0c000000 .* + 2210 00000000 00000000 00000000 00000000 .* + 2220 00000000 00000000 00000000 00000000 .* + 2230 00000000 00000000 00000000 00000000 .* Contents of section \.got: - 2268 f8210000 00000000 00000000 00000000 .* + 2240 d0210000 00000000 00000000 00000000 .* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-cris/gotplt3.d binutils-2.16.91.0.2/ld/testsuite/ld-cris/gotplt3.d --- binutils-2.16.91.0.1/ld/testsuite/ld-cris/gotplt3.d 2005-04-09 12:03:26.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-cris/gotplt3.d 2005-07-20 12:27:28.273031469 -0700 @@ -13,23 +13,23 @@ DYNAMIC RELOCATION RECORDS OFFSET TYPE VALUE -00002278 R_CRIS_GLOB_DAT dsofn +00002250 R_CRIS_GLOB_DAT dsofn Contents of section .* #... Contents of section \.rela\.got: - 01cc 78220000 0a0b0000 00000000 .* + 01a4 50220000 0a090000 00000000 .* Contents of section \.text: - 01d8 5f1d0c00 30096f1d 0c000000 30090000 .* - 01e8 6f0d0c00 0000611a 6f3e84df ffff0000 .* - 01f8 0f050000 .* + 01b0 5f1d0c00 30096f1d 0c000000 30090000 .* + 01c0 6f0d0c00 0000611a 6f3e84df ffff0000 .* + 01d0 0f050000 .* Contents of section \.dynamic: - 21fc 04000000 94000000 05000000 98010000 .* - 220c 06000000 d8000000 0a000000 33000000 .* - 221c 0b000000 10000000 07000000 cc010000 .* - 222c 08000000 0c000000 09000000 0c000000 .* - 223c 00000000 00000000 00000000 00000000 .* - 224c 00000000 00000000 00000000 00000000 .* - 225c 00000000 00000000 00000000 00000000 .* + 21d4 04000000 94000000 05000000 70010000 .* + 21e4 06000000 d0000000 0a000000 33000000 .* + 21f4 0b000000 10000000 07000000 a4010000 .* + 2204 08000000 0c000000 09000000 0c000000 .* + 2214 00000000 00000000 00000000 00000000 .* + 2224 00000000 00000000 00000000 00000000 .* + 2234 00000000 00000000 00000000 00000000 .* Contents of section \.got: - 226c fc210000 00000000 00000000 00000000 .* + 2244 d4210000 00000000 00000000 00000000 .* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-cris/hiddef1.d binutils-2.16.91.0.2/ld/testsuite/ld-cris/hiddef1.d --- binutils-2.16.91.0.1/ld/testsuite/ld-cris/hiddef1.d 2005-04-09 12:03:26.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-cris/hiddef1.d 2005-07-20 12:27:28.274031304 -0700 @@ -22,7 +22,7 @@ Relocation section '\.rela\.dyn' at offs #... [0-9a-f]+ 0+c R_CRIS_RELATIVE [0-9a-f]+ #... -Symbol table '\.dynsym' contains 9 entries: +Symbol table '\.dynsym' contains 7 entries: #... Symbol table '\.symtab' contains 19 entries: #pass diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-cris/libdso-10.d binutils-2.16.91.0.2/ld/testsuite/ld-cris/libdso-10.d --- binutils-2.16.91.0.1/ld/testsuite/ld-cris/libdso-10.d 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-cris/libdso-10.d 2005-07-20 12:27:28.274031304 -0700 @@ -9,29 +9,29 @@ Program Header: LOAD off 0x0+ vaddr 0x0+ paddr 0x0+ align 2\*\*13 - filesz 0x0+188 memsz 0x0+188 flags r-x - LOAD off 0x0+188 vaddr 0x0+2188 paddr 0x0+2188 align 2\*\*13 + filesz 0x0+160 memsz 0x0+160 flags r-x + LOAD off 0x0+160 vaddr 0x0+2160 paddr 0x0+2160 align 2\*\*13 filesz 0x0+64 memsz 0x0+64 flags rw- - DYNAMIC off 0x0+188 vaddr 0x0+2188 paddr 0x0+2188 align 2\*\*2 + DYNAMIC off 0x0+160 vaddr 0x0+2160 paddr 0x0+2160 align 2\*\*2 filesz 0x0+58 memsz 0x0+58 flags rw- Dynamic Section: HASH 0x94 - STRTAB 0x15c - SYMTAB 0xcc + STRTAB 0x134 + SYMTAB 0xc4 STRSZ 0x28 SYMENT 0x10 private flags = 2: \[v32\] Sections: Idx Name Size VMA LMA File off Algn - 0 \.hash 0+38 0+94 0+94 0+94 2\*\*2 + 0 \.hash 0+30 0+94 0+94 0+94 2\*\*2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 1 \.dynsym 0+90 0+cc 0+cc 0+cc 2\*\*2 + 1 \.dynsym 0+70 0+c4 0+c4 0+c4 2\*\*2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 2 \.dynstr 0+28 0+15c 0+15c 0+15c 2\*\*0 + 2 \.dynstr 0+28 0+134 0+134 0+134 2\*\*0 CONTENTS, ALLOC, LOAD, READONLY, DATA - 3 \.text 0+4 0+184 0+184 0+184 2\*\*0 + 3 \.text 0+4 0+15c 0+15c 0+15c 2\*\*0 CONTENTS, ALLOC, LOAD, READONLY, CODE - 4 \.dynamic 0+58 0+2188 0+2188 0+188 2\*\*2 + 4 \.dynamic 0+58 0+2160 0+2160 0+160 2\*\*2 CONTENTS, ALLOC, LOAD, DATA - 5 \.got 0+c 0+21e0 0+21e0 0+1e0 2\*\*2 + 5 \.got 0+c 0+21b8 0+21b8 0+1b8 2\*\*2 CONTENTS, ALLOC, LOAD, DATA diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-cris/libdso-11.d binutils-2.16.91.0.2/ld/testsuite/ld-cris/libdso-11.d --- binutils-2.16.91.0.1/ld/testsuite/ld-cris/libdso-11.d 2005-04-09 12:03:26.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-cris/libdso-11.d 2005-07-20 12:27:28.287029160 -0700 @@ -8,20 +8,20 @@ DYNAMIC SYMBOL TABLE: #... -0+1e4 g DF \.text 0+8 dsofn3 +0+1bc g DF \.text 0+8 dsofn3 #... -0+1e0 g DF \.text 0+ dsofn +0+1b8 g DF \.text 0+ dsofn #... Contents of section \.rela\.plt: - 01a0 70220000 0b090000 00000000 .* + 0178 48220000 0b070000 00000000 .* Contents of section \.plt: - 01ac 84e20401 7e7a3f7a 04f26ffa bf09b005 .* - 01bc 00000000 00000000 00006f0d 0c000000 .* - 01cc 6ffabf09 b0053f7e 00000000 bf0ed4ff .* - 01dc ffffb005 .* + 0184 84e20401 7e7a3f7a 04f26ffa bf09b005 .* + 0194 00000000 00000000 00006f0d 0c000000 .* + 01a4 6ffabf09 b0053f7e 00000000 bf0ed4ff .* + 01b4 ffffb005 .* Contents of section \.text: - 01e0 b0050000 bfbee2ff ffffb005 .* + 01b8 b0050000 bfbee2ff ffffb005 .* Contents of section \.dynamic: #... Contents of section \.got: - 2264 ec210000 00000000 00000000 d2010000 .* + 223c c4210000 00000000 00000000 aa010000 .* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-cris/libdso-12.d binutils-2.16.91.0.2/ld/testsuite/ld-cris/libdso-12.d --- binutils-2.16.91.0.1/ld/testsuite/ld-cris/libdso-12.d 2005-04-09 12:03:26.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-cris/libdso-12.d 2005-07-20 12:27:28.288028996 -0700 @@ -12,40 +12,40 @@ DYNAMIC SYMBOL TABLE: #... -0+282 g DF \.text 0+12 dsofn4 -0+278 g DF \.text 0+2 expfn -0+2340 g DO \.data 0+ expobj +0+26e g DF \.text 0+12 dsofn4 +0+264 g DF \.text 0+2 expfn +0+232c g DO \.data 0+ expobj #... -0+27a g DF \.text 0+8 dsofn3 +0+266 g DF \.text 0+8 dsofn3 #... 0+ D \*UND\* 0+ dsofn #... Contents of section \.rela\.got: - 0204 3c230000 0a070000 00000000 .* + 01f0 28230000 0a060000 00000000 .* Contents of section \.rela\.plt: - 0210 34230000 0b050000 00000000 38230000 .* - 0220 0b0d0000 00000000 .* + 01fc 20230000 0b040000 00000000 24230000 .* + 020c 0b0c0000 00000000 .* Contents of section \.plt: - 0228 84e20401 7e7a3f7a 04f26ffa bf09b005 .* - 0238 00000000 00000000 00006f0d 0c000000 .* - 0248 6ffabf09 b0053f7e 00000000 bf0ed4ff .* - 0258 ffffb005 6f0d1000 00006ffa bf09b005 .* - 0268 3f7e0c00 0000bf0e baffffff b005 .* + 0214 84e20401 7e7a3f7a 04f26ffa bf09b005 .* + 0224 00000000 00000000 00006f0d 0c000000 .* + 0234 6ffabf09 b0053f7e 00000000 bf0ed4ff .* + 0244 ffffb005 6f0d1000 00006ffa bf09b005 .* + 0254 3f7e0c00 0000bf0e baffffff b005 .* Contents of section \.text: - 0276 b005b005 bfbee2ff ffffb005 7f0da620 .* - 0286 00005f0d 1400bfbe b6ffffff b0050000 .* + 0262 b005b005 bfbee2ff ffffb005 7f0da620 .* + 0272 00005f0d 1400bfbe b6ffffff b0050000 .* Contents of section \.dynamic: - 2298 04000000 94000000 05000000 c0010000 .* - 22a8 06000000 e0000000 0a000000 43000000 .* - 22b8 0b000000 10000000 03000000 28230000 .* - 22c8 02000000 18000000 14000000 07000000 .* - 22d8 17000000 10020000 07000000 04020000 .* - 22e8 08000000 0c000000 09000000 0c000000 .* - 22f8 00000000 00000000 00000000 00000000 .* - 2308 00000000 00000000 00000000 00000000 .* - 2318 00000000 00000000 00000000 00000000 .* + 2284 04000000 94000000 05000000 ac010000 .* + 2294 06000000 dc000000 0a000000 43000000 .* + 22a4 0b000000 10000000 03000000 14230000 .* + 22b4 02000000 18000000 14000000 07000000 .* + 22c4 17000000 fc010000 07000000 f0010000 .* + 22d4 08000000 0c000000 09000000 0c000000 .* + 22e4 00000000 00000000 00000000 00000000 .* + 22f4 00000000 00000000 00000000 00000000 .* + 2304 00000000 00000000 00000000 00000000 .* Contents of section \.got: - 2328 98220000 00000000 00000000 4e020000 .* - 2338 68020000 00000000 .* + 2314 84220000 00000000 00000000 3a020000 .* + 2324 54020000 00000000 .* Contents of section \.data: - 2340 00000000 .* + 232c 00000000 .* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-cris/libdso-14.d binutils-2.16.91.0.2/ld/testsuite/ld-cris/libdso-14.d --- binutils-2.16.91.0.1/ld/testsuite/ld-cris/libdso-14.d 2005-04-09 12:03:26.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-cris/libdso-14.d 2005-07-20 12:27:28.288028996 -0700 @@ -7,11 +7,11 @@ # Checking that a bsr to a non-PLT-decorated nonvisible function # doesn't make the DSO textrel. -Dynamic section at offset 0x1b0 contains 6 entries: +Dynamic section at offset 0x188 contains 6 entries: Tag[ ]+Type[ ]+Name/Value 0x0+4 \(HASH\)[ ]+0x94 - 0x0+5 \(STRTAB\)[ ]+0x170 - 0x0+6 \(SYMTAB\)[ ]+0xd0 + 0x0+5 \(STRTAB\)[ ]+0x148 + 0x0+6 \(SYMTAB\)[ ]+0xc8 0x0+a \(STRSZ\)[ ]+47 \(bytes\) 0x0+b \(SYMENT\)[ ]+16 \(bytes\) 0x0+ \(NULL\)[ ]+0x0 diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-cris/libdso-2.d binutils-2.16.91.0.2/ld/testsuite/ld-cris/libdso-2.d --- binutils-2.16.91.0.1/ld/testsuite/ld-cris/libdso-2.d 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-cris/libdso-2.d 2005-07-20 12:27:28.289028831 -0700 @@ -27,16 +27,14 @@ There are 13 section headers.* #... Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 1 entries: #... -0000222c 0000000c R_CRIS_RELATIVE 00000184 +00002200 0000000c R_CRIS_RELATIVE 00000158 #... -Symbol table '\.dynsym' contains 6 entries: +Symbol table '\.dynsym' contains 4 entries: Num: Value Size Type Bind Vis Ndx Name 0: 0+ 0 NOTYPE LOCAL DEFAULT UND 1: [0-9a-f]+ 0 SECTION LOCAL DEFAULT 7 - 2: [0-9a-f]+ 0 NOTYPE LOCAL DEFAULT UND - 3: [0-9a-f]+ 0 NOTYPE LOCAL DEFAULT UND - 4: 0+ 0 OBJECT GLOBAL DEFAULT ABS TST1 - 5: 0+188 0 FUNC GLOBAL DEFAULT 7 export_1@@TST1 + 2: 0+ 0 OBJECT GLOBAL DEFAULT ABS TST1 + 3: 0+15c 0 FUNC GLOBAL DEFAULT 7 export_1@@TST1 Symbol table '\.symtab' contains 21 entries: Num: Value Size Type Bind Vis Ndx Name @@ -53,11 +51,11 @@ Symbol table '\.symtab' contains 21 entr 10: [0-9a-f]+ 0 SECTION LOCAL DEFAULT 10 11: [0-9a-f]+ 0 SECTION LOCAL DEFAULT 11 12: [0-9a-f]+ 0 SECTION LOCAL DEFAULT 12 - 13: 0+2198 0 OBJECT LOCAL DEFAULT ABS _DYNAMIC - 14: 0+2230 0 NOTYPE LOCAL DEFAULT ABS __bss_start - 15: 0+2230 0 NOTYPE LOCAL DEFAULT ABS _edata - 16: 0+2220 0 OBJECT LOCAL HIDDEN ABS _GLOBAL_OFFSET_TABLE_ - 17: 0+2240 0 NOTYPE LOCAL DEFAULT ABS _end - 18: 0+184 0 FUNC LOCAL DEFAULT 7 dsofn + 13: 0+216c 0 OBJECT LOCAL DEFAULT ABS _DYNAMIC + 14: 0+2204 0 NOTYPE LOCAL DEFAULT ABS __bss_start + 15: 0+2204 0 NOTYPE LOCAL DEFAULT ABS _edata + 16: 0+21f4 0 OBJECT LOCAL HIDDEN ABS _GLOBAL_OFFSET_TABLE_ + 17: 0+2220 0 NOTYPE LOCAL DEFAULT ABS _end + 18: 0+158 0 FUNC LOCAL DEFAULT 7 dsofn 19: 0+ 0 OBJECT GLOBAL DEFAULT ABS TST1 - 20: 0+188 0 FUNC GLOBAL DEFAULT 7 export_1 + 20: 0+15c 0 FUNC GLOBAL DEFAULT 7 export_1 diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-cris/pv32-1.d binutils-2.16.91.0.2/ld/testsuite/ld-cris/pv32-1.d --- binutils-2.16.91.0.1/ld/testsuite/ld-cris/pv32-1.d 2005-04-09 12:03:26.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-cris/pv32-1.d 2005-07-20 12:27:28.289028831 -0700 @@ -10,11 +10,11 @@ DYNAMIC SYMBOL TABLE: 0+8228c g DO \*ABS\* 0+ _DYNAMIC 0+8023a DF \*UND\* 0+2 expfn -0+82340 g DO \.bss 0+ expobj +0+82340 g DO \.bss 0+4 expobj 0+82340 g D \*ABS\* 0+ __bss_start 0+80254 DF \*UND\* 0+8 dsofn3 0+82340 g D \*ABS\* 0+ _edata -0+82340 g D \*ABS\* 0+ _end +0+82360 g D \*ABS\* 0+ _end 0+80280 g DF \.text 0+8 dsofn Contents of section \.interp: diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-cris/pv32.s binutils-2.16.91.0.2/ld/testsuite/ld-cris/pv32.s --- binutils-2.16.91.0.1/ld/testsuite/ld-cris/pv32.s 2004-11-22 12:33:33.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-cris/pv32.s 2005-07-20 12:27:28.293028171 -0700 @@ -14,6 +14,8 @@ pfn: .Lfe1: .size pfn,.Lfe1-pfn + .global expobj + .size expobj,4 .global dsofn .type dsofn,@function dsofn: diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-elf/elf.exp binutils-2.16.91.0.2/ld/testsuite/ld-elf/elf.exp --- binutils-2.16.91.0.1/ld/testsuite/ld-elf/elf.exp 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-elf/elf.exp 2005-07-20 12:27:28.293028171 -0700 @@ -28,3 +28,19 @@ foreach t $test_list { verbose [file rootname $t] run_dump_test [file rootname $t] } + +# The following tests require running the executable generated by ld. +if ![isnative] { + return +} + +set array_tests { + {"preinit array" "" "" {preinit.c} "preinit" "preinit.out"} + {"static preinit array" "-static" "" {preinit.c} "preinit" "preinit.out"} + {"init array" "" "" {init.c} "init" "init.out"} + {"static init array" "-static" "" {init.c} "init" "init.out"} + {"fini array" "" "" {fini.c} "fini" "fini.out"} + {"static fini array" "-static" "" {fini.c} "fini" "fini.out"} +} + +run_ld_link_exec_tests $array_tests diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-elf/fini.c binutils-2.16.91.0.2/ld/testsuite/ld-elf/fini.c --- binutils-2.16.91.0.1/ld/testsuite/ld-elf/fini.c 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-elf/fini.c 2005-07-20 12:27:28.293028171 -0700 @@ -0,0 +1,34 @@ +#include + +static void +fini_0 (void) +{ + printf ("fini array 0\n"); +} + +static void +fini_1 (void) +{ + printf ("fini array 1\n"); +} + +static void +fini_2 (void) +{ + printf ("fini array 2\n"); +} + +void (*const fini_array []) (void) + __attribute__ ((section (".fini_array"), + aligned (sizeof (void *)))) = +{ + &fini_0, + &fini_1, + &fini_2 +}; + +int +main (void) +{ + return 0; +} diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-elf/fini.out binutils-2.16.91.0.2/ld/testsuite/ld-elf/fini.out --- binutils-2.16.91.0.1/ld/testsuite/ld-elf/fini.out 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-elf/fini.out 2005-07-20 12:27:28.294028006 -0700 @@ -0,0 +1,3 @@ +fini array 2 +fini array 1 +fini array 0 diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-elf/init.c binutils-2.16.91.0.2/ld/testsuite/ld-elf/init.c --- binutils-2.16.91.0.1/ld/testsuite/ld-elf/init.c 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-elf/init.c 2005-07-20 12:27:28.294028006 -0700 @@ -0,0 +1,34 @@ +#include + +static void +init_0 (void) +{ + printf ("init array 0\n"); +} + +static void +init_1 (void) +{ + printf ("init array 1\n"); +} + +static void +init_2 (void) +{ + printf ("init array 2\n"); +} + +void (*const init_array []) (void) + __attribute__ ((section (".init_array"), + aligned (sizeof (void *)))) = +{ + &init_0, + &init_1, + &init_2 +}; + +int +main (void) +{ + return 0; +} diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-elf/init.out binutils-2.16.91.0.2/ld/testsuite/ld-elf/init.out --- binutils-2.16.91.0.1/ld/testsuite/ld-elf/init.out 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-elf/init.out 2005-07-20 12:27:28.294028006 -0700 @@ -0,0 +1,3 @@ +init array 0 +init array 1 +init array 2 diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-elf/preinit.c binutils-2.16.91.0.2/ld/testsuite/ld-elf/preinit.c --- binutils-2.16.91.0.1/ld/testsuite/ld-elf/preinit.c 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-elf/preinit.c 2005-07-20 12:27:28.294028006 -0700 @@ -0,0 +1,34 @@ +#include + +static void +preinit_0 (void) +{ + printf ("preinit array 0\n"); +} + +static void +preinit_1 (void) +{ + printf ("preinit array 1\n"); +} + +static void +preinit_2 (void) +{ + printf ("preinit array 2\n"); +} + +void (*const preinit_array []) (void) + __attribute__ ((section (".preinit_array"), + aligned (sizeof (void *)))) = +{ + &preinit_0, + &preinit_1, + &preinit_2 +}; + +int +main (void) +{ + return 0; +} diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-elf/preinit.out binutils-2.16.91.0.2/ld/testsuite/ld-elf/preinit.out --- binutils-2.16.91.0.1/ld/testsuite/ld-elf/preinit.out 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-elf/preinit.out 2005-07-20 12:27:28.295027841 -0700 @@ -0,0 +1,3 @@ +preinit array 0 +preinit array 1 +preinit array 2 diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-elfweak/size_foo.c binutils-2.16.91.0.2/ld/testsuite/ld-elfweak/size_foo.c --- binutils-2.16.91.0.1/ld/testsuite/ld-elfweak/size_foo.c 2004-05-27 11:26:05.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-elfweak/size_foo.c 2005-07-20 12:27:28.308025698 -0700 @@ -2,6 +2,7 @@ extern void bar (); +void foo () { bar (); diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-i386/abs.d binutils-2.16.91.0.2/ld/testsuite/ld-i386/abs.d --- binutils-2.16.91.0.1/ld/testsuite/ld-i386/abs.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-i386/abs.d 2005-07-20 12:27:28.309025533 -0700 @@ -0,0 +1,10 @@ +#name: Absolute non-overflowing relocs +#source: abs.s +#source: zero.s +#ld: +#objdump: -rs + +.*: file format .* + +Contents of section \.text: +[ ][0-9a-f]+ c800fff0 c8000110 c9c3.* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-i386/abs.s binutils-2.16.91.0.2/ld/testsuite/ld-i386/abs.s --- binutils-2.16.91.0.1/ld/testsuite/ld-i386/abs.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-i386/abs.s 2005-07-20 12:27:28.309025533 -0700 @@ -0,0 +1,8 @@ + .text + .global _start +_start: + enter $zero + 0xff00, $zero + 0xf0 + enter $zero - 0xff00, $zero - 0xf0 + leave + ret + .p2align 4,0x90 diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-i386/i386.exp binutils-2.16.91.0.2/ld/testsuite/ld-i386/i386.exp --- binutils-2.16.91.0.1/ld/testsuite/ld-i386/i386.exp 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-i386/i386.exp 2005-07-20 12:27:28.317024214 -0700 @@ -64,3 +64,7 @@ set i386tests { } run_ld_link_tests $i386tests + +run_dump_test "abs" +run_dump_test "pcrel8" +run_dump_test "pcrel16" diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-i386/pcrel16.d binutils-2.16.91.0.2/ld/testsuite/ld-i386/pcrel16.d --- binutils-2.16.91.0.1/ld/testsuite/ld-i386/pcrel16.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-i386/pcrel16.d 2005-07-20 12:27:28.317024214 -0700 @@ -0,0 +1,3 @@ +#name: PCREL16 overflow +#ld: +#error: .*relocation truncated to fit: R_386_PC16 .* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-i386/pcrel16.s binutils-2.16.91.0.2/ld/testsuite/ld-i386/pcrel16.s --- binutils-2.16.91.0.1/ld/testsuite/ld-i386/pcrel16.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-i386/pcrel16.s 2005-07-20 12:27:28.317024214 -0700 @@ -0,0 +1,11 @@ + .text + .code16 + .global _start, fwd +_start: + jpo fwd + .rept 2500 + testl $0x12345678, %ss:0x76543210(,%eax,4) + .endr +fwd: + leave + ret diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-i386/pcrel8.d binutils-2.16.91.0.2/ld/testsuite/ld-i386/pcrel8.d --- binutils-2.16.91.0.1/ld/testsuite/ld-i386/pcrel8.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-i386/pcrel8.d 2005-07-20 12:27:28.318024049 -0700 @@ -0,0 +1,3 @@ +#name: PCREL8 overflow +#ld: +#error: .*relocation truncated to fit: R_386_PC8 .* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-i386/pcrel8.s binutils-2.16.91.0.2/ld/testsuite/ld-i386/pcrel8.s --- binutils-2.16.91.0.1/ld/testsuite/ld-i386/pcrel8.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-i386/pcrel8.s 2005-07-20 12:27:28.318024049 -0700 @@ -0,0 +1,11 @@ + .text + .code16 + .global _start, fwd +_start: + jcxz fwd + .rept 10 + testl $0x12345678, %ss:0x76543210(,%eax,4) + .endr +fwd: + leave + ret diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-i386/tlsnopic.dd binutils-2.16.91.0.2/ld/testsuite/ld-i386/tlsnopic.dd --- binutils-2.16.91.0.1/ld/testsuite/ld-i386/tlsnopic.dd 2004-05-27 11:26:05.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-i386/tlsnopic.dd 2005-07-20 12:27:28.323023225 -0700 @@ -16,14 +16,14 @@ Disassembly of section .text: 1003: 65 a1 00 00 00 00[ ]+mov %gs:0x0,%eax 1009: 90[ ]+nop * 100a: 90[ ]+nop * - 100b: 03 05 88 20 00 00[ ]+add 0x2088,%eax + 100b: 03 05 7c 21 00 00[ ]+add 0x217c,%eax # ->R_386_TLS_TPOFF sg1 1011: 90[ ]+nop * 1012: 90[ ]+nop * 1013: 90[ ]+nop * 1014: 90[ ]+nop * # @indntpoff direct %gs access IE against global var - 1015: 8b 15 8c 20 00 00[ ]+mov 0x208c,%edx + 1015: 8b 15 80 21 00 00[ ]+mov 0x2180,%edx # ->R_386_TLS_TPOFF sg2 101b: 90[ ]+nop * 101c: 90[ ]+nop * @@ -36,14 +36,14 @@ Disassembly of section .text: 1024: 65 a1 00 00 00 00[ ]+mov %gs:0x0,%eax 102a: 90[ ]+nop * 102b: 90[ ]+nop * - 102c: 03 05 90 20 00 00[ ]+add 0x2090,%eax + 102c: 03 05 84 21 00 00[ ]+add 0x2184,%eax # ->R_386_TLS_TPOFF [0x14000000] 1032: 90[ ]+nop * 1033: 90[ ]+nop * 1034: 90[ ]+nop * 1035: 90[ ]+nop * # @indntpoff direct %gs access IE against hidden var - 1036: 8b 15 94 20 00 00[ ]+mov 0x2094,%edx + 1036: 8b 15 88 21 00 00[ ]+mov 0x2188,%edx # ->R_386_TLS_TPOFF [0x18000000] 103c: 90[ ]+nop * 103d: 90[ ]+nop * @@ -56,14 +56,14 @@ Disassembly of section .text: 1045: 65 a1 00 00 00 00[ ]+mov %gs:0x0,%eax 104b: 90[ ]+nop * 104c: 90[ ]+nop * - 104d: 03 05 80 20 00 00[ ]+add 0x2080,%eax + 104d: 03 05 74 21 00 00[ ]+add 0x2174,%eax # ->R_386_TLS_TPOFF [0x00000000] 1053: 90[ ]+nop * 1054: 90[ ]+nop * 1055: 90[ ]+nop * 1056: 90[ ]+nop * # @indntpoff direct %gs access IE against local var - 1057: 8b 15 84 20 00 00[ ]+mov 0x2084,%edx + 1057: 8b 15 78 21 00 00[ ]+mov 0x2178,%edx # ->R_386_TLS_TPOFF [0x04000000] 105d: 90[ ]+nop * 105e: 90[ ]+nop * diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-i386/tlsnopic.rd binutils-2.16.91.0.2/ld/testsuite/ld-i386/tlsnopic.rd --- binutils-2.16.91.0.1/ld/testsuite/ld-i386/tlsnopic.rd 2005-04-09 12:03:27.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-i386/tlsnopic.rd 2005-07-20 12:27:28.327022566 -0700 @@ -16,9 +16,9 @@ Section Headers: \[ 4\] \.rel.dyn +.* \[ 5\] \.text +PROGBITS +0+1000 .* \[ 6\] \.tbss +NOBITS +[0-9a-f]+ [0-9a-f]+ 000024 00 WAT 0 0 1 - \[ 7\] \.dynamic +DYNAMIC +0+2000 .* - \[ 8\] \.got +PROGBITS +0+2080 .* - \[ 9\] \.got.plt +PROGBITS +0+2098 .* + \[ 7\] \.dynamic +DYNAMIC +0+20f4 .* + \[ 8\] \.got +PROGBITS +0+2174 .* + \[ 9\] \.got.plt +PROGBITS +0+218c .* \[10\] \.shstrtab +.* \[11\] \.symtab +.* \[12\] \.strtab +.* @@ -47,36 +47,33 @@ Program Headers: Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 20 entries: Offset +Info +Type +Sym.Value +Sym. Name -0+100d 0+8 R_386_RELATIVE + -0+1017 0+8 R_386_RELATIVE + -0+102e 0+8 R_386_RELATIVE + -0+1038 0+8 R_386_RELATIVE + -0+104f 0+8 R_386_RELATIVE + -0+1059 0+8 R_386_RELATIVE + -0+1067 0+725 R_386_TLS_TPOFF32 0+ sg3 -0+107c 0+25 R_386_TLS_TPOFF32 -0+10a4 0+e R_386_TLS_TPOFF + -0+10c4 0+e R_386_TLS_TPOFF + -0+10d9 0+e R_386_TLS_TPOFF + -0+10e4 0+e R_386_TLS_TPOFF + -0+2080 0+e R_386_TLS_TPOFF + -0+2084 0+e R_386_TLS_TPOFF + -0+2090 0+e R_386_TLS_TPOFF + -0+2094 0+e R_386_TLS_TPOFF + -0+109b 0+80e R_386_TLS_TPOFF 0+ sg4 -0+10ce 0+a0e R_386_TLS_TPOFF 0+ sg5 -0+2088 0+b0e R_386_TLS_TPOFF 0+ sg1 -0+208c 0+d0e R_386_TLS_TPOFF 0+ sg2 +[0-9a-f ]+R_386_RELATIVE + +[0-9a-f ]+R_386_RELATIVE + +[0-9a-f ]+R_386_RELATIVE + +[0-9a-f ]+R_386_RELATIVE + +[0-9a-f ]+R_386_RELATIVE + +[0-9a-f ]+R_386_RELATIVE + +[0-9a-f ]+R_386_TLS_TPOFF32 0+ sg3 +[0-9a-f ]+R_386_TLS_TPOFF32 +[0-9a-f ]+R_386_TLS_TPOFF + +[0-9a-f ]+R_386_TLS_TPOFF + +[0-9a-f ]+R_386_TLS_TPOFF + +[0-9a-f ]+R_386_TLS_TPOFF + +[0-9a-f ]+R_386_TLS_TPOFF + +[0-9a-f ]+R_386_TLS_TPOFF + +[0-9a-f ]+R_386_TLS_TPOFF + +[0-9a-f ]+R_386_TLS_TPOFF + +[0-9a-f ]+R_386_TLS_TPOFF 0+ sg4 +[0-9a-f ]+R_386_TLS_TPOFF 0+ sg5 +[0-9a-f ]+R_386_TLS_TPOFF 0+ sg1 +[0-9a-f ]+R_386_TLS_TPOFF 0+ sg2 -Symbol table '.dynsym' contains 16 entries: +Symbol table '.dynsym' contains 13 entries: +Num: +Value Size Type +Bind +Vis +Ndx Name +[0-9]+: 0+ +0 NOTYPE LOCAL DEFAULT UND * +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL DEFAULT +5 * +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL DEFAULT +6 * - +[0-9]+: 0+ +0 NOTYPE LOCAL DEFAULT UND * - +[0-9]+: 0+ +0 NOTYPE LOCAL DEFAULT UND * - +[0-9]+: 0+ +0 NOTYPE LOCAL DEFAULT UND * +[0-9]+: [0-9a-f]+ +0 OBJECT GLOBAL DEFAULT ABS _DYNAMIC +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT UND sg3 +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT UND sg4 @@ -111,7 +108,7 @@ Symbol table '.symtab' contains 33 entri +[0-9]+: 0+1c +0 TLS +LOCAL HIDDEN +6 sh3 +[0-9]+: 0+20 +0 TLS +LOCAL HIDDEN +6 sh4 +[0-9]+: 0+14 +0 TLS +LOCAL HIDDEN +6 sh1 - +[0-9]+: 0+2098 +0 OBJECT LOCAL HIDDEN ABS _GLOBAL_OFFSET_TABLE_ + +[0-9]+: 0+218c +0 OBJECT LOCAL HIDDEN ABS _GLOBAL_OFFSET_TABLE_ +[0-9]+: 0+18 +0 TLS +LOCAL HIDDEN +6 sh2 +[0-9]+: [0-9a-f]+ +0 OBJECT GLOBAL DEFAULT ABS _DYNAMIC +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT UND sg3 diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-i386/tlsnopic.sd binutils-2.16.91.0.2/ld/testsuite/ld-i386/tlsnopic.sd --- binutils-2.16.91.0.1/ld/testsuite/ld-i386/tlsnopic.sd 2004-05-27 11:26:05.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-i386/tlsnopic.sd 2005-07-20 12:27:28.328022401 -0700 @@ -8,5 +8,5 @@ .*: file format elf32-i386 Contents of section \.got: - 2080 00000000 04000000 00000000 00000000 .* - 2090 14000000 18000000 +.* + 2174 00000000 04000000 00000000 00000000 .* + 2184 14000000 18000000 +.* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-i386/tlspic.rd binutils-2.16.91.0.2/ld/testsuite/ld-i386/tlspic.rd --- binutils-2.16.91.0.1/ld/testsuite/ld-i386/tlspic.rd 2005-04-09 12:03:27.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-i386/tlspic.rd 2005-07-20 12:27:28.342020092 -0700 @@ -50,45 +50,43 @@ Program Headers: Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 26 entries: Offset +Info +Type +Sym.Value +Sym. Name -[0-9a-f]+ +0+23 R_386_TLS_DTPMOD3 -[0-9a-f]+ +0+25 R_386_TLS_TPOFF32 -[0-9a-f]+ +0+0e R_386_TLS_TPOFF * -[0-9a-f]+ +0+25 R_386_TLS_TPOFF32 -[0-9a-f]+ +0+0e R_386_TLS_TPOFF * -[0-9a-f]+ +0+0e R_386_TLS_TPOFF * -[0-9a-f]+ +0+23 R_386_TLS_DTPMOD3 -[0-9a-f]+ +0+23 R_386_TLS_DTPMOD3 -[0-9a-f]+ +0+0e R_386_TLS_TPOFF * -[0-9a-f]+ +0+25 R_386_TLS_TPOFF32 -[0-9a-f]+ +0+25 R_386_TLS_TPOFF32 -[0-9a-f]+ +0+0e R_386_TLS_TPOFF * -[0-9a-f]+ +0+25 R_386_TLS_TPOFF32 -[0-9a-f]+ +0+0e R_386_TLS_TPOFF * -[0-9a-f]+ +0+0e R_386_TLS_TPOFF * -[0-9a-f]+ +0+0e R_386_TLS_TPOFF * -[0-9a-f]+ +0+0e R_386_TLS_TPOFF * -[0-9a-f]+ +0+23 R_386_TLS_DTPMOD3 -[0-9a-f]+ +0+25 R_386_TLS_TPOFF32 -[0-9a-f]+ +0+80e R_386_TLS_TPOFF 0+8 sg3 -[0-9a-f]+ +0+925 R_386_TLS_TPOFF32 0+c sg4 -[0-9a-f]+ +0+90e R_386_TLS_TPOFF 0+c sg4 -[0-9a-f]+ +0+a0e R_386_TLS_TPOFF 0+10 sg5 -[0-9a-f]+ +0+b23 R_386_TLS_DTPMOD3 0+ sg1 -[0-9a-f]+ +0+b24 R_386_TLS_DTPOFF3 0+ sg1 -[0-9a-f]+ +0+e25 R_386_TLS_TPOFF32 0+4 sg2 +[0-9a-f ]+R_386_TLS_DTPMOD3 +[0-9a-f ]+R_386_TLS_TPOFF32 +[0-9a-f ]+R_386_TLS_TPOFF * +[0-9a-f ]+R_386_TLS_TPOFF32 +[0-9a-f ]+R_386_TLS_TPOFF * +[0-9a-f ]+R_386_TLS_TPOFF * +[0-9a-f ]+R_386_TLS_DTPMOD3 +[0-9a-f ]+R_386_TLS_DTPMOD3 +[0-9a-f ]+R_386_TLS_TPOFF * +[0-9a-f ]+R_386_TLS_TPOFF32 +[0-9a-f ]+R_386_TLS_TPOFF32 +[0-9a-f ]+R_386_TLS_TPOFF * +[0-9a-f ]+R_386_TLS_TPOFF32 +[0-9a-f ]+R_386_TLS_TPOFF * +[0-9a-f ]+R_386_TLS_TPOFF * +[0-9a-f ]+R_386_TLS_TPOFF * +[0-9a-f ]+R_386_TLS_TPOFF * +[0-9a-f ]+R_386_TLS_DTPMOD3 +[0-9a-f ]+R_386_TLS_TPOFF32 +[0-9a-f ]+R_386_TLS_TPOFF 0+8 sg3 +[0-9a-f ]+R_386_TLS_TPOFF32 0+c sg4 +[0-9a-f ]+R_386_TLS_TPOFF 0+c sg4 +[0-9a-f ]+R_386_TLS_TPOFF 0+10 sg5 +[0-9a-f ]+R_386_TLS_DTPMOD3 0+ sg1 +[0-9a-f ]+R_386_TLS_DTPOFF3 0+ sg1 +[0-9a-f ]+R_386_TLS_TPOFF32 0+4 sg2 Relocation section '.rel.plt' at offset 0x[0-9a-f]+ contains 1 entries: - Offset Info Type Sym.Value Sym. Name -[0-9a-f]+ 0+1307 R_386_JUMP_SLOT 0+ ___tls_get_addr + Offset +Info +Type +Sym.Value +Sym. Name +[0-9a-f ]+R_386_JUMP_SLOT 0+ ___tls_get_addr -Symbol table '.dynsym' contains 20 entries: - +Num: + Value Size Type + Bind +Vis +Ndx Name +Symbol table '.dynsym' contains 18 entries: + +Num: +Value Size Type +Bind +Vis +Ndx Name +[0-9]+: 0+ +0 NOTYPE LOCAL DEFAULT UND * +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL DEFAULT +7 * +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL DEFAULT +8 * +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL DEFAULT +9 * - +[0-9]+: 0+ +0 NOTYPE LOCAL DEFAULT UND * - +[0-9]+: 0+ +0 NOTYPE LOCAL DEFAULT UND * +[0-9]+: 0+1c +0 TLS +GLOBAL DEFAULT +8 sg8 +[0-9]+: [0-9a-f]+ +0 OBJECT GLOBAL DEFAULT ABS _DYNAMIC +[0-9]+: 0+8 +0 TLS +GLOBAL DEFAULT +8 sg3 diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-i386/zero.s binutils-2.16.91.0.2/ld/testsuite/ld-i386/zero.s --- binutils-2.16.91.0.1/ld/testsuite/ld-i386/zero.s 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-i386/zero.s 2005-07-20 12:27:28.342020092 -0700 @@ -0,0 +1,2 @@ + .global zero + .equiv zero, 0 diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-ia64/tlsbin.rd binutils-2.16.91.0.2/ld/testsuite/ld-ia64/tlsbin.rd --- binutils-2.16.91.0.1/ld/testsuite/ld-ia64/tlsbin.rd 2005-04-09 12:03:27.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-ia64/tlsbin.rd 2005-07-20 12:27:28.343019928 -0700 @@ -23,7 +23,7 @@ Section Headers: \[11\] .tdata +PROGBITS +60+1[0-9a-f]+ 0+1[0-9a-f]+ 0+60 00 WAT +0 +0 +4 \[12\] .tbss +NOBITS +60+1[0-9a-f]+ 0+1[0-9a-f]+ 0+40 00 WAT +0 +0 +1 \[13\] .dynamic +DYNAMIC +60+1[0-9a-f]+ 0+1[0-9a-f]+ 0+150 10 +WA +4 +0 +8 - \[14\] .got +PROGBITS +60+2000 0+2000 0+48 00 WAp +0 +0 +8 + \[14\] .got +PROGBITS +60+1318 0+1318 0+48 00 WAp +0 +0 +8 \[15\] .IA_64.pltoff +.* \[16\] .shstrtab +.* \[17\] .symtab +.* @@ -48,13 +48,13 @@ Program Headers: Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 3 entries: +Offset +Info +Type +Symbol's Value Symbol's Name \+ Addend -60+2018 0+200000097 R_IA64_TPREL64LSB +0+ sG2 \+ 0 -60+2020 0+5000000a7 R_IA64_DTPMOD64LSB +0+ sG1 \+ 0 -60+2028 0+5000000b7 R_IA64_DTPREL64LSB +0+ sG1 \+ 0 +60+1330 0+200000097 R_IA64_TPREL64LSB +0+ sG2 \+ 0 +60+1338 0+5000000a7 R_IA64_DTPMOD64LSB +0+ sG1 \+ 0 +60+1340 0+5000000b7 R_IA64_DTPREL64LSB +0+ sG1 \+ 0 Relocation section '.rela.IA_64.pltoff' at offset 0x[0-9a-f]+ contains 1 entries: +Offset +Info +Type +Symbol's Value Symbol's Name \+ Addend -60+2050 0+300000081 R_IA64_IPLTLSB +0+ __tls_get_addr \+ 0 +60+1360 0+300000081 R_IA64_IPLTLSB +0+ __tls_get_addr \+ 0 Symbol table '.dynsym' contains 8 entries: +Num: +Value +Size Type +Bind +Vis +Ndx Name diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-ia64/tlsbin.sd binutils-2.16.91.0.2/ld/testsuite/ld-ia64/tlsbin.sd --- binutils-2.16.91.0.1/ld/testsuite/ld-ia64/tlsbin.sd 2004-05-27 11:26:05.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-ia64/tlsbin.sd 2005-07-20 12:27:28.348019103 -0700 @@ -8,8 +8,8 @@ .*: +file format elf..-ia64-.* Contents of section .got: - (60+)?2000 0+ 0+ 0+ 0+ .* - (60+)?2010 0+ 0+ 0+ 0+ .* - (60+)?2020 0+ 0+ 0+ 0+ .* - (60+)?2030 01000000 0+ 90000000 0+ .* - (60+)?2040 24000000 0+ .* + (60+)?1318 0+ 0+ 0+ 0+ .* + (60+)?1328 0+ 0+ 0+ 0+ .* + (60+)?1338 0+ 0+ 0+ 0+ .* + (60+)?1348 01000000 0+ 90000000 0+ .* + (60+)?1358 24000000 0+ .* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-ia64/tlspic.dd binutils-2.16.91.0.2/ld/testsuite/ld-ia64/tlspic.dd --- binutils-2.16.91.0.1/ld/testsuite/ld-ia64/tlspic.dd 2004-11-22 12:33:33.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-ia64/tlspic.dd 2005-07-20 12:27:28.352018444 -0700 @@ -18,25 +18,25 @@ Disassembly of section .text: +101c: 01 0a 00 90[ ]+addl r15=32,r1;; +1020: 19 18 01 1c 18 10[ ]+\[MMB\] +ld8 r35=\[r14\] +1026: 40 02 3c 30 20 00[ ]+ld8 r36=\[r15\] - +102c: 68 f5 ff 58[ ]+br.call.sptk.many b0=[0-9a-f]+ <.*>;; + +102c: 28 f5 ff 58[ ]+br.call.sptk.many b0=[0-9a-f]+ <.*>;; +1030: 0d 70 c0 02 00 24[ ]+\[MFI\] +addl r14=48,r1 +1036: 00 00 00 02 00 e0[ ]+nop.f 0x0 +103c: 01 0c 00 90[ ]+addl r15=64,r1;; +1040: 19 18 01 1c 18 10[ ]+\[MMB\] +ld8 r35=\[r14\] +1046: 40 02 3c 30 20 00[ ]+ld8 r36=\[r15\] - +104c: 48 f5 ff 58[ ]+br.call.sptk.many b0=[0-9a-f]+ <.*>;; + +104c: 08 f5 ff 58[ ]+br.call.sptk.many b0=[0-9a-f]+ <.*>;; +1050: 0d 70 c0 02 00 24[ ]+\[MFI\] +addl r14=48,r1 +1056: 00 00 00 02 00 80[ ]+nop.f 0x0 +105c: 14 02 00 90[ ]+mov r36=33;; +1060: 1d 18 01 1c 18 10[ ]+\[MFB\] +ld8 r35=\[r14\] +1066: 00 00 00 02 00 00[ ]+nop.f 0x0 - +106c: 28 f5 ff 58[ ]+br.call.sptk.many b0=[0-9a-f]+ <.*>;; + +106c: e8 f4 ff 58[ ]+br.call.sptk.many b0=[0-9a-f]+ <.*>;; +1070: 0d 70 c0 02 00 24[ ]+\[MFI\] +addl r14=48,r1 +1076: 00 00 00 02 00 80[ ]+nop.f 0x0 +107c: 04 00 00 84[ ]+mov r36=r0;; +1080: 1d 18 01 1c 18 10[ ]+\[MFB\] +ld8 r35=\[r14\] +1086: 00 00 00 02 00 00[ ]+nop.f 0x0 - +108c: 08 f5 ff 58[ ]+br.call.sptk.many b0=[0-9a-f]+ <.*>;; + +108c: c8 f4 ff 58[ ]+br.call.sptk.many b0=[0-9a-f]+ <.*>;; +1090: 0b 10 00 10 00 21[ ]+\[MMI\] +mov r2=r8;; +1096: e0 00 0a 00 48 e0[ ]+addl r14=64,r2 +109c: 21 16 00 90[ ]+addl r15=98,r2;; diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-ia64/tlspic.rd binutils-2.16.91.0.2/ld/testsuite/ld-ia64/tlspic.rd --- binutils-2.16.91.0.1/ld/testsuite/ld-ia64/tlspic.rd 2005-04-09 12:03:27.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-ia64/tlspic.rd 2005-07-20 12:27:28.353018279 -0700 @@ -22,7 +22,7 @@ Section Headers: \[10\] .tdata +PROGBITS +0+11[0-9a-f]+ 0+1[0-9a-f]+ 0+60 00 WAT +0 +0 +4 \[11\] .tbss +NOBITS +0+11[0-9a-f]+ 0+1[0-9a-f]+ 0+20 00 WAT +0 +0 +1 \[12\] .dynamic +DYNAMIC +0+11[0-9a-f]+ 0+1[0-9a-f]+ 0+140 10 +WA +3 +0 +8 - \[13\] .got +PROGBITS +0+12000 0+2000 0+50 00 WAp +0 +0 +8 + \[13\] .got +PROGBITS +0+112d8 0+12d8 0+50 00 WAp +0 +0 +8 \[14\] .IA_64.pltoff +.* \[15\] .shstrtab +.* \[16\] .symtab +.* @@ -45,18 +45,18 @@ Program Headers: Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 6 entries: +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend -0+12018 +0+f000000a7 R_IA64_DTPMOD64LSB +0+ sg1 \+ 0 -0+12020 +0+f000000b7 R_IA64_DTPREL64LSB +0+ sg1 \+ 0 -0+12028 +0+1200000097 R_IA64_TPREL64LSB +0+4 sg2 \+ 0 -0+12030 +0+a7 R_IA64_DTPMOD64LSB +0+ -0+12038 +0+97 R_IA64_TPREL64LSB +0+44 -0+12048 +0+97 R_IA64_TPREL64LSB +0+24 +0+112f0 +0+d000000a7 R_IA64_DTPMOD64LSB +0+ sg1 \+ 0 +0+112f8 +0+d000000b7 R_IA64_DTPREL64LSB +0+ sg1 \+ 0 +0+11300 +0+1000000097 R_IA64_TPREL64LSB +0+4 sg2 \+ 0 +0+11308 +0+a7 R_IA64_DTPMOD64LSB +0+ +0+11310 +0+97 R_IA64_TPREL64LSB +0+44 +0+11320 +0+97 R_IA64_TPREL64LSB +0+24 Relocation section '.rela.IA_64.pltoff' at offset 0x[0-9a-f]+ contains 1 entries: +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend -0+[0-9a-f]+ +0+e00000081 R_IA64_IPLTLSB +0+ __tls_get_addr \+ 0 +0+[0-9a-f]+ +0+c00000081 R_IA64_IPLTLSB +0+ __tls_get_addr \+ 0 -Symbol table '.dynsym' contains 23 entries: +Symbol table '.dynsym' contains 21 entries: +Num: +Value +Size Type +Bind +Vis +Ndx Name +[0-9]+: 0+ +0 NOTYPE +LOCAL +DEFAULT +UND * +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +7 * @@ -64,9 +64,7 @@ Symbol table '.dynsym' contains 23 entri +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +9 * +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +10 * +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +11 * - +[0-9]+: 0+ +0 NOTYPE +LOCAL +DEFAULT +UND * +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +14 * - +[0-9]+: 0+ +0 NOTYPE +LOCAL +DEFAULT +UND * +[0-9]+: 0+1c +0 TLS +GLOBAL DEFAULT +10 sg8 +[0-9]+: 0+11[0-9a-f]+ +0 OBJECT +GLOBAL DEFAULT +ABS _DYNAMIC +[0-9]+: 0+8 +0 TLS +GLOBAL DEFAULT +10 sg3 @@ -124,7 +122,7 @@ Symbol table '.symtab' contains 57 entri +[0-9]+: 0+74 +0 TLS +LOCAL +HIDDEN +11 sH6 +[0-9]+: 0+7c +0 TLS +LOCAL +HIDDEN +11 sH8 +[0-9]+: 0+40 +0 TLS +LOCAL +HIDDEN +10 sh1 - +[0-9]+: 0+12000 +0 OBJECT +LOCAL +HIDDEN +ABS _GLOBAL_OFFSET_TABLE_ + +[0-9]+: 0+112d8 +0 OBJECT +LOCAL +HIDDEN +ABS _GLOBAL_OFFSET_TABLE_ +[0-9]+: 0+44 +0 TLS +LOCAL +HIDDEN +10 sh2 +[0-9]+: 0+54 +0 TLS +LOCAL +HIDDEN +10 sh6 +[0-9]+: 0+1c +0 TLS +GLOBAL DEFAULT +10 sg8 diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-ia64/tlspic.sd binutils-2.16.91.0.2/ld/testsuite/ld-ia64/tlspic.sd --- binutils-2.16.91.0.1/ld/testsuite/ld-ia64/tlspic.sd 2004-05-27 11:26:05.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-ia64/tlspic.sd 2005-07-20 12:27:28.354018114 -0700 @@ -8,8 +8,8 @@ .*: +file format elf..-ia64-.* Contents of section .got: - 12000 0+ 0+ 0+ 0+ .* - 12010 0+ 0+ [0-9a-f]+ [0-9a-f]+ .* - 12020 [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ .* - 12030 [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ .* - 12040 440+ 0+ [0-9a-f]+ [0-9a-f]+ .* + 112d8 0+ 0+ 0+ 0+ .* + 112e8 0+ 0+ [0-9a-f]+ [0-9a-f]+ .* + 112f8 [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ .* + 11308 [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ .* + 11318 440+ 0+ [0-9a-f]+ [0-9a-f]+ .* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-mmix/bpo-10.d binutils-2.16.91.0.2/ld/testsuite/ld-mmix/bpo-10.d --- binutils-2.16.91.0.1/ld/testsuite/ld-mmix/bpo-10.d 2005-04-09 12:03:28.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-mmix/bpo-10.d 2005-07-20 12:27:28.372015146 -0700 @@ -12,6 +12,7 @@ SYMBOL TABLE: 0+ l d \.init 0+ (|\.init) 0+4 l d \.text 0+ (|\.text) +0+7f8 l +d \.MMIX.reg_contents 0+ (|\.MMIX\.reg_contents) 0+ l d \*ABS\* 0+ (|\.shstrtab) 0+ l d \*ABS\* 0+ (|\.symtab) 0+ l d \*ABS\* 0+ (|\.strtab) diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-mmix/bpo-22.d binutils-2.16.91.0.2/ld/testsuite/ld-mmix/bpo-22.d --- binutils-2.16.91.0.1/ld/testsuite/ld-mmix/bpo-22.d 2004-12-20 11:16:52.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-mmix/bpo-22.d 2005-07-20 12:27:28.379013992 -0700 @@ -11,8 +11,6 @@ SYMBOL TABLE: 0000000000000000 l d \.text 0+ (|\.text) -2000000000000000 l d \.data 0+ (|\.data) -2000000000000000 l d \.bss 0+ (|\.bss) 0+7f0 l d \.MMIX\.reg_contents 0+ (|\.MMIX\.reg_contents) 0+ l d \*ABS\* 0+ (|\.shstrtab) 0+ l d \*ABS\* 0+ (|\.symtab) diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-mmix/sec-7m.d binutils-2.16.91.0.2/ld/testsuite/ld-mmix/sec-7m.d --- binutils-2.16.91.0.1/ld/testsuite/ld-mmix/sec-7m.d 2003-05-15 13:42:26.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-mmix/sec-7m.d 2005-07-20 12:27:28.383013333 -0700 @@ -20,19 +20,19 @@ Sections: Idx Name[ ]+Size[ ]+VMA[ ]+LMA[ ]+File off Algn 0 \.text[ ]+0+4 0+ 0+ 0+ 2\*\*2 [ ]+CONTENTS, ALLOC, LOAD, CODE - 1 \.di 0+27ffb 2000000000000000 2000000000000000 0+ 2\*\*2 + 1 \.di +0+27ffb +0+4 +0+4 +0+ +2\*\*2 [ ]+CONTENTS, READONLY Contents of section \.text: 0000 e3fd0001[ ]+.* Contents of section \.di: - 2000000000000000 2a000000 00000000 00000000 00000000 .* + 00004 2a000000 00000000 00000000 00000000 .* #... - 2000000000007ff0 00000000 00000000 00000000 2b2c0000 .* + 07ff4 00000000 00000000 00000000 2b2c0000 .* #... - 200000000000fff0 00000000 00000000 00002d2e 00000000 .* + 0fff4 00000000 00000000 00002d2e 00000000 .* #... - 2000000000017ff0 00000000 00000000 002f3000 00000000 .* + 17ff4 00000000 00000000 002f3000 00000000 .* #... - 200000000001fff0 00000000 00000000 00313200 00000000 .* + 1fff4 00000000 00000000 00313200 00000000 .* #... - 2000000000027ff0 00000000 00000000 000033[ ]+.* + 27ff4 00000000 00000000 000033[ ]+.* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-powerpc/sdalib.s binutils-2.16.91.0.2/ld/testsuite/ld-powerpc/sdalib.s --- binutils-2.16.91.0.1/ld/testsuite/ld-powerpc/sdalib.s 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-powerpc/sdalib.s 2005-07-20 12:27:28.385013003 -0700 @@ -1,4 +1,5 @@ .globl lib_var .type lib_var, @object + .size lib_var, 2 lib_var: .word 1 diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-powerpc/tlsexe.r binutils-2.16.91.0.2/ld/testsuite/ld-powerpc/tlsexe.r --- binutils-2.16.91.0.1/ld/testsuite/ld-powerpc/tlsexe.r 2005-04-09 12:03:28.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-powerpc/tlsexe.r 2005-07-20 12:27:28.386012838 -0700 @@ -5,7 +5,7 @@ #readelf: -WSsrl #target: powerpc64*-*-* -There are 16 section headers.* +There are 17 section headers.* Section Headers: +\[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al @@ -17,14 +17,15 @@ Section Headers: +\[ 5\] \.rela\.dyn +.* +\[ 6\] \.rela\.plt +.* +\[ 7\] \.text +PROGBITS .* 0+fc 0+ +AX +0 +0 +4 - +\[ 8\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8 - +\[ 9\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8 - +\[10\] \.dynamic +DYNAMIC .* 0+150 10 +WA +4 +0 +8 - +\[11\] \.got +PROGBITS .* 0+30 08 +WA +0 +0 +8 - +\[12\] \.plt +.* - +\[13\] \.shstrtab +.* - +\[14\] \.symtab +.* - +\[15\] \.strtab +.* + +\[ 8\] \.rodata + PROGBITS .* 0+ 0+ +A +0 +0 +8 + +\[ 9\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8 + +\[10\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8 + +\[11\] \.dynamic +DYNAMIC .* 0+150 10 +WA +4 +0 +8 + +\[12\] \.got +PROGBITS .* 0+30 08 +WA +0 +0 +8 + +\[13\] \.plt +.* + +\[14\] \.shstrtab +.* + +\[15\] \.symtab +.* + +\[16\] \.strtab +.* #... Elf file type is EXEC \(Executable file\) @@ -36,7 +37,7 @@ Program Headers: +PHDR +0x0+40 0x0+10000040 0x0+10000040 0x0+150 0x0+150 R E 0x8 +INTERP +0x0+190 0x0+10000190 0x0+10000190 0x0+11 0x0+11 R +0x1 +\[Requesting program interpreter: .*\] - +LOAD +0x0+ 0x0+10000000 0x0+10000000 0x0+464 0x0+464 R E 0x10000 + +LOAD +0x0+ 0x0+10000000 0x0+10000000 0x0+468 0x0+468 R E 0x10000 +LOAD +0x0+468 0x0+10010468 0x0+10010468 0x0+1b8 0x0+1e8 RW +0x10000 +DYNAMIC +0x0+4a0 0x0+100104a0 0x0+100104a0 0x0+150 0x0+150 RW +0x8 +TLS +0x0+468 0x0+10010468 0x0+10010468 0x0+38 0x0+70 R +0x8 @@ -52,9 +53,9 @@ Program Headers: Relocation section '\.rela\.dyn' at offset .* contains 3 entries: +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend -0+10010600 +0+200000049 R_PPC64_TPREL64 +0+ gd \+ 0 -0+10010608 +0+400000044 R_PPC64_DTPMOD64 +0+ ld \+ 0 -0+10010618 +0+50000004e R_PPC64_DTPREL64 +0+50 ld2 \+ 0 +[0-9a-f ]+R_PPC64_TPREL64 +0+ gd \+ 0 +[0-9a-f ]+R_PPC64_DTPMOD64 +0+ ld \+ 0 +[0-9a-f ]+R_PPC64_DTPREL64 +0+50 ld2 \+ 0 Relocation section '\.rela\.plt' at offset .* contains 1 entries: +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend @@ -67,12 +68,12 @@ Symbol table '\.dynsym' contains 9 entri .* 0+ +0 TLS +GLOBAL DEFAULT +UND gd .* 0+ +0 FUNC +GLOBAL DEFAULT +UND __tls_get_addr .* 0+ +0 TLS +GLOBAL DEFAULT +UND ld -.* 0+50 +0 TLS +GLOBAL DEFAULT +9 ld2 +.* 0+50 +0 TLS +GLOBAL DEFAULT +10 ld2 .* 0+10010620 +0 NOTYPE +GLOBAL DEFAULT +ABS __bss_start .* 0+10010620 +0 NOTYPE +GLOBAL DEFAULT +ABS _edata .* 0+10010650 +0 NOTYPE +GLOBAL DEFAULT +ABS _end -Symbol table '\.symtab' contains 39 entries: +Symbol table '\.symtab' contains 40 entries: +Num: +Value +Size Type +Bind +Vis +Ndx Name .* 0+ +0 NOTYPE +LOCAL +DEFAULT +UND .* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +1 @@ -82,34 +83,35 @@ Symbol table '\.symtab' contains 39 entr .* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +5 .* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +6 .* 0+10000368 +0 SECTION LOCAL +DEFAULT +7 -.* 0+10010468 +0 SECTION LOCAL +DEFAULT +8 -.* 0+100104a0 +0 SECTION LOCAL +DEFAULT +9 +.* 0+10000468 +0 SECTION LOCAL +DEFAULT +8 +.* 0+10010468 +0 SECTION LOCAL +DEFAULT +9 .* 0+100104a0 +0 SECTION LOCAL +DEFAULT +10 -.* 0+100105f0 +0 SECTION LOCAL +DEFAULT +11 -.* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +12 +.* 0+100104a0 +0 SECTION LOCAL +DEFAULT +11 +.* 0+100105f0 +0 SECTION LOCAL +DEFAULT +12 .* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +13 .* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +14 .* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +15 -.* 0+ +0 TLS +LOCAL +DEFAULT +8 gd4 -.* 0+8 +0 TLS +LOCAL +DEFAULT +8 ld4 -.* 0+10 +0 TLS +LOCAL +DEFAULT +8 ld5 -.* 0+18 +0 TLS +LOCAL +DEFAULT +8 ld6 -.* 0+20 +0 TLS +LOCAL +DEFAULT +8 ie4 -.* 0+28 +0 TLS +LOCAL +DEFAULT +8 le4 -.* 0+30 +0 TLS +LOCAL +DEFAULT +8 le5 +.* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +16 +.* 0+ +0 TLS +LOCAL +DEFAULT +9 gd4 +.* 0+8 +0 TLS +LOCAL +DEFAULT +9 ld4 +.* 0+10 +0 TLS +LOCAL +DEFAULT +9 ld5 +.* 0+18 +0 TLS +LOCAL +DEFAULT +9 ld6 +.* 0+20 +0 TLS +LOCAL +DEFAULT +9 ie4 +.* 0+28 +0 TLS +LOCAL +DEFAULT +9 le4 +.* 0+30 +0 TLS +LOCAL +DEFAULT +9 le5 .* 0+ +0 FUNC +LOCAL +DEFAULT +UND \.__tls_get_addr .* 0+100104a0 +0 OBJECT +GLOBAL DEFAULT +ABS _DYNAMIC .* 0+ +0 TLS +GLOBAL DEFAULT +UND gd -.* 0+60 +0 TLS +GLOBAL DEFAULT +9 le0 +.* 0+60 +0 TLS +GLOBAL DEFAULT +10 le0 .* 0+ +0 FUNC +GLOBAL DEFAULT +UND __tls_get_addr -.* 0+40 +0 TLS +GLOBAL DEFAULT +9 ld0 -.* 0+68 +0 TLS +GLOBAL DEFAULT +9 le1 +.* 0+40 +0 TLS +GLOBAL DEFAULT +10 ld0 +.* 0+68 +0 TLS +GLOBAL DEFAULT +10 le1 .* 0+ +0 TLS +GLOBAL DEFAULT +UND ld .* [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +7 _start -.* 0+50 +0 TLS +GLOBAL DEFAULT +9 ld2 -.* 0+48 +0 TLS +GLOBAL DEFAULT +9 ld1 +.* 0+50 +0 TLS +GLOBAL DEFAULT +10 ld2 +.* 0+48 +0 TLS +GLOBAL DEFAULT +10 ld1 .* [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS __bss_start .* [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS _edata .* [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS _end -.* 0+38 +0 TLS +GLOBAL DEFAULT +9 gd0 -.* 0+58 +0 TLS +GLOBAL DEFAULT +9 ie0 +.* 0+38 +0 TLS +GLOBAL DEFAULT +10 gd0 +.* 0+58 +0 TLS +GLOBAL DEFAULT +10 ie0 diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-powerpc/tlsexetoc.r binutils-2.16.91.0.2/ld/testsuite/ld-powerpc/tlsexetoc.r --- binutils-2.16.91.0.1/ld/testsuite/ld-powerpc/tlsexetoc.r 2005-04-09 12:03:29.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-powerpc/tlsexetoc.r 2005-07-20 12:27:28.387012673 -0700 @@ -5,7 +5,7 @@ #readelf: -WSsrl #target: powerpc64*-*-* -There are 16 section headers.* +There are 17 section headers.* Section Headers: +\[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al @@ -17,14 +17,15 @@ Section Headers: +\[ 5\] \.rela\.dyn +.* +\[ 6\] \.rela\.plt +.* +\[ 7\] \.text +PROGBITS .* 0+bc 0+ +AX +0 +0 +4 - +\[ 8\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8 - +\[ 9\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8 - +\[10\] \.dynamic +DYNAMIC .* 0+150 10 +WA +4 +0 +8 - +\[11\] \.got +PROGBITS .* 0+58 08 +WA +0 +0 +8 - +\[12\] \.plt +.* - +\[13\] \.shstrtab +.* - +\[14\] \.symtab +.* - +\[15\] \.strtab +.* + +\[ 8\] \.rodata +PROGBITS .* 0+ 0+ +A +0 +0 +8 + +\[ 9\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8 + +\[10\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8 + +\[11\] \.dynamic +DYNAMIC .* 0+150 10 +WA +4 +0 +8 + +\[12\] \.got +PROGBITS .* 0+58 08 +WA +0 +0 +8 + +\[13\] \.plt +.* + +\[14\] \.shstrtab +.* + +\[15\] \.symtab +.* + +\[16\] \.strtab +.* #... Elf file type is EXEC \(Executable file\) @@ -36,7 +37,7 @@ Program Headers: +PHDR +0x0+40 0x0+10000040 0x0+10000040 0x0+150 0x0+150 R E 0x8 +INTERP +0x0+190 0x0+10000190 0x0+10000190 0x0+11 0x0+11 R +0x1 +\[Requesting program interpreter: .*\] - +LOAD +0x0+ 0x0+10000000 0x0+10000000 0x0+3f4 0x0+3f4 R E 0x10000 + +LOAD +0x0+ 0x0+10000000 0x0+10000000 0x0+3f8 0x0+3f8 R E 0x10000 +LOAD +0x0+3f8 0x0+100103f8 0x0+100103f8 0x0+1e0 0x0+210 RW +0x10000 +DYNAMIC +0x0+430 0x0+10010430 0x0+10010430 0x0+150 0x0+150 RW +0x8 +TLS +0x0+3f8 0x0+100103f8 0x0+100103f8 0x0+38 0x0+70 R +0x8 @@ -70,7 +71,7 @@ Symbol table '\.dynsym' contains 8 entri .* [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS _edata .* [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS _end -Symbol table '\.symtab' contains 40 entries: +Symbol table '\.symtab' contains 41 entries: +Num: +Value +Size Type +Bind +Vis +Ndx Name .* 0+ +0 NOTYPE +LOCAL +DEFAULT +UND .* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +1 @@ -80,35 +81,36 @@ Symbol table '\.symtab' contains 40 entr .* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +5 .* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +6 .* 0+10000338 +0 SECTION LOCAL +DEFAULT +7 -.* 0+100103f8 +0 SECTION LOCAL +DEFAULT +8 -.* 0+10010430 +0 SECTION LOCAL +DEFAULT +9 +.* 0+100003f8 +0 SECTION LOCAL +DEFAULT +8 +.* 0+100103f8 +0 SECTION LOCAL +DEFAULT +9 .* 0+10010430 +0 SECTION LOCAL +DEFAULT +10 -.* 0+10010580 +0 SECTION LOCAL +DEFAULT +11 -.* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +12 +.* 0+10010430 +0 SECTION LOCAL +DEFAULT +11 +.* 0+10010580 +0 SECTION LOCAL +DEFAULT +12 .* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +13 .* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +14 .* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +15 -.* 0+ +0 TLS +LOCAL +DEFAULT +8 gd4 -.* 0+8 +0 TLS +LOCAL +DEFAULT +8 ld4 -.* 0+10 +0 TLS +LOCAL +DEFAULT +8 ld5 -.* 0+18 +0 TLS +LOCAL +DEFAULT +8 ld6 -.* 0+20 +0 TLS +LOCAL +DEFAULT +8 ie4 -.* 0+28 +0 TLS +LOCAL +DEFAULT +8 le4 -.* 0+30 +0 TLS +LOCAL +DEFAULT +8 le5 -.* 0+100105d0 +0 NOTYPE +LOCAL +DEFAULT +11 \.Lie0 +.* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +16 +.* 0+ +0 TLS +LOCAL +DEFAULT +9 gd4 +.* 0+8 +0 TLS +LOCAL +DEFAULT +9 ld4 +.* 0+10 +0 TLS +LOCAL +DEFAULT +9 ld5 +.* 0+18 +0 TLS +LOCAL +DEFAULT +9 ld6 +.* 0+20 +0 TLS +LOCAL +DEFAULT +9 ie4 +.* 0+28 +0 TLS +LOCAL +DEFAULT +9 le4 +.* 0+30 +0 TLS +LOCAL +DEFAULT +9 le5 +.* 0+100105d0 +0 NOTYPE +LOCAL +DEFAULT +12 \.Lie0 .* 0+ +0 FUNC +LOCAL +DEFAULT +UND \.__tls_get_addr .* 0+10010430 +0 OBJECT +GLOBAL DEFAULT +ABS _DYNAMIC .* 0+ +0 TLS +GLOBAL DEFAULT +UND gd -.* 0+60 +0 TLS +GLOBAL DEFAULT +9 le0 +.* 0+60 +0 TLS +GLOBAL DEFAULT +10 le0 .* 0+ +0 FUNC +GLOBAL DEFAULT +UND __tls_get_addr -.* 0+40 +0 TLS +GLOBAL DEFAULT +9 ld0 -.* 0+68 +0 TLS +GLOBAL DEFAULT +9 le1 +.* 0+40 +0 TLS +GLOBAL DEFAULT +10 ld0 +.* 0+68 +0 TLS +GLOBAL DEFAULT +10 le1 .* 0+ +0 TLS +GLOBAL DEFAULT +UND ld .* 0+10000354 +0 NOTYPE +GLOBAL DEFAULT +7 _start -.* 0+50 +0 TLS +GLOBAL DEFAULT +9 ld2 -.* 0+48 +0 TLS +GLOBAL DEFAULT +9 ld1 +.* 0+50 +0 TLS +GLOBAL DEFAULT +10 ld2 +.* 0+48 +0 TLS +GLOBAL DEFAULT +10 ld1 .* 0+100105d8 +0 NOTYPE +GLOBAL DEFAULT +ABS __bss_start .* 0+100105d8 +0 NOTYPE +GLOBAL DEFAULT +ABS _edata .* 0+10010608 +0 NOTYPE +GLOBAL DEFAULT +ABS _end -.* 0+38 +0 TLS +GLOBAL DEFAULT +9 gd0 -.* 0+58 +0 TLS +GLOBAL DEFAULT +9 ie0 +.* 0+38 +0 TLS +GLOBAL DEFAULT +10 gd0 +.* 0+58 +0 TLS +GLOBAL DEFAULT +10 ie0 diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-powerpc/tlsso32.d binutils-2.16.91.0.2/ld/testsuite/ld-powerpc/tlsso32.d --- binutils-2.16.91.0.1/ld/testsuite/ld-powerpc/tlsso32.d 2005-05-10 15:46:53.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-powerpc/tlsso32.d 2005-07-20 12:27:28.425006408 -0700 @@ -42,5 +42,5 @@ Disassembly of section \.got: .* <\.got>: \.\.\. .*: 4e 80 00 21 blrl -.*: 00 01 04 90 .* +.*: 00 01 04 54 .* \.\.\. diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-powerpc/tlsso32.g binutils-2.16.91.0.2/ld/testsuite/ld-powerpc/tlsso32.g --- binutils-2.16.91.0.1/ld/testsuite/ld-powerpc/tlsso32.g 2005-05-10 15:46:53.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-powerpc/tlsso32.g 2005-07-20 12:27:28.425006408 -0700 @@ -9,5 +9,5 @@ Contents of section \.got: .* 00000000 00000000 00000000 00000000 .* .* 00000000 00000000 00000000 00000000 .* -.* 00000000 4e800021 00010490 00000000 .* +.* 00000000 4e800021 00010454 00000000 .* .* 00000000 .* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-powerpc/tlsso32.r binutils-2.16.91.0.2/ld/testsuite/ld-powerpc/tlsso32.r --- binutils-2.16.91.0.1/ld/testsuite/ld-powerpc/tlsso32.r 2005-05-10 15:46:53.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-powerpc/tlsso32.r 2005-07-20 12:27:28.426006243 -0700 @@ -14,11 +14,11 @@ Section Headers: +\[ 3\] \.dynstr +.* +\[ 4\] \.rela\.dyn +.* +\[ 5\] \.rela\.plt +.* - +\[ 6\] \.text +PROGBITS +0+404 0+404 0+70 0+ +AX +0 +0 +1 - +\[ 7\] \.tdata +PROGBITS +0+10474 0+474 0+1c 0+ WAT +0 +0 +4 - +\[ 8\] \.tbss +NOBITS +0+10490 0+490 0+1c 0+ WAT +0 +0 +4 - +\[ 9\] \.dynamic +DYNAMIC +0+10490 0+490 0+a0 08 +WA +3 +0 +4 - +\[10\] \.got +PROGBITS +0+10530 0+530 0+34 04 WAX +0 +0 +4 + +\[ 6\] \.text +PROGBITS +0+3c8 0+3c8 0+70 0+ +AX +0 +0 +1 + +\[ 7\] \.tdata +PROGBITS +0+10438 0+438 0+1c 0+ WAT +0 +0 +4 + +\[ 8\] \.tbss +NOBITS +0+10454 0+454 0+1c 0+ WAT +0 +0 +4 + +\[ 9\] \.dynamic +DYNAMIC +0+10454 0+454 0+a0 08 +WA +3 +0 +4 + +\[10\] \.got +PROGBITS +0+104f4 0+4f4 0+34 04 WAX +0 +0 +4 +\[11\] \.plt +.* +\[12\] \.shstrtab +.* +\[13\] \.symtab +.* @@ -31,10 +31,10 @@ There are 4 program headers.* Program Headers: +Type +Offset +VirtAddr +PhysAddr +FileSiz MemSiz +Flg Align - +LOAD +0x0+ 0x0+ 0x0+ 0x0+474 0x0+474 R E 0x10000 - +LOAD +0x0+474 0x0+10474 0x0+10474 0x0+f0 0x0+144 RWE 0x10000 - +DYNAMIC +0x0+490 0x0+10490 0x0+10490 0x0+a0 0x0+a0 RW +0x4 - +TLS +0x0+474 0x0+10474 0x0+10474 0x0+1c 0x0+38 R +0x4 + +LOAD +0x0+ 0x0+ 0x0+ 0x0+438 0x0+438 R E 0x10000 + +LOAD +0x0+438 0x0+10438 0x0+10438 0x0+f0 0x0+144 RWE 0x10000 + +DYNAMIC +0x0+454 0x0+10454 0x0+10454 0x0+a0 0x0+a0 RW +0x4 + +TLS +0x0+438 0x0+10438 0x0+10438 0x0+1c 0x0+38 R +0x4 Section to Segment mapping: +Segment Sections\.\.\. @@ -45,39 +45,36 @@ Program Headers: Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 18 entries: Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend -0+408 +0+a0a R_PPC_REL24 +0+ +__tls_get_addr \+ 0 -0+410 +0+a0a R_PPC_REL24 +0+ +__tls_get_addr \+ 0 -0+448 +0+a0a R_PPC_REL24 +0+ +__tls_get_addr \+ 0 -0+450 +0+a0a R_PPC_REL24 +0+ +__tls_get_addr \+ 0 -0+43a +0+945 R_PPC_TPREL16 +0+30 +le0 \+ 0 -0+43e +0+c48 R_PPC_TPREL16_HA +0+34 +le1 \+ 0 -0+442 +0+c46 R_PPC_TPREL16_LO +0+34 +le1 \+ 0 -0+46a +0+245 R_PPC_TPREL16 +0+10474 +\.tdata \+ 10488 -0+46e +0+248 R_PPC_TPREL16_HA +0+10474 +\.tdata \+ 1048c -0+472 +0+246 R_PPC_TPREL16_LO +0+10474 +\.tdata \+ 1048c -0+10530 +0+44 R_PPC_DTPMOD32 +0+ -0+10534 +0+4e R_PPC_DTPREL32 +0+ -0+10538 +0+44 R_PPC_DTPMOD32 +0+ -0+10540 +0+844 R_PPC_DTPMOD32 +0+ +gd \+ 0 -0+10544 +0+84e R_PPC_DTPREL32 +0+ +gd \+ 0 -0+10548 +0+1544 R_PPC_DTPMOD32 +0+1c +gd0 \+ 0 -0+1054c +0+154e R_PPC_DTPREL32 +0+1c +gd0 \+ 0 -0+10550 +0+1649 R_PPC_TPREL32 +0+2c +ie0 \+ 0 +[0-9a-f ]+R_PPC_REL24 +0+ +__tls_get_addr \+ 0 +[0-9a-f ]+R_PPC_REL24 +0+ +__tls_get_addr \+ 0 +[0-9a-f ]+R_PPC_REL24 +0+ +__tls_get_addr \+ 0 +[0-9a-f ]+R_PPC_REL24 +0+ +__tls_get_addr \+ 0 +[0-9a-f ]+R_PPC_TPREL16 +0+30 +le0 \+ 0 +[0-9a-f ]+R_PPC_TPREL16_HA +0+34 +le1 \+ 0 +[0-9a-f ]+R_PPC_TPREL16_LO +0+34 +le1 \+ 0 +[0-9a-f ]+R_PPC_TPREL16 +0+10438 +\.tdata \+ 1044c +[0-9a-f ]+R_PPC_TPREL16_HA +0+10438 +\.tdata \+ 10450 +[0-9a-f ]+R_PPC_TPREL16_LO +0+10438 +\.tdata \+ 10450 +[0-9a-f ]+R_PPC_DTPMOD32 +0+ +[0-9a-f ]+R_PPC_DTPREL32 +0+ +[0-9a-f ]+R_PPC_DTPMOD32 +0+ +[0-9a-f ]+R_PPC_DTPMOD32 +0+ +gd \+ 0 +[0-9a-f ]+R_PPC_DTPREL32 +0+ +gd \+ 0 +[0-9a-f ]+R_PPC_DTPMOD32 +0+1c +gd0 \+ 0 +[0-9a-f ]+R_PPC_DTPREL32 +0+1c +gd0 \+ 0 +[0-9a-f ]+R_PPC_TPREL32 +0+2c +ie0 \+ 0 Relocation section '\.rela\.plt' at offset 0x[0-9a-f]+ contains 1 entries: Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend -0+105ac +0+a15 R_PPC_JMP_SLOT +0+ +__tls_get_addr \+ 0 +[0-9a-f ]+R_PPC_JMP_SLOT +0+ +__tls_get_addr \+ 0 -Symbol table '\.dynsym' contains 23 entries: +Symbol table '\.dynsym' contains 20 entries: +Num: +Value +Size Type +Bind +Vis +Ndx Name +[0-9]+: 0+ +0 NOTYPE +LOCAL +DEFAULT +UND - +[0-9]+: 0+404 +0 SECTION LOCAL +DEFAULT +6 - +[0-9]+: 0+10474 +0 SECTION LOCAL +DEFAULT +7 - +[0-9]+: 0+10490 +0 SECTION LOCAL +DEFAULT +8 - +[0-9]+: 0+ +0 NOTYPE +LOCAL +DEFAULT +UND - +[0-9]+: 0+ +0 NOTYPE +LOCAL +DEFAULT +UND - +[0-9]+: 0+ +0 NOTYPE +LOCAL +DEFAULT +UND - +[0-9]+: 0+10490 +0 OBJECT +GLOBAL DEFAULT +ABS _DYNAMIC + +[0-9]+: 0+3c8 +0 SECTION LOCAL +DEFAULT +6 + +[0-9]+: 0+10438 +0 SECTION LOCAL +DEFAULT +7 + +[0-9]+: 0+10454 +0 SECTION LOCAL +DEFAULT +8 + +[0-9]+: 0+10454 +0 OBJECT +GLOBAL DEFAULT +ABS _DYNAMIC +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT +UND gd +[0-9]+: 0+30 +0 TLS +GLOBAL DEFAULT +8 le0 +[0-9]+: 0+ +0 NOTYPE +GLOBAL DEFAULT +UND __tls_get_addr @@ -102,11 +99,11 @@ Symbol table '\.symtab' contains 39 entr +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +3 +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +4 +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +5 - +[0-9]+: 0+404 +0 SECTION LOCAL +DEFAULT +6 - +[0-9]+: 0+10474 +0 SECTION LOCAL +DEFAULT +7 - +[0-9]+: 0+10490 +0 SECTION LOCAL +DEFAULT +8 + +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +6 + +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +7 + +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +8 +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +9 - +[0-9]+: 0+10530 +0 SECTION LOCAL +DEFAULT +10 + +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +10 +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +11 +[0-9]+: 0+ +0 SECTION LOCAL +DEFAULT +12 +[0-9]+: 0+ +0 SECTION LOCAL +DEFAULT +13 @@ -118,8 +115,8 @@ Symbol table '\.symtab' contains 39 entr +[0-9]+: 0+10 +0 TLS +LOCAL +DEFAULT +7 ie4 +[0-9]+: 0+14 +0 TLS +LOCAL +DEFAULT +7 le4 +[0-9]+: 0+18 +0 TLS +LOCAL +DEFAULT +7 le5 - +[0-9]+: 0+10558 +0 OBJECT +LOCAL +HIDDEN +ABS _GLOBAL_OFFSET_TABLE_ - +[0-9]+: 0+10490 +0 OBJECT +GLOBAL DEFAULT +ABS _DYNAMIC + +[0-9]+: 0+1051c +0 OBJECT +LOCAL +HIDDEN +ABS _GLOBAL_OFFSET_TABLE_ + +[0-9]+: 0+10454 +0 OBJECT +GLOBAL DEFAULT +ABS _DYNAMIC +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT +UND gd +[0-9]+: 0+30 +0 TLS +GLOBAL DEFAULT +8 le0 +[0-9]+: 0+ +0 NOTYPE +GLOBAL DEFAULT +UND __tls_get_addr diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-powerpc/tlsso.g binutils-2.16.91.0.2/ld/testsuite/ld-powerpc/tlsso.g --- binutils-2.16.91.0.1/ld/testsuite/ld-powerpc/tlsso.g 2004-05-27 11:26:06.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-powerpc/tlsso.g 2005-07-20 12:27:28.405009706 -0700 @@ -7,9 +7,9 @@ .*: +file format elf64-powerpc Contents of section \.got: - 10850 00000000 00018850 00000000 00000000 .* - 10860 00000000 00000000 00000000 00000000 .* - 10870 00000000 00000000 00000000 00000000 .* - 10880 00000000 00000000 00000000 00000000 .* - 10890 00000000 00000000 00000000 00000000 .* - 108a0 00000000 00000000 00000000 00000000 .* + 10818 00000000 00018818 00000000 00000000 .* + 10828 00000000 00000000 00000000 00000000 .* + 10838 00000000 00000000 00000000 00000000 .* + 10848 00000000 00000000 00000000 00000000 .* + 10858 00000000 00000000 00000000 00000000 .* + 10868 00000000 00000000 00000000 00000000 .* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-powerpc/tlsso.r binutils-2.16.91.0.2/ld/testsuite/ld-powerpc/tlsso.r --- binutils-2.16.91.0.1/ld/testsuite/ld-powerpc/tlsso.r 2005-04-09 12:03:29.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-powerpc/tlsso.r 2005-07-20 12:27:28.406009541 -0700 @@ -4,7 +4,7 @@ #readelf: -WSsrl #target: powerpc64*-*-* -There are 15 section headers.* +There are 16 section headers.* Section Headers: +\[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al @@ -14,15 +14,16 @@ Section Headers: +\[ 3\] \.dynstr +.* +\[ 4\] \.rela\.dyn +.* +\[ 5\] \.rela\.plt +.* - +\[ 6\] \.text +PROGBITS +0+5c8 0+5c8 0+fc 0+ +AX +0 +0 +4 - +\[ 7\] \.tdata +PROGBITS +0+106c8 0+6c8 0+38 0+ WAT +0 +0 +8 - +\[ 8\] \.tbss +NOBITS +0+10700 0+700 0+38 0+ WAT +0 +0 +8 - +\[ 9\] \.dynamic +DYNAMIC +0+10700 0+700 0+150 10 +WA +3 +0 +8 - +\[10\] \.got +PROGBITS +0+10850 0+850 0+60 08 +WA +0 +0 +8 - +\[11\] \.plt +.* - +\[12\] \.shstrtab +.* - +\[13\] \.symtab +.* - +\[14\] \.strtab +.* + +\[ 6\] \.text +PROGBITS +0+590 0+590 0+fc 0+ +AX +0 +0 +4 + +\[ 7\] \.tdata +PROGBITS +0+10690 0+690 0+38 0+ WAT +0 +0 +8 + +\[ 8\] \.tbss +NOBITS +0+106c8 0+6c8 0+38 0+ WAT +0 +0 +8 + +\[ 9\] \.data\.rel\.ro +PROGBITS .* + +\[10\] \.dynamic +DYNAMIC +0+106c8 0+6c8 0+150 10 +WA +3 +0 +8 + +\[11\] \.got +PROGBITS +0+10818 0+818 0+60 08 +WA +0 +0 +8 + +\[12\] \.plt +.* + +\[13\] \.shstrtab +.* + +\[14\] \.symtab +.* + +\[15\] \.strtab +.* #... Elf file type is DYN \(Shared object file\) @@ -31,10 +32,10 @@ There are 4 program headers.* Program Headers: +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align - +LOAD +0x0+ 0x0+ 0x0+ 0x0+6c4 0x0+6c4 R E 0x10000 - +LOAD +0x0+6c8 0x0+106c8 0x0+106c8 0x0+1e8 0x0+218 RW +0x10000 - +DYNAMIC +0x0+700 0x0+10700 0x0+10700 0x0+150 0x0+150 RW +0x8 - +TLS +0x0+6c8 0x0+106c8 0x0+106c8 0x0+38 0x0+70 R +0x8 + +LOAD +0x0+ 0x0+ 0x0+ 0x0+68c 0x0+68c R E 0x10000 + +LOAD +0x0+690 0x0+10690 0x0+10690 0x0+1e8 0x0+218 RW +0x10000 + +DYNAMIC +0x0+6c8 0x0+106c8 0x0+106c8 0x0+150 0x0+150 RW +0x8 + +TLS +0x0+690 0x0+10690 0x0+10690 0x0+38 0x0+70 R +0x8 Section to Segment mapping: +Segment Sections\.\.\. @@ -45,37 +46,35 @@ Program Headers: Relocation section '\.rela\.dyn' at offset .* contains 16 entries: +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend -0+632 +0+90+45 R_PPC64_TPREL16 +0+60 le0 \+ 0 -0+636 +0+c0+48 R_PPC64_TPREL16_HA +0+68 le1 \+ 0 -0+63a +0+c0+46 R_PPC64_TPREL16_LO +0+68 le1 \+ 0 -0+672 +0+20+5f R_PPC64_TPREL16_DS +0+106c8 \.tdata \+ 28 -0+676 +0+20+48 R_PPC64_TPREL16_HA +0+106c8 \.tdata \+ 30 -0+67a +0+20+46 R_PPC64_TPREL16_LO +0+106c8 \.tdata \+ 30 -0+10858 +0+44 R_PPC64_DTPMOD64 +0+ -0+10868 +0+44 R_PPC64_DTPMOD64 +0+ -0+10870 +0+4e R_PPC64_DTPREL64 +0+ -0+10878 +0+4e R_PPC64_DTPREL64 +0+18 -0+10880 +0+80+44 R_PPC64_DTPMOD64 +0+ gd \+ 0 -0+10888 +0+80+4e R_PPC64_DTPREL64 +0+ gd \+ 0 -0+10890 +0+f0+4e R_PPC64_DTPREL64 +0+50 ld2 \+ 0 -0+10898 +0+140+44 R_PPC64_DTPMOD64 +0+38 gd0 \+ 0 -0+108a0 +0+140+4e R_PPC64_DTPREL64 +0+38 gd0 \+ 0 -0+108a8 +0+150+49 R_PPC64_TPREL64 +0+58 ie0 \+ 0 +[0-9a-f ]+R_PPC64_TPREL16 +0+60 le0 \+ 0 +[0-9a-f ]+R_PPC64_TPREL16_HA +0+68 le1 \+ 0 +[0-9a-f ]+R_PPC64_TPREL16_LO +0+68 le1 \+ 0 +[0-9a-f ]+R_PPC64_TPREL16_DS +0+10690 \.tdata \+ 28 +[0-9a-f ]+R_PPC64_TPREL16_HA +0+10690 \.tdata \+ 30 +[0-9a-f ]+R_PPC64_TPREL16_LO +0+10690 \.tdata \+ 30 +[0-9a-f ]+R_PPC64_DTPMOD64 +0+ +[0-9a-f ]+R_PPC64_DTPMOD64 +0+ +[0-9a-f ]+R_PPC64_DTPREL64 +0+ +[0-9a-f ]+R_PPC64_DTPREL64 +0+18 +[0-9a-f ]+R_PPC64_DTPMOD64 +0+ gd \+ 0 +[0-9a-f ]+R_PPC64_DTPREL64 +0+ gd \+ 0 +[0-9a-f ]+R_PPC64_DTPREL64 +0+50 ld2 \+ 0 +[0-9a-f ]+R_PPC64_DTPMOD64 +0+38 gd0 \+ 0 +[0-9a-f ]+R_PPC64_DTPREL64 +0+38 gd0 \+ 0 +[0-9a-f ]+R_PPC64_TPREL64 +0+58 ie0 \+ 0 Relocation section '\.rela\.plt' at offset .* contains 1 entries: +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend -0+108c8 +0+a0+15 R_PPC64_JMP_SLOT +0+ __tls_get_addr \+ 0 +[0-9a-f ]+R_PPC64_JMP_SLOT +0+ __tls_get_addr \+ 0 -Symbol table '\.dynsym' contains 22 entries: +Symbol table '\.dynsym' contains 20 entries: +Num: +Value +Size Type +Bind +Vis +Ndx Name +[0-9]+: 0+ +0 NOTYPE +LOCAL +DEFAULT +UND - +[0-9]+: 0+5c8 +0 SECTION LOCAL +DEFAULT +6 - +[0-9]+: 0+106c8 +0 SECTION LOCAL +DEFAULT +7 - +[0-9]+: 0+10700 +0 SECTION LOCAL +DEFAULT +8 - +[0-9]+: 0+ +0 NOTYPE +LOCAL +DEFAULT +UND - +[0-9]+: 0+ +0 NOTYPE +LOCAL +DEFAULT +UND - +[0-9]+: 0+ +0 NOTYPE +LOCAL +DEFAULT +UND - +[0-9]+: 0+10700 +0 OBJECT +GLOBAL DEFAULT +ABS _DYNAMIC + +[0-9]+: 0+590 +0 SECTION LOCAL +DEFAULT +6 + +[0-9]+: 0+10690 +0 SECTION LOCAL +DEFAULT +7 + +[0-9]+: 0+106c8 +0 SECTION LOCAL +DEFAULT +8 + +[0-9]+: 0+106c8 +0 SECTION LOCAL +DEFAULT +9 + +[0-9]+: 0+106c8 +0 OBJECT +GLOBAL DEFAULT +ABS _DYNAMIC +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT +UND gd +[0-9]+: 0+60 +0 TLS +GLOBAL DEFAULT +8 le0 +[0-9]+: 0+ +0 NOTYPE +GLOBAL DEFAULT +UND __tls_get_addr @@ -91,7 +90,7 @@ Symbol table '\.dynsym' contains 22 entr +[0-9]+: 0+38 +0 TLS +GLOBAL DEFAULT +8 gd0 +[0-9]+: 0+58 +0 TLS +GLOBAL DEFAULT +8 ie0 -Symbol table '\.symtab' contains 38 entries: +Symbol table '\.symtab' contains 39 entries: +Num: +Value +Size Type +Bind +Vis +Ndx Name +[0-9]+: 0+ +0 NOTYPE +LOCAL +DEFAULT +UND +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +1 @@ -99,15 +98,16 @@ Symbol table '\.symtab' contains 38 entr +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +3 +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +4 +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +5 - +[0-9]+: 0+5c8 +0 SECTION LOCAL +DEFAULT +6 - +[0-9]+: 0+106c8 +0 SECTION LOCAL +DEFAULT +7 - +[0-9]+: 0+10700 +0 SECTION LOCAL +DEFAULT +8 - +[0-9]+: 0+10700 +0 SECTION LOCAL +DEFAULT +9 - +[0-9]+: 0+10850 +0 SECTION LOCAL +DEFAULT +10 + +[0-9]+: 0+590 +0 SECTION LOCAL +DEFAULT +6 + +[0-9]+: 0+10690 +0 SECTION LOCAL +DEFAULT +7 + +[0-9]+: 0+106c8 +0 SECTION LOCAL +DEFAULT +8 + +[0-9]+: 0+106c8 +0 SECTION LOCAL +DEFAULT +9 + +[0-9]+: 0+106c8 +0 SECTION LOCAL +DEFAULT +10 +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +11 +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +12 +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +13 +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +14 + +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +15 +[0-9]+: 0+ +0 TLS +LOCAL +DEFAULT +7 gd4 +[0-9]+: 0+8 +0 TLS +LOCAL +DEFAULT +7 ld4 +[0-9]+: 0+10 +0 TLS +LOCAL +DEFAULT +7 ld5 @@ -116,7 +116,7 @@ Symbol table '\.symtab' contains 38 entr +[0-9]+: 0+28 +0 TLS +LOCAL +DEFAULT +7 le4 +[0-9]+: 0+30 +0 TLS +LOCAL +DEFAULT +7 le5 +[0-9]+: [0-9a-f]+ +0 NOTYPE +LOCAL +DEFAULT +6 \.__tls_get_addr - +[0-9]+: 0+10700 +0 OBJECT +GLOBAL DEFAULT +ABS _DYNAMIC + +[0-9]+: 0+106c8 +0 OBJECT +GLOBAL DEFAULT +ABS _DYNAMIC +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT +UND gd +[0-9]+: 0+60 +0 TLS +GLOBAL DEFAULT +8 le0 +[0-9]+: 0+ +0 NOTYPE +GLOBAL DEFAULT +UND __tls_get_addr diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-powerpc/tlstocso.g binutils-2.16.91.0.2/ld/testsuite/ld-powerpc/tlstocso.g --- binutils-2.16.91.0.1/ld/testsuite/ld-powerpc/tlstocso.g 2004-05-27 11:26:06.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-powerpc/tlstocso.g 2005-07-20 12:27:28.427006078 -0700 @@ -7,9 +7,9 @@ .*: +file format elf64-powerpc Contents of section \.got: - 10798 00000000 00018798 00000000 00000000 .* - 107a8 00000000 00000000 00000000 00000000 .* - 107b8 00000000 00000000 00000000 00000000 .* - 107c8 00000000 00000000 00000000 00000000 .* - 107d8 00000000 00000000 00000000 00000000 .* - 107e8 00000000 00000000 .* + 10760 00000000 00018760 00000000 00000000 .* + 10770 00000000 00000000 00000000 00000000 .* + 10780 00000000 00000000 00000000 00000000 .* + 10790 00000000 00000000 00000000 00000000 .* + 107a0 00000000 00000000 00000000 00000000 .* + 107b0 00000000 00000000 .* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-powerpc/tlstocso.r binutils-2.16.91.0.2/ld/testsuite/ld-powerpc/tlstocso.r --- binutils-2.16.91.0.1/ld/testsuite/ld-powerpc/tlstocso.r 2005-04-09 12:03:29.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-powerpc/tlstocso.r 2005-07-20 12:27:28.428005913 -0700 @@ -4,7 +4,7 @@ #readelf: -WSsrl #target: powerpc64*-*-* -There are 15 section headers.* +There are 16 section headers.* Section Headers: +\[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al @@ -14,15 +14,16 @@ Section Headers: +\[ 3\] \.dynstr +.* +\[ 4\] \.rela\.dyn +.* +\[ 5\] \.rela\.plt +.* - +\[ 6\] \.text +PROGBITS +0+550 0+550 0+bc 0+ +AX +0 +0 +4 - +\[ 7\] \.tdata +PROGBITS +0+10610 0+610 0+38 0+ WAT +0 +0 +8 - +\[ 8\] \.tbss +NOBITS +0+10648 0+648 0+38 0+ WAT +0 +0 +8 - +\[ 9\] \.dynamic +DYNAMIC +0+10648 0+648 0+150 10 +WA +3 +0 +8 - +\[10\] \.got +PROGBITS +0+10798 0+798 0+58 08 +WA +0 +0 +8 - +\[11\] \.plt +.* - +\[12\] \.shstrtab +.* - +\[13\] \.symtab +.* - +\[14\] \.strtab +.* + +\[ 6\] \.text +PROGBITS +0+518 0+518 0+bc 0+ +AX +0 +0 +4 + +\[ 7\] \.tdata +PROGBITS +0+105d8 0+5d8 0+38 0+ WAT +0 +0 +8 + +\[ 8\] \.tbss +NOBITS +0+10610 0+610 0+38 0+ WAT +0 +0 +8 + +\[ 9\] \.data\.rel\.ro +PROGBITS .* + +\[10\] \.dynamic +DYNAMIC +0+10610 0+610 0+150 10 +WA +3 +0 +8 + +\[11\] \.got +PROGBITS +0+10760 0+760 0+58 08 +WA +0 +0 +8 + +\[12\] \.plt +.* + +\[13\] \.shstrtab +.* + +\[14\] \.symtab +.* + +\[15\] \.strtab +.* #... Elf file type is DYN \(Shared object file\) @@ -31,10 +32,10 @@ There are 4 program headers.* Program Headers: +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align - +LOAD +0x0+ 0x0+ 0x0+ 0x0+60c 0x0+60c R E 0x10000 - +LOAD +0x0+610 0x0+10610 0x0+10610 0x0+1e0 0x0+210 RW +0x10000 - +DYNAMIC +0x0+648 0x0+10648 0x0+10648 0x0+150 0x0+150 RW +0x8 - +TLS +0x0+610 0x0+10610 0x0+10610 0x0+38 0x0+70 R +0x8 + +LOAD +0x0+ 0x0+ 0x0+ 0x0+5d4 0x0+5d4 R E 0x10000 + +LOAD +0x0+5d8 0x0+105d8 0x0+105d8 0x0+1e0 0x0+210 RW +0x10000 + +DYNAMIC +0x0+610 0x0+10610 0x0+10610 0x0+150 0x0+150 RW +0x8 + +TLS +0x0+5d8 0x0+105d8 0x0+105d8 0x0+38 0x0+70 R +0x8 Section to Segment mapping: +Segment Sections\.\.\. @@ -45,32 +46,30 @@ Program Headers: Relocation section '\.rela\.dyn' at offset .* contains 11 entries: +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend -0+5ba +0+90+45 R_PPC64_TPREL16 +0+60 le0 \+ 0 -0+5be +0+c0+48 R_PPC64_TPREL16_HA +0+68 le1 \+ 0 -0+5c2 +0+c0+46 R_PPC64_TPREL16_LO +0+68 le1 \+ 0 -0+107a0 +0+80+44 R_PPC64_DTPMOD64 +0+ gd \+ 0 -0+107a8 +0+80+4e R_PPC64_DTPREL64 +0+ gd \+ 0 -0+107b0 +0+d0+44 R_PPC64_DTPMOD64 +0+ ld \+ 0 -0+107c0 +0+140+44 R_PPC64_DTPMOD64 +0+38 gd0 \+ 0 -0+107c8 +0+140+4e R_PPC64_DTPREL64 +0+38 gd0 \+ 0 -0+107d0 +0+b0+44 R_PPC64_DTPMOD64 +0+40 ld0 \+ 0 -0+107e0 +0+f0+4e R_PPC64_DTPREL64 +0+50 ld2 \+ 0 -0+107e8 +0+150+49 R_PPC64_TPREL64 +0+58 ie0 \+ 0 +[0-9a-f ]+R_PPC64_TPREL16 +0+60 le0 \+ 0 +[0-9a-f ]+R_PPC64_TPREL16_HA +0+68 le1 \+ 0 +[0-9a-f ]+R_PPC64_TPREL16_LO +0+68 le1 \+ 0 +[0-9a-f ]+R_PPC64_DTPMOD64 +0+ gd \+ 0 +[0-9a-f ]+R_PPC64_DTPREL64 +0+ gd \+ 0 +[0-9a-f ]+R_PPC64_DTPMOD64 +0+ ld \+ 0 +[0-9a-f ]+R_PPC64_DTPMOD64 +0+38 gd0 \+ 0 +[0-9a-f ]+R_PPC64_DTPREL64 +0+38 gd0 \+ 0 +[0-9a-f ]+R_PPC64_DTPMOD64 +0+40 ld0 \+ 0 +[0-9a-f ]+R_PPC64_DTPREL64 +0+50 ld2 \+ 0 +[0-9a-f ]+R_PPC64_TPREL64 +0+58 ie0 \+ 0 Relocation section '\.rela\.plt' at offset .* contains 1 entries: +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend -0+10808 +0+a0+15 R_PPC64_JMP_SLOT +0+ __tls_get_addr \+ 0 +[0-9a-f ]+R_PPC64_JMP_SLOT +0+ __tls_get_addr \+ 0 -Symbol table '\.dynsym' contains 22 entries: +Symbol table '\.dynsym' contains 20 entries: +Num: +Value +Size Type +Bind +Vis +Ndx Name +[0-9]+: 0+ +0 NOTYPE +LOCAL +DEFAULT +UND - +[0-9]+: 0+550 +0 SECTION LOCAL +DEFAULT +6 - +[0-9]+: 0+10610 +0 SECTION LOCAL +DEFAULT +7 - +[0-9]+: 0+10648 +0 SECTION LOCAL +DEFAULT +8 - +[0-9]+: 0+ +0 NOTYPE +LOCAL +DEFAULT +UND - +[0-9]+: 0+ +0 NOTYPE +LOCAL +DEFAULT +UND - +[0-9]+: 0+ +0 NOTYPE +LOCAL +DEFAULT +UND - +[0-9]+: 0+10648 +0 OBJECT +GLOBAL DEFAULT +ABS _DYNAMIC + +[0-9]+: 0+518 +0 SECTION LOCAL +DEFAULT +6 + +[0-9]+: 0+105d8 +0 SECTION LOCAL +DEFAULT +7 + +[0-9]+: 0+10610 +0 SECTION LOCAL +DEFAULT +8 + +[0-9]+: 0+10610 +0 SECTION LOCAL +DEFAULT +9 + +[0-9]+: 0+10610 +0 OBJECT +GLOBAL DEFAULT +ABS _DYNAMIC +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT +UND gd +[0-9]+: 0+60 +0 TLS +GLOBAL DEFAULT +8 le0 +[0-9]+: 0+ +0 NOTYPE +GLOBAL DEFAULT +UND __tls_get_addr @@ -86,7 +85,7 @@ Symbol table '\.dynsym' contains 22 entr +[0-9]+: 0+38 +0 TLS +GLOBAL DEFAULT +8 gd0 +[0-9]+: 0+58 +0 TLS +GLOBAL DEFAULT +8 ie0 -Symbol table '\.symtab' contains 39 entries: +Symbol table '\.symtab' contains 40 entries: +Num: +Value +Size Type +Bind +Vis +Ndx Name +[0-9]+: 0+ +0 NOTYPE +LOCAL +DEFAULT +UND +[0-9]+: 0+120 +0 SECTION LOCAL +DEFAULT +1 @@ -94,15 +93,16 @@ Symbol table '\.symtab' contains 39 entr +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +3 +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +4 +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +5 - +[0-9]+: 0+550 +0 SECTION LOCAL +DEFAULT +6 - +[0-9]+: 0+10610 +0 SECTION LOCAL +DEFAULT +7 - +[0-9]+: 0+10648 +0 SECTION LOCAL +DEFAULT +8 + +[0-9]+: 0+518 +0 SECTION LOCAL +DEFAULT +6 + +[0-9]+: 0+105d8 +0 SECTION LOCAL +DEFAULT +7 + +[0-9]+: 0+10610 +0 SECTION LOCAL +DEFAULT +8 +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +9 - +[0-9]+: 0+10798 +0 SECTION LOCAL +DEFAULT +10 - +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +11 + +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +10 + +[0-9]+: 0+10760 +0 SECTION LOCAL +DEFAULT +11 +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +12 +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +13 +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +14 + +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +15 +[0-9]+: 0+ +0 TLS +LOCAL +DEFAULT +7 gd4 +[0-9]+: 0+8 +0 TLS +LOCAL +DEFAULT +7 ld4 +[0-9]+: 0+10 +0 TLS +LOCAL +DEFAULT +7 ld5 @@ -110,9 +110,9 @@ Symbol table '\.symtab' contains 39 entr +[0-9]+: 0+20 +0 TLS +LOCAL +DEFAULT +7 ie4 +[0-9]+: 0+28 +0 TLS +LOCAL +DEFAULT +7 le4 +[0-9]+: 0+30 +0 TLS +LOCAL +DEFAULT +7 le5 - +[0-9]+: [0-9a-f]+ +0 NOTYPE +LOCAL +DEFAULT +10 \.Lie0 + +[0-9]+: [0-9a-f]+ +0 NOTYPE +LOCAL +DEFAULT +11 \.Lie0 +[0-9]+: [0-9a-f]+ +0 NOTYPE +LOCAL +DEFAULT +6 \.__tls_get_addr - +[0-9]+: 0+10648 +0 OBJECT +GLOBAL DEFAULT +ABS _DYNAMIC + +[0-9]+: 0+10610 +0 OBJECT +GLOBAL DEFAULT +ABS _DYNAMIC +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT +UND gd +[0-9]+: 0+60 +0 TLS +GLOBAL DEFAULT +8 le0 +[0-9]+: 0+ +0 NOTYPE +GLOBAL DEFAULT +UND __tls_get_addr diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-x86-64/abs.d binutils-2.16.91.0.2/ld/testsuite/ld-x86-64/abs.d --- binutils-2.16.91.0.1/ld/testsuite/ld-x86-64/abs.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-x86-64/abs.d 2005-07-20 12:27:28.428005913 -0700 @@ -0,0 +1,10 @@ +#name: Absolute non-overflowing relocs +#source: ../ld-i386/abs.s +#source: ../ld-i386/zero.s +#ld: +#objdump: -rs + +.*: file format .* + +Contents of section \.text: +[ ][0-9a-f]+ c800fff0 c8000110 c9c3.* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-x86-64/pcrel16.d binutils-2.16.91.0.2/ld/testsuite/ld-x86-64/pcrel16.d --- binutils-2.16.91.0.1/ld/testsuite/ld-x86-64/pcrel16.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-x86-64/pcrel16.d 2005-07-20 12:27:28.428005913 -0700 @@ -0,0 +1,4 @@ +#name: PCREL16 overflow +#source: ../ld-i386/pcrel16.s +#ld: +#error: .*relocation truncated to fit: R_X86_64_PC16 .* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-x86-64/pcrel8.d binutils-2.16.91.0.2/ld/testsuite/ld-x86-64/pcrel8.d --- binutils-2.16.91.0.1/ld/testsuite/ld-x86-64/pcrel8.d 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-x86-64/pcrel8.d 2005-07-20 12:27:28.429005749 -0700 @@ -0,0 +1,4 @@ +#name: PCREL8 overflow +#source: ../ld-i386/pcrel8.s +#ld: +#error: .*relocation truncated to fit: R_X86_64_PC8 .* diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-x86-64/tlspic.dd binutils-2.16.91.0.2/ld/testsuite/ld-x86-64/tlspic.dd --- binutils-2.16.91.0.1/ld/testsuite/ld-x86-64/tlspic.dd 2004-11-22 12:33:33.000000000 -0800 +++ binutils-2.16.91.0.2/ld/testsuite/ld-x86-64/tlspic.dd 2005-07-20 12:27:28.446002946 -0700 @@ -22,7 +22,7 @@ Disassembly of section .text: # -> R_X86_64_DTPMOD64 sg1 +1010: 66[ ]+data16 +1011: 66[ ]+data16 - +1012: 48 e8 58 f5 ff ff[ ]+rex64 callq [0-9a-f]+ <.*> + +1012: 48 e8 20 f5 ff ff[ ]+rex64 callq [0-9a-f]+ <.*> # -> R_X86_64_JUMP_SLOT __tls_get_addr +1018: 90[ ]+nop * +1019: 90[ ]+nop * @@ -43,7 +43,7 @@ Disassembly of section .text: # -> R_X86_64_DTPMOD64 [0 0x2000000000000000] +1038: 66[ ]+data16 +1039: 66[ ]+data16 - +103a: 48 e8 30 f5 ff ff[ ]+rex64 callq [0-9a-f]+ <.*> + +103a: 48 e8 f8 f4 ff ff[ ]+rex64 callq [0-9a-f]+ <.*> # -> R_X86_64_JUMP_SLOT __tls_get_addr +1040: 90[ ]+nop * +1041: 90[ ]+nop * @@ -64,7 +64,7 @@ Disassembly of section .text: # -> R_X86_64_DTPMOD64 [0 0x4000000000000000] +1060: 66[ ]+data16 +1061: 66[ ]+data16 - +1062: 48 e8 08 f5 ff ff[ ]+rex64 callq [0-9a-f]+ <.*> + +1062: 48 e8 d0 f4 ff ff[ ]+rex64 callq [0-9a-f]+ <.*> # -> R_X86_64_JUMP_SLOT __tls_get_addr +1068: 90[ ]+nop * +1069: 90[ ]+nop * @@ -85,7 +85,7 @@ Disassembly of section .text: # -> R_X86_64_DTPMOD64 [0 0x6000000000000000] +1088: 66[ ]+data16 +1089: 66[ ]+data16 - +108a: 48 e8 e0 f4 ff ff[ ]+rex64 callq [0-9a-f]+ <.*> + +108a: 48 e8 a8 f4 ff ff[ ]+rex64 callq [0-9a-f]+ <.*> # -> R_X86_64_JUMP_SLOT __tls_get_addr +1090: 90[ ]+nop * +1091: 90[ ]+nop * @@ -103,7 +103,7 @@ Disassembly of section .text: # LD +10a8: 48 8d 3d b1 02 10 00[ ]+lea 1049265\(%rip\),%rdi +# 101360 <.*> # -> R_X86_64_DTPMOD64 [0 0x000000000000000] - +10af: e8 bc f4 ff ff[ ]+callq [0-9a-f]+ <.*> + +10af: e8 84 f4 ff ff[ ]+callq [0-9a-f]+ <.*> # -> R_X86_64_JUMP_SLOT __tls_get_addr +10b4: 90[ ]+nop * +10b5: 90[ ]+nop * @@ -118,7 +118,7 @@ Disassembly of section .text: # LD against hidden and local variables +10ca: 48 8d 3d 8f 02 10 00[ ]+lea 1049231\(%rip\),%rdi +# 101360 <.*> # -> R_X86_64_DTPMOD64 [0 0x000000000000000] - +10d1: e8 9a f4 ff ff[ ]+callq [0-9a-f]+ <.*> + +10d1: e8 62 f4 ff ff[ ]+callq [0-9a-f]+ <.*> # -> R_X86_64_JUMP_SLOT __tls_get_addr +10d6: 90[ ]+nop * +10d7: 90[ ]+nop * @@ -133,7 +133,7 @@ Disassembly of section .text: # LD against hidden but not local variables +10ec: 48 8d 3d 6d 02 10 00[ ]+lea 1049197\(%rip\),%rdi +# 101360 <.*> # -> R_X86_64_DTPMOD64 [0 0x000000000000000] - +10f3: e8 78 f4 ff ff[ ]+callq [0-9a-f]+ <.*> + +10f3: e8 40 f4 ff ff[ ]+callq [0-9a-f]+ <.*> # -> R_X86_64_JUMP_SLOT __tls_get_addr +10f8: 90[ ]+nop * +10f9: 90[ ]+nop * diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-x86-64/tlspic.rd binutils-2.16.91.0.2/ld/testsuite/ld-x86-64/tlspic.rd --- binutils-2.16.91.0.1/ld/testsuite/ld-x86-64/tlspic.rd 2005-04-09 12:03:31.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-x86-64/tlspic.rd 2005-07-20 12:27:28.449002451 -0700 @@ -60,23 +60,21 @@ Relocation section '.rela.dyn' at offset 0+1013a8 0+12 R_X86_64_TPOFF64 +0+70 0+1013b8 0+10 R_X86_64_DTPMOD64 +0+ 0+1013c8 0+12 R_X86_64_TPOFF64 +0+44 -0+101388 0+a00000012 R_X86_64_TPOFF64 +0+10 sg5 \+ 0 -0+101390 0+c00000010 R_X86_64_DTPMOD64 +0+ sg1 \+ 0 -0+101398 0+c00000011 R_X86_64_DTPOFF64 +0+ sg1 \+ 0 -0+1013b0 0+f00000012 R_X86_64_TPOFF64 +0+4 sg2 \+ 0 +0+101388 0+800000012 R_X86_64_TPOFF64 +0+10 sg5 \+ 0 +0+101390 0+a00000010 R_X86_64_DTPMOD64 +0+ sg1 \+ 0 +0+101398 0+a00000011 R_X86_64_DTPOFF64 +0+ sg1 \+ 0 +0+1013b0 0+d00000012 R_X86_64_TPOFF64 +0+4 sg2 \+ 0 Relocation section '.rela.plt' at offset 0x[0-9a-f]+ contains 1 entries: +Offset +Info +Type +Symbol's Value Symbol's Name \+ Addend -0+[0-9a-f]+ 0+b00000007 R_X86_64_JUMP_SLOT +0+ __tls_get_addr \+ 0 +0+[0-9a-f]+ 0+900000007 R_X86_64_JUMP_SLOT +0+ __tls_get_addr \+ 0 -Symbol table '.dynsym' contains 20 entries: +Symbol table '.dynsym' contains 18 entries: +Num: +Value +Size Type +Bind +Vis +Ndx Name +[0-9]+: 0+ +0 NOTYPE LOCAL DEFAULT UND * +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL DEFAULT +7 * +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL DEFAULT +8 * +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL DEFAULT +9 * - +[0-9]+: 0+ +0 NOTYPE LOCAL DEFAULT UND * - +[0-9]+: 0+ +0 NOTYPE LOCAL DEFAULT UND * +[0-9]+: 0+1c +0 TLS +GLOBAL DEFAULT +8 sg8 +[0-9]+: 0+101210 +0 OBJECT GLOBAL DEFAULT ABS _DYNAMIC +[0-9]+: 0+8 +0 TLS +GLOBAL DEFAULT +8 sg3 diff -uprN binutils-2.16.91.0.1/ld/testsuite/ld-x86-64/x86-64.exp binutils-2.16.91.0.2/ld/testsuite/ld-x86-64/x86-64.exp --- binutils-2.16.91.0.1/ld/testsuite/ld-x86-64/x86-64.exp 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/ld-x86-64/x86-64.exp 2005-07-20 12:27:28.450002286 -0700 @@ -52,3 +52,7 @@ set x86_64tests { } run_ld_link_tests $x86_64tests + +run_dump_test "abs" +run_dump_test "pcrel8" +run_dump_test "pcrel16" diff -uprN binutils-2.16.91.0.1/ld/testsuite/lib/ld-lib.exp binutils-2.16.91.0.2/ld/testsuite/lib/ld-lib.exp --- binutils-2.16.91.0.1/ld/testsuite/lib/ld-lib.exp 2005-06-22 13:53:35.000000000 -0700 +++ binutils-2.16.91.0.2/ld/testsuite/lib/ld-lib.exp 2005-07-20 12:27:28.451002121 -0700 @@ -1262,3 +1262,86 @@ if ![string length [info proc prune_warn return $text } } + +# List contains test-items with 3 items followed by 1 lists, 2 items +# and one optional item: +# 0:name +# 1:ld options +# 2:assembler options +# 3:filenames of assembler files +# 4:name of output file +# 5:expected output +# 6:compiler flags (optional) + +proc run_ld_link_exec_tests { ldtests } { + global ld + global as + global srcdir + global subdir + global env + global CC + global CFLAGS + global errcnt + + foreach testitem $ldtests { + set testname [lindex $testitem 0] + set ld_options [lindex $testitem 1] + set as_options [lindex $testitem 2] + set src_files [lindex $testitem 3] + set binfile tmpdir/[lindex $testitem 4] + set expfile [lindex $testitem 5] + set cflags [lindex $testitem 6] + set objfiles {} + set failed 0 + +# verbose -log "Testname is $testname" +# verbose -log "ld_options is $ld_options" +# verbose -log "as_options is $as_options" +# verbose -log "src_files is $src_files" +# verbose -log "actions is $actions" +# verbose -log "binfile is $binfile" + + # Assemble each file in the test. + foreach src_file $src_files { + set objfile "tmpdir/[file rootname $src_file].o" + lappend objfiles $objfile + + # We ignore warnings since some compilers may generate + # incorrect section attributes and the assembler will warn + # them. + ld_compile "$CC -c $CFLAGS $cflags" $srcdir/$subdir/$src_file $objfile + + if ![ld_link $ld $binfile "-L$srcdir/$subdir $ld_options $objfiles"] { + set failed 1 + } else { + set failed 0 + send_log "Running: $binfile > $binfile.out\n" + verbose "Running: $binfile > $binfile.out" + catch "exec $binfile > $binfile.out" exec_output + + if ![string match "" $exec_output] then { + send_log "$exec_output\n" + verbose "$exec_output" 1 + set failed 1 + } else { + send_log "diff $binfile.out $srcdir/$subdir/$expfile\n" + verbose "diff $binfile.out $srcdir/$subdir/$expfile" + catch "exec diff $binfile.out $srcdir/$subdir/$expfile" exec_output + set exec_output [prune_warnings $exec_output] + + if ![string match "" $exec_output] then { + send_log "$exec_output\n" + verbose "$exec_output" 1 + set failed 1 + } + } + + if { $failed != 0 } { + fail $testname + } else { + set errcnt 0 + pass $testname + } } + } + } +} diff -uprN binutils-2.16.91.0.1/libiberty/ChangeLog binutils-2.16.91.0.2/libiberty/ChangeLog --- binutils-2.16.91.0.1/libiberty/ChangeLog 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/libiberty/ChangeLog 2005-07-20 12:27:28.460000638 -0700 @@ -1,3 +1,45 @@ +2005-07-15 Ben Elliston + + * regex.c (TRANSLATE): Cast rhs of ternary expression to char. + +2005-07-12 Ben Elliston + + * floatformat.c (floatformat_to_double): Add a comment about a + potential source of warnings when compiling this file. + +2005-07-12 Ben Elliston + + * pexecute.c (pexecute): Cast string litrals to char *. + * regex.c (re_comp): Cast a call to gettext() to char *. + +2005-07-07 Kelley Cook + + * config.table: Delete file. Move former contents into ... + * configure.ac: ... here and escape any brackets for m4. + * Makefile.in (config.status): Remove dependency on config.table. + * configure: Regenerate. + +2005-07-07 Kelley Cook + + * config.in: Regenerate for 6/20 change. + +2005-07-03 Steve Ellcey + + PR other/13906 + * md5.c (md5_process_bytes): Check alignment. + +2005-07-01 Ian Lance Taylor + + PR other/22268 + * cp-demangle.c (d_expr_primary): Don't run off the end of the + string while looking for the end of a literal value. + * testsuite/demangle-expected: Add test case. + +2005-06-30 Daniel Berlin + + * hashtab.c (EMPTY_ENTRY): Moved and renamed. + (DELETED_ENTRY): Ditto. + 2005-06-20 Geoffrey Keating * strverscmp.c: New. diff -uprN binutils-2.16.91.0.1/libiberty/config.in binutils-2.16.91.0.2/libiberty/config.in --- binutils-2.16.91.0.1/libiberty/config.in 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/libiberty/config.in 2005-07-20 12:27:28.462000308 -0700 @@ -72,6 +72,10 @@ don't. */ #undef HAVE_DECL_SNPRINTF +/* Define to 1 if you have the declaration of `strverscmp', and to 0 if you + don't. */ +#undef HAVE_DECL_STRVERSCMP + /* Define to 1 if you have the declaration of `vasprintf', and to 0 if you don't. */ #undef HAVE_DECL_VASPRINTF @@ -245,6 +249,9 @@ /* Define to 1 if you have the `strtoul' function. */ #undef HAVE_STRTOUL +/* Define to 1 if you have the `strverscmp' function. */ +#undef HAVE_STRVERSCMP + /* Define to 1 if you have the `sysconf' function. */ #undef HAVE_SYSCONF diff -uprN binutils-2.16.91.0.1/libiberty/config.table binutils-2.16.91.0.2/libiberty/config.table --- binutils-2.16.91.0.1/libiberty/config.table 2005-04-09 12:03:31.000000000 -0700 +++ binutils-2.16.91.0.2/libiberty/config.table 1969-12-31 16:00:00.000000000 -0800 @@ -1,68 +0,0 @@ -# Don't build the shared library for build. -if [ -n "${with_build_subdir}" ]; then - enable_shared=no -fi - -frag= -case "${host}" in - rs6000-ibm-aix3.1 | rs6000-ibm-aix) - frag=mh-aix ;; - *-*-cxux7*) frag=mh-cxux7 ;; - *-*-freebsd2.1.*) frag=mh-fbsd21 ;; - *-*-freebsd2.2.[012]) frag=mh-fbsd21 ;; - i370-*-opened*) frag=mh-openedition ;; - i[34567]86-*-windows*) frag=mh-windows ;; -esac - -if [ -n "${frag}" ]; then - frags=${libiberty_topdir}/libiberty/config/$frag -else - frags= -fi - -# If they didn't specify --enable-shared, don't generate shared libs. -case "${enable_shared}" in - yes) shared=yes ;; - no) shared=no ;; - "") shared=no ;; - *) shared=yes ;; -esac -if [ "${shared}" = "yes" ]; then - frag= - case "${host}" in - *-*-cygwin*) ;; - alpha*-*-linux*) frag=mh-elfalphapic ;; - arm*-*-*) frag=mh-armpic ;; - hppa*-*-*) frag=mh-papic ;; - i[34567]86-*-* | x86_64-*-*) - frag=mh-x86pic ;; - powerpc*-*-aix*) ;; - powerpc*-*-*) frag=mh-ppcpic ;; - sparc*-*-*) frag=mh-sparcpic ;; - s390*-*-*) frag=mh-s390pic ;; - *) frag=mh-${host_cpu}pic ;; - esac - if [ -n "${frag}" ]; then - frags="${frags} ${libiberty_topdir}/config/${frag}" - fi -fi - -echo "# Warning: this fragment is automatically generated" > temp-frag - -for frag in ${frags}; do - if [ -f ${frag} ]; then - echo "Appending ${frag} to xhost-mkfrag" - echo "# Following fragment copied from ${frag}" >> temp-frag - cat ${frag} >> temp-frag - fi -done - -# record if we want to build shared libs. -if [ "${shared}" = "yes" ]; then - echo enable_shared = yes >> temp-frag -else - echo enable_shared = no >> temp-frag -fi - -frag=xhost-mkfrag -${CONFIG_SHELL-/bin/sh} ${libiberty_topdir}/move-if-change temp-frag xhost-mkfrag diff -uprN binutils-2.16.91.0.1/libiberty/configure binutils-2.16.91.0.2/libiberty/configure --- binutils-2.16.91.0.1/libiberty/configure 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/libiberty/configure 2005-07-20 12:27:28.498994208 -0700 @@ -3529,7 +3529,75 @@ test -z "$INSTALL_SCRIPT" && INSTALL_SCR test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' -. ${srcdir}/config.table +# Don't build the shared library for build. +if [ -n "${with_build_subdir}" ]; then + enable_shared=no +fi + +frag= +case "${host}" in + rs6000-ibm-aix3.1 | rs6000-ibm-aix) + frag=mh-aix ;; + *-*-cxux7*) frag=mh-cxux7 ;; + *-*-freebsd2.1.*) frag=mh-fbsd21 ;; + *-*-freebsd2.2.[012]) frag=mh-fbsd21 ;; + i370-*-opened*) frag=mh-openedition ;; + i[34567]86-*-windows*) frag=mh-windows ;; +esac + +if [ -n "${frag}" ]; then + frags=${libiberty_topdir}/libiberty/config/$frag +else + frags= +fi + +# If they didn't specify --enable-shared, don't generate shared libs. +case "${enable_shared}" in + yes) shared=yes ;; + no) shared=no ;; + "") shared=no ;; + *) shared=yes ;; +esac +if [ "${shared}" = "yes" ]; then + frag= + case "${host}" in + *-*-cygwin*) ;; + alpha*-*-linux*) frag=mh-elfalphapic ;; + arm*-*-*) frag=mh-armpic ;; + hppa*-*-*) frag=mh-papic ;; + i[34567]86-*-* | x86_64-*-*) + frag=mh-x86pic ;; + powerpc*-*-aix*) ;; + powerpc*-*-*) frag=mh-ppcpic ;; + sparc*-*-*) frag=mh-sparcpic ;; + s390*-*-*) frag=mh-s390pic ;; + *) frag=mh-${host_cpu}pic ;; + esac + if [ -n "${frag}" ]; then + frags="${frags} ${libiberty_topdir}/config/${frag}" + fi +fi + +echo "# Warning: this fragment is automatically generated" > temp-frag + +for frag in ${frags}; do + if [ -f ${frag} ]; then + echo "Appending ${frag} to xhost-mkfrag" + echo "# Following fragment copied from ${frag}" >> temp-frag + cat ${frag} >> temp-frag + fi +done + +# record if we want to build shared libs. +if [ "${shared}" = "yes" ]; then + echo enable_shared = yes >> temp-frag +else + echo enable_shared = no >> temp-frag +fi + +frag=xhost-mkfrag +${CONFIG_SHELL-/bin/sh} ${libiberty_topdir}/move-if-change temp-frag xhost-mkfrag + host_makefile_frag=${frag} diff -uprN binutils-2.16.91.0.1/libiberty/configure.ac binutils-2.16.91.0.2/libiberty/configure.ac --- binutils-2.16.91.0.1/libiberty/configure.ac 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/libiberty/configure.ac 2005-07-20 12:27:28.499994043 -0700 @@ -152,7 +152,75 @@ dnl When we start using automake: dnl AM_PROG_INSTALL AC_PROG_INSTALL -. ${srcdir}/config.table +# Don't build the shared library for build. +if [[ -n "${with_build_subdir}" ]]; then + enable_shared=no +fi + +frag= +case "${host}" in + rs6000-ibm-aix3.1 | rs6000-ibm-aix) + frag=mh-aix ;; + *-*-cxux7*) frag=mh-cxux7 ;; + *-*-freebsd2.1.*) frag=mh-fbsd21 ;; + *-*-freebsd2.2.[[012]]) frag=mh-fbsd21 ;; + i370-*-opened*) frag=mh-openedition ;; + i[[34567]]86-*-windows*) frag=mh-windows ;; +esac + +if [[ -n "${frag}" ]]; then + frags=${libiberty_topdir}/libiberty/config/$frag +else + frags= +fi + +# If they didn't specify --enable-shared, don't generate shared libs. +case "${enable_shared}" in + yes) shared=yes ;; + no) shared=no ;; + "") shared=no ;; + *) shared=yes ;; +esac +if [[ "${shared}" = "yes" ]]; then + frag= + case "${host}" in + *-*-cygwin*) ;; + alpha*-*-linux*) frag=mh-elfalphapic ;; + arm*-*-*) frag=mh-armpic ;; + hppa*-*-*) frag=mh-papic ;; + i[[34567]]86-*-* | x86_64-*-*) + frag=mh-x86pic ;; + powerpc*-*-aix*) ;; + powerpc*-*-*) frag=mh-ppcpic ;; + sparc*-*-*) frag=mh-sparcpic ;; + s390*-*-*) frag=mh-s390pic ;; + *) frag=mh-${host_cpu}pic ;; + esac + if [[ -n "${frag}" ]]; then + frags="${frags} ${libiberty_topdir}/config/${frag}" + fi +fi + +echo "# Warning: this fragment is automatically generated" > temp-frag + +for frag in ${frags}; do + if [[ -f ${frag} ]]; then + echo "Appending ${frag} to xhost-mkfrag" + echo "# Following fragment copied from ${frag}" >> temp-frag + cat ${frag} >> temp-frag + fi +done + +# record if we want to build shared libs. +if [[ "${shared}" = "yes" ]]; then + echo enable_shared = yes >> temp-frag +else + echo enable_shared = no >> temp-frag +fi + +frag=xhost-mkfrag +${CONFIG_SHELL-/bin/sh} ${libiberty_topdir}/move-if-change temp-frag xhost-mkfrag + host_makefile_frag=${frag} AC_SUBST_FILE(host_makefile_frag) diff -uprN binutils-2.16.91.0.1/libiberty/cp-demangle.c binutils-2.16.91.0.2/libiberty/cp-demangle.c --- binutils-2.16.91.0.1/libiberty/cp-demangle.c 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/libiberty/cp-demangle.c 2005-07-20 12:27:28.503993383 -0700 @@ -2337,7 +2337,11 @@ d_expr_primary (struct d_info *di) } s = d_str (di); while (d_peek_char (di) != 'E') - d_advance (di, 1); + { + if (d_peek_char (di) == '\0') + return NULL; + d_advance (di, 1); + } ret = d_make_comp (di, t, type, d_make_name (di, s, d_str (di) - s)); } if (d_next_char (di) != 'E') diff -uprN binutils-2.16.91.0.1/libiberty/floatformat.c binutils-2.16.91.0.2/libiberty/floatformat.c --- binutils-2.16.91.0.1/libiberty/floatformat.c 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/libiberty/floatformat.c 2005-07-20 12:27:28.505993053 -0700 @@ -306,6 +306,13 @@ floatformat_to_double (const struct floa mant_bits_left -= mant_bits; } + /* On certain systems (such as GNU/Linux), the use of the + INFINITY macro below may generate a warning that can not be + silenced due to a bug in GCC (PR preprocessor/11931). The + preprocessor fails to recognise the __extension__ keyword in + conjunction with the GNU/C99 extension for hexadecimal + floating point constants and will issue a warning when + compiling with -pedantic. */ if (nan) dto = NAN; else diff -uprN binutils-2.16.91.0.1/libiberty/hashtab.c binutils-2.16.91.0.2/libiberty/hashtab.c --- binutils-2.16.91.0.1/libiberty/hashtab.c 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/libiberty/hashtab.c 2005-07-20 12:27:28.506992889 -0700 @@ -64,15 +64,6 @@ Boston, MA 02110-1301, USA. */ #define CHAR_BIT 8 #endif -/* This macro defines reserved value for empty table entry. */ - -#define EMPTY_ENTRY ((PTR) 0) - -/* This macro defines reserved value for table entry which contained - a deleted element. */ - -#define DELETED_ENTRY ((PTR) 1) - static unsigned int higher_prime_index (unsigned long); static hashval_t htab_mod_1 (hashval_t, hashval_t, hashval_t, int); static hashval_t htab_mod (hashval_t, htab_t); @@ -290,7 +281,7 @@ htab_mod_m2 (hashval_t hash, htab_t htab /* This function creates table with length slightly longer than given source length. Created hash table is initiated as empty (all the - hash table entries are EMPTY_ENTRY). The function returns the + hash table entries are HTAB_EMPTY_ENTRY). The function returns the created hash table, or NULL if memory allocation fails. */ htab_t @@ -401,7 +392,7 @@ htab_delete (htab_t htab) if (htab->del_f) for (i = size - 1; i >= 0; i--) - if (entries[i] != EMPTY_ENTRY && entries[i] != DELETED_ENTRY) + if (entries[i] != HTAB_EMPTY_ENTRY && entries[i] != HTAB_DELETED_ENTRY) (*htab->del_f) (entries[i]); if (htab->free_f != NULL) @@ -427,7 +418,7 @@ htab_empty (htab_t htab) if (htab->del_f) for (i = size - 1; i >= 0; i--) - if (entries[i] != EMPTY_ENTRY && entries[i] != DELETED_ENTRY) + if (entries[i] != HTAB_EMPTY_ENTRY && entries[i] != HTAB_DELETED_ENTRY) (*htab->del_f) (entries[i]); memset (entries, 0, size * sizeof (PTR)); @@ -448,9 +439,9 @@ find_empty_slot_for_expand (htab_t htab, PTR *slot = htab->entries + index; hashval_t hash2; - if (*slot == EMPTY_ENTRY) + if (*slot == HTAB_EMPTY_ENTRY) return slot; - else if (*slot == DELETED_ENTRY) + else if (*slot == HTAB_DELETED_ENTRY) abort (); hash2 = htab_mod_m2 (hash, htab); @@ -461,9 +452,9 @@ find_empty_slot_for_expand (htab_t htab, index -= size; slot = htab->entries + index; - if (*slot == EMPTY_ENTRY) + if (*slot == HTAB_EMPTY_ENTRY) return slot; - else if (*slot == DELETED_ENTRY) + else if (*slot == HTAB_DELETED_ENTRY) abort (); } } @@ -523,7 +514,7 @@ htab_expand (htab_t htab) { PTR x = *p; - if (x != EMPTY_ENTRY && x != DELETED_ENTRY) + if (x != HTAB_EMPTY_ENTRY && x != HTAB_DELETED_ENTRY) { PTR *q = find_empty_slot_for_expand (htab, (*htab->hash_f) (x)); @@ -556,8 +547,8 @@ htab_find_with_hash (htab_t htab, const index = htab_mod (hash, htab); entry = htab->entries[index]; - if (entry == EMPTY_ENTRY - || (entry != DELETED_ENTRY && (*htab->eq_f) (entry, element))) + if (entry == HTAB_EMPTY_ENTRY + || (entry != HTAB_DELETED_ENTRY && (*htab->eq_f) (entry, element))) return entry; hash2 = htab_mod_m2 (hash, htab); @@ -569,8 +560,8 @@ htab_find_with_hash (htab_t htab, const index -= size; entry = htab->entries[index]; - if (entry == EMPTY_ENTRY - || (entry != DELETED_ENTRY && (*htab->eq_f) (entry, element))) + if (entry == HTAB_EMPTY_ENTRY + || (entry != HTAB_DELETED_ENTRY && (*htab->eq_f) (entry, element))) return entry; } } @@ -615,9 +606,9 @@ htab_find_slot_with_hash (htab_t htab, c first_deleted_slot = NULL; entry = htab->entries[index]; - if (entry == EMPTY_ENTRY) + if (entry == HTAB_EMPTY_ENTRY) goto empty_entry; - else if (entry == DELETED_ENTRY) + else if (entry == HTAB_DELETED_ENTRY) first_deleted_slot = &htab->entries[index]; else if ((*htab->eq_f) (entry, element)) return &htab->entries[index]; @@ -631,9 +622,9 @@ htab_find_slot_with_hash (htab_t htab, c index -= size; entry = htab->entries[index]; - if (entry == EMPTY_ENTRY) + if (entry == HTAB_EMPTY_ENTRY) goto empty_entry; - else if (entry == DELETED_ENTRY) + else if (entry == HTAB_DELETED_ENTRY) { if (!first_deleted_slot) first_deleted_slot = &htab->entries[index]; @@ -649,7 +640,7 @@ htab_find_slot_with_hash (htab_t htab, c if (first_deleted_slot) { htab->n_deleted--; - *first_deleted_slot = EMPTY_ENTRY; + *first_deleted_slot = HTAB_EMPTY_ENTRY; return first_deleted_slot; } @@ -688,13 +679,13 @@ htab_remove_elt_with_hash (htab_t htab, PTR *slot; slot = htab_find_slot_with_hash (htab, element, hash, NO_INSERT); - if (*slot == EMPTY_ENTRY) + if (*slot == HTAB_EMPTY_ENTRY) return; if (htab->del_f) (*htab->del_f) (*slot); - *slot = DELETED_ENTRY; + *slot = HTAB_DELETED_ENTRY; htab->n_deleted++; } @@ -706,13 +697,13 @@ void htab_clear_slot (htab_t htab, PTR *slot) { if (slot < htab->entries || slot >= htab->entries + htab_size (htab) - || *slot == EMPTY_ENTRY || *slot == DELETED_ENTRY) + || *slot == HTAB_EMPTY_ENTRY || *slot == HTAB_DELETED_ENTRY) abort (); if (htab->del_f) (*htab->del_f) (*slot); - *slot = DELETED_ENTRY; + *slot = HTAB_DELETED_ENTRY; htab->n_deleted++; } @@ -726,7 +717,7 @@ htab_traverse_noresize (htab_t htab, hta { PTR *slot; PTR *limit; - + slot = htab->entries; limit = slot + htab_size (htab); @@ -734,7 +725,7 @@ htab_traverse_noresize (htab_t htab, hta { PTR x = *slot; - if (x != EMPTY_ENTRY && x != DELETED_ENTRY) + if (x != HTAB_EMPTY_ENTRY && x != HTAB_DELETED_ENTRY) if (!(*callback) (slot, info)) break; } diff -uprN binutils-2.16.91.0.1/libiberty/Makefile.in binutils-2.16.91.0.2/libiberty/Makefile.in --- binutils-2.16.91.0.1/libiberty/Makefile.in 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/libiberty/Makefile.in 2005-07-20 12:27:28.461000473 -0700 @@ -402,7 +402,7 @@ config.h: stamp-h ; @true stamp-h: $(srcdir)/config.in config.status Makefile CONFIG_FILES= CONFIG_HEADERS=config.h:$(srcdir)/config.in $(SHELL) ./config.status -config.status: $(srcdir)/configure $(srcdir)/config.table +config.status: $(srcdir)/configure $(SHELL) ./config.status --recheck # Depending on config.h makes sure that config.status has been re-run diff -uprN binutils-2.16.91.0.1/libiberty/md5.c binutils-2.16.91.0.2/libiberty/md5.c --- binutils-2.16.91.0.1/libiberty/md5.c 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/libiberty/md5.c 2005-07-20 12:27:28.507992724 -0700 @@ -223,6 +223,23 @@ md5_process_bytes (const void *buffer, s /* Process available complete blocks. */ if (len > 64) { +#if !_STRING_ARCH_unaligned +/* To check alignment gcc has an appropriate operator. Other + compilers don't. */ +# if __GNUC__ >= 2 +# define UNALIGNED_P(p) (((md5_uintptr) p) % __alignof__ (md5_uint32) != 0) +# else +# define UNALIGNED_P(p) (((md5_uintptr) p) % sizeof (md5_uint32) != 0) +# endif + if (UNALIGNED_P (buffer)) + while (len > 64) + { + md5_process_block (memcpy (ctx->buffer, buffer, 64), 64, ctx); + buffer = (const char *) buffer + 64; + len -= 64; + } + else +#endif md5_process_block (buffer, len & ~63, ctx); buffer = (const void *) ((const char *) buffer + (len & ~63)); len &= 63; diff -uprN binutils-2.16.91.0.1/libiberty/pexecute.c binutils-2.16.91.0.2/libiberty/pexecute.c --- binutils-2.16.91.0.1/libiberty/pexecute.c 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/libiberty/pexecute.c 2005-07-20 12:27:28.508992559 -0700 @@ -47,7 +47,7 @@ pexecute (const char *program, char * co { if (pex != NULL) { - *errmsg_fmt = "pexecute already in progress"; + *errmsg_fmt = (char *) "pexecute already in progress"; *errmsg_arg = NULL; return -1; } @@ -58,7 +58,7 @@ pexecute (const char *program, char * co { if (pex == NULL) { - *errmsg_fmt = "pexecute not in progress"; + *errmsg_fmt = (char *) "pexecute not in progress"; *errmsg_arg = NULL; return -1; } diff -uprN binutils-2.16.91.0.1/libiberty/regex.c binutils-2.16.91.0.2/libiberty/regex.c --- binutils-2.16.91.0.1/libiberty/regex.c 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/libiberty/regex.c 2005-07-20 12:27:28.520990580 -0700 @@ -2,7 +2,9 @@ version 0.12. (Implements POSIX draft P1003.2/D11.2, except for some of the internationalization features.) - Copyright (C) 1993-1999, 2000, 2001, 2002 Free Software Foundation, Inc. + + Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, + 2002, 2005 Free Software Foundation, Inc. This file is part of the GNU C Library. The GNU C Library is free software; you can redistribute it and/or @@ -1918,7 +1920,7 @@ static reg_errcode_t byte_compile_range ? (char) translate[(unsigned char) (d)] : (d)) # else /* BYTE */ # define TRANSLATE(d) \ - (translate ? (char) translate[(unsigned char) (d)] : (d)) + (translate ? (char) translate[(unsigned char) (d)] : (char) (d)) # endif /* WCHAR */ # endif @@ -7814,7 +7816,7 @@ re_comp (const char *s) if (!s) { if (!re_comp_buf.buffer) - return gettext ("No previous regular expression"); + return (char *) gettext ("No previous regular expression"); return 0; } diff -uprN binutils-2.16.91.0.1/libiberty/testsuite/demangle-expected binutils-2.16.91.0.2/libiberty/testsuite/demangle-expected --- binutils-2.16.91.0.1/libiberty/testsuite/demangle-expected 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/libiberty/testsuite/demangle-expected 2005-07-20 12:27:28.524989921 -0700 @@ -3704,6 +3704,12 @@ foo _ZN13PatternDriver23StringScalarDeleteValueC1ERKNS_25ConflateStringScalarValueERKNS_25AbstractStringScalarValueERKNS_12TemplateEnumINS_12pdcomplementELZNS_16complement_namesEELZNS_14COMPLEMENTENUMEEEE _ZN13PatternDriver23StringScalarDeleteValueC1ERKNS_25ConflateStringScalarValueERKNS_25AbstractStringScalarValueERKNS_12TemplateEnumINS_12pdcomplementELZNS_16complement_namesEELZNS_14COMPLEMENTENUMEEEE PatternDriver::StringScalarDeleteValue::StringScalarDeleteValue +# +# This used to cause the demangler to walk into undefined memory--PR 22268 +--format=gnu-v3 --no-params +ALsetchannels +ALsetchannels +ALsetchannels # Test GNU V3 constructor and destructor identification. # 0 means it is not a constructor/destructor. # Other integers correspond to enum gnu_v3_{c,d}tor_kinds in demangle.h. diff -uprN binutils-2.16.91.0.1/libtool.m4 binutils-2.16.91.0.2/libtool.m4 --- binutils-2.16.91.0.1/libtool.m4 2004-07-27 21:36:06.000000000 -0700 +++ binutils-2.16.91.0.2/libtool.m4 2005-07-20 12:27:26.839267895 -0700 @@ -15,7 +15,7 @@ ## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software -## Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +## Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ## ## As a special exception to the GNU General Public License, if you ## distribute this file as part of a program that contains a diff -uprN binutils-2.16.91.0.1/ltcf-c.sh binutils-2.16.91.0.2/ltcf-c.sh --- binutils-2.16.91.0.1/ltcf-c.sh 2004-11-22 12:33:30.000000000 -0800 +++ binutils-2.16.91.0.2/ltcf-c.sh 2005-07-20 12:27:26.846266741 -0700 @@ -17,7 +17,7 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. # # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a diff -uprN binutils-2.16.91.0.1/ltcf-cxx.sh binutils-2.16.91.0.2/ltcf-cxx.sh --- binutils-2.16.91.0.1/ltcf-cxx.sh 2004-11-22 12:33:30.000000000 -0800 +++ binutils-2.16.91.0.2/ltcf-cxx.sh 2005-07-20 12:27:26.847266576 -0700 @@ -22,7 +22,7 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. # # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a diff -uprN binutils-2.16.91.0.1/ltcf-gcj.sh binutils-2.16.91.0.2/ltcf-gcj.sh --- binutils-2.16.91.0.1/ltcf-gcj.sh 2004-07-27 21:36:06.000000000 -0700 +++ binutils-2.16.91.0.2/ltcf-gcj.sh 2005-07-20 12:27:26.853265587 -0700 @@ -20,7 +20,7 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. # # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a diff -uprN binutils-2.16.91.0.1/ltconfig binutils-2.16.91.0.2/ltconfig --- binutils-2.16.91.0.1/ltconfig 2004-11-22 12:33:30.000000000 -0800 +++ binutils-2.16.91.0.2/ltconfig 2005-07-20 12:27:26.861264268 -0700 @@ -17,7 +17,7 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. # # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a @@ -2211,7 +2211,7 @@ case $ltmain in # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. # # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a @@ -2635,7 +2635,7 @@ EOF # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. # */ # # #include /* for printf() */ diff -uprN binutils-2.16.91.0.1/ltmain.sh binutils-2.16.91.0.2/ltmain.sh --- binutils-2.16.91.0.1/ltmain.sh 2005-04-09 12:02:55.000000000 -0700 +++ binutils-2.16.91.0.2/ltmain.sh 2005-07-20 12:27:26.870262784 -0700 @@ -17,7 +17,7 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. # # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a diff -uprN binutils-2.16.91.0.1/MAINTAINERS binutils-2.16.91.0.2/MAINTAINERS --- binutils-2.16.91.0.1/MAINTAINERS 2005-04-09 12:02:55.000000000 -0700 +++ binutils-2.16.91.0.2/MAINTAINERS 2005-07-20 12:27:26.537317686 -0700 @@ -32,10 +32,6 @@ config.guess; config.sub; readline/suppo binutils@sources.redhat.com gdb-patches@sources.redhat.com -dejagnu/ - dejagnu: http://www.gnu.org/software/dejagnu/ - Patches to bug-dejagnu@gnu.org - depcomp Send bug reports and patches to bug-automake@gnu.org. diff -uprN binutils-2.16.91.0.1/Makefile.def binutils-2.16.91.0.2/Makefile.def --- binutils-2.16.91.0.1/Makefile.def 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/Makefile.def 2005-07-20 12:27:26.538317521 -0700 @@ -18,7 +18,7 @@ AutoGen definitions Makefile.tpl; // // You should have received a copy of the GNU General Public License // along with this program; if not, write to the Free Software -// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. // "missing" indicates that that module doesn't supply @@ -115,6 +115,7 @@ host_modules= { module= gnattools; }; target_modules = { module= libstdc++-v3; lib_path=.libs; raw_cxx=true; }; target_modules = { module= libmudflap; lib_path=.libs; }; +target_modules = { module= libssp; lib_path=.libs; }; target_modules = { module= newlib; }; target_modules = { module= libgfortran; }; target_modules = { module= libobjc; }; @@ -186,6 +187,7 @@ flags_to_pass = { flag= target_alias ; } // Build tools flags_to_pass = { flag= BISON ; }; flags_to_pass = { flag= CC_FOR_BUILD ; }; +flags_to_pass = { flag= CFLAGS_FOR_BUILD ; }; flags_to_pass = { flag= CXX_FOR_BUILD ; }; flags_to_pass = { flag= EXPECT ; }; flags_to_pass = { flag= FLEX ; }; @@ -473,6 +475,7 @@ bootstrap_stage = { stage_configure_flags="@stage2_werror_flag@" ; stage_make_flags='CFLAGS="$(BOOT_CFLAGS) -fprofile-generate"' ; }; bootstrap_stage = { - id=feedback ; prev=1 ; + id=feedback ; prev=profile ; + bootstrap_target=profiledbootstrap ; stage_configure_flags="@stage2_werror_flag@" ; stage_make_flags='CFLAGS="$(BOOT_CFLAGS) -fprofile-use"' ; }; diff -uprN binutils-2.16.91.0.1/Makefile.in binutils-2.16.91.0.2/Makefile.in --- binutils-2.16.91.0.1/Makefile.in 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/Makefile.in 2005-07-20 12:27:26.591308783 -0700 @@ -17,7 +17,7 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. # # ------------------------------- @@ -480,7 +480,7 @@ PICFLAG_FOR_TARGET = # This is the list of directories that may be needed in RPATH_ENVVAR # so that prorgams built for the target machine work. -TARGET_LIB_PATH = $(TARGET_LIB_PATH_libstdc++-v3)$(TARGET_LIB_PATH_libmudflap)$(HOST_LIB_PATH_gcc) +TARGET_LIB_PATH = $(TARGET_LIB_PATH_libstdc++-v3)$(TARGET_LIB_PATH_libmudflap)$(TARGET_LIB_PATH_libssp)$(HOST_LIB_PATH_gcc) @if target-libstdc++-v3 TARGET_LIB_PATH_libstdc++-v3 = $$r/$(TARGET_SUBDIR)/libstdc++-v3/.libs: @@ -490,6 +490,10 @@ TARGET_LIB_PATH_libstdc++-v3 = $$r/$(TAR TARGET_LIB_PATH_libmudflap = $$r/$(TARGET_SUBDIR)/libmudflap/.libs: @endif target-libmudflap +@if target-libssp +TARGET_LIB_PATH_libssp = $$r/$(TARGET_SUBDIR)/libssp/.libs: +@endif target-libssp + # This is the list of directories that may be needed in RPATH_ENVVAR @@ -538,6 +542,7 @@ BASE_FLAGS_TO_PASS = \ "target_alias=$(target_alias)" \ "BISON=$(BISON)" \ "CC_FOR_BUILD=$(CC_FOR_BUILD)" \ + "CFLAGS_FOR_BUILD=$(CFLAGS_FOR_BUILD)" \ "CXX_FOR_BUILD=$(CXX_FOR_BUILD)" \ "EXPECT=$(EXPECT)" \ "FLEX=$(FLEX)" \ @@ -645,7 +650,6 @@ EXTRA_GCC_FLAGS = \ 'BUILD_PREFIX=$(BUILD_PREFIX)' \ 'BUILD_PREFIX_1=$(BUILD_PREFIX_1)' \ "GCC_FOR_TARGET=$(GCC_FOR_TARGET)" \ - "CFLAGS_FOR_BUILD=$(CFLAGS_FOR_BUILD)" \ "`echo 'LANGUAGES=$(LANGUAGES)' | sed -e s'/[^=][^=]*=$$/XFOO=/'`" \ "`echo 'STMP_FIXPROTO=$(STMP_FIXPROTO)' | sed -e s'/[^=][^=]*=$$/XFOO=/'`" \ "`echo 'LIMITS_H_TEST=$(LIMITS_H_TEST)' | sed -e s'/[^=][^=]*=$$/XFOO=/'`" \ @@ -731,6 +735,7 @@ configure-host: \ configure-target: \ maybe-configure-target-libstdc++-v3 \ maybe-configure-target-libmudflap \ + maybe-configure-target-libssp \ maybe-configure-target-newlib \ maybe-configure-target-libgfortran \ maybe-configure-target-libobjc \ @@ -834,6 +839,7 @@ all-host: \ all-target: \ maybe-all-target-libstdc++-v3 \ maybe-all-target-libmudflap \ + maybe-all-target-libssp \ maybe-all-target-newlib \ maybe-all-target-libgfortran \ maybe-all-target-libobjc \ @@ -933,6 +939,7 @@ info-host: \ info-target: \ maybe-info-target-libstdc++-v3 \ maybe-info-target-libmudflap \ + maybe-info-target-libssp \ maybe-info-target-newlib \ maybe-info-target-libgfortran \ maybe-info-target-libobjc \ @@ -1027,6 +1034,7 @@ dvi-host: \ dvi-target: \ maybe-dvi-target-libstdc++-v3 \ maybe-dvi-target-libmudflap \ + maybe-dvi-target-libssp \ maybe-dvi-target-newlib \ maybe-dvi-target-libgfortran \ maybe-dvi-target-libobjc \ @@ -1121,6 +1129,7 @@ html-host: \ html-target: \ maybe-html-target-libstdc++-v3 \ maybe-html-target-libmudflap \ + maybe-html-target-libssp \ maybe-html-target-newlib \ maybe-html-target-libgfortran \ maybe-html-target-libobjc \ @@ -1215,6 +1224,7 @@ TAGS-host: \ TAGS-target: \ maybe-TAGS-target-libstdc++-v3 \ maybe-TAGS-target-libmudflap \ + maybe-TAGS-target-libssp \ maybe-TAGS-target-newlib \ maybe-TAGS-target-libgfortran \ maybe-TAGS-target-libobjc \ @@ -1309,6 +1319,7 @@ install-info-host: \ install-info-target: \ maybe-install-info-target-libstdc++-v3 \ maybe-install-info-target-libmudflap \ + maybe-install-info-target-libssp \ maybe-install-info-target-newlib \ maybe-install-info-target-libgfortran \ maybe-install-info-target-libobjc \ @@ -1403,6 +1414,7 @@ installcheck-host: \ installcheck-target: \ maybe-installcheck-target-libstdc++-v3 \ maybe-installcheck-target-libmudflap \ + maybe-installcheck-target-libssp \ maybe-installcheck-target-newlib \ maybe-installcheck-target-libgfortran \ maybe-installcheck-target-libobjc \ @@ -1497,6 +1509,7 @@ mostlyclean-host: \ mostlyclean-target: \ maybe-mostlyclean-target-libstdc++-v3 \ maybe-mostlyclean-target-libmudflap \ + maybe-mostlyclean-target-libssp \ maybe-mostlyclean-target-newlib \ maybe-mostlyclean-target-libgfortran \ maybe-mostlyclean-target-libobjc \ @@ -1591,6 +1604,7 @@ clean-host: \ clean-target: \ maybe-clean-target-libstdc++-v3 \ maybe-clean-target-libmudflap \ + maybe-clean-target-libssp \ maybe-clean-target-newlib \ maybe-clean-target-libgfortran \ maybe-clean-target-libobjc \ @@ -1685,6 +1699,7 @@ distclean-host: \ distclean-target: \ maybe-distclean-target-libstdc++-v3 \ maybe-distclean-target-libmudflap \ + maybe-distclean-target-libssp \ maybe-distclean-target-newlib \ maybe-distclean-target-libgfortran \ maybe-distclean-target-libobjc \ @@ -1779,6 +1794,7 @@ maintainer-clean-host: \ maintainer-clean-target: \ maybe-maintainer-clean-target-libstdc++-v3 \ maybe-maintainer-clean-target-libmudflap \ + maybe-maintainer-clean-target-libssp \ maybe-maintainer-clean-target-newlib \ maybe-maintainer-clean-target-libgfortran \ maybe-maintainer-clean-target-libobjc \ @@ -1932,6 +1948,7 @@ do-check: unstage \ maybe-check-gnattools \ maybe-check-target-libstdc++-v3 \ maybe-check-target-libmudflap \ + maybe-check-target-libssp \ maybe-check-target-newlib \ maybe-check-target-libgfortran \ maybe-check-target-libobjc \ @@ -2118,6 +2135,7 @@ install-host: \ install-target: \ maybe-install-target-libstdc++-v3 \ maybe-install-target-libmudflap \ + maybe-install-target-libssp \ maybe-install-target-newlib \ maybe-install-target-libgfortran \ maybe-install-target-libobjc \ @@ -27936,6 +27954,341 @@ maintainer-clean-target-libmudflap: # There's only one multilib.out. Cleverer subdirs shouldn't need it copied. +@if target-libssp +$(TARGET_SUBDIR)/libssp/multilib.out: multilib.out + $(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libssp ; \ + rm -f $(TARGET_SUBDIR)/libssp/Makefile || : ; \ + cp multilib.out $(TARGET_SUBDIR)/libssp/multilib.out +@endif target-libssp + + + +.PHONY: configure-target-libssp maybe-configure-target-libssp +maybe-configure-target-libssp: +@if target-libssp +maybe-configure-target-libssp: configure-target-libssp +configure-target-libssp: $(TARGET_SUBDIR)/libssp/multilib.out + @test ! -f $(TARGET_SUBDIR)/libssp/Makefile || exit 0; \ + $(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/libssp ; \ + r=`${PWD_COMMAND}`; export r; \ + s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ + $(NORMAL_TARGET_EXPORTS) \ + echo Configuring in $(TARGET_SUBDIR)/libssp; \ + cd "$(TARGET_SUBDIR)/libssp" || exit 1; \ + case $(srcdir) in \ + /* | [A-Za-z]:[\\/]*) topdir=$(srcdir) ;; \ + *) topdir=`echo $(TARGET_SUBDIR)/libssp/ | \ + sed -e 's,\./,,g' -e 's,[^/]*/,../,g' `$(srcdir) ;; \ + esac; \ + srcdiroption="--srcdir=$${topdir}/libssp"; \ + libsrcdir="$$s/libssp"; \ + rm -f no-such-file || : ; \ + CONFIG_SITE=no-such-file $(SHELL) $${libsrcdir}/configure \ + $(TARGET_CONFIGARGS) $${srcdiroption} \ + || exit 1 +@endif target-libssp + + + + + +.PHONY: all-target-libssp maybe-all-target-libssp +maybe-all-target-libssp: +@if target-libssp +TARGET-target-libssp=all +maybe-all-target-libssp: all-target-libssp +all-target-libssp: configure-target-libssp + @r=`${PWD_COMMAND}`; export r; \ + s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ + $(NORMAL_TARGET_EXPORTS) \ + (cd $(TARGET_SUBDIR)/libssp && \ + $(MAKE) $(TARGET_FLAGS_TO_PASS) $(TARGET-target-libssp)) +@endif target-libssp + + + + + +.PHONY: check-target-libssp maybe-check-target-libssp +maybe-check-target-libssp: +@if target-libssp +maybe-check-target-libssp: check-target-libssp + +check-target-libssp: + @r=`${PWD_COMMAND}`; export r; \ + s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ + $(NORMAL_TARGET_EXPORTS) \ + (cd $(TARGET_SUBDIR)/libssp && \ + $(MAKE) $(TARGET_FLAGS_TO_PASS) check) + +@endif target-libssp + +.PHONY: install-target-libssp maybe-install-target-libssp +maybe-install-target-libssp: +@if target-libssp +maybe-install-target-libssp: install-target-libssp + +install-target-libssp: installdirs + @r=`${PWD_COMMAND}`; export r; \ + s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ + $(NORMAL_TARGET_EXPORTS) \ + (cd $(TARGET_SUBDIR)/libssp && \ + $(MAKE) $(TARGET_FLAGS_TO_PASS) install) + +@endif target-libssp + +# Other targets (info, dvi, etc.) + +.PHONY: maybe-info-target-libssp info-target-libssp +maybe-info-target-libssp: +@if target-libssp +maybe-info-target-libssp: info-target-libssp + +info-target-libssp: \ + configure-target-libssp + @[ -f $(TARGET_SUBDIR)/libssp/Makefile ] || exit 0 ; \ + r=`${PWD_COMMAND}`; export r; \ + s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ + $(NORMAL_TARGET_EXPORTS) \ + echo "Doing info in $(TARGET_SUBDIR)/libssp" ; \ + for flag in $(EXTRA_TARGET_FLAGS); do \ + eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \ + done; \ + (cd $(TARGET_SUBDIR)/libssp && \ + $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \ + "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \ + "RANLIB=$${RANLIB}" \ + "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" \ + info) \ + || exit 1 + +@endif target-libssp + +.PHONY: maybe-dvi-target-libssp dvi-target-libssp +maybe-dvi-target-libssp: +@if target-libssp +maybe-dvi-target-libssp: dvi-target-libssp + +dvi-target-libssp: \ + configure-target-libssp + @[ -f $(TARGET_SUBDIR)/libssp/Makefile ] || exit 0 ; \ + r=`${PWD_COMMAND}`; export r; \ + s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ + $(NORMAL_TARGET_EXPORTS) \ + echo "Doing dvi in $(TARGET_SUBDIR)/libssp" ; \ + for flag in $(EXTRA_TARGET_FLAGS); do \ + eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \ + done; \ + (cd $(TARGET_SUBDIR)/libssp && \ + $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \ + "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \ + "RANLIB=$${RANLIB}" \ + "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" \ + dvi) \ + || exit 1 + +@endif target-libssp + +.PHONY: maybe-html-target-libssp html-target-libssp +maybe-html-target-libssp: +@if target-libssp +maybe-html-target-libssp: html-target-libssp + +html-target-libssp: \ + configure-target-libssp + @[ -f $(TARGET_SUBDIR)/libssp/Makefile ] || exit 0 ; \ + r=`${PWD_COMMAND}`; export r; \ + s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ + $(NORMAL_TARGET_EXPORTS) \ + echo "Doing html in $(TARGET_SUBDIR)/libssp" ; \ + for flag in $(EXTRA_TARGET_FLAGS); do \ + eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \ + done; \ + (cd $(TARGET_SUBDIR)/libssp && \ + $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \ + "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \ + "RANLIB=$${RANLIB}" \ + "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" \ + html) \ + || exit 1 + +@endif target-libssp + +.PHONY: maybe-TAGS-target-libssp TAGS-target-libssp +maybe-TAGS-target-libssp: +@if target-libssp +maybe-TAGS-target-libssp: TAGS-target-libssp + +TAGS-target-libssp: \ + configure-target-libssp + @[ -f $(TARGET_SUBDIR)/libssp/Makefile ] || exit 0 ; \ + r=`${PWD_COMMAND}`; export r; \ + s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ + $(NORMAL_TARGET_EXPORTS) \ + echo "Doing TAGS in $(TARGET_SUBDIR)/libssp" ; \ + for flag in $(EXTRA_TARGET_FLAGS); do \ + eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \ + done; \ + (cd $(TARGET_SUBDIR)/libssp && \ + $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \ + "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \ + "RANLIB=$${RANLIB}" \ + "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" \ + TAGS) \ + || exit 1 + +@endif target-libssp + +.PHONY: maybe-install-info-target-libssp install-info-target-libssp +maybe-install-info-target-libssp: +@if target-libssp +maybe-install-info-target-libssp: install-info-target-libssp + +install-info-target-libssp: \ + configure-target-libssp \ + info-target-libssp + @[ -f $(TARGET_SUBDIR)/libssp/Makefile ] || exit 0 ; \ + r=`${PWD_COMMAND}`; export r; \ + s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ + $(NORMAL_TARGET_EXPORTS) \ + echo "Doing install-info in $(TARGET_SUBDIR)/libssp" ; \ + for flag in $(EXTRA_TARGET_FLAGS); do \ + eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \ + done; \ + (cd $(TARGET_SUBDIR)/libssp && \ + $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \ + "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \ + "RANLIB=$${RANLIB}" \ + "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" \ + install-info) \ + || exit 1 + +@endif target-libssp + +.PHONY: maybe-installcheck-target-libssp installcheck-target-libssp +maybe-installcheck-target-libssp: +@if target-libssp +maybe-installcheck-target-libssp: installcheck-target-libssp + +installcheck-target-libssp: \ + configure-target-libssp + @[ -f $(TARGET_SUBDIR)/libssp/Makefile ] || exit 0 ; \ + r=`${PWD_COMMAND}`; export r; \ + s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ + $(NORMAL_TARGET_EXPORTS) \ + echo "Doing installcheck in $(TARGET_SUBDIR)/libssp" ; \ + for flag in $(EXTRA_TARGET_FLAGS); do \ + eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \ + done; \ + (cd $(TARGET_SUBDIR)/libssp && \ + $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \ + "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \ + "RANLIB=$${RANLIB}" \ + "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" \ + installcheck) \ + || exit 1 + +@endif target-libssp + +.PHONY: maybe-mostlyclean-target-libssp mostlyclean-target-libssp +maybe-mostlyclean-target-libssp: +@if target-libssp +maybe-mostlyclean-target-libssp: mostlyclean-target-libssp + +mostlyclean-target-libssp: + @[ -f $(TARGET_SUBDIR)/libssp/Makefile ] || exit 0 ; \ + r=`${PWD_COMMAND}`; export r; \ + s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ + $(NORMAL_TARGET_EXPORTS) \ + echo "Doing mostlyclean in $(TARGET_SUBDIR)/libssp" ; \ + for flag in $(EXTRA_TARGET_FLAGS); do \ + eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \ + done; \ + (cd $(TARGET_SUBDIR)/libssp && \ + $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \ + "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \ + "RANLIB=$${RANLIB}" \ + "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" \ + mostlyclean) \ + || exit 1 + +@endif target-libssp + +.PHONY: maybe-clean-target-libssp clean-target-libssp +maybe-clean-target-libssp: +@if target-libssp +maybe-clean-target-libssp: clean-target-libssp + +clean-target-libssp: + @[ -f $(TARGET_SUBDIR)/libssp/Makefile ] || exit 0 ; \ + r=`${PWD_COMMAND}`; export r; \ + s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ + $(NORMAL_TARGET_EXPORTS) \ + echo "Doing clean in $(TARGET_SUBDIR)/libssp" ; \ + for flag in $(EXTRA_TARGET_FLAGS); do \ + eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \ + done; \ + (cd $(TARGET_SUBDIR)/libssp && \ + $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \ + "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \ + "RANLIB=$${RANLIB}" \ + "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" \ + clean) \ + || exit 1 + +@endif target-libssp + +.PHONY: maybe-distclean-target-libssp distclean-target-libssp +maybe-distclean-target-libssp: +@if target-libssp +maybe-distclean-target-libssp: distclean-target-libssp + +distclean-target-libssp: + @[ -f $(TARGET_SUBDIR)/libssp/Makefile ] || exit 0 ; \ + r=`${PWD_COMMAND}`; export r; \ + s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ + $(NORMAL_TARGET_EXPORTS) \ + echo "Doing distclean in $(TARGET_SUBDIR)/libssp" ; \ + for flag in $(EXTRA_TARGET_FLAGS); do \ + eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \ + done; \ + (cd $(TARGET_SUBDIR)/libssp && \ + $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \ + "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \ + "RANLIB=$${RANLIB}" \ + "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" \ + distclean) \ + || exit 1 + +@endif target-libssp + +.PHONY: maybe-maintainer-clean-target-libssp maintainer-clean-target-libssp +maybe-maintainer-clean-target-libssp: +@if target-libssp +maybe-maintainer-clean-target-libssp: maintainer-clean-target-libssp + +maintainer-clean-target-libssp: + @[ -f $(TARGET_SUBDIR)/libssp/Makefile ] || exit 0 ; \ + r=`${PWD_COMMAND}`; export r; \ + s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ + $(NORMAL_TARGET_EXPORTS) \ + echo "Doing maintainer-clean in $(TARGET_SUBDIR)/libssp" ; \ + for flag in $(EXTRA_TARGET_FLAGS); do \ + eval `echo "$$flag" | sed -e "s|^\([^=]*\)=\(.*\)|\1='\2'; export \1|"`; \ + done; \ + (cd $(TARGET_SUBDIR)/libssp && \ + $(MAKE) $(BASE_FLAGS_TO_PASS) "AR=$${AR}" "AS=$${AS}" \ + "CC=$${CC}" "CXX=$${CXX}" "LD=$${LD}" "NM=$${NM}" \ + "RANLIB=$${RANLIB}" \ + "DLLTOOL=$${DLLTOOL}" "WINDRES=$${WINDRES}" \ + maintainer-clean) \ + || exit 1 + +@endif target-libssp + + + +# There's only one multilib.out. Cleverer subdirs shouldn't need it copied. @if target-newlib $(TARGET_SUBDIR)/newlib/multilib.out: multilib.out $(SHELL) $(srcdir)/mkinstalldirs $(TARGET_SUBDIR)/newlib ; \ @@ -33394,7 +33747,7 @@ objext = .o # Flags to pass to stage2 and later makes. POSTSTAGE1_FLAGS_TO_PASS = \ CC="$${CC}" CC_FOR_BUILD="$${CC_FOR_BUILD}" \ - STAGE_PREFIX=$$r/stage-gcc/ \ + STAGE_PREFIX=$$r/prev-gcc/ \ CFLAGS="$(BOOT_CFLAGS)" \ ADAC="\$$(CC)" @@ -34363,7 +34716,7 @@ stagefeedback-start:: mkdir stagefeedback-bfd; \ set stagefeedback-bfd bfd ; \ @CREATE_LINK_TO_DIR@ ; \ - set stage1-bfd prev-bfd ; \ + set stageprofile-bfd prev-bfd ; \ @CREATE_LINK_TO_DIR@ @endif bfd @if opcodes @@ -34371,7 +34724,7 @@ stagefeedback-start:: mkdir stagefeedback-opcodes; \ set stagefeedback-opcodes opcodes ; \ @CREATE_LINK_TO_DIR@ ; \ - set stage1-opcodes prev-opcodes ; \ + set stageprofile-opcodes prev-opcodes ; \ @CREATE_LINK_TO_DIR@ @endif opcodes @if binutils @@ -34379,7 +34732,7 @@ stagefeedback-start:: mkdir stagefeedback-binutils; \ set stagefeedback-binutils binutils ; \ @CREATE_LINK_TO_DIR@ ; \ - set stage1-binutils prev-binutils ; \ + set stageprofile-binutils prev-binutils ; \ @CREATE_LINK_TO_DIR@ @endif binutils @if gas @@ -34387,7 +34740,7 @@ stagefeedback-start:: mkdir stagefeedback-gas; \ set stagefeedback-gas gas ; \ @CREATE_LINK_TO_DIR@ ; \ - set stage1-gas prev-gas ; \ + set stageprofile-gas prev-gas ; \ @CREATE_LINK_TO_DIR@ @endif gas @if gcc @@ -34395,7 +34748,7 @@ stagefeedback-start:: mkdir stagefeedback-gcc; \ set stagefeedback-gcc gcc ; \ @CREATE_LINK_TO_DIR@ ; \ - set stage1-gcc prev-gcc ; \ + set stageprofile-gcc prev-gcc ; \ @CREATE_LINK_TO_DIR@ @endif gcc @if intl @@ -34403,7 +34756,7 @@ stagefeedback-start:: mkdir stagefeedback-intl; \ set stagefeedback-intl intl ; \ @CREATE_LINK_TO_DIR@ ; \ - set stage1-intl prev-intl ; \ + set stageprofile-intl prev-intl ; \ @CREATE_LINK_TO_DIR@ @endif intl @if ld @@ -34411,7 +34764,7 @@ stagefeedback-start:: mkdir stagefeedback-ld; \ set stagefeedback-ld ld ; \ @CREATE_LINK_TO_DIR@ ; \ - set stage1-ld prev-ld ; \ + set stageprofile-ld prev-ld ; \ @CREATE_LINK_TO_DIR@ @endif ld @if libcpp @@ -34419,7 +34772,7 @@ stagefeedback-start:: mkdir stagefeedback-libcpp; \ set stagefeedback-libcpp libcpp ; \ @CREATE_LINK_TO_DIR@ ; \ - set stage1-libcpp prev-libcpp ; \ + set stageprofile-libcpp prev-libcpp ; \ @CREATE_LINK_TO_DIR@ @endif libcpp @if libiberty @@ -34427,7 +34780,7 @@ stagefeedback-start:: mkdir stagefeedback-libiberty; \ set stagefeedback-libiberty libiberty ; \ @CREATE_LINK_TO_DIR@ ; \ - set stage1-libiberty prev-libiberty ; \ + set stageprofile-libiberty prev-libiberty ; \ @CREATE_LINK_TO_DIR@ @endif libiberty @if zlib @@ -34435,7 +34788,7 @@ stagefeedback-start:: mkdir stagefeedback-zlib; \ set stagefeedback-zlib zlib ; \ @CREATE_LINK_TO_DIR@ ; \ - set stage1-zlib prev-zlib ; \ + set stageprofile-zlib prev-zlib ; \ @CREATE_LINK_TO_DIR@ @endif zlib @@ -34444,61 +34797,61 @@ stagefeedback-end:: @if bfd @cd $(HOST_SUBDIR); set bfd stagefeedback-bfd ; \ @UNDO_LINK_TO_DIR@ ; \ - set prev-bfd stage1-bfd ; \ + set prev-bfd stageprofile-bfd ; \ @UNDO_LINK_TO_DIR@ @endif bfd @if opcodes @cd $(HOST_SUBDIR); set opcodes stagefeedback-opcodes ; \ @UNDO_LINK_TO_DIR@ ; \ - set prev-opcodes stage1-opcodes ; \ + set prev-opcodes stageprofile-opcodes ; \ @UNDO_LINK_TO_DIR@ @endif opcodes @if binutils @cd $(HOST_SUBDIR); set binutils stagefeedback-binutils ; \ @UNDO_LINK_TO_DIR@ ; \ - set prev-binutils stage1-binutils ; \ + set prev-binutils stageprofile-binutils ; \ @UNDO_LINK_TO_DIR@ @endif binutils @if gas @cd $(HOST_SUBDIR); set gas stagefeedback-gas ; \ @UNDO_LINK_TO_DIR@ ; \ - set prev-gas stage1-gas ; \ + set prev-gas stageprofile-gas ; \ @UNDO_LINK_TO_DIR@ @endif gas @if gcc @cd $(HOST_SUBDIR); set gcc stagefeedback-gcc ; \ @UNDO_LINK_TO_DIR@ ; \ - set prev-gcc stage1-gcc ; \ + set prev-gcc stageprofile-gcc ; \ @UNDO_LINK_TO_DIR@ @endif gcc @if intl @cd $(HOST_SUBDIR); set intl stagefeedback-intl ; \ @UNDO_LINK_TO_DIR@ ; \ - set prev-intl stage1-intl ; \ + set prev-intl stageprofile-intl ; \ @UNDO_LINK_TO_DIR@ @endif intl @if ld @cd $(HOST_SUBDIR); set ld stagefeedback-ld ; \ @UNDO_LINK_TO_DIR@ ; \ - set prev-ld stage1-ld ; \ + set prev-ld stageprofile-ld ; \ @UNDO_LINK_TO_DIR@ @endif ld @if libcpp @cd $(HOST_SUBDIR); set libcpp stagefeedback-libcpp ; \ @UNDO_LINK_TO_DIR@ ; \ - set prev-libcpp stage1-libcpp ; \ + set prev-libcpp stageprofile-libcpp ; \ @UNDO_LINK_TO_DIR@ @endif libcpp @if libiberty @cd $(HOST_SUBDIR); set libiberty stagefeedback-libiberty ; \ @UNDO_LINK_TO_DIR@ ; \ - set prev-libiberty stage1-libiberty ; \ + set prev-libiberty stageprofile-libiberty ; \ @UNDO_LINK_TO_DIR@ @endif libiberty @if zlib @cd $(HOST_SUBDIR); set zlib stagefeedback-zlib ; \ @UNDO_LINK_TO_DIR@ ; \ - set prev-zlib stage1-zlib ; \ + set prev-zlib stageprofile-zlib ; \ @UNDO_LINK_TO_DIR@ @endif zlib @@ -34506,8 +34859,8 @@ stagefeedback-end:: # are remade, but not reconfigured. The next stage (if any) will not # be reconfigured as well. .PHONY: stagefeedback-bubble -stagefeedback-bubble:: stage1-bubble - @if test -f stagefeedback-lean || test -f stage1-lean ; then \ +stagefeedback-bubble:: stageprofile-bubble + @if test -f stagefeedback-lean || test -f stageprofile-lean ; then \ echo Skipping rebuild of stagefeedback ; \ else \ $(MAKE) $(RECURSE_FLAGS_TO_PASS) NOTPARALLEL= all-stagefeedback; \ @@ -34522,9 +34875,12 @@ do-clean: clean-stagefeedback +.PHONY: profiledbootstrap +profiledbootstrap: stagefeedback-bubble all + # Rules to wipe a stage and all the following ones, also used for cleanstrap -distclean-stage1:: distclean-stagefeedback +distclean-stageprofile:: distclean-stagefeedback .PHONY: distclean-stagefeedback distclean-stagefeedback:: [ -f stage_current ] && $(MAKE) `cat stage_current`-end || : @@ -34535,32 +34891,18 @@ distclean-stagefeedback:: -stagefeedback-start:: - @r=`${PWD_COMMAND}`; export r; \ - s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ - cd stageprofile-gcc && \ - { find . -type d | sort | sed 's,.*,$(SHELL) '"$$s"'/mkinstalldirs "../gcc/&",' | $(SHELL); } && \ - { find . -name '*.*da' | sed 's,.*,$(LN) -f "&" "../gcc/&",' | $(SHELL); } +stageprofile-end:: + $(MAKE) distclean-stagefeedback -# FIXME: Will not need to be conditional when toplevel bootstrap is the -# only possibility, but now it conflicts with no-bootstrap rules -@if gcc-bootstrap -profiledbootstrap: - @r=`${PWD_COMMAND}`; export r; \ - s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ - $(HOST_EXPORTS) \ - echo "Bootstrapping the compiler"; \ - $(MAKE) stageprofile-bubble distclean-stagefeedback - @r=`${PWD_COMMAND}`; export r; \ - s=`cd $(srcdir); ${PWD_COMMAND}` ; export s; \ - echo "Building runtime libraries and training compiler"; \ - $(MAKE) $(BASE_FLAGS_TO_PASS) $(RECURSE_FLAGS) all +stagefeedback-start:: @r=`${PWD_COMMAND}`; export r; \ s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ - $(HOST_EXPORTS) \ - echo "Building feedback based compiler"; \ - $(MAKE) stagefeedback-bubble stagefeedback-end -@endif gcc-bootstrap + for i in prev-*; do \ + j=`echo $$i | sed s/^prev-//` ; \ + cd $$r/$$i && \ + { find . -type d | sort | sed 's,.*,$(SHELL) '"$$s"'/mkinstalldirs "../'$$j'/&",' | $(SHELL) ; } && \ + { find . -name '*.*da' | sed 's,.*,$(LN) -f "&" "../'$$j'/&",' | $(SHELL) ; } ; \ + done @if gcc-bootstrap NOTPARALLEL = .NOTPARALLEL @@ -34578,6 +34920,8 @@ configure-target-libstdc++-v3: maybe-all configure-target-libmudflap: maybe-all-gcc +configure-target-libssp: maybe-all-gcc + configure-target-newlib: maybe-all-gcc configure-target-libgfortran: maybe-all-gcc diff -uprN binutils-2.16.91.0.1/Makefile.tpl binutils-2.16.91.0.2/Makefile.tpl --- binutils-2.16.91.0.1/Makefile.tpl 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/Makefile.tpl 2005-07-20 12:27:26.595308124 -0700 @@ -20,7 +20,7 @@ in # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. # # ------------------------------- @@ -586,7 +586,6 @@ EXTRA_GCC_FLAGS = \ 'BUILD_PREFIX=$(BUILD_PREFIX)' \ 'BUILD_PREFIX_1=$(BUILD_PREFIX_1)' \ "GCC_FOR_TARGET=$(GCC_FOR_TARGET)" \ - "CFLAGS_FOR_BUILD=$(CFLAGS_FOR_BUILD)" \ "`echo 'LANGUAGES=$(LANGUAGES)' | sed -e s'/[^=][^=]*=$$/XFOO=/'`" \ "`echo 'STMP_FIXPROTO=$(STMP_FIXPROTO)' | sed -e s'/[^=][^=]*=$$/XFOO=/'`" \ "`echo 'LIMITS_H_TEST=$(LIMITS_H_TEST)' | sed -e s'/[^=][^=]*=$$/XFOO=/'`" \ @@ -1320,7 +1319,7 @@ objext = .o # Flags to pass to stage2 and later makes. POSTSTAGE1_FLAGS_TO_PASS = \ CC="$${CC}" CC_FOR_BUILD="$${CC_FOR_BUILD}" \ - STAGE_PREFIX=$$r/stage[+prev+]-gcc/ \ + STAGE_PREFIX=$$r/prev-gcc/ \ CFLAGS="$(BOOT_CFLAGS)" \ ADAC="\$$(CC)" @@ -1445,32 +1444,18 @@ distclean-stage[+id+]:: [+ ENDFOR bootstrap-stage +] -stagefeedback-start:: - @r=`${PWD_COMMAND}`; export r; \ - s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ - cd stageprofile-gcc && \ - { find . -type d | sort | sed 's,.*,$(SHELL) '"$$s"'/mkinstalldirs "../gcc/&",' | $(SHELL); } && \ - { find . -name '*.*da' | sed 's,.*,$(LN) -f "&" "../gcc/&",' | $(SHELL); } +stageprofile-end:: + $(MAKE) distclean-stagefeedback -# FIXME: Will not need to be conditional when toplevel bootstrap is the -# only possibility, but now it conflicts with no-bootstrap rules -@if gcc-bootstrap -profiledbootstrap: - @r=`${PWD_COMMAND}`; export r; \ - s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ - $(HOST_EXPORTS) \ - echo "Bootstrapping the compiler"; \ - $(MAKE) stageprofile-bubble distclean-stagefeedback - @r=`${PWD_COMMAND}`; export r; \ - s=`cd $(srcdir); ${PWD_COMMAND}` ; export s; \ - echo "Building runtime libraries and training compiler"; \ - $(MAKE) $(BASE_FLAGS_TO_PASS) $(RECURSE_FLAGS) all +stagefeedback-start:: @r=`${PWD_COMMAND}`; export r; \ s=`cd $(srcdir); ${PWD_COMMAND}`; export s; \ - $(HOST_EXPORTS) \ - echo "Building feedback based compiler"; \ - $(MAKE) stagefeedback-bubble stagefeedback-end -@endif gcc-bootstrap + for i in prev-*; do \ + j=`echo $$i | sed s/^prev-//` ; \ + cd $$r/$$i && \ + { find . -type d | sort | sed 's,.*,$(SHELL) '"$$s"'/mkinstalldirs "../'$$j'/&",' | $(SHELL) ; } && \ + { find . -name '*.*da' | sed 's,.*,$(LN) -f "&" "../'$$j'/&",' | $(SHELL) ; } ; \ + done @if gcc-bootstrap NOTPARALLEL = .NOTPARALLEL diff -uprN binutils-2.16.91.0.1/missing binutils-2.16.91.0.2/missing --- binutils-2.16.91.0.1/missing 2004-09-15 12:05:02.000000000 -0700 +++ binutils-2.16.91.0.2/missing 2005-07-20 12:27:26.876261795 -0700 @@ -1,9 +1,9 @@ #! /bin/sh # Common stub for a few missing GNU programs while installing. -scriptversion=2004-09-07.08 +scriptversion=2005-06-08.21 -# Copyright (C) 1996, 1997, 1999, 2000, 2002, 2003, 2004 +# Copyright (C) 1996, 1997, 1999, 2000, 2002, 2003, 2004, 2005 # Free Software Foundation, Inc. # Originally by Fran,cois Pinard , 1996. @@ -19,8 +19,8 @@ scriptversion=2004-09-07.08 # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA -# 02111-1307, USA. +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA +# 02110-1301, USA. # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a @@ -87,12 +87,12 @@ Supported PROGRAM values: yacc create \`y.tab.[ch]', if possible, from existing .[ch] Send bug reports to ." - exit 0 + exit $? ;; -v|--v|--ve|--ver|--vers|--versi|--versio|--version) echo "missing $scriptversion (GNU Automake)" - exit 0 + exit $? ;; -*) @@ -288,11 +288,18 @@ WARNING: \`$1' is $msg. You should only call might also be the consequence of using a buggy \`make' (AIX, DU, IRIX). You might want to install the \`Texinfo' package or the \`GNU make' package. Grab either from any GNU archive site." + # The file to touch is that specified with -o ... file=`echo "$*" | sed -n 's/.*-o \([^ ]*\).*/\1/p'` if test -z "$file"; then - file=`echo "$*" | sed 's/.* \([^ ]*\) *$/\1/'` - file=`sed -n '/^@setfilename/ { s/.* \([^ ]*\) *$/\1/; p; q; }' $file` - fi + # ... or it is the one specified with @setfilename ... + infile=`echo "$*" | sed 's/.* \([^ ]*\) *$/\1/'` + file=`sed -n '/^@setfilename/ { s/.* \([^ ]*\) *$/\1/; p; q; }' $infile` + # ... or it is derived from the source name (dir/f.texi becomes f.info) + test -z "$file" && file=`echo "$infile" | sed 's,.*/,,;s,.[^.]*$,,'`.info + fi + # If the file does not exist, the user really needs makeinfo; + # let's fail without touching anything. + test -f $file || exit 1 touch $file ;; diff -uprN binutils-2.16.91.0.1/mkinstalldirs binutils-2.16.91.0.2/mkinstalldirs --- binutils-2.16.91.0.1/mkinstalldirs 2004-03-03 12:24:33.000000000 -0800 +++ binutils-2.16.91.0.2/mkinstalldirs 2005-07-20 12:27:26.883260640 -0700 @@ -1,7 +1,7 @@ #! /bin/sh # mkinstalldirs --- make directory hierarchy -scriptversion=2004-02-15.20 +scriptversion=2005-06-29.22 # Original author: Noah Friedman # Created: 1993-05-16 @@ -12,7 +12,7 @@ scriptversion=2004-02-15.20 # . errstatus=0 -dirmode="" +dirmode= usage="\ Usage: mkinstalldirs [-h] [--help] [--version] [-m MODE] DIR ... @@ -27,7 +27,7 @@ while test $# -gt 0 ; do case $1 in -h | --help | --h*) # -h for help echo "$usage" - exit 0 + exit $? ;; -m) # -m PERM arg shift @@ -37,7 +37,7 @@ while test $# -gt 0 ; do ;; --version) echo "$0 $scriptversion" - exit 0 + exit $? ;; --) # stop option processing shift @@ -103,13 +103,21 @@ esac for file do - set fnord `echo ":$file" | sed -ne 's/^:\//#/;s/^://;s/\// /g;s/^#/\//;p'` + case $file in + /*) pathcomp=/ ;; + *) pathcomp= ;; + esac + oIFS=$IFS + IFS=/ + set fnord $file shift + IFS=$oIFS - pathcomp= for d do - pathcomp="$pathcomp$d" + test "x$d" = x && continue + + pathcomp=$pathcomp$d case $pathcomp in -*) pathcomp=./$pathcomp ;; esac @@ -124,7 +132,7 @@ do else if test ! -z "$dirmode"; then echo "chmod $dirmode $pathcomp" - lasterr="" + lasterr= chmod "$dirmode" "$pathcomp" || lasterr=$? if test ! -z "$lasterr"; then @@ -134,7 +142,7 @@ do fi fi - pathcomp="$pathcomp/" + pathcomp=$pathcomp/ done done diff -uprN binutils-2.16.91.0.1/move-if-change binutils-2.16.91.0.2/move-if-change --- binutils-2.16.91.0.1/move-if-change 1999-06-03 11:01:52.000000000 -0700 +++ binutils-2.16.91.0.2/move-if-change 2005-07-20 12:27:26.884260476 -0700 @@ -14,7 +14,7 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. if test -r $2 diff -uprN binutils-2.16.91.0.1/opcodes/a29k-dis.c binutils-2.16.91.0.2/opcodes/a29k-dis.c --- binutils-2.16.91.0.1/opcodes/a29k-dis.c 2005-05-10 15:46:53.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/a29k-dis.c 2005-07-20 12:27:28.538987613 -0700 @@ -3,46 +3,34 @@ Free Software Foundation, Inc. Contributed by Cygnus Support. Written by Jim Kingdon. -This file is part of GDB. + This file is part of GDB and GNU Binutils. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "sysdep.h" #include "dis-asm.h" #include "opcode/a29k.h" -static void print_general PARAMS ((int, struct disassemble_info *)); -static void print_special PARAMS ((unsigned int, struct disassemble_info *)); -static int is_delayed_branch PARAMS ((int)); -static void find_bytes_little - PARAMS ((char *, unsigned char *, unsigned char *, unsigned char *, - unsigned char *)); -static void find_bytes_big - PARAMS ((char *, unsigned char *, unsigned char *, unsigned char *, - unsigned char *)); -static int print_insn PARAMS ((bfd_vma, struct disassemble_info *)); - - /* Print a symbolic representation of a general-purpose register number NUM on STREAM. NUM is a number as found in the instruction, not as found in debugging symbols; it must be in the range 0-255. */ + static void -print_general (num, info) - int num; - struct disassemble_info *info; +print_general (int num, struct disassemble_info *info) { if (num < 128) (*info->fprintf_func) (info->stream, "gr%d", num); @@ -55,29 +43,31 @@ print_general (num, info) The mnemonics used by the AMD assembler are not quite the same as the ones in the User's Manual. We use the ones that the assembler uses. */ + static void -print_special (num, info) - unsigned int num; - struct disassemble_info *info; +print_special (unsigned int num, struct disassemble_info *info) { /* Register names of registers 0-SPEC0_NUM-1. */ - static char *spec0_names[] = { - "vab", "ops", "cps", "cfg", "cha", "chd", "chc", "rbp", "tmc", "tmr", - "pc0", "pc1", "pc2", "mmu", "lru", "rsn", "rma0", "rmc0", "rma1", "rmc1", - "spc0", "spc1", "spc2", "iba0", "ibc0", "iba1", "ibc1", "dba", "dbc", - "cir", "cdr" + static char *spec0_names[] = + { + "vab", "ops", "cps", "cfg", "cha", "chd", "chc", "rbp", "tmc", "tmr", + "pc0", "pc1", "pc2", "mmu", "lru", "rsn", "rma0", "rmc0", "rma1", "rmc1", + "spc0", "spc1", "spc2", "iba0", "ibc0", "iba1", "ibc1", "dba", "dbc", + "cir", "cdr" }; #define SPEC0_NUM ((sizeof spec0_names) / (sizeof spec0_names[0])) /* Register names of registers 128-128+SPEC128_NUM-1. */ - static char *spec128_names[] = { - "ipc", "ipa", "ipb", "q", "alu", "bp", "fc", "cr" + static char *spec128_names[] = + { + "ipc", "ipa", "ipb", "q", "alu", "bp", "fc", "cr" }; #define SPEC128_NUM ((sizeof spec128_names) / (sizeof spec128_names[0])) /* Register names of registers 160-160+SPEC160_NUM-1. */ - static char *spec160_names[] = { - "fpe", "inte", "fps", "sr163", "exop" + static char *spec160_names[] = + { + "fpe", "inte", "fps", "sr163", "exop" }; #define SPEC160_NUM ((sizeof spec160_names) / (sizeof spec160_names[0])) @@ -92,9 +82,9 @@ print_special (num, info) } /* Is an instruction with OPCODE a delayed branch? */ + static int -is_delayed_branch (opcode) - int opcode; +is_delayed_branch (int opcode) { return (opcode == 0xa8 || opcode == 0xa9 || opcode == 0xa0 || opcode == 0xa1 || opcode == 0xa4 || opcode == 0xa5 @@ -105,13 +95,13 @@ is_delayed_branch (opcode) } /* Now find the four bytes of INSN and put them in *INSN{0,8,16,24}. */ + static void -find_bytes_big (insn, insn0, insn8, insn16, insn24) - char *insn; - unsigned char *insn0; - unsigned char *insn8; - unsigned char *insn16; - unsigned char *insn24; +find_bytes_big (char *insn, + unsigned char *insn0, + unsigned char *insn8, + unsigned char *insn16, + unsigned char *insn24) { *insn24 = insn[0]; *insn16 = insn[1]; @@ -120,12 +110,11 @@ find_bytes_big (insn, insn0, insn8, insn } static void -find_bytes_little (insn, insn0, insn8, insn16, insn24) - char *insn; - unsigned char *insn0; - unsigned char *insn8; - unsigned char *insn16; - unsigned char *insn24; +find_bytes_little (char *insn, + unsigned char *insn0, + unsigned char *insn8, + unsigned char *insn16, + unsigned char *insn24) { *insn24 = insn[3]; *insn16 = insn[2]; @@ -134,16 +123,14 @@ find_bytes_little (insn, insn0, insn8, i } typedef void (*find_byte_func_type) - PARAMS ((char *, unsigned char *, unsigned char *, - unsigned char *, unsigned char *)); + (char *, unsigned char *, unsigned char *, + unsigned char *, unsigned char *); /* Print one instruction from MEMADDR on INFO->STREAM. Return the size of the instruction (always 4 on a29k). */ static int -print_insn (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn (bfd_vma memaddr, struct disassemble_info *info) { /* The raw instruction. */ char insn[4]; @@ -169,11 +156,15 @@ print_insn (memaddr, info) printf ("%02x%02x%02x%02x ", insn24, insn16, insn8, insn0); - /* Handle the nop (aseq 0x40,gr1,gr1) specially */ - if ((insn24==0x70) && (insn16==0x40) && (insn8==0x01) && (insn0==0x01)) { - (*info->fprintf_func) (info->stream,"nop"); - return 4; - } + /* Handle the nop (aseq 0x40,gr1,gr1) specially. */ + if ( (insn24 == 0x70) + && (insn16 == 0x40) + && (insn8 == 0x01) + && (insn0 == 0x01)) + { + (*info->fprintf_func) (info->stream,"nop"); + return 4; + } /* The opcode is always in insn24. */ for (opcode = &a29k_opcodes[0]; @@ -206,18 +197,19 @@ print_insn (memaddr, info) break; case 'x': - (*info->fprintf_func) (info->stream, "0x%x", (insn16 << 8) + insn0); + (*info->fprintf_func) (info->stream, "0x%x", + (insn16 << 8) + insn0); break; case 'h': /* This used to be %x for binutils. */ (*info->fprintf_func) (info->stream, "0x%x", - (insn16 << 24) + (insn0 << 16)); + (insn16 << 24) + (insn0 << 16)); break; case 'X': (*info->fprintf_func) (info->stream, "%d", - ((insn16 << 8) + insn0) | 0xffff0000); + ((insn16 << 8) + insn0) | 0xffff0000); break; case 'P': @@ -274,7 +266,8 @@ print_insn (memaddr, info) break; case 'F': - (*info->fprintf_func) (info->stream, "%d", (insn16 >> 2) & 15); + (*info->fprintf_func) (info->stream, "%d", + (insn16 >> 2) & 15); break; case 'C': @@ -308,14 +301,14 @@ print_insn (memaddr, info) call _printf consth _foo */ - (*find_byte_func) (prev_insn, &prev_insn0, &prev_insn8, - &prev_insn16, &prev_insn24); + (*find_byte_func) (prev_insn, & prev_insn0, & prev_insn8, + & prev_insn16, & prev_insn24); if (is_delayed_branch (prev_insn24)) { errcode = (*info->read_memory_func) - (memaddr - 8, (bfd_byte *) &prev_insn[0], 4, info); - (*find_byte_func) (prev_insn, &prev_insn0, &prev_insn8, - &prev_insn16, &prev_insn24); + (memaddr - 8, (bfd_byte *) & prev_insn[0], 4, info); + (*find_byte_func) (prev_insn, & prev_insn0, & prev_insn8, + & prev_insn16, & prev_insn24); } } @@ -347,20 +340,18 @@ print_insn (memaddr, info) } /* Disassemble an big-endian a29k instruction. */ + int -print_insn_big_a29k (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_big_a29k (bfd_vma memaddr, struct disassemble_info *info) { info->private_data = (PTR) find_bytes_big; return print_insn (memaddr, info); } /* Disassemble a little-endian a29k instruction. */ + int -print_insn_little_a29k (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_little_a29k (bfd_vma memaddr, struct disassemble_info *info) { info->private_data = (PTR) find_bytes_little; return print_insn (memaddr, info); diff -uprN binutils-2.16.91.0.1/opcodes/aclocal.m4 binutils-2.16.91.0.2/opcodes/aclocal.m4 --- binutils-2.16.91.0.1/opcodes/aclocal.m4 2005-05-10 15:46:53.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/aclocal.m4 2005-07-20 12:27:28.540987283 -0700 @@ -1,7 +1,7 @@ -# generated automatically by aclocal 1.9.3 -*- Autoconf -*- +# generated automatically by aclocal 1.9.5 -*- Autoconf -*- -# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 -# Free Software Foundation, Inc. +# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, +# 2005 Free Software Foundation, Inc. # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. @@ -11,23 +11,11 @@ # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. -# -*- Autoconf -*- -# Copyright (C) 2002, 2003 Free Software Foundation, Inc. -# Generated from amversion.in; do not edit by hand. - -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. - -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA +# Copyright (C) 2002, 2003, 2005 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. # AM_AUTOMAKE_VERSION(VERSION) # ---------------------------- @@ -40,26 +28,15 @@ AC_DEFUN([AM_AUTOMAKE_VERSION], [am__api # Call AM_AUTOMAKE_VERSION so it can be traced. # This function is AC_REQUIREd by AC_INIT_AUTOMAKE. AC_DEFUN([AM_SET_CURRENT_AUTOMAKE_VERSION], - [AM_AUTOMAKE_VERSION([1.9.3])]) - -# AM_AUX_DIR_EXPAND + [AM_AUTOMAKE_VERSION([1.9.5])]) -# Copyright (C) 2001, 2003 Free Software Foundation, Inc. +# AM_AUX_DIR_EXPAND -*- Autoconf -*- -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. - -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA -# 02110-1301, USA. +# Copyright (C) 2001, 2003, 2005 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. # For projects using AC_CONFIG_AUX_DIR([foo]), Autoconf sets # $ac_aux_dir to `$srcdir/foo'. In other projects, it is set to @@ -106,26 +83,16 @@ AC_PREREQ([2.50])dnl am_aux_dir=`cd $ac_aux_dir && pwd` ]) -# AM_CONDITIONAL -*- Autoconf -*- - -# Copyright (C) 1997, 2000, 2001, 2003, 2004 Free Software Foundation, Inc. +# AM_CONDITIONAL -*- Autoconf -*- -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. - -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA -# 02110-1301, USA. +# Copyright (C) 1997, 2000, 2001, 2003, 2004, 2005 +# Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. -# serial 6 +# serial 7 # AM_CONDITIONAL(NAME, SHELL-CONDITION) # ------------------------------------- @@ -149,26 +116,15 @@ AC_CONFIG_COMMANDS_PRE( Usually this means the macro was only invoked conditionally.]]) fi])]) -# serial 7 -*- Autoconf -*- -# Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004 +# Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005 # Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. - -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA -# 02110-1301, USA. - +# serial 8 # There are a few dirty hacks below to avoid letting `AC_PROG_CC' be # written in clear, in which case automake, when reading aclocal.m4, @@ -177,7 +133,6 @@ fi])]) # CC etc. in the Makefile, will ask for an AC_PROG_CC use... - # _AM_DEPENDENCIES(NAME) # ---------------------- # See how the compiler implements dependency checking. @@ -317,27 +272,16 @@ AM_CONDITIONAL([AMDEP], [test "x$enable_ AC_SUBST([AMDEPBACKSLASH]) ]) -# Generate code to set up dependency tracking. -*- Autoconf -*- - -# Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004 -# Free Software Foundation, Inc. - -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. +# Generate code to set up dependency tracking. -*- Autoconf -*- -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA -# 02110-1301, USA. +# Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005 +# Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. -#serial 2 +#serial 3 # _AM_OUTPUT_DEPENDENCY_COMMANDS # ------------------------------ @@ -396,54 +340,31 @@ AC_DEFUN([AM_OUTPUT_DEPENDENCY_COMMANDS] [AMDEP_TRUE="$AMDEP_TRUE" ac_aux_dir="$ac_aux_dir"]) ]) -# Like AC_CONFIG_HEADER, but automatically create stamp file. -*- Autoconf -*- - -# Copyright (C) 1996, 1997, 2000, 2001, 2003 Free Software Foundation, Inc. - -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. - -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA -# 02110-1301, USA. +# Copyright (C) 1996, 1997, 2000, 2001, 2003, 2005 +# Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. -# serial 7 +# serial 8 # AM_CONFIG_HEADER is obsolete. It has been replaced by AC_CONFIG_HEADERS. AU_DEFUN([AM_CONFIG_HEADER], [AC_CONFIG_HEADERS($@)]) -# Do all the work for Automake. -*- Autoconf -*- +# Do all the work for Automake. -*- Autoconf -*- -# This macro actually does too much some checks are only needed if -# your package does certain things. But this isn't really a big deal. - -# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 +# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 # Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. - -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA -# 02110-1301, USA. +# serial 12 -# serial 11 +# This macro actually does too much. Some checks are only needed if +# your package does certain things. But this isn't really a big deal. # AM_INIT_AUTOMAKE(PACKAGE, VERSION, [NO-DEFINE]) # AM_INIT_AUTOMAKE([OPTIONS]) @@ -545,51 +466,27 @@ for _am_header in $config_headers :; do done echo "timestamp for $1" >`AS_DIRNAME([$1])`/stamp-h[]$_am_stamp_count]) +# Copyright (C) 2001, 2003, 2005 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + # AM_PROG_INSTALL_SH # ------------------ # Define $install_sh. - -# Copyright (C) 2001, 2003 Free Software Foundation, Inc. - -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. - -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA -# 02110-1301, USA. - AC_DEFUN([AM_PROG_INSTALL_SH], [AC_REQUIRE([AM_AUX_DIR_EXPAND])dnl install_sh=${install_sh-"$am_aux_dir/install-sh"} AC_SUBST(install_sh)]) -# -*- Autoconf -*- -# Copyright (C) 2003 Free Software Foundation, Inc. - -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. - -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA -# 02110-1301, USA. +# Copyright (C) 2003, 2005 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. -# serial 1 +# serial 2 # Check whether the underlying file-system supports filenames # with a leading dot. For instance MS-DOS doesn't. @@ -604,28 +501,17 @@ fi rmdir .tst 2>/dev/null AC_SUBST([am__leading_dot])]) -# Add --enable-maintainer-mode option to configure. +# Add --enable-maintainer-mode option to configure. -*- Autoconf -*- # From Jim Meyering -# Copyright (C) 1996, 1998, 2000, 2001, 2002, 2003, 2004 +# Copyright (C) 1996, 1998, 2000, 2001, 2002, 2003, 2004, 2005 # Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. - -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA -# 02110-1301, USA. - -# serial 3 +# serial 4 AC_DEFUN([AM_MAINTAINER_MODE], [AC_MSG_CHECKING([whether to enable maintainer-specific portions of Makefiles]) @@ -644,26 +530,15 @@ AC_DEFUN([AM_MAINTAINER_MODE], AU_DEFUN([jm_MAINTAINER_MODE], [AM_MAINTAINER_MODE]) -# Check to see how 'make' treats includes. -*- Autoconf -*- - -# Copyright (C) 2001, 2002, 2003 Free Software Foundation, Inc. +# Check to see how 'make' treats includes. -*- Autoconf -*- -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. - -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA -# 02110-1301, USA. +# Copyright (C) 2001, 2002, 2003, 2005 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. -# serial 2 +# serial 3 # AM_MAKE_INCLUDE() # ----------------- @@ -707,27 +582,16 @@ AC_MSG_RESULT([$_am_result]) rm -f confinc confmf ]) -# -*- Autoconf -*- - - -# Copyright (C) 1997, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. - -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. +# Fake the existence of programs that GNU maintainers use. -*- Autoconf -*- -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA -# 02110-1301, USA. +# Copyright (C) 1997, 1999, 2000, 2001, 2003, 2005 +# Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. -# serial 3 +# serial 4 # AM_MISSING_PROG(NAME, PROGRAM) # ------------------------------ @@ -753,27 +617,16 @@ else fi ]) +# Copyright (C) 2003, 2004, 2005 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. + # AM_PROG_MKDIR_P # --------------- # Check whether `mkdir -p' is supported, fallback to mkinstalldirs otherwise. - -# Copyright (C) 2003, 2004 Free Software Foundation, Inc. - -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. - -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA -# 02110-1301, USA. - +# # Automake 1.8 used `mkdir -m 0755 -p --' to ensure that directories # created by `make install' are always world readable, even if the # installer happens to have an overly restrictive umask (e.g. 077). @@ -827,26 +680,15 @@ else fi AC_SUBST([mkdir_p])]) -# Helper functions for option handling. -*- Autoconf -*- - -# Copyright (C) 2001, 2002, 2003 Free Software Foundation, Inc. +# Helper functions for option handling. -*- Autoconf -*- -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. - -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA -# 02110-1301, USA. +# Copyright (C) 2001, 2002, 2003, 2005 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. -# serial 2 +# serial 3 # _AM_MANGLE_OPTION(NAME) # ----------------------- @@ -871,28 +713,16 @@ AC_DEFUN([_AM_SET_OPTIONS], AC_DEFUN([_AM_IF_OPTION], [m4_ifset(_AM_MANGLE_OPTION([$1]), [$2], [$3])]) -# -# Check to make sure that the build environment is sane. -# +# Check to make sure that the build environment is sane. -*- Autoconf -*- -# Copyright (C) 1996, 1997, 2000, 2001, 2003 Free Software Foundation, Inc. - -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. - -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA -# 02110-1301, USA. +# Copyright (C) 1996, 1997, 2000, 2001, 2003, 2005 +# Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. -# serial 3 +# serial 4 # AM_SANITY_CHECK # --------------- @@ -935,25 +765,14 @@ Check your system clock]) fi AC_MSG_RESULT(yes)]) -# AM_PROG_INSTALL_STRIP - -# Copyright (C) 2001, 2003 Free Software Foundation, Inc. - -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. - -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA -# 02110-1301, USA. +# Copyright (C) 2001, 2003, 2005 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. +# AM_PROG_INSTALL_STRIP +# --------------------- # One issue with vendor `install' (even GNU) is that you can't # specify the program used to strip binaries. This is especially # annoying in cross-compiling environments, where the build's strip @@ -976,25 +795,13 @@ AC_SUBST([INSTALL_STRIP_PROGRAM])]) # Check how to create a tarball. -*- Autoconf -*- -# Copyright (C) 2004 Free Software Foundation, Inc. - -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2, or (at your option) -# any later version. - -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. - -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA -# 02110-1301, USA. - -# serial 1 +# Copyright (C) 2004, 2005 Free Software Foundation, Inc. +# +# This file is free software; the Free Software Foundation +# gives unlimited permission to copy and/or distribute it, +# with or without modifications, as long as this notice is preserved. +# serial 2 # _AM_PROG_TAR(FORMAT) # -------------------- diff -uprN binutils-2.16.91.0.1/opcodes/alpha-opc.c binutils-2.16.91.0.2/opcodes/alpha-opc.c --- binutils-2.16.91.0.1/opcodes/alpha-opc.c 2005-05-10 15:46:53.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/alpha-opc.c 2005-07-20 12:27:28.544986623 -0700 @@ -1,5 +1,5 @@ /* alpha-opc.c -- Alpha AXP opcode list - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. Contributed by Richard Henderson , patterned after the PPC opcode handling written by Ian Lance Taylor. @@ -54,28 +54,147 @@ _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital Order Number EC-QAEQB-TE, preliminary revision dated April 1995. */ -/* Local insertion and extraction functions */ +/* The RB field when it is the same as the RA field in the same insn. + This operand is marked fake. The insertion function just copies + the RA field into the RB field, and the extraction function just + checks that the fields are the same. */ -static unsigned insert_rba PARAMS((unsigned, int, const char **)); -static unsigned insert_rca PARAMS((unsigned, int, const char **)); -static unsigned insert_za PARAMS((unsigned, int, const char **)); -static unsigned insert_zb PARAMS((unsigned, int, const char **)); -static unsigned insert_zc PARAMS((unsigned, int, const char **)); -static unsigned insert_bdisp PARAMS((unsigned, int, const char **)); -static unsigned insert_jhint PARAMS((unsigned, int, const char **)); -static unsigned insert_ev6hwjhint PARAMS((unsigned, int, const char **)); - -static int extract_rba PARAMS((unsigned, int *)); -static int extract_rca PARAMS((unsigned, int *)); -static int extract_za PARAMS((unsigned, int *)); -static int extract_zb PARAMS((unsigned, int *)); -static int extract_zc PARAMS((unsigned, int *)); -static int extract_bdisp PARAMS((unsigned, int *)); -static int extract_jhint PARAMS((unsigned, int *)); -static int extract_ev6hwjhint PARAMS((unsigned, int *)); +static unsigned +insert_rba (unsigned insn, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | (((insn >> 21) & 0x1f) << 16); +} +static int +extract_rba (unsigned insn, int *invalid) +{ + if (invalid != (int *) NULL + && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) + *invalid = 1; + return 0; +} + +/* The same for the RC field. */ + +static unsigned +insert_rca (unsigned insn, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((insn >> 21) & 0x1f); +} + +static int +extract_rca (unsigned insn, int *invalid) +{ + if (invalid != (int *) NULL + && ((insn >> 21) & 0x1f) != (insn & 0x1f)) + *invalid = 1; + return 0; +} + +/* Fake arguments in which the registers must be set to ZERO. */ + +static unsigned +insert_za (unsigned insn, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | (31 << 21); +} + +static int +extract_za (unsigned insn, int *invalid) +{ + if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31) + *invalid = 1; + return 0; +} + +static unsigned +insert_zb (unsigned insn, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | (31 << 16); +} + +static int +extract_zb (unsigned insn, int *invalid) +{ + if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31) + *invalid = 1; + return 0; +} + +static unsigned +insert_zc (unsigned insn, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | 31; +} + +static int +extract_zc (unsigned insn, int *invalid) +{ + if (invalid != (int *) NULL && (insn & 0x1f) != 31) + *invalid = 1; + return 0; +} + + +/* The displacement field of a Branch format insn. */ + +static unsigned +insert_bdisp (unsigned insn, int value, const char **errmsg) +{ + if (errmsg != (const char **)NULL && (value & 3)) + *errmsg = _("branch operand unaligned"); + return insn | ((value / 4) & 0x1FFFFF); +} + +static int +extract_bdisp (unsigned insn, int *invalid ATTRIBUTE_UNUSED) +{ + return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000); +} + +/* The hint field of a JMP/JSR insn. */ + +static unsigned +insert_jhint (unsigned insn, int value, const char **errmsg) +{ + if (errmsg != (const char **)NULL && (value & 3)) + *errmsg = _("jump hint unaligned"); + return insn | ((value / 4) & 0x3FFF); +} + +static int +extract_jhint (unsigned insn, int *invalid ATTRIBUTE_UNUSED) +{ + return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000); +} + +/* The hint field of an EV6 HW_JMP/JSR insn. */ + +static unsigned +insert_ev6hwjhint (unsigned insn, int value, const char **errmsg) +{ + if (errmsg != (const char **)NULL && (value & 3)) + *errmsg = _("jump hint unaligned"); + return insn | ((value / 4) & 0x1FFF); +} + +static int +extract_ev6hwjhint (unsigned insn, int *invalid ATTRIBUTE_UNUSED) +{ + return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000); +} -/* The operands table */ +/* The operands table. */ const struct alpha_operand alpha_operands[] = { @@ -84,7 +203,7 @@ const struct alpha_operand alpha_operand #define UNUSED 0 { 0, 0, 0, 0, 0, 0 }, - /* The plain integer register fields */ + /* The plain integer register fields. */ #define RA (UNUSED + 1) { 5, 21, 0, AXP_OPERAND_IR, 0, 0 }, #define RB (RA + 1) @@ -92,7 +211,7 @@ const struct alpha_operand alpha_operand #define RC (RB + 1) { 5, 0, 0, AXP_OPERAND_IR, 0, 0 }, - /* The plain fp register fields */ + /* The plain fp register fields. */ #define FA (RC + 1) { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 }, #define FB (FA + 1) @@ -100,7 +219,7 @@ const struct alpha_operand alpha_operand #define FC (FB + 1) { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 }, - /* The integer registers when they are ZERO */ + /* The integer registers when they are ZERO. */ #define ZA (FC + 1) { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za }, #define ZB (ZA + 1) @@ -108,53 +227,53 @@ const struct alpha_operand alpha_operand #define ZC (ZB + 1) { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc }, - /* The RB field when it needs parentheses */ + /* The RB field when it needs parentheses. */ #define PRB (ZC + 1) { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 }, - /* The RB field when it needs parentheses _and_ a preceding comma */ + /* The RB field when it needs parentheses _and_ a preceding comma. */ #define CPRB (PRB + 1) { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 }, - /* The RB field when it must be the same as the RA field */ + /* The RB field when it must be the same as the RA field. */ #define RBA (CPRB + 1) { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba }, - /* The RC field when it must be the same as the RB field */ + /* The RC field when it must be the same as the RB field. */ #define RCA (RBA + 1) { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca }, - /* The RC field when it can *default* to RA */ + /* The RC field when it can *default* to RA. */ #define DRC1 (RCA + 1) { 5, 0, 0, AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, - /* The RC field when it can *default* to RB */ + /* The RC field when it can *default* to RB. */ #define DRC2 (DRC1 + 1) { 5, 0, 0, AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, - /* The FC field when it can *default* to RA */ + /* The FC field when it can *default* to RA. */ #define DFC1 (DRC2 + 1) { 5, 0, 0, AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 }, - /* The FC field when it can *default* to RB */ + /* The FC field when it can *default* to RB. */ #define DFC2 (DFC1 + 1) { 5, 0, 0, AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 }, - /* The unsigned 8-bit literal of Operate format insns */ + /* The unsigned 8-bit literal of Operate format insns. */ #define LIT (DFC2 + 1) { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 }, /* The signed 16-bit displacement of Memory format insns. From here - we can't tell what relocation should be used, so don't use a default. */ + we can't tell what relocation should be used, so don't use a default. */ #define MDISP (LIT + 1) { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 }, - /* The signed "23-bit" aligned displacement of Branch format insns */ + /* The signed "23-bit" aligned displacement of Branch format insns. */ #define BDISP (MDISP + 1) { 21, 0, BFD_RELOC_23_PCREL_S2, AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp }, @@ -163,23 +282,23 @@ const struct alpha_operand alpha_operand #define PALFN (BDISP + 1) { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 }, - /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */ + /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint. */ #define JMPHINT (PALFN + 1) { 14, 0, BFD_RELOC_ALPHA_HINT, AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, insert_jhint, extract_jhint }, - /* The optional hint to RET/JSR_COROUTINE */ + /* The optional hint to RET/JSR_COROUTINE. */ #define RETHINT (JMPHINT + 1) { 14, 0, -RETHINT, AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 }, - /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns */ + /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns. */ #define EV4HWDISP (RETHINT + 1) #define EV6HWDISP (EV4HWDISP) { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, - /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */ + /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns. */ #define EV4HWINDEX (EV4HWDISP + 1) { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, @@ -188,20 +307,20 @@ const struct alpha_operand alpha_operand #define EV4EXTHWINDEX (EV4HWINDEX + 1) { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, - /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */ + /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns. */ #define EV5HWDISP (EV4EXTHWINDEX + 1) { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 }, - /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */ + /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns. */ #define EV5HWINDEX (EV5HWDISP + 1) { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, /* The 16-bit combined index/scoreboard mask for the ev6 - hw_m[ft]pr (pal19/pal1d) insns */ + hw_m[ft]pr (pal19/pal1d) insns. */ #define EV6HWINDEX (EV5HWINDEX + 1) { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 }, - /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn */ + /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn. */ #define EV6HWJMPHINT (EV6HWINDEX+ 1) { 8, 0, -EV6HWJMPHINT, AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW, @@ -210,230 +329,57 @@ const struct alpha_operand alpha_operand const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands); -/* The RB field when it is the same as the RA field in the same insn. - This operand is marked fake. The insertion function just copies - the RA field into the RB field, and the extraction function just - checks that the fields are the same. */ - -static unsigned -insert_rba(insn, value, errmsg) - unsigned insn; - int value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | (((insn >> 21) & 0x1f) << 16); -} - -static int -extract_rba(insn, invalid) - unsigned insn; - int *invalid; -{ - if (invalid != (int *) NULL - && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) - *invalid = 1; - return 0; -} - - -/* The same for the RC field */ - -static unsigned -insert_rca(insn, value, errmsg) - unsigned insn; - int value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | ((insn >> 21) & 0x1f); -} - -static int -extract_rca(insn, invalid) - unsigned insn; - int *invalid; -{ - if (invalid != (int *) NULL - && ((insn >> 21) & 0x1f) != (insn & 0x1f)) - *invalid = 1; - return 0; -} - - -/* Fake arguments in which the registers must be set to ZERO */ - -static unsigned -insert_za(insn, value, errmsg) - unsigned insn; - int value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | (31 << 21); -} - -static int -extract_za(insn, invalid) - unsigned insn; - int *invalid; -{ - if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31) - *invalid = 1; - return 0; -} - -static unsigned -insert_zb(insn, value, errmsg) - unsigned insn; - int value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | (31 << 16); -} - -static int -extract_zb(insn, invalid) - unsigned insn; - int *invalid; -{ - if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31) - *invalid = 1; - return 0; -} - -static unsigned -insert_zc(insn, value, errmsg) - unsigned insn; - int value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - return insn | 31; -} - -static int -extract_zc(insn, invalid) - unsigned insn; - int *invalid; -{ - if (invalid != (int *) NULL && (insn & 0x1f) != 31) - *invalid = 1; - return 0; -} - - -/* The displacement field of a Branch format insn. */ - -static unsigned -insert_bdisp(insn, value, errmsg) - unsigned insn; - int value; - const char **errmsg; -{ - if (errmsg != (const char **)NULL && (value & 3)) - *errmsg = _("branch operand unaligned"); - return insn | ((value / 4) & 0x1FFFFF); -} - -static int -extract_bdisp(insn, invalid) - unsigned insn; - int *invalid ATTRIBUTE_UNUSED; -{ - return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000); -} - - -/* The hint field of a JMP/JSR insn. */ - -static unsigned -insert_jhint(insn, value, errmsg) - unsigned insn; - int value; - const char **errmsg; -{ - if (errmsg != (const char **)NULL && (value & 3)) - *errmsg = _("jump hint unaligned"); - return insn | ((value / 4) & 0x3FFF); -} - -static int -extract_jhint(insn, invalid) - unsigned insn; - int *invalid ATTRIBUTE_UNUSED; -{ - return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000); -} - -/* The hint field of an EV6 HW_JMP/JSR insn. */ - -static unsigned -insert_ev6hwjhint(insn, value, errmsg) - unsigned insn; - int value; - const char **errmsg; -{ - if (errmsg != (const char **)NULL && (value & 3)) - *errmsg = _("jump hint unaligned"); - return insn | ((value / 4) & 0x1FFF); -} - -static int -extract_ev6hwjhint(insn, invalid) - unsigned insn; - int *invalid ATTRIBUTE_UNUSED; -{ - return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000); -} - -/* Macros used to form opcodes */ +/* Macros used to form opcodes. */ -/* The main opcode */ +/* The main opcode. */ #define OP(x) (((x) & 0x3F) << 26) #define OP_MASK 0xFC000000 -/* Branch format instructions */ +/* Branch format instructions. */ #define BRA_(oo) OP(oo) #define BRA_MASK OP_MASK #define BRA(oo) BRA_(oo), BRA_MASK -/* Floating point format instructions */ +/* Floating point format instructions. */ #define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5)) #define FP_MASK (OP_MASK | 0xFFE0) #define FP(oo,fff) FP_(oo,fff), FP_MASK -/* Memory format instructions */ +/* Memory format instructions. */ #define MEM_(oo) OP(oo) #define MEM_MASK OP_MASK #define MEM(oo) MEM_(oo), MEM_MASK -/* Memory/Func Code format instructions */ +/* Memory/Func Code format instructions. */ #define MFC_(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF)) #define MFC_MASK (OP_MASK | 0xFFFF) #define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK -/* Memory/Branch format instructions */ +/* Memory/Branch format instructions. */ #define MBR_(oo,h) (OP(oo) | (((h) & 3) << 14)) #define MBR_MASK (OP_MASK | 0xC000) #define MBR(oo,h) MBR_(oo,h), MBR_MASK /* Operate format instructions. The OPRL variant specifies a - literal second argument. */ + literal second argument. */ #define OPR_(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5)) #define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000) #define OPR_MASK (OP_MASK | 0x1FE0) #define OPR(oo,ff) OPR_(oo,ff), OPR_MASK #define OPRL(oo,ff) OPRL_(oo,ff), OPR_MASK -/* Generic PALcode format instructions */ +/* Generic PALcode format instructions. */ #define PCD_(oo) OP(oo) #define PCD_MASK OP_MASK #define PCD(oo) PCD_(oo), PCD_MASK -/* Specific PALcode instructions */ +/* Specific PALcode instructions. */ #define SPCD_(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF)) #define SPCD_MASK 0xFFFFFFFF #define SPCD(oo,ffff) SPCD_(oo,ffff), SPCD_MASK -/* Hardware memory (hw_{ld,st}) instructions */ +/* Hardware memory (hw_{ld,st}) instructions. */ #define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12)) #define EV4HWMEM_MASK (OP_MASK | 0xF000) #define EV4HWMEM(oo,f) EV4HWMEM_(oo,f), EV4HWMEM_MASK @@ -459,7 +405,7 @@ extract_ev6hwjhint(insn, invalid) #define CIX AXP_OPCODE_CIX #define MAX AXP_OPCODE_MAX -/* Common combinations of arguments */ +/* Common combinations of arguments. */ #define ARG_NONE { 0 } #define ARG_BRA { RA, BDISP } #define ARG_FBRA { FA, BDISP } @@ -519,10 +465,10 @@ extract_ev6hwjhint(insn, invalid) EV56 UNA opcodes that were introduced as of the ev56 with presumably undefined results on previous implementations - that were not assigned to a particular extension. -*/ + that were not assigned to a particular extension. */ -const struct alpha_opcode alpha_opcodes[] = { +const struct alpha_opcode alpha_opcodes[] = +{ { "halt", SPCD(0x00,0x0000), BASE, ARG_NONE }, { "draina", SPCD(0x00,0x0002), BASE, ARG_NONE }, { "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE }, diff -uprN binutils-2.16.91.0.1/opcodes/arc-dis.c binutils-2.16.91.0.2/opcodes/arc-dis.c --- binutils-2.16.91.0.1/opcodes/arc-dis.c 2005-05-10 15:46:53.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/arc-dis.c 2005-07-20 12:27:28.546986294 -0700 @@ -1,5 +1,5 @@ /* Instruction printing code for the ARC. - Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002 + Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2005 Free Software Foundation, Inc. Contributed by Doug Evans (dje@cygnus.com). @@ -15,7 +15,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "ansidecl.h" #include "libiberty.h" @@ -34,11 +35,11 @@ #define dbg (0) #endif - /* Classification of the opcodes for the decoder to print the instructions. */ -typedef enum { +typedef enum +{ CLASS_A4_ARITH, CLASS_A4_OP3_GENERAL, CLASS_A4_FLAG, @@ -56,7 +57,6 @@ typedef enum { CLASS_A4_LR } a4_decoding_class; - #define BIT(word,n) ((word) & (1 << n)) #define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e))) #define OPCODE(word) (BITS ((word), 27, 31)) @@ -64,7 +64,6 @@ typedef enum { #define FIELDB(word) (BITS ((word), 15, 20)) #define FIELDC(word) (BITS ((word), 9, 14)) - /* FIELD D is signed in all of its uses, so we make sure argument is treated as signed for bit shifting purposes: */ #define FIELDD(word) (BITS (((signed int)word), 0, 8)) @@ -146,15 +145,15 @@ typedef enum { } \ while (0) -#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257)) -#define IS_REG(x) (field##x##isReg) -#define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT(x,"[","]","","") -#define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT(x,"",",[","",",[") -#define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT(x,",","]",",","]") -#define WRITE_FORMAT_x_RB(x) WRITE_FORMAT(x,"","]","","]") -#define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT(x,",","",",","") -#define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT(x,"",",","",",") -#define WRITE_FORMAT_x(x) WRITE_FORMAT(x,"","","","") +#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257)) +#define IS_REG(x) (field##x##isReg) +#define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT (x, "[","]","","") +#define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT (x, "",",[","",",[") +#define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT (x, ",","]",",","]") +#define WRITE_FORMAT_x_RB(x) WRITE_FORMAT (x, "","]","","]") +#define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT (x, ",","",",","") +#define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT (x, "",",","",",") +#define WRITE_FORMAT_x(x) WRITE_FORMAT (x, "","","","") #define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \ (IS_REG (x) ? cb1"%r"ca1 : \ usesAuxReg ? cb"%a"ca : \ @@ -169,25 +168,8 @@ typedef enum { static char comment_prefix[] = "\t; "; -static const char *core_reg_name PARAMS ((struct arcDisState *, int)); -static const char *aux_reg_name PARAMS ((struct arcDisState *, int)); -static const char *cond_code_name PARAMS ((struct arcDisState *, int)); -static const char *instruction_name - PARAMS ((struct arcDisState *, int, int, int *)); -static void mwerror PARAMS ((struct arcDisState *, const char *)); -static const char *post_address PARAMS ((struct arcDisState *, int)); -static void write_comments_ - PARAMS ((struct arcDisState *, int, int, long int)); -static void write_instr_name_ - PARAMS ((struct arcDisState *, const char *, int, int, int, int, int, int)); -static int dsmOneArcInst PARAMS ((bfd_vma, struct arcDisState *)); -static const char *_coreRegName PARAMS ((void *, int)); -static int decodeInstr PARAMS ((bfd_vma, disassemble_info *)); - static const char * -core_reg_name (state, val) - struct arcDisState * state; - int val; +core_reg_name (struct arcDisState * state, int val) { if (state->coreRegName) return (*state->coreRegName)(state->_this, val); @@ -195,9 +177,7 @@ core_reg_name (state, val) } static const char * -aux_reg_name (state, val) - struct arcDisState * state; - int val; +aux_reg_name (struct arcDisState * state, int val) { if (state->auxRegName) return (*state->auxRegName)(state->_this, val); @@ -205,9 +185,7 @@ aux_reg_name (state, val) } static const char * -cond_code_name (state, val) - struct arcDisState * state; - int val; +cond_code_name (struct arcDisState * state, int val) { if (state->condCodeName) return (*state->condCodeName)(state->_this, val); @@ -215,11 +193,10 @@ cond_code_name (state, val) } static const char * -instruction_name (state, op1, op2, flags) - struct arcDisState * state; - int op1; - int op2; - int * flags; +instruction_name (struct arcDisState * state, + int op1, + int op2, + int * flags) { if (state->instName) return (*state->instName)(state->_this, op1, op2, flags); @@ -227,18 +204,14 @@ instruction_name (state, op1, op2, flags } static void -mwerror (state, msg) - struct arcDisState * state; - const char * msg; +mwerror (struct arcDisState * state, const char * msg) { if (state->err != 0) (*state->err)(state->_this, (msg)); } static const char * -post_address (state, addr) - struct arcDisState * state; - int addr; +post_address (struct arcDisState * state, int addr) { static char id[3 * ARRAY_SIZE (state->addresses)]; int j, i = state->acnt; @@ -257,22 +230,16 @@ post_address (state, addr) return ""; } -static void my_sprintf PARAMS ((struct arcDisState *, char *, const char *, - ...)); - static void -my_sprintf VPARAMS ((struct arcDisState *state, char *buf, const char *format, - ...)) +arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...) { char *bp; const char *p; int size, leading_zero, regMap[2]; long auxNum; + va_list ap; - VA_OPEN (ap, format); - VA_FIXEDARG (ap, struct arcDisState *, state); - VA_FIXEDARG (ap, char *, buf); - VA_FIXEDARG (ap, const char *, format); + va_start (ap, format); bp = buf; *bp = 0; @@ -413,7 +380,7 @@ my_sprintf VPARAMS ((struct arcDisState if (ext) sprintf (bp, "%s", ext); else - my_sprintf (state, bp, "%h", val); + arc_sprintf (state, bp, "%h", val); } break; } @@ -435,15 +402,14 @@ my_sprintf VPARAMS ((struct arcDisState } DOCOMM: *bp = 0; - VA_CLOSE (ap); + va_end (ap); } static void -write_comments_(state, shimm, is_limm, limm_value) - struct arcDisState * state; - int shimm; - int is_limm; - long limm_value; +write_comments_(struct arcDisState * state, + int shimm, + int is_limm, + long limm_value) { if (state->commentBuffer != 0) { @@ -468,25 +434,25 @@ write_comments_(state, shimm, is_limm, l } } -#define write_comments2(x) write_comments_(state, x, is_limm, limm_value) -#define write_comments() write_comments2(0) +#define write_comments2(x) write_comments_ (state, x, is_limm, limm_value) +#define write_comments() write_comments2 (0) -static const char *condName[] = { +static const char *condName[] = +{ /* 0..15. */ "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" , "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz" }; static void -write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem) - struct arcDisState * state; - const char * instrName; - int cond; - int condCodeIsPartOfName; - int flag; - int signExtend; - int addrWriteBack; - int directMem; +write_instr_name_(struct arcDisState * state, + const char * instrName, + int cond, + int condCodeIsPartOfName, + int flag, + int signExtend, + int addrWriteBack, + int directMem) { strcpy (state->instrBuffer, instrName); @@ -540,7 +506,8 @@ write_instr_name_(state, instrName, cond } \ while (0) -enum { +enum +{ op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3, op_BC = 4, op_BLC = 5, op_LPC = 6, op_JC = 7, op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11, @@ -550,9 +517,7 @@ enum { extern disassemble_info tm_print_insn_info; static int -dsmOneArcInst (addr, state) - bfd_vma addr; - struct arcDisState * state; +dsmOneArcInst (bfd_vma addr, struct arcDisState * state) { int condCodeIsPartOfName = 0; a4_decoding_class decodingClass; @@ -641,7 +606,7 @@ dsmOneArcInst (addr, state) } else { - switch (BITS (state->words[0],10,11)) + switch (BITS (state->words[0], 10, 11)) { case 0: instrName = "ld"; @@ -665,14 +630,14 @@ dsmOneArcInst (addr, state) break; case op_ST: - if (BIT (state->words[0],25)) + if (BIT (state->words[0], 25)) { instrName = "sr"; decodingClass = CLASS_A4_SR; } else { - switch (BITS (state->words[0],22,23)) + switch (BITS (state->words[0], 22, 23)) { case 0: instrName = "st"; @@ -727,7 +692,7 @@ dsmOneArcInst (addr, state) case 0x3f: { decodingClass = CLASS_A4_OP3_SUBOPC3F; - switch( FIELDD (state->words[0]) ) + switch (FIELDD (state->words[0])) { case 0: instrName = "brk"; @@ -822,7 +787,7 @@ dsmOneArcInst (addr, state) case op_XOR: if (state->words[0] == 0x7fffffff) { - /* nop encoded as xor -1, -1, -1 */ + /* NOP encoded as xor -1, -1, -1. */ instrName = "nop"; decodingClass = CLASS_A4_OP3_SUBOPC3F; } @@ -866,7 +831,7 @@ dsmOneArcInst (addr, state) if (!repeatsOp) WRITE_FORMAT_COMMA_x (C); WRITE_NOP_COMMENT (); - my_sprintf (state, state->operandBuffer, formatString, + arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); } else @@ -874,7 +839,7 @@ dsmOneArcInst (addr, state) WRITE_FORMAT_x (B); if (!repeatsOp) WRITE_FORMAT_COMMA_x (C); - my_sprintf (state, state->operandBuffer, formatString, + arc_sprintf (state, state->operandBuffer, formatString, fieldB, fieldC); } write_comments (); @@ -891,13 +856,13 @@ dsmOneArcInst (addr, state) WRITE_FORMAT_x (A); WRITE_FORMAT_COMMA_x (B); WRITE_NOP_COMMENT (); - my_sprintf (state, state->operandBuffer, formatString, + arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB); } else { WRITE_FORMAT_x (B); - my_sprintf (state, state->operandBuffer, formatString, fieldB); + arc_sprintf (state, state->operandBuffer, formatString, fieldB); } write_comments (); break; @@ -905,17 +870,17 @@ dsmOneArcInst (addr, state) case CLASS_A4_FLAG: CHECK_FIELD_B (); CHECK_FLAG_COND_NULLIFY (); - flag = 0; /* this is the FLAG instruction -- it's redundant */ + flag = 0; /* This is the FLAG instruction -- it's redundant. */ write_instr_name (); WRITE_FORMAT_x (B); - my_sprintf (state, state->operandBuffer, formatString, fieldB); + arc_sprintf (state, state->operandBuffer, formatString, fieldB); write_comments (); break; case CLASS_A4_BRANCH: fieldA = BITS (state->words[0],7,26) << 2; - fieldA = (fieldA << 10) >> 10; /* make it signed */ + fieldA = (fieldA << 10) >> 10; /* Make it signed. */ fieldA += addr + 4; CHECK_FLAG_COND_NULLIFY (); flag = 0; @@ -932,8 +897,8 @@ dsmOneArcInst (addr, state) lr dest<- func addr; j [dest]" */ } - strcat (formatString, "%s"); /* address/label name */ - my_sprintf (state, state->operandBuffer, formatString, + strcat (formatString, "%s"); /* Address/label name. */ + arc_sprintf (state, state->operandBuffer, formatString, post_address (state, fieldA)); write_comments (); break; @@ -949,12 +914,12 @@ dsmOneArcInst (addr, state) if (!fieldBisReg) { fieldAisReg = 0; - fieldA = (fieldB >> 25) & 0x7F; /* flags */ + fieldA = (fieldB >> 25) & 0x7F; /* Flags. */ fieldB = (fieldB & 0xFFFFFF) << 2; state->flow = is_linked ? direct_call : direct_jump; add_target (fieldB); - /* screwy JLcc requires .jd mode to execute correctly - * but we pretend it is .nd (no delay slot). */ + /* Screwy JLcc requires .jd mode to execute correctly + but we pretend it is .nd (no delay slot). */ if (is_linked && state->nullifyMode == BR_exec_when_jump) state->nullifyMode = BR_exec_when_no_jump; } @@ -962,24 +927,24 @@ dsmOneArcInst (addr, state) { state->flow = is_linked ? indirect_call : indirect_jump; /* We should also treat this as indirect call if NOT linked - * but the preceding instruction was a "lr blink,[status]" - * and we have a delay slot with "add blink,blink,2". - * For now we can't detect such. */ + but the preceding instruction was a "lr blink,[status]" + and we have a delay slot with "add blink,blink,2". + For now we can't detect such. */ state->register_for_indirect_jump = fieldB; } write_instr_name (); strcat (formatString, - IS_REG (B) ? "[%r]" : "%s"); /* address/label name */ + IS_REG (B) ? "[%r]" : "%s"); /* Address/label name. */ if (fieldA != 0) { fieldAisReg = 0; WRITE_FORMAT_COMMA_x (A); } if (IS_REG (B)) - my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA); + arc_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA); else - my_sprintf (state, state->operandBuffer, formatString, + arc_sprintf (state, state->operandBuffer, formatString, post_address (state, fieldB), fieldA); write_comments (); break; @@ -1005,9 +970,9 @@ dsmOneArcInst (addr, state) state->_offset += fieldC; state->_mem_load = 1; - directMem = BIT (state->words[0],5); - addrWriteBack = BIT (state->words[0],3); - signExtend = BIT (state->words[0],0); + directMem = BIT (state->words[0], 5); + addrWriteBack = BIT (state->words[0], 3); + signExtend = BIT (state->words[0], 0); write_instr_name (); WRITE_FORMAT_x_COMMA_LB(A); @@ -1017,7 +982,7 @@ dsmOneArcInst (addr, state) fieldB = fieldC; WRITE_FORMAT_x_RB (C); - my_sprintf (state, state->operandBuffer, formatString, + arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); write_comments (); break; @@ -1036,7 +1001,7 @@ dsmOneArcInst (addr, state) state->_mem_load = 1; if (fieldBisReg) state->ea_reg1 = fieldB; - /* field B is either a shimm (same as fieldC) or limm (different!) + /* Field B is either a shimm (same as fieldC) or limm (different!) Say ea is not present, so only one of us will do the name lookup. */ else state->_offset += fieldB, state->_ea_present = 0; @@ -1063,7 +1028,7 @@ dsmOneArcInst (addr, state) else WRITE_FORMAT_RB (); } - my_sprintf (state, state->operandBuffer, formatString, + arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); write_comments (); break; @@ -1081,26 +1046,26 @@ dsmOneArcInst (addr, state) state->_offset = fieldA; if (fieldBisReg) state->ea_reg1 = fieldB; - /* field B is either a shimm (same as fieldA) or limm (different!) + /* Field B is either a shimm (same as fieldA) or limm (different!) Say ea is not present, so only one of us will do the name lookup. (for is_limm we do the name translation here). */ else state->_offset += fieldB, state->_ea_present = 0; - directMem = BIT(state->words[0],26); - addrWriteBack = BIT(state->words[0],24); + directMem = BIT (state->words[0], 26); + addrWriteBack = BIT (state->words[0], 24); - write_instr_name(); + write_instr_name (); WRITE_FORMAT_x_COMMA_LB(C); if (!fieldBisReg) { fieldB = state->_offset; - WRITE_FORMAT_x_RB(B); + WRITE_FORMAT_x_RB (B); } else { - WRITE_FORMAT_x(B); + WRITE_FORMAT_x (B); if (fieldBisReg && fieldA != 0) { fieldAisReg = 0; @@ -1109,9 +1074,9 @@ dsmOneArcInst (addr, state) else WRITE_FORMAT_RB(); } - my_sprintf (state, state->operandBuffer, formatString, + arc_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB, fieldA); - write_comments2(fieldA); + write_comments2 (fieldA); break; case CLASS_A4_SR: @@ -1119,37 +1084,36 @@ dsmOneArcInst (addr, state) CHECK_FIELD_B(); CHECK_FIELD_C(); - write_instr_name(); + write_instr_name (); WRITE_FORMAT_x_COMMA_LB(C); /* Try to print B as an aux reg if it is not a core reg. */ usesAuxReg = 1; - WRITE_FORMAT_x(B); - WRITE_FORMAT_RB(); - my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB); - write_comments(); + WRITE_FORMAT_x (B); + WRITE_FORMAT_RB (); + arc_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB); + write_comments (); break; case CLASS_A4_OP3_SUBOPC3F: - write_instr_name(); + write_instr_name (); state->operandBuffer[0] = '\0'; break; case CLASS_A4_LR: /* LR instruction */ - CHECK_FIELD_A(); - CHECK_FIELD_B(); + CHECK_FIELD_A (); + CHECK_FIELD_B (); - write_instr_name(); - WRITE_FORMAT_x_COMMA_LB(A); + write_instr_name (); + WRITE_FORMAT_x_COMMA_LB (A); /* Try to print B as an aux reg if it is not a core reg. */ usesAuxReg = 1; - WRITE_FORMAT_x(B); - WRITE_FORMAT_RB(); - my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB); - write_comments(); + WRITE_FORMAT_x (B); + WRITE_FORMAT_RB (); + arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB); + write_comments (); break; - default: mwerror (state, "Bad decoding class in ARC disassembler"); break; @@ -1161,23 +1125,23 @@ dsmOneArcInst (addr, state) /* Returns the name the user specified core extension register. */ + static const char * -_coreRegName(arg, regval) - void * arg ATTRIBUTE_UNUSED; - int regval; +_coreRegName(void * arg ATTRIBUTE_UNUSED, int regval) { return arcExtMap_coreRegName (regval); } /* Returns the name the user specified AUX extension register. */ + static const char * _auxRegName(void *_this ATTRIBUTE_UNUSED, int regval) { return arcExtMap_auxRegName(regval); } - /* Returns the name the user specified condition code name. */ + static const char * _condCodeName(void *_this ATTRIBUTE_UNUSED, int regval) { @@ -1185,6 +1149,7 @@ _condCodeName(void *_this ATTRIBUTE_UNUS } /* Returns the name the user specified extension instruction. */ + static const char * _instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags) { @@ -1193,15 +1158,15 @@ _instName (void *_this ATTRIBUTE_UNUSED, /* Decode an instruction returning the size of the instruction in bytes or zero if unrecognized. */ + static int -decodeInstr (address, info) - bfd_vma address; /* Address of this instruction. */ - disassemble_info * info; +decodeInstr (bfd_vma address, /* Address of this instruction. */ + disassemble_info * info) { int status; bfd_byte buffer[4]; - struct arcDisState s; /* ARC Disassembler state */ - void *stream = info->stream; /* output stream */ + struct arcDisState s; /* ARC Disassembler state. */ + void *stream = info->stream; /* Output stream. */ fprintf_ftype func = info->fprintf_func; int bytes; @@ -1218,9 +1183,9 @@ decodeInstr (address, info) s.words[0] = bfd_getl32(buffer); else s.words[0] = bfd_getb32(buffer); - /* always read second word in case of limm */ + /* Always read second word in case of limm. */ - /* we ignore the result since last insn may not have a limm */ + /* We ignore the result since last insn may not have a limm. */ status = (*info->read_memory_func) (address + 4, buffer, 4, info); if (info->endian == BFD_ENDIAN_LITTLE) s.words[1] = bfd_getl32(buffer); @@ -1233,23 +1198,24 @@ decodeInstr (address, info) s.condCodeName = _condCodeName; s.instName = _instName; - /* disassemble */ - bytes = dsmOneArcInst(address, (void *)&s); + /* Disassemble. */ + bytes = dsmOneArcInst (address, (void *)& s); - /* display the disassembly instruction */ - (*func) (stream, "%08x ", s.words[0]); + /* Display the disassembly instruction. */ + (*func) (stream, "%08lx ", s.words[0]); (*func) (stream, " "); - (*func) (stream, "%-10s ", s.instrBuffer); - if (__TRANSLATION_REQUIRED(s)) + if (__TRANSLATION_REQUIRED (s)) { bfd_vma addr = s.addresses[s.operandBuffer[1] - '0']; + (*info->print_address_func) ((bfd_vma) addr, info); (*func) (stream, "\n"); } else (*func) (stream, "%s",s.operandBuffer); + return s.instructionLen; } diff -uprN binutils-2.16.91.0.1/opcodes/arc-opc.c binutils-2.16.91.0.2/opcodes/arc-opc.c --- binutils-2.16.91.0.1/opcodes/arc-opc.c 2005-05-10 15:46:53.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/arc-opc.c 2005-07-20 12:27:28.552985305 -0700 @@ -1,5 +1,5 @@ /* Opcode table for the ARC. - Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2004 + Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2004, 2005 Free Software Foundation, Inc. Contributed by Doug Evans (dje@cygnus.com). @@ -22,14 +22,70 @@ #include "ansidecl.h" #include "bfd.h" #include "opcode/arc.h" +#include "opintl.h" +enum operand {OP_NONE,OP_REG,OP_SHIMM,OP_LIMM}; + +#define OPERANDS 3 + +enum operand ls_operand[OPERANDS]; + +struct arc_opcode *arc_ext_opcodes; +struct arc_ext_operand_value *arc_ext_operands; + +#define LS_VALUE 0 +#define LS_DEST 0 +#define LS_BASE 1 +#define LS_OFFSET 2 + +/* Given a format letter, yields the index into `arc_operands'. + eg: arc_operand_map['a'] = REGA. */ +unsigned char arc_operand_map[256]; + +/* Nonzero if we've seen an 'f' suffix (in certain insns). */ +static int flag_p; + +/* Nonzero if we've finished processing the 'f' suffix. */ +static int flagshimm_handled_p; + +/* Nonzero if we've seen a 'a' suffix (address writeback). */ +static int addrwb_p; + +/* Nonzero if we've seen a 'q' suffix (condition code). */ +static int cond_p; + +/* Nonzero if we've inserted a nullify condition. */ +static int nullify_p; + +/* The value of the a nullify condition we inserted. */ +static int nullify; + +/* Nonzero if we've inserted jumpflags. */ +static int jumpflags_p; + +/* Nonzero if we've inserted a shimm. */ +static int shimm_p; + +/* The value of the shimm we inserted (each insn only gets one but it can + appear multiple times). */ +static int shimm; + +/* Nonzero if we've inserted a limm (during assembly) or seen a limm + (during disassembly). */ +static int limm_p; + +/* The value of the limm we inserted. Each insn only gets one but it can + appear multiple times. */ +static long limm; + #define INSERT_FN(fn) \ -static arc_insn fn PARAMS ((arc_insn, const struct arc_operand *, \ - int, const struct arc_operand_value *, long, \ - const char **)) +static arc_insn fn (arc_insn, const struct arc_operand *, \ + int, const struct arc_operand_value *, long, \ + const char **) + #define EXTRACT_FN(fn) \ -static long fn PARAMS ((arc_insn *, const struct arc_operand *, \ - int, const struct arc_operand_value **, int *)) +static long fn (arc_insn *, const struct arc_operand *, \ + int, const struct arc_operand_value **, int *) INSERT_FN (insert_reg); INSERT_FN (insert_shimmfinish); @@ -60,20 +116,6 @@ EXTRACT_FN (extract_reladdr); EXTRACT_FN (extract_jumpflags); EXTRACT_FN (extract_unopmacro); -enum operand {OP_NONE,OP_REG,OP_SHIMM,OP_LIMM}; - -#define OPERANDS 3 - -enum operand ls_operand[OPERANDS]; - -struct arc_opcode *arc_ext_opcodes; -struct arc_ext_operand_value *arc_ext_operands; - -#define LS_VALUE 0 -#define LS_DEST 0 -#define LS_BASE 1 -#define LS_OFFSET 2 - /* Various types of ARC operands, including insn suffixes. */ /* Insn format values: @@ -124,39 +166,39 @@ struct arc_ext_operand_value *arc_ext_op const struct arc_operand arc_operands[] = { -/* place holder (??? not sure if needed). */ +/* Place holder (??? not sure if needed). */ #define UNUSED 0 { 0, 0, 0, 0, 0, 0 }, -/* register A or shimm/limm indicator. */ +/* Register A or shimm/limm indicator. */ #define REGA (UNUSED + 1) { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, -/* register B or shimm/limm indicator. */ +/* Register B or shimm/limm indicator. */ #define REGB (REGA + 1) { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, -/* register C or shimm/limm indicator. */ +/* Register C or shimm/limm indicator. */ #define REGC (REGB + 1) { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, -/* fake operand used to insert shimm value into most instructions. */ +/* Fake operand used to insert shimm value into most instructions. */ #define SHIMMFINISH (REGC + 1) { 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 }, -/* fake operand used to insert limm value into most instructions. */ +/* Fake operand used to insert limm value into most instructions. */ #define LIMMFINISH (SHIMMFINISH + 1) { 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 }, -/* shimm operand when there is no reg indicator (st). */ +/* Shimm operand when there is no reg indicator (st). */ #define ST_OFFSET (LIMMFINISH + 1) { 'o', 9, 0, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_STORE, insert_offset, extract_st_offset }, -/* shimm operand when there is no reg indicator (ld). */ +/* Shimm operand when there is no reg indicator (ld). */ #define LD_OFFSET (ST_OFFSET + 1) { 'O', 9, 0,ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_LOAD, insert_offset, extract_ld_offset }, -/* operand for base. */ +/* Operand for base. */ #define BASE (LD_OFFSET + 1) { 's', 6, ARC_SHIFT_REGB, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_base, extract_reg}, @@ -176,88 +218,88 @@ const struct arc_operand arc_operands[] #define SYNTAX_LD (SYNTAX_ST + 1) { '3', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_ld_syntax, extract_ld_syntax }, -/* flag update bit (insertion is defered until we know how). */ +/* Flag update bit (insertion is defered until we know how). */ #define FLAG (SYNTAX_LD + 1) { 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag }, -/* fake utility operand to finish 'f' suffix handling. */ +/* Fake utility operand to finish 'f' suffix handling. */ #define FLAGFINISH (FLAG + 1) { 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 }, -/* fake utility operand to set the 'f' flag for the "flag" insn. */ +/* Fake utility operand to set the 'f' flag for the "flag" insn. */ #define FLAGINSN (FLAGFINISH + 1) { 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 }, -/* branch delay types. */ +/* Branch delay types. */ #define DELAY (FLAGINSN + 1) { 'n', 2, 5, ARC_OPERAND_SUFFIX , insert_nullify, 0 }, -/* conditions. */ +/* Conditions. */ #define COND (DELAY + 1) { 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond }, -/* set `cond_p' to 1 to ensure a constant is treated as a limm. */ +/* Set `cond_p' to 1 to ensure a constant is treated as a limm. */ #define FORCELIMM (COND + 1) { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm, 0 }, -/* branch address; b, bl, and lp insns. */ +/* Branch address; b, bl, and lp insns. */ #define BRANCH (FORCELIMM + 1) { 'B', 20, 7, (ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED) | ARC_OPERAND_ERROR, insert_reladdr, extract_reladdr }, -/* jump address; j insn (this is basically the same as 'L' except that the +/* Jump address; j insn (this is basically the same as 'L' except that the value is right shifted by 2). */ #define JUMP (BRANCH + 1) { 'J', 24, 32, ARC_OPERAND_ERROR | (ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE), insert_absaddr, 0 }, -/* jump flags; j{,l} insn value or'ed into 'J' addr for flag values. */ +/* Jump flags; j{,l} insn value or'ed into 'J' addr for flag values. */ #define JUMPFLAGS (JUMP + 1) { 'j', 6, 26, ARC_OPERAND_JUMPFLAGS | ARC_OPERAND_ERROR, insert_jumpflags, extract_jumpflags }, -/* size field, stored in bit 1,2. */ +/* Size field, stored in bit 1,2. */ #define SIZE1 (JUMPFLAGS + 1) { 'z', 2, 1, ARC_OPERAND_SUFFIX, 0, 0 }, -/* size field, stored in bit 10,11. */ +/* Size field, stored in bit 10,11. */ #define SIZE10 (SIZE1 + 1) { 'Z', 2, 10, ARC_OPERAND_SUFFIX, 0, 0 }, -/* size field, stored in bit 22,23. */ +/* Size field, stored in bit 22,23. */ #define SIZE22 (SIZE10 + 1) { 'y', 2, 22, ARC_OPERAND_SUFFIX, 0, 0 }, -/* sign extend field, stored in bit 0. */ +/* Sign extend field, stored in bit 0. */ #define SIGN0 (SIZE22 + 1) { 'x', 1, 0, ARC_OPERAND_SUFFIX, 0, 0 }, -/* sign extend field, stored in bit 9. */ +/* Sign extend field, stored in bit 9. */ #define SIGN9 (SIGN0 + 1) { 'X', 1, 9, ARC_OPERAND_SUFFIX, 0, 0 }, -/* address write back, stored in bit 3. */ +/* Address write back, stored in bit 3. */ #define ADDRESS3 (SIGN9 + 1) { 'w', 1, 3, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, -/* address write back, stored in bit 12. */ +/* Address write back, stored in bit 12. */ #define ADDRESS12 (ADDRESS3 + 1) { 'W', 1, 12, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, -/* address write back, stored in bit 24. */ +/* Address write back, stored in bit 24. */ #define ADDRESS24 (ADDRESS12 + 1) { 'v', 1, 24, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, -/* cache bypass, stored in bit 5. */ +/* Cache bypass, stored in bit 5. */ #define CACHEBYPASS5 (ADDRESS24 + 1) { 'e', 1, 5, ARC_OPERAND_SUFFIX, 0, 0 }, -/* cache bypass, stored in bit 14. */ +/* Cache bypass, stored in bit 14. */ #define CACHEBYPASS14 (CACHEBYPASS5 + 1) { 'E', 1, 14, ARC_OPERAND_SUFFIX, 0, 0 }, -/* cache bypass, stored in bit 26. */ +/* Cache bypass, stored in bit 26. */ #define CACHEBYPASS26 (CACHEBYPASS14 + 1) { 'D', 1, 26, ARC_OPERAND_SUFFIX, 0, 0 }, -/* unop macro, used to copy REGB to REGC. */ +/* Unop macro, used to copy REGB to REGC. */ #define UNOPMACRO (CACHEBYPASS26 + 1) { 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro }, @@ -275,646 +317,249 @@ const struct arc_operand arc_operands[] #define AUXREG (REG + 1) { 'A', 9, 0, ARC_MOD_AUXREG, 0, 0 }, -/* end of list place holder. */ +/* End of list place holder. */ { 0, 0, 0, 0, 0, 0 } }; -/* Given a format letter, yields the index into `arc_operands'. - eg: arc_operand_map['a'] = REGA. */ -unsigned char arc_operand_map[256]; - -/* ARC instructions. - - Longer versions of insns must appear before shorter ones (if gas sees - "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is - junk). This isn't necessary for `ld' because of the trailing ']'. +/* Insert a value into a register field. + If REG is NULL, then this is actually a constant. - Instructions that are really macros based on other insns must appear - before the real insn so they're chosen when disassembling. Eg: The `mov' - insn is really the `and' insn. */ + We must also handle auxiliary registers for lr/sr insns. */ -struct arc_opcode arc_opcodes[] = +static arc_insn +insert_reg (arc_insn insn, + const struct arc_operand *operand, + int mods, + const struct arc_operand_value *reg, + long value, + const char **errmsg) { - /* Base case instruction set (core versions 5-8) */ + static char buf[100]; + enum operand op_type = OP_NONE; - /* "mov" is really an "and". */ - { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12), ARC_MACH_5, 0, 0 }, - /* "asl" is really an "add". */ - { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 }, - /* "lsl" is really an "add". */ - { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 }, - /* "nop" is really an "xor". */ - { "nop", 0x7fffffff, 0x7fffffff, ARC_MACH_5, 0, 0 }, - /* "rlc" is really an "adc". */ - { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9), ARC_MACH_5, 0, 0 }, - { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9), ARC_MACH_5, 0, 0 }, - { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8), ARC_MACH_5, 0, 0 }, - { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12), ARC_MACH_5, 0, 0 }, - { "asr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(1), ARC_MACH_5, 0, 0 }, - { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14), ARC_MACH_5, 0, 0 }, - { "b%q%.n %B", I(-1), I(4), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - { "bl%q%.n %B", I(-1), I(5), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - { "extb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(7), ARC_MACH_5, 0, 0 }, - { "extw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(8), ARC_MACH_5, 0, 0 }, - { "flag%.q %b%G%S%L", I(-1)|A(-1)|C(-1), I(3)|A(ARC_REG_SHIMM_UPDATE)|C(0), ARC_MACH_5, 0, 0 }, - { "brk", 0x1ffffe00, 0x1ffffe00, ARC_MACH_7, 0, 0 }, - { "sleep", 0x1ffffe01, 0x1ffffe01, ARC_MACH_7, 0, 0 }, - { "swi", 0x1ffffe02, 0x1ffffe02, ARC_MACH_8, 0, 0 }, - /* %Q: force cond_p=1 -> no shimm values. This insn allows an - optional flags spec. */ - { "j%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - { "j%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - /* This insn allows an optional flags spec. */ - { "jl%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - { "jl%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - /* Put opcode 1 ld insns first so shimm gets prefered over limm. - "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */ - { "ld%Z%.X%.W%.E %a,[%s]%S%L%1", I(-1)|R(-1,13,1)|R(-1,0,511), I(1)|R(0,13,1)|R(0,0,511), ARC_MACH_5, 0, 0 }, - { "ld%z%.x%.w%.e %a,[%s]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 }, - { "ld%z%.x%.w%.e %a,[%s,%O]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 }, - { "ld%Z%.X%.W%.E %a,[%s,%O]%S%L%3", I(-1)|R(-1,13,1), I(1)|R(0,13,1), ARC_MACH_5, 0, 0 }, - { "lp%q%.n %B", I(-1), I(6), ARC_MACH_5, 0, 0 }, - { "lr %a,[%Ab]%S%L", I(-1)|C(-1), I(1)|C(0x10), ARC_MACH_5, 0, 0 }, - { "lsr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(2), ARC_MACH_5, 0, 0 }, - { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13), ARC_MACH_5, 0, 0 }, - { "ror%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(3), ARC_MACH_5, 0, 0 }, - { "rrc%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(4), ARC_MACH_5, 0, 0 }, - { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11), ARC_MACH_5, 0, 0 }, - { "sexb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(5), ARC_MACH_5, 0, 0 }, - { "sexw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(6), ARC_MACH_5, 0, 0 }, - { "sr %c,[%Ab]%S%L", I(-1)|A(-1), I(2)|A(0x10), ARC_MACH_5, 0, 0 }, - /* "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */ - { "st%y%.v%.D %c,[%s]%L%S%0", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 }, - { "st%y%.v%.D %c,[%s,%o]%S%L%2", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 }, - { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10), ARC_MACH_5, 0, 0 }, - { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15), ARC_MACH_5, 0, 0 } -}; + if (reg == NULL) + { + /* We have a constant that also requires a value stored in a register + field. Handle these by updating the register field and saving the + value for later handling by either %S (shimm) or %L (limm). */ -const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]); + /* Try to use a shimm value before a limm one. */ + if (ARC_SHIMM_CONST_P (value) + /* If we've seen a conditional suffix we have to use a limm. */ + && !cond_p + /* If we already have a shimm value that is different than ours + we have to use a limm. */ + && (!shimm_p || shimm == value)) + { + int marker; -const struct arc_operand_value arc_reg_names[] = -{ - /* Core register set r0-r63. */ + op_type = OP_SHIMM; + /* Forget about shimm as dest mlm. */ - /* r0-r28 - general purpose registers. */ - { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 }, - { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 }, - { "r6", 6, REG, 0 }, { "r7", 7, REG, 0 }, { "r8", 8, REG, 0 }, - { "r9", 9, REG, 0 }, { "r10", 10, REG, 0 }, { "r11", 11, REG, 0 }, - { "r12", 12, REG, 0 }, { "r13", 13, REG, 0 }, { "r14", 14, REG, 0 }, - { "r15", 15, REG, 0 }, { "r16", 16, REG, 0 }, { "r17", 17, REG, 0 }, - { "r18", 18, REG, 0 }, { "r19", 19, REG, 0 }, { "r20", 20, REG, 0 }, - { "r21", 21, REG, 0 }, { "r22", 22, REG, 0 }, { "r23", 23, REG, 0 }, - { "r24", 24, REG, 0 }, { "r25", 25, REG, 0 }, { "r26", 26, REG, 0 }, - { "r27", 27, REG, 0 }, { "r28", 28, REG, 0 }, - /* Maskable interrupt link register. */ - { "ilink1", 29, REG, 0 }, - /* Maskable interrupt link register. */ - { "ilink2", 30, REG, 0 }, - /* Branch-link register. */ - { "blink", 31, REG, 0 }, + if ('a' != operand->fmt) + { + shimm_p = 1; + shimm = value; + flagshimm_handled_p = 1; + marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM; + } + else + { + /* Don't request flag setting on shimm as dest. */ + marker = ARC_REG_SHIMM; + } + insn |= marker << operand->shift; + /* insn |= value & 511; - done later. */ + } + /* We have to use a limm. If we've already seen one they must match. */ + else if (!limm_p || limm == value) + { + op_type = OP_LIMM; + limm_p = 1; + limm = value; + insn |= ARC_REG_LIMM << operand->shift; + /* The constant is stored later. */ + } + else + *errmsg = _("unable to fit different valued constants into instruction"); + } + else + { + /* We have to handle both normal and auxiliary registers. */ - /* r32-r59 reserved for extensions. */ - { "r32", 32, REG, 0 }, { "r33", 33, REG, 0 }, { "r34", 34, REG, 0 }, - { "r35", 35, REG, 0 }, { "r36", 36, REG, 0 }, { "r37", 37, REG, 0 }, - { "r38", 38, REG, 0 }, { "r39", 39, REG, 0 }, { "r40", 40, REG, 0 }, - { "r41", 41, REG, 0 }, { "r42", 42, REG, 0 }, { "r43", 43, REG, 0 }, - { "r44", 44, REG, 0 }, { "r45", 45, REG, 0 }, { "r46", 46, REG, 0 }, - { "r47", 47, REG, 0 }, { "r48", 48, REG, 0 }, { "r49", 49, REG, 0 }, - { "r50", 50, REG, 0 }, { "r51", 51, REG, 0 }, { "r52", 52, REG, 0 }, - { "r53", 53, REG, 0 }, { "r54", 54, REG, 0 }, { "r55", 55, REG, 0 }, - { "r56", 56, REG, 0 }, { "r57", 57, REG, 0 }, { "r58", 58, REG, 0 }, - { "r59", 59, REG, 0 }, + if (reg->type == AUXREG) + { + if (!(mods & ARC_MOD_AUXREG)) + *errmsg = _("auxiliary register not allowed here"); + else + { + if ((insn & I(-1)) == I(2)) /* Check for use validity. */ + { + if (reg->flags & ARC_REGISTER_READONLY) + *errmsg = _("attempt to set readonly register"); + } + else + { + if (reg->flags & ARC_REGISTER_WRITEONLY) + *errmsg = _("attempt to read writeonly register"); + } + insn |= ARC_REG_SHIMM << operand->shift; + insn |= reg->value << arc_operands[reg->type].shift; + } + } + else + { + /* check for use validity. */ + if ('a' == operand->fmt || ((insn & I(-1)) < I(2))) + { + if (reg->flags & ARC_REGISTER_READONLY) + *errmsg = _("attempt to set readonly register"); + } + if ('a' != operand->fmt) + { + if (reg->flags & ARC_REGISTER_WRITEONLY) + *errmsg = _("attempt to read writeonly register"); + } + /* We should never get an invalid register number here. */ + if ((unsigned int) reg->value > 60) + { + sprintf (buf, _("invalid register number `%d'"), reg->value); + *errmsg = buf; + } + insn |= reg->value << operand->shift; + op_type = OP_REG; + } + } - /* Loop count register (24 bits). */ - { "lp_count", 60, REG, 0 }, - /* Short immediate data indicator setting flags. */ - { "r61", 61, REG, ARC_REGISTER_READONLY }, - /* Long immediate data indicator setting flags. */ - { "r62", 62, REG, ARC_REGISTER_READONLY }, - /* Short immediate data indicator not setting flags. */ - { "r63", 63, REG, ARC_REGISTER_READONLY }, - - /* Small-data base register. */ - { "gp", 26, REG, 0 }, - /* Frame pointer. */ - { "fp", 27, REG, 0 }, - /* Stack pointer. */ - { "sp", 28, REG, 0 }, - - { "r29", 29, REG, 0 }, - { "r30", 30, REG, 0 }, - { "r31", 31, REG, 0 }, - { "r60", 60, REG, 0 }, - - /* Auxiliary register set. */ - - /* Auxiliary register address map: - 0xffffffff-0xffffff00 (-1..-256) - customer shimm allocation - 0xfffffeff-0x80000000 - customer limm allocation - 0x7fffffff-0x00000100 - ARC limm allocation - 0x000000ff-0x00000000 - ARC shimm allocation */ - - /* Base case auxiliary registers (shimm address). */ - { "status", 0x00, AUXREG, 0 }, - { "semaphore", 0x01, AUXREG, 0 }, - { "lp_start", 0x02, AUXREG, 0 }, - { "lp_end", 0x03, AUXREG, 0 }, - { "identity", 0x04, AUXREG, ARC_REGISTER_READONLY }, - { "debug", 0x05, AUXREG, 0 }, -}; + switch (operand->fmt) + { + case 'a': + ls_operand[LS_DEST] = op_type; + break; + case 's': + ls_operand[LS_BASE] = op_type; + break; + case 'c': + if ((insn & I(-1)) == I(2)) + ls_operand[LS_VALUE] = op_type; + else + ls_operand[LS_OFFSET] = op_type; + break; + case 'o': case 'O': + ls_operand[LS_OFFSET] = op_type; + break; + } -const int arc_reg_names_count = - sizeof (arc_reg_names) / sizeof (arc_reg_names[0]); + return insn; +} -/* The suffix table. - Operands with the same name must be stored together. */ +/* Called when we see an 'f' flag. */ -const struct arc_operand_value arc_suffixes[] = +static arc_insn +insert_flag (arc_insn insn, + const struct arc_operand *operand ATTRIBUTE_UNUSED, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) { - /* Entry 0 is special, default values aren't printed by the disassembler. */ - { "", 0, -1, 0 }, - - /* Base case condition codes. */ - { "al", 0, COND, 0 }, - { "ra", 0, COND, 0 }, - { "eq", 1, COND, 0 }, - { "z", 1, COND, 0 }, - { "ne", 2, COND, 0 }, - { "nz", 2, COND, 0 }, - { "pl", 3, COND, 0 }, - { "p", 3, COND, 0 }, - { "mi", 4, COND, 0 }, - { "n", 4, COND, 0 }, - { "cs", 5, COND, 0 }, - { "c", 5, COND, 0 }, - { "lo", 5, COND, 0 }, - { "cc", 6, COND, 0 }, - { "nc", 6, COND, 0 }, - { "hs", 6, COND, 0 }, - { "vs", 7, COND, 0 }, - { "v", 7, COND, 0 }, - { "vc", 8, COND, 0 }, - { "nv", 8, COND, 0 }, - { "gt", 9, COND, 0 }, - { "ge", 10, COND, 0 }, - { "lt", 11, COND, 0 }, - { "le", 12, COND, 0 }, - { "hi", 13, COND, 0 }, - { "ls", 14, COND, 0 }, - { "pnz", 15, COND, 0 }, - - /* Condition codes 16-31 reserved for extensions. */ - - { "f", 1, FLAG, 0 }, - - { "nd", ARC_DELAY_NONE, DELAY, 0 }, - { "d", ARC_DELAY_NORMAL, DELAY, 0 }, - { "jd", ARC_DELAY_JUMP, DELAY, 0 }, - - { "b", 1, SIZE1, 0 }, - { "b", 1, SIZE10, 0 }, - { "b", 1, SIZE22, 0 }, - { "w", 2, SIZE1, 0 }, - { "w", 2, SIZE10, 0 }, - { "w", 2, SIZE22, 0 }, - { "x", 1, SIGN0, 0 }, - { "x", 1, SIGN9, 0 }, - { "a", 1, ADDRESS3, 0 }, - { "a", 1, ADDRESS12, 0 }, - { "a", 1, ADDRESS24, 0 }, - - { "di", 1, CACHEBYPASS5, 0 }, - { "di", 1, CACHEBYPASS14, 0 }, - { "di", 1, CACHEBYPASS26, 0 }, -}; - -const int arc_suffixes_count = - sizeof (arc_suffixes) / sizeof (arc_suffixes[0]); - -/* Indexed by first letter of opcode. Points to chain of opcodes with same - first letter. */ -static struct arc_opcode *opcode_map[26 + 1]; - -/* Indexed by insn code. Points to chain of opcodes with same insn code. */ -static struct arc_opcode *icode_map[32]; - -/* Configuration flags. */ - -/* Various ARC_HAVE_XXX bits. */ -static int cpu_type; + /* We can't store anything in the insn until we've parsed the registers. + Just record the fact that we've got this flag. `insert_reg' will use it + to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */ + flag_p = 1; + return insn; +} -/* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value. */ +/* Called when we see an nullify condition. */ -int -arc_get_opcode_mach (bfd_mach, big_p) - int bfd_mach, big_p; +static arc_insn +insert_nullify (arc_insn insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value, + const char **errmsg ATTRIBUTE_UNUSED) { - static int mach_type_map[] = - { - ARC_MACH_5, - ARC_MACH_6, - ARC_MACH_7, - ARC_MACH_8 - }; - return mach_type_map[bfd_mach - bfd_mach_arc_5] | (big_p ? ARC_MACH_BIG : 0); + nullify_p = 1; + insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; + nullify = value; + return insn; } -/* Initialize any tables that need it. - Must be called once at start up (or when first needed). - - FLAGS is a set of bits that say what version of the cpu we have, - and in particular at least (one of) ARC_MACH_XXX. */ +/* Called after completely building an insn to ensure the 'f' flag gets set + properly. This is needed because we don't know how to set this flag until + we've parsed the registers. */ -void -arc_opcode_init_tables (flags) - int flags; +static arc_insn +insert_flagfinish (arc_insn insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) { - static int init_p = 0; - - cpu_type = flags; - - /* We may be intentionally called more than once (for example gdb will call - us each time the user switches cpu). These tables only need to be init'd - once though. */ - if (!init_p) + if (flag_p && !flagshimm_handled_p) { - register int i,n; - - memset (arc_operand_map, 0, sizeof (arc_operand_map)); - n = sizeof (arc_operands) / sizeof (arc_operands[0]); - for (i = 0; i < n; ++i) - arc_operand_map[arc_operands[i].fmt] = i; - - memset (opcode_map, 0, sizeof (opcode_map)); - memset (icode_map, 0, sizeof (icode_map)); - /* Scan the table backwards so macros appear at the front. */ - for (i = arc_opcodes_count - 1; i >= 0; --i) - { - int opcode_hash = ARC_HASH_OPCODE (arc_opcodes[i].syntax); - int icode_hash = ARC_HASH_ICODE (arc_opcodes[i].value); - - arc_opcodes[i].next_asm = opcode_map[opcode_hash]; - opcode_map[opcode_hash] = &arc_opcodes[i]; - - arc_opcodes[i].next_dis = icode_map[icode_hash]; - icode_map[icode_hash] = &arc_opcodes[i]; - } - - init_p = 1; + if (shimm_p) + abort (); + flagshimm_handled_p = 1; + insn |= (1 << operand->shift); } + return insn; } -/* Return non-zero if OPCODE is supported on the specified cpu. - Cpu selection is made when calling `arc_opcode_init_tables'. */ +/* Called when we see a conditional flag (eg: .eq). */ -int -arc_opcode_supported (opcode) - const struct arc_opcode *opcode; +static arc_insn +insert_cond (arc_insn insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value, + const char **errmsg ATTRIBUTE_UNUSED) { - if (ARC_OPCODE_CPU (opcode->flags) <= cpu_type) - return 1; - return 0; + cond_p = 1; + insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; + return insn; } -/* Return the first insn in the chain for assembling INSN. */ +/* Used in the "j" instruction to prevent constants from being interpreted as + shimm values (which the jump insn doesn't accept). This can also be used + to force the use of limm values in other situations (eg: ld r0,[foo] uses + this). + ??? The mechanism is sound. Access to it is a bit klunky right now. */ -const struct arc_opcode * -arc_opcode_lookup_asm (insn) - const char *insn; +static arc_insn +insert_forcelimm (arc_insn insn, + const struct arc_operand *operand ATTRIBUTE_UNUSED, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) { - return opcode_map[ARC_HASH_OPCODE (insn)]; + cond_p = 1; + return insn; } -/* Return the first insn in the chain for disassembling INSN. */ - -const struct arc_opcode * -arc_opcode_lookup_dis (insn) - unsigned int insn; +static arc_insn +insert_addr_wb (arc_insn insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) { - return icode_map[ARC_HASH_ICODE (insn)]; -} - -/* Nonzero if we've seen an 'f' suffix (in certain insns). */ -static int flag_p; - -/* Nonzero if we've finished processing the 'f' suffix. */ -static int flagshimm_handled_p; - -/* Nonzero if we've seen a 'a' suffix (address writeback). */ -static int addrwb_p; - -/* Nonzero if we've seen a 'q' suffix (condition code). */ -static int cond_p; - -/* Nonzero if we've inserted a nullify condition. */ -static int nullify_p; - -/* The value of the a nullify condition we inserted. */ -static int nullify; - -/* Nonzero if we've inserted jumpflags. */ -static int jumpflags_p; - -/* Nonzero if we've inserted a shimm. */ -static int shimm_p; - -/* The value of the shimm we inserted (each insn only gets one but it can - appear multiple times). */ -static int shimm; - -/* Nonzero if we've inserted a limm (during assembly) or seen a limm - (during disassembly). */ -static int limm_p; - -/* The value of the limm we inserted. Each insn only gets one but it can - appear multiple times. */ -static long limm; - -/* Insertion functions. */ - -/* Called by the assembler before parsing an instruction. */ - -void -arc_opcode_init_insert () -{ - int i; - - for(i = 0; i < OPERANDS; i++) - ls_operand[i] = OP_NONE; - - flag_p = 0; - flagshimm_handled_p = 0; - cond_p = 0; - addrwb_p = 0; - shimm_p = 0; - limm_p = 0; - jumpflags_p = 0; - nullify_p = 0; - nullify = 0; /* the default is important. */ -} - -/* Called by the assembler to see if the insn has a limm operand. - Also called by the disassembler to see if the insn contains a limm. */ - -int -arc_opcode_limm_p (limmp) - long *limmp; -{ - if (limmp) - *limmp = limm; - return limm_p; -} - -/* Insert a value into a register field. - If REG is NULL, then this is actually a constant. - - We must also handle auxiliary registers for lr/sr insns. */ - -static arc_insn -insert_reg (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - static char buf[100]; - enum operand op_type = OP_NONE; - - if (reg == NULL) - { - /* We have a constant that also requires a value stored in a register - field. Handle these by updating the register field and saving the - value for later handling by either %S (shimm) or %L (limm). */ - - /* Try to use a shimm value before a limm one. */ - if (ARC_SHIMM_CONST_P (value) - /* If we've seen a conditional suffix we have to use a limm. */ - && !cond_p - /* If we already have a shimm value that is different than ours - we have to use a limm. */ - && (!shimm_p || shimm == value)) - { - int marker; - - op_type = OP_SHIMM; - /* forget about shimm as dest mlm. */ - - if ('a' != operand->fmt) - { - shimm_p = 1; - shimm = value; - flagshimm_handled_p = 1; - marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM; - } - else - { - /* don't request flag setting on shimm as dest. */ - marker = ARC_REG_SHIMM; - } - insn |= marker << operand->shift; - /* insn |= value & 511; - done later. */ - } - /* We have to use a limm. If we've already seen one they must match. */ - else if (!limm_p || limm == value) - { - op_type = OP_LIMM; - limm_p = 1; - limm = value; - insn |= ARC_REG_LIMM << operand->shift; - /* The constant is stored later. */ - } - else - { - *errmsg = "unable to fit different valued constants into instruction"; - } - } - else - { - /* We have to handle both normal and auxiliary registers. */ - - if (reg->type == AUXREG) - { - if (!(mods & ARC_MOD_AUXREG)) - *errmsg = "auxiliary register not allowed here"; - else - { - if ((insn & I(-1)) == I(2)) /* check for use validity. */ - { - if (reg->flags & ARC_REGISTER_READONLY) - *errmsg = "attempt to set readonly register"; - } - else - { - if (reg->flags & ARC_REGISTER_WRITEONLY) - *errmsg = "attempt to read writeonly register"; - } - insn |= ARC_REG_SHIMM << operand->shift; - insn |= reg->value << arc_operands[reg->type].shift; - } - } - else - { - /* check for use validity. */ - if ('a' == operand->fmt || ((insn & I(-1)) < I(2))) - { - if (reg->flags & ARC_REGISTER_READONLY) - *errmsg = "attempt to set readonly register"; - } - if ('a' != operand->fmt) - { - if (reg->flags & ARC_REGISTER_WRITEONLY) - *errmsg = "attempt to read writeonly register"; - } - /* We should never get an invalid register number here. */ - if ((unsigned int) reg->value > 60) - { - sprintf (buf, "invalid register number `%d'", reg->value); - *errmsg = buf; - } - insn |= reg->value << operand->shift; - op_type = OP_REG; - } - } - - switch (operand->fmt) - { - case 'a': - ls_operand[LS_DEST] = op_type; - break; - case 's': - ls_operand[LS_BASE] = op_type; - break; - case 'c': - if ((insn & I(-1)) == I(2)) - ls_operand[LS_VALUE] = op_type; - else - ls_operand[LS_OFFSET] = op_type; - break; - case 'o': case 'O': - ls_operand[LS_OFFSET] = op_type; - break; - } - - return insn; -} - -/* Called when we see an 'f' flag. */ - -static arc_insn -insert_flag (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand ATTRIBUTE_UNUSED; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - /* We can't store anything in the insn until we've parsed the registers. - Just record the fact that we've got this flag. `insert_reg' will use it - to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */ - flag_p = 1; - return insn; -} - -/* Called when we see an nullify condition. */ - -static arc_insn -insert_nullify (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value; - const char **errmsg ATTRIBUTE_UNUSED; -{ - nullify_p = 1; - insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; - nullify = value; - return insn; -} - -/* Called after completely building an insn to ensure the 'f' flag gets set - properly. This is needed because we don't know how to set this flag until - we've parsed the registers. */ - -static arc_insn -insert_flagfinish (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - if (flag_p && !flagshimm_handled_p) - { - if (shimm_p) - abort (); - flagshimm_handled_p = 1; - insn |= (1 << operand->shift); - } - return insn; -} - -/* Called when we see a conditional flag (eg: .eq). */ - -static arc_insn -insert_cond (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value; - const char **errmsg ATTRIBUTE_UNUSED; -{ - cond_p = 1; - insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; - return insn; -} - -/* Used in the "j" instruction to prevent constants from being interpreted as - shimm values (which the jump insn doesn't accept). This can also be used - to force the use of limm values in other situations (eg: ld r0,[foo] uses - this). - ??? The mechanism is sound. Access to it is a bit klunky right now. */ - -static arc_insn -insert_forcelimm (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand ATTRIBUTE_UNUSED; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - cond_p = 1; - return insn; -} - -static arc_insn -insert_addr_wb (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; -{ - addrwb_p = 1 << operand->shift; - return insn; + addrwb_p = 1 << operand->shift; + return insn; } static arc_insn -insert_base (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; +insert_base (arc_insn insn, + const struct arc_operand *operand, + int mods, + const struct arc_operand_value *reg, + long value, + const char **errmsg) { if (reg != NULL) { @@ -927,10 +572,10 @@ insert_base (insn, operand, mods, reg, v { if (shimm_p && value != shimm) { - /* convert the previous shimm operand to a limm. */ + /* Convert the previous shimm operand to a limm. */ limm_p = 1; limm = shimm; - insn &= ~C(-1); /* we know where the value is in insn. */ + insn &= ~C(-1); /* We know where the value is in insn. */ insn |= C(ARC_REG_LIMM); ls_operand[LS_VALUE] = OP_LIMM; } @@ -944,7 +589,7 @@ insert_base (insn, operand, mods, reg, v { if (limm_p && value != limm) { - *errmsg = "too many long constants"; + *errmsg = _("too many long constants"); return insn; } limm_p = 1; @@ -960,13 +605,12 @@ insert_base (insn, operand, mods, reg, v match operand syntax here. we catch bad combinations later. */ static arc_insn -insert_offset (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; +insert_offset (arc_insn insn, + const struct arc_operand *operand, + int mods, + const struct arc_operand_value *reg, + long value, + const char **errmsg) { long minval, maxval; @@ -975,9 +619,9 @@ insert_offset (insn, operand, mods, reg, arc_insn myinsn; myinsn = insert_reg (0,operand,mods,reg,value,errmsg) >> operand->shift; ls_operand[LS_OFFSET] = OP_REG; - if (operand->flags & ARC_OPERAND_LOAD) /* not if store, catch it later. */ - if ((insn & I(-1)) != I(1)) /* not if opcode == 1, catch it later. */ - insn |= C(myinsn); + if (operand->flags & ARC_OPERAND_LOAD) /* Not if store, catch it later. */ + if ((insn & I(-1)) != I(1)) /* Not if opcode == 1, catch it later. */ + insn |= C (myinsn); } else { @@ -996,9 +640,8 @@ insert_offset (insn, operand, mods, reg, if ((cond_p && !limm_p) || (value < minval || value > maxval)) { if (limm_p && value != limm) - { - *errmsg = "too many long constants"; - } + *errmsg = _("too many long constants"); + else { limm_p = 1; @@ -1016,27 +659,30 @@ insert_offset (insn, operand, mods, reg, *errmsg = "need too many limms"; else if (shimm_p && value != shimm) { - /* check for bad operand combinations before we lose info about them. */ + /* Check for bad operand combinations + before we lose info about them. */ if ((insn & I(-1)) == I(1)) { - *errmsg = "to many shimms in load"; + *errmsg = _("to many shimms in load"); goto out; } if (limm_p && operand->flags & ARC_OPERAND_LOAD) { - *errmsg = "too many long constants"; + *errmsg = _("too many long constants"); goto out; } - /* convert what we thought was a shimm to a limm. */ + /* Convert what we thought was a shimm to a limm. */ limm_p = 1; limm = shimm; - if (ls_operand[LS_VALUE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE) + if (ls_operand[LS_VALUE] == OP_SHIMM + && operand->flags & ARC_OPERAND_STORE) { insn &= ~C(-1); insn |= C(ARC_REG_LIMM); ls_operand[LS_VALUE] = OP_LIMM; } - if (ls_operand[LS_BASE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE) + if (ls_operand[LS_BASE] == OP_SHIMM + && operand->flags & ARC_OPERAND_STORE) { insn &= ~B(-1); insn |= B(ARC_REG_LIMM); @@ -1055,12 +701,11 @@ insert_offset (insn, operand, mods, reg, /* Used in st insns to do final disasemble syntax check. */ static long -extract_st_syntax (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand ATTRIBUTE_UNUSED; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value **opval ATTRIBUTE_UNUSED; - int *invalid; +extract_st_syntax (arc_insn *insn, + const struct arc_operand *operand ATTRIBUTE_UNUSED, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value **opval ATTRIBUTE_UNUSED, + int *invalid) { #define ST_SYNTAX(V,B,O) \ ((ls_operand[LS_VALUE] == (V) && \ @@ -1086,36 +731,34 @@ extract_st_syntax (insn, operand, mods, } int -arc_limm_fixup_adjust(insn) - arc_insn insn; +arc_limm_fixup_adjust (arc_insn insn) { int retval = 0; - /* check for st shimm,[limm]. */ + /* Check for st shimm,[limm]. */ if ((insn & (I(-1) | C(-1) | B(-1))) == (I(2) | C(ARC_REG_SHIMM) | B(ARC_REG_LIMM))) { retval = insn & 0x1ff; - if (retval & 0x100) /* sign extend 9 bit offset. */ + if (retval & 0x100) /* Sign extend 9 bit offset. */ retval |= ~0x1ff; } - return -retval; /* negate offset for return. */ + return -retval; /* Negate offset for return. */ } /* Used in st insns to do final syntax check. */ static arc_insn -insert_st_syntax (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand ATTRIBUTE_UNUSED; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value ATTRIBUTE_UNUSED; - const char **errmsg; +insert_st_syntax (arc_insn insn, + const struct arc_operand *operand ATTRIBUTE_UNUSED, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + const char **errmsg) { - if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm != 0) + if (ST_SYNTAX (OP_SHIMM,OP_REG,OP_NONE) && shimm != 0) { - /* change an illegal insn into a legal one, it's easier to + /* Change an illegal insn into a legal one, it's easier to do it here than to try to handle it during operand scan. */ limm_p = 1; limm = shimm; @@ -1126,15 +769,15 @@ insert_st_syntax (insn, operand, mods, r ls_operand[LS_VALUE] = OP_LIMM; } - if (ST_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE)) + if (ST_SYNTAX (OP_REG, OP_SHIMM, OP_NONE) + || ST_SYNTAX (OP_LIMM, OP_SHIMM, OP_NONE)) { - /* try to salvage this syntax. */ - if (shimm & 0x1) /* odd shimms won't work. */ + /* Try to salvage this syntax. */ + if (shimm & 0x1) /* Odd shimms won't work. */ { - if (limm_p) /* do we have a limm already? */ - { - *errmsg = "impossible store"; - } + if (limm_p) /* Do we have a limm already? */ + *errmsg = _("impossible store"); + limm_p = 1; limm = shimm; shimm = 0; @@ -1152,56 +795,54 @@ insert_st_syntax (insn, operand, mods, r } } if (ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)) - { - limm += arc_limm_fixup_adjust(insn); - } - if (!(ST_SYNTAX(OP_REG,OP_REG,OP_NONE) - || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE) - || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM) - || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) - || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (shimm == 0)) - || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE) - || ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) - || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM) - || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM) - || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM) - || ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) - || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM))) - *errmsg = "st operand error"; + limm += arc_limm_fixup_adjust(insn); + + if (! (ST_SYNTAX (OP_REG,OP_REG,OP_NONE) + || ST_SYNTAX (OP_REG,OP_LIMM,OP_NONE) + || ST_SYNTAX (OP_REG,OP_REG,OP_SHIMM) + || ST_SYNTAX (OP_REG,OP_SHIMM,OP_SHIMM) + || (ST_SYNTAX (OP_SHIMM,OP_SHIMM,OP_NONE) && (shimm == 0)) + || ST_SYNTAX (OP_SHIMM,OP_LIMM,OP_NONE) + || ST_SYNTAX (OP_SHIMM,OP_REG,OP_NONE) + || ST_SYNTAX (OP_SHIMM,OP_REG,OP_SHIMM) + || ST_SYNTAX (OP_SHIMM,OP_SHIMM,OP_SHIMM) + || ST_SYNTAX (OP_LIMM,OP_SHIMM,OP_SHIMM) + || ST_SYNTAX (OP_LIMM,OP_REG,OP_NONE) + || ST_SYNTAX (OP_LIMM,OP_REG,OP_SHIMM))) + *errmsg = _("st operand error"); if (addrwb_p) { if (ls_operand[LS_BASE] != OP_REG) - *errmsg = "address writeback not allowed"; + *errmsg = _("address writeback not allowed"); insn |= addrwb_p; } if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm) - *errmsg = "store value must be zero"; + *errmsg = _("store value must be zero"); return insn; } /* Used in ld insns to do final syntax check. */ static arc_insn -insert_ld_syntax (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand ATTRIBUTE_UNUSED; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value ATTRIBUTE_UNUSED; - const char **errmsg; -{ -#define LD_SYNTAX(D,B,O) \ -((ls_operand[LS_DEST] == (D) && \ - ls_operand[LS_BASE] == (B) && \ - ls_operand[LS_OFFSET] == (O))) +insert_ld_syntax (arc_insn insn, + const struct arc_operand *operand ATTRIBUTE_UNUSED, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + const char **errmsg) +{ +#define LD_SYNTAX(D, B, O) \ + ( (ls_operand[LS_DEST] == (D) \ + && ls_operand[LS_BASE] == (B) \ + && ls_operand[LS_OFFSET] == (O))) - int test = insn & I(-1); + int test = insn & I (-1); - if (!(test == I(1))) + if (!(test == I (1))) { if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM || ls_operand[LS_OFFSET] == OP_SHIMM)) - *errmsg = "invalid load/shimm insn"; + *errmsg = _("invalid load/shimm insn"); } if (!(LD_SYNTAX(OP_REG,OP_REG,OP_NONE) || LD_SYNTAX(OP_REG,OP_REG,OP_REG) @@ -1210,11 +851,11 @@ insert_ld_syntax (insn, operand, mods, r || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1))) || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1))))) - *errmsg = "ld operand error"; + *errmsg = _("ld operand error"); if (addrwb_p) { if (ls_operand[LS_BASE] != OP_REG) - *errmsg = "address writeback not allowed"; + *errmsg = _("address writeback not allowed"); insn |= addrwb_p; } return insn; @@ -1223,12 +864,11 @@ insert_ld_syntax (insn, operand, mods, r /* Used in ld insns to do final syntax check. */ static long -extract_ld_syntax (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand ATTRIBUTE_UNUSED; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value **opval ATTRIBUTE_UNUSED; - int *invalid; +extract_ld_syntax (arc_insn *insn, + const struct arc_operand *operand ATTRIBUTE_UNUSED, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value **opval ATTRIBUTE_UNUSED, + int *invalid) { int test = insn[0] & I(-1); @@ -1238,14 +878,14 @@ extract_ld_syntax (insn, operand, mods, || ls_operand[LS_OFFSET] == OP_SHIMM)) *invalid = 1; } - if (!((LD_SYNTAX(OP_REG,OP_REG,OP_NONE) && (test == I(1))) - || LD_SYNTAX(OP_REG,OP_REG,OP_REG) - || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM) - || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1))) - || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1))) - || (LD_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) && (shimm == 0)) - || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) - || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1))))) + if (!( (LD_SYNTAX (OP_REG, OP_REG, OP_NONE) && (test == I(1))) + || LD_SYNTAX (OP_REG, OP_REG, OP_REG) + || LD_SYNTAX (OP_REG, OP_REG, OP_SHIMM) + || (LD_SYNTAX (OP_REG, OP_REG, OP_LIMM) && !(test == I(1))) + || (LD_SYNTAX (OP_REG, OP_LIMM, OP_REG) && !(test == I(1))) + || (LD_SYNTAX (OP_REG, OP_SHIMM, OP_NONE) && (shimm == 0)) + || LD_SYNTAX (OP_REG, OP_SHIMM, OP_SHIMM) + || (LD_SYNTAX (OP_REG, OP_LIMM, OP_NONE) && (test == I(1))))) *invalid = 1; return 0; } @@ -1254,13 +894,12 @@ extract_ld_syntax (insn, operand, mods, value (if present) into the insn. */ static arc_insn -insert_shimmfinish (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; +insert_shimmfinish (arc_insn insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) { if (shimm_p) insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift; @@ -1280,50 +919,39 @@ insert_shimmfinish (insn, operand, mods, a 2 word quantity. That's too much so we don't handle them. */ static arc_insn -insert_limmfinish (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand ATTRIBUTE_UNUSED; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; +insert_limmfinish (arc_insn insn, + const struct arc_operand *operand ATTRIBUTE_UNUSED, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) { -#if 0 - if (limm_p) - ; /* nothing to do, gas does it. */ -#endif return insn; } static arc_insn -insert_jumpflags (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value; - const char **errmsg; +insert_jumpflags (arc_insn insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value, + const char **errmsg) { if (!flag_p) - { - *errmsg = "jump flags, but no .f seen"; - } - if (!limm_p) - { - *errmsg = "jump flags, but no limm addr"; - } - if (limm & 0xfc000000) - { - *errmsg = "flag bits of jump address limm lost"; - } - if (limm & 0x03000000) - { - *errmsg = "attempt to set HR bits"; - } - if ((value & ((1 << operand->bits) - 1)) != value) - { - *errmsg = "bad jump flags value"; - } + *errmsg = _("jump flags, but no .f seen"); + + else if (!limm_p) + *errmsg = _("jump flags, but no limm addr"); + + else if (limm & 0xfc000000) + *errmsg = _("flag bits of jump address limm lost"); + + else if (limm & 0x03000000) + *errmsg = _("attempt to set HR bits"); + + else if ((value & ((1 << operand->bits) - 1)) != value) + *errmsg = _("bad jump flags value"); + jumpflags_p = 1; limm = ((limm & ((1 << operand->shift) - 1)) | ((value & ((1 << operand->bits) - 1)) << operand->shift)); @@ -1333,13 +961,12 @@ insert_jumpflags (insn, operand, mods, r /* Called at the end of unary operand macros to copy the B field to C. */ static arc_insn -insert_unopmacro (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; +insert_unopmacro (arc_insn insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) { insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift; return insn; @@ -1348,16 +975,15 @@ insert_unopmacro (insn, operand, mods, r /* Insert a relative address for a branch insn (b, bl, or lp). */ static arc_insn -insert_reladdr (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value; - const char **errmsg; +insert_reladdr (arc_insn insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value, + const char **errmsg) { if (value & 3) - *errmsg = "branch address not on 4 byte boundary"; + *errmsg = _("branch address not on 4 byte boundary"); insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift; return insn; } @@ -1377,30 +1003,23 @@ insert_reladdr (insn, operand, mods, reg set the default correctly, though. */ static arc_insn -insert_absaddr (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand ATTRIBUTE_UNUSED; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value *reg ATTRIBUTE_UNUSED; - long value ATTRIBUTE_UNUSED; - const char **errmsg; +insert_absaddr (arc_insn insn, + const struct arc_operand *operand ATTRIBUTE_UNUSED, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value *reg ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + const char **errmsg) { if (limm_p) { - /* if it is a jump and link, .jd must be specified. */ - if (insn & R(-1,9,1)) + /* If it is a jump and link, .jd must be specified. */ + if (insn & R (-1, 9, 1)) { if (!nullify_p) - { - insn |= 0x02 << 5; /* default nullify to .jd. */ - } - else - { - if (nullify != 0x02) - { - *errmsg = "must specify .jd or no nullify suffix"; - } - } + insn |= 0x02 << 5; /* Default nullify to .jd. */ + + else if (nullify != 0x02) + *errmsg = _("must specify .jd or no nullify suffix"); } } return insn; @@ -1413,14 +1032,36 @@ insert_absaddr (insn, operand, mods, reg a suffix table entry for the "false" case, so values of zero must be obtained from the return value (*OPVAL == NULL). */ -static const struct arc_operand_value *lookup_register (int type, long regno); - /* Called by the disassembler before printing an instruction. */ void -arc_opcode_init_extract () +arc_opcode_init_extract (void) +{ + arc_opcode_init_insert (); +} + +static const struct arc_operand_value * +lookup_register (int type, long regno) { - arc_opcode_init_insert(); + const struct arc_operand_value *r,*end; + struct arc_ext_operand_value *ext_oper = arc_ext_operands; + + while (ext_oper) + { + if (ext_oper->operand.type == type && ext_oper->operand.value == regno) + return (&ext_oper->operand); + ext_oper = ext_oper->next; + } + + if (type == REG) + return &arc_reg_names[regno]; + + /* ??? This is a little slow and can be speeded up. */ + for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count; + r < end; ++r) + if (type == r->type && regno == r->value) + return r; + return 0; } /* As we're extracting registers, keep an eye out for the 'f' indicator @@ -1431,12 +1072,11 @@ arc_opcode_init_extract () constants with special names. */ static long -extract_reg (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; - int *invalid ATTRIBUTE_UNUSED; +extract_reg (arc_insn *insn, + const struct arc_operand *operand, + int mods, + const struct arc_operand_value **opval, + int *invalid ATTRIBUTE_UNUSED) { int regno; long value; @@ -1449,7 +1089,7 @@ extract_reg (insn, operand, mods, opval, if (regno == ARC_REG_SHIMM) { op_type = OP_SHIMM; - /* always return zero if dest is a shimm mlm. */ + /* Always return zero if dest is a shimm mlm. */ if ('a' != operand->fmt) { @@ -1462,16 +1102,13 @@ extract_reg (insn, operand, mods, opval, flagshimm_handled_p = 1; } else - { - value = 0; - } + value = 0; } else if (regno == ARC_REG_SHIMM_UPDATE) { op_type = OP_SHIMM; - /* always return zero if dest is a shimm mlm. */ - + /* Always return zero if dest is a shimm mlm. */ if ('a' != operand->fmt) { value = *insn & 511; @@ -1479,9 +1116,8 @@ extract_reg (insn, operand, mods, opval, value -= 512; } else - { - value = 0; - } + value = 0; + flag_p = 1; flagshimm_handled_p = 1; } @@ -1490,237 +1126,570 @@ extract_reg (insn, operand, mods, opval, op_type = OP_LIMM; value = insn[1]; limm_p = 1; - /* if this is a jump instruction (j,jl), show new pc correctly. */ + + /* If this is a jump instruction (j,jl), show new pc correctly. */ if (0x07 == ((*insn & I(-1)) >> 27)) - { - value = (value & 0xffffff); - } + value = (value & 0xffffff); } + /* It's a register, set OPVAL (that's the only way we distinguish registers from constants here). */ else { const struct arc_operand_value *reg = lookup_register (REG, regno); + op_type = OP_REG; - if (reg == NULL) - abort (); - if (opval != NULL) - *opval = reg; - value = regno; - } + if (reg == NULL) + abort (); + if (opval != NULL) + *opval = reg; + value = regno; + } + + /* If this field takes an auxiliary register, see if it's a known one. */ + if ((mods & ARC_MOD_AUXREG) + && ARC_REG_CONSTANT_P (regno)) + { + const struct arc_operand_value *reg = lookup_register (AUXREG, value); + + /* This is really a constant, but tell the caller it has a special + name. */ + if (reg != NULL && opval != NULL) + *opval = reg; + } + + switch(operand->fmt) + { + case 'a': + ls_operand[LS_DEST] = op_type; + break; + case 's': + ls_operand[LS_BASE] = op_type; + break; + case 'c': + if ((insn[0]& I(-1)) == I(2)) + ls_operand[LS_VALUE] = op_type; + else + ls_operand[LS_OFFSET] = op_type; + break; + case 'o': case 'O': + ls_operand[LS_OFFSET] = op_type; + break; + } + + return value; +} + +/* Return the value of the "flag update" field for shimm insns. + This value is actually stored in the register field. */ + +static long +extract_flag (arc_insn *insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value **opval, + int *invalid ATTRIBUTE_UNUSED) +{ + int f; + const struct arc_operand_value *val; + + if (flagshimm_handled_p) + f = flag_p != 0; + else + f = (*insn & (1 << operand->shift)) != 0; + + /* There is no text for zero values. */ + if (f == 0) + return 0; + flag_p = 1; + val = arc_opcode_lookup_suffix (operand, 1); + if (opval != NULL && val != NULL) + *opval = val; + return val->value; +} + +/* Extract the condition code (if it exists). + If we've seen a shimm value in this insn (meaning that the insn can't have + a condition code field), then we don't store anything in OPVAL and return + zero. */ + +static long +extract_cond (arc_insn *insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value **opval, + int *invalid ATTRIBUTE_UNUSED) +{ + long cond; + const struct arc_operand_value *val; + + if (flagshimm_handled_p) + return 0; + + cond = (*insn >> operand->shift) & ((1 << operand->bits) - 1); + val = arc_opcode_lookup_suffix (operand, cond); + + /* Ignore NULL values of `val'. Several condition code values are + reserved for extensions. */ + if (opval != NULL && val != NULL) + *opval = val; + return cond; +} + +/* Extract a branch address. + We return the value as a real address (not right shifted by 2). */ + +static long +extract_reladdr (arc_insn *insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value **opval ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + long addr; + + addr = (*insn >> operand->shift) & ((1 << operand->bits) - 1); + if ((operand->flags & ARC_OPERAND_SIGNED) + && (addr & (1 << (operand->bits - 1)))) + addr -= 1 << operand->bits; + return addr << 2; +} + +/* Extract the flags bits from a j or jl long immediate. */ + +static long +extract_jumpflags (arc_insn *insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value **opval ATTRIBUTE_UNUSED, + int *invalid) +{ + if (!flag_p || !limm_p) + *invalid = 1; + return ((flag_p && limm_p) + ? (insn[1] >> operand->shift) & ((1 << operand->bits) -1): 0); +} + +/* Extract st insn's offset. */ + +static long +extract_st_offset (arc_insn *insn, + const struct arc_operand *operand, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value **opval ATTRIBUTE_UNUSED, + int *invalid) +{ + int value = 0; + + if (ls_operand[LS_VALUE] != OP_SHIMM || ls_operand[LS_BASE] != OP_LIMM) + { + value = insn[0] & 511; + if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) + value -= 512; + if (value) + ls_operand[LS_OFFSET] = OP_SHIMM; + } + else + *invalid = 1; + + return value; +} + +/* Extract ld insn's offset. */ + +static long +extract_ld_offset (arc_insn *insn, + const struct arc_operand *operand, + int mods, + const struct arc_operand_value **opval, + int *invalid) +{ + int test = insn[0] & I(-1); + int value; + + if (test) + { + value = insn[0] & 511; + if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) + value -= 512; + if (value) + ls_operand[LS_OFFSET] = OP_SHIMM; + + return value; + } + /* If it isn't in the insn, it's concealed behind reg 'c'. */ + return extract_reg (insn, &arc_operands[arc_operand_map['c']], + mods, opval, invalid); +} + +/* The only thing this does is set the `invalid' flag if B != C. + This is needed because the "mov" macro appears before it's real insn "and" + and we don't want the disassembler to confuse them. */ + +static long +extract_unopmacro (arc_insn *insn, + const struct arc_operand *operand ATTRIBUTE_UNUSED, + int mods ATTRIBUTE_UNUSED, + const struct arc_operand_value **opval ATTRIBUTE_UNUSED, + int *invalid) +{ + /* This misses the case where B == ARC_REG_SHIMM_UPDATE && + C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get + printed as "and"s. */ + if (((*insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) + != ((*insn >> ARC_SHIFT_REGC) & ARC_MASK_REG)) + if (invalid != NULL) + *invalid = 1; + return 0; +} + +/* ARC instructions. + + Longer versions of insns must appear before shorter ones (if gas sees + "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is + junk). This isn't necessary for `ld' because of the trailing ']'. + + Instructions that are really macros based on other insns must appear + before the real insn so they're chosen when disassembling. Eg: The `mov' + insn is really the `and' insn. */ + +struct arc_opcode arc_opcodes[] = +{ + /* Base case instruction set (core versions 5-8). */ + + /* "mov" is really an "and". */ + { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12), ARC_MACH_5, 0, 0 }, + /* "asl" is really an "add". */ + { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 }, + /* "lsl" is really an "add". */ + { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 }, + /* "nop" is really an "xor". */ + { "nop", 0x7fffffff, 0x7fffffff, ARC_MACH_5, 0, 0 }, + /* "rlc" is really an "adc". */ + { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9), ARC_MACH_5, 0, 0 }, + { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9), ARC_MACH_5, 0, 0 }, + { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8), ARC_MACH_5, 0, 0 }, + { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12), ARC_MACH_5, 0, 0 }, + { "asr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(1), ARC_MACH_5, 0, 0 }, + { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14), ARC_MACH_5, 0, 0 }, + { "b%q%.n %B", I(-1), I(4), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + { "bl%q%.n %B", I(-1), I(5), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + { "extb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(7), ARC_MACH_5, 0, 0 }, + { "extw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(8), ARC_MACH_5, 0, 0 }, + { "flag%.q %b%G%S%L", I(-1)|A(-1)|C(-1), I(3)|A(ARC_REG_SHIMM_UPDATE)|C(0), ARC_MACH_5, 0, 0 }, + { "brk", 0x1ffffe00, 0x1ffffe00, ARC_MACH_7, 0, 0 }, + { "sleep", 0x1ffffe01, 0x1ffffe01, ARC_MACH_7, 0, 0 }, + { "swi", 0x1ffffe02, 0x1ffffe02, ARC_MACH_8, 0, 0 }, + /* %Q: force cond_p=1 -> no shimm values. This insn allows an + optional flags spec. */ + { "j%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + { "j%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + /* This insn allows an optional flags spec. */ + { "jl%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + { "jl%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 }, + /* Put opcode 1 ld insns first so shimm gets prefered over limm. + "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */ + { "ld%Z%.X%.W%.E %a,[%s]%S%L%1", I(-1)|R(-1,13,1)|R(-1,0,511), I(1)|R(0,13,1)|R(0,0,511), ARC_MACH_5, 0, 0 }, + { "ld%z%.x%.w%.e %a,[%s]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 }, + { "ld%z%.x%.w%.e %a,[%s,%O]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 }, + { "ld%Z%.X%.W%.E %a,[%s,%O]%S%L%3", I(-1)|R(-1,13,1), I(1)|R(0,13,1), ARC_MACH_5, 0, 0 }, + { "lp%q%.n %B", I(-1), I(6), ARC_MACH_5, 0, 0 }, + { "lr %a,[%Ab]%S%L", I(-1)|C(-1), I(1)|C(0x10), ARC_MACH_5, 0, 0 }, + { "lsr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(2), ARC_MACH_5, 0, 0 }, + { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13), ARC_MACH_5, 0, 0 }, + { "ror%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(3), ARC_MACH_5, 0, 0 }, + { "rrc%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(4), ARC_MACH_5, 0, 0 }, + { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11), ARC_MACH_5, 0, 0 }, + { "sexb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(5), ARC_MACH_5, 0, 0 }, + { "sexw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(6), ARC_MACH_5, 0, 0 }, + { "sr %c,[%Ab]%S%L", I(-1)|A(-1), I(2)|A(0x10), ARC_MACH_5, 0, 0 }, + /* "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */ + { "st%y%.v%.D %c,[%s]%L%S%0", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 }, + { "st%y%.v%.D %c,[%s,%o]%S%L%2", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 }, + { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10), ARC_MACH_5, 0, 0 }, + { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15), ARC_MACH_5, 0, 0 } +}; + +const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]); + +const struct arc_operand_value arc_reg_names[] = +{ + /* Core register set r0-r63. */ + + /* r0-r28 - general purpose registers. */ + { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 }, + { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 }, + { "r6", 6, REG, 0 }, { "r7", 7, REG, 0 }, { "r8", 8, REG, 0 }, + { "r9", 9, REG, 0 }, { "r10", 10, REG, 0 }, { "r11", 11, REG, 0 }, + { "r12", 12, REG, 0 }, { "r13", 13, REG, 0 }, { "r14", 14, REG, 0 }, + { "r15", 15, REG, 0 }, { "r16", 16, REG, 0 }, { "r17", 17, REG, 0 }, + { "r18", 18, REG, 0 }, { "r19", 19, REG, 0 }, { "r20", 20, REG, 0 }, + { "r21", 21, REG, 0 }, { "r22", 22, REG, 0 }, { "r23", 23, REG, 0 }, + { "r24", 24, REG, 0 }, { "r25", 25, REG, 0 }, { "r26", 26, REG, 0 }, + { "r27", 27, REG, 0 }, { "r28", 28, REG, 0 }, + /* Maskable interrupt link register. */ + { "ilink1", 29, REG, 0 }, + /* Maskable interrupt link register. */ + { "ilink2", 30, REG, 0 }, + /* Branch-link register. */ + { "blink", 31, REG, 0 }, + + /* r32-r59 reserved for extensions. */ + { "r32", 32, REG, 0 }, { "r33", 33, REG, 0 }, { "r34", 34, REG, 0 }, + { "r35", 35, REG, 0 }, { "r36", 36, REG, 0 }, { "r37", 37, REG, 0 }, + { "r38", 38, REG, 0 }, { "r39", 39, REG, 0 }, { "r40", 40, REG, 0 }, + { "r41", 41, REG, 0 }, { "r42", 42, REG, 0 }, { "r43", 43, REG, 0 }, + { "r44", 44, REG, 0 }, { "r45", 45, REG, 0 }, { "r46", 46, REG, 0 }, + { "r47", 47, REG, 0 }, { "r48", 48, REG, 0 }, { "r49", 49, REG, 0 }, + { "r50", 50, REG, 0 }, { "r51", 51, REG, 0 }, { "r52", 52, REG, 0 }, + { "r53", 53, REG, 0 }, { "r54", 54, REG, 0 }, { "r55", 55, REG, 0 }, + { "r56", 56, REG, 0 }, { "r57", 57, REG, 0 }, { "r58", 58, REG, 0 }, + { "r59", 59, REG, 0 }, + + /* Loop count register (24 bits). */ + { "lp_count", 60, REG, 0 }, + /* Short immediate data indicator setting flags. */ + { "r61", 61, REG, ARC_REGISTER_READONLY }, + /* Long immediate data indicator setting flags. */ + { "r62", 62, REG, ARC_REGISTER_READONLY }, + /* Short immediate data indicator not setting flags. */ + { "r63", 63, REG, ARC_REGISTER_READONLY }, + + /* Small-data base register. */ + { "gp", 26, REG, 0 }, + /* Frame pointer. */ + { "fp", 27, REG, 0 }, + /* Stack pointer. */ + { "sp", 28, REG, 0 }, + + { "r29", 29, REG, 0 }, + { "r30", 30, REG, 0 }, + { "r31", 31, REG, 0 }, + { "r60", 60, REG, 0 }, + + /* Auxiliary register set. */ + + /* Auxiliary register address map: + 0xffffffff-0xffffff00 (-1..-256) - customer shimm allocation + 0xfffffeff-0x80000000 - customer limm allocation + 0x7fffffff-0x00000100 - ARC limm allocation + 0x000000ff-0x00000000 - ARC shimm allocation */ + + /* Base case auxiliary registers (shimm address). */ + { "status", 0x00, AUXREG, 0 }, + { "semaphore", 0x01, AUXREG, 0 }, + { "lp_start", 0x02, AUXREG, 0 }, + { "lp_end", 0x03, AUXREG, 0 }, + { "identity", 0x04, AUXREG, ARC_REGISTER_READONLY }, + { "debug", 0x05, AUXREG, 0 }, +}; + +const int arc_reg_names_count = + sizeof (arc_reg_names) / sizeof (arc_reg_names[0]); + +/* The suffix table. + Operands with the same name must be stored together. */ + +const struct arc_operand_value arc_suffixes[] = +{ + /* Entry 0 is special, default values aren't printed by the disassembler. */ + { "", 0, -1, 0 }, + + /* Base case condition codes. */ + { "al", 0, COND, 0 }, + { "ra", 0, COND, 0 }, + { "eq", 1, COND, 0 }, + { "z", 1, COND, 0 }, + { "ne", 2, COND, 0 }, + { "nz", 2, COND, 0 }, + { "pl", 3, COND, 0 }, + { "p", 3, COND, 0 }, + { "mi", 4, COND, 0 }, + { "n", 4, COND, 0 }, + { "cs", 5, COND, 0 }, + { "c", 5, COND, 0 }, + { "lo", 5, COND, 0 }, + { "cc", 6, COND, 0 }, + { "nc", 6, COND, 0 }, + { "hs", 6, COND, 0 }, + { "vs", 7, COND, 0 }, + { "v", 7, COND, 0 }, + { "vc", 8, COND, 0 }, + { "nv", 8, COND, 0 }, + { "gt", 9, COND, 0 }, + { "ge", 10, COND, 0 }, + { "lt", 11, COND, 0 }, + { "le", 12, COND, 0 }, + { "hi", 13, COND, 0 }, + { "ls", 14, COND, 0 }, + { "pnz", 15, COND, 0 }, + + /* Condition codes 16-31 reserved for extensions. */ + + { "f", 1, FLAG, 0 }, + + { "nd", ARC_DELAY_NONE, DELAY, 0 }, + { "d", ARC_DELAY_NORMAL, DELAY, 0 }, + { "jd", ARC_DELAY_JUMP, DELAY, 0 }, + + { "b", 1, SIZE1, 0 }, + { "b", 1, SIZE10, 0 }, + { "b", 1, SIZE22, 0 }, + { "w", 2, SIZE1, 0 }, + { "w", 2, SIZE10, 0 }, + { "w", 2, SIZE22, 0 }, + { "x", 1, SIGN0, 0 }, + { "x", 1, SIGN9, 0 }, + { "a", 1, ADDRESS3, 0 }, + { "a", 1, ADDRESS12, 0 }, + { "a", 1, ADDRESS24, 0 }, - /* If this field takes an auxiliary register, see if it's a known one. */ - if ((mods & ARC_MOD_AUXREG) - && ARC_REG_CONSTANT_P (regno)) - { - const struct arc_operand_value *reg = lookup_register (AUXREG, value); + { "di", 1, CACHEBYPASS5, 0 }, + { "di", 1, CACHEBYPASS14, 0 }, + { "di", 1, CACHEBYPASS26, 0 }, +}; - /* This is really a constant, but tell the caller it has a special - name. */ - if (reg != NULL && opval != NULL) - *opval = reg; - } - switch(operand->fmt) - { - case 'a': - ls_operand[LS_DEST] = op_type; - break; - case 's': - ls_operand[LS_BASE] = op_type; - break; - case 'c': - if ((insn[0]& I(-1)) == I(2)) - ls_operand[LS_VALUE] = op_type; - else - ls_operand[LS_OFFSET] = op_type; - break; - case 'o': case 'O': - ls_operand[LS_OFFSET] = op_type; - break; - } +const int arc_suffixes_count = + sizeof (arc_suffixes) / sizeof (arc_suffixes[0]); - return value; -} +/* Indexed by first letter of opcode. Points to chain of opcodes with same + first letter. */ +static struct arc_opcode *opcode_map[26 + 1]; -/* Return the value of the "flag update" field for shimm insns. - This value is actually stored in the register field. */ +/* Indexed by insn code. Points to chain of opcodes with same insn code. */ +static struct arc_opcode *icode_map[32]; + +/* Configuration flags. */ -static long -extract_flag (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value **opval; - int *invalid ATTRIBUTE_UNUSED; -{ - int f; - const struct arc_operand_value *val; +/* Various ARC_HAVE_XXX bits. */ +static int cpu_type; - if (flagshimm_handled_p) - f = flag_p != 0; - else - f = (*insn & (1 << operand->shift)) != 0; +/* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value. */ - /* There is no text for zero values. */ - if (f == 0) - return 0; - flag_p = 1; - val = arc_opcode_lookup_suffix (operand, 1); - if (opval != NULL && val != NULL) - *opval = val; - return val->value; +int +arc_get_opcode_mach (int bfd_mach, int big_p) +{ + static int mach_type_map[] = + { + ARC_MACH_5, + ARC_MACH_6, + ARC_MACH_7, + ARC_MACH_8 + }; + return mach_type_map[bfd_mach - bfd_mach_arc_5] | (big_p ? ARC_MACH_BIG : 0); } -/* Extract the condition code (if it exists). - If we've seen a shimm value in this insn (meaning that the insn can't have - a condition code field), then we don't store anything in OPVAL and return - zero. */ +/* Initialize any tables that need it. + Must be called once at start up (or when first needed). -static long -extract_cond (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value **opval; - int *invalid ATTRIBUTE_UNUSED; + FLAGS is a set of bits that say what version of the cpu we have, + and in particular at least (one of) ARC_MACH_XXX. */ + +void +arc_opcode_init_tables (int flags) { - long cond; - const struct arc_operand_value *val; + static int init_p = 0; - if (flagshimm_handled_p) - return 0; + cpu_type = flags; - cond = (*insn >> operand->shift) & ((1 << operand->bits) - 1); - val = arc_opcode_lookup_suffix (operand, cond); + /* We may be intentionally called more than once (for example gdb will call + us each time the user switches cpu). These tables only need to be init'd + once though. */ + if (!init_p) + { + int i,n; - /* Ignore NULL values of `val'. Several condition code values are - reserved for extensions. */ - if (opval != NULL && val != NULL) - *opval = val; - return cond; -} + memset (arc_operand_map, 0, sizeof (arc_operand_map)); + n = sizeof (arc_operands) / sizeof (arc_operands[0]); + for (i = 0; i < n; ++i) + arc_operand_map[arc_operands[i].fmt] = i; -/* Extract a branch address. - We return the value as a real address (not right shifted by 2). */ + memset (opcode_map, 0, sizeof (opcode_map)); + memset (icode_map, 0, sizeof (icode_map)); + /* Scan the table backwards so macros appear at the front. */ + for (i = arc_opcodes_count - 1; i >= 0; --i) + { + int opcode_hash = ARC_HASH_OPCODE (arc_opcodes[i].syntax); + int icode_hash = ARC_HASH_ICODE (arc_opcodes[i].value); -static long -extract_reladdr (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value **opval ATTRIBUTE_UNUSED; - int *invalid ATTRIBUTE_UNUSED; -{ - long addr; + arc_opcodes[i].next_asm = opcode_map[opcode_hash]; + opcode_map[opcode_hash] = &arc_opcodes[i]; - addr = (*insn >> operand->shift) & ((1 << operand->bits) - 1); - if ((operand->flags & ARC_OPERAND_SIGNED) - && (addr & (1 << (operand->bits - 1)))) - addr -= 1 << operand->bits; - return addr << 2; + arc_opcodes[i].next_dis = icode_map[icode_hash]; + icode_map[icode_hash] = &arc_opcodes[i]; + } + + init_p = 1; + } } -/* extract the flags bits from a j or jl long immediate. */ -static long -extract_jumpflags(insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value **opval ATTRIBUTE_UNUSED; - int *invalid; +/* Return non-zero if OPCODE is supported on the specified cpu. + Cpu selection is made when calling `arc_opcode_init_tables'. */ + +int +arc_opcode_supported (const struct arc_opcode *opcode) { - if (!flag_p || !limm_p) - *invalid = 1; - return ((flag_p && limm_p) - ? (insn[1] >> operand->shift) & ((1 << operand->bits) -1): 0); + if (ARC_OPCODE_CPU (opcode->flags) <= cpu_type) + return 1; + return 0; } -/* extract st insn's offset. */ +/* Return the first insn in the chain for assembling INSN. */ -static long -extract_st_offset (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value **opval ATTRIBUTE_UNUSED; - int *invalid; +const struct arc_opcode * +arc_opcode_lookup_asm (const char *insn) { - int value = 0; + return opcode_map[ARC_HASH_OPCODE (insn)]; +} - if (ls_operand[LS_VALUE] != OP_SHIMM || ls_operand[LS_BASE] != OP_LIMM) - { - value = insn[0] & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) - value -= 512; - if (value) - ls_operand[LS_OFFSET] = OP_SHIMM; - } - else - { - *invalid = 1; - } - return(value); +/* Return the first insn in the chain for disassembling INSN. */ + +const struct arc_opcode * +arc_opcode_lookup_dis (unsigned int insn) +{ + return icode_map[ARC_HASH_ICODE (insn)]; } -/* extract ld insn's offset. */ +/* Called by the assembler before parsing an instruction. */ -static long -extract_ld_offset (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; - int *invalid; +void +arc_opcode_init_insert (void) { - int test = insn[0] & I(-1); - int value; + int i; - if (test) - { - value = insn[0] & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) - value -= 512; - if (value) - ls_operand[LS_OFFSET] = OP_SHIMM; - return(value); - } - /* if it isn't in the insn, it's concealed behind reg 'c'. */ - return extract_reg (insn, &arc_operands[arc_operand_map['c']], - mods, opval, invalid); + for(i = 0; i < OPERANDS; i++) + ls_operand[i] = OP_NONE; + + flag_p = 0; + flagshimm_handled_p = 0; + cond_p = 0; + addrwb_p = 0; + shimm_p = 0; + limm_p = 0; + jumpflags_p = 0; + nullify_p = 0; + nullify = 0; /* The default is important. */ } -/* The only thing this does is set the `invalid' flag if B != C. - This is needed because the "mov" macro appears before it's real insn "and" - and we don't want the disassembler to confuse them. */ +/* Called by the assembler to see if the insn has a limm operand. + Also called by the disassembler to see if the insn contains a limm. */ -static long -extract_unopmacro (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand ATTRIBUTE_UNUSED; - int mods ATTRIBUTE_UNUSED; - const struct arc_operand_value **opval ATTRIBUTE_UNUSED; - int *invalid; +int +arc_opcode_limm_p (long *limmp) { - /* This misses the case where B == ARC_REG_SHIMM_UPDATE && - C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get - printed as "and"s. */ - if (((*insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) - != ((*insn >> ARC_SHIFT_REGC) & ARC_MASK_REG)) - if (invalid != NULL) - *invalid = 1; - return 0; + if (limmp) + *limmp = limm; + return limm_p; } /* Utility for the extraction functions to return the index into `arc_suffixes'. */ const struct arc_operand_value * -arc_opcode_lookup_suffix (type, value) - const struct arc_operand *type; - int value; +arc_opcode_lookup_suffix (const struct arc_operand *type, int value) { - register const struct arc_operand_value *v,*end; + const struct arc_operand_value *v,*end; struct arc_ext_operand_value *ext_oper = arc_ext_operands; while (ext_oper) @@ -1732,7 +1701,6 @@ arc_opcode_lookup_suffix (type, value) } /* ??? This is a little slow and can be speeded up. */ - for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v) if (type == &arc_operands[v->type] && value == v->value) @@ -1740,69 +1708,39 @@ arc_opcode_lookup_suffix (type, value) return 0; } -static const struct arc_operand_value * -lookup_register (type, regno) - int type; - long regno; -{ - register const struct arc_operand_value *r,*end; - struct arc_ext_operand_value *ext_oper = arc_ext_operands; - - while (ext_oper) - { - if (ext_oper->operand.type == type && ext_oper->operand.value == regno) - return (&ext_oper->operand); - ext_oper = ext_oper->next; - } - - if (type == REG) - return &arc_reg_names[regno]; - - /* ??? This is a little slow and can be speeded up. */ - - for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count; - r < end; ++r) - if (type == r->type && regno == r->value) - return r; - return 0; -} - int -arc_insn_is_j(insn) - arc_insn insn; +arc_insn_is_j (arc_insn insn) { return (insn & (I(-1))) == I(0x7); } int -arc_insn_not_jl(insn) - arc_insn insn; +arc_insn_not_jl (arc_insn insn) { return ((insn & (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1))) != (I(0x7) | R(-1,9,1))); } int -arc_operand_type(int opertype) +arc_operand_type (int opertype) { switch (opertype) { case 0: - return(COND); + return COND; break; case 1: - return(REG); + return REG; break; case 2: - return(AUXREG); + return AUXREG; break; } return -1; } struct arc_operand_value * -get_ext_suffix(s) - char *s; +get_ext_suffix (char *s) { struct arc_ext_operand_value *suffix = arc_ext_operands; @@ -1817,7 +1755,7 @@ get_ext_suffix(s) } int -arc_get_noshortcut_flag() +arc_get_noshortcut_flag (void) { return ARC_REGISTER_NOSHORT_CUT; } diff -uprN binutils-2.16.91.0.1/opcodes/arm-dis.c binutils-2.16.91.0.2/opcodes/arm-dis.c --- binutils-2.16.91.0.1/opcodes/arm-dis.c 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/arm-dis.c 2005-07-20 12:27:28.556984645 -0700 @@ -460,7 +460,7 @@ static const struct opcode32 arm_opcodes {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fff0ff0, "fabsd%c\t%1z, %0z"}, {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%1y, %0y"}, {FPU_VFP_EXT_V1, 0x0e300b00, 0x0ff00ff0, "faddd%c\t%1z, %2z, %0z"}, - {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "fadds%c\t%1y, %2y, %1y"}, + {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "fadds%c\t%1y, %2y, %0y"}, {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fff0f70, "fcmp%7'ed%c\t%1z, %0z"}, {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%1y, %0y"}, {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fff0f70, "fcmp%7'ezd%c\t%1z"}, @@ -1578,7 +1578,7 @@ print_insn_arm (bfd_vma pc, struct disas reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; - func (stream, "%d", reg); + func (stream, "%ld", reg); } break; case 'W': @@ -1588,7 +1588,7 @@ print_insn_arm (bfd_vma pc, struct disas reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; - func (stream, "%d", reg + 1); + func (stream, "%ld", reg + 1); } break; case 'x': @@ -1598,7 +1598,7 @@ print_insn_arm (bfd_vma pc, struct disas reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; - func (stream, "0x%08x", reg); + func (stream, "0x%08lx", reg); /* Some SWI instructions have special meanings. */ @@ -1615,7 +1615,7 @@ print_insn_arm (bfd_vma pc, struct disas reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; - func (stream, "%01x", reg & 0xf); + func (stream, "%01lx", reg & 0xf); } break; case 'f': @@ -1629,7 +1629,7 @@ print_insn_arm (bfd_vma pc, struct disas func (stream, "#%s", arm_fp_const[reg & 7]); else - func (stream, "f%d", reg); + func (stream, "f%ld", reg); } break; @@ -1991,7 +1991,7 @@ print_insn_thumb16 (bfd_vma pc, struct d long imm = (given & 0x07c0) >> 6; if (imm == 0) imm = 32; - func (stream, "#%d", imm); + func (stream, "#%ld", imm); } break; @@ -2024,15 +2024,15 @@ print_insn_thumb16 (bfd_vma pc, struct d break; case 'd': - func (stream, "%d", reg); + func (stream, "%ld", reg); break; case 'H': - func (stream, "%d", reg << 1); + func (stream, "%ld", reg << 1); break; case 'W': - func (stream, "%d", reg << 2); + func (stream, "%ld", reg << 2); break; case 'a': @@ -2044,7 +2044,7 @@ print_insn_thumb16 (bfd_vma pc, struct d break; case 'x': - func (stream, "0x%04x", reg); + func (stream, "0x%04lx", reg); break; case 'B': diff -uprN binutils-2.16.91.0.1/opcodes/avr-dis.c binutils-2.16.91.0.2/opcodes/avr-dis.c --- binutils-2.16.91.0.1/opcodes/avr-dis.c 2005-05-10 15:46:53.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/avr-dis.c 2005-07-20 12:27:28.557984480 -0700 @@ -1,21 +1,21 @@ /* Disassemble AVR instructions. - Copyright 1999, 2000, 2002, 2004 Free Software Foundation, Inc. + Copyright 1999, 2000, 2002, 2004, 2005 Free Software Foundation, Inc. Contributed by Denis Chertykov -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ #include #include "sysdep.h" @@ -28,7 +28,7 @@ struct avr_opcodes_s char *name; char *constraints; char *opcode; - int insn_size; /* in words */ + int insn_size; /* In words. */ int isa; unsigned int bin_opcode; }; @@ -42,9 +42,6 @@ const struct avr_opcodes_s avr_opcodes[] {NULL, NULL, NULL, 0, 0, 0} }; -static int avr_operand (unsigned int, unsigned int, unsigned int, int, - char *, char *, int, int *, bfd_vma *); - static int avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constraint, char *buf, char *comment, int regs, int *sym, bfd_vma *sym_addr) @@ -57,9 +54,9 @@ avr_operand (unsigned int insn, unsigned /* Any register operand. */ case 'r': if (regs) - insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* source register */ + insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* Source register. */ else - insn = (insn & 0x01f0) >> 4; /* destination register */ + insn = (insn & 0x01f0) >> 4; /* Destination register. */ sprintf (buf, "r%d", insn); break; @@ -201,6 +198,7 @@ avr_operand (unsigned int insn, unsigned case 'P': { unsigned int x; + x = (insn & 0xf); x |= (insn >> 5) & 0x30; sprintf (buf, "0x%02x", x); @@ -231,29 +229,24 @@ avr_operand (unsigned int insn, unsigned return ok; } -static unsigned short avrdis_opcode PARAMS ((bfd_vma, disassemble_info *)); - static unsigned short -avrdis_opcode (addr, info) - bfd_vma addr; - disassemble_info *info; +avrdis_opcode (bfd_vma addr, disassemble_info *info) { bfd_byte buffer[2]; int status; - status = info->read_memory_func(addr, buffer, 2, info); - if (status != 0) - { - info->memory_error_func(status, addr, info); - return -1; - } - return bfd_getl16 (buffer); + + status = info->read_memory_func (addr, buffer, 2, info); + + if (status == 0) + return bfd_getl16 (buffer); + + info->memory_error_func (status, addr, info); + return -1; } int -print_insn_avr(addr, info) - bfd_vma addr; - disassemble_info *info; +print_insn_avr (bfd_vma addr, disassemble_info *info) { unsigned int insn, insn2; const struct avr_opcodes_s *opcode; @@ -274,8 +267,7 @@ print_insn_avr(addr, info) nopcodes = sizeof (avr_opcodes) / sizeof (struct avr_opcodes_s); - avr_bin_masks = (unsigned int *) - xmalloc (nopcodes * sizeof (unsigned int)); + avr_bin_masks = xmalloc (nopcodes * sizeof (unsigned int)); for (opcode = avr_opcodes, maskptr = avr_bin_masks; opcode->name; @@ -305,10 +297,8 @@ print_insn_avr(addr, info) for (opcode = avr_opcodes, maskptr = avr_bin_masks; opcode->name; opcode++, maskptr++) - { - if ((insn & *maskptr) == opcode->bin_opcode) - break; - } + if ((insn & *maskptr) == opcode->bin_opcode) + break; /* Special case: disassemble `ldd r,b+0' as `ld r,b', and `std b+0,r' as `st b,r' (next entry in the table). */ diff -uprN binutils-2.16.91.0.1/opcodes/cgen-asm.in binutils-2.16.91.0.2/opcodes/cgen-asm.in --- binutils-2.16.91.0.1/opcodes/cgen-asm.in 2005-05-10 15:46:53.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/cgen-asm.in 2005-07-20 12:27:28.558984315 -0700 @@ -1,26 +1,27 @@ /* Assembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-asm.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -421,30 +422,3 @@ const CGEN_INSN * return NULL; } } - -#if 0 /* This calls back to GAS which we can't do without care. */ - -/* Record each member of OPVALS in the assembler's symbol table. - This lets GAS parse registers for us. - ??? Interesting idea but not currently used. */ - -/* Record each member of OPVALS in the assembler's symbol table. - FIXME: Not currently used. */ - -void -@arch@_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) -{ - CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); - const CGEN_KEYWORD_ENTRY * ke; - - while ((ke = cgen_keyword_search_next (& search)) != NULL) - { -#if 0 /* Unnecessary, should be done in the search routine. */ - if (! @arch@_cgen_opval_supported (ke)) - continue; -#endif - cgen_asm_record_register (cd, ke->name, ke->value); - } -} - -#endif /* 0 */ diff -uprN binutils-2.16.91.0.1/opcodes/cgen-dis.in binutils-2.16.91.0.2/opcodes/cgen-dis.in --- binutils-2.16.91.0.1/opcodes/cgen-dis.in 2005-05-10 15:46:53.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/cgen-dis.in 2005-07-20 12:27:28.559984150 -0700 @@ -1,27 +1,27 @@ /* Disassembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-dis.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 -Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -56,7 +56,7 @@ static int read_insn (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, unsigned long *); -/* -- disassembler routines inserted here */ +/* -- disassembler routines inserted here. */ /* Default print handler. */ @@ -101,7 +101,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUT /* Print the operand as directed by the attributes. */ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) - ; /* nothing to do */ + ; /* Nothing to do. */ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) (*info->print_address_func) (value, info); else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) @@ -183,6 +183,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UN unsigned long *insn_value) { int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) { (*info->memory_error_func) (status, pc, info); @@ -287,13 +288,13 @@ print_insn (CGEN_CPU_DESC cd, length = CGEN_EXTRACT_FN (cd, insn) (cd, insn, &ex_info, insn_value_cropped, &fields, pc); - /* length < 0 -> error */ + /* Length < 0 -> error. */ if (length < 0) return length; if (length > 0) { CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); - /* length is in bits, result is in bytes */ + /* Length is in bits, result is in bytes. */ return length / 8; } } @@ -343,7 +344,8 @@ default_print_insn (CGEN_CPU_DESC cd, bf Print one instruction from PC on INFO->STREAM. Return the size of the instruction (in bytes). */ -typedef struct cpu_desc_list { +typedef struct cpu_desc_list +{ struct cpu_desc_list *next; int isa; int mach; @@ -428,7 +430,7 @@ print_insn_@arch@ (bfd_vma pc, disassemb if (!cd) abort (); - /* save this away for future reference */ + /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; cl->isa = isa; diff -uprN binutils-2.16.91.0.1/opcodes/cgen-ibld.in binutils-2.16.91.0.2/opcodes/cgen-ibld.in --- binutils-2.16.91.0.1/opcodes/cgen-ibld.in 2005-05-10 15:46:53.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/cgen-ibld.in 2005-07-20 12:27:28.560983986 -0700 @@ -1,25 +1,26 @@ /* Instruction building/extraction support for @arch@. -*- C -*- -THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. -- the resultant file is machine generated, cgen-ibld.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -35,9 +36,9 @@ along with this program; if not, write t #include "opintl.h" #include "safe-ctype.h" -#undef min +#undef min #define min(a,b) ((a) < (b) ? (a) : (b)) -#undef max +#undef max #define max(a,b) ((a) > (b) ? (a) : (b)) /* Used by the ifield rtx function. */ @@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd, if (length == 0) return NULL; -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - if (word_length > 32) abort (); @@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd, #if CGEN_INT_INSN_P /* Cover function to store an insn value into an integral insn. Must go here - because it needs -desc.h for CGEN_INT_INSN_P. */ + because it needs -desc.h for CGEN_INT_INSN_P. */ static void put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, @@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATT int shift = insn_length - length; /* Written this way to avoid undefined behaviour. */ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); } } @@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd, { unsigned long x; int shift; -#if 0 - int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; -#endif + x = cgen_get_insn_value (cd, bufp, word_length); if (CGEN_INSN_LSB0_P) @@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd, return 1; } -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - if (word_length > 32) abort (); @@ -539,4 +527,4 @@ extract_insn_normal (CGEN_CPU_DESC cd, return CGEN_INSN_BITSIZE (insn); } -/* machine generated code added here */ +/* Machine generated code added here. */ diff -uprN binutils-2.16.91.0.1/opcodes/cgen-opc.c binutils-2.16.91.0.2/opcodes/cgen-opc.c --- binutils-2.16.91.0.1/opcodes/cgen-opc.c 2005-05-10 15:46:53.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/cgen-opc.c 2005-07-20 12:27:28.561983821 -0700 @@ -157,7 +157,7 @@ cgen_keyword_search_init (CGEN_KEYWORD * { CGEN_KEYWORD_SEARCH search; - /* FIXME: Need to specify format of PARAMS. */ + /* FIXME: Need to specify format of params. */ if (spec != NULL) abort (); diff -uprN binutils-2.16.91.0.1/opcodes/cgen-ops.h binutils-2.16.91.0.2/opcodes/cgen-ops.h --- binutils-2.16.91.0.1/opcodes/cgen-ops.h 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/opcodes/cgen-ops.h 2005-07-20 12:27:28.562983656 -0700 @@ -0,0 +1,434 @@ +/* Semantics ops support for CGEN-based opcode libraries. + Copyright (C) 2005 Free Software Foundation, Inc. + Contributed by Red Hat. + +This file is part of the GNU opcodes library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef CGEN_SEM_OPS_H +#define CGEN_SEM_OPS_H + +#include + +#if defined (__GNUC__) && ! defined (SEMOPS_DEFINE_INLINE) +#define SEMOPS_DEFINE_INLINE +#define SEMOPS_INLINE extern inline +#else +#define SEMOPS_INLINE +#endif + +/* TODO: Lazy encoding/decoding of fp values. */ + +/* These don't really have a mode. */ +#define ANDIF(x, y) ((x) && (y)) +#define ORIF(x, y) ((x) || (y)) + +#define SUBBI(x, y) ((x) - (y)) +#define ANDBI(x, y) ((x) & (y)) +#define ORBI(x, y) ((x) | (y)) +#define XORBI(x, y) ((x) ^ (y)) +#define NEGBI(x) (- (x)) +#define NOTBI(x) (! (BI) (x)) +#define INVBI(x) (~ (x)) +#define EQBI(x, y) ((BI) (x) == (BI) (y)) +#define NEBI(x, y) ((BI) (x) != (BI) (y)) +#define LTBI(x, y) ((BI) (x) < (BI) (y)) +#define LEBI(x, y) ((BI) (x) <= (BI) (y)) +#define GTBI(x, y) ((BI) (x) > (BI) (y)) +#define GEBI(x, y) ((BI) (x) >= (BI) (y)) +#define LTUBI(x, y) ((BI) (x) < (BI) (y)) +#define LEUBI(x, y) ((BI) (x) <= (BI) (y)) +#define GTUBI(x, y) ((BI) (x) > (BI) (y)) +#define GEUBI(x, y) ((BI) (x) >= (BI) (y)) + +#define ADDQI(x, y) ((x) + (y)) +#define SUBQI(x, y) ((x) - (y)) +#define MULQI(x, y) ((x) * (y)) +#define DIVQI(x, y) ((QI) (x) / (QI) (y)) +#define UDIVQI(x, y) ((UQI) (x) / (UQI) (y)) +#define MODQI(x, y) ((QI) (x) % (QI) (y)) +#define UMODQI(x, y) ((UQI) (x) % (UQI) (y)) +#define SRAQI(x, y) ((QI) (x) >> (y)) +#define SRLQI(x, y) ((UQI) (x) >> (y)) +#define SLLQI(x, y) ((UQI) (x) << (y)) +extern QI RORQI (QI, int); +extern QI ROLQI (QI, int); +#define ANDQI(x, y) ((x) & (y)) +#define ORQI(x, y) ((x) | (y)) +#define XORQI(x, y) ((x) ^ (y)) +#define NEGQI(x) (- (x)) +#define NOTQI(x) (! (QI) (x)) +#define INVQI(x) (~ (x)) +#define ABSQI(x) ((x) < 0 ? -(x) : (x)) +#define EQQI(x, y) ((QI) (x) == (QI) (y)) +#define NEQI(x, y) ((QI) (x) != (QI) (y)) +#define LTQI(x, y) ((QI) (x) < (QI) (y)) +#define LEQI(x, y) ((QI) (x) <= (QI) (y)) +#define GTQI(x, y) ((QI) (x) > (QI) (y)) +#define GEQI(x, y) ((QI) (x) >= (QI) (y)) +#define LTUQI(x, y) ((UQI) (x) < (UQI) (y)) +#define LEUQI(x, y) ((UQI) (x) <= (UQI) (y)) +#define GTUQI(x, y) ((UQI) (x) > (UQI) (y)) +#define GEUQI(x, y) ((UQI) (x) >= (UQI) (y)) + +#define ADDHI(x, y) ((x) + (y)) +#define SUBHI(x, y) ((x) - (y)) +#define MULHI(x, y) ((x) * (y)) +#define DIVHI(x, y) ((HI) (x) / (HI) (y)) +#define UDIVHI(x, y) ((UHI) (x) / (UHI) (y)) +#define MODHI(x, y) ((HI) (x) % (HI) (y)) +#define UMODHI(x, y) ((UHI) (x) % (UHI) (y)) +#define SRAHI(x, y) ((HI) (x) >> (y)) +#define SRLHI(x, y) ((UHI) (x) >> (y)) +#define SLLHI(x, y) ((UHI) (x) << (y)) +extern HI RORHI (HI, int); +extern HI ROLHI (HI, int); +#define ANDHI(x, y) ((x) & (y)) +#define ORHI(x, y) ((x) | (y)) +#define XORHI(x, y) ((x) ^ (y)) +#define NEGHI(x) (- (x)) +#define NOTHI(x) (! (HI) (x)) +#define INVHI(x) (~ (x)) +#define ABSHI(x) ((x) < 0 ? -(x) : (x)) +#define EQHI(x, y) ((HI) (x) == (HI) (y)) +#define NEHI(x, y) ((HI) (x) != (HI) (y)) +#define LTHI(x, y) ((HI) (x) < (HI) (y)) +#define LEHI(x, y) ((HI) (x) <= (HI) (y)) +#define GTHI(x, y) ((HI) (x) > (HI) (y)) +#define GEHI(x, y) ((HI) (x) >= (HI) (y)) +#define LTUHI(x, y) ((UHI) (x) < (UHI) (y)) +#define LEUHI(x, y) ((UHI) (x) <= (UHI) (y)) +#define GTUHI(x, y) ((UHI) (x) > (UHI) (y)) +#define GEUHI(x, y) ((UHI) (x) >= (UHI) (y)) + +#define ADDSI(x, y) ((x) + (y)) +#define SUBSI(x, y) ((x) - (y)) +#define MULSI(x, y) ((x) * (y)) +#define DIVSI(x, y) ((SI) (x) / (SI) (y)) +#define UDIVSI(x, y) ((USI) (x) / (USI) (y)) +#define MODSI(x, y) ((SI) (x) % (SI) (y)) +#define UMODSI(x, y) ((USI) (x) % (USI) (y)) +#define SRASI(x, y) ((SI) (x) >> (y)) +#define SRLSI(x, y) ((USI) (x) >> (y)) +#define SLLSI(x, y) ((USI) (x) << (y)) +extern SI RORSI (SI, int); +extern SI ROLSI (SI, int); +#define ANDSI(x, y) ((x) & (y)) +#define ORSI(x, y) ((x) | (y)) +#define XORSI(x, y) ((x) ^ (y)) +#define NEGSI(x) (- (x)) +#define NOTSI(x) (! (SI) (x)) +#define INVSI(x) (~ (x)) +#define ABSSI(x) ((x) < 0 ? -(x) : (x)) +#define EQSI(x, y) ((SI) (x) == (SI) (y)) +#define NESI(x, y) ((SI) (x) != (SI) (y)) +#define LTSI(x, y) ((SI) (x) < (SI) (y)) +#define LESI(x, y) ((SI) (x) <= (SI) (y)) +#define GTSI(x, y) ((SI) (x) > (SI) (y)) +#define GESI(x, y) ((SI) (x) >= (SI) (y)) +#define LTUSI(x, y) ((USI) (x) < (USI) (y)) +#define LEUSI(x, y) ((USI) (x) <= (USI) (y)) +#define GTUSI(x, y) ((USI) (x) > (USI) (y)) +#define GEUSI(x, y) ((USI) (x) >= (USI) (y)) + +#ifdef DI_FN_SUPPORT +extern DI ADDDI (DI, DI); +extern DI SUBDI (DI, DI); +extern DI MULDI (DI, DI); +extern DI DIVDI (DI, DI); +extern DI UDIVDI (DI, DI); +extern DI MODDI (DI, DI); +extern DI UMODDI (DI, DI); +extern DI SRADI (DI, int); +extern UDI SRLDI (UDI, int); +extern UDI SLLDI (UDI, int); +extern DI RORDI (DI, int); +extern DI ROLDI (DI, int); +extern DI ANDDI (DI, DI); +extern DI ORDI (DI, DI); +extern DI XORDI (DI, DI); +extern DI NEGDI (DI); +extern int NOTDI (DI); +extern DI INVDI (DI); +extern int EQDI (DI, DI); +extern int NEDI (DI, DI); +extern int LTDI (DI, DI); +extern int LEDI (DI, DI); +extern int GTDI (DI, DI); +extern int GEDI (DI, DI); +extern int LTUDI (UDI, UDI); +extern int LEUDI (UDI, UDI); +extern int GTUDI (UDI, UDI); +extern int GEUDI (UDI, UDI); +#else /* ! DI_FN_SUPPORT */ +#define ADDDI(x, y) ((x) + (y)) +#define SUBDI(x, y) ((x) - (y)) +#define MULDI(x, y) ((x) * (y)) +#define DIVDI(x, y) ((DI) (x) / (DI) (y)) +#define UDIVDI(x, y) ((UDI) (x) / (UDI) (y)) +#define MODDI(x, y) ((DI) (x) % (DI) (y)) +#define UMODDI(x, y) ((UDI) (x) % (UDI) (y)) +#define SRADI(x, y) ((DI) (x) >> (y)) +#define SRLDI(x, y) ((UDI) (x) >> (y)) +#define SLLDI(x, y) ((UDI) (x) << (y)) +extern DI RORDI (DI, int); +extern DI ROLDI (DI, int); +#define ANDDI(x, y) ((x) & (y)) +#define ORDI(x, y) ((x) | (y)) +#define XORDI(x, y) ((x) ^ (y)) +#define NEGDI(x) (- (x)) +#define NOTDI(x) (! (DI) (x)) +#define INVDI(x) (~ (x)) +#define ABSDI(x) ((x) < 0 ? -(x) : (x)) +#define EQDI(x, y) ((DI) (x) == (DI) (y)) +#define NEDI(x, y) ((DI) (x) != (DI) (y)) +#define LTDI(x, y) ((DI) (x) < (DI) (y)) +#define LEDI(x, y) ((DI) (x) <= (DI) (y)) +#define GTDI(x, y) ((DI) (x) > (DI) (y)) +#define GEDI(x, y) ((DI) (x) >= (DI) (y)) +#define LTUDI(x, y) ((UDI) (x) < (UDI) (y)) +#define LEUDI(x, y) ((UDI) (x) <= (UDI) (y)) +#define GTUDI(x, y) ((UDI) (x) > (UDI) (y)) +#define GEUDI(x, y) ((UDI) (x) >= (UDI) (y)) +#endif /* DI_FN_SUPPORT */ + +#define EXTBIQI(x) ((QI) (BI) (x)) +#define EXTBIHI(x) ((HI) (BI) (x)) +#define EXTBISI(x) ((SI) (BI) (x)) +#if defined (DI_FN_SUPPORT) +extern DI EXTBIDI (BI); +#else +#define EXTBIDI(x) ((DI) (BI) (x)) +#endif +#define EXTQIHI(x) ((HI) (QI) (x)) +#define EXTQISI(x) ((SI) (QI) (x)) +#if defined (DI_FN_SUPPORT) +extern DI EXTQIDI (QI); +#else +#define EXTQIDI(x) ((DI) (QI) (x)) +#endif +#define EXTHIHI(x) ((HI) (HI) (x)) +#define EXTHISI(x) ((SI) (HI) (x)) +#define EXTSISI(x) ((SI) (SI) (x)) +#if defined (DI_FN_SUPPORT) +extern DI EXTHIDI (HI); +#else +#define EXTHIDI(x) ((DI) (HI) (x)) +#endif +#if defined (DI_FN_SUPPORT) +extern DI EXTSIDI (SI); +#else +#define EXTSIDI(x) ((DI) (SI) (x)) +#endif + +#define ZEXTBIQI(x) ((QI) (BI) (x)) +#define ZEXTBIHI(x) ((HI) (BI) (x)) +#define ZEXTBISI(x) ((SI) (BI) (x)) +#if defined (DI_FN_SUPPORT) +extern DI ZEXTBIDI (BI); +#else +#define ZEXTBIDI(x) ((DI) (BI) (x)) +#endif +#define ZEXTQIHI(x) ((HI) (UQI) (x)) +#define ZEXTQISI(x) ((SI) (UQI) (x)) +#if defined (DI_FN_SUPPORT) +extern DI ZEXTQIDI (QI); +#else +#define ZEXTQIDI(x) ((DI) (UQI) (x)) +#endif +#define ZEXTHISI(x) ((SI) (UHI) (x)) +#define ZEXTHIHI(x) ((HI) (UHI) (x)) +#define ZEXTSISI(x) ((SI) (USI) (x)) +#if defined (DI_FN_SUPPORT) +extern DI ZEXTHIDI (HI); +#else +#define ZEXTHIDI(x) ((DI) (UHI) (x)) +#endif +#if defined (DI_FN_SUPPORT) +extern DI ZEXTSIDI (SI); +#else +#define ZEXTSIDI(x) ((DI) (USI) (x)) +#endif + +#define TRUNCQIBI(x) ((BI) (QI) (x)) +#define TRUNCHIBI(x) ((BI) (HI) (x)) +#define TRUNCHIQI(x) ((QI) (HI) (x)) +#define TRUNCSIBI(x) ((BI) (SI) (x)) +#define TRUNCSIQI(x) ((QI) (SI) (x)) +#define TRUNCSIHI(x) ((HI) (SI) (x)) +#define TRUNCSISI(x) ((SI) (SI) (x)) +#if defined (DI_FN_SUPPORT) +extern BI TRUNCDIBI (DI); +#else +#define TRUNCDIBI(x) ((BI) (DI) (x)) +#endif +#if defined (DI_FN_SUPPORT) +extern QI TRUNCDIQI (DI); +#else +#define TRUNCDIQI(x) ((QI) (DI) (x)) +#endif +#if defined (DI_FN_SUPPORT) +extern HI TRUNCDIHI (DI); +#else +#define TRUNCDIHI(x) ((HI) (DI) (x)) +#endif +#if defined (DI_FN_SUPPORT) +extern SI TRUNCDISI (DI); +#else +#define TRUNCDISI(x) ((SI) (DI) (x)) +#endif + +/* Composing/decomposing the various types. + Word ordering is endian-independent. Words are specified most to least + significant and word number 0 is the most significant word. + ??? May also wish an endian-dependent version. Later. */ + +QI SUBWORDSIQI (SI, int); +HI SUBWORDSIHI (SI, int); +SI SUBWORDSFSI (SF); +SF SUBWORDSISF (SI); +DI SUBWORDDFDI (DF); +DF SUBWORDDIDF (DI); +QI SUBWORDDIQI (DI, int); +HI SUBWORDDIHI (DI, int); +SI SUBWORDDISI (DI, int); +SI SUBWORDDFSI (DF, int); +SI SUBWORDXFSI (XF, int); +SI SUBWORDTFSI (TF, int); + +UQI SUBWORDSIUQI (SI, int); +UQI SUBWORDDIUQI (DI, int); + +#ifdef SEMOPS_DEFINE_INLINE + +SEMOPS_INLINE SF +SUBWORDSISF (SI in) +{ + union { SI in; SF out; } x; + x.in = in; + return x.out; +} + +SEMOPS_INLINE DF +SUBWORDDIDF (DI in) +{ + union { DI in; DF out; } x; + x.in = in; + return x.out; +} + +SEMOPS_INLINE QI +SUBWORDSIQI (SI in, int byte) +{ + assert (byte >= 0 && byte <= 3); + return (UQI) (in >> (8 * (3 - byte))) & 0xFF; +} + +SEMOPS_INLINE UQI +SUBWORDSIUQI (SI in, int byte) +{ + assert (byte >= 0 && byte <= 3); + return (UQI) (in >> (8 * (3 - byte))) & 0xFF; +} + +SEMOPS_INLINE QI +SUBWORDDIQI (DI in, int byte) +{ + assert (byte >= 0 && byte <= 7); + return (UQI) (in >> (8 * (7 - byte))) & 0xFF; +} + +SEMOPS_INLINE HI +SUBWORDDIHI (DI in, int word) +{ + assert (word >= 0 && word <= 3); + return (UHI) (in >> (16 * (3 - word))) & 0xFFFF; +} + +SEMOPS_INLINE HI +SUBWORDSIHI (SI in, int word) +{ + if (word == 0) + return (USI) in >> 16; + else + return in; +} + +SEMOPS_INLINE SI +SUBWORDSFSI (SF in) +{ + union { SF in; SI out; } x; + x.in = in; + return x.out; +} + +SEMOPS_INLINE DI +SUBWORDDFDI (DF in) +{ + union { DF in; DI out; } x; + x.in = in; + return x.out; +} + +SEMOPS_INLINE UQI +SUBWORDDIUQI (DI in, int byte) +{ + assert (byte >= 0 && byte <= 7); + return (UQI) (in >> (8 * (7 - byte))); +} + +SEMOPS_INLINE SI +SUBWORDDISI (DI in, int word) +{ + if (word == 0) + return (UDI) in >> 32; + else + return in; +} + +SEMOPS_INLINE SI +SUBWORDDFSI (DF in, int word) +{ + /* Note: typedef UDI DF; */ + if (word == 0) + return (UDI) in >> 32; + else + return in; +} + +SEMOPS_INLINE SI +SUBWORDXFSI (XF in, int word) +{ + /* Note: typedef struct { SI parts[3]; } XF; */ + union { XF in; SI out[3]; } x; + x.in = in; + return x.out[word]; +} + +SEMOPS_INLINE SI +SUBWORDTFSI (TF in, int word) +{ + /* Note: typedef struct { SI parts[4]; } TF; */ + union { TF in; SI out[4]; } x; + x.in = in; + return x.out[word]; +} + +#endif /* SUBWORD,JOIN */ + +#endif /* CGEN_SEM_OPS_H */ diff -uprN binutils-2.16.91.0.1/opcodes/cgen-types.h binutils-2.16.91.0.2/opcodes/cgen-types.h --- binutils-2.16.91.0.1/opcodes/cgen-types.h 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/opcodes/cgen-types.h 2005-07-20 12:27:28.563983491 -0700 @@ -0,0 +1,44 @@ +/* Type definitions for CGEN-based opcode libraries. + Copyright (C) 2005 Free Software Foundation, Inc. + Contributed by Red Hat. + +This file is part of the GNU opcodes library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef CGEN_TYPES_H +#define CGEN_TYPES_H + +#include + +typedef int8_t QI; +typedef uint8_t UQI; +typedef int16_t HI; +typedef uint16_t UHI; +typedef int32_t SI; +typedef uint32_t USI; +typedef int64_t DI; +typedef uint64_t UDI; + +typedef int INT; +typedef unsigned int UINT; + +typedef float SF; +typedef double DF; +typedef long double XF, TF; + +#endif /* CGEN_TYPES_H */ diff -uprN binutils-2.16.91.0.1/opcodes/ChangeLog binutils-2.16.91.0.2/opcodes/ChangeLog --- binutils-2.16.91.0.1/opcodes/ChangeLog 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/ChangeLog 2005-07-20 12:27:28.526989591 -0700 @@ -1,3 +1,183 @@ +2005-07-18 Nick Clifton + + * configure.in: Restore alpha ordering to list of arches. + * configure: Regenerate. + * disassemble.c: Restore alpha ordering to list of arches. + +2005-07-18 Nick Clifton + + * m32c-asm.c: Regenerate. + * m32c-desc.c: Regenerate. + * m32c-desc.h: Regenerate. + * m32c-dis.c: Regenerate. + * m32c-ibld.h: Regenerate. + * m32c-opc.c: Regenerate. + * m32c-opc.h: Regenerate. + +2005-07-18 H.J. Lu + + * i386-dis.c (PNI_Fixup): Update comment. + (VMX_Fixup): Properly handle the suffix check. + +2005-07-16 John David Anglin + + * hppa-dis.c (print_insn_hppa): Add space after 'w' in wide-mode + mfctl disassembly. + +2005-07-16 Alan Modra + + * Makefile.am: Run "make dep-am". + (stamp-m32c): Fix cpu dependencies. + * Makefile.in: Regenerate. + * ip2k-dis.c: Regenerate. + +2007-07-15 H.J. Lu + + * i386-dis.c (OP_VMX): New. Handle Intel VMX Instructions. + (VMX_Fixup): New. Fix up Intel VMX Instructions. + (Em): New. + (Gm): New. + (VM): New. + (dis386_twobyte): Updated entries 0x78 and 0x79. + (twobyte_has_modrm): Likewise. + (grps): Use OP_VMX in the "sgdtIQ" entry. Updated GRP9. + (OP_G): Handle m_mode. + +2005-07-14 Jim Blandy + + Add support for the Renesas M32C and M16C. + * m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c: New. + * m32c-desc.h, m32c-opc.h: New. + * Makefile.am (HFILES): List m32c-desc.h and m32c-opc.h. + (CFILES): List m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, + m32c-opc.c. + (ALL_MACHINES): List m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, + m32c-ibld.lo, m32c-opc.lo. + (CLEANFILES): List stamp-m32c. + (M32C_DEPS): List stamp-m32c, if CGEN_MAINT. + (CGEN_CPUS): Add m32c. + (m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c) + (m32c-desc.h, m32c-opc.h): Depend on M32C_DEPS. + (m32c_opc_h): New variable. + (stamp-m32c, m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo) + (m32c-opc.lo): New rules. + * Makefile.in: Regenerated. + * configure.in: Add case for bfd_m32c_arch. + * configure: Regenerated. + * disassemble.c (ARCH_m32c): New. + [ARCH_m32c]: #include "m32c-desc.h". + (disassembler) [ARCH_m32c]: Add case for bfd_arch_m32c. + (disassemble_init_for_target) [ARCH_m32c]: Same. + + * cgen-ops.h, cgen-types.h: New files. + * Makefile.am (HFILES): List them. + * Makefile.in: Regenerated. + +2005-07-07 Kaveh R. Ghazi + + * arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c, + d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c, + ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c, + m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c, + ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c, + v850-dis.c: Fix format bugs. + * ia64-gen.c (fail, warn): Add format attribute. + * or32-opc.c (debug): Likewise. + +2005-07-07 Khem Raj + + * arm-dis.c (opcode32 arm_opcodes): Fix ARM VFP fadds instruction + disassembly pattern. + +2005-07-06 Alan Modra + + * Makefile.am (stamp-m32r): Fix path to cpu files. + (stamp-m32r, stamp-iq2000): Likewise. + * Makefile.in: Regenerate. + * m32r-asm.c: Regenerate. + * po/POTFILES.in: Remove arm-opc.h. Add ms1-asm.c, ms1-desc.c, + ms1-desc.h, ms1-dis.c, ms1-ibld.c, ms1-opc.c, ms1-opc.h. + +2005-07-05 Nick Clifton + + * iq2000-asm.c: Regenerate. + * ms1-asm.c: Regenerate. + +2005-07-05 Jan Beulich + + * i386-dis.c (SVME_Fixup): New. + (grps): Use it for the lidt entry. + (PNI_Fixup): Call OP_M rather than OP_E. + (INVLPG_Fixup): Likewise. + +2005-07-04 H.J. Lu + + * tic30-dis.c (cnvt_tmsfloat_ieee): Use HUGE_VALF if defined. + +2005-07-01 Nick Clifton + + * a29k-dis.c: Update to ISO C90 style function declarations and + fix formatting. + * alpha-opc.c: Likewise. + * arc-dis.c: Likewise. + * arc-opc.c: Likewise. + * avr-dis.c: Likewise. + * cgen-asm.in: Likewise. + * cgen-dis.in: Likewise. + * cgen-ibld.in: Likewise. + * cgen-opc.c: Likewise. + * cris-dis.c: Likewise. + * d10v-dis.c: Likewise. + * d30v-dis.c: Likewise. + * d30v-opc.c: Likewise. + * dis-buf.c: Likewise. + * dlx-dis.c: Likewise. + * h8300-dis.c: Likewise. + * h8500-dis.c: Likewise. + * hppa-dis.c: Likewise. + * i370-dis.c: Likewise. + * i370-opc.c: Likewise. + * m10200-dis.c: Likewise. + * m10300-dis.c: Likewise. + * m68k-dis.c: Likewise. + * m88k-dis.c: Likewise. + * mips-dis.c: Likewise. + * mmix-dis.c: Likewise. + * msp430-dis.c: Likewise. + * ns32k-dis.c: Likewise. + * or32-dis.c: Likewise. + * or32-opc.c: Likewise. + * pdp11-dis.c: Likewise. + * pj-dis.c: Likewise. + * s390-dis.c: Likewise. + * sh-dis.c: Likewise. + * sh64-dis.c: Likewise. + * sparc-dis.c: Likewise. + * sparc-opc.c: Likewise. + * sysdep.h: Likewise. + * tic30-dis.c: Likewise. + * tic4x-dis.c: Likewise. + * tic80-dis.c: Likewise. + * v850-dis.c: Likewise. + * v850-opc.c: Likewise. + * vax-dis.c: Likewise. + * w65-dis.c: Likewise. + * z8kgen.c: Likewise. + + * fr30-*: Regenerate. + * frv-*: Regenerate. + * ip2k-*: Regenerate. + * iq2000-*: Regenerate. + * m32r-*: Regenerate. + * ms1-*: Regenerate. + * openrisc-*: Regenerate. + * xstormy16-*: Regenerate. + +2005-06-23 Ben Elliston + + * m68k-dis.c: Use ISC C90. + * m68k-opc.c: Formatting fixes. + 2005-06-16 David Ung * mips16-opc.c (mips16_opcodes): Add the following MIPS16e diff -uprN binutils-2.16.91.0.1/opcodes/configure binutils-2.16.91.0.2/opcodes/configure --- binutils-2.16.91.0.1/opcodes/configure 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/configure 2005-07-20 12:27:28.574981677 -0700 @@ -8771,6 +8771,7 @@ if test x${all_targets} = xfalse ; then bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;; bfd_z8k_arch) ta="$ta z8k-dis.lo" ;; bfd_frv_arch) ta="$ta frv-asm.lo frv-desc.lo frv-dis.lo frv-ibld.lo frv-opc.lo" using_cgen=yes ;; + bfd_m32c_arch) ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;; "") ;; *) { { echo "$as_me:$LINENO: error: *** unknown target architecture $arch" >&5 diff -uprN binutils-2.16.91.0.1/opcodes/configure.in binutils-2.16.91.0.2/opcodes/configure.in --- binutils-2.16.91.0.1/opcodes/configure.in 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/configure.in 2005-07-20 12:27:28.575981512 -0700 @@ -166,6 +166,7 @@ if test x${all_targets} = xfalse ; then bfd_d30v_arch) ta="$ta d30v-dis.lo d30v-opc.lo" ;; bfd_dlx_arch) ta="$ta dlx-dis.lo" ;; bfd_fr30_arch) ta="$ta fr30-asm.lo fr30-desc.lo fr30-dis.lo fr30-ibld.lo fr30-opc.lo" using_cgen=yes ;; + bfd_frv_arch) ta="$ta frv-asm.lo frv-desc.lo frv-dis.lo frv-ibld.lo frv-opc.lo" using_cgen=yes ;; bfd_h8300_arch) ta="$ta h8300-dis.lo" ;; bfd_h8500_arch) ta="$ta h8500-dis.lo" ;; bfd_hppa_arch) ta="$ta hppa-dis.lo" ;; @@ -176,6 +177,7 @@ if test x${all_targets} = xfalse ; then bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;; bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;; + bfd_m32c_arch) ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;; bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;; bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; @@ -230,7 +232,6 @@ if test x${all_targets} = xfalse ; then bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;; bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;; bfd_z8k_arch) ta="$ta z8k-dis.lo" ;; - bfd_frv_arch) ta="$ta frv-asm.lo frv-desc.lo frv-dis.lo frv-ibld.lo frv-opc.lo" using_cgen=yes ;; "") ;; *) AC_MSG_ERROR(*** unknown target architecture $arch) ;; diff -uprN binutils-2.16.91.0.1/opcodes/cris-dis.c binutils-2.16.91.0.2/opcodes/cris-dis.c --- binutils-2.16.91.0.1/opcodes/cris-dis.c 2005-05-10 15:46:53.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/cris-dis.c 2005-07-20 12:27:28.584980029 -0700 @@ -3,21 +3,22 @@ Contributed by Axis Communications AB, Lund, Sweden. Written by Hans-Peter Nilsson. -This file is part of the GNU binutils and GDB, the GNU debugger. + This file is part of the GNU binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any later + version. + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "dis-asm.h" #include "sysdep.h" @@ -92,56 +93,15 @@ static long no_of_case_offsets = 0; /* Candidate for next case_offset. */ static long last_immediate = 0; -static int number_of_bits - PARAMS ((unsigned int)); -static char *format_hex - PARAMS ((unsigned long, char *, struct cris_disasm_data *)); -static char *format_dec - PARAMS ((long, char *, int)); -static char *format_reg - PARAMS ((struct cris_disasm_data *, int, char *, bfd_boolean)); -static char *format_sup_reg - PARAMS ((unsigned int, char *, bfd_boolean)); static int cris_constraint - PARAMS ((const char *, unsigned int, unsigned int, - struct cris_disasm_data *)); -static unsigned bytes_to_skip - PARAMS ((unsigned int, const struct cris_opcode *, - enum cris_disass_family)); -static char *print_flags - PARAMS ((struct cris_disasm_data *, unsigned int, char *)); -static void print_with_operands - PARAMS ((const struct cris_opcode *, unsigned int, unsigned char *, - bfd_vma, disassemble_info *, const struct cris_opcode *, - unsigned int, unsigned char *, bfd_boolean)); -static const struct cris_spec_reg *spec_reg_info - PARAMS ((unsigned int, enum cris_disass_family)); -static int print_insn_cris_generic - PARAMS ((bfd_vma, disassemble_info *, bfd_boolean)); -static int print_insn_cris_with_register_prefix - PARAMS ((bfd_vma, disassemble_info *)); -static int print_insn_cris_without_register_prefix - PARAMS ((bfd_vma, disassemble_info *)); -static int print_insn_crisv32_with_register_prefix - PARAMS ((bfd_vma, disassemble_info *)); -static int print_insn_crisv32_without_register_prefix - PARAMS ((bfd_vma, disassemble_info *)); -static int print_insn_crisv10_v32_with_register_prefix - PARAMS ((bfd_vma, disassemble_info *)); -static int print_insn_crisv10_v32_without_register_prefix - PARAMS ((bfd_vma, disassemble_info *)); -static bfd_boolean cris_parse_disassembler_options - PARAMS ((disassemble_info *, enum cris_disass_family)); -static const struct cris_opcode *get_opcode_entry - PARAMS ((unsigned int, unsigned int, struct cris_disasm_data *)); + (const char *, unsigned, unsigned, struct cris_disasm_data *); /* Parse disassembler options and store state in info. FIXME: For the time being, we abuse static variables. */ static bfd_boolean -cris_parse_disassembler_options (info, distype) - disassemble_info *info; - enum cris_disass_family distype; +cris_parse_disassembler_options (disassemble_info *info, + enum cris_disass_family distype) { struct cris_disasm_data *disdata; @@ -159,13 +119,11 @@ cris_parse_disassembler_options (info, d return TRUE; } - static const struct cris_spec_reg * -spec_reg_info (sreg, distype) - unsigned int sreg; - enum cris_disass_family distype; +spec_reg_info (unsigned int sreg, enum cris_disass_family distype) { int i; + for (i = 0; cris_spec_regs[i].name != NULL; i++) { if (cris_spec_regs[i].number == sreg) @@ -196,8 +154,7 @@ spec_reg_info (sreg, distype) /* Return the number of bits in the argument. */ static int -number_of_bits (val) - unsigned int val; +number_of_bits (unsigned int val) { int bits; @@ -210,10 +167,9 @@ number_of_bits (val) /* Get an entry in the opcode-table. */ static const struct cris_opcode * -get_opcode_entry (insn, prefix_insn, disdata) - unsigned int insn; - unsigned int prefix_insn; - struct cris_disasm_data *disdata; +get_opcode_entry (unsigned int insn, + unsigned int prefix_insn, + struct cris_disasm_data *disdata) { /* For non-prefixed insns, we keep a table of pointers, indexed by the insn code. Each entry is initialized when found to be NULL. */ @@ -440,121 +396,21 @@ get_opcode_entry (insn, prefix_insn, dis return max_matchedp; } -/* Format number as hex with a leading "0x" into outbuffer. */ - -static char * -format_hex (number, outbuffer, disdata) - unsigned long number; - char *outbuffer; - struct cris_disasm_data *disdata; -{ - /* Truncate negative numbers on >32-bit hosts. */ - number &= 0xffffffff; - - sprintf (outbuffer, "0x%lx", number); - - /* Save this value for the "case" support. */ - if (TRACE_CASE) - last_immediate = number; - - return outbuffer + strlen (outbuffer); -} - -/* Format number as decimal into outbuffer. Parameter signedp says - whether the number should be formatted as signed (!= 0) or - unsigned (== 0). */ - -static char * -format_dec (number, outbuffer, signedp) - long number; - char *outbuffer; - int signedp; -{ - last_immediate = number; - sprintf (outbuffer, signedp ? "%ld" : "%lu", number); - - return outbuffer + strlen (outbuffer); -} - -/* Format the name of the general register regno into outbuffer. */ - -static char * -format_reg (disdata, regno, outbuffer_start, with_reg_prefix) - struct cris_disasm_data *disdata; - int regno; - char *outbuffer_start; - bfd_boolean with_reg_prefix; -{ - char *outbuffer = outbuffer_start; - - if (with_reg_prefix) - *outbuffer++ = REGISTER_PREFIX_CHAR; - - switch (regno) - { - case 15: - /* For v32, there is no context in which we output PC. */ - if (disdata->distype == cris_dis_v32) - strcpy (outbuffer, "acr"); - else - strcpy (outbuffer, "pc"); - break; - - case 14: - strcpy (outbuffer, "sp"); - break; - - default: - sprintf (outbuffer, "r%d", regno); - break; - } - - return outbuffer_start + strlen (outbuffer_start); -} - -/* Format the name of a support register into outbuffer. */ - -static char * -format_sup_reg (regno, outbuffer_start, with_reg_prefix) - unsigned int regno; - char *outbuffer_start; - bfd_boolean with_reg_prefix; -{ - char *outbuffer = outbuffer_start; - int i; - - if (with_reg_prefix) - *outbuffer++ = REGISTER_PREFIX_CHAR; - - for (i = 0; cris_support_regs[i].name != NULL; i++) - if (cris_support_regs[i].number == regno) - { - sprintf (outbuffer, "%s", cris_support_regs[i].name); - return outbuffer_start + strlen (outbuffer_start); - } - - /* There's supposed to be register names covering all numbers, though - some may be generic names. */ - sprintf (outbuffer, "format_sup_reg-BUG"); - return outbuffer_start + strlen (outbuffer_start); -} - /* Return -1 if the constraints of a bitwise-matched instruction say that there is no match. Otherwise return a nonnegative number indicating the confidence in the match (higher is better). */ static int -cris_constraint (cs, insn, prefix_insn, disdata) - const char *cs; - unsigned int insn; - unsigned int prefix_insn; - struct cris_disasm_data *disdata; +cris_constraint (const char *cs, + unsigned int insn, + unsigned int prefix_insn, + struct cris_disasm_data *disdata) { int retval = 0; int tmp; int prefix_ok = 0; - const char *s; + for (s = cs; *s; s++) switch (*s) { @@ -697,13 +553,105 @@ cris_constraint (cs, insn, prefix_insn, return retval; } +/* Format number as hex with a leading "0x" into outbuffer. */ + +static char * +format_hex (unsigned long number, + char *outbuffer, + struct cris_disasm_data *disdata) +{ + /* Truncate negative numbers on >32-bit hosts. */ + number &= 0xffffffff; + + sprintf (outbuffer, "0x%lx", number); + + /* Save this value for the "case" support. */ + if (TRACE_CASE) + last_immediate = number; + + return outbuffer + strlen (outbuffer); +} + +/* Format number as decimal into outbuffer. Parameter signedp says + whether the number should be formatted as signed (!= 0) or + unsigned (== 0). */ + +static char * +format_dec (long number, char *outbuffer, int signedp) +{ + last_immediate = number; + sprintf (outbuffer, signedp ? "%ld" : "%lu", number); + + return outbuffer + strlen (outbuffer); +} + +/* Format the name of the general register regno into outbuffer. */ + +static char * +format_reg (struct cris_disasm_data *disdata, + int regno, + char *outbuffer_start, + bfd_boolean with_reg_prefix) +{ + char *outbuffer = outbuffer_start; + + if (with_reg_prefix) + *outbuffer++ = REGISTER_PREFIX_CHAR; + + switch (regno) + { + case 15: + /* For v32, there is no context in which we output PC. */ + if (disdata->distype == cris_dis_v32) + strcpy (outbuffer, "acr"); + else + strcpy (outbuffer, "pc"); + break; + + case 14: + strcpy (outbuffer, "sp"); + break; + + default: + sprintf (outbuffer, "r%d", regno); + break; + } + + return outbuffer_start + strlen (outbuffer_start); +} + +/* Format the name of a support register into outbuffer. */ + +static char * +format_sup_reg (unsigned int regno, + char *outbuffer_start, + bfd_boolean with_reg_prefix) +{ + char *outbuffer = outbuffer_start; + int i; + + if (with_reg_prefix) + *outbuffer++ = REGISTER_PREFIX_CHAR; + + for (i = 0; cris_support_regs[i].name != NULL; i++) + if (cris_support_regs[i].number == regno) + { + sprintf (outbuffer, "%s", cris_support_regs[i].name); + return outbuffer_start + strlen (outbuffer_start); + } + + /* There's supposed to be register names covering all numbers, though + some may be generic names. */ + sprintf (outbuffer, "format_sup_reg-BUG"); + return outbuffer_start + strlen (outbuffer_start); +} + /* Return the length of an instruction. */ static unsigned -bytes_to_skip (insn, matchedp, distype) - unsigned int insn; - const struct cris_opcode *matchedp; - enum cris_disass_family distype; +bytes_to_skip (unsigned int insn, + const struct cris_opcode *matchedp, + enum cris_disass_family distype) { /* Each insn is a word plus "immediate" operands. */ unsigned to_skip = 2; @@ -750,10 +698,7 @@ bytes_to_skip (insn, matchedp, distype) /* Print condition code flags. */ static char * -print_flags (disdata, insn, cp) - struct cris_disasm_data *disdata; - unsigned int insn; - char *cp; +print_flags (struct cris_disasm_data *disdata, unsigned int insn, char *cp) { /* Use the v8 (Etrax 100) flag definitions for disassembly. The differences with v0 (Etrax 1..4) vs. Svinto are: @@ -780,20 +725,18 @@ print_flags (disdata, insn, cp) supposed to be output as an address mode. */ static void -print_with_operands (opcodep, insn, buffer, addr, info, prefix_opcodep, - prefix_insn, prefix_buffer, with_reg_prefix) - const struct cris_opcode *opcodep; - unsigned int insn; - unsigned char *buffer; - bfd_vma addr; - disassemble_info *info; - - /* If a prefix insn was before this insn (and is supposed to be - output as an address), here is a description of it. */ - const struct cris_opcode *prefix_opcodep; - unsigned int prefix_insn; - unsigned char *prefix_buffer; - bfd_boolean with_reg_prefix; +print_with_operands (const struct cris_opcode *opcodep, + unsigned int insn, + unsigned char *buffer, + bfd_vma addr, + disassemble_info *info, + /* If a prefix insn was before this insn (and is supposed + to be output as an address), here is a description of + it. */ + const struct cris_opcode *prefix_opcodep, + unsigned int prefix_insn, + unsigned char *prefix_buffer, + bfd_boolean with_reg_prefix) { /* Get a buffer of somewhat reasonable size where we store intermediate parts of the insn. */ @@ -1420,15 +1363,13 @@ print_with_operands (opcodep, insn, buff /* It could also be an "add", if there are negative case-values. */ else if (strncmp (opcodep->name, "add", 3) == 0) - { - /* The first case is the negated operand to the add. */ - case_offset = -last_immediate; - } + /* The first case is the negated operand to the add. */ + case_offset = -last_immediate; + /* A bound insn will tell us the number of cases. */ else if (strncmp (opcodep->name, "bound", 5) == 0) - { - no_of_case_offsets = last_immediate + 1; - } + no_of_case_offsets = last_immediate + 1; + /* A jump or jsr or branch breaks the chain of insns for a case-table, so assume default first-case again. */ else if (info->insn_type == dis_jsr @@ -1444,10 +1385,9 @@ print_with_operands (opcodep, insn, buff WITH_REG_PREFIX. */ static int -print_insn_cris_generic (memaddr, info, with_reg_prefix) - bfd_vma memaddr; - disassemble_info *info; - bfd_boolean with_reg_prefix; +print_insn_cris_generic (bfd_vma memaddr, + disassemble_info *info, + bfd_boolean with_reg_prefix) { int nbytes; unsigned int insn; @@ -1508,7 +1448,7 @@ print_insn_cris_generic (memaddr, info, advance += 2; /* If to print data as offsets, then shortcut here. */ - (*info->fprintf_func) (info->stream, "case %d%s: -> ", + (*info->fprintf_func) (info->stream, "case %ld%s: -> ", case_offset + no_of_case_offsets - case_offset_counter, case_offset_counter == 1 ? "/default" : @@ -1580,7 +1520,7 @@ print_insn_cris_generic (memaddr, info, if (matchedp == NULL) { - (*info->fprintf_func) (info->stream, "??0x%lx", insn); + (*info->fprintf_func) (info->stream, "??0x%x", insn); advance += 2; info->insn_type = dis_noninsn; @@ -1631,9 +1571,8 @@ print_insn_cris_generic (memaddr, info, /* Disassemble, prefixing register names with `$'. CRIS v0..v10. */ static int -print_insn_cris_with_register_prefix (vma, info) - bfd_vma vma; - disassemble_info *info; +print_insn_cris_with_register_prefix (bfd_vma vma, + disassemble_info *info) { if (info->private_data == NULL && !cris_parse_disassembler_options (info, cris_dis_v0_v10)) @@ -1644,9 +1583,8 @@ print_insn_cris_with_register_prefix (vm /* Disassemble, prefixing register names with `$'. CRIS v32. */ static int -print_insn_crisv32_with_register_prefix (vma, info) - bfd_vma vma; - disassemble_info *info; +print_insn_crisv32_with_register_prefix (bfd_vma vma, + disassemble_info *info) { if (info->private_data == NULL && !cris_parse_disassembler_options (info, cris_dis_v32)) @@ -1658,9 +1596,8 @@ print_insn_crisv32_with_register_prefix Common v10 and v32 subset. */ static int -print_insn_crisv10_v32_with_register_prefix (vma, info) - bfd_vma vma; - disassemble_info *info; +print_insn_crisv10_v32_with_register_prefix (bfd_vma vma, + disassemble_info *info) { if (info->private_data == NULL && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32)) @@ -1671,9 +1608,8 @@ print_insn_crisv10_v32_with_register_pre /* Disassemble, no prefixes on register names. CRIS v0..v10. */ static int -print_insn_cris_without_register_prefix (vma, info) - bfd_vma vma; - disassemble_info *info; +print_insn_cris_without_register_prefix (bfd_vma vma, + disassemble_info *info) { if (info->private_data == NULL && !cris_parse_disassembler_options (info, cris_dis_v0_v10)) @@ -1684,9 +1620,8 @@ print_insn_cris_without_register_prefix /* Disassemble, no prefixes on register names. CRIS v32. */ static int -print_insn_crisv32_without_register_prefix (vma, info) - bfd_vma vma; - disassemble_info *info; +print_insn_crisv32_without_register_prefix (bfd_vma vma, + disassemble_info *info) { if (info->private_data == NULL && !cris_parse_disassembler_options (info, cris_dis_v32)) @@ -1698,9 +1633,8 @@ print_insn_crisv32_without_register_pref Common v10 and v32 subset. */ static int -print_insn_crisv10_v32_without_register_prefix (vma, info) - bfd_vma vma; - disassemble_info *info; +print_insn_crisv10_v32_without_register_prefix (bfd_vma vma, + disassemble_info *info) { if (info->private_data == NULL && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32)) @@ -1714,8 +1648,7 @@ print_insn_crisv10_v32_without_register_ functions seen above. */ disassembler_ftype -cris_get_disassembler (abfd) - bfd *abfd; +cris_get_disassembler (bfd *abfd) { /* If there's no bfd in sight, we return what is valid as input in all contexts if fed back to the assembler: disassembly *with* register @@ -1742,9 +1675,7 @@ cris_get_disassembler (abfd) return print_insn_cris_without_register_prefix; } -/* - * Local variables: - * eval: (c-set-style "gnu") - * indent-tabs-mode: t - * End: - */ +/* Local variables: + eval: (c-set-style "gnu") + indent-tabs-mode: t + End: */ diff -uprN binutils-2.16.91.0.1/opcodes/crx-dis.c binutils-2.16.91.0.2/opcodes/crx-dis.c --- binutils-2.16.91.0.1/opcodes/crx-dis.c 2005-05-10 15:46:53.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/crx-dis.c 2005-07-20 12:27:28.588979369 -0700 @@ -547,7 +547,7 @@ print_arg (argument *a, bfd_vma memaddr, func (stream, "%s", string); } else - func (stream, "$0x%x", a->constant); + func (stream, "$0x%lx", a->constant); } else { @@ -556,11 +556,11 @@ print_arg (argument *a, bfd_vma memaddr, } } else - func (stream, "$0x%x", a->constant); + func (stream, "$0x%lx", a->constant); break; case arg_idxr: - func (stream, "0x%x(%s,%s,%d)", a->constant, getregname (a->r), + func (stream, "0x%lx(%s,%s,%d)", a->constant, getregname (a->r), getregname (a->i_r), powerof2 (a->scale)); break; @@ -569,7 +569,7 @@ print_arg (argument *a, bfd_vma memaddr, break; case arg_cr: - func (stream, "0x%x(%s)", a->constant, getregname (a->r)); + func (stream, "0x%lx(%s)", a->constant, getregname (a->r)); if (IS_INSN_TYPE (LD_STOR_INS_INC)) func (stream, "+"); diff -uprN binutils-2.16.91.0.1/opcodes/d10v-dis.c binutils-2.16.91.0.2/opcodes/d10v-dis.c --- binutils-2.16.91.0.1/opcodes/d10v-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/d10v-dis.c 2005-07-20 12:27:28.589979204 -0700 @@ -1,19 +1,20 @@ /* Disassemble D10V instructions. - Copyright 1996, 1997, 1998, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 2000, 2001, 2005 Free Software Foundation, Inc. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include @@ -25,57 +26,12 @@ Foundation, Inc., 51 Franklin Street - F so use this mask to keep the parts we want. */ #define PC_MASK 0x0303FFFF -static void dis_2_short PARAMS ((unsigned long insn, bfd_vma memaddr, - struct disassemble_info *info, int order)); -static void dis_long PARAMS ((unsigned long insn, bfd_vma memaddr, - struct disassemble_info *info)); -static void print_operand - PARAMS ((struct d10v_operand *, long unsigned int, struct d10v_opcode *, - bfd_vma, struct disassemble_info *)); - -int -print_insn_d10v (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - int status; - bfd_byte buffer[4]; - unsigned long insn; - - status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn = bfd_getb32 (buffer); - - status = insn & FM11; - switch (status) - { - case 0: - dis_2_short (insn, memaddr, info, 2); - break; - case FM01: - dis_2_short (insn, memaddr, info, 0); - break; - case FM10: - dis_2_short (insn, memaddr, info, 1); - break; - case FM11: - dis_long (insn, memaddr, info); - break; - } - return 4; -} - static void -print_operand (oper, insn, op, memaddr, info) - struct d10v_operand *oper; - unsigned long insn; - struct d10v_opcode *op; - bfd_vma memaddr; - struct disassemble_info *info; +print_operand (struct d10v_operand *oper, + unsigned long insn, + struct d10v_opcode *op, + bfd_vma memaddr, + struct disassemble_info *info) { int num, shift; @@ -117,6 +73,7 @@ print_operand (oper, insn, op, memaddr, { int i; int match = 0; + num += (oper->flags & (OPERAND_GPR | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL)); if (oper->flags & (OPERAND_ACC0 | OPERAND_ACC1)) @@ -155,6 +112,7 @@ print_operand (oper, insn, op, memaddr, { long max; int neg = 0; + max = (1 << (oper->bits - 1)); if (num & max) { @@ -189,10 +147,9 @@ print_operand (oper, insn, op, memaddr, } static void -dis_long (insn, memaddr, info) - unsigned long insn; - bfd_vma memaddr; - struct disassemble_info *info; +dis_long (unsigned long insn, + bfd_vma memaddr, + struct disassemble_info *info) { int i; struct d10v_opcode *op = (struct d10v_opcode *) d10v_opcodes; @@ -202,10 +159,12 @@ dis_long (insn, memaddr, info) while (op->name) { - if ((op->format & LONG_OPCODE) && ((op->mask & insn) == (unsigned long) op->opcode)) + if ((op->format & LONG_OPCODE) + && ((op->mask & insn) == (unsigned long) op->opcode)) { match = 1; (*info->fprintf_func) (info->stream, "%s\t", op->name); + for (i = 0; op->operands[i]; i++) { oper = (struct d10v_operand *) &d10v_operands[op->operands[i]]; @@ -223,18 +182,17 @@ dis_long (insn, memaddr, info) } if (!match) - (*info->fprintf_func) (info->stream, ".long\t0x%08x", insn); + (*info->fprintf_func) (info->stream, ".long\t0x%08lx", insn); if (need_paren) (*info->fprintf_func) (info->stream, ")"); } static void -dis_2_short (insn, memaddr, info, order) - unsigned long insn; - bfd_vma memaddr; - struct disassemble_info *info; - int order; +dis_2_short (unsigned long insn, + bfd_vma memaddr, + struct disassemble_info *info, + int order) { int i, j; unsigned int ins[2]; @@ -297,8 +255,42 @@ dis_2_short (insn, memaddr, info, order) } if (num_match == 0) - (*info->fprintf_func) (info->stream, ".long\t0x%08x", insn); + (*info->fprintf_func) (info->stream, ".long\t0x%08lx", insn); if (need_paren) (*info->fprintf_func) (info->stream, ")"); } + +int +print_insn_d10v (bfd_vma memaddr, struct disassemble_info *info) +{ + int status; + bfd_byte buffer[4]; + unsigned long insn; + + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb32 (buffer); + + status = insn & FM11; + switch (status) + { + case 0: + dis_2_short (insn, memaddr, info, 2); + break; + case FM01: + dis_2_short (insn, memaddr, info, 0); + break; + case FM10: + dis_2_short (insn, memaddr, info, 1); + break; + case FM11: + dis_long (insn, memaddr, info); + break; + } + return 4; +} diff -uprN binutils-2.16.91.0.1/opcodes/d30v-dis.c binutils-2.16.91.0.2/opcodes/d30v-dis.c --- binutils-2.16.91.0.1/opcodes/d30v-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/d30v-dis.c 2005-07-20 12:27:28.591978875 -0700 @@ -1,19 +1,20 @@ /* Disassemble D30V instructions. - Copyright 1997, 1998, 2000, 2001 Free Software Foundation, Inc. + Copyright 1997, 1998, 2000, 2001, 2005 Free Software Foundation, Inc. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include #include "sysdep.h" @@ -23,100 +24,12 @@ Foundation, Inc., 51 Franklin Street - F #define PC_MASK 0xFFFFFFFF -static int lookup_opcode PARAMS ((struct d30v_insn *insn, long num, int is_long)); -static void print_insn PARAMS ((struct disassemble_info *info, bfd_vma memaddr, long long num, - struct d30v_insn *insn, int is_long, int show_ext)); -static int extract_value PARAMS ((long long num, struct d30v_operand *oper, int is_long)); - -int -print_insn_d30v (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - int status, result; - bfd_byte buffer[12]; - unsigned long in1, in2; - struct d30v_insn insn; - long long num; - - insn.form = (struct d30v_format *) NULL; - - info->bytes_per_line = 8; - info->bytes_per_chunk = 4; - info->display_endian = BFD_ENDIAN_BIG; - - status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - in1 = bfd_getb32 (buffer); - - status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info); - if (status != 0) - { - info->bytes_per_line = 8; - if (!(result = lookup_opcode (&insn, in1, 0))) - (*info->fprintf_func) (info->stream, ".long\t0x%x", in1); - else - print_insn (info, memaddr, (long long) in1, &insn, 0, result); - return 4; - } - in2 = bfd_getb32 (buffer); - - if (in1 & in2 & FM01) - { - /* LONG instruction. */ - if (!(result = lookup_opcode (&insn, in1, 1))) - { - (*info->fprintf_func) (info->stream, ".long\t0x%x,0x%x", in1, in2); - return 8; - } - num = (long long) in1 << 32 | in2; - print_insn (info, memaddr, num, &insn, 1, result); - } - else - { - num = in1; - if (!(result = lookup_opcode (&insn, in1, 0))) - (*info->fprintf_func) (info->stream, ".long\t0x%x", in1); - else - print_insn (info, memaddr, num, &insn, 0, result); - - switch (((in1 >> 31) << 1) | (in2 >> 31)) - { - case 0: - (*info->fprintf_func) (info->stream, "\t||\t"); - break; - case 1: - (*info->fprintf_func) (info->stream, "\t->\t"); - break; - case 2: - (*info->fprintf_func) (info->stream, "\t<-\t"); - default: - break; - } - - insn.form = (struct d30v_format *) NULL; - num = in2; - if (!(result = lookup_opcode (&insn, in2, 0))) - (*info->fprintf_func) (info->stream, ".long\t0x%x", in2); - else - print_insn (info, memaddr, num, &insn, 0, result); - } - return 8; -} - /* Return 0 if lookup fails, 1 if found and only one form, 2 if found and there are short and long forms. */ static int -lookup_opcode (insn, num, is_long) - struct d30v_insn *insn; - long num; - int is_long; +lookup_opcode (struct d30v_insn *insn, long num, int is_long) { int i = 0, index; struct d30v_format *f; @@ -173,14 +86,39 @@ lookup_opcode (insn, num, is_long) return 1; } +static int +extract_value (long long num, struct d30v_operand *oper, int is_long) +{ + int val; + int shift = 12 - oper->position; + int mask = (0xFFFFFFFF >> (32 - oper->bits)); + + if (is_long) + { + if (oper->bits == 32) + /* Piece together 32-bit constant. */ + val = ((num & 0x3FFFF) + | ((num & 0xFF00000) >> 2) + | ((num & 0x3F00000000LL) >> 6)); + else + val = (num >> (32 + shift)) & mask; + } + else + val = (num >> shift) & mask; + + if (oper->flags & OPERAND_SHIFT) + val <<= 3; + + return val; +} + static void -print_insn (info, memaddr, num, insn, is_long, show_ext) - struct disassemble_info *info; - bfd_vma memaddr; - long long num; - struct d30v_insn *insn; - int is_long; - int show_ext; +print_insn (struct disassemble_info *info, + bfd_vma memaddr, + long long num, + struct d30v_insn *insn, + int is_long, + int show_ext) { int val, opnum, need_comma = 0; struct d30v_operand *oper; @@ -216,6 +154,7 @@ print_insn (info, memaddr, num, insn, is while ((opnum = insn->form->operands[opind++]) != 0) { int bits; + oper = (struct d30v_operand *) &d30v_operand_table[opnum]; bits = oper->bits; if (oper->flags & OPERAND_SHIFT) @@ -269,6 +208,7 @@ print_insn (info, memaddr, num, insn, is struct d30v_operand *oper3 = (struct d30v_operand *) &d30v_operand_table[insn->form->operands[2]]; int id = extract_value (num, oper3, is_long); + found_control = 1; switch (id) { @@ -357,6 +297,7 @@ print_insn (info, memaddr, num, insn, is if (oper->flags & OPERAND_SIGNED) { int max = (1 << (bits - 1)); + if (val & max) { val = -val; @@ -375,33 +316,80 @@ print_insn (info, memaddr, num, insn, is (*info->fprintf_func) (info->stream, ")"); } -static int -extract_value (num, oper, is_long) - long long num; - struct d30v_operand *oper; - int is_long; +int +print_insn_d30v (bfd_vma memaddr, struct disassemble_info *info) { - int val; - int shift = 12 - oper->position; - int mask = (0xFFFFFFFF >> (32 - oper->bits)); + int status, result; + bfd_byte buffer[12]; + unsigned long in1, in2; + struct d30v_insn insn; + long long num; - if (is_long) + insn.form = NULL; + + info->bytes_per_line = 8; + info->bytes_per_chunk = 4; + info->display_endian = BFD_ENDIAN_BIG; + + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) { - if (oper->bits == 32) + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + in1 = bfd_getb32 (buffer); + + status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info); + if (status != 0) + { + info->bytes_per_line = 8; + if (!(result = lookup_opcode (&insn, in1, 0))) + (*info->fprintf_func) (info->stream, ".long\t0x%lx", in1); + else + print_insn (info, memaddr, (long long) in1, &insn, 0, result); + return 4; + } + in2 = bfd_getb32 (buffer); + + if (in1 & in2 & FM01) + { + /* LONG instruction. */ + if (!(result = lookup_opcode (&insn, in1, 1))) { - /* Piece together 32-bit constant. */ - val = ((num & 0x3FFFF) - | ((num & 0xFF00000) >> 2) - | ((num & 0x3F00000000LL) >> 6)); + (*info->fprintf_func) (info->stream, ".long\t0x%lx,0x%lx", in1, in2); + return 8; } - else - val = (num >> (32 + shift)) & mask; + num = (long long) in1 << 32 | in2; + print_insn (info, memaddr, num, &insn, 1, result); } else - val = (num >> shift) & mask; + { + num = in1; + if (!(result = lookup_opcode (&insn, in1, 0))) + (*info->fprintf_func) (info->stream, ".long\t0x%lx", in1); + else + print_insn (info, memaddr, num, &insn, 0, result); - if (oper->flags & OPERAND_SHIFT) - val <<= 3; + switch (((in1 >> 31) << 1) | (in2 >> 31)) + { + case 0: + (*info->fprintf_func) (info->stream, "\t||\t"); + break; + case 1: + (*info->fprintf_func) (info->stream, "\t->\t"); + break; + case 2: + (*info->fprintf_func) (info->stream, "\t<-\t"); + default: + break; + } - return val; + insn.form = NULL; + num = in2; + if (!(result = lookup_opcode (&insn, in2, 0))) + (*info->fprintf_func) (info->stream, ".long\t0x%lx", in2); + else + print_insn (info, memaddr, num, &insn, 0, result); + } + return 8; } diff -uprN binutils-2.16.91.0.1/opcodes/d30v-opc.c binutils-2.16.91.0.2/opcodes/d30v-opc.c --- binutils-2.16.91.0.1/opcodes/d30v-opc.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/d30v-opc.c 2005-07-20 12:27:28.592978710 -0700 @@ -1,125 +1,126 @@ /* d30v-opc.c -- D30V opcode list - Copyright 1997, 1998, 1999, 2000 Free Software Foundation, Inc. + Copyright 1997, 1998, 1999, 2000, 2005 Free Software Foundation, Inc. Written by Martin Hunt, Cygnus Support -This file is part of GDB, GAS, and the GNU binutils. + This file is part of GDB, GAS, and the GNU binutils. -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -2, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include #include "sysdep.h" #include "opcode/d30v.h" -/* This table is sorted. */ -/* If you add anything, it MUST be in alphabetical order */ -/* The first field is the name the assembler uses when looking */ -/* up orcodes. The second field is the name the disassembler will use. */ -/* This allows the assembler to assemble references to r63 (for example) */ -/* or "sp". The disassembler will always use the preferred form (sp) */ +/* This table is sorted. + If you add anything, it MUST be in alphabetical order. + The first field is the name the assembler uses when looking + up orcodes. The second field is the name the disassembler will use. + This allows the assembler to assemble references to r63 (for example) + or "sp". The disassembler will always use the preferred form (sp). */ const struct pd_reg pre_defined_registers[] = { - { "a0", NULL, OPERAND_ACC+0 }, - { "a1", NULL, OPERAND_ACC+1 }, - { "bpc", NULL, OPERAND_CONTROL+3 }, - { "bpsw", NULL, OPERAND_CONTROL+1 }, - { "c", "c", OPERAND_FLAG+7 }, + { "a0", NULL, OPERAND_ACC + 0 }, + { "a1", NULL, OPERAND_ACC + 1 }, + { "bpc", NULL, OPERAND_CONTROL + 3 }, + { "bpsw", NULL, OPERAND_CONTROL + 1 }, + { "c", "c", OPERAND_FLAG + 7 }, { "cr0", "psw", OPERAND_CONTROL }, - { "cr1", "bpsw", OPERAND_CONTROL+1 }, - { "cr10", "mod_s", OPERAND_CONTROL+10 }, - { "cr11", "mod_e", OPERAND_CONTROL+11 }, - { "cr12", NULL, OPERAND_CONTROL+12 }, - { "cr13", NULL, OPERAND_CONTROL+13 }, - { "cr14", "iba", OPERAND_CONTROL+14 }, - { "cr15", "eit_vb", OPERAND_CONTROL+15 }, - { "cr16", "int_s", OPERAND_CONTROL+16 }, - { "cr17", "int_m", OPERAND_CONTROL+17 }, - { "cr18", NULL, OPERAND_CONTROL+18 }, - { "cr19", NULL, OPERAND_CONTROL+19 }, - { "cr2", "pc", OPERAND_CONTROL+2 }, - { "cr20", NULL, OPERAND_CONTROL+20 }, - { "cr21", NULL, OPERAND_CONTROL+21 }, - { "cr22", NULL, OPERAND_CONTROL+22 }, - { "cr23", NULL, OPERAND_CONTROL+23 }, - { "cr24", NULL, OPERAND_CONTROL+24 }, - { "cr25", NULL, OPERAND_CONTROL+25 }, - { "cr26", NULL, OPERAND_CONTROL+26 }, - { "cr27", NULL, OPERAND_CONTROL+27 }, - { "cr28", NULL, OPERAND_CONTROL+28 }, - { "cr29", NULL, OPERAND_CONTROL+29 }, - { "cr3", "bpc", OPERAND_CONTROL+3 }, - { "cr30", NULL, OPERAND_CONTROL+30 }, - { "cr31", NULL, OPERAND_CONTROL+31 }, - { "cr32", NULL, OPERAND_CONTROL+32 }, - { "cr33", NULL, OPERAND_CONTROL+33 }, - { "cr34", NULL, OPERAND_CONTROL+34 }, - { "cr35", NULL, OPERAND_CONTROL+35 }, - { "cr36", NULL, OPERAND_CONTROL+36 }, - { "cr37", NULL, OPERAND_CONTROL+37 }, - { "cr38", NULL, OPERAND_CONTROL+38 }, - { "cr39", NULL, OPERAND_CONTROL+39 }, - { "cr4", "dpsw", OPERAND_CONTROL+4 }, - { "cr40", NULL, OPERAND_CONTROL+40 }, - { "cr41", NULL, OPERAND_CONTROL+41 }, - { "cr42", NULL, OPERAND_CONTROL+42 }, - { "cr43", NULL, OPERAND_CONTROL+43 }, - { "cr44", NULL, OPERAND_CONTROL+44 }, - { "cr45", NULL, OPERAND_CONTROL+45 }, - { "cr46", NULL, OPERAND_CONTROL+46 }, - { "cr47", NULL, OPERAND_CONTROL+47 }, - { "cr48", NULL, OPERAND_CONTROL+48 }, - { "cr49", NULL, OPERAND_CONTROL+49 }, - { "cr5","dpc", OPERAND_CONTROL+5 }, - { "cr50", NULL, OPERAND_CONTROL+50 }, - { "cr51", NULL, OPERAND_CONTROL+51 }, - { "cr52", NULL, OPERAND_CONTROL+52 }, - { "cr53", NULL, OPERAND_CONTROL+53 }, - { "cr54", NULL, OPERAND_CONTROL+54 }, - { "cr55", NULL, OPERAND_CONTROL+55 }, - { "cr56", NULL, OPERAND_CONTROL+56 }, - { "cr57", NULL, OPERAND_CONTROL+57 }, - { "cr58", NULL, OPERAND_CONTROL+58 }, - { "cr59", NULL, OPERAND_CONTROL+59 }, - { "cr6", NULL, OPERAND_CONTROL+6 }, - { "cr60", NULL, OPERAND_CONTROL+60 }, - { "cr61", NULL, OPERAND_CONTROL+61 }, - { "cr62", NULL, OPERAND_CONTROL+62 }, - { "cr63", NULL, OPERAND_CONTROL+63 }, - { "cr7", "rpt_c", OPERAND_CONTROL+7 }, - { "cr8", "rpt_s", OPERAND_CONTROL+8 }, - { "cr9", "rpt_e", OPERAND_CONTROL+9 }, - { "dpc", NULL, OPERAND_CONTROL+5 }, - { "dpsw", NULL, OPERAND_CONTROL+4 }, - { "eit_vb", NULL, OPERAND_CONTROL+15 }, - { "f0", NULL, OPERAND_FLAG+0 }, - { "f1", NULL, OPERAND_FLAG+1 }, - { "f2", NULL, OPERAND_FLAG+2 }, - { "f3", NULL, OPERAND_FLAG+3 }, - { "f4", "s", OPERAND_FLAG+4 }, - { "f5", "v", OPERAND_FLAG+5 }, - { "f6", "va", OPERAND_FLAG+6 }, - { "f7", "c", OPERAND_FLAG+7 }, - { "iba", NULL, OPERAND_CONTROL+14 }, - { "int_m", NULL, OPERAND_CONTROL+17 }, - { "int_s", NULL, OPERAND_CONTROL+16 }, + { "cr1", "bpsw", OPERAND_CONTROL + 1 }, + { "cr10", "mod_s", OPERAND_CONTROL + 10 }, + { "cr11", "mod_e", OPERAND_CONTROL + 11 }, + { "cr12", NULL, OPERAND_CONTROL + 12 }, + { "cr13", NULL, OPERAND_CONTROL + 13 }, + { "cr14", "iba", OPERAND_CONTROL + 14 }, + { "cr15", "eit_vb", OPERAND_CONTROL + 15 }, + { "cr16", "int_s", OPERAND_CONTROL + 16 }, + { "cr17", "int_m", OPERAND_CONTROL + 17 }, + { "cr18", NULL, OPERAND_CONTROL + 18 }, + { "cr19", NULL, OPERAND_CONTROL + 19 }, + { "cr2", "pc", OPERAND_CONTROL + 2 }, + { "cr20", NULL, OPERAND_CONTROL + 20 }, + { "cr21", NULL, OPERAND_CONTROL + 21 }, + { "cr22", NULL, OPERAND_CONTROL + 22 }, + { "cr23", NULL, OPERAND_CONTROL + 23 }, + { "cr24", NULL, OPERAND_CONTROL + 24 }, + { "cr25", NULL, OPERAND_CONTROL + 25 }, + { "cr26", NULL, OPERAND_CONTROL + 26 }, + { "cr27", NULL, OPERAND_CONTROL + 27 }, + { "cr28", NULL, OPERAND_CONTROL + 28 }, + { "cr29", NULL, OPERAND_CONTROL + 29 }, + { "cr3", "bpc", OPERAND_CONTROL + 3 }, + { "cr30", NULL, OPERAND_CONTROL + 30 }, + { "cr31", NULL, OPERAND_CONTROL + 31 }, + { "cr32", NULL, OPERAND_CONTROL + 32 }, + { "cr33", NULL, OPERAND_CONTROL + 33 }, + { "cr34", NULL, OPERAND_CONTROL + 34 }, + { "cr35", NULL, OPERAND_CONTROL + 35 }, + { "cr36", NULL, OPERAND_CONTROL + 36 }, + { "cr37", NULL, OPERAND_CONTROL + 37 }, + { "cr38", NULL, OPERAND_CONTROL + 38 }, + { "cr39", NULL, OPERAND_CONTROL + 39 }, + { "cr4", "dpsw", OPERAND_CONTROL + 4 }, + { "cr40", NULL, OPERAND_CONTROL + 40 }, + { "cr41", NULL, OPERAND_CONTROL + 41 }, + { "cr42", NULL, OPERAND_CONTROL + 42 }, + { "cr43", NULL, OPERAND_CONTROL + 43 }, + { "cr44", NULL, OPERAND_CONTROL + 44 }, + { "cr45", NULL, OPERAND_CONTROL + 45 }, + { "cr46", NULL, OPERAND_CONTROL + 46 }, + { "cr47", NULL, OPERAND_CONTROL + 47 }, + { "cr48", NULL, OPERAND_CONTROL + 48 }, + { "cr49", NULL, OPERAND_CONTROL + 49 }, + { "cr5","dpc", OPERAND_CONTROL + 5 }, + { "cr50", NULL, OPERAND_CONTROL + 50 }, + { "cr51", NULL, OPERAND_CONTROL + 51 }, + { "cr52", NULL, OPERAND_CONTROL + 52 }, + { "cr53", NULL, OPERAND_CONTROL + 53 }, + { "cr54", NULL, OPERAND_CONTROL + 54 }, + { "cr55", NULL, OPERAND_CONTROL + 55 }, + { "cr56", NULL, OPERAND_CONTROL + 56 }, + { "cr57", NULL, OPERAND_CONTROL + 57 }, + { "cr58", NULL, OPERAND_CONTROL + 58 }, + { "cr59", NULL, OPERAND_CONTROL + 59 }, + { "cr6", NULL, OPERAND_CONTROL + 6 }, + { "cr60", NULL, OPERAND_CONTROL + 60 }, + { "cr61", NULL, OPERAND_CONTROL + 61 }, + { "cr62", NULL, OPERAND_CONTROL + 62 }, + { "cr63", NULL, OPERAND_CONTROL + 63 }, + { "cr7", "rpt_c", OPERAND_CONTROL + 7 }, + { "cr8", "rpt_s", OPERAND_CONTROL + 8 }, + { "cr9", "rpt_e", OPERAND_CONTROL + 9 }, + { "dpc", NULL, OPERAND_CONTROL + 5 }, + { "dpsw", NULL, OPERAND_CONTROL + 4 }, + { "eit_vb", NULL, OPERAND_CONTROL + 15 }, + { "f0", NULL, OPERAND_FLAG + 0 }, + { "f1", NULL, OPERAND_FLAG + 1 }, + { "f2", NULL, OPERAND_FLAG + 2 }, + { "f3", NULL, OPERAND_FLAG + 3 }, + { "f4", "s", OPERAND_FLAG + 4 }, + { "f5", "v", OPERAND_FLAG + 5 }, + { "f6", "va", OPERAND_FLAG + 6 }, + { "f7", "c", OPERAND_FLAG + 7 }, + { "iba", NULL, OPERAND_CONTROL + 14 }, + { "int_m", NULL, OPERAND_CONTROL + 17 }, + { "int_s", NULL, OPERAND_CONTROL + 16 }, { "link", "r62", 62 }, - { "mod_e", NULL, OPERAND_CONTROL+11 }, - { "mod_s", NULL, OPERAND_CONTROL+10 }, - { "pc", NULL, OPERAND_CONTROL+2 }, + { "mod_e", NULL, OPERAND_CONTROL + 11 }, + { "mod_s", NULL, OPERAND_CONTROL + 10 }, + { "pc", NULL, OPERAND_CONTROL + 2 }, { "psw", NULL, OPERAND_CONTROL }, - { "pswh", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+2 }, - { "pswl", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+1 }, + { "pswh", NULL, OPERAND_CONTROL + MAX_CONTROL_REG + 2 }, + { "pswl", NULL, OPERAND_CONTROL + MAX_CONTROL_REG + 1 }, { "r0", NULL, 0 }, { "r1", NULL, 1 }, { "r10", NULL, 10 }, @@ -184,24 +185,26 @@ const struct pd_reg pre_defined_register { "r7", NULL, 7 }, { "r8", NULL, 8 }, { "r9", NULL, 9 }, - { "rpt_c", NULL, OPERAND_CONTROL+7 }, - { "rpt_e", NULL, OPERAND_CONTROL+9 }, - { "rpt_s", NULL, OPERAND_CONTROL+8 }, - { "s", NULL, OPERAND_FLAG+4 }, + { "rpt_c", NULL, OPERAND_CONTROL + 7 }, + { "rpt_e", NULL, OPERAND_CONTROL + 9 }, + { "rpt_s", NULL, OPERAND_CONTROL + 8 }, + { "s", NULL, OPERAND_FLAG + 4 }, { "sp", NULL, 63 }, - { "v", NULL, OPERAND_FLAG+5 }, - { "va", NULL, OPERAND_FLAG+6 }, + { "v", NULL, OPERAND_FLAG + 5 }, + { "va", NULL, OPERAND_FLAG + 6 }, }; int -reg_name_cnt() +reg_name_cnt (void) { - return (sizeof(pre_defined_registers) / sizeof(struct pd_reg)); + return sizeof (pre_defined_registers) / sizeof (struct pd_reg); } -/* OPCODE TABLE */ -/* The format of this table is defined in opcode/d30v.h */ -const struct d30v_opcode d30v_opcode_table[] = { +/* OPCODE TABLE. + The format of this table is defined in opcode/d30v.h. */ + +const struct d30v_opcode d30v_opcode_table[] = +{ { "abs", IALU1, 0x8, { SHORT_U }, EITHER, 0, 0, 0 }, { "add", IALU1, 0x0, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, { "add2h", IALU1, 0x1, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, @@ -335,52 +338,53 @@ const struct d30v_opcode d30v_opcode_tab }; -/* now define the operand types */ -/* format is length, bits, position, flags */ +/* Now define the operand types. + Format is length, bits, position, flags. */ + const struct d30v_operand d30v_operand_table[] = { #define UNUSED (0) { 0, 0, 0, 0 }, #define Ra (UNUSED + 1) - { 6, 6, 0, OPERAND_REG|OPERAND_DEST }, + { 6, 6, 0, OPERAND_REG | OPERAND_DEST }, #define Ra2 (Ra + 1) - { 6, 6, 0, OPERAND_REG|OPERAND_DEST|OPERAND_2REG }, + { 6, 6, 0, OPERAND_REG | OPERAND_DEST | OPERAND_2REG }, #define Ra3 (Ra2 + 1) { 6, 6, 0, OPERAND_REG }, #define Rb (Ra3 + 1) { 6, 6, 6, OPERAND_REG }, #define Rb2 (Rb + 1) - { 6, 6, 6, OPERAND_REG|OPERAND_DEST }, + { 6, 6, 6, OPERAND_REG | OPERAND_DEST }, #define Rc (Rb2 + 1) { 6, 6, 12, OPERAND_REG }, #define Aa (Rc + 1) - { 6, 1, 0, OPERAND_ACC|OPERAND_REG|OPERAND_DEST }, + { 6, 1, 0, OPERAND_ACC | OPERAND_REG | OPERAND_DEST }, #define Ab (Aa + 1) - { 6, 1, 6, OPERAND_ACC|OPERAND_REG }, + { 6, 1, 6, OPERAND_ACC | OPERAND_REG }, #define IMM5 (Ab + 1) { 6, 5, 12, OPERAND_NUM }, #define IMM5U (IMM5 + 1) - { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, /* not used */ + { 6, 5, 12, OPERAND_NUM | OPERAND_SIGNED }, /* Not used. */ #define IMM5S3 (IMM5U + 1) - { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, /* not used */ + { 6, 5, 12, OPERAND_NUM | OPERAND_SIGNED }, /* Not used. */ #define IMM6 (IMM5S3 + 1) - { 6, 6, 12, OPERAND_NUM|OPERAND_SIGNED }, + { 6, 6, 12, OPERAND_NUM | OPERAND_SIGNED }, #define IMM6U (IMM6 + 1) { 6, 6, 0, OPERAND_NUM }, #define IMM6U2 (IMM6U + 1) { 6, 6, 12, OPERAND_NUM }, #define REL6S3 (IMM6U2 + 1) - { 6, 6, 0, OPERAND_NUM|OPERAND_SHIFT|OPERAND_PCREL }, + { 6, 6, 0, OPERAND_NUM | OPERAND_SHIFT | OPERAND_PCREL }, #define REL12S3 (REL6S3 + 1) - { 12, 12, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT|OPERAND_PCREL }, + { 12, 12, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT | OPERAND_PCREL }, #define IMM12S3 (REL12S3 + 1) - { 12, 12, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT }, + { 12, 12, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT }, #define REL18S3 (IMM12S3 + 1) - { 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT|OPERAND_PCREL }, + { 18, 18, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT | OPERAND_PCREL }, #define IMM18S3 (REL18S3 + 1) - { 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT }, + { 18, 18, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT }, #define REL32 (IMM18S3 + 1) - { 32, 32, 0, OPERAND_NUM|OPERAND_PCREL }, + { 32, 32, 0, OPERAND_NUM | OPERAND_PCREL }, #define IMM32 (REL32 + 1) { 32, 32, 0, OPERAND_NUM }, #define Fa (IMM32 + 1) @@ -393,25 +397,26 @@ const struct d30v_operand d30v_operand_t { 0, 0, 0, OPERAND_ATSIGN}, #define ATPAR (ATSIGN + 1) /* "@(" */ { 0, 0, 0, OPERAND_ATPAR}, -#define PLUS (ATPAR + 1) /* postincrement */ +#define PLUS (ATPAR + 1) /* Postincrement. */ { 0, 0, 0, OPERAND_PLUS}, -#define MINUS (PLUS + 1) /* postdecrement */ +#define MINUS (PLUS + 1) /* Postdecrement. */ { 0, 0, 0, OPERAND_MINUS}, -#define ATMINUS (MINUS + 1) /* predecrement */ +#define ATMINUS (MINUS + 1) /* Predecrement. */ { 0, 0, 0, OPERAND_ATMINUS}, -#define Ca (ATMINUS + 1) /* control register */ - { 6, 6, 0, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST}, -#define Cb (Ca + 1) /* control register */ - { 6, 6, 6, OPERAND_REG|OPERAND_CONTROL}, -#define CC (Cb + 1) /* condition code (CMPcc and CMPUcc) */ +#define Ca (ATMINUS + 1) /* Control register. */ + { 6, 6, 0, OPERAND_REG | OPERAND_CONTROL | OPERAND_DEST}, +#define Cb (Ca + 1) /* Control register. */ + { 6, 6, 6, OPERAND_REG | OPERAND_CONTROL}, +#define CC (Cb + 1) /* Condition code (CMPcc and CMPUcc). */ { 3, 3, -3, OPERAND_NAME}, -#define Fa2 (CC + 1) /* flag register (CMPcc and CMPUcc) */ - { 3, 3, 0, OPERAND_REG|OPERAND_FLAG|OPERAND_DEST}, -#define Fake (Fa2 + 1) /* place holder for "id" field in mvfsys and mvtsys */ +#define Fa2 (CC + 1) /* Flag register (CMPcc and CMPUcc). */ + { 3, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST}, +#define Fake (Fa2 + 1) /* Place holder for "id" field in mvfsys and mvtsys. */ { 6, 2, 12, OPERAND_SPECIAL}, }; -/* now we need to define the instruction formats */ +/* Now we need to define the instruction formats. */ + const struct d30v_format d30v_format_table[] = { { 0, 0, { 0 } }, diff -uprN binutils-2.16.91.0.1/opcodes/disassemble.c binutils-2.16.91.0.2/opcodes/disassemble.c --- binutils-2.16.91.0.1/opcodes/disassemble.c 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/disassemble.c 2005-07-20 12:27:28.594978380 -0700 @@ -30,6 +30,8 @@ #define ARCH_d10v #define ARCH_d30v #define ARCH_dlx +#define ARCH_fr30 +#define ARCH_frv #define ARCH_h8300 #define ARCH_h8500 #define ARCH_hppa @@ -37,13 +39,14 @@ #define ARCH_i386 #define ARCH_i860 #define ARCH_i960 -#define ARCH_ip2k #define ARCH_ia64 -#define ARCH_fr30 +#define ARCH_ip2k +#define ARCH_iq2000 +#define ARCH_m32c #define ARCH_m32r -#define ARCH_m68k #define ARCH_m68hc11 #define ARCH_m68hc12 +#define ARCH_m68k #define ARCH_m88k #define ARCH_maxq #define ARCH_mcore @@ -73,11 +76,12 @@ #define ARCH_xstormy16 #define ARCH_xtensa #define ARCH_z8k -#define ARCH_frv -#define ARCH_iq2000 #define INCLUDE_SHMEDIA #endif +#ifdef ARCH_m32c +#include "m32c-desc.h" +#endif disassembler_ftype disassembler (abfd) @@ -394,6 +398,11 @@ disassembler (abfd) disassemble = print_insn_iq2000; break; #endif +#ifdef ARCH_m32c + case bfd_arch_m32c: + disassemble = print_insn_m32c; + break; +#endif default: return 0; } @@ -439,6 +448,15 @@ disassemble_init_for_target (struct disa case bfd_arch_tic4x: info->skip_zeroes = 32; #endif +#ifdef ARCH_m32c + case bfd_arch_m32c: + info->endian = BFD_ENDIAN_BIG; + if (info->mach == bfd_mach_m16c) + info->insn_sets = ISA_M16C; + else + info->insn_sets = ISA_M32C; + break; +#endif default: break; } diff -uprN binutils-2.16.91.0.1/opcodes/dis-buf.c binutils-2.16.91.0.2/opcodes/dis-buf.c --- binutils-2.16.91.0.1/opcodes/dis-buf.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/dis-buf.c 2005-07-20 12:27:28.593978545 -0700 @@ -2,19 +2,20 @@ Copyright 1993, 1994, 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2005 Free Software Foundation, Inc. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "sysdep.h" #include "dis-asm.h" @@ -24,11 +25,10 @@ Foundation, Inc., 51 Franklin Street - F /* Get LENGTH bytes from info's buffer, at target address memaddr. Transfer them to myaddr. */ int -buffer_read_memory (memaddr, myaddr, length, info) - bfd_vma memaddr; - bfd_byte *myaddr; - unsigned int length; - struct disassemble_info *info; +buffer_read_memory (bfd_vma memaddr, + bfd_byte *myaddr, + unsigned int length, + struct disassemble_info *info) { unsigned int opb = info->octets_per_byte; unsigned int end_addr_offset = length / opb; @@ -46,11 +46,11 @@ buffer_read_memory (memaddr, myaddr, len /* Print an error message. We can assume that this is in response to an error return from buffer_read_memory. */ + void -perror_memory (status, memaddr, info) - int status; - bfd_vma memaddr; - struct disassemble_info *info; +perror_memory (int status, + bfd_vma memaddr, + struct disassemble_info *info) { if (status != EIO) /* Can't happen. */ @@ -75,9 +75,7 @@ perror_memory (status, memaddr, info) addresses). */ void -generic_print_address (addr, info) - bfd_vma addr; - struct disassemble_info *info; +generic_print_address (bfd_vma addr, struct disassemble_info *info) { char buf[30]; @@ -85,39 +83,11 @@ generic_print_address (addr, info) (*info->fprintf_func) (info->stream, "0x%s", buf); } -#if 0 -/* Just concatenate the address as hex. This is included for - completeness even though both GDB and objdump provide their own (to - print symbolic addresses). */ - -void generic_strcat_address PARAMS ((bfd_vma, char *, int)); - -void -generic_strcat_address (addr, buf, len) - bfd_vma addr; - char *buf; - int len; -{ - if (buf != (char *)NULL && len > 0) - { - char tmpBuf[30]; - - sprintf_vma (tmpBuf, addr); - if ((strlen (buf) + strlen (tmpBuf)) <= (unsigned int) len) - strcat (buf, tmpBuf); - else - strncat (buf, tmpBuf, (len - strlen(buf))); - } - return; -} -#endif - /* Just return true. */ int -generic_symbol_at_address (addr, info) - bfd_vma addr ATTRIBUTE_UNUSED; - struct disassemble_info *info ATTRIBUTE_UNUSED; +generic_symbol_at_address (bfd_vma addr ATTRIBUTE_UNUSED, + struct disassemble_info *info ATTRIBUTE_UNUSED) { return 1; } diff -uprN binutils-2.16.91.0.1/opcodes/dlx-dis.c binutils-2.16.91.0.2/opcodes/dlx-dis.c --- binutils-2.16.91.0.1/opcodes/dlx-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/dlx-dis.c 2005-07-20 12:27:28.611975577 -0700 @@ -1,5 +1,5 @@ /* Instruction printing code for the DLX Microprocessor - Copyright 2002 Free Software Foundation, Inc. + Copyright 2002, 2005 Free Software Foundation, Inc. Contributed by Kuang Hwa Lin. Written by Kuang Hwa Lin, 03/2002. This program is free software; you can redistribute it and/or modify @@ -14,7 +14,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "sysdep.h" #include "dis-asm.h" @@ -36,79 +37,55 @@ unsigned char opc, rs1, rs2, rd; unsigned long imm26, imm16, func, current_insn_addr; -static unsigned char dlx_get_opcode PARAMS ((unsigned long)); -static unsigned char dlx_get_rs1 PARAMS ((unsigned long)); -static unsigned char dlx_get_rs2 PARAMS ((unsigned long)); -static unsigned char dlx_get_rdR PARAMS ((unsigned long)); -static unsigned long dlx_get_func PARAMS ((unsigned long)); -static unsigned long dlx_get_imm16 PARAMS ((unsigned long)); -static unsigned long dlx_get_imm26 PARAMS ((unsigned long)); -static void operand_deliminator PARAMS ((struct disassemble_info *, char *)); -static unsigned char dlx_r_type PARAMS ((struct disassemble_info *)); -static unsigned char dlx_load_type PARAMS ((struct disassemble_info *)); -static unsigned char dlx_store_type PARAMS ((struct disassemble_info *)); -static unsigned char dlx_aluI_type PARAMS ((struct disassemble_info *)); -static unsigned char dlx_br_type PARAMS ((struct disassemble_info *)); -static unsigned char dlx_jmp_type PARAMS ((struct disassemble_info *)); -static unsigned char dlx_jr_type PARAMS ((struct disassemble_info *)); - /* Print one instruction from MEMADDR on INFO->STREAM. Return the size of the instruction (always 4 on dlx). */ static unsigned char -dlx_get_opcode (opcode) - unsigned long opcode; +dlx_get_opcode (unsigned long opcode) { return (unsigned char) ((opcode >> 26) & 0x3F); } static unsigned char -dlx_get_rs1 (opcode) - unsigned long opcode; +dlx_get_rs1 (unsigned long opcode) { return (unsigned char) ((opcode >> 21) & 0x1F); } static unsigned char -dlx_get_rs2 (opcode) - unsigned long opcode; +dlx_get_rs2 (unsigned long opcode) { return (unsigned char) ((opcode >> 16) & 0x1F); } static unsigned char -dlx_get_rdR (opcode) - unsigned long opcode; +dlx_get_rdR (unsigned long opcode) { return (unsigned char) ((opcode >> 11) & 0x1F); } static unsigned long -dlx_get_func (opcode) - unsigned long opcode; +dlx_get_func (unsigned long opcode) { return (unsigned char) (opcode & 0x7FF); } static unsigned long -dlx_get_imm16 (opcode) - unsigned long opcode; +dlx_get_imm16 (unsigned long opcode) { return (unsigned long) (opcode & 0xFFFF); } static unsigned long -dlx_get_imm26 (opcode) - unsigned long opcode; +dlx_get_imm26 (unsigned long opcode) { return (unsigned long) (opcode & 0x03FFFFFF); } /* Fill the opcode to the max length. */ + static void -operand_deliminator (info, ptr) - struct disassemble_info *info; - char *ptr; +operand_deliminator (struct disassemble_info *info, char *ptr) { int difft = 8 - (int) strlen (ptr); @@ -120,9 +97,9 @@ operand_deliminator (info, ptr) } /* Process the R-type opcode. */ + static unsigned char -dlx_r_type (info) - struct disassemble_info *info; +dlx_r_type (struct disassemble_info *info) { unsigned char r_opc[] = { OPC(ALUOP) }; /* Fix ME */ int r_opc_num = (sizeof r_opc) / (sizeof (char)); @@ -132,7 +109,7 @@ dlx_r_type (info) char *name; } dlx_r_opcode[] = - { + { { NOPF, "nop" }, /* NOP */ { ADDF, "add" }, /* Add */ { ADDUF, "addu" }, /* Add Unsigned */ @@ -174,7 +151,7 @@ dlx_r_type (info) continue; else break; - } + } if (idx == r_opc_num) return NIL; @@ -202,8 +179,7 @@ dlx_r_type (info) /* Process the memory read opcode. */ static unsigned char -dlx_load_type (info) - struct disassemble_info* info; +dlx_load_type (struct disassemble_info* info) { struct _load_opcode { @@ -211,17 +187,17 @@ dlx_load_type (info) char *name; } dlx_load_opcode[] = - { - { OPC(LHIOP), "lhi" }, /* Load HI to register. */ - { OPC(LBOP), "lb" }, /* load byte sign extended. */ - { OPC(LBUOP), "lbu" }, /* load byte unsigned. */ - { OPC(LSBUOP),"ldstbu"}, /* load store byte unsigned. */ - { OPC(LHOP), "lh" }, /* load halfword sign extended. */ - { OPC(LHUOP), "lhu" }, /* load halfword unsigned. */ - { OPC(LSHUOP),"ldsthu"}, /* load store halfword unsigned. */ - { OPC(LWOP), "lw" }, /* load word. */ - { OPC(LSWOP), "ldstw" } /* load store word. */ - }; + { + { OPC(LHIOP), "lhi" }, /* Load HI to register. */ + { OPC(LBOP), "lb" }, /* load byte sign extended. */ + { OPC(LBUOP), "lbu" }, /* load byte unsigned. */ + { OPC(LSBUOP),"ldstbu"}, /* load store byte unsigned. */ + { OPC(LHOP), "lh" }, /* load halfword sign extended. */ + { OPC(LHUOP), "lhu" }, /* load halfword unsigned. */ + { OPC(LSHUOP),"ldsthu"}, /* load store halfword unsigned. */ + { OPC(LWOP), "lw" }, /* load word. */ + { OPC(LSWOP), "ldstw" } /* load store word. */ + }; int dlx_load_opcode_num = (sizeof dlx_load_opcode) / (sizeof dlx_load_opcode[0]); int idx; @@ -253,8 +229,7 @@ dlx_load_type (info) /* Process the memory store opcode. */ static unsigned char -dlx_store_type (info) - struct disassemble_info* info; +dlx_store_type (struct disassemble_info* info) { struct _store_opcode { @@ -262,11 +237,11 @@ dlx_store_type (info) char *name; } dlx_store_opcode[] = - { - { OPC(SBOP), "sb" }, /* Store byte. */ - { OPC(SHOP), "sh" }, /* Store halfword. */ - { OPC(SWOP), "sw" }, /* Store word. */ - }; + { + { OPC(SBOP), "sb" }, /* Store byte. */ + { OPC(SHOP), "sh" }, /* Store halfword. */ + { OPC(SWOP), "sw" }, /* Store word. */ + }; int dlx_store_opcode_num = (sizeof dlx_store_opcode) / (sizeof dlx_store_opcode[0]); int idx; @@ -287,8 +262,7 @@ dlx_store_type (info) /* Process the Arithmetic and Logical I-TYPE opcode. */ static unsigned char -dlx_aluI_type (info) - struct disassemble_info* info; +dlx_aluI_type (struct disassemble_info* info) { struct _aluI_opcode { @@ -296,34 +270,34 @@ dlx_aluI_type (info) char *name; } dlx_aluI_opcode[] = - { - { OPC(ADDIOP), "addi" }, /* Store byte. */ - { OPC(ADDUIOP), "addui" }, /* Store halfword. */ - { OPC(SUBIOP), "subi" }, /* Store word. */ - { OPC(SUBUIOP), "subui" }, /* Store word. */ - { OPC(ANDIOP), "andi" }, /* Store word. */ - { OPC(ORIOP), "ori" }, /* Store word. */ - { OPC(XORIOP), "xori" }, /* Store word. */ - { OPC(SLLIOP), "slli" }, /* Store word. */ - { OPC(SRAIOP), "srai" }, /* Store word. */ - { OPC(SRLIOP), "srli" }, /* Store word. */ - { OPC(SEQIOP), "seqi" }, /* Store word. */ - { OPC(SNEIOP), "snei" }, /* Store word. */ - { OPC(SLTIOP), "slti" }, /* Store word. */ - { OPC(SGTIOP), "sgti" }, /* Store word. */ - { OPC(SLEIOP), "slei" }, /* Store word. */ - { OPC(SGEIOP), "sgei" }, /* Store word. */ - { OPC(SEQUIOP), "sequi" }, /* Store word. */ - { OPC(SNEUIOP), "sneui" }, /* Store word. */ - { OPC(SLTUIOP), "sltui" }, /* Store word. */ - { OPC(SGTUIOP), "sgtui" }, /* Store word. */ - { OPC(SLEUIOP), "sleui" }, /* Store word. */ - { OPC(SGEUIOP), "sgeui" }, /* Store word. */ + { + { OPC(ADDIOP), "addi" }, /* Store byte. */ + { OPC(ADDUIOP), "addui" }, /* Store halfword. */ + { OPC(SUBIOP), "subi" }, /* Store word. */ + { OPC(SUBUIOP), "subui" }, /* Store word. */ + { OPC(ANDIOP), "andi" }, /* Store word. */ + { OPC(ORIOP), "ori" }, /* Store word. */ + { OPC(XORIOP), "xori" }, /* Store word. */ + { OPC(SLLIOP), "slli" }, /* Store word. */ + { OPC(SRAIOP), "srai" }, /* Store word. */ + { OPC(SRLIOP), "srli" }, /* Store word. */ + { OPC(SEQIOP), "seqi" }, /* Store word. */ + { OPC(SNEIOP), "snei" }, /* Store word. */ + { OPC(SLTIOP), "slti" }, /* Store word. */ + { OPC(SGTIOP), "sgti" }, /* Store word. */ + { OPC(SLEIOP), "slei" }, /* Store word. */ + { OPC(SGEIOP), "sgei" }, /* Store word. */ + { OPC(SEQUIOP), "sequi" }, /* Store word. */ + { OPC(SNEUIOP), "sneui" }, /* Store word. */ + { OPC(SLTUIOP), "sltui" }, /* Store word. */ + { OPC(SGTUIOP), "sgtui" }, /* Store word. */ + { OPC(SLEUIOP), "sleui" }, /* Store word. */ + { OPC(SGEUIOP), "sgeui" }, /* Store word. */ #if 0 - { OPC(MVTSOP), "mvts" }, /* Store word. */ - { OPC(MVFSOP), "mvfs" }, /* Store word. */ + { OPC(MVTSOP), "mvts" }, /* Store word. */ + { OPC(MVFSOP), "mvfs" }, /* Store word. */ #endif - }; + }; int dlx_aluI_opcode_num = (sizeof dlx_aluI_opcode) / (sizeof dlx_aluI_opcode[0]); int idx; @@ -346,8 +320,7 @@ dlx_aluI_type (info) /* Process the branch instruction. */ static unsigned char -dlx_br_type (info) - struct disassemble_info* info; +dlx_br_type (struct disassemble_info* info) { struct _br_opcode { @@ -355,10 +328,10 @@ dlx_br_type (info) char *name; } dlx_br_opcode[] = - { - { OPC(BEQOP), "beqz" }, /* Store byte. */ - { OPC(BNEOP), "bnez" } /* Store halfword. */ - }; + { + { OPC(BEQOP), "beqz" }, /* Store byte. */ + { OPC(BNEOP), "bnez" } /* Store halfword. */ + }; int dlx_br_opcode_num = (sizeof dlx_br_opcode) / (sizeof dlx_br_opcode[0]); int idx; @@ -372,8 +345,8 @@ dlx_br_type (info) imm16 += (current_insn_addr + 4); (*info->fprintf_func) (info->stream, "%s", dlx_br_opcode[idx].name); operand_deliminator (info, dlx_br_opcode[idx].name); - (*info->fprintf_func) (info->stream, "r%d,", (int)rs1); - (*info->fprintf_func) (info->stream, "0x%08x", (int)imm16); + (*info->fprintf_func) (info->stream, "r%d,", (int) rs1); + (*info->fprintf_func) (info->stream, "0x%08x", (int) imm16); return (unsigned char) IBR_TYPE; } @@ -384,8 +357,7 @@ dlx_br_type (info) /* Process the jump instruction. */ static unsigned char -dlx_jmp_type (info) - struct disassemble_info* info; +dlx_jmp_type (struct disassemble_info* info) { struct _jmp_opcode { @@ -393,13 +365,13 @@ dlx_jmp_type (info) char *name; } dlx_jmp_opcode[] = - { - { OPC(JOP), "j" }, /* Store byte. */ - { OPC(JALOP), "jal" }, /* Store halfword. */ - { OPC(BREAKOP), "break" }, /* Store halfword. */ - { OPC(TRAPOP), "trap" }, /* Store halfword. */ - { OPC(RFEOP), "rfe" } /* Store halfword. */ - }; + { + { OPC(JOP), "j" }, /* Store byte. */ + { OPC(JALOP), "jal" }, /* Store halfword. */ + { OPC(BREAKOP), "break" }, /* Store halfword. */ + { OPC(TRAPOP), "trap" }, /* Store halfword. */ + { OPC(RFEOP), "rfe" } /* Store halfword. */ + }; int dlx_jmp_opcode_num = (sizeof dlx_jmp_opcode) / (sizeof dlx_jmp_opcode[0]); int idx; @@ -425,15 +397,15 @@ dlx_jmp_type (info) /* Process the jump register instruction. */ static unsigned char -dlx_jr_type (info) - struct disassemble_info* info; +dlx_jr_type (struct disassemble_info* info) { struct _jr_opcode { unsigned long opcode; char *name; } - dlx_jr_opcode[] = { + dlx_jr_opcode[] = + { { OPC(JROP), "jr" }, /* Store byte. */ { OPC(JALROP), "jalr" } /* Store halfword. */ }; @@ -453,29 +425,27 @@ dlx_jr_type (info) return (unsigned char) NIL; } -typedef unsigned char (* dlx_insn) PARAMS ((struct disassemble_info *)); +typedef unsigned char (* dlx_insn) (struct disassemble_info *); /* This is the main DLX insn handling routine. */ int -print_insn_dlx (memaddr, info) - bfd_vma memaddr; - struct disassemble_info* info; +print_insn_dlx (bfd_vma memaddr, struct disassemble_info* info) { bfd_byte buffer[4]; int insn_idx; unsigned long insn_word; unsigned char rtn_code; unsigned long dlx_insn_type[] = - { - (unsigned long) dlx_r_type, - (unsigned long) dlx_load_type, - (unsigned long) dlx_store_type, - (unsigned long) dlx_aluI_type, - (unsigned long) dlx_br_type, - (unsigned long) dlx_jmp_type, - (unsigned long) dlx_jr_type, - (unsigned long) NULL + { + (unsigned long) dlx_r_type, + (unsigned long) dlx_load_type, + (unsigned long) dlx_store_type, + (unsigned long) dlx_aluI_type, + (unsigned long) dlx_br_type, + (unsigned long) dlx_jmp_type, + (unsigned long) dlx_jr_type, + (unsigned long) NULL }; int dlx_insn_type_num = ((sizeof dlx_insn_type) / (sizeof (unsigned long))) - 1; int status = diff -uprN binutils-2.16.91.0.1/opcodes/fr30-asm.c binutils-2.16.91.0.2/opcodes/fr30-asm.c --- binutils-2.16.91.0.1/opcodes/fr30-asm.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/fr30-asm.c 2005-07-20 12:27:28.612975412 -0700 @@ -1,26 +1,27 @@ /* Assembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-asm.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -50,26 +51,13 @@ static const char * parse_insn_normal /* -- asm.c */ /* Handle register lists for LDMx and STMx. */ -static int parse_register_number - PARAMS ((const char **)); -static const char * parse_register_list - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *, int, int)); -static const char * parse_low_register_list_ld - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_hi_register_list_ld - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_low_register_list_st - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_hi_register_list_st - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); - static int -parse_register_number (strp) - const char **strp; +parse_register_number (const char **strp) { int regno; + if (**strp < '0' || **strp > '9') - return -1; /* error. */ + return -1; /* Error. */ regno = **strp - '0'; ++*strp; @@ -83,30 +71,29 @@ parse_register_number (strp) } static const char * -parse_register_list (cd, strp, opindex, valuep, high_low, load_store) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - const char **strp; - int opindex ATTRIBUTE_UNUSED; - unsigned long *valuep; - int high_low; /* 0 == high, 1 == low */ - int load_store; /* 0 == load, 1 == store */ +parse_register_list (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + unsigned long *valuep, + int high_low, /* 0 == high, 1 == low. */ + int load_store) /* 0 == load, 1 == store. */ { - int regno; - *valuep = 0; while (**strp && **strp != ')') { + int regno; + if (**strp != 'R' && **strp != 'r') break; ++*strp; regno = parse_register_number (strp); if (regno == -1) - return "Register number is not valid"; + return _("Register number is not valid"); if (regno > 7 && !high_low) - return "Register must be between r0 and r7"; + return _("Register must be between r0 and r7"); if (regno < 8 && high_low) - return "Register must be between r8 and r15"; + return _("Register must be between r8 and r15"); if (high_low) regno -= 8; @@ -125,55 +112,55 @@ parse_register_list (cd, strp, opindex, } if (!*strp || **strp != ')') - return "Register list is not valid"; + return _("Register list is not valid"); return NULL; } static const char * -parse_low_register_list_ld (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_low_register_list_ld (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { - return parse_register_list (cd, strp, opindex, valuep, 0/*low*/, 0/*load*/); + return parse_register_list (cd, strp, opindex, valuep, + 0 /* Low. */, 0 /* Load. */); } static const char * -parse_hi_register_list_ld (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_hi_register_list_ld (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { - return parse_register_list (cd, strp, opindex, valuep, 1/*high*/, 0/*load*/); + return parse_register_list (cd, strp, opindex, valuep, + 1 /* High. */, 0 /* Load. */); } static const char * -parse_low_register_list_st (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_low_register_list_st (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { - return parse_register_list (cd, strp, opindex, valuep, 0/*low*/, 1/*store*/); + return parse_register_list (cd, strp, opindex, valuep, + 0 /* Low. */, 1 /* Store. */); } static const char * -parse_hi_register_list_st (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_hi_register_list_st (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { - return parse_register_list (cd, strp, opindex, valuep, 1/*high*/, 1/*store*/); + return parse_register_list (cd, strp, opindex, valuep, + 1 /* High. */, 1 /* Store. */); } /* -- */ const char * fr30_cgen_parse_operand - PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); /* Main entry point for operand parsing. @@ -189,11 +176,10 @@ const char * fr30_cgen_parse_operand the handlers. */ const char * -fr30_cgen_parse_operand (cd, opindex, strp, fields) - CGEN_CPU_DESC cd; - int opindex; - const char ** strp; - CGEN_FIELDS * fields; +fr30_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) { const char * errmsg = NULL; /* Used by scalar operands that still need to be parsed. */ @@ -333,8 +319,7 @@ cgen_parse_fn * const fr30_cgen_parse_ha }; void -fr30_cgen_init_asm (cd) - CGEN_CPU_DESC cd; +fr30_cgen_init_asm (CGEN_CPU_DESC cd) { fr30_cgen_init_opcode_table (cd); fr30_cgen_init_ibld_table (cd); @@ -717,30 +702,3 @@ fr30_cgen_assemble_insn (CGEN_CPU_DESC c return NULL; } } - -#if 0 /* This calls back to GAS which we can't do without care. */ - -/* Record each member of OPVALS in the assembler's symbol table. - This lets GAS parse registers for us. - ??? Interesting idea but not currently used. */ - -/* Record each member of OPVALS in the assembler's symbol table. - FIXME: Not currently used. */ - -void -fr30_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) -{ - CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); - const CGEN_KEYWORD_ENTRY * ke; - - while ((ke = cgen_keyword_search_next (& search)) != NULL) - { -#if 0 /* Unnecessary, should be done in the search routine. */ - if (! fr30_cgen_opval_supported (ke)) - continue; -#endif - cgen_asm_record_register (cd, ke->name, ke->value); - } -} - -#endif /* 0 */ diff -uprN binutils-2.16.91.0.1/opcodes/fr30-desc.c binutils-2.16.91.0.2/opcodes/fr30-desc.c --- binutils-2.16.91.0.1/opcodes/fr30-desc.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/fr30-desc.c 2005-07-20 12:27:28.629972609 -0700 @@ -1429,27 +1429,23 @@ static const CGEN_IBASE fr30_cgen_insn_t #undef A /* Initialize anything needed to be done once, before any cpu_open call. */ -static void init_tables PARAMS ((void)); static void -init_tables () +init_tables (void) { } -static const CGEN_MACH * lookup_mach_via_bfd_name - PARAMS ((const CGEN_MACH *, const char *)); -static void build_hw_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_operand_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_insn_table PARAMS ((CGEN_CPU_TABLE *)); -static void fr30_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *)); +static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); +static void build_hw_table (CGEN_CPU_TABLE *); +static void build_ifield_table (CGEN_CPU_TABLE *); +static void build_operand_table (CGEN_CPU_TABLE *); +static void build_insn_table (CGEN_CPU_TABLE *); +static void fr30_cgen_rebuild_tables (CGEN_CPU_TABLE *); /* Subroutine of fr30_cgen_cpu_open to look up a mach via its bfd name. */ static const CGEN_MACH * -lookup_mach_via_bfd_name (table, name) - const CGEN_MACH *table; - const char *name; +lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) { while (table->name) { @@ -1463,8 +1459,7 @@ lookup_mach_via_bfd_name (table, name) /* Subroutine of fr30_cgen_cpu_open to build the hardware table. */ static void -build_hw_table (cd) - CGEN_CPU_TABLE *cd; +build_hw_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; @@ -1490,8 +1485,7 @@ build_hw_table (cd) /* Subroutine of fr30_cgen_cpu_open to build the hardware table. */ static void -build_ifield_table (cd) - CGEN_CPU_TABLE *cd; +build_ifield_table (CGEN_CPU_TABLE *cd) { cd->ifld_table = & fr30_cgen_ifld_table[0]; } @@ -1499,8 +1493,7 @@ build_ifield_table (cd) /* Subroutine of fr30_cgen_cpu_open to build the hardware table. */ static void -build_operand_table (cd) - CGEN_CPU_TABLE *cd; +build_operand_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; @@ -1508,8 +1501,7 @@ build_operand_table (cd) /* MAX_OPERANDS is only an upper bound on the number of selected entries. However each entry is indexed by it's enum so there can be holes in the table. */ - const CGEN_OPERAND **selected = - (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); cd->operand_table.init_entries = init; cd->operand_table.entry_size = sizeof (CGEN_OPERAND); @@ -1532,12 +1524,11 @@ build_operand_table (cd) operand elements to be in the table [which they mightn't be]. */ static void -build_insn_table (cd) - CGEN_CPU_TABLE *cd; +build_insn_table (CGEN_CPU_TABLE *cd) { int i; const CGEN_IBASE *ib = & fr30_cgen_insn_table[0]; - CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); for (i = 0; i < MAX_INSNS; ++i) @@ -1550,8 +1541,7 @@ build_insn_table (cd) /* Subroutine of fr30_cgen_cpu_open to rebuild the tables. */ static void -fr30_cgen_rebuild_tables (cd) - CGEN_CPU_TABLE *cd; +fr30_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) { int i; unsigned int isas = cd->isas; @@ -1563,7 +1553,7 @@ fr30_cgen_rebuild_tables (cd) #define UNSET (CGEN_SIZE_UNKNOWN + 1) cd->default_insn_bitsize = UNSET; cd->base_insn_bitsize = UNSET; - cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) if (((1 << i) & isas) != 0) @@ -1575,7 +1565,7 @@ fr30_cgen_rebuild_tables (cd) if (cd->default_insn_bitsize == UNSET) cd->default_insn_bitsize = isa->default_insn_bitsize; else if (isa->default_insn_bitsize == cd->default_insn_bitsize) - ; /* this is ok */ + ; /* This is ok. */ else cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; @@ -1584,7 +1574,7 @@ fr30_cgen_rebuild_tables (cd) if (cd->base_insn_bitsize == UNSET) cd->base_insn_bitsize = isa->base_insn_bitsize; else if (isa->base_insn_bitsize == cd->base_insn_bitsize) - ; /* this is ok */ + ; /* This is ok. */ else cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; @@ -1696,12 +1686,12 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_a } va_end (ap); - /* mach unspecified means "all" */ + /* Mach unspecified means "all". */ if (machs == 0) machs = (1 << MAX_MACHS) - 1; - /* base mach is always selected */ + /* Base mach is always selected. */ machs |= 1; - /* isa unspecified means "all" */ + /* ISA unspecified means "all". */ if (isas == 0) isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) @@ -1734,9 +1724,7 @@ fr30_cgen_cpu_open (enum cgen_cpu_open_a MACH_NAME is the bfd name of the mach. */ CGEN_CPU_DESC -fr30_cgen_cpu_open_1 (mach_name, endian) - const char *mach_name; - enum cgen_endian endian; +fr30_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) { return fr30_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, CGEN_CPU_OPEN_ENDIAN, endian, @@ -1749,8 +1737,7 @@ fr30_cgen_cpu_open_1 (mach_name, endian) place as some simulator ports use this but they don't use libopcodes. */ void -fr30_cgen_cpu_close (cd) - CGEN_CPU_DESC cd; +fr30_cgen_cpu_close (CGEN_CPU_DESC cd) { unsigned int i; const CGEN_INSN *insns; @@ -1759,23 +1746,17 @@ fr30_cgen_cpu_close (cd) { insns = cd->macro_insn_table.init_entries; for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) - { - if (CGEN_INSN_RX ((insns))) - regfree (CGEN_INSN_RX (insns)); - } + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); } if (cd->insn_table.init_entries) { insns = cd->insn_table.init_entries; for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) - { - if (CGEN_INSN_RX (insns)) - regfree (CGEN_INSN_RX (insns)); - } - } - - + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } if (cd->macro_insn_table.init_entries) free ((CGEN_INSN *) cd->macro_insn_table.init_entries); diff -uprN binutils-2.16.91.0.1/opcodes/fr30-dis.c binutils-2.16.91.0.2/opcodes/fr30-dis.c --- binutils-2.16.91.0.1/opcodes/fr30-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/fr30-dis.c 2005-07-20 12:27:28.630972445 -0700 @@ -1,27 +1,27 @@ /* Disassembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-dis.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 -Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -56,33 +56,19 @@ static int read_insn (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, unsigned long *); -/* -- disassembler routines inserted here */ +/* -- disassembler routines inserted here. */ /* -- dis.c */ -static void print_register_list - PARAMS ((PTR, long, long, int)); -static void print_hi_register_list_ld - PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); -static void print_low_register_list_ld - PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); -static void print_hi_register_list_st - PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); -static void print_low_register_list_st - PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); -static void print_m4 - PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); - static void -print_register_list (dis_info, value, offset, load_store) - PTR dis_info; - long value; - long offset; - int load_store; /* 0 == load, 1 == store */ +print_register_list (void * dis_info, + long value, + long offset, + int load_store) /* 0 == load, 1 == store. */ { disassemble_info *info = dis_info; int mask; int index = 0; - char* comma = ""; + char * comma = ""; if (load_store) mask = 0x80; @@ -91,7 +77,7 @@ print_register_list (dis_info, value, of if (value & mask) { - (*info->fprintf_func) (info->stream, "r%i", index + offset); + (*info->fprintf_func) (info->stream, "r%li", index + offset); comma = ","; } @@ -104,77 +90,72 @@ print_register_list (dis_info, value, of if (value & mask) { - (*info->fprintf_func) (info->stream, "%sr%i", comma, index + offset); + (*info->fprintf_func) (info->stream, "%sr%li", comma, index + offset); comma = ","; } } } static void -print_hi_register_list_ld (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_hi_register_list_ld (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { - print_register_list (dis_info, value, 8, 0/*load*/); + print_register_list (dis_info, value, 8, 0 /* Load. */); } static void -print_low_register_list_ld (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_low_register_list_ld (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { - print_register_list (dis_info, value, 0, 0/*load*/); + print_register_list (dis_info, value, 0, 0 /* Load. */); } static void -print_hi_register_list_st (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_hi_register_list_st (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { - print_register_list (dis_info, value, 8, 1/*store*/); + print_register_list (dis_info, value, 8, 1 /* Store. */); } static void -print_low_register_list_st (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_low_register_list_st (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { - print_register_list (dis_info, value, 0, 1/*store*/); + print_register_list (dis_info, value, 0, 1 /* Store. */); } static void -print_m4 (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_m4 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; + (*info->fprintf_func) (info->stream, "%ld", value); } /* -- */ void fr30_cgen_print_operand - PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, - void const *, bfd_vma, int)); + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); /* Main entry point for printing operands. XINFO is a `void *' and not a `disassemble_info *' to not put a requirement @@ -192,16 +173,15 @@ void fr30_cgen_print_operand the handlers. */ void -fr30_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) - CGEN_CPU_DESC cd; - int opindex; - PTR xinfo; - CGEN_FIELDS *fields; - void const *attrs ATTRIBUTE_UNUSED; - bfd_vma pc; - int length; +fr30_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) { - disassemble_info *info = (disassemble_info *) xinfo; + disassemble_info *info = (disassemble_info *) xinfo; switch (opindex) { @@ -329,8 +309,7 @@ cgen_print_fn * const fr30_cgen_print_ha void -fr30_cgen_init_dis (cd) - CGEN_CPU_DESC cd; +fr30_cgen_init_dis (CGEN_CPU_DESC cd) { fr30_cgen_init_opcode_table (cd); fr30_cgen_init_ibld_table (cd); @@ -382,7 +361,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUT /* Print the operand as directed by the attributes. */ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) - ; /* nothing to do */ + ; /* Nothing to do. */ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) (*info->print_address_func) (value, info); else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) @@ -464,6 +443,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UN unsigned long *insn_value) { int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) { (*info->memory_error_func) (status, pc, info); @@ -568,13 +548,13 @@ print_insn (CGEN_CPU_DESC cd, length = CGEN_EXTRACT_FN (cd, insn) (cd, insn, &ex_info, insn_value_cropped, &fields, pc); - /* length < 0 -> error */ + /* Length < 0 -> error. */ if (length < 0) return length; if (length > 0) { CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); - /* length is in bits, result is in bytes */ + /* Length is in bits, result is in bytes. */ return length / 8; } } @@ -624,7 +604,8 @@ default_print_insn (CGEN_CPU_DESC cd, bf Print one instruction from PC on INFO->STREAM. Return the size of the instruction (in bytes). */ -typedef struct cpu_desc_list { +typedef struct cpu_desc_list +{ struct cpu_desc_list *next; int isa; int mach; @@ -709,7 +690,7 @@ print_insn_fr30 (bfd_vma pc, disassemble if (!cd) abort (); - /* save this away for future reference */ + /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; cl->isa = isa; diff -uprN binutils-2.16.91.0.1/opcodes/fr30-ibld.c binutils-2.16.91.0.2/opcodes/fr30-ibld.c --- binutils-2.16.91.0.1/opcodes/fr30-ibld.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/fr30-ibld.c 2005-07-20 12:27:28.632972115 -0700 @@ -1,25 +1,26 @@ /* Instruction building/extraction support for fr30. -*- C -*- -THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. -- the resultant file is machine generated, cgen-ibld.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -35,9 +36,9 @@ along with this program; if not, write t #include "opintl.h" #include "safe-ctype.h" -#undef min +#undef min #define min(a,b) ((a) < (b) ? (a) : (b)) -#undef max +#undef max #define max(a,b) ((a) > (b) ? (a) : (b)) /* Used by the ifield rtx function. */ @@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd, if (length == 0) return NULL; -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - if (word_length > 32) abort (); @@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd, #if CGEN_INT_INSN_P /* Cover function to store an insn value into an integral insn. Must go here - because it needs -desc.h for CGEN_INT_INSN_P. */ + because it needs -desc.h for CGEN_INT_INSN_P. */ static void put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, @@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATT int shift = insn_length - length; /* Written this way to avoid undefined behaviour. */ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); } } @@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd, { unsigned long x; int shift; -#if 0 - int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; -#endif + x = cgen_get_insn_value (cd, bufp, word_length); if (CGEN_INSN_LSB0_P) @@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd, return 1; } -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - if (word_length > 32) abort (); @@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd, return CGEN_INSN_BITSIZE (insn); } -/* machine generated code added here */ +/* Machine generated code added here. */ const char * fr30_cgen_insert_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); /* Main entry point for operand insertion. @@ -559,12 +547,11 @@ const char * fr30_cgen_insert_operand resolved during parsing. */ const char * -fr30_cgen_insert_operand (cd, opindex, fields, buffer, pc) - CGEN_CPU_DESC cd; - int opindex; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc ATTRIBUTE_UNUSED; +fr30_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) { const char * errmsg = NULL; unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); @@ -738,8 +725,7 @@ fr30_cgen_insert_operand (cd, opindex, f } int fr30_cgen_extract_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - CGEN_FIELDS *, bfd_vma)); + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); /* Main entry point for operand extraction. The result is <= 0 for error, >0 for success. @@ -757,13 +743,12 @@ int fr30_cgen_extract_operand the handlers. */ int -fr30_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) - CGEN_CPU_DESC cd; - int opindex; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS * fields; - bfd_vma pc; +fr30_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) { /* Assume success (for those operands that are nops). */ int length = 1; @@ -954,10 +939,8 @@ cgen_extract_fn * const fr30_cgen_extrac extract_insn_normal, }; -int fr30_cgen_get_int_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); -bfd_vma fr30_cgen_get_vma_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +int fr30_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma fr30_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); /* Getting values from cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they return. @@ -965,10 +948,9 @@ bfd_vma fr30_cgen_get_vma_operand not appropriate. */ int -fr30_cgen_get_int_operand (cd, opindex, fields) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - const CGEN_FIELDS * fields; +fr30_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) { int value; @@ -1094,10 +1076,9 @@ fr30_cgen_get_int_operand (cd, opindex, } bfd_vma -fr30_cgen_get_vma_operand (cd, opindex, fields) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - const CGEN_FIELDS * fields; +fr30_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) { bfd_vma value; @@ -1222,10 +1203,8 @@ fr30_cgen_get_vma_operand (cd, opindex, return value; } -void fr30_cgen_set_int_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); -void fr30_cgen_set_vma_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); +void fr30_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void fr30_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); /* Stuffing values in cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they accept. @@ -1233,11 +1212,10 @@ void fr30_cgen_set_vma_operand not appropriate. */ void -fr30_cgen_set_int_operand (cd, opindex, fields, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - CGEN_FIELDS * fields; - int value; +fr30_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) { switch (opindex) { @@ -1355,11 +1333,10 @@ fr30_cgen_set_int_operand (cd, opindex, } void -fr30_cgen_set_vma_operand (cd, opindex, fields, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - CGEN_FIELDS * fields; - bfd_vma value; +fr30_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) { switch (opindex) { @@ -1479,8 +1456,7 @@ fr30_cgen_set_vma_operand (cd, opindex, /* Function to call before using the instruction builder tables. */ void -fr30_cgen_init_ibld_table (cd) - CGEN_CPU_DESC cd; +fr30_cgen_init_ibld_table (CGEN_CPU_DESC cd) { cd->insert_handlers = & fr30_cgen_insert_handlers[0]; cd->extract_handlers = & fr30_cgen_extract_handlers[0]; diff -uprN binutils-2.16.91.0.1/opcodes/fr30-opc.c binutils-2.16.91.0.2/opcodes/fr30-opc.c --- binutils-2.16.91.0.1/opcodes/fr30-opc.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/fr30-opc.c 2005-07-20 12:27:28.634971785 -0700 @@ -33,10 +33,10 @@ with this program; if not, write to the /* The hash functions are recorded here to help keep assembler code out of the disassembler and vice versa. */ -static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int asm_hash_insn PARAMS ((const char *)); -static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); /* Instruction formats. */ @@ -1340,14 +1340,10 @@ dis_hash_insn (buf, value) return CGEN_DIS_HASH (buf, value); } -static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int)); - /* Set the recorded length of the insn in the CGEN_FIELDS struct. */ static void -set_fields_bitsize (fields, size) - CGEN_FIELDS *fields; - int size; +set_fields_bitsize (CGEN_FIELDS *fields, int size) { CGEN_FIELDS_BITSIZE (fields) = size; } @@ -1356,15 +1352,15 @@ set_fields_bitsize (fields, size) This plugs the opcode entries and macro instructions into the cpu table. */ void -fr30_cgen_init_opcode_table (cd) - CGEN_CPU_DESC cd; +fr30_cgen_init_opcode_table (CGEN_CPU_DESC cd) { int i; int num_macros = (sizeof (fr30_cgen_macro_insn_table) / sizeof (fr30_cgen_macro_insn_table[0])); const CGEN_IBASE *ib = & fr30_cgen_macro_insn_table[0]; const CGEN_OPCODE *oc = & fr30_cgen_macro_insn_opcode_table[0]; - CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN)); + CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); for (i = 0; i < num_macros; ++i) { diff -uprN binutils-2.16.91.0.1/opcodes/fr30-opc.h binutils-2.16.91.0.2/opcodes/fr30-opc.h --- binutils-2.16.91.0.1/opcodes/fr30-opc.h 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/fr30-opc.h 2005-07-20 12:27:28.641970631 -0700 @@ -28,9 +28,9 @@ with this program; if not, write to the /* -- opc.h */ /* ??? This can be improved upon. */ -#undef CGEN_DIS_HASH_SIZE +#undef CGEN_DIS_HASH_SIZE #define CGEN_DIS_HASH_SIZE 16 -#undef CGEN_DIS_HASH +#undef CGEN_DIS_HASH #define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 4) /* -- */ diff -uprN binutils-2.16.91.0.1/opcodes/frv-asm.c binutils-2.16.91.0.2/opcodes/frv-asm.c --- binutils-2.16.91.0.1/opcodes/frv-asm.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/frv-asm.c 2005-07-20 12:27:28.643970301 -0700 @@ -1,26 +1,27 @@ /* Assembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-asm.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -48,31 +49,6 @@ static const char * parse_insn_normal /* -- assembler routines inserted here. */ /* -- asm.c */ -static const char * parse_ulo16 - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_uslo16 - PARAMS ((CGEN_CPU_DESC, const char **, int, signed long *)); -static const char * parse_uhi16 - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static long parse_register_number - PARAMS ((const char **)); -static const char * parse_spr - PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *)); -static const char * parse_d12 - PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); -static const char * parse_s12 - PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); -static const char * parse_u12 - PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); -static const char * parse_even_register - PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *)); -static const char * parse_A0 - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_A1 - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_A - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *, unsigned long)); - inline static const char * parse_symbolic_address (CGEN_CPU_DESC cd, const char **strp, @@ -214,11 +190,10 @@ parse_ld_annotation (CGEN_CPU_DESC cd, } static const char * -parse_ulo16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_ulo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -230,7 +205,7 @@ parse_ulo16 (cd, strp, opindex, valuep) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing `)'"; ++*strp; @@ -245,7 +220,7 @@ parse_ulo16 (cd, strp, opindex, valuep) *strp += 9; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -257,7 +232,7 @@ parse_ulo16 (cd, strp, opindex, valuep) *strp += 7; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -269,7 +244,7 @@ parse_ulo16 (cd, strp, opindex, valuep) *strp += 15; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_FUNCDESC_GOTLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -281,7 +256,7 @@ parse_ulo16 (cd, strp, opindex, valuep) *strp += 10; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTOFFLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -293,7 +268,7 @@ parse_ulo16 (cd, strp, opindex, valuep) *strp += 18; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_FUNCDESC_GOTOFFLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -305,7 +280,7 @@ parse_ulo16 (cd, strp, opindex, valuep) *strp += 14; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTTLSDESCLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -317,7 +292,7 @@ parse_ulo16 (cd, strp, opindex, valuep) *strp += 11; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_TLSMOFFLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -329,7 +304,7 @@ parse_ulo16 (cd, strp, opindex, valuep) *strp += 13; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTTLSOFFLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -341,11 +316,10 @@ parse_ulo16 (cd, strp, opindex, valuep) } static const char * -parse_uslo16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - signed long *valuep; +parse_uslo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + signed long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -357,7 +331,7 @@ parse_uslo16 (cd, strp, opindex, valuep) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing `)'"; ++*strp; @@ -372,7 +346,7 @@ parse_uslo16 (cd, strp, opindex, valuep) *strp += 9; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -384,7 +358,7 @@ parse_uslo16 (cd, strp, opindex, valuep) *strp += 7; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -396,7 +370,7 @@ parse_uslo16 (cd, strp, opindex, valuep) *strp += 15; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_FUNCDESC_GOTLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -408,7 +382,7 @@ parse_uslo16 (cd, strp, opindex, valuep) *strp += 10; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTOFFLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -420,7 +394,7 @@ parse_uslo16 (cd, strp, opindex, valuep) *strp += 18; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_FUNCDESC_GOTOFFLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -432,7 +406,7 @@ parse_uslo16 (cd, strp, opindex, valuep) *strp += 14; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTTLSDESCLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -444,7 +418,7 @@ parse_uslo16 (cd, strp, opindex, valuep) *strp += 11; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_TLSMOFFLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -456,7 +430,7 @@ parse_uslo16 (cd, strp, opindex, valuep) *strp += 13; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTTLSOFFLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -468,11 +442,10 @@ parse_uslo16 (cd, strp, opindex, valuep) } static const char * -parse_uhi16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_uhi16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -484,7 +457,7 @@ parse_uhi16 (cd, strp, opindex, valuep) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_HI16, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing `)'"; ++*strp; @@ -506,7 +479,7 @@ parse_uhi16 (cd, strp, opindex, valuep) *strp += 9; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELHI, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -518,7 +491,7 @@ parse_uhi16 (cd, strp, opindex, valuep) *strp += 7; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTHI, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -530,7 +503,7 @@ parse_uhi16 (cd, strp, opindex, valuep) *strp += 15; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_FUNCDESC_GOTHI, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -542,7 +515,7 @@ parse_uhi16 (cd, strp, opindex, valuep) *strp += 10; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTOFFHI, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -554,7 +527,7 @@ parse_uhi16 (cd, strp, opindex, valuep) *strp += 18; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_FUNCDESC_GOTOFFHI, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -578,7 +551,7 @@ parse_uhi16 (cd, strp, opindex, valuep) *strp += 11; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_TLSMOFFHI, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -590,7 +563,7 @@ parse_uhi16 (cd, strp, opindex, valuep) *strp += 13; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTTLSOFFHI, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -602,10 +575,10 @@ parse_uhi16 (cd, strp, opindex, valuep) } static long -parse_register_number (strp) - const char **strp; +parse_register_number (const char **strp) { int regno; + if (**strp < '0' || **strp > '9') return -1; /* error */ @@ -617,11 +590,10 @@ parse_register_number (strp) } static const char * -parse_spr (cd, strp, table, valuep) - CGEN_CPU_DESC cd; - const char **strp; - CGEN_KEYWORD * table; - long *valuep; +parse_spr (CGEN_CPU_DESC cd, + const char **strp, + CGEN_KEYWORD * table, + long *valuep) { const char *save_strp; long regno; @@ -632,10 +604,10 @@ parse_spr (cd, strp, table, valuep) *strp += 4; regno = parse_register_number (strp); if (**strp != ']') - return "missing `]'"; + return _("missing `]'"); ++*strp; if (! spr_valid (regno)) - return "Special purpose register number is out of range"; + return _("Special purpose register number is out of range"); *valuep = regno; return NULL; } @@ -645,7 +617,7 @@ parse_spr (cd, strp, table, valuep) if (regno != -1) { if (! spr_valid (regno)) - return "Special purpose register number is out of range"; + return _("Special purpose register number is out of range"); *valuep = regno; return NULL; } @@ -655,11 +627,10 @@ parse_spr (cd, strp, table, valuep) } static const char * -parse_d12 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - long *valuep; +parse_d12 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -673,7 +644,7 @@ parse_d12 (cd, strp, opindex, valuep) *strp += 9; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GPREL12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing `)'"; ++*strp; @@ -685,7 +656,7 @@ parse_d12 (cd, strp, opindex, valuep) *strp += 7; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOT12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -697,7 +668,7 @@ parse_d12 (cd, strp, opindex, valuep) *strp += 15; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_FUNCDESC_GOT12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -709,7 +680,7 @@ parse_d12 (cd, strp, opindex, valuep) *strp += 10; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTOFF12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -721,7 +692,7 @@ parse_d12 (cd, strp, opindex, valuep) *strp += 18; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_FUNCDESC_GOTOFF12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -733,7 +704,7 @@ parse_d12 (cd, strp, opindex, valuep) *strp += 14; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTTLSDESC12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -745,7 +716,7 @@ parse_d12 (cd, strp, opindex, valuep) *strp += 11; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_TLSMOFF12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -757,7 +728,7 @@ parse_d12 (cd, strp, opindex, valuep) *strp += 13; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTTLSOFF12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -769,11 +740,10 @@ parse_d12 (cd, strp, opindex, valuep) } static const char * -parse_s12 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - long *valuep; +parse_s12 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -787,7 +757,7 @@ parse_s12 (cd, strp, opindex, valuep) *strp += 9; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GPREL12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing `)'"; ++*strp; @@ -799,7 +769,7 @@ parse_s12 (cd, strp, opindex, valuep) *strp += 7; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOT12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -811,7 +781,7 @@ parse_s12 (cd, strp, opindex, valuep) *strp += 15; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_FUNCDESC_GOT12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -823,7 +793,7 @@ parse_s12 (cd, strp, opindex, valuep) *strp += 10; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTOFF12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -835,7 +805,7 @@ parse_s12 (cd, strp, opindex, valuep) *strp += 18; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_FUNCDESC_GOTOFF12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -847,7 +817,7 @@ parse_s12 (cd, strp, opindex, valuep) *strp += 14; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTTLSDESC12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -859,7 +829,7 @@ parse_s12 (cd, strp, opindex, valuep) *strp += 11; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_TLSMOFF12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -871,7 +841,7 @@ parse_s12 (cd, strp, opindex, valuep) *strp += 13; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GOTTLSOFF12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing ')'"; ++*strp; @@ -886,11 +856,10 @@ parse_s12 (cd, strp, opindex, valuep) } static const char * -parse_u12 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - long *valuep; +parse_u12 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -903,7 +872,7 @@ parse_u12 (cd, strp, opindex, valuep) *strp += 9; errmsg = parse_symbolic_address (cd, strp, opindex, BFD_RELOC_FRV_GPRELU12, - &result_type, &value); + & result_type, & value); if (**strp != ')') return "missing `)'"; ++*strp; @@ -919,12 +888,11 @@ parse_u12 (cd, strp, opindex, valuep) } static const char * -parse_A (cd, strp, opindex, valuep, A) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; - unsigned long A; +parse_A (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep, + unsigned long A) { const char *errmsg; @@ -936,37 +904,34 @@ parse_A (cd, strp, opindex, valuep, A) return errmsg; if (*valuep != A) - return "Value of A operand must be 0 or 1"; + return _("Value of A operand must be 0 or 1"); return NULL; } static const char * -parse_A0 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_A0 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { return parse_A (cd, strp, opindex, valuep, 0); } static const char * -parse_A1 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_A1 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { return parse_A (cd, strp, opindex, valuep, 1); } static const char * -parse_even_register (cd, strP, tableP, valueP) - CGEN_CPU_DESC cd; - const char ** strP; - CGEN_KEYWORD * tableP; - long * valueP; +parse_even_register (CGEN_CPU_DESC cd, + const char ** strP, + CGEN_KEYWORD * tableP, + long * valueP) { const char * errmsg; const char * saved_star_strP = * strP; @@ -1003,7 +968,7 @@ parse_call_label (CGEN_CPU_DESC cd, BFD_RELOC_FRV_GETTLSOFF, resultp, &value); if (**strp != ')') - return "missing `)'"; + return _("missing `)'"); ++*strp; *valuep = value; return errmsg; @@ -1016,7 +981,7 @@ parse_call_label (CGEN_CPU_DESC cd, /* -- */ const char * frv_cgen_parse_operand - PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); /* Main entry point for operand parsing. @@ -1032,11 +997,10 @@ const char * frv_cgen_parse_operand the handlers. */ const char * -frv_cgen_parse_operand (cd, opindex, strp, fields) - CGEN_CPU_DESC cd; - int opindex; - const char ** strp; - CGEN_FIELDS * fields; +frv_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) { const char * errmsg = NULL; /* Used by scalar operands that still need to be parsed. */ @@ -1308,8 +1272,7 @@ cgen_parse_fn * const frv_cgen_parse_han }; void -frv_cgen_init_asm (cd) - CGEN_CPU_DESC cd; +frv_cgen_init_asm (CGEN_CPU_DESC cd) { frv_cgen_init_opcode_table (cd); frv_cgen_init_ibld_table (cd); @@ -1692,30 +1655,3 @@ frv_cgen_assemble_insn (CGEN_CPU_DESC cd return NULL; } } - -#if 0 /* This calls back to GAS which we can't do without care. */ - -/* Record each member of OPVALS in the assembler's symbol table. - This lets GAS parse registers for us. - ??? Interesting idea but not currently used. */ - -/* Record each member of OPVALS in the assembler's symbol table. - FIXME: Not currently used. */ - -void -frv_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) -{ - CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); - const CGEN_KEYWORD_ENTRY * ke; - - while ((ke = cgen_keyword_search_next (& search)) != NULL) - { -#if 0 /* Unnecessary, should be done in the search routine. */ - if (! frv_cgen_opval_supported (ke)) - continue; -#endif - cgen_asm_record_register (cd, ke->name, ke->value); - } -} - -#endif /* 0 */ diff -uprN binutils-2.16.91.0.1/opcodes/frv-desc.c binutils-2.16.91.0.2/opcodes/frv-desc.c --- binutils-2.16.91.0.1/opcodes/frv-desc.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/frv-desc.c 2005-07-20 12:27:28.652968817 -0700 @@ -6142,27 +6142,23 @@ static const CGEN_IBASE frv_cgen_insn_ta #undef A /* Initialize anything needed to be done once, before any cpu_open call. */ -static void init_tables PARAMS ((void)); static void -init_tables () +init_tables (void) { } -static const CGEN_MACH * lookup_mach_via_bfd_name - PARAMS ((const CGEN_MACH *, const char *)); -static void build_hw_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_operand_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_insn_table PARAMS ((CGEN_CPU_TABLE *)); -static void frv_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *)); +static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); +static void build_hw_table (CGEN_CPU_TABLE *); +static void build_ifield_table (CGEN_CPU_TABLE *); +static void build_operand_table (CGEN_CPU_TABLE *); +static void build_insn_table (CGEN_CPU_TABLE *); +static void frv_cgen_rebuild_tables (CGEN_CPU_TABLE *); /* Subroutine of frv_cgen_cpu_open to look up a mach via its bfd name. */ static const CGEN_MACH * -lookup_mach_via_bfd_name (table, name) - const CGEN_MACH *table; - const char *name; +lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) { while (table->name) { @@ -6176,8 +6172,7 @@ lookup_mach_via_bfd_name (table, name) /* Subroutine of frv_cgen_cpu_open to build the hardware table. */ static void -build_hw_table (cd) - CGEN_CPU_TABLE *cd; +build_hw_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; @@ -6203,8 +6198,7 @@ build_hw_table (cd) /* Subroutine of frv_cgen_cpu_open to build the hardware table. */ static void -build_ifield_table (cd) - CGEN_CPU_TABLE *cd; +build_ifield_table (CGEN_CPU_TABLE *cd) { cd->ifld_table = & frv_cgen_ifld_table[0]; } @@ -6212,8 +6206,7 @@ build_ifield_table (cd) /* Subroutine of frv_cgen_cpu_open to build the hardware table. */ static void -build_operand_table (cd) - CGEN_CPU_TABLE *cd; +build_operand_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; @@ -6221,8 +6214,7 @@ build_operand_table (cd) /* MAX_OPERANDS is only an upper bound on the number of selected entries. However each entry is indexed by it's enum so there can be holes in the table. */ - const CGEN_OPERAND **selected = - (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); cd->operand_table.init_entries = init; cd->operand_table.entry_size = sizeof (CGEN_OPERAND); @@ -6245,12 +6237,11 @@ build_operand_table (cd) operand elements to be in the table [which they mightn't be]. */ static void -build_insn_table (cd) - CGEN_CPU_TABLE *cd; +build_insn_table (CGEN_CPU_TABLE *cd) { int i; const CGEN_IBASE *ib = & frv_cgen_insn_table[0]; - CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); for (i = 0; i < MAX_INSNS; ++i) @@ -6263,8 +6254,7 @@ build_insn_table (cd) /* Subroutine of frv_cgen_cpu_open to rebuild the tables. */ static void -frv_cgen_rebuild_tables (cd) - CGEN_CPU_TABLE *cd; +frv_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) { int i; unsigned int isas = cd->isas; @@ -6276,7 +6266,7 @@ frv_cgen_rebuild_tables (cd) #define UNSET (CGEN_SIZE_UNKNOWN + 1) cd->default_insn_bitsize = UNSET; cd->base_insn_bitsize = UNSET; - cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) if (((1 << i) & isas) != 0) @@ -6288,7 +6278,7 @@ frv_cgen_rebuild_tables (cd) if (cd->default_insn_bitsize == UNSET) cd->default_insn_bitsize = isa->default_insn_bitsize; else if (isa->default_insn_bitsize == cd->default_insn_bitsize) - ; /* this is ok */ + ; /* This is ok. */ else cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; @@ -6297,7 +6287,7 @@ frv_cgen_rebuild_tables (cd) if (cd->base_insn_bitsize == UNSET) cd->base_insn_bitsize = isa->base_insn_bitsize; else if (isa->base_insn_bitsize == cd->base_insn_bitsize) - ; /* this is ok */ + ; /* This is ok. */ else cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; @@ -6409,12 +6399,12 @@ frv_cgen_cpu_open (enum cgen_cpu_open_ar } va_end (ap); - /* mach unspecified means "all" */ + /* Mach unspecified means "all". */ if (machs == 0) machs = (1 << MAX_MACHS) - 1; - /* base mach is always selected */ + /* Base mach is always selected. */ machs |= 1; - /* isa unspecified means "all" */ + /* ISA unspecified means "all". */ if (isas == 0) isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) @@ -6447,9 +6437,7 @@ frv_cgen_cpu_open (enum cgen_cpu_open_ar MACH_NAME is the bfd name of the mach. */ CGEN_CPU_DESC -frv_cgen_cpu_open_1 (mach_name, endian) - const char *mach_name; - enum cgen_endian endian; +frv_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) { return frv_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, CGEN_CPU_OPEN_ENDIAN, endian, @@ -6462,8 +6450,7 @@ frv_cgen_cpu_open_1 (mach_name, endian) place as some simulator ports use this but they don't use libopcodes. */ void -frv_cgen_cpu_close (cd) - CGEN_CPU_DESC cd; +frv_cgen_cpu_close (CGEN_CPU_DESC cd) { unsigned int i; const CGEN_INSN *insns; @@ -6472,23 +6459,17 @@ frv_cgen_cpu_close (cd) { insns = cd->macro_insn_table.init_entries; for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) - { - if (CGEN_INSN_RX ((insns))) - regfree (CGEN_INSN_RX (insns)); - } + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); } if (cd->insn_table.init_entries) { insns = cd->insn_table.init_entries; for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) - { - if (CGEN_INSN_RX (insns)) - regfree (CGEN_INSN_RX (insns)); - } - } - - + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } if (cd->macro_insn_table.init_entries) free ((CGEN_INSN *) cd->macro_insn_table.init_entries); diff -uprN binutils-2.16.91.0.1/opcodes/frv-dis.c binutils-2.16.91.0.2/opcodes/frv-dis.c --- binutils-2.16.91.0.1/opcodes/frv-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/frv-dis.c 2005-07-20 12:27:28.654968488 -0700 @@ -1,27 +1,27 @@ /* Disassembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-dis.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 -Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -56,36 +56,28 @@ static int read_insn (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, unsigned long *); -/* -- disassembler routines inserted here */ +/* -- disassembler routines inserted here. */ /* -- dis.c */ -static void print_spr - PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned)); -static void print_hi - PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); -static void print_lo - PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); - static void print_at (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - PTR dis_info, + void * dis_info, long reloc_ann ATTRIBUTE_UNUSED, long value ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED - ) + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; + (*info->fprintf_func) (info->stream, "@"); } static void -print_spr (cd, dis_info, names, regno, attrs) - CGEN_CPU_DESC cd; - PTR dis_info; - CGEN_KEYWORD *names; - long regno; - unsigned int attrs; +print_spr (CGEN_CPU_DESC cd, + void * dis_info, + CGEN_KEYWORD *names, + long regno, + unsigned int attrs) { /* Use the register index format for any unnamed registers. */ if (cgen_keyword_lookup_value (names, regno) == NULL) @@ -98,29 +90,25 @@ print_spr (cd, dis_info, names, regno, a } static void -print_hi (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_hi (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; - if (value) - (*info->fprintf_func) (info->stream, "0x%lx", value); - else - (*info->fprintf_func) (info->stream, "hi(0x%lx)", value); + + (*info->fprintf_func) (info->stream, value ? "0x%lx" : "hi(0x%lx)", value); } static void -print_lo (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_lo (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; if (value) @@ -132,8 +120,7 @@ print_lo (cd, dis_info, value, attrs, pc /* -- */ void frv_cgen_print_operand - PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, - void const *, bfd_vma, int)); + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); /* Main entry point for printing operands. XINFO is a `void *' and not a `disassemble_info *' to not put a requirement @@ -151,16 +138,15 @@ void frv_cgen_print_operand the handlers. */ void -frv_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) - CGEN_CPU_DESC cd; - int opindex; - PTR xinfo; - CGEN_FIELDS *fields; - void const *attrs ATTRIBUTE_UNUSED; - bfd_vma pc; - int length; +frv_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) { - disassemble_info *info = (disassemble_info *) xinfo; + disassemble_info *info = (disassemble_info *) xinfo; switch (opindex) { @@ -420,8 +406,7 @@ cgen_print_fn * const frv_cgen_print_han void -frv_cgen_init_dis (cd) - CGEN_CPU_DESC cd; +frv_cgen_init_dis (CGEN_CPU_DESC cd) { frv_cgen_init_opcode_table (cd); frv_cgen_init_ibld_table (cd); @@ -473,7 +458,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUT /* Print the operand as directed by the attributes. */ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) - ; /* nothing to do */ + ; /* Nothing to do. */ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) (*info->print_address_func) (value, info); else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) @@ -555,6 +540,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UN unsigned long *insn_value) { int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) { (*info->memory_error_func) (status, pc, info); @@ -659,13 +645,13 @@ print_insn (CGEN_CPU_DESC cd, length = CGEN_EXTRACT_FN (cd, insn) (cd, insn, &ex_info, insn_value_cropped, &fields, pc); - /* length < 0 -> error */ + /* Length < 0 -> error. */ if (length < 0) return length; if (length > 0) { CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); - /* length is in bits, result is in bytes */ + /* Length is in bits, result is in bytes. */ return length / 8; } } @@ -715,7 +701,8 @@ default_print_insn (CGEN_CPU_DESC cd, bf Print one instruction from PC on INFO->STREAM. Return the size of the instruction (in bytes). */ -typedef struct cpu_desc_list { +typedef struct cpu_desc_list +{ struct cpu_desc_list *next; int isa; int mach; @@ -800,7 +787,7 @@ print_insn_frv (bfd_vma pc, disassemble_ if (!cd) abort (); - /* save this away for future reference */ + /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; cl->isa = isa; diff -uprN binutils-2.16.91.0.1/opcodes/frv-ibld.c binutils-2.16.91.0.2/opcodes/frv-ibld.c --- binutils-2.16.91.0.1/opcodes/frv-ibld.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/frv-ibld.c 2005-07-20 12:27:28.658967828 -0700 @@ -1,25 +1,26 @@ /* Instruction building/extraction support for frv. -*- C -*- -THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. -- the resultant file is machine generated, cgen-ibld.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -35,9 +36,9 @@ along with this program; if not, write t #include "opintl.h" #include "safe-ctype.h" -#undef min +#undef min #define min(a,b) ((a) < (b) ? (a) : (b)) -#undef max +#undef max #define max(a,b) ((a) > (b) ? (a) : (b)) /* Used by the ifield rtx function. */ @@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd, if (length == 0) return NULL; -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - if (word_length > 32) abort (); @@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd, #if CGEN_INT_INSN_P /* Cover function to store an insn value into an integral insn. Must go here - because it needs -desc.h for CGEN_INT_INSN_P. */ + because it needs -desc.h for CGEN_INT_INSN_P. */ static void put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, @@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATT int shift = insn_length - length; /* Written this way to avoid undefined behaviour. */ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); } } @@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd, { unsigned long x; int shift; -#if 0 - int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; -#endif + x = cgen_get_insn_value (cd, bufp, word_length); if (CGEN_INSN_LSB0_P) @@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd, return 1; } -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - if (word_length > 32) abort (); @@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd, return CGEN_INSN_BITSIZE (insn); } -/* machine generated code added here */ +/* Machine generated code added here. */ const char * frv_cgen_insert_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); /* Main entry point for operand insertion. @@ -559,12 +547,11 @@ const char * frv_cgen_insert_operand resolved during parsing. */ const char * -frv_cgen_insert_operand (cd, opindex, fields, buffer, pc) - CGEN_CPU_DESC cd; - int opindex; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc ATTRIBUTE_UNUSED; +frv_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) { const char * errmsg = NULL; unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); @@ -864,8 +851,7 @@ frv_cgen_insert_operand (cd, opindex, fi } int frv_cgen_extract_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - CGEN_FIELDS *, bfd_vma)); + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); /* Main entry point for operand extraction. The result is <= 0 for error, >0 for success. @@ -883,13 +869,12 @@ int frv_cgen_extract_operand the handlers. */ int -frv_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) - CGEN_CPU_DESC cd; - int opindex; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS * fields; - bfd_vma pc; +frv_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) { /* Assume success (for those operands that are nops). */ int length = 1; @@ -1192,10 +1177,8 @@ cgen_extract_fn * const frv_cgen_extract extract_insn_normal, }; -int frv_cgen_get_int_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); -bfd_vma frv_cgen_get_vma_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +int frv_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma frv_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); /* Getting values from cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they return. @@ -1203,10 +1186,9 @@ bfd_vma frv_cgen_get_vma_operand not appropriate. */ int -frv_cgen_get_int_operand (cd, opindex, fields) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - const CGEN_FIELDS * fields; +frv_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) { int value; @@ -1464,10 +1446,9 @@ frv_cgen_get_int_operand (cd, opindex, f } bfd_vma -frv_cgen_get_vma_operand (cd, opindex, fields) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - const CGEN_FIELDS * fields; +frv_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) { bfd_vma value; @@ -1724,10 +1705,8 @@ frv_cgen_get_vma_operand (cd, opindex, f return value; } -void frv_cgen_set_int_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); -void frv_cgen_set_vma_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); +void frv_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void frv_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); /* Stuffing values in cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they accept. @@ -1735,11 +1714,10 @@ void frv_cgen_set_vma_operand not appropriate. */ void -frv_cgen_set_int_operand (cd, opindex, fields, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - CGEN_FIELDS * fields; - int value; +frv_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) { switch (opindex) { @@ -1993,11 +1971,10 @@ frv_cgen_set_int_operand (cd, opindex, f } void -frv_cgen_set_vma_operand (cd, opindex, fields, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - CGEN_FIELDS * fields; - bfd_vma value; +frv_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) { switch (opindex) { @@ -2253,8 +2230,7 @@ frv_cgen_set_vma_operand (cd, opindex, f /* Function to call before using the instruction builder tables. */ void -frv_cgen_init_ibld_table (cd) - CGEN_CPU_DESC cd; +frv_cgen_init_ibld_table (CGEN_CPU_DESC cd) { cd->insert_handlers = & frv_cgen_insert_handlers[0]; cd->extract_handlers = & frv_cgen_extract_handlers[0]; diff -uprN binutils-2.16.91.0.1/opcodes/frv-opc.c binutils-2.16.91.0.2/opcodes/frv-opc.c --- binutils-2.16.91.0.1/opcodes/frv-opc.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/frv-opc.c 2005-07-20 12:27:28.666966509 -0700 @@ -34,132 +34,120 @@ with this program; if not, write to the #include "elf/frv.h" #include -static int match_unit - PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, CGEN_ATTR_VALUE_TYPE)); -static int match_vliw - PARAMS ((VLIW_COMBO *, VLIW_COMBO *, int)); -static VLIW_COMBO * add_next_to_vliw - PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); -static int find_major_in_vliw - PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); -static int fr400_check_insn_major_constraints - PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); -static int fr450_check_insn_major_constraints - PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); -static int fr500_check_insn_major_constraints - PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE)); -static int fr550_check_insn_major_constraints - PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, const CGEN_INSN *)); -static int check_insn_major_constraints - PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE, const CGEN_INSN *)); +/* Returns TRUE if {MAJOR,MACH} is a major branch of the FRV + development tree. */ -int +bfd_boolean frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) { switch (mach) { case bfd_mach_fr400: if (major >= FR400_MAJOR_B_1 && major <= FR400_MAJOR_B_6) - return 1; /* is a branch */ + return TRUE; break; case bfd_mach_fr450: if (major >= FR450_MAJOR_B_1 && major <= FR450_MAJOR_B_6) - return 1; /* is a branch */ + return TRUE; break; default: if (major >= FR500_MAJOR_B_1 && major <= FR500_MAJOR_B_6) - return 1; /* is a branch */ + return TRUE; break; } - return 0; /* not a branch */ + return FALSE; } -int +/* Returns TRUE if {MAJOR,MACH} supports floating point insns. */ + +bfd_boolean frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) { switch (mach) { case bfd_mach_fr400: case bfd_mach_fr450: - return 0; /* No float insns */ + return FALSE; default: if (major >= FR500_MAJOR_F_1 && major <= FR500_MAJOR_F_8) - return 1; /* is a float insn */ + return TRUE; break; } - return 0; /* not a branch */ + return FALSE; } -int +/* Returns TRUE if {MAJOR,MACH} supports media insns. */ + +bfd_boolean frv_is_media_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) { switch (mach) { case bfd_mach_fr400: if (major >= FR400_MAJOR_M_1 && major <= FR400_MAJOR_M_2) - return 1; /* is a media insn */ + return TRUE; break; case bfd_mach_fr450: if (major >= FR450_MAJOR_M_1 && major <= FR450_MAJOR_M_6) - return 1; /* is a media insn */ + return TRUE; break; default: if (major >= FR500_MAJOR_M_1 && major <= FR500_MAJOR_M_8) - return 1; /* is a media insn */ + return TRUE; break; } - return 0; /* not a branch */ + return FALSE; } -int +bfd_boolean frv_is_branch_insn (const CGEN_INSN *insn) { if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), bfd_mach_fr400)) - return 1; + return TRUE; if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR), bfd_mach_fr450)) - return 1; + return TRUE; if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), bfd_mach_fr500)) - return 1; + return TRUE; - return 0; + return FALSE; } -int +bfd_boolean frv_is_float_insn (const CGEN_INSN *insn) { if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), bfd_mach_fr400)) - return 1; + return TRUE; if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR), bfd_mach_fr450)) - return 1; + return TRUE; if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), bfd_mach_fr500)) - return 1; + return TRUE; - return 0; + return FALSE; } -int +bfd_boolean frv_is_media_insn (const CGEN_INSN *insn) { if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), bfd_mach_fr400)) - return 1; + return TRUE; if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR), bfd_mach_fr450)) - return 1; + return TRUE; if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), bfd_mach_fr500)) - return 1; + return TRUE; - return 0; + return FALSE; } /* This table represents the allowable packing for vliw insns for the fr400. @@ -397,10 +385,10 @@ frv_vliw_reset (FRV_VLIW *vliw, unsigned } } -/* Return 1 if unit1 is a match for unit2. +/* Return TRUE if unit1 is a match for unit2. Unit1 comes from the insn's UNIT attribute. unit2 comes from one of the *_allowed_vliw tables above. */ -static int +static bfd_boolean match_unit (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit1, CGEN_ATTR_VALUE_TYPE unit2) { @@ -408,9 +396,9 @@ match_unit (FRV_VLIW *vliw, unit1 = vliw->unit_mapping[unit1]; if (unit1 == unit2) - return 1; + return TRUE; if (unit1 < unit2) - return 0; + return FALSE; switch (unit1) { @@ -420,36 +408,34 @@ match_unit (FRV_VLIW *vliw, /* The 01 versions of these units are within 2 enums of the 0 or 1 versions. */ if (unit1 - unit2 <= 2) - return 1; + return TRUE; break; case UNIT_IALL: case UNIT_FMALL: /* The ALL versions of these units are within 5 enums of the 0, 1, 2 or 3 versions. */ if (unit1 - unit2 <= 5) - return 1; + return TRUE; break; default: break; } - return 0; + return FALSE; } -/* Return 1 if the vliws match, 0 otherwise. */ +/* Return TRUE if the vliws match, FALSE otherwise. */ -static int +static bfd_boolean match_vliw (VLIW_COMBO *vliw1, VLIW_COMBO *vliw2, int vliw_size) { int i; for (i = 0; i < vliw_size; ++i) - { - if ((*vliw1)[i] != (*vliw2)[i]) - return 0; - } + if ((*vliw1)[i] != (*vliw2)[i]) + return FALSE; - return 1; + return TRUE; } /* Find the next vliw vliw in the table that can accomodate the new insn. @@ -466,7 +452,7 @@ add_next_to_vliw (FRV_VLIW *vliw, CGEN_A { fprintf (stderr, "frv-opc.c line %d: bad vliw->next_slot value.\n", __LINE__); - abort (); /* Should never happen */ + abort (); /* Should never happen. */ } /* The table is sorted by units allowed within slots, so vliws with @@ -483,28 +469,26 @@ add_next_to_vliw (FRV_VLIW *vliw, CGEN_A return NULL; } -/* Look for the given major insn type in the given vliw. Return 1 if found, - return 0 otherwise. */ +/* Look for the given major insn type in the given vliw. + Returns TRUE if found, FALSE otherwise. */ -static int +static bfd_boolean find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) { int i; for (i = 0; i < vliw->next_slot; ++i) if (vliw->major[i] == major) - return 1; + return TRUE; - return 0; + return FALSE; } /* Check for constraints between the insns in the vliw due to major insn types. */ -static int -fr400_check_insn_major_constraints ( - FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major -) +static bfd_boolean +fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) { /* In the cpu file, all media insns are represented as being allowed in both media units. This makes it easier since this is the case for fr500. @@ -516,17 +500,15 @@ fr400_check_insn_major_constraints ( return ! find_major_in_vliw (vliw, FR400_MAJOR_M_1) && ! find_major_in_vliw (vliw, FR400_MAJOR_M_2); case FR400_MAJOR_M_1: - return !find_major_in_vliw (vliw, FR400_MAJOR_M_2); + return ! find_major_in_vliw (vliw, FR400_MAJOR_M_2); default: break; } - return 1; + return TRUE; } -static int -fr450_check_insn_major_constraints ( - FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major -) +static bfd_boolean +fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) { CGEN_ATTR_VALUE_TYPE other_major; @@ -536,7 +518,7 @@ fr450_check_insn_major_constraints ( /* (M4, M5) and (M4, M6) are allowed. */ if (other_major == FR450_MAJOR_M_4) if (major == FR450_MAJOR_M_5 || major == FR450_MAJOR_M_6) - return 1; + return TRUE; /* Otherwise, instructions in even-numbered media categories cannot be executed in parallel with other media instructions. */ @@ -556,38 +538,37 @@ fr450_check_insn_major_constraints ( || other_major == FR450_MAJOR_M_6); default: - return 1; + return TRUE; } } -static int -find_unit_in_vliw ( - FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit -) +static bfd_boolean +find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit) { int i; + for (i = 0; i < vliw->next_slot; ++i) if (CGEN_INSN_ATTR_VALUE (vliw->insn[i], CGEN_INSN_UNIT) == unit) - return 1; + return TRUE; - return 0; /* not found */ + return FALSE; /* Not found. */ } -static int -find_major_in_slot ( - FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major, CGEN_ATTR_VALUE_TYPE slot -) +static bfd_boolean +find_major_in_slot (FRV_VLIW *vliw, + CGEN_ATTR_VALUE_TYPE major, + CGEN_ATTR_VALUE_TYPE slot) { int i; for (i = 0; i < vliw->next_slot; ++i) if (vliw->major[i] == major && (*vliw->current_vliw)[i] == slot) - return 1; + return TRUE; - return 0; + return FALSE; } -static int +static bfd_boolean fr550_find_media_in_vliw (FRV_VLIW *vliw) { int i; @@ -603,13 +584,13 @@ fr550_find_media_in_vliw (FRV_VLIW *vliw || CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MCLRACC_1) continue; - return 1; /* found one */ + return TRUE; /* Found one. */ } - return 0; + return FALSE; } -static int +static bfd_boolean fr550_find_float_in_vliw (FRV_VLIW *vliw) { int i; @@ -623,16 +604,16 @@ fr550_find_float_in_vliw (FRV_VLIW *vliw if (CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_FNOP) continue; - return 1; /* found one */ + return TRUE; /* Found one. */ } - return 0; + return FALSE; } -static int -fr550_check_insn_major_constraints ( - FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major, const CGEN_INSN *insn -) +static bfd_boolean +fr550_check_insn_major_constraints (FRV_VLIW *vliw, + CGEN_ATTR_VALUE_TYPE major, + const CGEN_INSN *insn) { CGEN_ATTR_VALUE_TYPE unit; CGEN_ATTR_VALUE_TYPE slot = (*vliw->current_vliw)[vliw->next_slot]; @@ -646,8 +627,8 @@ fr550_check_insn_major_constraints ( break; case UNIT_FM2: case UNIT_FM3: - /* Floating point insns other than FNOP in slot f2 or f3 cannot coexist with - media insns. */ + /* Floating point insns other than FNOP in slot f2 or f3 cannot coexist + with media insns. */ if (major >= FR550_MAJOR_F_1 && major <= FR550_MAJOR_F_4 && CGEN_INSN_NUM (insn) != FRV_INSN_FNOP) return ! fr550_find_media_in_vliw (vliw); @@ -657,30 +638,31 @@ fr550_check_insn_major_constraints ( && CGEN_INSN_NUM (insn) != FRV_INSN_MNOP) return ! fr550_find_float_in_vliw (vliw); /* F-2 in slot f2 or f3 cannot coexist with F-2 or F-4 in slot f1 or f2 - respectively. - */ + respectively. */ if (major == FR550_MAJOR_F_2) - return ! find_major_in_slot (vliw, FR550_MAJOR_F_2, slot - (UNIT_FM2 - UNIT_FM0)) - && ! find_major_in_slot (vliw, FR550_MAJOR_F_4, slot - (UNIT_FM2 - UNIT_FM0)); + return ! find_major_in_slot (vliw, FR550_MAJOR_F_2, + slot - (UNIT_FM2 - UNIT_FM0)) + && ! find_major_in_slot (vliw, FR550_MAJOR_F_4, + slot - (UNIT_FM2 - UNIT_FM0)); /* M-2 or M-5 in slot m2 or m3 cannot coexist with M-2 in slot m1 or m2 respectively. */ if (major == FR550_MAJOR_M_2 || major == FR550_MAJOR_M_5) - return ! find_major_in_slot (vliw, FR550_MAJOR_M_2, slot - (UNIT_FM2 - UNIT_FM0)); + return ! find_major_in_slot (vliw, FR550_MAJOR_M_2, + slot - (UNIT_FM2 - UNIT_FM0)); /* M-4 in slot m2 or m3 cannot coexist with M-4 in slot m1 or m2 respectively. */ if (major == FR550_MAJOR_M_4) - return ! find_major_in_slot (vliw, FR550_MAJOR_M_4, slot - (UNIT_FM2 - UNIT_FM0)); + return ! find_major_in_slot (vliw, FR550_MAJOR_M_4, + slot - (UNIT_FM2 - UNIT_FM0)); break; default: break; } - return 1; /* all ok */ + return TRUE; /* All OK. */ } -static int -fr500_check_insn_major_constraints ( - FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major -) +static bfd_boolean +fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) { /* TODO: A table might be faster for some of the more complex instances here. */ @@ -699,7 +681,7 @@ fr500_check_insn_major_constraints ( case FR500_MAJOR_F_4: case FR500_MAJOR_F_8: case FR500_MAJOR_M_8: - return 1; /* OK */ + return TRUE; /* OK */ case FR500_MAJOR_I_2: /* Cannot coexist with I-3 insn. */ return ! find_major_in_vliw (vliw, FR500_MAJOR_I_3); @@ -783,35 +765,33 @@ fr500_check_insn_major_constraints ( abort (); break; } - return 1; + return TRUE; } -static int -check_insn_major_constraints ( - FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major, const CGEN_INSN *insn -) +static bfd_boolean +check_insn_major_constraints (FRV_VLIW *vliw, + CGEN_ATTR_VALUE_TYPE major, + const CGEN_INSN *insn) { - int rc; switch (vliw->mach) { case bfd_mach_fr400: - rc = fr400_check_insn_major_constraints (vliw, major); - break; + return fr400_check_insn_major_constraints (vliw, major); + case bfd_mach_fr450: - rc = fr450_check_insn_major_constraints (vliw, major); - break; + return fr450_check_insn_major_constraints (vliw, major); + case bfd_mach_fr550: - rc = fr550_check_insn_major_constraints (vliw, major, insn); - break; + return fr550_check_insn_major_constraints (vliw, major, insn); + default: - rc = fr500_check_insn_major_constraints (vliw, major); - break; + return fr500_check_insn_major_constraints (vliw, major); } - return rc; } -/* Add in insn to the VLIW vliw if possible. Return 0 if successful, - non-zero otherwise. */ +/* Add in insn to the VLIW vliw if possible. + Return 0 if successful, non-zero otherwise. */ + int frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn) { @@ -832,7 +812,7 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const { fprintf (stderr, "frv-opc.c line %d: bad insn unit.\n", __LINE__); - abort (); /* no UNIT specified for this insn in frv.cpu */ + abort (); /* No UNIT specified for this insn in frv.cpu. */ } switch (vliw->mach) @@ -888,22 +868,21 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const return 1; } -int -spr_valid (regno) - long regno; +bfd_boolean +spr_valid (long regno) { - if (regno < 0) return 0; - if (regno <= 4095) return 1; - return 0; + if (regno < 0) return FALSE; + if (regno <= 4095) return TRUE; + return FALSE; } /* -- */ /* The hash functions are recorded here to help keep assembler code out of the disassembler and vice versa. */ -static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int asm_hash_insn PARAMS ((const char *)); -static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); /* Instruction formats. */ @@ -6223,14 +6202,10 @@ dis_hash_insn (buf, value) return CGEN_DIS_HASH (buf, value); } -static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int)); - /* Set the recorded length of the insn in the CGEN_FIELDS struct. */ static void -set_fields_bitsize (fields, size) - CGEN_FIELDS *fields; - int size; +set_fields_bitsize (CGEN_FIELDS *fields, int size) { CGEN_FIELDS_BITSIZE (fields) = size; } @@ -6239,15 +6214,15 @@ set_fields_bitsize (fields, size) This plugs the opcode entries and macro instructions into the cpu table. */ void -frv_cgen_init_opcode_table (cd) - CGEN_CPU_DESC cd; +frv_cgen_init_opcode_table (CGEN_CPU_DESC cd) { int i; int num_macros = (sizeof (frv_cgen_macro_insn_table) / sizeof (frv_cgen_macro_insn_table[0])); const CGEN_IBASE *ib = & frv_cgen_macro_insn_table[0]; const CGEN_OPCODE *oc = & frv_cgen_macro_insn_opcode_table[0]; - CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN)); + CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); for (i = 0; i < num_macros; ++i) { diff -uprN binutils-2.16.91.0.1/opcodes/frv-opc.h binutils-2.16.91.0.2/opcodes/frv-opc.h --- binutils-2.16.91.0.1/opcodes/frv-opc.h 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/frv-opc.h 2005-07-20 12:27:28.667966344 -0700 @@ -38,29 +38,30 @@ with this program; if not, write to the /* Vliw support. */ #define FRV_VLIW_SIZE 8 /* fr550 has largest vliw size of 8. */ #define PAD_VLIW_COMBO ,UNIT_NIL,UNIT_NIL,UNIT_NIL,UNIT_NIL + typedef CGEN_ATTR_VALUE_TYPE VLIW_COMBO[FRV_VLIW_SIZE]; typedef struct { - int next_slot; - int constraint_violation; - unsigned long mach; - unsigned long elf_flags; - CGEN_ATTR_VALUE_TYPE *unit_mapping; - VLIW_COMBO *current_vliw; - CGEN_ATTR_VALUE_TYPE major[FRV_VLIW_SIZE]; - const CGEN_INSN* insn[FRV_VLIW_SIZE]; + int next_slot; + int constraint_violation; + unsigned long mach; + unsigned long elf_flags; + CGEN_ATTR_VALUE_TYPE * unit_mapping; + VLIW_COMBO * current_vliw; + CGEN_ATTR_VALUE_TYPE major[FRV_VLIW_SIZE]; + const CGEN_INSN * insn[FRV_VLIW_SIZE]; } FRV_VLIW; -int frv_is_branch_major PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long)); -int frv_is_float_major PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long)); -int frv_is_media_major PARAMS ((CGEN_ATTR_VALUE_TYPE, unsigned long)); -int frv_is_branch_insn PARAMS ((const CGEN_INSN *)); -int frv_is_float_insn PARAMS ((const CGEN_INSN *)); -int frv_is_media_insn PARAMS ((const CGEN_INSN *)); -void frv_vliw_reset PARAMS ((FRV_VLIW *, unsigned long mach, unsigned long elf_flags)); -int frv_vliw_add_insn PARAMS ((FRV_VLIW *, const CGEN_INSN *)); -int spr_valid PARAMS ((long)); +int frv_is_branch_major (CGEN_ATTR_VALUE_TYPE, unsigned long); +int frv_is_float_major (CGEN_ATTR_VALUE_TYPE, unsigned long); +int frv_is_media_major (CGEN_ATTR_VALUE_TYPE, unsigned long); +int frv_is_branch_insn (const CGEN_INSN *); +int frv_is_float_insn (const CGEN_INSN *); +int frv_is_media_insn (const CGEN_INSN *); +void frv_vliw_reset (FRV_VLIW *, unsigned long, unsigned long); +int frv_vliw_add_insn (FRV_VLIW *, const CGEN_INSN *); +int spr_valid (long); /* -- */ /* Enum declaration for frv instruction types. */ typedef enum cgen_insn_type { diff -uprN binutils-2.16.91.0.1/opcodes/h8300-dis.c binutils-2.16.91.0.2/opcodes/h8300-dis.c --- binutils-2.16.91.0.1/opcodes/h8300-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/h8300-dis.c 2005-07-20 12:27:28.669966015 -0700 @@ -1,5 +1,5 @@ /* Disassemble h8300 instructions. - Copyright 1993, 1994, 1996, 1998, 2000, 2001, 2002, 2003, 2004 + Copyright 1993, 1994, 1996, 1998, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify @@ -14,7 +14,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #define DEFINE_TABLE @@ -33,23 +34,11 @@ struct h8_instruction struct h8_instruction *h8_instructions; -static void bfd_h8_disassemble_init PARAMS ((void)); -static void print_one_arg PARAMS ((disassemble_info *, bfd_vma, op_type, - int, int, int, int, const char **, int)); -static unsigned int bfd_h8_disassemble PARAMS ((bfd_vma, - disassemble_info *, - int)); -static void extract_immediate PARAMS ((FILE *, - op_type, int, - unsigned char *, - int *, int *, - const struct h8_opcode *)); - /* Run through the opcodes and sort them into order to make them easy to disassemble. */ static void -bfd_h8_disassemble_init () +bfd_h8_disassemble_init (void) { unsigned int i; unsigned int nopcodes; @@ -58,8 +47,7 @@ bfd_h8_disassemble_init () nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode); - h8_instructions = (struct h8_instruction *) - xmalloc (nopcodes * sizeof (struct h8_instruction)); + h8_instructions = xmalloc (nopcodes * sizeof (struct h8_instruction)); for (p = h8_opcodes, pi = h8_instructions; p->name; p++, pi++) { @@ -97,13 +85,13 @@ bfd_h8_disassemble_init () } static void -extract_immediate (stream, looking_for, thisnib, data, cst, len, q) - FILE *stream; - op_type looking_for; - int thisnib; - unsigned char *data; - int *cst, *len; - const struct h8_opcode *q; +extract_immediate (FILE *stream, + op_type looking_for, + int thisnib, + unsigned char *data, + int *cst, + int *len, + const struct h8_opcode *q) { switch (looking_for & SIZE) { @@ -114,35 +102,37 @@ extract_immediate (stream, looking_for, /* DISP2 special treatment. */ if ((looking_for & MODE) == DISP) { - if (OP_KIND (q->how) == O_MOVAB || - OP_KIND (q->how) == O_MOVAW || - OP_KIND (q->how) == O_MOVAL) + if (OP_KIND (q->how) == O_MOVAB + || OP_KIND (q->how) == O_MOVAW + || OP_KIND (q->how) == O_MOVAL) { /* Handling for mova insn. */ - switch (q->args.nib[0] & MODE) { - case INDEXB: - default: - break; - case INDEXW: - *cst *= 2; - break; - case INDEXL: - *cst *= 4; - break; - } + switch (q->args.nib[0] & MODE) + { + case INDEXB: + default: + break; + case INDEXW: + *cst *= 2; + break; + case INDEXL: + *cst *= 4; + break; + } } else { /* Handling for non-mova insn. */ - switch (OP_SIZE (q->how)) { - default: break; - case SW: - *cst *= 2; - break; - case SL: - *cst *= 4; - break; - } + switch (OP_SIZE (q->how)) + { + default: break; + case SW: + *cst *= 2; + break; + case SL: + *cst *= 4; + break; + } } } break; @@ -156,7 +146,7 @@ extract_immediate (stream, looking_for, *cst = (data[0] << 8) + data [1]; #if 0 if ((looking_for & SIZE) == L_16) - *cst = (short) *cst; /* sign extend */ + *cst = (short) *cst; /* Sign extend. */ #endif break; case L_32: @@ -192,31 +182,25 @@ static const char *cregnames[] = }; static void -print_one_arg (info, addr, x, cst, cstlen, rdisp_n, rn, pregnames, len) - disassemble_info *info; - bfd_vma addr; - op_type x; - int cst, cstlen, rdisp_n, rn; - const char **pregnames; - int len; +print_one_arg (disassemble_info *info, + bfd_vma addr, + op_type x, + int cst, + int cstlen, + int rdisp_n, + int rn, + const char **pregnames, + int len) { - void *stream = info->stream; + void * stream = info->stream; fprintf_ftype outfn = info->fprintf_func; - if ((x & SIZE) == L_3 || - (x & SIZE) == L_3NZ) - { - outfn (stream, "#0x%x", (unsigned) cst); - } + if ((x & SIZE) == L_3 || (x & SIZE) == L_3NZ) + outfn (stream, "#0x%x", (unsigned) cst); else if ((x & MODE) == IMM) - { - outfn (stream, "#0x%x", (unsigned) cst); - } - else if ((x & MODE) == DBIT || - (x & MODE) == KBIT) - { - outfn (stream, "#%d", (unsigned) cst); - } + outfn (stream, "#0x%x", (unsigned) cst); + else if ((x & MODE) == DBIT || (x & MODE) == KBIT) + outfn (stream, "#%d", (unsigned) cst); else if ((x & MODE) == CONST_2) outfn (stream, "#2"); else if ((x & MODE) == CONST_4) @@ -262,33 +246,26 @@ print_one_arg (info, addr, x, cst, cstle } } else if ((x & MODE) == POSTINC) - { - outfn (stream, "@%s+", pregnames[rn]); - } + outfn (stream, "@%s+", pregnames[rn]); + else if ((x & MODE) == POSTDEC) - { - outfn (stream, "@%s-", pregnames[rn]); - } + outfn (stream, "@%s-", pregnames[rn]); + else if ((x & MODE) == PREINC) - { - outfn (stream, "@+%s", pregnames[rn]); - } + outfn (stream, "@+%s", pregnames[rn]); + else if ((x & MODE) == PREDEC) - { - outfn (stream, "@-%s", pregnames[rn]); - } + outfn (stream, "@-%s", pregnames[rn]); + else if ((x & MODE) == IND) - { - outfn (stream, "@%s", pregnames[rn]); - } + outfn (stream, "@%s", pregnames[rn]); + else if ((x & MODE) == ABS || (x & ABSJMP)) - { - outfn (stream, "@0x%x:%d", (unsigned) cst, cstlen); - } + outfn (stream, "@0x%x:%d", (unsigned) cst, cstlen); + else if ((x & MODE) == MEMIND) - { - outfn (stream, "@@%d (0x%x)", cst, cst); - } + outfn (stream, "@@%d (0x%x)", cst, cst); + else if ((x & MODE) == VECIND) { /* FIXME Multiplier should be 2 or 4, depending on processor mode, @@ -302,67 +279,54 @@ print_one_arg (info, addr, x, cst, cstle if ((x & SIZE) == L_16 || (x & SIZE) == L_16U) { - outfn (stream, ".%s%d (0x%x)", + outfn (stream, ".%s%d (0x%lx)", (short) cst > 0 ? "+" : "", (short) cst, - addr + (short) cst + len); + (long)(addr + (short) cst + len)); } else { - outfn (stream, ".%s%d (0x%x)", + outfn (stream, ".%s%d (0x%lx)", (char) cst > 0 ? "+" : "", (char) cst, - addr + (char) cst + len); + (long)(addr + (char) cst + len)); } } else if ((x & MODE) == DISP) - { - outfn (stream, "@(0x%x:%d,%s)", cst, cstlen, - pregnames[rdisp_n]); - } + outfn (stream, "@(0x%x:%d,%s)", cst, cstlen, pregnames[rdisp_n]); + else if ((x & MODE) == INDEXB) - { - /* Always take low half of reg. */ - outfn (stream, "@(0x%x:%d,%s.b)", cst, cstlen, - regnames[rdisp_n < 8 ? rdisp_n + 8 : rdisp_n]); - } + /* Always take low half of reg. */ + outfn (stream, "@(0x%x:%d,%s.b)", cst, cstlen, + regnames[rdisp_n < 8 ? rdisp_n + 8 : rdisp_n]); + else if ((x & MODE) == INDEXW) - { - /* Always take low half of reg. */ - outfn (stream, "@(0x%x:%d,%s.w)", cst, cstlen, - wregnames[rdisp_n < 8 ? rdisp_n : rdisp_n - 8]); - } + /* Always take low half of reg. */ + outfn (stream, "@(0x%x:%d,%s.w)", cst, cstlen, + wregnames[rdisp_n < 8 ? rdisp_n : rdisp_n - 8]); + else if ((x & MODE) == INDEXL) - { - outfn (stream, "@(0x%x:%d,%s.l)", cst, cstlen, - lregnames[rdisp_n]); - } + outfn (stream, "@(0x%x:%d,%s.l)", cst, cstlen, lregnames[rdisp_n]); + else if (x & CTRL) - { - outfn (stream, cregnames[rn]); - } + outfn (stream, cregnames[rn]); + else if ((x & MODE) == CCR) - { - outfn (stream, "ccr"); - } + outfn (stream, "ccr"); + else if ((x & MODE) == EXR) - { - outfn (stream, "exr"); - } + outfn (stream, "exr"); + else if ((x & MODE) == MACREG) - { - outfn (stream, "mac%c", cst ? 'l' : 'h'); - } + outfn (stream, "mac%c", cst ? 'l' : 'h'); + else /* xgettext:c-format */ outfn (stream, _("Hmmmm 0x%x"), x); } static unsigned int -bfd_h8_disassemble (addr, info, mach) - bfd_vma addr; - disassemble_info *info; - int mach; +bfd_h8_disassemble (bfd_vma addr, disassemble_info *info, int mach) { /* Find the first entry in the table for this opcode. */ int regno[3] = { 0, 0, 0 }; @@ -501,12 +465,12 @@ bfd_h8_disassemble (addr, info, mach) cst[opnr] = (thisnib & 0x8) ? 2 : 1; } - else if ((looking_for & MODE) == DISP || - (looking_for & MODE) == ABS || - (looking_for & MODE) == PCREL || - (looking_for & MODE) == INDEXB || - (looking_for & MODE) == INDEXW || - (looking_for & MODE) == INDEXL) + else if ((looking_for & MODE) == DISP + || (looking_for & MODE) == ABS + || (looking_for & MODE) == PCREL + || (looking_for & MODE) == INDEXB + || (looking_for & MODE) == INDEXW + || (looking_for & MODE) == INDEXL) { extract_immediate (stream, looking_for, thisnib, data + len / 2, cst + opnr, @@ -515,36 +479,36 @@ bfd_h8_disassemble (addr, info, mach) if (q->how == O (O_BRAS, SB)) cst[opnr] -= 1; } - else if ((looking_for & MODE) == REG || - (looking_for & MODE) == LOWREG || - (looking_for & MODE) == IND || - (looking_for & MODE) == PREINC || - (looking_for & MODE) == POSTINC || - (looking_for & MODE) == PREDEC || - (looking_for & MODE) == POSTDEC) + else if ((looking_for & MODE) == REG + || (looking_for & MODE) == LOWREG + || (looking_for & MODE) == IND + || (looking_for & MODE) == PREINC + || (looking_for & MODE) == POSTINC + || (looking_for & MODE) == PREDEC + || (looking_for & MODE) == POSTDEC) { regno[opnr] = thisnib; } - else if (looking_for & CTRL) /* Control Register */ + else if (looking_for & CTRL) /* Control Register. */ { thisnib &= 7; - if (((looking_for & MODE) == CCR && (thisnib != C_CCR)) || - ((looking_for & MODE) == EXR && (thisnib != C_EXR)) || - ((looking_for & MODE) == MACH && (thisnib != C_MACH)) || - ((looking_for & MODE) == MACL && (thisnib != C_MACL)) || - ((looking_for & MODE) == VBR && (thisnib != C_VBR)) || - ((looking_for & MODE) == SBR && (thisnib != C_SBR))) - goto fail; - if (((looking_for & MODE) == CCR_EXR && - (thisnib != C_CCR && thisnib != C_EXR)) || - ((looking_for & MODE) == VBR_SBR && - (thisnib != C_VBR && thisnib != C_SBR)) || - ((looking_for & MODE) == MACREG && - (thisnib != C_MACH && thisnib != C_MACL))) - goto fail; - if (((looking_for & MODE) == CC_EX_VB_SB && - (thisnib != C_CCR && thisnib != C_EXR && - thisnib != C_VBR && thisnib != C_SBR))) + if (((looking_for & MODE) == CCR && (thisnib != C_CCR)) + || ((looking_for & MODE) == EXR && (thisnib != C_EXR)) + || ((looking_for & MODE) == MACH && (thisnib != C_MACH)) + || ((looking_for & MODE) == MACL && (thisnib != C_MACL)) + || ((looking_for & MODE) == VBR && (thisnib != C_VBR)) + || ((looking_for & MODE) == SBR && (thisnib != C_SBR))) + goto fail; + if (((looking_for & MODE) == CCR_EXR + && (thisnib != C_CCR && thisnib != C_EXR)) + || ((looking_for & MODE) == VBR_SBR + && (thisnib != C_VBR && thisnib != C_SBR)) + || ((looking_for & MODE) == MACREG + && (thisnib != C_MACH && thisnib != C_MACL))) + goto fail; + if (((looking_for & MODE) == CC_EX_VB_SB + && (thisnib != C_CCR && thisnib != C_EXR + && thisnib != C_VBR && thisnib != C_SBR))) goto fail; regno[opnr] = thisnib; @@ -559,8 +523,8 @@ bfd_h8_disassemble (addr, info, mach) cst[opnr] = thisnib; cstlen[opnr] = 4; } - else if ((looking_for & SIZE) == L_16 || - (looking_for & SIZE) == L_16U) + else if ((looking_for & SIZE) == L_16 + || (looking_for & SIZE) == L_16U) { cst[opnr] = (data[len / 2]) * 256 + data[(len + 2) / 2]; cstlen[opnr] = 16; @@ -622,8 +586,8 @@ bfd_h8_disassemble (addr, info, mach) cstlen[opnr] = 8; cst[opnr] = data[len / 2]; } - else if ((looking_for & SIZE) == L_3 || - (looking_for & SIZE) == L_3NZ) + else if ((looking_for & SIZE) == L_3 + || (looking_for & SIZE) == L_3NZ) { cst[opnr] = thisnib & 0x7; if (cst[opnr] == 0 && (looking_for & SIZE) == L_3NZ) @@ -670,10 +634,8 @@ bfd_h8_disassemble (addr, info, mach) if (regno[0] == 0) outfn (stream, "er%d", regno[1]); else - { - outfn (stream, "er%d-er%d", regno[1] - regno[0], - regno[1]); - } + outfn (stream, "er%d-er%d", regno[1] - regno[0], + regno[1]); return qi->length; } if (strncmp (q->name, "mova", 4) == 0) @@ -709,9 +671,9 @@ bfd_h8_disassemble (addr, info, mach) int nargs; /* Special case handling for the adds and subs instructions - since in H8 mode thay can only take the r0-r7 registers but - in other (higher) modes they can take the er0-er7 registers - as well. */ + since in H8 mode thay can only take the r0-r7 registers + but in other (higher) modes they can take the er0-er7 + registers as well. */ if (strcmp (qi->opcode->name, "adds") == 0 || strcmp (qi->opcode->name, "subs") == 0) { @@ -720,7 +682,7 @@ bfd_h8_disassemble (addr, info, mach) } for (nargs = 0; - nargs < 3 && args[nargs] != (op_type) E; + nargs < 3 && args[nargs] != (op_type) E; nargs++) { int x = args[nargs]; @@ -758,25 +720,19 @@ bfd_h8_disassemble (addr, info, mach) } int -print_insn_h8300 (addr, info) - bfd_vma addr; - disassemble_info *info; +print_insn_h8300 (bfd_vma addr, disassemble_info *info) { return bfd_h8_disassemble (addr, info, 0); } int -print_insn_h8300h (addr, info) - bfd_vma addr; - disassemble_info *info; +print_insn_h8300h (bfd_vma addr, disassemble_info *info) { return bfd_h8_disassemble (addr, info, 1); } int -print_insn_h8300s (addr, info) - bfd_vma addr; - disassemble_info *info; +print_insn_h8300s (bfd_vma addr, disassemble_info *info) { return bfd_h8_disassemble (addr, info, 2); } diff -uprN binutils-2.16.91.0.1/opcodes/h8500-dis.c binutils-2.16.91.0.2/opcodes/h8500-dis.c --- binutils-2.16.91.0.1/opcodes/h8500-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/h8500-dis.c 2005-07-20 12:27:28.670965850 -0700 @@ -1,5 +1,6 @@ /* Disassemble h8500 instructions. - Copyright 1993, 1998, 2000, 2001, 2002, 2004 Free Software Foundation, Inc. + Copyright 1993, 1998, 2000, 2001, 2002, 2004, 2005 + Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -13,7 +14,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include @@ -30,8 +32,6 @@ #include -static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *)); - struct private { /* Points to first byte not fetched. */ @@ -49,9 +49,7 @@ struct private ? 1 : fetch_data ((info), (addr))) static int -fetch_data (info, addr) - struct disassemble_info *info; - bfd_byte *addr; +fetch_data (struct disassemble_info *info, bfd_byte *addr) { int status; struct private *priv = (struct private *) info->private_data; @@ -74,14 +72,11 @@ fetch_data (info, addr) static char *crname[] = { "sr", "ccr", "*", "br", "ep", "dp", "*", "tp" }; int -print_insn_h8500 (addr, info) - bfd_vma addr; - disassemble_info *info; +print_insn_h8500 (bfd_vma addr, disassemble_info *info) { const h8500_opcode_info *opcode; void *stream = info->stream; fprintf_ftype func = info->fprintf_func; - struct private priv; bfd_byte *buffer = priv.the_buffer; @@ -92,21 +87,6 @@ print_insn_h8500 (addr, info) /* Error return. */ return -1; - if (0) - { - static int one; - - if (!one) - { - one = 1; - for (opcode = h8500_table; opcode->name; opcode++) - { - if ((opcode->bytes[0].contents & 0x8) == 0) - printf ("%s\n", opcode->name); - } - } - } - /* Run down the table to find the one which matches. */ for (opcode = h8500_table; opcode->name; opcode++) { @@ -127,9 +107,8 @@ print_insn_h8500 (addr, info) FETCH_DATA (info, buffer + byte + 1); if ((buffer[byte] & opcode->bytes[byte].mask) != (opcode->bytes[byte].contents)) - { - goto next; - } + goto next; + else { /* Extract any info parts. */ @@ -250,7 +229,7 @@ print_insn_h8500 (addr, info) func (stream, "@(0x%x:8 (%d), r%d)", disp & 0xff, disp, rd); break; case FPIND_D8: - func (stream, "@(0x%x:8 (%d), fp)", disp & 0xff, disp, rn); + func (stream, "@(0x%x:8 (%d), fp)", disp & 0xff, disp); break; case CRB: case CRW: @@ -299,6 +278,7 @@ print_insn_h8500 (addr, info) { int i; int nc = 0; + func (stream, "("); for (i = 0; i < 8; i++) { @@ -318,11 +298,11 @@ print_insn_h8500 (addr, info) break; case PCREL16: func (stream, "0x%0x:16", - (pcrel + addr + opcode->length) & 0xffff); + (int)(pcrel + addr + opcode->length) & 0xffff); break; case PCREL8: func (stream, "#0x%0x:8", - ((char) pcrel + addr + opcode->length) & 0xffff); + (int)((char) pcrel + addr + opcode->length) & 0xffff); break; case QIM: func (stream, "#%d:q", qim); diff -uprN binutils-2.16.91.0.1/opcodes/hppa-dis.c binutils-2.16.91.0.2/opcodes/hppa-dis.c --- binutils-2.16.91.0.1/opcodes/hppa-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/hppa-dis.c 2005-07-20 12:27:28.672965520 -0700 @@ -1,23 +1,24 @@ /* Disassembler for the PA-RISC. Somewhat derived from sparc-pinsn.c. - Copyright 1989, 1990, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2003 - Free Software Foundation, Inc. + Copyright 1989, 1990, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2003, + 2005 Free Software Foundation, Inc. Contributed by the Center for Software Science at the University of Utah (pa-gdb-bugs@cs.utah.edu). -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "sysdep.h" #include "dis-asm.h" @@ -27,32 +28,36 @@ Foundation, Inc., 51 Franklin Street - F /* Integer register names, indexed by the numbers which appear in the opcodes. */ static const char *const reg_names[] = - {"flags", "r1", "rp", "r3", "r4", "r5", "r6", "r7", "r8", "r9", +{ + "flags", "r1", "rp", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26", "dp", "ret0", "ret1", - "sp", "r31"}; + "sp", "r31" +}; /* Floating point register names, indexed by the numbers which appear in the opcodes. */ static const char *const fp_reg_names[] = - {"fpsr", "fpe2", "fpe4", "fpe6", +{ + "fpsr", "fpe2", "fpe4", "fpe6", "fr4", "fr5", "fr6", "fr7", "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", - "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31"}; + "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31" +}; typedef unsigned int CORE_ADDR; /* Get at various relevent fields of an instruction word. */ -#define MASK_5 0x1f +#define MASK_5 0x1f #define MASK_10 0x3ff #define MASK_11 0x7ff #define MASK_14 0x3fff #define MASK_16 0xffff #define MASK_21 0x1fffff -/* These macros get bit fields using HP's numbering (MSB = 0) */ +/* These macros get bit fields using HP's numbering (MSB = 0). */ #define GET_FIELD(X, FROM, TO) \ ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) @@ -63,7 +68,8 @@ typedef unsigned int CORE_ADDR; /* Some of these have been converted to 2-d arrays because they consume less storage this way. If the maintenance becomes a problem, convert them back to const 1-d pointer arrays. */ -static const char *const control_reg[] = { +static const char *const control_reg[] = +{ "rctr", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", "pidr1", "pidr2", "ccr", "sar", "pidr3", "pidr4", "iva", "eiem", "itmr", "pcsq", "pcoq", "iir", "isr", @@ -71,55 +77,69 @@ static const char *const control_reg[] = "tr4", "tr5", "tr6", "tr7" }; -static const char *const compare_cond_names[] = { +static const char *const compare_cond_names[] = +{ "", ",=", ",<", ",<=", ",<<", ",<<=", ",sv", ",od", ",tr", ",<>", ",>=", ",>", ",>>=", ",>>", ",nsv", ",ev" }; -static const char *const compare_cond_64_names[] = { +static const char *const compare_cond_64_names[] = +{ "", ",*=", ",*<", ",*<=", ",*<<", ",*<<=", ",*sv", ",*od", ",*tr", ",*<>", ",*>=", ",*>", ",*>>=", ",*>>", ",*nsv", ",*ev" }; -static const char *const cmpib_cond_64_names[] = { +static const char *const cmpib_cond_64_names[] = +{ ",*<<", ",*=", ",*<", ",*<=", ",*>>=", ",*<>", ",*>=", ",*>" }; -static const char *const add_cond_names[] = { +static const char *const add_cond_names[] = +{ "", ",=", ",<", ",<=", ",nuv", ",znv", ",sv", ",od", ",tr", ",<>", ",>=", ",>", ",uv", ",vnz", ",nsv", ",ev" }; -static const char *const add_cond_64_names[] = { +static const char *const add_cond_64_names[] = +{ "", ",*=", ",*<", ",*<=", ",*nuv", ",*znv", ",*sv", ",*od", ",*tr", ",*<>", ",*>=", ",*>", ",*uv", ",*vnz", ",*nsv", ",*ev" }; -static const char *const wide_add_cond_names[] = { +static const char *const wide_add_cond_names[] = +{ "", ",=", ",<", ",<=", ",nuv", ",*=", ",*<", ",*<=", ",tr", ",<>", ",>=", ",>", ",uv", ",*<>", ",*>=", ",*>" }; -static const char *const logical_cond_names[] = { +static const char *const logical_cond_names[] = +{ "", ",=", ",<", ",<=", 0, 0, 0, ",od", ",tr", ",<>", ",>=", ",>", 0, 0, 0, ",ev"}; -static const char *const logical_cond_64_names[] = { +static const char *const logical_cond_64_names[] = +{ "", ",*=", ",*<", ",*<=", 0, 0, 0, ",*od", ",*tr", ",*<>", ",*>=", ",*>", 0, 0, 0, ",*ev"}; -static const char *const unit_cond_names[] = { +static const char *const unit_cond_names[] = +{ "", ",swz", ",sbz", ",shz", ",sdc", ",swc", ",sbc", ",shc", ",tr", ",nwz", ",nbz", ",nhz", ",ndc", ",nwc", ",nbc", ",nhc" }; -static const char *const unit_cond_64_names[] = { +static const char *const unit_cond_64_names[] = +{ "", ",*swz", ",*sbz", ",*shz", ",*sdc", ",*swc", ",*sbc", ",*shc", ",*tr", ",*nwz", ",*nbz", ",*nhz", ",*ndc", ",*nwc", ",*nbc", ",*nhc" }; -static const char *const shift_cond_names[] = { +static const char *const shift_cond_names[] = +{ "", ",=", ",<", ",od", ",tr", ",<>", ",>=", ",ev" }; -static const char *const shift_cond_64_names[] = { +static const char *const shift_cond_64_names[] = +{ "", ",*=", ",*<", ",*od", ",*tr", ",*<>", ",*>=", ",*ev" }; -static const char *const bb_cond_64_names[] = { +static const char *const bb_cond_64_names[] = +{ ",*<", ",*>=" }; static const char *const index_compl_names[] = {"", ",m", ",s", ",sm"}; static const char *const short_ldst_compl_names[] = {"", ",ma", "", ",mb"}; -static const char *const short_bytes_compl_names[] = { +static const char *const short_bytes_compl_names[] = +{ "", ",b,m", ",e", ",e,m" }; static const char *const float_format_names[] = {",sgl", ",dbl", "", ",quad"}; @@ -146,51 +166,25 @@ static const char *const add_compl_names #define GET_COND(insn) (GET_FIELD ((insn), 16, 18) + \ (GET_FIELD ((insn), 19, 19) ? 8 : 0)) -static void fput_reg PARAMS ((unsigned int, disassemble_info *)); -static void fput_fp_reg PARAMS ((unsigned int, disassemble_info *)); -static void fput_fp_reg_r PARAMS ((unsigned int, disassemble_info *)); -static void fput_creg PARAMS ((unsigned int, disassemble_info *)); -static void fput_const PARAMS ((unsigned int, disassemble_info *)); -static int extract_3 PARAMS ((unsigned int)); -static int extract_5_load PARAMS ((unsigned int)); -static int extract_5_store PARAMS ((unsigned int)); -static unsigned extract_5r_store PARAMS ((unsigned int)); -static unsigned extract_5R_store PARAMS ((unsigned int)); -static unsigned extract_10U_store PARAMS ((unsigned int)); -static unsigned extract_5Q_store PARAMS ((unsigned int)); -static int extract_11 PARAMS ((unsigned int)); -static int extract_14 PARAMS ((unsigned int)); -static int extract_16 PARAMS ((unsigned int)); -static int extract_21 PARAMS ((unsigned int)); -static int extract_12 PARAMS ((unsigned int)); -static int extract_17 PARAMS ((unsigned int)); -static int extract_22 PARAMS ((unsigned int)); - /* Utility function to print registers. Put these first, so gcc's function inlining can do its stuff. */ #define fputs_filtered(STR,F) (*info->fprintf_func) (info->stream, "%s", STR) static void -fput_reg (reg, info) - unsigned reg; - disassemble_info *info; +fput_reg (unsigned reg, disassemble_info *info) { (*info->fprintf_func) (info->stream, reg ? reg_names[reg] : "r0"); } static void -fput_fp_reg (reg, info) - unsigned reg; - disassemble_info *info; +fput_fp_reg (unsigned reg, disassemble_info *info) { (*info->fprintf_func) (info->stream, reg ? fp_reg_names[reg] : "fr0"); } static void -fput_fp_reg_r (reg, info) - unsigned reg; - disassemble_info *info; +fput_fp_reg_r (unsigned reg, disassemble_info *info) { /* Special case floating point exception registers. */ if (reg < 4) @@ -201,9 +195,7 @@ fput_fp_reg_r (reg, info) } static void -fput_creg (reg, info) - unsigned reg; - disassemble_info *info; +fput_creg (unsigned reg, disassemble_info *info) { (*info->fprintf_func) (info->stream, control_reg[reg]); } @@ -211,12 +203,10 @@ fput_creg (reg, info) /* Print constants with sign. */ static void -fput_const (num, info) - unsigned num; - disassemble_info *info; +fput_const (unsigned num, disassemble_info *info) { - if ((int)num < 0) - (*info->fprintf_func) (info->stream, "-%x", -(int)num); + if ((int) num < 0) + (*info->fprintf_func) (info->stream, "-%x", - (int) num); else (*info->fprintf_func) (info->stream, "%x", num); } @@ -226,81 +216,80 @@ fput_const (num, info) /* Extract a 3-bit space register number from a be, ble, mtsp or mfsp. */ static int -extract_3 (word) - unsigned word; +extract_3 (unsigned word) { return GET_FIELD (word, 18, 18) << 2 | GET_FIELD (word, 16, 17); } static int -extract_5_load (word) - unsigned word; +extract_5_load (unsigned word) { return low_sign_extend (word >> 16 & MASK_5, 5); } /* Extract the immediate field from a st{bhw}s instruction. */ + static int -extract_5_store (word) - unsigned word; +extract_5_store (unsigned word) { return low_sign_extend (word & MASK_5, 5); } /* Extract the immediate field from a break instruction. */ + static unsigned -extract_5r_store (word) - unsigned word; +extract_5r_store (unsigned word) { return (word & MASK_5); } /* Extract the immediate field from a {sr}sm instruction. */ + static unsigned -extract_5R_store (word) - unsigned word; +extract_5R_store (unsigned word) { return (word >> 16 & MASK_5); } /* Extract the 10 bit immediate field from a {sr}sm instruction. */ + static unsigned -extract_10U_store (word) - unsigned word; +extract_10U_store (unsigned word) { return (word >> 16 & MASK_10); } /* Extract the immediate field from a bb instruction. */ + static unsigned -extract_5Q_store (word) - unsigned word; +extract_5Q_store (unsigned word) { return (word >> 21 & MASK_5); } /* Extract an 11 bit immediate field. */ + static int -extract_11 (word) - unsigned word; +extract_11 (unsigned word) { return low_sign_extend (word & MASK_11, 11); } /* Extract a 14 bit immediate field. */ + static int -extract_14 (word) - unsigned word; +extract_14 (unsigned word) { return low_sign_extend (word & MASK_14, 14); } /* Extract a 16 bit immediate field (PA2.0 wide only). */ + static int -extract_16 (word) - unsigned word; +extract_16 (unsigned word) { int m15, m0, m1; + m0 = GET_BIT (word, 16); m1 = GET_BIT (word, 17); m15 = GET_BIT (word, 31); @@ -312,8 +301,7 @@ extract_16 (word) /* Extract a 21 bit constant. */ static int -extract_21 (word) - unsigned word; +extract_21 (unsigned word) { int val; @@ -334,43 +322,39 @@ extract_21 (word) /* Extract a 12 bit constant from branch instructions. */ static int -extract_12 (word) - unsigned word; +extract_12 (unsigned word) { - return sign_extend (GET_FIELD (word, 19, 28) | - GET_FIELD (word, 29, 29) << 10 | - (word & 0x1) << 11, 12) << 2; + return sign_extend (GET_FIELD (word, 19, 28) + | GET_FIELD (word, 29, 29) << 10 + | (word & 0x1) << 11, 12) << 2; } /* Extract a 17 bit constant from branch instructions, returning the 19 bit signed value. */ static int -extract_17 (word) - unsigned word; +extract_17 (unsigned word) { - return sign_extend (GET_FIELD (word, 19, 28) | - GET_FIELD (word, 29, 29) << 10 | - GET_FIELD (word, 11, 15) << 11 | - (word & 0x1) << 16, 17) << 2; + return sign_extend (GET_FIELD (word, 19, 28) + | GET_FIELD (word, 29, 29) << 10 + | GET_FIELD (word, 11, 15) << 11 + | (word & 0x1) << 16, 17) << 2; } static int -extract_22 (word) - unsigned word; +extract_22 (unsigned word) { - return sign_extend (GET_FIELD (word, 19, 28) | - GET_FIELD (word, 29, 29) << 10 | - GET_FIELD (word, 11, 15) << 11 | - GET_FIELD (word, 6, 10) << 16 | - (word & 0x1) << 21, 22) << 2; + return sign_extend (GET_FIELD (word, 19, 28) + | GET_FIELD (word, 29, 29) << 10 + | GET_FIELD (word, 11, 15) << 11 + | GET_FIELD (word, 6, 10) << 16 + | (word & 0x1) << 21, 22) << 2; } /* Print one instruction. */ + int -print_insn_hppa (memaddr, info) - bfd_vma memaddr; - disassemble_info *info; +print_insn_hppa (bfd_vma memaddr, disassemble_info *info) { bfd_byte buffer[4]; unsigned int insn, i; @@ -390,9 +374,10 @@ print_insn_hppa (memaddr, info) for (i = 0; i < NUMOPCODES; ++i) { const struct pa_opcode *opcode = &pa_opcodes[i]; + if ((insn & opcode->mask) == opcode->match) { - register const char *s; + const char *s; #ifndef BFD64 if (opcode->arch == pa20w) continue; @@ -633,7 +618,7 @@ print_insn_hppa (memaddr, info) read_write_names[GET_FIELD (insn, 25, 25)]); break; case 'W': - (*info->fprintf_func) (info->stream, ",w"); + (*info->fprintf_func) (info->stream, ",w "); break; case 'r': if (GET_FIELD (insn, 23, 26) == 5) @@ -789,10 +774,10 @@ print_insn_hppa (memaddr, info) float_comp_names[GET_FIELD (insn, 27, 31)]); break; - /* these four conditions are for the set of instructions + /* These four conditions are for the set of instructions which distinguish true/false conditions by opcode rather than by the 'f' bit (sigh): comb, comib, - addb, addib */ + addb, addib. */ case 't': fputs_filtered (compare_cond_names[GET_FIELD (insn, 16, 18)], info); @@ -1070,8 +1055,8 @@ print_insn_hppa (memaddr, info) GET_FIELD (insn, 23, 25)); break; case 'F': - /* if no destination completer and not before a completer - for fcmp, need a space here */ + /* If no destination completer and not before a completer + for fcmp, need a space here. */ if (s[1] == 'G' || s[1] == '?') fputs_filtered (float_format_names[GET_FIELD (insn, 19, 20)], info); @@ -1094,8 +1079,8 @@ print_insn_hppa (memaddr, info) float_format_names[1]); break; case 'I': - /* if no destination completer and not before a completer - for fcmp, need a space here */ + /* If no destination completer and not before a completer + for fcmp, need a space here. */ if (s[1] == '?') fputs_filtered (float_format_names[GET_FIELD (insn, 20, 20)], info); @@ -1171,6 +1156,7 @@ print_insn_hppa (memaddr, info) const char * const * source = float_format_names; const char * const * dest = float_format_names; char *t = ""; + if (sub == 4) { fputs_filtered (",UND ", info); @@ -1212,22 +1198,18 @@ print_insn_hppa (memaddr, info) { int cond = GET_FIELD (insn, 27, 31); - if (cond == 0) - fputs_filtered (" ", info); - else if (cond == 1) - fputs_filtered ("acc ", info); - else if (cond == 2) - fputs_filtered ("rej ", info); - else if (cond == 5) - fputs_filtered ("acc8 ", info); - else if (cond == 6) - fputs_filtered ("rej8 ", info); - else if (cond == 9) - fputs_filtered ("acc6 ", info); - else if (cond == 13) - fputs_filtered ("acc4 ", info); - else if (cond == 17) - fputs_filtered ("acc2 ", info); + switch (cond) + { + case 0: fputs_filtered (" ", info); break; + case 1: fputs_filtered ("acc ", info); break; + case 2: fputs_filtered ("rej ", info); break; + case 5: fputs_filtered ("acc8 ", info); break; + case 6: fputs_filtered ("rej8 ", info); break; + case 9: fputs_filtered ("acc6 ", info); break; + case 13: fputs_filtered ("acc4 ", info); break; + case 17: fputs_filtered ("acc2 ", info); break; + default: break; + } break; } @@ -1243,9 +1225,9 @@ print_insn_hppa (memaddr, info) break; } } - return sizeof(insn); + return sizeof (insn); } } (*info->fprintf_func) (info->stream, "#%8x", insn); - return sizeof(insn); + return sizeof (insn); } diff -uprN binutils-2.16.91.0.1/opcodes/i370-dis.c binutils-2.16.91.0.2/opcodes/i370-dis.c --- binutils-2.16.91.0.1/opcodes/i370-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/i370-dis.c 2005-07-20 12:27:28.673965355 -0700 @@ -1,23 +1,24 @@ /* i370-dis.c -- Disassemble Instruction 370 (ESA/390) instructions - Copyright 1994, 2000, 2003 Free Software Foundation, Inc. + Copyright 1994, 2000, 2003, 2005 Free Software Foundation, Inc. PowerPC version written by Ian Lance Taylor, Cygnus Support Rewritten for i370 ESA/390 support by Linas Vepstas -This file is part of GDB, GAS, and the GNU binutils. + This file is part of GDB, GAS, and the GNU binutils. -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -2, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include #include "sysdep.h" @@ -25,8 +26,7 @@ Software Foundation, 51 Franklin Street #include "opcode/i370.h" /* This file provides several disassembler functions, all of which use - the disassembler interface defined in dis-asm.h. -*/ + the disassembler interface defined in dis-asm.h. */ int print_insn_i370 (bfd_vma memaddr, struct disassemble_info *info) @@ -44,7 +44,7 @@ print_insn_i370 (bfd_vma memaddr, struct return -1; } - /* Cast the bytes into the insn (in a host-endian indep way) */ + /* Cast the bytes into the insn (in a host-endian indep way). */ insn.i[0] = (buffer[0] << 24) & 0xff000000; insn.i[0] |= (buffer[1] << 16) & 0xff0000; insn.i[0] |= (buffer[2] << 8) & 0xff00; @@ -70,15 +70,17 @@ print_insn_i370 (bfd_vma memaddr, struct masked.i[0] &= 0xffff; } masked.i[0] &= opcode->mask.i[0]; - if (masked.i[0] != opcode->opcode.i[0]) continue; + if (masked.i[0] != opcode->opcode.i[0]) + continue; if (6 == opcode->len) { masked.i[1] &= opcode->mask.i[1]; - if (masked.i[1] != opcode->opcode.i[1]) continue; + if (masked.i[1] != opcode->opcode.i[1]) + continue; } - /* Found a match. adjust a tad */ + /* Found a match. adjust a tad. */ if (2 == opcode->len) { insn.i[0] >>= 16; @@ -95,7 +97,8 @@ print_insn_i370 (bfd_vma memaddr, struct if (operand->extract) (*operand->extract) (insn, &invalid); } - if (invalid) continue; + if (invalid) + continue; /* The instruction is valid. */ (*info->fprintf_func) (info->stream, "%s", opcode->name); @@ -113,9 +116,7 @@ print_insn_i370 (bfd_vma memaddr, struct if (operand->extract) value = (*operand->extract) (insn, (int *) NULL); else - { - value = (insn.i[0] >> operand->shift) & ((1 << operand->bits) - 1); - } + value = (insn.i[0] >> operand->shift) & ((1 << operand->bits) - 1); /* Print the operand as directed by the flags. */ if ((operand->flags & I370_OPERAND_OPTIONAL) != 0) @@ -148,14 +149,11 @@ print_insn_i370 (bfd_vma memaddr, struct (*info->fprintf_func) (info->stream, "%ld", value); else (*info->fprintf_func) (info->stream, " %ld, ", value); - } return opcode->len; - } - /* We could not find a match. */ (*info->fprintf_func) (info->stream, ".short 0x%02x%02x", buffer[0], buffer[1]); diff -uprN binutils-2.16.91.0.1/opcodes/i370-opc.c binutils-2.16.91.0.2/opcodes/i370-opc.c --- binutils-2.16.91.0.1/opcodes/i370-opc.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/i370-opc.c 2005-07-20 12:27:28.676964860 -0700 @@ -1,24 +1,24 @@ /* i370-opc.c -- Instruction 370 (ESA/390) architecture opcode list - Copyright 1994, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. + Copyright 1994, 1999, 2000, 2001, 2003, 2005 Free Software Foundation, Inc. PowerPC version written by Ian Lance Taylor, Cygnus Support Rewritten for i370 ESA/390 support by Linas Vepstas 1998, 1999 -This file is part of GDB, GAS, and the GNU binutils. + This file is part of GDB, GAS, and the GNU binutils. -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -2, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA -02110-1301, USA. */ + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ #include #include "sysdep.h" @@ -35,14 +35,49 @@ Software Foundation, 51 Franklin Street inserting operands into instructions and vice-versa is kept in this file. */ -/* Local insertion and extraction functions. */ -static i370_insn_t insert_ss_b2 (i370_insn_t, long, const char **); -static i370_insn_t insert_ss_d2 (i370_insn_t, long, const char **); -static i370_insn_t insert_rxf_r3 (i370_insn_t, long, const char **); -static long extract_ss_b2 (i370_insn_t, int *); -static long extract_ss_d2 (i370_insn_t, int *); -static long extract_rxf_r3 (i370_insn_t, int *); +/* The functions used to insert and extract complicated operands. */ + +static i370_insn_t +insert_ss_b2 (i370_insn_t insn, long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + insn.i[1] |= (value & 0xf) << 28; + return insn; +} + +static i370_insn_t +insert_ss_d2 (i370_insn_t insn, long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + insn.i[1] |= (value & 0xfff) << 16; + return insn; +} + +static i370_insn_t +insert_rxf_r3 (i370_insn_t insn, long value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + insn.i[1] |= (value & 0xf) << 28; + return insn; +} + +static long +extract_ss_b2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED) +{ + return (insn.i[1] >>28) & 0xf; +} + +static long +extract_ss_d2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED) +{ + return (insn.i[1] >>16) & 0xfff; +} +static long +extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED) +{ + return (insn.i[1] >>28) & 0xf; +} /* The operands table. The fields are bits, shift, insert, extract, flags, name. @@ -53,8 +88,7 @@ static long extract_rxf_r3 (i370_insn_t, if absent, should take value of zero I370_OPERAND_INDEX index register; if present, must name a register if absent, should take value of zero - I370_OPERAND_OPTIONAL other optional operand (usuall reg?) -*/ + I370_OPERAND_OPTIONAL other optional operand (usuall reg?). */ const struct i370_operand i370_operands[] = { @@ -223,180 +257,135 @@ const struct i370_operand i370_operands[ #define SS_D2 (SS_B2 + 1) #define SS_D2_MASK (0xfff) { 12, 0, insert_ss_d2, extract_ss_d2, I370_OPERAND_RELATIVE, "SS D2" }, - - + }; -/* The functions used to insert and extract complicated operands. */ - -static i370_insn_t -insert_ss_b2 (i370_insn_t insn, long value, - const char **errmsg ATTRIBUTE_UNUSED) -{ - insn.i[1] |= (value & 0xf) << 28; - return insn; -} - -static i370_insn_t -insert_ss_d2 (i370_insn_t insn, long value, - const char **errmsg ATTRIBUTE_UNUSED) -{ - insn.i[1] |= (value & 0xfff) << 16; - return insn; -} - -static i370_insn_t -insert_rxf_r3 (i370_insn_t insn, long value, - const char **errmsg ATTRIBUTE_UNUSED) -{ - insn.i[1] |= (value & 0xf) << 28; - return insn; -} - -static long -extract_ss_b2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED) -{ - return (insn.i[1] >>28) & 0xf; -} - -static long -extract_ss_d2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED) -{ - return (insn.i[1] >>16) & 0xfff; -} - -static long -extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED) -{ - return (insn.i[1] >>28) & 0xf; -} - /* Macros used to form opcodes. */ /* The short-instruction opcode. */ -#define OPS(x) ((((unsigned short)(x)) & 0xff) << 8) +#define OPS(x) ((((unsigned short) (x)) & 0xff) << 8) #define OPS_MASK OPS (0xff) /* the extended instruction opcode */ -#define XOPS(x) ((((unsigned short)(x)) & 0xff) << 24) +#define XOPS(x) ((((unsigned short) (x)) & 0xff) << 24) #define XOPS_MASK XOPS (0xff) /* the S instruction opcode */ -#define SOPS(x) ((((unsigned short)(x)) & 0xffff) << 16) +#define SOPS(x) ((((unsigned short) (x)) & 0xffff) << 16) #define SOPS_MASK SOPS (0xffff) /* the E instruction opcode */ -#define EOPS(x) (((unsigned short)(x)) & 0xffff) +#define EOPS(x) (((unsigned short) (x)) & 0xffff) #define EOPS_MASK EOPS (0xffff) /* the RI instruction opcode */ -#define ROPS(x) (((((unsigned short)(x)) & 0xff0) << 20) | \ - ((((unsigned short)(x)) & 0x00f) << 16)) +#define ROPS(x) (((((unsigned short) (x)) & 0xff0) << 20) | \ + ((((unsigned short) (x)) & 0x00f) << 16)) #define ROPS_MASK ROPS (0xfff) -/* --------------------------------------------------------- */ + /* An E form instruction. */ #define E(op) (EOPS (op)) #define E_MASK E (0xffff) /* An RR form instruction. */ #define RR(op, r1, r2) \ - (OPS (op) | ((((unsigned short)(r1)) & 0xf) << 4) | \ - ((((unsigned short)(r2)) & 0xf) )) + (OPS (op) | ((((unsigned short) (r1)) & 0xf) << 4) | \ + ((((unsigned short) (r2)) & 0xf) )) #define RR_MASK RR (0xff, 0x0, 0x0) /* An SVC-style instruction. */ #define SVC(op, i) \ - (OPS (op) | (((unsigned short)(i)) & 0xff)) + (OPS (op) | (((unsigned short) (i)) & 0xff)) #define SVC_MASK SVC (0xff, 0x0) /* An RRE form instruction. */ #define RRE(op, r1, r2) \ - (SOPS (op) | ((((unsigned short)(r1)) & 0xf) << 4) | \ - ((((unsigned short)(r2)) & 0xf) )) + (SOPS (op) | ((((unsigned short) (r1)) & 0xf) << 4) | \ + ((((unsigned short) (r2)) & 0xf) )) #define RRE_MASK RRE (0xffff, 0x0, 0x0) /* An RRF form instruction. */ #define RRF(op, r3, r1, r2) \ - (SOPS (op) | ((((unsigned short)(r3)) & 0xf) << 12) | \ - ((((unsigned short)(r1)) & 0xf) << 4) | \ - ((((unsigned short)(r2)) & 0xf) )) + (SOPS (op) | ((((unsigned short) (r3)) & 0xf) << 12) | \ + ((((unsigned short) (r1)) & 0xf) << 4) | \ + ((((unsigned short) (r2)) & 0xf) )) #define RRF_MASK RRF (0xffff, 0x0, 0x0, 0x0) /* An RX form instruction. */ #define RX(op, r1, x2, b2, d2) \ - (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \ - ((((unsigned short)(x2)) & 0xf) << 16) | \ - ((((unsigned short)(b2)) & 0xf) << 12) | \ - ((((unsigned short)(d2)) & 0xfff))) + (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ + ((((unsigned short) (x2)) & 0xf) << 16) | \ + ((((unsigned short) (b2)) & 0xf) << 12) | \ + ((((unsigned short) (d2)) & 0xfff))) #define RX_MASK RX (0xff, 0x0, 0x0, 0x0, 0x0) /* An RXE form instruction high word. */ #define RXEH(op, r1, x2, b2, d2) \ - (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \ - ((((unsigned short)(x2)) & 0xf) << 16) | \ - ((((unsigned short)(b2)) & 0xf) << 12) | \ - ((((unsigned short)(d2)) & 0xfff))) + (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ + ((((unsigned short) (x2)) & 0xf) << 16) | \ + ((((unsigned short) (b2)) & 0xf) << 12) | \ + ((((unsigned short) (d2)) & 0xfff))) #define RXEH_MASK RXEH (0xff, 0, 0, 0, 0) /* An RXE form instruction low word. */ #define RXEL(op) \ - ((((unsigned short)(op)) & 0xff) << 16 ) + ((((unsigned short) (op)) & 0xff) << 16 ) #define RXEL_MASK RXEL (0xff) /* An RXF form instruction high word. */ #define RXFH(op, r1, x2, b2, d2) \ - (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \ - ((((unsigned short)(x2)) & 0xf) << 16) | \ - ((((unsigned short)(b2)) & 0xf) << 12) | \ - ((((unsigned short)(d2)) & 0xfff))) + (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ + ((((unsigned short) (x2)) & 0xf) << 16) | \ + ((((unsigned short) (b2)) & 0xf) << 12) | \ + ((((unsigned short) (d2)) & 0xfff))) #define RXFH_MASK RXFH (0xff, 0, 0, 0, 0) /* An RXF form instruction low word. */ #define RXFL(op, r3) \ - (((((unsigned short)(r3)) & 0xf) << 28 ) | \ - ((((unsigned short)(op)) & 0xff) << 16 )) + (((((unsigned short) (r3)) & 0xf) << 28 ) | \ + ((((unsigned short) (op)) & 0xff) << 16 )) #define RXFL_MASK RXFL (0xff, 0) /* An RS form instruction. */ #define RS(op, r1, b3, b2, d2) \ - (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \ - ((((unsigned short)(b3)) & 0xf) << 16) | \ - ((((unsigned short)(b2)) & 0xf) << 12) | \ - ((((unsigned short)(d2)) & 0xfff))) + (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ + ((((unsigned short) (b3)) & 0xf) << 16) | \ + ((((unsigned short) (b2)) & 0xf) << 12) | \ + ((((unsigned short) (d2)) & 0xfff))) #define RS_MASK RS (0xff, 0x0, 0x0, 0x0, 0x0) /* An RSI form instruction. */ #define RSI(op, r1, r3, i2) \ - (XOPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \ - ((((unsigned short)(r3)) & 0xf) << 16) | \ - ((((unsigned short)(i2)) & 0xffff))) + (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ + ((((unsigned short) (r3)) & 0xf) << 16) | \ + ((((unsigned short) (i2)) & 0xffff))) #define RSI_MASK RSI (0xff, 0x0, 0x0, 0x0) /* An RI form instruction. */ #define RI(op, r1, i2) \ - (ROPS(op) | ((((unsigned short)(r1)) & 0xf) << 20) | \ - ((((unsigned short)(i2)) & 0xffff))) + (ROPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) | \ + ((((unsigned short) (i2)) & 0xffff))) #define RI_MASK RI (0xfff, 0x0, 0x0) /* An SI form instruction. */ #define SI(op, i2, b1, d1) \ - (XOPS(op) | ((((unsigned short)(i2)) & 0xff) << 16) | \ - ((((unsigned short)(b1)) & 0xf) << 12) | \ - ((((unsigned short)(d1)) & 0xfff))) + (XOPS(op) | ((((unsigned short) (i2)) & 0xff) << 16) | \ + ((((unsigned short) (b1)) & 0xf) << 12) | \ + ((((unsigned short) (d1)) & 0xfff))) #define SI_MASK SI (0xff, 0x0, 0x0, 0x0) @@ -409,26 +398,26 @@ extract_rxf_r3 (i370_insn_t insn, int *i /* An SS form instruction high word. */ #define SSH(op, l, b1, d1) \ - (XOPS(op) | ((((unsigned short)(l)) & 0xff) << 16) | \ - ((((unsigned short)(b1)) & 0xf) << 12) | \ - ((((unsigned short)(d1)) & 0xfff))) + (XOPS(op) | ((((unsigned short) (l)) & 0xff) << 16) | \ + ((((unsigned short) (b1)) & 0xf) << 12) | \ + ((((unsigned short) (d1)) & 0xfff))) /* An SS form instruction low word. */ #define SSL(b2, d2) \ - ( ((((unsigned short)(b1)) & 0xf) << 28) | \ - ((((unsigned short)(d1)) & 0xfff) << 16 )) + ( ((((unsigned short) (b1)) & 0xf) << 28) | \ + ((((unsigned short) (d1)) & 0xfff) << 16 )) #define SS_MASK SSH (0xff, 0x0, 0x0, 0x0) /* An SSE form instruction high word. */ #define SSEH(op, b1, d1) \ - (SOPS(op) | ((((unsigned short)(b1)) & 0xf) << 12) | \ - ((((unsigned short)(d1)) & 0xfff))) + (SOPS(op) | ((((unsigned short) (b1)) & 0xf) << 12) | \ + ((((unsigned short) (d1)) & 0xfff))) /* An SSE form instruction low word. */ #define SSEL(b2, d2) \ - ( ((((unsigned short)(b1)) & 0xf) << 28) | \ - ((((unsigned short)(d1)) & 0xfff) << 16 )) + ( ((((unsigned short) (b1)) & 0xf) << 28) | \ + ((((unsigned short) (d1)) & 0xfff) << 16 )) #define SSE_MASK SSEH (0xffff, 0x0, 0x0) @@ -436,8 +425,7 @@ extract_rxf_r3 (i370_insn_t insn, int *i /* Smaller names for the flags so each entry in the opcodes table will fit on a single line. These flags are set up so that e.g. IXA means the insn is supported on the 370/XA or newer architecture. - Note that 370 or older obsolete insn's are not supported ... - */ + Note that 370 or older obsolete insn's are not supported ... */ #define IBF I370_OPCODE_ESA390_BF #define IBS I370_OPCODE_ESA390_BS #define ICK I370_OPCODE_ESA390_CK @@ -479,8 +467,8 @@ extract_rxf_r3 (i370_insn_t insn, int *i specific instructions before more general instructions. It is also sorted by major opcode. */ -const struct i370_opcode i370_opcodes[] = { - +const struct i370_opcode i370_opcodes[] = +{ /* E form instructions */ { "pr", 2, {{E(0x0101), 0}}, {{E_MASK, 0}}, IESA, {0} }, @@ -546,10 +534,10 @@ const struct i370_opcode i370_opcodes[] { "sxr", 2, {{RR(0x37,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, { "xr", 2, {{RR(0x17,0,0), 0}}, {{RR_MASK, 0}}, I370, {RR_R1, RR_R2} }, -/* unusual RR formats */ +/* Unusual RR formats. */ { "svc", 2, {{SVC(0x0a,0), 0}}, {{SVC_MASK, 0}}, I370, {RR_I} }, -/* RRE form instructions */ +/* RRE form instructions. */ { "adbr", 4, {{RRE(0xb31a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, { "aebr", 4, {{RRE(0xb30a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, { "axbr", 4, {{RRE(0xb34a,0,0), 0}}, {{RRE_MASK, 0}}, IBF, {RRE_R1, RRE_R2} }, @@ -654,7 +642,7 @@ const struct i370_opcode i370_opcodes[] { "thdr", 4, {{RRE(0xb359,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, { "thder", 4, {{RRE(0xb359,0,0), 0}}, {{RRE_MASK, 0}}, IFX, {RRE_R1, RRE_R2} }, -/* RRF form instructions */ +/* RRF form instructions. */ { "cfdbr", 4, {{RRF(0xb399,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, { "cfdr", 4, {{RRF(0xb3b9,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX, {RRF_R1, RRF_R3, RRF_R2} }, { "cfebr", 4, {{RRF(0xb398,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF, {RRF_R1, RRF_R3, RRF_R2} }, @@ -673,7 +661,7 @@ const struct i370_opcode i370_opcodes[] { "tbdr", 4, {{RRF(0xb351,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX, {RRF_R1, RRF_R3, RRF_R2} }, { "tbedr", 4, {{RRF(0xb350,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX, {RRF_R1, RRF_R3, RRF_R2} }, -/* RX form instructions */ +/* RX form instructions. */ { "a", 4, {{RX(0x5a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "ad", 4, {{RX(0x6a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "ae", 4, {{RX(0x7a,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, @@ -726,7 +714,7 @@ const struct i370_opcode i370_opcodes[] { "sw", 4, {{RX(0x6f,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "x", 4, {{RX(0x57,0,0,0,0), 0}}, {{RX_MASK, 0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} }, -/* RXE form instructions */ +/* RXE form instructions. */ { "adb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x1a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "aeb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x0a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "cdb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x19)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, @@ -756,13 +744,13 @@ const struct i370_opcode i370_opcodes[] { "tceb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x10)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, { "tcxb", 6, {{RXEH(0xed,0,0,0,0), RXEL(0x12)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} }, -/* RXF form instructions */ +/* RXF form instructions. */ { "madb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x1e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, { "maeb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x0e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, { "msdb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x1f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, { "mseb", 6, {{RXFH(0xed,0,0,0,0), RXFL(0x0f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} }, -/* RS form instructions */ +/* RS form instructions. */ { "bxh", 4, {{RS(0x86,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, { "bxle", 4, {{RS(0x87,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, { "cds", 4, {{RS(0xbb,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, @@ -781,7 +769,7 @@ const struct i370_opcode i370_opcodes[] { "stm", 4, {{RS(0x90,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} }, { "trace", 4, {{RS(0x99,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA, {RX_R1, RS_R3, RS_D2, RS_B2} }, -/* RS form instructions with blank R3 and optional B2 (shift left/right) */ +/* RS form instructions with blank R3 and optional B2 (shift left/right). */ { "sla", 4, {{RS(0x8b,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, { "slda", 4, {{RS(0x8f,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, { "sldl", 4, {{RS(0x8d,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, @@ -791,11 +779,11 @@ const struct i370_opcode i370_opcodes[] { "srdl", 4, {{RS(0x8c,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, { "srl", 4, {{RS(0x88,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} }, -/* RSI form instructions */ +/* RSI form instructions. */ { "brxh", 4, {{RSI(0x84,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} }, { "brxle", 4, {{RSI(0x85,0,0,0), 0}}, {{RSI_MASK, 0}}, IIR, {RSI_R1, RSI_R3, RSI_I2} }, -/* RI form instructions */ +/* RI form instructions. */ { "ahi", 4, {{RI(0xa7a,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, { "bras", 4, {{RI(0xa75,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, { "brc", 4, {{RI(0xa74,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, @@ -806,7 +794,7 @@ const struct i370_opcode i370_opcodes[] { "tmh", 4, {{RI(0xa70,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, { "tml", 4, {{RI(0xa71,0,0), 0}}, {{RI_MASK, 0}}, IIR, {RI_R1, RI_I2} }, -/* SI form instructions */ +/* SI form instructions. */ { "cli", 4, {{SI(0x95,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, { "mc", 4, {{SI(0xaf,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, { "mvi", 4, {{SI(0x92,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, @@ -817,7 +805,7 @@ const struct i370_opcode i370_opcodes[] { "tm", 4, {{SI(0x91,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, { "xi", 4, {{SI(0x97,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} }, -/* S form instructions */ +/* S form instructions. */ { "cfc", 4, {{S(0xb21a,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, { "csch", 4, {{S(0xb230,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, { "hsch", 4, {{S(0xb231,0,0), 0}}, {{S_MASK, 0}}, IXA, {0} }, @@ -858,7 +846,7 @@ const struct i370_opcode i370_opcodes[] { "ts", 4, {{S(0x9300,0,0), 0}}, {{S_MASK, 0}}, I370, {S_D2, S_B2} }, { "tsch", 4, {{S(0xb235,0,0), 0}}, {{S_MASK, 0}}, IXA, {S_D2, S_B2} }, -/* SS form instructions */ +/* SS form instructions. */ { "ap", 6, {{SSH(0xfa,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "clc", 6, {{SSH(0xd5,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "cp", 6, {{SSH(0xf9,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, @@ -885,7 +873,7 @@ const struct i370_opcode i370_opcodes[] { "xc", 6, {{SSH(0xd7,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, { "zap", 6, {{SSH(0xf8,0,0,0), 0}}, {{SS_MASK, 0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} }, -/* SSE form instructions */ +/* SSE form instructions. */ { "lasp", 6, {{SSEH(0xe500,0,0), 0}}, {{SSE_MASK, 0}}, IXA, {SS_D1, SS_B1, SS_D2, SS_B2} }, { "mvcdk", 6, {{SSEH(0xe50f,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} }, { "mvcsk", 6, {{SSEH(0xe50e,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} }, @@ -899,7 +887,8 @@ const int i370_num_opcodes = /* The macro table. This is only used by the assembler. */ -const struct i370_macro i370_macros[] = { +const struct i370_macro i370_macros[] = +{ { "b", 1, I370, "bc 15,%0" }, { "br", 1, I370, "bcr 15,%0" }, diff -uprN binutils-2.16.91.0.1/opcodes/i386-dis.c binutils-2.16.91.0.2/opcodes/i386-dis.c --- binutils-2.16.91.0.1/opcodes/i386-dis.c 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/i386-dis.c 2005-07-20 12:27:28.680964201 -0700 @@ -88,6 +88,7 @@ static void OP_EX (int, int); static void OP_MS (int, int); static void OP_XS (int, int); static void OP_M (int, int); +static void OP_VMX (int, int); static void OP_0fae (int, int); static void OP_0f07 (int, int); static void NOP_Fixup (int, int); @@ -95,9 +96,11 @@ static void OP_3DNowSuffix (int, int); static void OP_SIMD_Suffix (int, int); static void SIMD_Fixup (int, int); static void PNI_Fixup (int, int); +static void SVME_Fixup (int, int); static void INVLPG_Fixup (int, int); static void BadOp (void); static void SEG_Fixup (int, int); +static void VMX_Fixup (int, int); struct dis_private { /* Points to first byte not fetched. */ @@ -199,6 +202,7 @@ fetch_data (struct disassemble_info *inf #define Edqw OP_E, dqw_mode #define indirEv OP_indirE, branch_v_mode #define indirEp OP_indirE, f_mode +#define Em OP_E, m_mode #define Ew OP_E, w_mode #define Ma OP_E, v_mode #define M OP_M, 0 /* lea, lgdt, etc. */ @@ -207,6 +211,7 @@ fetch_data (struct disassemble_info *inf #define Gv OP_G, v_mode #define Gd OP_G, d_mode #define Gdq OP_G, dq_mode +#define Gm OP_G, m_mode #define Gw OP_G, w_mode #define Rd OP_Rd, d_mode #define Rm OP_Rd, m_mode @@ -298,6 +303,7 @@ fetch_data (struct disassemble_info *inf #define EX OP_EX, v_mode #define MS OP_MS, v_mode #define XS OP_XS, v_mode +#define VM OP_VMX, q_mode #define OPSUF OP_3DNowSuffix, 0 #define OPSIMD OP_SIMD_Suffix, 0 @@ -914,8 +920,8 @@ static const struct dis386 dis386_twobyt { "pcmpeqd", MX, EM, XX }, { "emms", XX, XX, XX }, /* 78 */ - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, + { "vmread", Em, Gm, XX }, + { "vmwrite", Gm, Em, XX }, { "(bad)", XX, XX, XX }, { "(bad)", XX, XX, XX }, { PREGRP28 }, @@ -1101,7 +1107,7 @@ static const unsigned char twobyte_has_m /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ - /* 70 */ 1,1,1,1,1,1,1,0,0,0,0,0,1,1,1,1, /* 7f */ + /* 70 */ 1,1,1,1,1,1,1,0,1,1,0,0,1,1,1,1, /* 7f */ /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ @@ -1371,10 +1377,10 @@ static const struct dis386 grps[][8] = { }, /* GRP7 */ { - { "sgdtIQ", M, XX, XX }, + { "sgdtIQ", VMX_Fixup, 0, XX, XX }, { "sidtIQ", PNI_Fixup, 0, XX, XX }, { "lgdt{Q|Q||}", M, XX, XX }, - { "lidt{Q|Q||}", M, XX, XX }, + { "lidt{Q|Q||}", SVME_Fixup, 0, XX, XX }, { "smswQ", Ev, XX, XX }, { "(bad)", XX, XX, XX }, { "lmsw", Ew, XX, XX }, @@ -1399,8 +1405,8 @@ static const struct dis386 grps[][8] = { { "(bad)", XX, XX, XX }, { "(bad)", XX, XX, XX }, { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, + { "", VM, XX, XX }, /* See OP_VMX. */ + { "vmptrst", Eq, XX, XX }, }, /* GRP10 */ { @@ -3486,6 +3492,12 @@ OP_G (int bytemode, int sizeflag) oappend (names16[reg + add]); used_prefixes |= (prefixes & PREFIX_DATA); break; + case m_mode: + if (mode_64bit) + oappend (names64[reg + add]); + else + oappend (names32[reg + add]); + break; default: oappend (INTERNAL_DISASSEMBLER_ERROR); break; @@ -4407,7 +4419,7 @@ PNI_Fixup (int extrachar ATTRIBUTE_UNUSE /* Override "sidt". */ char *p = obuf + strlen (obuf) - 4; - /* We might have a suffix. */ + /* We might have a suffix when disassembling with -Msuffix. */ if (*p == 'i') --p; @@ -4445,7 +4457,77 @@ PNI_Fixup (int extrachar ATTRIBUTE_UNUSE codep++; } else - OP_E (0, sizeflag); + OP_M (0, sizeflag); +} + +static void +SVME_Fixup (int bytemode, int sizeflag) +{ + const char *alt; + char *p; + + switch (*codep) + { + case 0xd8: + alt = "vmrun"; + break; + case 0xd9: + alt = "vmmcall"; + break; + case 0xda: + alt = "vmload"; + break; + case 0xdb: + alt = "vmsave"; + break; + case 0xdc: + alt = "stgi"; + break; + case 0xdd: + alt = "clgi"; + break; + case 0xde: + alt = "skinit"; + break; + case 0xdf: + alt = "invlpga"; + break; + default: + OP_M (bytemode, sizeflag); + return; + } + /* Override "lidt". */ + p = obuf + strlen (obuf) - 4; + /* We might have a suffix. */ + if (*p == 'i') + --p; + strcpy (p, alt); + if (!(prefixes & PREFIX_ADDR)) + { + ++codep; + return; + } + used_prefixes |= PREFIX_ADDR; + switch (*codep++) + { + case 0xdf: + strcpy (op2out, names32[1]); + two_source_ops = 1; + /* Fall through. */ + case 0xd8: + case 0xda: + case 0xdb: + *obufp++ = open_char; + if (mode_64bit || (sizeflag & AFLAG)) + alt = names32[0]; + else + alt = names16[0]; + strcpy (obufp, alt); + obufp += strlen (alt); + *obufp++ = close_char; + *obufp = '\0'; + break; + } } static void @@ -4462,7 +4544,7 @@ INVLPG_Fixup (int bytemode, int sizeflag alt = "rdtscp"; break; default: - OP_E (bytemode, sizeflag); + OP_M (bytemode, sizeflag); return; } /* Override "invlpg". */ @@ -4526,3 +4608,50 @@ SEG_Fixup (int extrachar, int sizeflag) OP_E (extrachar, sizeflag); } + +static void +VMX_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag) +{ + if (mod == 3 && reg == 0 && rm >=1 && rm <= 4) + { + /* Override "sgdt". */ + char *p = obuf + strlen (obuf) - 4; + + /* We might have a suffix when disassembling with -Msuffix. */ + if (*p == 'g') + --p; + + switch (rm) + { + case 1: + strcpy (p, "vmcall"); + break; + case 2: + strcpy (p, "vmlaunch"); + break; + case 3: + strcpy (p, "vmresume"); + break; + case 4: + strcpy (p, "vmxoff"); + break; + } + + codep++; + } + else + OP_E (0, sizeflag); +} + +static void +OP_VMX (int bytemode, int sizeflag) +{ + used_prefixes |= (prefixes & (PREFIX_DATA | PREFIX_REPZ)); + if (prefixes & PREFIX_DATA) + strcpy (obuf, "vmclear"); + else if (prefixes & PREFIX_REPZ) + strcpy (obuf, "vmxon"); + else + strcpy (obuf, "vmptrld"); + OP_E (bytemode, sizeflag); +} diff -uprN binutils-2.16.91.0.1/opcodes/i860-dis.c binutils-2.16.91.0.2/opcodes/i860-dis.c --- binutils-2.16.91.0.1/opcodes/i860-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/i860-dis.c 2005-07-20 12:27:28.681964036 -0700 @@ -73,7 +73,7 @@ print_br_address (disassemble_info *info long adj = (long)memaddr + 4 + (val << 2); - (*info->fprintf_func) (info->stream, "0x%08x", adj); + (*info->fprintf_func) (info->stream, "0x%08lx", adj); /* Attempt to obtain a symbol for the target address. */ diff -uprN binutils-2.16.91.0.1/opcodes/ia64-dis.c binutils-2.16.91.0.2/opcodes/ia64-dis.c --- binutils-2.16.91.0.1/opcodes/ia64-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/ia64-dis.c 2005-07-20 12:27:28.682963871 -0700 @@ -109,7 +109,7 @@ print_insn_ia64 (bfd_vma memaddr, struct if (slotnum == 0) (*info->fprintf_func) (info->stream, "[%s] ", tname); else - (*info->fprintf_func) (info->stream, " ", tname); + (*info->fprintf_func) (info->stream, " "); unit = ia64_templ_desc[template].exec_unit[slotnum]; @@ -237,11 +237,11 @@ print_insn_ia64 (bfd_vma memaddr, struct if (str) (*info->fprintf_func) (info->stream, "%s", str); else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_SIGNED) - (*info->fprintf_func) (info->stream, "%lld", value); + (*info->fprintf_func) (info->stream, "%lld", (long long) value); else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_UNSIGNED) - (*info->fprintf_func) (info->stream, "%llu", value); + (*info->fprintf_func) (info->stream, "%llu", (long long) value); else - (*info->fprintf_func) (info->stream, "0x%llx", value); + (*info->fprintf_func) (info->stream, "0x%llx", (long long) value); break; case IA64_OPND_CLASS_REL: @@ -268,6 +268,6 @@ print_insn_ia64 (bfd_vma memaddr, struct return retval; decoding_failed: - (*info->fprintf_func) (info->stream, " data8 %#011llx", insn); + (*info->fprintf_func) (info->stream, " data8 %#011llx", (long long) insn); goto failed; } diff -uprN binutils-2.16.91.0.1/opcodes/ia64-gen.c binutils-2.16.91.0.2/opcodes/ia64-gen.c --- binutils-2.16.91.0.1/opcodes/ia64-gen.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/ia64-gen.c 2005-07-20 12:27:28.691962387 -0700 @@ -239,8 +239,8 @@ static int dlistlen = 0; static int dlisttotlen = 0; -static void fail (const char *, ...); -static void warn (const char *, ...); +static void fail (const char *, ...) ATTRIBUTE_PRINTF_1; +static void warn (const char *, ...) ATTRIBUTE_PRINTF_1; static struct rdep * insert_resource (const char *, enum ia64_dependency_mode); static int deplist_equals (struct deplist *, struct deplist *); static short insert_deplist (int, unsigned short *); diff -uprN binutils-2.16.91.0.1/opcodes/ip2k-asm.c binutils-2.16.91.0.2/opcodes/ip2k-asm.c --- binutils-2.16.91.0.1/opcodes/ip2k-asm.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/ip2k-asm.c 2005-07-20 12:27:28.693962058 -0700 @@ -1,26 +1,27 @@ /* Assembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-asm.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -49,24 +50,11 @@ static const char * parse_insn_normal /* -- asm.c */ -#define PARSE_FUNC_DECL(name) \ - static const char *name (CGEN_CPU_DESC, const char **, int, long *) -#define PARSE_UFUNC_DECL(name) \ - static const char *name (CGEN_CPU_DESC, const char **, int, unsigned long *) - -PARSE_UFUNC_DECL (parse_fr); -PARSE_UFUNC_DECL (parse_addr16); -PARSE_UFUNC_DECL (parse_addr16_cjp); -PARSE_FUNC_DECL (parse_lit8); -PARSE_UFUNC_DECL (parse_bit3); - - static const char * -parse_fr (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_fr (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { const char *errmsg; const char *old_strp; @@ -77,7 +65,7 @@ parse_fr (cd, strp, opindex, valuep) bfd_vma tempvalue; old_strp = *strp; - afteroffset = NULL; + afteroffset = NULL; /* Check here to see if you're about to try parsing a w as the first arg and return an error if you are. */ @@ -155,7 +143,7 @@ parse_fr (cd, strp, opindex, valuep) { /* Value is ok. Fix up the first 2 bits and return. */ *valuep = 0x0100 | tempvalue; - *strp += 4; /* skip over the (DP) in *strp. */ + *strp += 4; /* Skip over the (DP) in *strp. */ return errmsg; } else @@ -196,7 +184,7 @@ parse_fr (cd, strp, opindex, valuep) { /* Value is ok. Fix up the first 2 bits and return. */ *valuep = 0x0180 | tempvalue; - *strp += 4; /* skip over the (SP) in *strp. */ + *strp += 4; /* Skip over the (SP) in *strp. */ return errmsg; } else @@ -217,11 +205,11 @@ parse_fr (cd, strp, opindex, valuep) { *valuep = value; - /* if a parenthesis is found, warn about invalid form. */ + /* If a parenthesis is found, warn about invalid form. */ if (**strp == '(') errmsg = _("illegal use of parentheses"); - /* if a numeric value is specified, ensure that it is between + /* If a numeric value is specified, ensure that it is between 1 and 255. */ else if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) { @@ -233,11 +221,10 @@ parse_fr (cd, strp, opindex, valuep) } static const char * -parse_addr16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_addr16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -250,7 +237,7 @@ parse_addr16 (cd, strp, opindex, valuep) code = BFD_RELOC_IP2K_LO8DATA; else { - /* Something is very wrong. opindex has to be one of the above. */ + /* Something is very wrong. opindex has to be one of the above. */ errmsg = _("parse_addr16: invalid opindex."); return errmsg; } @@ -259,13 +246,14 @@ parse_addr16 (cd, strp, opindex, valuep) & result_type, & value); if (errmsg == NULL) { - /* We either have a relocation or a number now. */ + /* We either have a relocation or a number now. */ if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) { - /* We got a number back. */ + /* We got a number back. */ if (code == BFD_RELOC_IP2K_HI8DATA) value >>= 8; - else /* code = BFD_RELOC_IP2K_LOW8DATA */ + else + /* code = BFD_RELOC_IP2K_LOW8DATA. */ value &= 0x00FF; } *valuep = value; @@ -274,13 +262,11 @@ parse_addr16 (cd, strp, opindex, valuep) return errmsg; } - static const char * -parse_addr16_cjp (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_addr16_cjp (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -301,7 +287,7 @@ parse_addr16_cjp (cd, strp, opindex, val if ((value & 0x1) == 0) /* If the address is even .... */ { if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16CJP) - *valuep = (value >> 1) & 0x1FFF; /* Should mask be 1FFF? */ + *valuep = (value >> 1) & 0x1FFF; /* Should mask be 1FFF? */ else if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16P) *valuep = (value >> 14) & 0x7; } @@ -320,20 +306,18 @@ parse_addr16_cjp (cd, strp, opindex, val return errmsg; } - static const char * -parse_lit8 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - long *valuep; +parse_lit8 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; bfd_reloc_code_real_type code = BFD_RELOC_NONE; bfd_vma value; - /* Parse %OP relocating operators. */ + /* Parse %OP relocating operators. */ if (strncmp (*strp, "%bank", 5) == 0) { *strp += 5; @@ -364,7 +348,6 @@ parse_lit8 (cd, strp, opindex, valuep) *strp += 8; code = BFD_RELOC_IP2K_HI8INSN; } - /* Parse %op operand. */ if (code != BFD_RELOC_NONE) @@ -382,7 +365,7 @@ parse_lit8 (cd, strp, opindex, valuep) { errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep); - /* Truncate to eight bits to accept both signed and unsigned input. */ + /* Truncate to eight bits to accept both signed and unsigned input. */ if (errmsg == NULL) *valuep &= 0xFF; } @@ -391,11 +374,10 @@ parse_lit8 (cd, strp, opindex, valuep) } static const char * -parse_bit3 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_bit3 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { const char *errmsg; char mode = 0; @@ -456,11 +438,10 @@ parse_bit3 (cd, strp, opindex, valuep) return errmsg; } - /* -- dis.c */ const char * ip2k_cgen_parse_operand - PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); /* Main entry point for operand parsing. @@ -476,11 +457,10 @@ const char * ip2k_cgen_parse_operand the handlers. */ const char * -ip2k_cgen_parse_operand (cd, opindex, strp, fields) - CGEN_CPU_DESC cd; - int opindex; - const char ** strp; - CGEN_FIELDS * fields; +ip2k_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) { const char * errmsg = NULL; /* Used by scalar operands that still need to be parsed. */ @@ -540,8 +520,7 @@ cgen_parse_fn * const ip2k_cgen_parse_ha }; void -ip2k_cgen_init_asm (cd) - CGEN_CPU_DESC cd; +ip2k_cgen_init_asm (CGEN_CPU_DESC cd) { ip2k_cgen_init_opcode_table (cd); ip2k_cgen_init_ibld_table (cd); @@ -924,30 +903,3 @@ ip2k_cgen_assemble_insn (CGEN_CPU_DESC c return NULL; } } - -#if 0 /* This calls back to GAS which we can't do without care. */ - -/* Record each member of OPVALS in the assembler's symbol table. - This lets GAS parse registers for us. - ??? Interesting idea but not currently used. */ - -/* Record each member of OPVALS in the assembler's symbol table. - FIXME: Not currently used. */ - -void -ip2k_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) -{ - CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); - const CGEN_KEYWORD_ENTRY * ke; - - while ((ke = cgen_keyword_search_next (& search)) != NULL) - { -#if 0 /* Unnecessary, should be done in the search routine. */ - if (! ip2k_cgen_opval_supported (ke)) - continue; -#endif - cgen_asm_record_register (cd, ke->name, ke->value); - } -} - -#endif /* 0 */ diff -uprN binutils-2.16.91.0.1/opcodes/ip2k-desc.c binutils-2.16.91.0.2/opcodes/ip2k-desc.c --- binutils-2.16.91.0.1/opcodes/ip2k-desc.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/ip2k-desc.c 2005-07-20 12:27:28.710959255 -0700 @@ -858,27 +858,23 @@ static const CGEN_IBASE ip2k_cgen_insn_t #undef A /* Initialize anything needed to be done once, before any cpu_open call. */ -static void init_tables PARAMS ((void)); static void -init_tables () +init_tables (void) { } -static const CGEN_MACH * lookup_mach_via_bfd_name - PARAMS ((const CGEN_MACH *, const char *)); -static void build_hw_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_operand_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_insn_table PARAMS ((CGEN_CPU_TABLE *)); -static void ip2k_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *)); +static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); +static void build_hw_table (CGEN_CPU_TABLE *); +static void build_ifield_table (CGEN_CPU_TABLE *); +static void build_operand_table (CGEN_CPU_TABLE *); +static void build_insn_table (CGEN_CPU_TABLE *); +static void ip2k_cgen_rebuild_tables (CGEN_CPU_TABLE *); /* Subroutine of ip2k_cgen_cpu_open to look up a mach via its bfd name. */ static const CGEN_MACH * -lookup_mach_via_bfd_name (table, name) - const CGEN_MACH *table; - const char *name; +lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) { while (table->name) { @@ -892,8 +888,7 @@ lookup_mach_via_bfd_name (table, name) /* Subroutine of ip2k_cgen_cpu_open to build the hardware table. */ static void -build_hw_table (cd) - CGEN_CPU_TABLE *cd; +build_hw_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; @@ -919,8 +914,7 @@ build_hw_table (cd) /* Subroutine of ip2k_cgen_cpu_open to build the hardware table. */ static void -build_ifield_table (cd) - CGEN_CPU_TABLE *cd; +build_ifield_table (CGEN_CPU_TABLE *cd) { cd->ifld_table = & ip2k_cgen_ifld_table[0]; } @@ -928,8 +922,7 @@ build_ifield_table (cd) /* Subroutine of ip2k_cgen_cpu_open to build the hardware table. */ static void -build_operand_table (cd) - CGEN_CPU_TABLE *cd; +build_operand_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; @@ -937,8 +930,7 @@ build_operand_table (cd) /* MAX_OPERANDS is only an upper bound on the number of selected entries. However each entry is indexed by it's enum so there can be holes in the table. */ - const CGEN_OPERAND **selected = - (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); cd->operand_table.init_entries = init; cd->operand_table.entry_size = sizeof (CGEN_OPERAND); @@ -961,12 +953,11 @@ build_operand_table (cd) operand elements to be in the table [which they mightn't be]. */ static void -build_insn_table (cd) - CGEN_CPU_TABLE *cd; +build_insn_table (CGEN_CPU_TABLE *cd) { int i; const CGEN_IBASE *ib = & ip2k_cgen_insn_table[0]; - CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); for (i = 0; i < MAX_INSNS; ++i) @@ -979,8 +970,7 @@ build_insn_table (cd) /* Subroutine of ip2k_cgen_cpu_open to rebuild the tables. */ static void -ip2k_cgen_rebuild_tables (cd) - CGEN_CPU_TABLE *cd; +ip2k_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) { int i; unsigned int isas = cd->isas; @@ -992,7 +982,7 @@ ip2k_cgen_rebuild_tables (cd) #define UNSET (CGEN_SIZE_UNKNOWN + 1) cd->default_insn_bitsize = UNSET; cd->base_insn_bitsize = UNSET; - cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) if (((1 << i) & isas) != 0) @@ -1004,7 +994,7 @@ ip2k_cgen_rebuild_tables (cd) if (cd->default_insn_bitsize == UNSET) cd->default_insn_bitsize = isa->default_insn_bitsize; else if (isa->default_insn_bitsize == cd->default_insn_bitsize) - ; /* this is ok */ + ; /* This is ok. */ else cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; @@ -1013,7 +1003,7 @@ ip2k_cgen_rebuild_tables (cd) if (cd->base_insn_bitsize == UNSET) cd->base_insn_bitsize = isa->base_insn_bitsize; else if (isa->base_insn_bitsize == cd->base_insn_bitsize) - ; /* this is ok */ + ; /* This is ok. */ else cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; @@ -1125,12 +1115,12 @@ ip2k_cgen_cpu_open (enum cgen_cpu_open_a } va_end (ap); - /* mach unspecified means "all" */ + /* Mach unspecified means "all". */ if (machs == 0) machs = (1 << MAX_MACHS) - 1; - /* base mach is always selected */ + /* Base mach is always selected. */ machs |= 1; - /* isa unspecified means "all" */ + /* ISA unspecified means "all". */ if (isas == 0) isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) @@ -1163,9 +1153,7 @@ ip2k_cgen_cpu_open (enum cgen_cpu_open_a MACH_NAME is the bfd name of the mach. */ CGEN_CPU_DESC -ip2k_cgen_cpu_open_1 (mach_name, endian) - const char *mach_name; - enum cgen_endian endian; +ip2k_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) { return ip2k_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, CGEN_CPU_OPEN_ENDIAN, endian, @@ -1178,8 +1166,7 @@ ip2k_cgen_cpu_open_1 (mach_name, endian) place as some simulator ports use this but they don't use libopcodes. */ void -ip2k_cgen_cpu_close (cd) - CGEN_CPU_DESC cd; +ip2k_cgen_cpu_close (CGEN_CPU_DESC cd) { unsigned int i; const CGEN_INSN *insns; @@ -1188,23 +1175,17 @@ ip2k_cgen_cpu_close (cd) { insns = cd->macro_insn_table.init_entries; for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) - { - if (CGEN_INSN_RX ((insns))) - regfree (CGEN_INSN_RX (insns)); - } + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); } if (cd->insn_table.init_entries) { insns = cd->insn_table.init_entries; for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) - { - if (CGEN_INSN_RX (insns)) - regfree (CGEN_INSN_RX (insns)); - } - } - - + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } if (cd->macro_insn_table.init_entries) free ((CGEN_INSN *) cd->macro_insn_table.init_entries); diff -uprN binutils-2.16.91.0.1/opcodes/ip2k-dis.c binutils-2.16.91.0.2/opcodes/ip2k-dis.c --- binutils-2.16.91.0.1/opcodes/ip2k-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/ip2k-dis.c 2005-07-20 12:27:28.712958925 -0700 @@ -1,27 +1,27 @@ /* Disassembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-dis.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 -Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -56,30 +56,17 @@ static int read_insn (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, unsigned long *); -/* -- disassembler routines inserted here */ +/* -- disassembler routines inserted here. */ /* -- dis.c */ -#define PRINT_FUNC_DECL(name) \ -static void name PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)) - -PRINT_FUNC_DECL (print_fr); -PRINT_FUNC_DECL (print_dollarhex); -PRINT_FUNC_DECL (print_dollarhex8); -PRINT_FUNC_DECL (print_dollarhex_addr16h); -PRINT_FUNC_DECL (print_dollarhex_addr16l); -PRINT_FUNC_DECL (print_dollarhex_p); -PRINT_FUNC_DECL (print_dollarhex_cj); -PRINT_FUNC_DECL (print_decimal); - -static void -print_fr (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +static void +print_fr (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; const CGEN_KEYWORD_ENTRY *ke; @@ -87,7 +74,7 @@ print_fr (cd, dis_info, value, attrs, pc long offsettest; long offsetvalue; - if ( value == 0 ) /* This is (IP) */ + if (value == 0) /* This is (IP). */ { (*info->fprintf_func) (info->stream, "%s", "(IP)"); return; @@ -96,142 +83,132 @@ print_fr (cd, dis_info, value, attrs, pc offsettest = value >> 7; offsetvalue = value & 0x7F; - /* Check to see if first two bits are 10 -> (DP) */ - if ( offsettest == 2 ) + /* Check to see if first two bits are 10 -> (DP). */ + if (offsettest == 2) { - if ( offsetvalue == 0 ) + if (offsetvalue == 0) (*info->fprintf_func) (info->stream, "%s","(DP)"); else - (*info->fprintf_func) (info->stream, "$%x%s",offsetvalue, "(DP)"); + (*info->fprintf_func) (info->stream, "$%lx%s", offsetvalue, "(DP)"); return; } - /* Check to see if first two bits are 11 -> (SP) */ - if ( offsettest == 3 ) + /* Check to see if first two bits are 11 -> (SP). */ + if (offsettest == 3) { - if ( offsetvalue == 0 ) + if (offsetvalue == 0) (*info->fprintf_func) (info->stream, "%s", "(SP)"); else - (*info->fprintf_func) (info->stream, "$%x%s", offsetvalue,"(SP)"); + (*info->fprintf_func) (info->stream, "$%lx%s", offsetvalue,"(SP)"); return; } - /* Attempt to print as a register keyword. */ + /* Attempt to print as a register keyword. */ ke = cgen_keyword_lookup_value (& ip2k_cgen_opval_register_names, value); - if (ke != NULL) - { - (*info->fprintf_func) (info->stream, "%s", ke->name); - return; - } - /* Print as an address literal. */ - (*info->fprintf_func) (info->stream, "$%02x", value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + /* Print as an address literal. */ + (*info->fprintf_func) (info->stream, "$%02lx", value); } static void -print_dollarhex (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; - (*info->fprintf_func) (info->stream, "$%x", value); + (*info->fprintf_func) (info->stream, "$%lx", value); } static void -print_dollarhex8 (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_dollarhex8 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; - (*info->fprintf_func) (info->stream, "$%02x", value); + (*info->fprintf_func) (info->stream, "$%02lx", value); } static void -print_dollarhex_addr16h (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_dollarhex_addr16h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; - /* This is a loadh instruction. Shift the value to the left */ - /* by 8 bits so that disassembled code will reassemble properly. */ + /* This is a loadh instruction. Shift the value to the left + by 8 bits so that disassembled code will reassemble properly. */ value = ((value << 8) & 0xFF00); - (*info->fprintf_func) (info->stream, "$%04x", value); + (*info->fprintf_func) (info->stream, "$%04lx", value); } static void -print_dollarhex_addr16l (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_dollarhex_addr16l (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; - (*info->fprintf_func) (info->stream, "$%04x", value); + (*info->fprintf_func) (info->stream, "$%04lx", value); } static void -print_dollarhex_p (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_dollarhex_p (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; value = ((value << 14) & 0x1C000); ;value = (value & 0x1FFFF); - (*info->fprintf_func) (info->stream, "$%05x", value); + (*info->fprintf_func) (info->stream, "$%05lx", value); } static void -print_dollarhex_cj (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_dollarhex_cj (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; value = ((value << 1) & 0x1FFFF); - (*info->fprintf_func) (info->stream, "$%05x", value); + (*info->fprintf_func) (info->stream, "$%05lx", value); } - static void -print_decimal (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_decimal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; - (*info->fprintf_func) (info->stream, "%d", value); + (*info->fprintf_func) (info->stream, "%ld", value); } @@ -239,8 +216,7 @@ print_decimal (cd, dis_info, value, attr /* -- */ void ip2k_cgen_print_operand - PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, - void const *, bfd_vma, int)); + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); /* Main entry point for printing operands. XINFO is a `void *' and not a `disassemble_info *' to not put a requirement @@ -258,16 +234,15 @@ void ip2k_cgen_print_operand the handlers. */ void -ip2k_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) - CGEN_CPU_DESC cd; - int opindex; - PTR xinfo; - CGEN_FIELDS *fields; - void const *attrs ATTRIBUTE_UNUSED; - bfd_vma pc; - int length; +ip2k_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) { - disassemble_info *info = (disassemble_info *) xinfo; + disassemble_info *info = (disassemble_info *) xinfo; switch (opindex) { @@ -323,8 +298,7 @@ cgen_print_fn * const ip2k_cgen_print_ha void -ip2k_cgen_init_dis (cd) - CGEN_CPU_DESC cd; +ip2k_cgen_init_dis (CGEN_CPU_DESC cd) { ip2k_cgen_init_opcode_table (cd); ip2k_cgen_init_ibld_table (cd); @@ -376,7 +350,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUT /* Print the operand as directed by the attributes. */ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) - ; /* nothing to do */ + ; /* Nothing to do. */ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) (*info->print_address_func) (value, info); else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) @@ -458,6 +432,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UN unsigned long *insn_value) { int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) { (*info->memory_error_func) (status, pc, info); @@ -562,13 +537,13 @@ print_insn (CGEN_CPU_DESC cd, length = CGEN_EXTRACT_FN (cd, insn) (cd, insn, &ex_info, insn_value_cropped, &fields, pc); - /* length < 0 -> error */ + /* Length < 0 -> error. */ if (length < 0) return length; if (length > 0) { CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); - /* length is in bits, result is in bytes */ + /* Length is in bits, result is in bytes. */ return length / 8; } } @@ -618,7 +593,8 @@ default_print_insn (CGEN_CPU_DESC cd, bf Print one instruction from PC on INFO->STREAM. Return the size of the instruction (in bytes). */ -typedef struct cpu_desc_list { +typedef struct cpu_desc_list +{ struct cpu_desc_list *next; int isa; int mach; @@ -703,7 +679,7 @@ print_insn_ip2k (bfd_vma pc, disassemble if (!cd) abort (); - /* save this away for future reference */ + /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; cl->isa = isa; diff -uprN binutils-2.16.91.0.1/opcodes/ip2k-ibld.c binutils-2.16.91.0.2/opcodes/ip2k-ibld.c --- binutils-2.16.91.0.1/opcodes/ip2k-ibld.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/ip2k-ibld.c 2005-07-20 12:27:28.727956452 -0700 @@ -1,25 +1,26 @@ /* Instruction building/extraction support for ip2k. -*- C -*- -THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. -- the resultant file is machine generated, cgen-ibld.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -35,9 +36,9 @@ along with this program; if not, write t #include "opintl.h" #include "safe-ctype.h" -#undef min +#undef min #define min(a,b) ((a) < (b) ? (a) : (b)) -#undef max +#undef max #define max(a,b) ((a) > (b) ? (a) : (b)) /* Used by the ifield rtx function. */ @@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd, if (length == 0) return NULL; -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - if (word_length > 32) abort (); @@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd, #if CGEN_INT_INSN_P /* Cover function to store an insn value into an integral insn. Must go here - because it needs -desc.h for CGEN_INT_INSN_P. */ + because it needs -desc.h for CGEN_INT_INSN_P. */ static void put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, @@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATT int shift = insn_length - length; /* Written this way to avoid undefined behaviour. */ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); } } @@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd, { unsigned long x; int shift; -#if 0 - int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; -#endif + x = cgen_get_insn_value (cd, bufp, word_length); if (CGEN_INSN_LSB0_P) @@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd, return 1; } -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - if (word_length > 32) abort (); @@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd, return CGEN_INSN_BITSIZE (insn); } -/* machine generated code added here */ +/* Machine generated code added here. */ const char * ip2k_cgen_insert_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); /* Main entry point for operand insertion. @@ -559,12 +547,11 @@ const char * ip2k_cgen_insert_operand resolved during parsing. */ const char * -ip2k_cgen_insert_operand (cd, opindex, fields, buffer, pc) - CGEN_CPU_DESC cd; - int opindex; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc ATTRIBUTE_UNUSED; +ip2k_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) { const char * errmsg = NULL; unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); @@ -615,8 +602,7 @@ ip2k_cgen_insert_operand (cd, opindex, f } int ip2k_cgen_extract_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - CGEN_FIELDS *, bfd_vma)); + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); /* Main entry point for operand extraction. The result is <= 0 for error, >0 for success. @@ -634,13 +620,12 @@ int ip2k_cgen_extract_operand the handlers. */ int -ip2k_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) - CGEN_CPU_DESC cd; - int opindex; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS * fields; - bfd_vma pc; +ip2k_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) { /* Assume success (for those operands that are nops). */ int length = 1; @@ -701,10 +686,8 @@ cgen_extract_fn * const ip2k_cgen_extrac extract_insn_normal, }; -int ip2k_cgen_get_int_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); -bfd_vma ip2k_cgen_get_vma_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +int ip2k_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma ip2k_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); /* Getting values from cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they return. @@ -712,10 +695,9 @@ bfd_vma ip2k_cgen_get_vma_operand not appropriate. */ int -ip2k_cgen_get_int_operand (cd, opindex, fields) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - const CGEN_FIELDS * fields; +ip2k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) { int value; @@ -769,10 +751,9 @@ ip2k_cgen_get_int_operand (cd, opindex, } bfd_vma -ip2k_cgen_get_vma_operand (cd, opindex, fields) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - const CGEN_FIELDS * fields; +ip2k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) { bfd_vma value; @@ -825,10 +806,8 @@ ip2k_cgen_get_vma_operand (cd, opindex, return value; } -void ip2k_cgen_set_int_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); -void ip2k_cgen_set_vma_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); +void ip2k_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void ip2k_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); /* Stuffing values in cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they accept. @@ -836,11 +815,10 @@ void ip2k_cgen_set_vma_operand not appropriate. */ void -ip2k_cgen_set_int_operand (cd, opindex, fields, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - CGEN_FIELDS * fields; - int value; +ip2k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) { switch (opindex) { @@ -886,11 +864,10 @@ ip2k_cgen_set_int_operand (cd, opindex, } void -ip2k_cgen_set_vma_operand (cd, opindex, fields, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - CGEN_FIELDS * fields; - bfd_vma value; +ip2k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) { switch (opindex) { @@ -938,8 +915,7 @@ ip2k_cgen_set_vma_operand (cd, opindex, /* Function to call before using the instruction builder tables. */ void -ip2k_cgen_init_ibld_table (cd) - CGEN_CPU_DESC cd; +ip2k_cgen_init_ibld_table (CGEN_CPU_DESC cd) { cd->insert_handlers = & ip2k_cgen_insert_handlers[0]; cd->extract_handlers = & ip2k_cgen_extract_handlers[0]; diff -uprN binutils-2.16.91.0.1/opcodes/ip2k-opc.c binutils-2.16.91.0.2/opcodes/ip2k-opc.c --- binutils-2.16.91.0.1/opcodes/ip2k-opc.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/ip2k-opc.c 2005-07-20 12:27:28.728956287 -0700 @@ -34,16 +34,15 @@ with this program; if not, write to the #include "safe-ctype.h" -/* A better hash function for instruction mnemonics. */ +/* A better hash function for instruction mnemonics. */ unsigned int -ip2k_asm_hash (insn) - const char* insn; +ip2k_asm_hash (const char* insn) { unsigned int hash; const char* m = insn; - for (hash = 0; *m && !ISSPACE(*m); m++) - hash = (hash * 23) ^ (0x1F & TOLOWER(*m)); + for (hash = 0; *m && ! ISSPACE (*m); m++) + hash = (hash * 23) ^ (0x1F & TOLOWER (*m)); /* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */ @@ -51,11 +50,10 @@ ip2k_asm_hash (insn) } -/* Special check to ensure that instruction exists for given machine. */ +/* Special check to ensure that instruction exists for given machine. */ + int -ip2k_cgen_insn_supported (cd, insn) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; +ip2k_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) { int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); @@ -63,7 +61,7 @@ ip2k_cgen_insn_supported (cd, insn) if (machs == 0) return 1; - return ((machs & cd->machs) != 0); + return (machs & cd->machs) != 0; } @@ -71,10 +69,10 @@ ip2k_cgen_insn_supported (cd, insn) /* The hash functions are recorded here to help keep assembler code out of the disassembler and vice versa. */ -static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int asm_hash_insn PARAMS ((const char *)); -static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); /* Instruction formats. */ @@ -873,14 +871,10 @@ dis_hash_insn (buf, value) return CGEN_DIS_HASH (buf, value); } -static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int)); - /* Set the recorded length of the insn in the CGEN_FIELDS struct. */ static void -set_fields_bitsize (fields, size) - CGEN_FIELDS *fields; - int size; +set_fields_bitsize (CGEN_FIELDS *fields, int size) { CGEN_FIELDS_BITSIZE (fields) = size; } @@ -889,15 +883,15 @@ set_fields_bitsize (fields, size) This plugs the opcode entries and macro instructions into the cpu table. */ void -ip2k_cgen_init_opcode_table (cd) - CGEN_CPU_DESC cd; +ip2k_cgen_init_opcode_table (CGEN_CPU_DESC cd) { int i; int num_macros = (sizeof (ip2k_cgen_macro_insn_table) / sizeof (ip2k_cgen_macro_insn_table[0])); const CGEN_IBASE *ib = & ip2k_cgen_macro_insn_table[0]; const CGEN_OPCODE *oc = & ip2k_cgen_macro_insn_opcode_table[0]; - CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN)); + CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); for (i = 0; i < num_macros; ++i) { diff -uprN binutils-2.16.91.0.1/opcodes/ip2k-opc.h binutils-2.16.91.0.2/opcodes/ip2k-opc.h --- binutils-2.16.91.0.1/opcodes/ip2k-opc.h 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/ip2k-opc.h 2005-07-20 12:27:28.729956122 -0700 @@ -36,14 +36,14 @@ with this program; if not, write to the /* Override disassembly hashing - there are variable bits in the top byte of these instructions. */ #define CGEN_DIS_HASH_SIZE 8 -#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 5) % CGEN_DIS_HASH_SIZE) +#define CGEN_DIS_HASH(buf, value) \ + (((* (unsigned char*) (buf)) >> 5) % CGEN_DIS_HASH_SIZE) #define CGEN_ASM_HASH_SIZE 127 -#define CGEN_ASM_HASH(insn) ip2k_asm_hash(insn) +#define CGEN_ASM_HASH(insn) ip2k_asm_hash (insn) -extern unsigned int ip2k_asm_hash PARAMS ((const char *insn)); -extern int ip2k_cgen_insn_supported - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *)); +extern unsigned int ip2k_asm_hash (const char *); +extern int ip2k_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); /* -- opc.c */ /* Enum declaration for ip2k instruction types. */ diff -uprN binutils-2.16.91.0.1/opcodes/iq2000-asm.c binutils-2.16.91.0.2/opcodes/iq2000-asm.c --- binutils-2.16.91.0.1/opcodes/iq2000-asm.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/iq2000-asm.c 2005-07-20 12:27:28.730955957 -0700 @@ -1,26 +1,27 @@ /* Assembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-asm.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -51,30 +52,24 @@ static const char * parse_insn_normal #include "safe-ctype.h" -static int iq2000_cgen_isa_register PARAMS ((const char **)); -static const char * parse_jtargq10 PARAMS ((CGEN_CPU_DESC, const char **, int, int, enum cgen_parse_operand_result *, bfd_vma *)); -static const char * parse_mimm PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_imm PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_hi16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_lo16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_mlo16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'"); + +/* Special check to ensure that instruction exists for given machine. */ -/* Special check to ensure that instruction exists for given machine */ int -iq2000_cgen_insn_supported (cd, insn) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; +iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) { int machs = cd->machs; - return ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0); + return (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0; } -static int iq2000_cgen_isa_register (strp) - const char **strp; +static int +iq2000_cgen_isa_register (const char **strp) { int len; int ch1, ch2; + if (**strp == 'r' || **strp == 'R') { len = strlen (*strp); @@ -94,7 +89,9 @@ static int iq2000_cgen_isa_register (str return 1; } } - if (**strp == '%' && TOLOWER((*strp)[1]) != 'l' && TOLOWER((*strp)[1]) != 'h') + if (**strp == '%' + && TOLOWER ((*strp)[1]) != 'l' + && TOLOWER ((*strp)[1]) != 'h') return 1; return 0; } @@ -102,11 +99,10 @@ static int iq2000_cgen_isa_register (str /* Handle negated literal. */ static const char * -parse_mimm (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_mimm (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { const char *errmsg; @@ -134,11 +130,10 @@ parse_mimm (cd, strp, opindex, valuep) /* Handle signed/unsigned literal. */ static const char * -parse_imm (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_imm (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { const char *errmsg; @@ -152,6 +147,7 @@ parse_imm (cd, strp, opindex, valuep) if (errmsg == NULL) { long x = value & 0xFFFF0000; + if (x != 0 && x != (long) 0xFFFF0000) errmsg = _("immediate value out of range"); else @@ -164,23 +160,23 @@ parse_imm (cd, strp, opindex, valuep) /* Handle iq10 21-bit jmp offset. */ static const char * -parse_jtargq10 (cd, strp, opindex, reloc, type_addr, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - int reloc ATTRIBUTE_UNUSED; - enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED; - bfd_vma *valuep; +parse_jtargq10 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + int reloc ATTRIBUTE_UNUSED, + enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED, + bfd_vma *valuep) { const char *errmsg; bfd_vma value; enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_OFFSET_21, - &result_type, &value); + & result_type, & value); if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) { - /* Check value is within 23-bits (remembering that 2-bit shift right will occur). */ + /* Check value is within 23-bits + (remembering that 2-bit shift right will occur). */ if (value > 0x7fffff) return _("21-bit offset out of range"); } @@ -191,11 +187,10 @@ parse_jtargq10 (cd, strp, opindex, reloc /* Handle high(). */ static const char * -parse_hi16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_hi16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { if (strncasecmp (*strp, "%hi(", 4) == 0) { @@ -205,17 +200,17 @@ parse_hi16 (cd, strp, opindex, valuep) *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return _("missing `)'"); + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) { - /* if value has top-bit of %lo on, then it will + /* If value has top-bit of %lo on, then it will sign-propagate and so we compensate by adding - 1 to the resultant %hi value */ + 1 to the resultant %hi value. */ if (value & 0x8000) value += 0x10000; value >>= 16; @@ -225,8 +220,8 @@ parse_hi16 (cd, strp, opindex, valuep) return errmsg; } - /* we add %uhi in case a user just wants the high 16-bits or is using - an insn like ori for %lo which does not sign-propagate */ + /* We add %uhi in case a user just wants the high 16-bits or is using + an insn like ori for %lo which does not sign-propagate. */ if (strncasecmp (*strp, "%uhi(", 5) == 0) { enum cgen_parse_operand_result result_type; @@ -235,16 +230,15 @@ parse_hi16 (cd, strp, opindex, valuep) *strp += 5; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_UHI16, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return _("missing `)'"); + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - { - value >>= 16; - } + value >>= 16; + *valuep = value; return errmsg; @@ -258,11 +252,10 @@ parse_hi16 (cd, strp, opindex, valuep) handles the case where %lo() isn't present. */ static const char * -parse_lo16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_lo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { if (strncasecmp (*strp, "%lo(", 4) == 0) { @@ -272,9 +265,9 @@ parse_lo16 (cd, strp, opindex, valuep) *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return _("missing `)'"); + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) @@ -291,11 +284,10 @@ parse_lo16 (cd, strp, opindex, valuep) handles the case where %lo() isn't present. */ static const char * -parse_mlo16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_mlo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { if (strncasecmp (*strp, "%lo(", 4) == 0) { @@ -305,9 +297,9 @@ parse_mlo16 (cd, strp, opindex, valuep) *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return _("missing `)'"); + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) @@ -322,7 +314,7 @@ parse_mlo16 (cd, strp, opindex, valuep) /* -- */ const char * iq2000_cgen_parse_operand - PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); /* Main entry point for operand parsing. @@ -338,11 +330,10 @@ const char * iq2000_cgen_parse_operand the handlers. */ const char * -iq2000_cgen_parse_operand (cd, opindex, strp, fields) - CGEN_CPU_DESC cd; - int opindex; - const char ** strp; - CGEN_FIELDS * fields; +iq2000_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) { const char * errmsg = NULL; /* Used by scalar operands that still need to be parsed. */ @@ -475,8 +466,7 @@ cgen_parse_fn * const iq2000_cgen_parse_ }; void -iq2000_cgen_init_asm (cd) - CGEN_CPU_DESC cd; +iq2000_cgen_init_asm (CGEN_CPU_DESC cd) { iq2000_cgen_init_opcode_table (cd); iq2000_cgen_init_ibld_table (cd); @@ -859,30 +849,3 @@ iq2000_cgen_assemble_insn (CGEN_CPU_DESC return NULL; } } - -#if 0 /* This calls back to GAS which we can't do without care. */ - -/* Record each member of OPVALS in the assembler's symbol table. - This lets GAS parse registers for us. - ??? Interesting idea but not currently used. */ - -/* Record each member of OPVALS in the assembler's symbol table. - FIXME: Not currently used. */ - -void -iq2000_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) -{ - CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); - const CGEN_KEYWORD_ENTRY * ke; - - while ((ke = cgen_keyword_search_next (& search)) != NULL) - { -#if 0 /* Unnecessary, should be done in the search routine. */ - if (! iq2000_cgen_opval_supported (ke)) - continue; -#endif - cgen_asm_record_register (cd, ke->name, ke->value); - } -} - -#endif /* 0 */ diff -uprN binutils-2.16.91.0.1/opcodes/iq2000-desc.c binutils-2.16.91.0.2/opcodes/iq2000-desc.c --- binutils-2.16.91.0.1/opcodes/iq2000-desc.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/iq2000-desc.c 2005-07-20 12:27:28.733955463 -0700 @@ -1863,27 +1863,23 @@ static const CGEN_IBASE iq2000_cgen_insn #undef A /* Initialize anything needed to be done once, before any cpu_open call. */ -static void init_tables PARAMS ((void)); static void -init_tables () +init_tables (void) { } -static const CGEN_MACH * lookup_mach_via_bfd_name - PARAMS ((const CGEN_MACH *, const char *)); -static void build_hw_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_operand_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_insn_table PARAMS ((CGEN_CPU_TABLE *)); -static void iq2000_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *)); +static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); +static void build_hw_table (CGEN_CPU_TABLE *); +static void build_ifield_table (CGEN_CPU_TABLE *); +static void build_operand_table (CGEN_CPU_TABLE *); +static void build_insn_table (CGEN_CPU_TABLE *); +static void iq2000_cgen_rebuild_tables (CGEN_CPU_TABLE *); /* Subroutine of iq2000_cgen_cpu_open to look up a mach via its bfd name. */ static const CGEN_MACH * -lookup_mach_via_bfd_name (table, name) - const CGEN_MACH *table; - const char *name; +lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) { while (table->name) { @@ -1897,8 +1893,7 @@ lookup_mach_via_bfd_name (table, name) /* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */ static void -build_hw_table (cd) - CGEN_CPU_TABLE *cd; +build_hw_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; @@ -1924,8 +1919,7 @@ build_hw_table (cd) /* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */ static void -build_ifield_table (cd) - CGEN_CPU_TABLE *cd; +build_ifield_table (CGEN_CPU_TABLE *cd) { cd->ifld_table = & iq2000_cgen_ifld_table[0]; } @@ -1933,8 +1927,7 @@ build_ifield_table (cd) /* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */ static void -build_operand_table (cd) - CGEN_CPU_TABLE *cd; +build_operand_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; @@ -1942,8 +1935,7 @@ build_operand_table (cd) /* MAX_OPERANDS is only an upper bound on the number of selected entries. However each entry is indexed by it's enum so there can be holes in the table. */ - const CGEN_OPERAND **selected = - (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); cd->operand_table.init_entries = init; cd->operand_table.entry_size = sizeof (CGEN_OPERAND); @@ -1966,12 +1958,11 @@ build_operand_table (cd) operand elements to be in the table [which they mightn't be]. */ static void -build_insn_table (cd) - CGEN_CPU_TABLE *cd; +build_insn_table (CGEN_CPU_TABLE *cd) { int i; const CGEN_IBASE *ib = & iq2000_cgen_insn_table[0]; - CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); for (i = 0; i < MAX_INSNS; ++i) @@ -1984,8 +1975,7 @@ build_insn_table (cd) /* Subroutine of iq2000_cgen_cpu_open to rebuild the tables. */ static void -iq2000_cgen_rebuild_tables (cd) - CGEN_CPU_TABLE *cd; +iq2000_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) { int i; unsigned int isas = cd->isas; @@ -1997,7 +1987,7 @@ iq2000_cgen_rebuild_tables (cd) #define UNSET (CGEN_SIZE_UNKNOWN + 1) cd->default_insn_bitsize = UNSET; cd->base_insn_bitsize = UNSET; - cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) if (((1 << i) & isas) != 0) @@ -2009,7 +1999,7 @@ iq2000_cgen_rebuild_tables (cd) if (cd->default_insn_bitsize == UNSET) cd->default_insn_bitsize = isa->default_insn_bitsize; else if (isa->default_insn_bitsize == cd->default_insn_bitsize) - ; /* this is ok */ + ; /* This is ok. */ else cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; @@ -2018,7 +2008,7 @@ iq2000_cgen_rebuild_tables (cd) if (cd->base_insn_bitsize == UNSET) cd->base_insn_bitsize = isa->base_insn_bitsize; else if (isa->base_insn_bitsize == cd->base_insn_bitsize) - ; /* this is ok */ + ; /* This is ok. */ else cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; @@ -2130,12 +2120,12 @@ iq2000_cgen_cpu_open (enum cgen_cpu_open } va_end (ap); - /* mach unspecified means "all" */ + /* Mach unspecified means "all". */ if (machs == 0) machs = (1 << MAX_MACHS) - 1; - /* base mach is always selected */ + /* Base mach is always selected. */ machs |= 1; - /* isa unspecified means "all" */ + /* ISA unspecified means "all". */ if (isas == 0) isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) @@ -2168,9 +2158,7 @@ iq2000_cgen_cpu_open (enum cgen_cpu_open MACH_NAME is the bfd name of the mach. */ CGEN_CPU_DESC -iq2000_cgen_cpu_open_1 (mach_name, endian) - const char *mach_name; - enum cgen_endian endian; +iq2000_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) { return iq2000_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, CGEN_CPU_OPEN_ENDIAN, endian, @@ -2183,8 +2171,7 @@ iq2000_cgen_cpu_open_1 (mach_name, endia place as some simulator ports use this but they don't use libopcodes. */ void -iq2000_cgen_cpu_close (cd) - CGEN_CPU_DESC cd; +iq2000_cgen_cpu_close (CGEN_CPU_DESC cd) { unsigned int i; const CGEN_INSN *insns; @@ -2193,23 +2180,17 @@ iq2000_cgen_cpu_close (cd) { insns = cd->macro_insn_table.init_entries; for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) - { - if (CGEN_INSN_RX ((insns))) - regfree (CGEN_INSN_RX (insns)); - } + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); } if (cd->insn_table.init_entries) { insns = cd->insn_table.init_entries; for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) - { - if (CGEN_INSN_RX (insns)) - regfree (CGEN_INSN_RX (insns)); - } - } - - + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } if (cd->macro_insn_table.init_entries) free ((CGEN_INSN *) cd->macro_insn_table.init_entries); diff -uprN binutils-2.16.91.0.1/opcodes/iq2000-dis.c binutils-2.16.91.0.2/opcodes/iq2000-dis.c --- binutils-2.16.91.0.1/opcodes/iq2000-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/iq2000-dis.c 2005-07-20 12:27:28.735955133 -0700 @@ -1,27 +1,27 @@ /* Disassembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-dis.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 -Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -56,12 +56,11 @@ static int read_insn (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, unsigned long *); -/* -- disassembler routines inserted here */ +/* -- disassembler routines inserted here. */ void iq2000_cgen_print_operand - PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, - void const *, bfd_vma, int)); + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); /* Main entry point for printing operands. XINFO is a `void *' and not a `disassemble_info *' to not put a requirement @@ -79,16 +78,15 @@ void iq2000_cgen_print_operand the handlers. */ void -iq2000_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) - CGEN_CPU_DESC cd; - int opindex; - PTR xinfo; - CGEN_FIELDS *fields; - void const *attrs ATTRIBUTE_UNUSED; - bfd_vma pc; - int length; +iq2000_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) { - disassemble_info *info = (disassemble_info *) xinfo; + disassemble_info *info = (disassemble_info *) xinfo; switch (opindex) { @@ -201,8 +199,7 @@ cgen_print_fn * const iq2000_cgen_print_ void -iq2000_cgen_init_dis (cd) - CGEN_CPU_DESC cd; +iq2000_cgen_init_dis (CGEN_CPU_DESC cd) { iq2000_cgen_init_opcode_table (cd); iq2000_cgen_init_ibld_table (cd); @@ -254,7 +251,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUT /* Print the operand as directed by the attributes. */ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) - ; /* nothing to do */ + ; /* Nothing to do. */ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) (*info->print_address_func) (value, info); else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) @@ -336,6 +333,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UN unsigned long *insn_value) { int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) { (*info->memory_error_func) (status, pc, info); @@ -440,13 +438,13 @@ print_insn (CGEN_CPU_DESC cd, length = CGEN_EXTRACT_FN (cd, insn) (cd, insn, &ex_info, insn_value_cropped, &fields, pc); - /* length < 0 -> error */ + /* Length < 0 -> error. */ if (length < 0) return length; if (length > 0) { CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); - /* length is in bits, result is in bytes */ + /* Length is in bits, result is in bytes. */ return length / 8; } } @@ -496,7 +494,8 @@ default_print_insn (CGEN_CPU_DESC cd, bf Print one instruction from PC on INFO->STREAM. Return the size of the instruction (in bytes). */ -typedef struct cpu_desc_list { +typedef struct cpu_desc_list +{ struct cpu_desc_list *next; int isa; int mach; @@ -581,7 +580,7 @@ print_insn_iq2000 (bfd_vma pc, disassemb if (!cd) abort (); - /* save this away for future reference */ + /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; cl->isa = isa; diff -uprN binutils-2.16.91.0.1/opcodes/iq2000-ibld.c binutils-2.16.91.0.2/opcodes/iq2000-ibld.c --- binutils-2.16.91.0.1/opcodes/iq2000-ibld.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/iq2000-ibld.c 2005-07-20 12:27:28.737954803 -0700 @@ -1,25 +1,26 @@ /* Instruction building/extraction support for iq2000. -*- C -*- -THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. -- the resultant file is machine generated, cgen-ibld.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -35,9 +36,9 @@ along with this program; if not, write t #include "opintl.h" #include "safe-ctype.h" -#undef min +#undef min #define min(a,b) ((a) < (b) ? (a) : (b)) -#undef max +#undef max #define max(a,b) ((a) > (b) ? (a) : (b)) /* Used by the ifield rtx function. */ @@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd, if (length == 0) return NULL; -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - if (word_length > 32) abort (); @@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd, #if CGEN_INT_INSN_P /* Cover function to store an insn value into an integral insn. Must go here - because it needs -desc.h for CGEN_INT_INSN_P. */ + because it needs -desc.h for CGEN_INT_INSN_P. */ static void put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, @@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATT int shift = insn_length - length; /* Written this way to avoid undefined behaviour. */ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); } } @@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd, { unsigned long x; int shift; -#if 0 - int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; -#endif + x = cgen_get_insn_value (cd, bufp, word_length); if (CGEN_INSN_LSB0_P) @@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd, return 1; } -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - if (word_length > 32) abort (); @@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd, return CGEN_INSN_BITSIZE (insn); } -/* machine generated code added here */ +/* Machine generated code added here. */ const char * iq2000_cgen_insert_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); /* Main entry point for operand insertion. @@ -559,12 +547,11 @@ const char * iq2000_cgen_insert_operand resolved during parsing. */ const char * -iq2000_cgen_insert_operand (cd, opindex, fields, buffer, pc) - CGEN_CPU_DESC cd; - int opindex; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc ATTRIBUTE_UNUSED; +iq2000_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) { const char * errmsg = NULL; unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); @@ -721,8 +708,7 @@ iq2000_cgen_insert_operand (cd, opindex, } int iq2000_cgen_extract_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - CGEN_FIELDS *, bfd_vma)); + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); /* Main entry point for operand extraction. The result is <= 0 for error, >0 for success. @@ -740,13 +726,12 @@ int iq2000_cgen_extract_operand the handlers. */ int -iq2000_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) - CGEN_CPU_DESC cd; - int opindex; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS * fields; - bfd_vma pc; +iq2000_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) { /* Assume success (for those operands that are nops). */ int length = 1; @@ -907,10 +892,8 @@ cgen_extract_fn * const iq2000_cgen_extr extract_insn_normal, }; -int iq2000_cgen_get_int_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); -bfd_vma iq2000_cgen_get_vma_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +int iq2000_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma iq2000_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); /* Getting values from cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they return. @@ -918,10 +901,9 @@ bfd_vma iq2000_cgen_get_vma_operand not appropriate. */ int -iq2000_cgen_get_int_operand (cd, opindex, fields) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - const CGEN_FIELDS * fields; +iq2000_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) { int value; @@ -1032,10 +1014,9 @@ iq2000_cgen_get_int_operand (cd, opindex } bfd_vma -iq2000_cgen_get_vma_operand (cd, opindex, fields) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - const CGEN_FIELDS * fields; +iq2000_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) { bfd_vma value; @@ -1145,10 +1126,8 @@ iq2000_cgen_get_vma_operand (cd, opindex return value; } -void iq2000_cgen_set_int_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); -void iq2000_cgen_set_vma_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); +void iq2000_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void iq2000_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); /* Stuffing values in cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they accept. @@ -1156,11 +1135,10 @@ void iq2000_cgen_set_vma_operand not appropriate. */ void -iq2000_cgen_set_int_operand (cd, opindex, fields, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - CGEN_FIELDS * fields; - int value; +iq2000_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) { switch (opindex) { @@ -1267,11 +1245,10 @@ iq2000_cgen_set_int_operand (cd, opindex } void -iq2000_cgen_set_vma_operand (cd, opindex, fields, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - CGEN_FIELDS * fields; - bfd_vma value; +iq2000_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) { switch (opindex) { @@ -1380,8 +1357,7 @@ iq2000_cgen_set_vma_operand (cd, opindex /* Function to call before using the instruction builder tables. */ void -iq2000_cgen_init_ibld_table (cd) - CGEN_CPU_DESC cd; +iq2000_cgen_init_ibld_table (CGEN_CPU_DESC cd) { cd->insert_handlers = & iq2000_cgen_insert_handlers[0]; cd->extract_handlers = & iq2000_cgen_extract_handlers[0]; diff -uprN binutils-2.16.91.0.1/opcodes/iq2000-opc.c binutils-2.16.91.0.2/opcodes/iq2000-opc.c --- binutils-2.16.91.0.1/opcodes/iq2000-opc.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/iq2000-opc.c 2005-07-20 12:27:28.740954309 -0700 @@ -33,10 +33,10 @@ with this program; if not, write to the /* The hash functions are recorded here to help keep assembler code out of the disassembler and vice versa. */ -static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int asm_hash_insn PARAMS ((const char *)); -static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); /* Instruction formats. */ @@ -3425,14 +3425,10 @@ dis_hash_insn (buf, value) return CGEN_DIS_HASH (buf, value); } -static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int)); - /* Set the recorded length of the insn in the CGEN_FIELDS struct. */ static void -set_fields_bitsize (fields, size) - CGEN_FIELDS *fields; - int size; +set_fields_bitsize (CGEN_FIELDS *fields, int size) { CGEN_FIELDS_BITSIZE (fields) = size; } @@ -3441,15 +3437,15 @@ set_fields_bitsize (fields, size) This plugs the opcode entries and macro instructions into the cpu table. */ void -iq2000_cgen_init_opcode_table (cd) - CGEN_CPU_DESC cd; +iq2000_cgen_init_opcode_table (CGEN_CPU_DESC cd) { int i; int num_macros = (sizeof (iq2000_cgen_macro_insn_table) / sizeof (iq2000_cgen_macro_insn_table[0])); const CGEN_IBASE *ib = & iq2000_cgen_macro_insn_table[0]; const CGEN_OPCODE *oc = & iq2000_cgen_macro_insn_opcode_table[0]; - CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN)); + CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); for (i = 0; i < num_macros; ++i) { diff -uprN binutils-2.16.91.0.1/opcodes/iq2000-opc.h binutils-2.16.91.0.2/opcodes/iq2000-opc.h --- binutils-2.16.91.0.1/opcodes/iq2000-opc.h 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/iq2000-opc.h 2005-07-20 12:27:28.741954144 -0700 @@ -39,7 +39,7 @@ with this program; if not, write to the instructions have same mnemonics but different functionality. */ #define CGEN_VALIDATE_INSN_SUPPORTED -extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn); +extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); /* -- asm.c */ /* Enum declaration for iq2000 instruction types. */ diff -uprN binutils-2.16.91.0.1/opcodes/m10200-dis.c binutils-2.16.91.0.2/opcodes/m10200-dis.c --- binutils-2.16.91.0.1/opcodes/m10200-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/m10200-dis.c 2005-07-20 12:27:28.742953979 -0700 @@ -1,20 +1,20 @@ /* Disassemble MN10200 instructions. - Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Copyright 1996, 1997, 1998, 2000, 2005 Free Software Foundation, Inc. + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include @@ -23,14 +23,141 @@ Foundation, Inc., 51 Franklin Street - F #include "dis-asm.h" #include "opintl.h" -static void disassemble PARAMS ((bfd_vma, struct disassemble_info *, - unsigned long insn, unsigned long, - unsigned int)); +static void +disassemble (bfd_vma memaddr, + struct disassemble_info *info, + unsigned long insn, + unsigned long extension, + unsigned int size) +{ + struct mn10200_opcode *op = (struct mn10200_opcode *)mn10200_opcodes; + const struct mn10200_operand *operand; + int match = 0; + + /* Find the opcode. */ + while (op->name) + { + int mysize, extra_shift; + + if (op->format == FMT_1) + mysize = 1; + else if (op->format == FMT_2 + || op->format == FMT_4) + mysize = 2; + else if (op->format == FMT_3 + || op->format == FMT_5) + mysize = 3; + else if (op->format == FMT_6) + mysize = 4; + else if (op->format == FMT_7) + mysize = 5; + else + abort (); + + if (op->format == FMT_2 || op->format == FMT_5) + extra_shift = 8; + else if (op->format == FMT_3 + || op->format == FMT_6 + || op->format == FMT_7) + extra_shift = 16; + else + extra_shift = 0; + + if ((op->mask & insn) == op->opcode + && size == (unsigned int) mysize) + { + const unsigned char *opindex_ptr; + unsigned int nocomma; + int paren = 0; + + match = 1; + (*info->fprintf_func) (info->stream, "%s\t", op->name); + + /* Now print the operands. */ + for (opindex_ptr = op->operands, nocomma = 1; + *opindex_ptr != 0; + opindex_ptr++) + { + unsigned long value; + + operand = &mn10200_operands[*opindex_ptr]; + + if ((operand->flags & MN10200_OPERAND_EXTENDED) != 0) + { + value = (insn & 0xffff) << 8; + value |= extension; + } + else + { + value = ((insn >> (operand->shift)) + & ((1L << operand->bits) - 1L)); + } + + if ((operand->flags & MN10200_OPERAND_SIGNED) != 0) + value = ((long)(value << (32 - operand->bits)) + >> (32 - operand->bits)); + + if (!nocomma + && (!paren + || ((operand->flags & MN10200_OPERAND_PAREN) == 0))) + (*info->fprintf_func) (info->stream, ","); + + nocomma = 0; + + if ((operand->flags & MN10200_OPERAND_DREG) != 0) + { + value = ((insn >> (operand->shift + extra_shift)) + & ((1 << operand->bits) - 1)); + (*info->fprintf_func) (info->stream, "d%ld", value); + } + + else if ((operand->flags & MN10200_OPERAND_AREG) != 0) + { + value = ((insn >> (operand->shift + extra_shift)) + & ((1 << operand->bits) - 1)); + (*info->fprintf_func) (info->stream, "a%ld", value); + } + + else if ((operand->flags & MN10200_OPERAND_PSW) != 0) + (*info->fprintf_func) (info->stream, "psw"); + + else if ((operand->flags & MN10200_OPERAND_MDR) != 0) + (*info->fprintf_func) (info->stream, "mdr"); + + else if ((operand->flags & MN10200_OPERAND_PAREN) != 0) + { + if (paren) + (*info->fprintf_func) (info->stream, ")"); + else + { + (*info->fprintf_func) (info->stream, "("); + nocomma = 1; + } + paren = !paren; + } + + else if ((operand->flags & MN10200_OPERAND_PCREL) != 0) + (*info->print_address_func) + ((value + memaddr + mysize) & 0xffffff, info); + + else if ((operand->flags & MN10200_OPERAND_MEMADDR) != 0) + (*info->print_address_func) (value, info); + + else + (*info->fprintf_func) (info->stream, "%ld", value); + } + /* All done. */ + break; + } + op++; + } + + if (!match) + (*info->fprintf_func) (info->stream, _("unknown\t0x%04lx"), insn); +} int -print_insn_mn10200 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_mn10200 (bfd_vma memaddr, struct disassemble_info *info) { int status; bfd_byte buffer[4]; @@ -196,7 +323,7 @@ print_insn_mn10200 (memaddr, info) } else { - (*info->fprintf_func) (info->stream, _("unknown\t0x%02x"), insn); + (*info->fprintf_func) (info->stream, _("unknown\t0x%02lx"), insn); return 1; } @@ -204,138 +331,3 @@ print_insn_mn10200 (memaddr, info) return consume; } - -static void -disassemble (memaddr, info, insn, extension, size) - bfd_vma memaddr; - struct disassemble_info *info; - unsigned long insn; - unsigned long extension; - unsigned int size; -{ - struct mn10200_opcode *op = (struct mn10200_opcode *)mn10200_opcodes; - const struct mn10200_operand *operand; - int match = 0; - - /* Find the opcode. */ - while (op->name) - { - int mysize, extra_shift; - - if (op->format == FMT_1) - mysize = 1; - else if (op->format == FMT_2 - || op->format == FMT_4) - mysize = 2; - else if (op->format == FMT_3 - || op->format == FMT_5) - mysize = 3; - else if (op->format == FMT_6) - mysize = 4; - else if (op->format == FMT_7) - mysize = 5; - else - abort (); - - if (op->format == FMT_2 || op->format == FMT_5) - extra_shift = 8; - else if (op->format == FMT_3 - || op->format == FMT_6 - || op->format == FMT_7) - extra_shift = 16; - else - extra_shift = 0; - - if ((op->mask & insn) == op->opcode - && size == (unsigned int) mysize) - { - const unsigned char *opindex_ptr; - unsigned int nocomma; - int paren = 0; - - match = 1; - (*info->fprintf_func) (info->stream, "%s\t", op->name); - - /* Now print the operands. */ - for (opindex_ptr = op->operands, nocomma = 1; - *opindex_ptr != 0; - opindex_ptr++) - { - unsigned long value; - - operand = &mn10200_operands[*opindex_ptr]; - - if ((operand->flags & MN10200_OPERAND_EXTENDED) != 0) - { - value = (insn & 0xffff) << 8; - value |= extension; - } - else - { - value = ((insn >> (operand->shift)) - & ((1L << operand->bits) - 1L)); - } - - if ((operand->flags & MN10200_OPERAND_SIGNED) != 0) - value = ((long)(value << (32 - operand->bits)) - >> (32 - operand->bits)); - - if (!nocomma - && (!paren - || ((operand->flags & MN10200_OPERAND_PAREN) == 0))) - (*info->fprintf_func) (info->stream, ","); - - nocomma = 0; - - if ((operand->flags & MN10200_OPERAND_DREG) != 0) - { - value = ((insn >> (operand->shift + extra_shift)) - & ((1 << operand->bits) - 1)); - (*info->fprintf_func) (info->stream, "d%d", value); - } - - else if ((operand->flags & MN10200_OPERAND_AREG) != 0) - { - value = ((insn >> (operand->shift + extra_shift)) - & ((1 << operand->bits) - 1)); - (*info->fprintf_func) (info->stream, "a%d", value); - } - - else if ((operand->flags & MN10200_OPERAND_PSW) != 0) - (*info->fprintf_func) (info->stream, "psw"); - - else if ((operand->flags & MN10200_OPERAND_MDR) != 0) - (*info->fprintf_func) (info->stream, "mdr"); - - else if ((operand->flags & MN10200_OPERAND_PAREN) != 0) - { - if (paren) - (*info->fprintf_func) (info->stream, ")"); - else - { - (*info->fprintf_func) (info->stream, "("); - nocomma = 1; - } - paren = !paren; - } - - else if ((operand->flags & MN10200_OPERAND_PCREL) != 0) - (*info->print_address_func) ((value + memaddr + mysize) & 0xffffff, info); - - else if ((operand->flags & MN10200_OPERAND_MEMADDR) != 0) - (*info->print_address_func) (value, info); - - else - (*info->fprintf_func) (info->stream, "%ld", value); - } - /* All done. */ - break; - } - op++; - } - - if (!match) - { - (*info->fprintf_func) (info->stream, _("unknown\t0x%04lx"), insn); - } -} diff -uprN binutils-2.16.91.0.1/opcodes/m10300-dis.c binutils-2.16.91.0.2/opcodes/m10300-dis.c --- binutils-2.16.91.0.1/opcodes/m10300-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/m10300-dis.c 2005-07-20 12:27:28.743953814 -0700 @@ -1,21 +1,21 @@ /* Disassemble MN10300 instructions. - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003 + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2005 Free Software Foundation, Inc. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include @@ -24,202 +24,17 @@ Foundation, Inc., 51 Franklin Street - F #include "dis-asm.h" #include "opintl.h" -static void disassemble PARAMS ((bfd_vma, struct disassemble_info *, - unsigned long insn, unsigned int)); - #define HAVE_AM33_2 (info->mach == AM33_2) -#define HAVE_AM33 (info->mach == AM33 || HAVE_AM33_2) -#define HAVE_AM30 (info->mach == AM30) - -int -print_insn_mn10300 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - int status; - bfd_byte buffer[4]; - unsigned long insn; - unsigned int consume; - - /* First figure out how big the opcode is. */ - status = (*info->read_memory_func) (memaddr, buffer, 1, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn = *(unsigned char *) buffer; - - /* These are one byte insns. */ - if ((insn & 0xf3) == 0x00 - || (insn & 0xf0) == 0x10 - || (insn & 0xfc) == 0x3c - || (insn & 0xf3) == 0x41 - || (insn & 0xf3) == 0x40 - || (insn & 0xfc) == 0x50 - || (insn & 0xfc) == 0x54 - || (insn & 0xf0) == 0x60 - || (insn & 0xf0) == 0x70 - || ((insn & 0xf0) == 0x80 - && (insn & 0x0c) >> 2 != (insn & 0x03)) - || ((insn & 0xf0) == 0x90 - && (insn & 0x0c) >> 2 != (insn & 0x03)) - || ((insn & 0xf0) == 0xa0 - && (insn & 0x0c) >> 2 != (insn & 0x03)) - || ((insn & 0xf0) == 0xb0 - && (insn & 0x0c) >> 2 != (insn & 0x03)) - || (insn & 0xff) == 0xcb - || (insn & 0xfc) == 0xd0 - || (insn & 0xfc) == 0xd4 - || (insn & 0xfc) == 0xd8 - || (insn & 0xf0) == 0xe0 - || (insn & 0xff) == 0xff) - { - consume = 1; - } - - /* These are two byte insns. */ - else if ((insn & 0xf0) == 0x80 - || (insn & 0xf0) == 0x90 - || (insn & 0xf0) == 0xa0 - || (insn & 0xf0) == 0xb0 - || (insn & 0xfc) == 0x20 - || (insn & 0xfc) == 0x28 - || (insn & 0xf3) == 0x43 - || (insn & 0xf3) == 0x42 - || (insn & 0xfc) == 0x58 - || (insn & 0xfc) == 0x5c - || ((insn & 0xf0) == 0xc0 - && (insn & 0xff) != 0xcb - && (insn & 0xff) != 0xcc - && (insn & 0xff) != 0xcd) - || (insn & 0xff) == 0xf0 - || (insn & 0xff) == 0xf1 - || (insn & 0xff) == 0xf2 - || (insn & 0xff) == 0xf3 - || (insn & 0xff) == 0xf4 - || (insn & 0xff) == 0xf5 - || (insn & 0xff) == 0xf6) - { - status = (*info->read_memory_func) (memaddr, buffer, 2, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn = bfd_getb16 (buffer); - consume = 2; - } - - /* These are three byte insns. */ - else if ((insn & 0xff) == 0xf8 - || (insn & 0xff) == 0xcc - || (insn & 0xff) == 0xf9 - || (insn & 0xf3) == 0x01 - || (insn & 0xf3) == 0x02 - || (insn & 0xf3) == 0x03 - || (insn & 0xfc) == 0x24 - || (insn & 0xfc) == 0x2c - || (insn & 0xfc) == 0x30 - || (insn & 0xfc) == 0x34 - || (insn & 0xfc) == 0x38 - || (insn & 0xff) == 0xde - || (insn & 0xff) == 0xdf - || (insn & 0xff) == 0xf9 - || (insn & 0xff) == 0xcc) - { - status = (*info->read_memory_func) (memaddr, buffer, 2, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn = bfd_getb16 (buffer); - insn <<= 8; - status = (*info->read_memory_func) (memaddr + 2, buffer, 1, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn |= *(unsigned char *) buffer; - consume = 3; - } - - /* These are four byte insns. */ - else if ((insn & 0xff) == 0xfa - || (insn & 0xff) == 0xf7 - || (insn & 0xff) == 0xfb) - { - status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn = bfd_getb32 (buffer); - consume = 4; - } - - /* These are five byte insns. */ - else if ((insn & 0xff) == 0xcd - || (insn & 0xff) == 0xdc) - { - status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - insn = bfd_getb32 (buffer); - consume = 5; - } - - /* These are six byte insns. */ - else if ((insn & 0xff) == 0xfd - || (insn & 0xff) == 0xfc) - { - status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - - insn = bfd_getb32 (buffer); - consume = 6; - } - - /* Else its a seven byte insns (in theory). */ - else - { - status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - - insn = bfd_getb32 (buffer); - consume = 7; - /* Handle the 5-byte extended instruction codes. */ - if ((insn & 0xfff80000) == 0xfe800000) - consume = 5; - } - - disassemble (memaddr, info, insn, consume); - - return consume; -} +#define HAVE_AM33 (info->mach == AM33 || HAVE_AM33_2) +#define HAVE_AM30 (info->mach == AM30) static void -disassemble (memaddr, info, insn, size) - bfd_vma memaddr; - struct disassemble_info *info; - unsigned long insn; - unsigned int size; +disassemble (bfd_vma memaddr, + struct disassemble_info *info, + unsigned long insn, + unsigned int size) { - struct mn10300_opcode *op = (struct mn10300_opcode *)mn10300_opcodes; + struct mn10300_opcode *op = (struct mn10300_opcode *) mn10300_opcodes; const struct mn10300_operand *operand; bfd_byte buffer[4]; unsigned long extension = 0; @@ -282,21 +97,18 @@ disassemble (memaddr, info, insn, size) extra_shift = 0; if (size == 1 || size == 2) - { - extension = 0; - } + extension = 0; + else if (size == 3 && (op->format == FMT_D1 || op->opcode == 0xdf0000 || op->opcode == 0xde0000)) - { - extension = 0; - } + extension = 0; + else if (size == 3 && op->format == FMT_D6) - { - extension = 0; - } + extension = 0; + else if (size == 3) { insn &= 0xff0000; @@ -314,15 +126,13 @@ disassemble (memaddr, info, insn, size) && (op->opcode == 0xfaf80000 || op->opcode == 0xfaf00000 || op->opcode == 0xfaf40000)) - { - extension = 0; - } + extension = 0; + else if (size == 4 && (op->format == FMT_D7 || op->format == FMT_D10)) - { - extension = 0; - } + extension = 0; + else if (size == 4) { insn &= 0xffff0000; @@ -339,6 +149,7 @@ disassemble (memaddr, info, insn, size) else if (size == 5 && op->opcode == 0xdc000000) { unsigned long temp = 0; + status = (*info->read_memory_func) (memaddr + 1, buffer, 4, info); if (status != 0) { @@ -373,6 +184,7 @@ disassemble (memaddr, info, insn, size) else if (size == 5) { unsigned long temp = 0; + status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info); if (status != 0) { @@ -414,6 +226,7 @@ disassemble (memaddr, info, insn, size) else if (size == 6) { unsigned long temp = 0; + status = (*info->read_memory_func) (memaddr + 2, buffer, 4, info); if (status != 0) { @@ -442,6 +255,7 @@ disassemble (memaddr, info, insn, size) else if (size == 7 && op->opcode == 0xdd000000) { unsigned long temp = 0; + status = (*info->read_memory_func) (memaddr + 1, buffer, 4, info); if (status != 0) { @@ -465,6 +279,7 @@ disassemble (memaddr, info, insn, size) else if (size == 7) { unsigned long temp = 0; + status = (*info->read_memory_func) (memaddr + 2, buffer, 4, info); if (status != 0) { @@ -506,6 +321,7 @@ disassemble (memaddr, info, insn, size) if ((operand->flags & MN10300_OPERAND_SPLIT) != 0) { unsigned long temp; + value = insn & ((1 << operand->bits) - 1); value <<= (32 - operand->bits); temp = extension >> operand->shift; @@ -517,6 +333,7 @@ disassemble (memaddr, info, insn, size) else if ((operand->flags & MN10300_OPERAND_24BIT) != 0) { unsigned long temp; + value = insn & ((1 << operand->bits) - 1); value <<= (24 - operand->bits); temp = extension >> operand->shift; @@ -572,15 +389,12 @@ disassemble (memaddr, info, insn, size) | ((insn >> shl_low) & mask_low)); } else if ((operand->flags & MN10300_OPERAND_EXTENDED) != 0) - { - value = ((extension >> (operand->shift)) - & ((1 << operand->bits) - 1)); - } + value = ((extension >> (operand->shift)) + & ((1 << operand->bits) - 1)); + else - { - value = ((insn >> (operand->shift)) - & ((1 << operand->bits) - 1)); - } + value = ((insn >> (operand->shift)) + & ((1 << operand->bits) - 1)); if ((operand->flags & MN10300_OPERAND_SIGNED) != 0 /* These are properly extended by the code above. */ @@ -635,7 +449,7 @@ disassemble (memaddr, info, insn, size) value = ((insn >> (operand->shift + extra_shift)) & ((1 << operand->bits) - 1)); if (value == 0) - (*info->fprintf_func) (info->stream, "sp", value); + (*info->fprintf_func) (info->stream, "sp"); else (*info->fprintf_func) (info->stream, "xr%d", (int) value); } @@ -762,8 +576,185 @@ disassemble (memaddr, info, insn, size) } if (!match) + /* xgettext:c-format */ + (*info->fprintf_func) (info->stream, _("unknown\t0x%04lx"), insn); +} + +int +print_insn_mn10300 (bfd_vma memaddr, struct disassemble_info *info) +{ + int status; + bfd_byte buffer[4]; + unsigned long insn; + unsigned int consume; + + /* First figure out how big the opcode is. */ + status = (*info->read_memory_func) (memaddr, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = *(unsigned char *) buffer; + + /* These are one byte insns. */ + if ((insn & 0xf3) == 0x00 + || (insn & 0xf0) == 0x10 + || (insn & 0xfc) == 0x3c + || (insn & 0xf3) == 0x41 + || (insn & 0xf3) == 0x40 + || (insn & 0xfc) == 0x50 + || (insn & 0xfc) == 0x54 + || (insn & 0xf0) == 0x60 + || (insn & 0xf0) == 0x70 + || ((insn & 0xf0) == 0x80 + && (insn & 0x0c) >> 2 != (insn & 0x03)) + || ((insn & 0xf0) == 0x90 + && (insn & 0x0c) >> 2 != (insn & 0x03)) + || ((insn & 0xf0) == 0xa0 + && (insn & 0x0c) >> 2 != (insn & 0x03)) + || ((insn & 0xf0) == 0xb0 + && (insn & 0x0c) >> 2 != (insn & 0x03)) + || (insn & 0xff) == 0xcb + || (insn & 0xfc) == 0xd0 + || (insn & 0xfc) == 0xd4 + || (insn & 0xfc) == 0xd8 + || (insn & 0xf0) == 0xe0 + || (insn & 0xff) == 0xff) { - /* xgettext:c-format */ - (*info->fprintf_func) (info->stream, _("unknown\t0x%04x"), insn); + consume = 1; } + + /* These are two byte insns. */ + else if ((insn & 0xf0) == 0x80 + || (insn & 0xf0) == 0x90 + || (insn & 0xf0) == 0xa0 + || (insn & 0xf0) == 0xb0 + || (insn & 0xfc) == 0x20 + || (insn & 0xfc) == 0x28 + || (insn & 0xf3) == 0x43 + || (insn & 0xf3) == 0x42 + || (insn & 0xfc) == 0x58 + || (insn & 0xfc) == 0x5c + || ((insn & 0xf0) == 0xc0 + && (insn & 0xff) != 0xcb + && (insn & 0xff) != 0xcc + && (insn & 0xff) != 0xcd) + || (insn & 0xff) == 0xf0 + || (insn & 0xff) == 0xf1 + || (insn & 0xff) == 0xf2 + || (insn & 0xff) == 0xf3 + || (insn & 0xff) == 0xf4 + || (insn & 0xff) == 0xf5 + || (insn & 0xff) == 0xf6) + { + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb16 (buffer); + consume = 2; + } + + /* These are three byte insns. */ + else if ((insn & 0xff) == 0xf8 + || (insn & 0xff) == 0xcc + || (insn & 0xff) == 0xf9 + || (insn & 0xf3) == 0x01 + || (insn & 0xf3) == 0x02 + || (insn & 0xf3) == 0x03 + || (insn & 0xfc) == 0x24 + || (insn & 0xfc) == 0x2c + || (insn & 0xfc) == 0x30 + || (insn & 0xfc) == 0x34 + || (insn & 0xfc) == 0x38 + || (insn & 0xff) == 0xde + || (insn & 0xff) == 0xdf + || (insn & 0xff) == 0xf9 + || (insn & 0xff) == 0xcc) + { + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb16 (buffer); + insn <<= 8; + status = (*info->read_memory_func) (memaddr + 2, buffer, 1, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn |= *(unsigned char *) buffer; + consume = 3; + } + + /* These are four byte insns. */ + else if ((insn & 0xff) == 0xfa + || (insn & 0xff) == 0xf7 + || (insn & 0xff) == 0xfb) + { + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb32 (buffer); + consume = 4; + } + + /* These are five byte insns. */ + else if ((insn & 0xff) == 0xcd + || (insn & 0xff) == 0xdc) + { + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb32 (buffer); + consume = 5; + } + + /* These are six byte insns. */ + else if ((insn & 0xff) == 0xfd + || (insn & 0xff) == 0xfc) + { + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + insn = bfd_getb32 (buffer); + consume = 6; + } + + /* Else its a seven byte insns (in theory). */ + else + { + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + insn = bfd_getb32 (buffer); + consume = 7; + /* Handle the 5-byte extended instruction codes. */ + if ((insn & 0xfff80000) == 0xfe800000) + consume = 5; + } + + disassemble (memaddr, info, insn, consume); + + return consume; } diff -uprN binutils-2.16.91.0.1/opcodes/m32c-asm.c binutils-2.16.91.0.2/opcodes/m32c-asm.c --- binutils-2.16.91.0.1/opcodes/m32c-asm.c 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/opcodes/m32c-asm.c 2005-07-20 12:27:28.747953155 -0700 @@ -0,0 +1,1761 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. + + This file is part of the GNU Binutils and GDB, the GNU debugger. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "m32c-desc.h" +#include "m32c-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ +#include "safe-ctype.h" + +#define MACH_M32C 5 /* Must match md_begin. */ + +static int +m32c_cgen_isa_register (const char **strp) + { + int u; + const char *s = *strp; + static char * m32c_register_names [] = + { + "r0", "r1", "r2", "r3", "r0l", "r0h", "r1l", "r1h", + "a0", "a1", "r2r0", "r3r1", "sp", "fb", "dct0", "dct1", "flg", "svf", + "drc0", "drc1", "dmd0", "dmd1", "intb", "svp", "vct", "isp", "dma0", + "dma1", "dra0", "dra1", "dsa0", "dsa1", 0 + }; + + for (u = 0; m32c_register_names[u]; u++) + { + int len = strlen (m32c_register_names[u]); + + if (memcmp (m32c_register_names[u], s, len) == 0 + && (s[len] == 0 || ! ISALNUM (s[len]))) + return 1; + } + return 0; +} + +#define PARSE_UNSIGNED \ + do \ + { \ + /* Don't successfully parse literals beginning with '['. */ \ + if (**strp == '[') \ + return "Invalid literal"; /* Anything -- will not be seen. */ \ + \ + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);\ + if (errmsg) \ + return errmsg; \ + } \ + while (0) + +#define PARSE_SIGNED \ + do \ + { \ + /* Don't successfully parse literals beginning with '['. */ \ + if (**strp == '[') \ + return "Invalid literal"; /* Anything -- will not be seen. */ \ + \ + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); \ + if (errmsg) \ + return errmsg; \ + } \ + while (0) + +static const char * +parse_unsigned6 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value; + + PARSE_UNSIGNED; + + if (value > 0x3f) + return _("imm:6 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_unsigned8 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value; + long have_zero = 0; + + if (strncmp (*strp, "0x0", 3) == 0 + || (**strp == '0' && *(*strp + 1) != 'x')) + have_zero = 1; + + PARSE_UNSIGNED; + + if (value > 0xff) + return _("dsp:8 immediate is out of range"); + + /* If this field may require a relocation then use larger dsp16. */ + if (! have_zero && value == 0) + return _("dsp:8 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_signed4 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + long have_zero = 0; + + if (strncmp (*strp, "0x0", 3) == 0 + || (**strp == '0' && *(*strp + 1) != 'x')) + have_zero = 1; + + PARSE_SIGNED; + + if (value < -8 || value > 7) + return _("Immediate is out of range -8 to 7"); + + /* If this field may require a relocation then use larger dsp16. */ + if (! have_zero && value == 0) + return _("Immediate is out of range -8 to 7"); + + *valuep = value; + return 0; +} + +static const char * +parse_signed8 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + + PARSE_SIGNED; + + if (value <= 255 && value > 127) + value -= 0x100; + + if (value < -128 || value > 127) + return _("dsp:8 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_unsigned16 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value; + long have_zero = 0; + + /* Don't successfully parse literals beginning with '['. */ + if (**strp == '[') + return "Invalid literal"; /* Anything -- will not be seen. */ + + /* Don't successfully parse register names. */ + if (m32c_cgen_isa_register (strp)) + return "Invalid literal"; /* Anything -- will not be seen. */ + + if (strncmp (*strp, "0x0", 3) == 0 + || (**strp == '0' && *(*strp + 1) != 'x')) + have_zero = 1; + + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value > 0xffff) + return _("dsp:16 immediate is out of range"); + + /* If this field may require a relocation then use larger dsp24. */ + if (cd->machs == MACH_M32C && ! have_zero && value == 0 + && (strncmp (*strp, "[a", 2) == 0 + || **strp == ',' + || **strp == 0)) + return _("dsp:16 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_signed16 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + + PARSE_SIGNED; + + if (value <= 65535 && value > 32767) + value -= 0x10000; + + if (value < -32768 || value > 32767) + return _("dsp:16 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_unsigned20 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value; + + /* Don't successfully parse literals beginning with '['. */ + if (**strp == '[') + return "Invalid literal"; /* Anything -- will not be seen. */ + + /* Don't successfully parse register names. */ + if (m32c_cgen_isa_register (strp)) + return "Invalid literal"; /* Anything -- will not be seen. */ + + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value > 0xfffff) + return _("dsp:20 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_unsigned24 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value; + + /* Don't successfully parse literals beginning with '['. */ + if (**strp == '[') + return "Invalid literal"; /* Anything -- will not be seen. */ + + /* Don't successfully parse register names. */ + if (m32c_cgen_isa_register (strp)) + return "Invalid literal"; /* Anything -- will not be seen. */ + + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value > 0xffffff) + return _("dsp:24 immediate is out of range"); + + *valuep = value; + return 0; +} + +static const char * +parse_signed32 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + *valuep = value; + return 0; +} + +static const char * +parse_imm1_S (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value < 1 || value > 2) + return _("immediate is out of range 1-2"); + + *valuep = value; + return 0; +} + +static const char * +parse_imm3_S (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value < 1 || value > 8) + return _("immediate is out of range 1-8"); + + *valuep = value; + return 0; +} + +static const char * +parse_lab_5_3 (CGEN_CPU_DESC cd, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + int opinfo, + enum cgen_parse_operand_result *type_addr, + unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value; + enum cgen_parse_operand_result op_res; + + errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_5_3, + opinfo, & op_res, & value); + + if (type_addr) + *type_addr = op_res; + + if (op_res == CGEN_PARSE_OPERAND_ADDRESS) + { + /* This is a hack; the field cannot handle near-zero signed + offsets that CGEN wants to put in to indicate an "empty" + operand at first. */ + *valuep = 2; + return 0; + } + if (errmsg) + return errmsg; + + if (value < 2 || value > 9) + return _("immediate is out of range 2-9"); + + *valuep = value; + return 0; +} + +static const char * +parse_Bitno16R (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value; + + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); + if (errmsg) + return errmsg; + + if (value > 15) + return _("Bit number for indexing general register is out of range 0-15"); + + *valuep = value; + return 0; +} + +static const char * +parse_unsigned_bitbase (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep, + unsigned bits) +{ + const char *errmsg = 0; + unsigned long bit; + unsigned long base; + const char *newp = *strp; + unsigned long long bitbase; + + errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & bit); + if (errmsg) + return errmsg; + + if (*newp != ',') + return "Missing base for bit,base:8"; + + ++newp; + errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & base); + if (errmsg) + return errmsg; + + bitbase = (unsigned long long) bit + ((unsigned long long) base * 8); + + if (bitbase >= (1ull << bits)) + return _("bit,base is out of range"); + + *valuep = bitbase; + *strp = newp; + return 0; +} + +static const char * +parse_signed_bitbase (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep, + unsigned bits) +{ + const char *errmsg = 0; + unsigned long bit; + signed long base; + const char *newp = *strp; + long long bitbase; + long long limit; + + errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & bit); + if (errmsg) + return errmsg; + + if (*newp != ',') + return "Missing base for bit,base:8"; + + ++newp; + errmsg = cgen_parse_signed_integer (cd, & newp, opindex, & base); + if (errmsg) + return errmsg; + + bitbase = (long long)bit + ((long long)base * 8); + + limit = 1ll << (bits - 1); + if (bitbase < -limit || bitbase >= limit) + return _("bit,base is out of range"); + + *valuep = bitbase; + *strp = newp; + return 0; +} + +static const char * +parse_unsigned_bitbase8 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + return parse_unsigned_bitbase (cd, strp, opindex, valuep, 8); +} + +static const char * +parse_unsigned_bitbase11 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + return parse_unsigned_bitbase (cd, strp, opindex, valuep, 11); +} + +static const char * +parse_unsigned_bitbase16 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + return parse_unsigned_bitbase (cd, strp, opindex, valuep, 16); +} + +static const char * +parse_unsigned_bitbase19 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + return parse_unsigned_bitbase (cd, strp, opindex, valuep, 19); +} + +static const char * +parse_unsigned_bitbase27 (CGEN_CPU_DESC cd, const char **strp, + int opindex, unsigned long *valuep) +{ + return parse_unsigned_bitbase (cd, strp, opindex, valuep, 27); +} + +static const char * +parse_signed_bitbase8 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + return parse_signed_bitbase (cd, strp, opindex, valuep, 8); +} + +static const char * +parse_signed_bitbase11 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + return parse_signed_bitbase (cd, strp, opindex, valuep, 11); +} + +static const char * +parse_signed_bitbase19 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + return parse_signed_bitbase (cd, strp, opindex, valuep, 19); +} + +/* Parse the suffix as : or as nothing followed by a whitespace. */ + +static const char * +parse_suffix (const char **strp, char suffix) +{ + const char *newp = *strp; + + if (**strp == ':' && TOLOWER (*(*strp + 1)) == suffix) + newp = *strp + 2; + + if (ISSPACE (*newp)) + { + *strp = newp; + return 0; + } + + return "Invalid suffix"; /* Anything -- will not be seen. */ +} + +static const char * +parse_S (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) +{ + return parse_suffix (strp, 's'); +} + +static const char * +parse_G (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) +{ + return parse_suffix (strp, 'g'); +} + +static const char * +parse_Q (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) +{ + return parse_suffix (strp, 'q'); +} + +static const char * +parse_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) +{ + return parse_suffix (strp, 'z'); +} + +/* Parse an empty suffix. Fail if the next char is ':'. */ + +static const char * +parse_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) +{ + if (**strp == ':') + return "Unexpected suffix"; + return 0; +} + +static const char * +parse_r0l_r0h (CGEN_CPU_DESC cd, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep) +{ + const char *errmsg; + signed long value; + signed long junk; + const char *newp = *strp; + + /* Parse r0[hl]. */ + errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0l_r0h, & value); + if (errmsg) + return errmsg; + + if (*newp != ',') + return _("not a valid r0l/r0h pair"); + ++newp; + + /* Parse the second register in the pair. */ + if (value == 0) /* r0l */ + errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0h, & junk); + else + errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0l, & junk); + if (errmsg) + return errmsg; + + *strp = newp; + *valuep = ! value; + return 0; +} + +/* Accept .b or .w in any case. */ + +static const char * +parse_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, + int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) +{ + if (**strp == '.' + && (*(*strp + 1) == 'b' || *(*strp + 1) == 'B' + || *(*strp + 1) == 'w' || *(*strp + 1) == 'W')) + { + *strp += 2; + return NULL; + } + + return _("Invalid size specifier"); +} + +/* Special check to ensure that instruction exists for given machine. */ + +int +m32c_cgen_insn_supported (CGEN_CPU_DESC cd, + const CGEN_INSN *insn) +{ + int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); + int isas = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ISA); + + /* If attributes are absent, assume no restriction. */ + if (machs == 0) + machs = ~0; + + return ((machs & cd->machs) + && (isas & cd->isas)); +} + +/* Parse a set of registers, R0,R1,A0,A1,SB,FB. */ + +static const char * +parse_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + unsigned long *valuep, + int push) +{ + const char *errmsg = 0; + int regno = 0; + + *valuep = 0; + while (**strp && **strp != ')') + { + if (**strp == 'r' || **strp == 'R') + { + ++*strp; + regno = **strp - '0'; + if (regno > 4) + errmsg = _("Register number is not valid"); + } + else if (**strp == 'a' || **strp == 'A') + { + ++*strp; + regno = **strp - '0'; + if (regno > 2) + errmsg = _("Register number is not valid"); + regno = **strp - '0' + 4; + } + + else if (strncasecmp (*strp, "sb", 2) == 0 || strncasecmp (*strp, "SB", 2) == 0) + { + regno = 6; + ++*strp; + } + + else if (strncasecmp (*strp, "fb", 2) == 0 || strncasecmp (*strp, "FB", 2) == 0) + { + regno = 7; + ++*strp; + } + + if (push) /* Mask is reversed for push. */ + *valuep |= 0x80 >> regno; + else + *valuep |= 1 << regno; + + ++*strp; + if (**strp == ',') + { + if (*(*strp + 1) == ')') + break; + ++*strp; + } + } + + if (!*strp) + errmsg = _("Register list is not valid"); + + return errmsg; +} + +#define POP 0 +#define PUSH 1 + +static const char * +parse_pop_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + unsigned long *valuep) +{ + return parse_regset (cd, strp, opindex, valuep, POP); +} + +static const char * +parse_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + unsigned long *valuep) +{ + return parse_regset (cd, strp, opindex, valuep, PUSH); +} + +/* -- dis.c */ + +const char * m32c_cgen_parse_operand + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +m32c_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case M32C_OPERAND_A0 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_a0, & junk); + break; + case M32C_OPERAND_A1 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_a1, & junk); + break; + case M32C_OPERAND_AN16_PUSH_S : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_4_1); + break; + case M32C_OPERAND_BIT16AN : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_dst16_an); + break; + case M32C_OPERAND_BIT16RN : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_HI, & fields->f_dst16_rn); + break; + case M32C_OPERAND_BIT32ANPREFIXED : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_dst32_an_prefixed); + break; + case M32C_OPERAND_BIT32ANUNPREFIXED : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_BIT32RNPREFIXED : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_QI, & fields->f_dst32_rn_prefixed_QI); + break; + case M32C_OPERAND_BIT32RNUNPREFIXED : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_QI, & fields->f_dst32_rn_unprefixed_QI); + break; + case M32C_OPERAND_BITBASE16_16_S8 : + errmsg = parse_signed_bitbase8 (cd, strp, M32C_OPERAND_BITBASE16_16_S8, (long *) (& fields->f_dsp_16_s8)); + break; + case M32C_OPERAND_BITBASE16_16_U16 : + errmsg = parse_unsigned_bitbase16 (cd, strp, M32C_OPERAND_BITBASE16_16_U16, (unsigned long *) (& fields->f_dsp_16_u16)); + break; + case M32C_OPERAND_BITBASE16_16_U8 : + errmsg = parse_unsigned_bitbase8 (cd, strp, M32C_OPERAND_BITBASE16_16_U8, (unsigned long *) (& fields->f_dsp_16_u8)); + break; + case M32C_OPERAND_BITBASE16_8_U11_S : + errmsg = parse_unsigned_bitbase11 (cd, strp, M32C_OPERAND_BITBASE16_8_U11_S, (unsigned long *) (& fields->f_bitbase16_u11_S)); + break; + case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED : + errmsg = parse_signed_bitbase11 (cd, strp, M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, (long *) (& fields->f_bitbase32_16_s11_unprefixed)); + break; + case M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED : + errmsg = parse_signed_bitbase19 (cd, strp, M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, (long *) (& fields->f_bitbase32_16_s19_unprefixed)); + break; + case M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED : + errmsg = parse_unsigned_bitbase11 (cd, strp, M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, (unsigned long *) (& fields->f_bitbase32_16_u11_unprefixed)); + break; + case M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED : + errmsg = parse_unsigned_bitbase19 (cd, strp, M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, (unsigned long *) (& fields->f_bitbase32_16_u19_unprefixed)); + break; + case M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED : + errmsg = parse_unsigned_bitbase27 (cd, strp, M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, (unsigned long *) (& fields->f_bitbase32_16_u27_unprefixed)); + break; + case M32C_OPERAND_BITBASE32_24_S11_PREFIXED : + errmsg = parse_signed_bitbase11 (cd, strp, M32C_OPERAND_BITBASE32_24_S11_PREFIXED, (long *) (& fields->f_bitbase32_24_s11_prefixed)); + break; + case M32C_OPERAND_BITBASE32_24_S19_PREFIXED : + errmsg = parse_signed_bitbase19 (cd, strp, M32C_OPERAND_BITBASE32_24_S19_PREFIXED, (long *) (& fields->f_bitbase32_24_s19_prefixed)); + break; + case M32C_OPERAND_BITBASE32_24_U11_PREFIXED : + errmsg = parse_unsigned_bitbase11 (cd, strp, M32C_OPERAND_BITBASE32_24_U11_PREFIXED, (unsigned long *) (& fields->f_bitbase32_24_u11_prefixed)); + break; + case M32C_OPERAND_BITBASE32_24_U19_PREFIXED : + errmsg = parse_unsigned_bitbase19 (cd, strp, M32C_OPERAND_BITBASE32_24_U19_PREFIXED, (unsigned long *) (& fields->f_bitbase32_24_u19_prefixed)); + break; + case M32C_OPERAND_BITBASE32_24_U27_PREFIXED : + errmsg = parse_unsigned_bitbase27 (cd, strp, M32C_OPERAND_BITBASE32_24_U27_PREFIXED, (unsigned long *) (& fields->f_bitbase32_24_u27_prefixed)); + break; + case M32C_OPERAND_BITNO16R : + errmsg = parse_Bitno16R (cd, strp, M32C_OPERAND_BITNO16R, (unsigned long *) (& fields->f_dsp_16_u8)); + break; + case M32C_OPERAND_BITNO32PREFIXED : + errmsg = cgen_parse_unsigned_integer (cd, strp, M32C_OPERAND_BITNO32PREFIXED, (unsigned long *) (& fields->f_bitno32_prefixed)); + break; + case M32C_OPERAND_BITNO32UNPREFIXED : + errmsg = cgen_parse_unsigned_integer (cd, strp, M32C_OPERAND_BITNO32UNPREFIXED, (unsigned long *) (& fields->f_bitno32_unprefixed)); + break; + case M32C_OPERAND_DSP_10_U6 : + errmsg = parse_unsigned6 (cd, strp, M32C_OPERAND_DSP_10_U6, (unsigned long *) (& fields->f_dsp_10_u6)); + break; + case M32C_OPERAND_DSP_16_S16 : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_DSP_16_S16, (long *) (& fields->f_dsp_16_s16)); + break; + case M32C_OPERAND_DSP_16_S8 : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_16_S8, (long *) (& fields->f_dsp_16_s8)); + break; + case M32C_OPERAND_DSP_16_U16 : + errmsg = parse_unsigned16 (cd, strp, M32C_OPERAND_DSP_16_U16, (unsigned long *) (& fields->f_dsp_16_u16)); + break; + case M32C_OPERAND_DSP_16_U20 : + errmsg = parse_unsigned20 (cd, strp, M32C_OPERAND_DSP_16_U20, (unsigned long *) (& fields->f_dsp_16_u24)); + break; + case M32C_OPERAND_DSP_16_U24 : + errmsg = parse_unsigned24 (cd, strp, M32C_OPERAND_DSP_16_U24, (unsigned long *) (& fields->f_dsp_16_u24)); + break; + case M32C_OPERAND_DSP_16_U8 : + errmsg = parse_unsigned8 (cd, strp, M32C_OPERAND_DSP_16_U8, (unsigned long *) (& fields->f_dsp_16_u8)); + break; + case M32C_OPERAND_DSP_24_S16 : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_DSP_24_S16, (long *) (& fields->f_dsp_24_s16)); + break; + case M32C_OPERAND_DSP_24_S8 : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_24_S8, (long *) (& fields->f_dsp_24_s8)); + break; + case M32C_OPERAND_DSP_24_U16 : + errmsg = parse_unsigned16 (cd, strp, M32C_OPERAND_DSP_24_U16, (unsigned long *) (& fields->f_dsp_24_u16)); + break; + case M32C_OPERAND_DSP_24_U20 : + errmsg = parse_unsigned20 (cd, strp, M32C_OPERAND_DSP_24_U20, (unsigned long *) (& fields->f_dsp_24_u24)); + break; + case M32C_OPERAND_DSP_24_U24 : + errmsg = parse_unsigned24 (cd, strp, M32C_OPERAND_DSP_24_U24, (unsigned long *) (& fields->f_dsp_24_u24)); + break; + case M32C_OPERAND_DSP_24_U8 : + errmsg = parse_unsigned8 (cd, strp, M32C_OPERAND_DSP_24_U8, (unsigned long *) (& fields->f_dsp_24_u8)); + break; + case M32C_OPERAND_DSP_32_S16 : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_DSP_32_S16, (long *) (& fields->f_dsp_32_s16)); + break; + case M32C_OPERAND_DSP_32_S8 : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_32_S8, (long *) (& fields->f_dsp_32_s8)); + break; + case M32C_OPERAND_DSP_32_U16 : + errmsg = parse_unsigned16 (cd, strp, M32C_OPERAND_DSP_32_U16, (unsigned long *) (& fields->f_dsp_32_u16)); + break; + case M32C_OPERAND_DSP_32_U20 : + errmsg = parse_unsigned20 (cd, strp, M32C_OPERAND_DSP_32_U20, (unsigned long *) (& fields->f_dsp_32_u24)); + break; + case M32C_OPERAND_DSP_32_U24 : + errmsg = parse_unsigned24 (cd, strp, M32C_OPERAND_DSP_32_U24, (unsigned long *) (& fields->f_dsp_32_u24)); + break; + case M32C_OPERAND_DSP_32_U8 : + errmsg = parse_unsigned8 (cd, strp, M32C_OPERAND_DSP_32_U8, (unsigned long *) (& fields->f_dsp_32_u8)); + break; + case M32C_OPERAND_DSP_40_S16 : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_DSP_40_S16, (long *) (& fields->f_dsp_40_s16)); + break; + case M32C_OPERAND_DSP_40_S8 : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_40_S8, (long *) (& fields->f_dsp_40_s8)); + break; + case M32C_OPERAND_DSP_40_U16 : + errmsg = parse_unsigned16 (cd, strp, M32C_OPERAND_DSP_40_U16, (unsigned long *) (& fields->f_dsp_40_u16)); + break; + case M32C_OPERAND_DSP_40_U24 : + errmsg = parse_unsigned24 (cd, strp, M32C_OPERAND_DSP_40_U24, (unsigned long *) (& fields->f_dsp_40_u24)); + break; + case M32C_OPERAND_DSP_40_U8 : + errmsg = parse_unsigned8 (cd, strp, M32C_OPERAND_DSP_40_U8, (unsigned long *) (& fields->f_dsp_40_u8)); + break; + case M32C_OPERAND_DSP_48_S16 : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_DSP_48_S16, (long *) (& fields->f_dsp_48_s16)); + break; + case M32C_OPERAND_DSP_48_S8 : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_48_S8, (long *) (& fields->f_dsp_48_s8)); + break; + case M32C_OPERAND_DSP_48_U16 : + errmsg = parse_unsigned16 (cd, strp, M32C_OPERAND_DSP_48_U16, (unsigned long *) (& fields->f_dsp_48_u16)); + break; + case M32C_OPERAND_DSP_48_U24 : + errmsg = parse_unsigned24 (cd, strp, M32C_OPERAND_DSP_48_U24, (unsigned long *) (& fields->f_dsp_48_u24)); + break; + case M32C_OPERAND_DSP_48_U8 : + errmsg = parse_unsigned8 (cd, strp, M32C_OPERAND_DSP_48_U8, (unsigned long *) (& fields->f_dsp_48_u8)); + break; + case M32C_OPERAND_DSP_8_S8 : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_8_S8, (long *) (& fields->f_dsp_8_s8)); + break; + case M32C_OPERAND_DSP_8_U16 : + errmsg = parse_unsigned16 (cd, strp, M32C_OPERAND_DSP_8_U16, (unsigned long *) (& fields->f_dsp_8_u16)); + break; + case M32C_OPERAND_DSP_8_U24 : + errmsg = parse_unsigned24 (cd, strp, M32C_OPERAND_DSP_8_U24, (unsigned long *) (& fields->f_dsp_8_u24)); + break; + case M32C_OPERAND_DSP_8_U6 : + errmsg = parse_unsigned6 (cd, strp, M32C_OPERAND_DSP_8_U6, (unsigned long *) (& fields->f_dsp_8_u6)); + break; + case M32C_OPERAND_DSP_8_U8 : + errmsg = parse_unsigned8 (cd, strp, M32C_OPERAND_DSP_8_U8, (unsigned long *) (& fields->f_dsp_8_u8)); + break; + case M32C_OPERAND_DST16AN : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_dst16_an); + break; + case M32C_OPERAND_DST16AN_S : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_dst16_an_s); + break; + case M32C_OPERAND_DST16ANHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_dst16_an); + break; + case M32C_OPERAND_DST16ANQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_QI, & fields->f_dst16_an); + break; + case M32C_OPERAND_DST16ANQI_S : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_QI, & fields->f_dst16_rn_QI_s); + break; + case M32C_OPERAND_DST16ANSI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_SI, & fields->f_dst16_an); + break; + case M32C_OPERAND_DST16RNEXTQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_ext_QI, & fields->f_dst16_rn_ext); + break; + case M32C_OPERAND_DST16RNHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_HI, & fields->f_dst16_rn); + break; + case M32C_OPERAND_DST16RNQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_QI, & fields->f_dst16_rn); + break; + case M32C_OPERAND_DST16RNQI_S : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r0l_r0h, & fields->f_dst16_rn_QI_s); + break; + case M32C_OPERAND_DST16RNSI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_SI, & fields->f_dst16_rn); + break; + case M32C_OPERAND_DST32ANEXTUNPREFIXED : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_DST32ANPREFIXED : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_dst32_an_prefixed); + break; + case M32C_OPERAND_DST32ANPREFIXEDHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_dst32_an_prefixed); + break; + case M32C_OPERAND_DST32ANPREFIXEDQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_QI, & fields->f_dst32_an_prefixed); + break; + case M32C_OPERAND_DST32ANPREFIXEDSI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_dst32_an_prefixed); + break; + case M32C_OPERAND_DST32ANUNPREFIXED : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_QI, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDSI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_DST32R0HI_S : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r0, & junk); + break; + case M32C_OPERAND_DST32R0QI_S : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r0l, & junk); + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_ext_HI, & fields->f_dst32_rn_ext_unprefixed); + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_ext_QI, & fields->f_dst32_rn_ext_unprefixed); + break; + case M32C_OPERAND_DST32RNPREFIXEDHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_HI, & fields->f_dst32_rn_prefixed_HI); + break; + case M32C_OPERAND_DST32RNPREFIXEDQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_QI, & fields->f_dst32_rn_prefixed_QI); + break; + case M32C_OPERAND_DST32RNPREFIXEDSI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_SI, & fields->f_dst32_rn_prefixed_SI); + break; + case M32C_OPERAND_DST32RNUNPREFIXEDHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_HI, & fields->f_dst32_rn_unprefixed_HI); + break; + case M32C_OPERAND_DST32RNUNPREFIXEDQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_QI, & fields->f_dst32_rn_unprefixed_QI); + break; + case M32C_OPERAND_DST32RNUNPREFIXEDSI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_SI, & fields->f_dst32_rn_unprefixed_SI); + break; + case M32C_OPERAND_G : + errmsg = parse_G (cd, strp, M32C_OPERAND_G, (long *) (& junk)); + break; + case M32C_OPERAND_IMM_12_S4 : + errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_12_S4, (long *) (& fields->f_imm_12_s4)); + break; + case M32C_OPERAND_IMM_13_U3 : + errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_13_U3, (long *) (& fields->f_imm_13_u3)); + break; + case M32C_OPERAND_IMM_16_HI : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_IMM_16_HI, (long *) (& fields->f_dsp_16_s16)); + break; + case M32C_OPERAND_IMM_16_QI : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_IMM_16_QI, (long *) (& fields->f_dsp_16_s8)); + break; + case M32C_OPERAND_IMM_16_SI : + errmsg = parse_signed32 (cd, strp, M32C_OPERAND_IMM_16_SI, (long *) (& fields->f_dsp_16_s32)); + break; + case M32C_OPERAND_IMM_20_S4 : + errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_20_S4, (long *) (& fields->f_imm_20_s4)); + break; + case M32C_OPERAND_IMM_24_HI : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_IMM_24_HI, (long *) (& fields->f_dsp_24_s16)); + break; + case M32C_OPERAND_IMM_24_QI : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_IMM_24_QI, (long *) (& fields->f_dsp_24_s8)); + break; + case M32C_OPERAND_IMM_24_SI : + errmsg = parse_signed32 (cd, strp, M32C_OPERAND_IMM_24_SI, (long *) (& fields->f_dsp_24_s32)); + break; + case M32C_OPERAND_IMM_32_HI : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_IMM_32_HI, (long *) (& fields->f_dsp_32_s16)); + break; + case M32C_OPERAND_IMM_32_QI : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_IMM_32_QI, (long *) (& fields->f_dsp_32_s8)); + break; + case M32C_OPERAND_IMM_32_SI : + errmsg = parse_signed32 (cd, strp, M32C_OPERAND_IMM_32_SI, (long *) (& fields->f_dsp_32_s32)); + break; + case M32C_OPERAND_IMM_40_HI : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_IMM_40_HI, (long *) (& fields->f_dsp_40_s16)); + break; + case M32C_OPERAND_IMM_40_QI : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_IMM_40_QI, (long *) (& fields->f_dsp_40_s8)); + break; + case M32C_OPERAND_IMM_40_SI : + errmsg = parse_signed32 (cd, strp, M32C_OPERAND_IMM_40_SI, (long *) (& fields->f_dsp_40_s32)); + break; + case M32C_OPERAND_IMM_48_HI : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_IMM_48_HI, (long *) (& fields->f_dsp_48_s16)); + break; + case M32C_OPERAND_IMM_48_QI : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_IMM_48_QI, (long *) (& fields->f_dsp_48_s8)); + break; + case M32C_OPERAND_IMM_48_SI : + errmsg = parse_signed32 (cd, strp, M32C_OPERAND_IMM_48_SI, (long *) (& fields->f_dsp_48_s32)); + break; + case M32C_OPERAND_IMM_56_HI : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_IMM_56_HI, (long *) (& fields->f_dsp_56_s16)); + break; + case M32C_OPERAND_IMM_56_QI : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_IMM_56_QI, (long *) (& fields->f_dsp_56_s8)); + break; + case M32C_OPERAND_IMM_64_HI : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_IMM_64_HI, (long *) (& fields->f_dsp_64_s16)); + break; + case M32C_OPERAND_IMM_8_HI : + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_IMM_8_HI, (long *) (& fields->f_dsp_8_s16)); + break; + case M32C_OPERAND_IMM_8_QI : + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_IMM_8_QI, (long *) (& fields->f_dsp_8_s8)); + break; + case M32C_OPERAND_IMM_8_S4 : + errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_8_S4, (long *) (& fields->f_imm_8_s4)); + break; + case M32C_OPERAND_IMM_SH_12_S4 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_shimm, & fields->f_imm_12_s4); + break; + case M32C_OPERAND_IMM_SH_20_S4 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_shimm, & fields->f_imm_20_s4); + break; + case M32C_OPERAND_IMM_SH_8_S4 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_shimm, & fields->f_imm_8_s4); + break; + case M32C_OPERAND_IMM1_S : + errmsg = parse_imm1_S (cd, strp, M32C_OPERAND_IMM1_S, (long *) (& fields->f_imm1_S)); + break; + case M32C_OPERAND_IMM3_S : + errmsg = parse_imm3_S (cd, strp, M32C_OPERAND_IMM3_S, (long *) (& fields->f_imm3_S)); + break; + case M32C_OPERAND_LAB_16_8 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_16_8, 0, NULL, & value); + fields->f_lab_16_8 = value; + } + break; + case M32C_OPERAND_LAB_24_8 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_24_8, 0, NULL, & value); + fields->f_lab_24_8 = value; + } + break; + case M32C_OPERAND_LAB_32_8 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_32_8, 0, NULL, & value); + fields->f_lab_32_8 = value; + } + break; + case M32C_OPERAND_LAB_40_8 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_40_8, 0, NULL, & value); + fields->f_lab_40_8 = value; + } + break; + case M32C_OPERAND_LAB_5_3 : + { + bfd_vma value = 0; + errmsg = parse_lab_5_3 (cd, strp, M32C_OPERAND_LAB_5_3, 0, NULL, & value); + fields->f_lab_5_3 = value; + } + break; + case M32C_OPERAND_LAB_8_16 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_8_16, 0, NULL, & value); + fields->f_lab_8_16 = value; + } + break; + case M32C_OPERAND_LAB_8_24 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_8_24, 0, NULL, & value); + fields->f_lab_8_24 = value; + } + break; + case M32C_OPERAND_LAB_8_8 : + { + bfd_vma value = 0; + errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_8_8, 0, NULL, & value); + fields->f_lab_8_8 = value; + } + break; + case M32C_OPERAND_LAB32_JMP_S : + { + bfd_vma value = 0; + errmsg = parse_lab_5_3 (cd, strp, M32C_OPERAND_LAB32_JMP_S, 0, NULL, & value); + fields->f_lab32_jmp_s = value; + } + break; + case M32C_OPERAND_Q : + errmsg = parse_Q (cd, strp, M32C_OPERAND_Q, (long *) (& junk)); + break; + case M32C_OPERAND_R0 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r0, & junk); + break; + case M32C_OPERAND_R0H : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r0h, & junk); + break; + case M32C_OPERAND_R0L : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r0l, & junk); + break; + case M32C_OPERAND_R1 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r1, & junk); + break; + case M32C_OPERAND_R1R2R0 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r1r2r0, & junk); + break; + case M32C_OPERAND_R2 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r2, & junk); + break; + case M32C_OPERAND_R2R0 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r2r0, & junk); + break; + case M32C_OPERAND_R3 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r3, & junk); + break; + case M32C_OPERAND_R3R1 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_r3r1, & junk); + break; + case M32C_OPERAND_REGSETPOP : + errmsg = parse_pop_regset (cd, strp, M32C_OPERAND_REGSETPOP, (unsigned long *) (& fields->f_8_8)); + break; + case M32C_OPERAND_REGSETPUSH : + errmsg = parse_push_regset (cd, strp, M32C_OPERAND_REGSETPUSH, (unsigned long *) (& fields->f_8_8)); + break; + case M32C_OPERAND_RN16_PUSH_S : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_QI, & fields->f_4_1); + break; + case M32C_OPERAND_S : + errmsg = parse_S (cd, strp, M32C_OPERAND_S, (long *) (& junk)); + break; + case M32C_OPERAND_SRC16AN : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_src16_an); + break; + case M32C_OPERAND_SRC16ANHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_src16_an); + break; + case M32C_OPERAND_SRC16ANQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_QI, & fields->f_src16_an); + break; + case M32C_OPERAND_SRC16RNHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_HI, & fields->f_src16_rn); + break; + case M32C_OPERAND_SRC16RNQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_QI, & fields->f_src16_rn); + break; + case M32C_OPERAND_SRC32ANPREFIXED : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_src32_an_prefixed); + break; + case M32C_OPERAND_SRC32ANPREFIXEDHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_src32_an_prefixed); + break; + case M32C_OPERAND_SRC32ANPREFIXEDQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_QI, & fields->f_src32_an_prefixed); + break; + case M32C_OPERAND_SRC32ANPREFIXEDSI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_src32_an_prefixed); + break; + case M32C_OPERAND_SRC32ANUNPREFIXED : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_src32_an_unprefixed); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_src32_an_unprefixed); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_QI, & fields->f_src32_an_unprefixed); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDSI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar, & fields->f_src32_an_unprefixed); + break; + case M32C_OPERAND_SRC32RNPREFIXEDHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_HI, & fields->f_src32_rn_prefixed_HI); + break; + case M32C_OPERAND_SRC32RNPREFIXEDQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_QI, & fields->f_src32_rn_prefixed_QI); + break; + case M32C_OPERAND_SRC32RNPREFIXEDSI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_SI, & fields->f_src32_rn_prefixed_SI); + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDHI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_HI, & fields->f_src32_rn_unprefixed_HI); + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDQI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_QI, & fields->f_src32_rn_unprefixed_QI); + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDSI : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_SI, & fields->f_src32_rn_unprefixed_SI); + break; + case M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL : + errmsg = parse_r0l_r0h (cd, strp, M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, (long *) (& fields->f_5_1)); + break; + case M32C_OPERAND_X : + errmsg = parse_X (cd, strp, M32C_OPERAND_X, (long *) (& junk)); + break; + case M32C_OPERAND_Z : + errmsg = parse_Z (cd, strp, M32C_OPERAND_Z, (long *) (& junk)); + break; + case M32C_OPERAND_COND16_16 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond16, & fields->f_dsp_16_u8); + break; + case M32C_OPERAND_COND16_24 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond16, & fields->f_dsp_24_u8); + break; + case M32C_OPERAND_COND16_32 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond16, & fields->f_dsp_32_u8); + break; + case M32C_OPERAND_COND16C : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond16c, & fields->f_cond16); + break; + case M32C_OPERAND_COND16J : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond16j, & fields->f_cond16); + break; + case M32C_OPERAND_COND16J5 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond16j_5, & fields->f_cond16j_5); + break; + case M32C_OPERAND_COND32 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond32, & fields->f_cond32); + break; + case M32C_OPERAND_COND32_16 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond32, & fields->f_dsp_16_u8); + break; + case M32C_OPERAND_COND32_24 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond32, & fields->f_dsp_24_u8); + break; + case M32C_OPERAND_COND32_32 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond32, & fields->f_dsp_32_u8); + break; + case M32C_OPERAND_COND32_40 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond32, & fields->f_dsp_40_u8); + break; + case M32C_OPERAND_COND32J : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond32, & fields->f_cond32j); + break; + case M32C_OPERAND_CR1_PREFIXED_32 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cr1_32, & fields->f_21_3); + break; + case M32C_OPERAND_CR1_UNPREFIXED_32 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cr1_32, & fields->f_13_3); + break; + case M32C_OPERAND_CR16 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cr_16, & fields->f_9_3); + break; + case M32C_OPERAND_CR2_32 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cr2_32, & fields->f_13_3); + break; + case M32C_OPERAND_CR3_PREFIXED_32 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cr3_32, & fields->f_21_3); + break; + case M32C_OPERAND_CR3_UNPREFIXED_32 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cr3_32, & fields->f_13_3); + break; + case M32C_OPERAND_FLAGS16 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_flags, & fields->f_9_3); + break; + case M32C_OPERAND_FLAGS32 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_flags, & fields->f_13_3); + break; + case M32C_OPERAND_SCCOND32 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_cond32, & fields->f_cond16); + break; + case M32C_OPERAND_SIZE : + errmsg = parse_size (cd, strp, M32C_OPERAND_SIZE, (long *) (& junk)); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const m32c_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +m32c_cgen_init_asm (CGEN_CPU_DESC cd) +{ + m32c_cgen_init_opcode_table (cd); + m32c_cgen_init_ibld_table (cd); + cd->parse_handlers = & m32c_cgen_parse_handlers[0]; + cd->parse_operand = m32c_cgen_parse_operand; +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by m32c_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +m32c_cgen_build_insn_regex (CGEN_INSN *insn) +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), + &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +m32c_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! m32c_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAXED attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS + const char *tmp_errmsg; + + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); +#else + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); +#endif + + *errmsg = errbuf; + return NULL; + } +} diff -uprN binutils-2.16.91.0.1/opcodes/m32c-desc.c binutils-2.16.91.0.2/opcodes/m32c-desc.c --- binutils-2.16.91.0.1/opcodes/m32c-desc.c 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/opcodes/m32c-desc.c 2005-07-20 12:27:28.950919686 -0700 @@ -0,0 +1,62619 @@ +/* CPU data for m32c. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2005 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "m32c-desc.h" +#include "m32c-opc.h" +#include "opintl.h" +#include "libiberty.h" +#include "xregex.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = +{ + { "base", MACH_BASE }, + { "m16c", MACH_M16C }, + { "m32c", MACH_M32C }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = +{ + { "m16c", ISA_M16C }, + { "m32c", ISA_M32C }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE m32c_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ISA", & ISA_attr[0], & ISA_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE m32c_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ISA", & ISA_attr[0], & ISA_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE m32c_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ISA", & ISA_attr[0], & ISA_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE m32c_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ISA", & ISA_attr[0], & ISA_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAXED", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA m32c_cgen_isa_table[] = { + { "m16c", 32, 32, 8, 56 }, + { "m32c", 32, 32, 8, 80 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH m32c_cgen_mach_table[] = { + { "m16c", "m16c", MACH_M16C, 0 }, + { "m32c", "m32c", MACH_M32C, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_entries[] = +{ + { "r0", 0, {0, {0}}, 0, 0 }, + { "r1", 1, {0, {0}}, 0, 0 }, + { "r2", 2, {0, {0}}, 0, 0 }, + { "r3", 3, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_gr = +{ + & m32c_cgen_opval_h_gr_entries[0], + 4, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_QI_entries[] = +{ + { "r0l", 0, {0, {0}}, 0, 0 }, + { "r0h", 1, {0, {0}}, 0, 0 }, + { "r1l", 2, {0, {0}}, 0, 0 }, + { "r1h", 3, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_gr_QI = +{ + & m32c_cgen_opval_h_gr_QI_entries[0], + 4, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_HI_entries[] = +{ + { "r0", 0, {0, {0}}, 0, 0 }, + { "r1", 1, {0, {0}}, 0, 0 }, + { "r2", 2, {0, {0}}, 0, 0 }, + { "r3", 3, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_gr_HI = +{ + & m32c_cgen_opval_h_gr_HI_entries[0], + 4, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_SI_entries[] = +{ + { "r2r0", 0, {0, {0}}, 0, 0 }, + { "r3r1", 1, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_gr_SI = +{ + & m32c_cgen_opval_h_gr_SI_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_QI_entries[] = +{ + { "r0l", 0, {0, {0}}, 0, 0 }, + { "r1l", 1, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_QI = +{ + & m32c_cgen_opval_h_gr_ext_QI_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_HI_entries[] = +{ + { "r0", 0, {0, {0}}, 0, 0 }, + { "r1", 1, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_HI = +{ + & m32c_cgen_opval_h_gr_ext_HI_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_entries[] = +{ + { "r0l", 0, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r0l = +{ + & m32c_cgen_opval_h_r0l_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0h_entries[] = +{ + { "r0h", 0, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r0h = +{ + & m32c_cgen_opval_h_r0h_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1l_entries[] = +{ + { "r1l", 0, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r1l = +{ + & m32c_cgen_opval_h_r1l_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1h_entries[] = +{ + { "r1h", 0, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r1h = +{ + & m32c_cgen_opval_h_r1h_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0_entries[] = +{ + { "r0", 0, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r0 = +{ + & m32c_cgen_opval_h_r0_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1_entries[] = +{ + { "r1", 0, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r1 = +{ + & m32c_cgen_opval_h_r1_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2_entries[] = +{ + { "r2", 0, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r2 = +{ + & m32c_cgen_opval_h_r2_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3_entries[] = +{ + { "r3", 0, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r3 = +{ + & m32c_cgen_opval_h_r3_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_r0h_entries[] = +{ + { "r0l", 0, {0, {0}}, 0, 0 }, + { "r0h", 1, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r0l_r0h = +{ + & m32c_cgen_opval_h_r0l_r0h_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2r0_entries[] = +{ + { "r2r0", 0, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r2r0 = +{ + & m32c_cgen_opval_h_r2r0_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3r1_entries[] = +{ + { "r3r1", 0, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r3r1 = +{ + & m32c_cgen_opval_h_r3r1_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1r2r0_entries[] = +{ + { "r1r2r0", 0, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_r1r2r0 = +{ + & m32c_cgen_opval_h_r1r2r0_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_entries[] = +{ + { "a0", 0, {0, {0}}, 0, 0 }, + { "a1", 1, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_ar = +{ + & m32c_cgen_opval_h_ar_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_QI_entries[] = +{ + { "a0", 0, {0, {0}}, 0, 0 }, + { "a1", 1, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_ar_QI = +{ + & m32c_cgen_opval_h_ar_QI_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_HI_entries[] = +{ + { "a0", 0, {0, {0}}, 0, 0 }, + { "a1", 1, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_ar_HI = +{ + & m32c_cgen_opval_h_ar_HI_entries[0], + 2, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_SI_entries[] = +{ + { "a1a0", 0, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_ar_SI = +{ + & m32c_cgen_opval_h_ar_SI_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a0_entries[] = +{ + { "a0", 0, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_a0 = +{ + & m32c_cgen_opval_h_a0_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a1_entries[] = +{ + { "a1", 1, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_a1 = +{ + & m32c_cgen_opval_h_a1_entries[0], + 1, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16_entries[] = +{ + { "geu", 0, {0, {0}}, 0, 0 }, + { "c", 0, {0, {0}}, 0, 0 }, + { "gtu", 1, {0, {0}}, 0, 0 }, + { "eq", 2, {0, {0}}, 0, 0 }, + { "z", 2, {0, {0}}, 0, 0 }, + { "n", 3, {0, {0}}, 0, 0 }, + { "le", 4, {0, {0}}, 0, 0 }, + { "o", 5, {0, {0}}, 0, 0 }, + { "ge", 6, {0, {0}}, 0, 0 }, + { "ltu", 248, {0, {0}}, 0, 0 }, + { "nc", 248, {0, {0}}, 0, 0 }, + { "leu", 249, {0, {0}}, 0, 0 }, + { "ne", 250, {0, {0}}, 0, 0 }, + { "nz", 250, {0, {0}}, 0, 0 }, + { "pz", 251, {0, {0}}, 0, 0 }, + { "gt", 252, {0, {0}}, 0, 0 }, + { "no", 253, {0, {0}}, 0, 0 }, + { "lt", 254, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_cond16 = +{ + & m32c_cgen_opval_h_cond16_entries[0], + 18, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16c_entries[] = +{ + { "geu", 0, {0, {0}}, 0, 0 }, + { "c", 0, {0, {0}}, 0, 0 }, + { "gtu", 1, {0, {0}}, 0, 0 }, + { "eq", 2, {0, {0}}, 0, 0 }, + { "z", 2, {0, {0}}, 0, 0 }, + { "n", 3, {0, {0}}, 0, 0 }, + { "ltu", 4, {0, {0}}, 0, 0 }, + { "nc", 4, {0, {0}}, 0, 0 }, + { "leu", 5, {0, {0}}, 0, 0 }, + { "ne", 6, {0, {0}}, 0, 0 }, + { "nz", 6, {0, {0}}, 0, 0 }, + { "pz", 7, {0, {0}}, 0, 0 }, + { "le", 8, {0, {0}}, 0, 0 }, + { "o", 9, {0, {0}}, 0, 0 }, + { "ge", 10, {0, {0}}, 0, 0 }, + { "gt", 12, {0, {0}}, 0, 0 }, + { "no", 13, {0, {0}}, 0, 0 }, + { "lt", 14, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_cond16c = +{ + & m32c_cgen_opval_h_cond16c_entries[0], + 18, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_entries[] = +{ + { "le", 8, {0, {0}}, 0, 0 }, + { "o", 9, {0, {0}}, 0, 0 }, + { "ge", 10, {0, {0}}, 0, 0 }, + { "gt", 12, {0, {0}}, 0, 0 }, + { "no", 13, {0, {0}}, 0, 0 }, + { "lt", 14, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_cond16j = +{ + & m32c_cgen_opval_h_cond16j_entries[0], + 6, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_5_entries[] = +{ + { "geu", 0, {0, {0}}, 0, 0 }, + { "c", 0, {0, {0}}, 0, 0 }, + { "gtu", 1, {0, {0}}, 0, 0 }, + { "eq", 2, {0, {0}}, 0, 0 }, + { "z", 2, {0, {0}}, 0, 0 }, + { "n", 3, {0, {0}}, 0, 0 }, + { "ltu", 4, {0, {0}}, 0, 0 }, + { "nc", 4, {0, {0}}, 0, 0 }, + { "leu", 5, {0, {0}}, 0, 0 }, + { "ne", 6, {0, {0}}, 0, 0 }, + { "nz", 6, {0, {0}}, 0, 0 }, + { "pz", 7, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_cond16j_5 = +{ + & m32c_cgen_opval_h_cond16j_5_entries[0], + 12, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond32_entries[] = +{ + { "ltu", 0, {0, {0}}, 0, 0 }, + { "nc", 0, {0, {0}}, 0, 0 }, + { "leu", 1, {0, {0}}, 0, 0 }, + { "ne", 2, {0, {0}}, 0, 0 }, + { "nz", 2, {0, {0}}, 0, 0 }, + { "pz", 3, {0, {0}}, 0, 0 }, + { "no", 4, {0, {0}}, 0, 0 }, + { "gt", 5, {0, {0}}, 0, 0 }, + { "ge", 6, {0, {0}}, 0, 0 }, + { "geu", 8, {0, {0}}, 0, 0 }, + { "c", 8, {0, {0}}, 0, 0 }, + { "gtu", 9, {0, {0}}, 0, 0 }, + { "eq", 10, {0, {0}}, 0, 0 }, + { "z", 10, {0, {0}}, 0, 0 }, + { "n", 11, {0, {0}}, 0, 0 }, + { "o", 12, {0, {0}}, 0, 0 }, + { "le", 13, {0, {0}}, 0, 0 }, + { "lt", 14, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_cond32 = +{ + & m32c_cgen_opval_h_cond32_entries[0], + 18, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr1_32_entries[] = +{ + { "dct0", 0, {0, {0}}, 0, 0 }, + { "dct1", 1, {0, {0}}, 0, 0 }, + { "flg", 2, {0, {0}}, 0, 0 }, + { "svf", 3, {0, {0}}, 0, 0 }, + { "drc0", 4, {0, {0}}, 0, 0 }, + { "drc1", 5, {0, {0}}, 0, 0 }, + { "dmd0", 6, {0, {0}}, 0, 0 }, + { "dmd1", 7, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_cr1_32 = +{ + & m32c_cgen_opval_h_cr1_32_entries[0], + 8, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr2_32_entries[] = +{ + { "intb", 0, {0, {0}}, 0, 0 }, + { "sp", 1, {0, {0}}, 0, 0 }, + { "sb", 2, {0, {0}}, 0, 0 }, + { "fb", 3, {0, {0}}, 0, 0 }, + { "svp", 4, {0, {0}}, 0, 0 }, + { "vct", 5, {0, {0}}, 0, 0 }, + { "isp", 7, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_cr2_32 = +{ + & m32c_cgen_opval_h_cr2_32_entries[0], + 7, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr3_32_entries[] = +{ + { "dma0", 2, {0, {0}}, 0, 0 }, + { "dma1", 3, {0, {0}}, 0, 0 }, + { "dra0", 4, {0, {0}}, 0, 0 }, + { "dra1", 5, {0, {0}}, 0, 0 }, + { "dsa0", 6, {0, {0}}, 0, 0 }, + { "dsa1", 7, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_cr3_32 = +{ + & m32c_cgen_opval_h_cr3_32_entries[0], + 6, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr_16_entries[] = +{ + { "intbl", 1, {0, {0}}, 0, 0 }, + { "intbh", 2, {0, {0}}, 0, 0 }, + { "flg", 3, {0, {0}}, 0, 0 }, + { "isp", 4, {0, {0}}, 0, 0 }, + { "sp", 5, {0, {0}}, 0, 0 }, + { "sb", 6, {0, {0}}, 0, 0 }, + { "fb", 7, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_cr_16 = +{ + & m32c_cgen_opval_h_cr_16_entries[0], + 7, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_flags_entries[] = +{ + { "c", 0, {0, {0}}, 0, 0 }, + { "d", 1, {0, {0}}, 0, 0 }, + { "z", 2, {0, {0}}, 0, 0 }, + { "s", 3, {0, {0}}, 0, 0 }, + { "b", 4, {0, {0}}, 0, 0 }, + { "o", 5, {0, {0}}, 0, 0 }, + { "i", 6, {0, {0}}, 0, 0 }, + { "u", 7, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_flags = +{ + & m32c_cgen_opval_h_flags_entries[0], + 8, + 0, 0, 0, 0, "" +}; + +static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_shimm_entries[] = +{ + { "1", 0, {0, {0}}, 0, 0 }, + { "2", 1, {0, {0}}, 0, 0 }, + { "3", 2, {0, {0}}, 0, 0 }, + { "4", 3, {0, {0}}, 0, 0 }, + { "5", 4, {0, {0}}, 0, 0 }, + { "6", 5, {0, {0}}, 0, 0 }, + { "7", 6, {0, {0}}, 0, 0 }, + { "8", 7, {0, {0}}, 0, 0 }, + { "-1", -8, {0, {0}}, 0, 0 }, + { "-2", -7, {0, {0}}, 0, 0 }, + { "-3", -6, {0, {0}}, 0, 0 }, + { "-4", -5, {0, {0}}, 0, 0 }, + { "-5", -4, {0, {0}}, 0, 0 }, + { "-6", -3, {0, {0}}, 0, 0 }, + { "-7", -2, {0, {0}}, 0, 0 }, + { "-8", -1, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD m32c_cgen_opval_h_shimm = +{ + & m32c_cgen_opval_h_shimm_entries[0], + 16, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_HW_##a) +#else +#define A(a) (1 << CGEN_HW_/**/a) +#endif + +const CGEN_HW_ENTRY m32c_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of m32c_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & m32c_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of m32c_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (CGEN_CPU_TABLE *cd) +{ + cd->ifld_table = & m32c_cgen_ifld_table[0]; +} + +/* Subroutine of m32c_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (CGEN_CPU_TABLE *cd) +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & m32c_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of m32c_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (CGEN_CPU_TABLE *cd) +{ + int i; + const CGEN_IBASE *ib = & m32c_cgen_insn_table[0]; + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of m32c_cgen_cpu_open to rebuild the tables. */ + +static void +m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) +{ + int i; + unsigned int isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (((1 << i) & isas) != 0) + { + const CGEN_ISA *isa = & m32c_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* This is ok. */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* This is ok. */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & m32c_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "m32c_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. + + ??? We only support ISO C stdargs here, not K&R. + Laziness, plus experiment to see if anything requires K&R - eventually + K&R will no longer be supported - e.g. GDB is currently trying this. */ + +CGEN_CPU_DESC +m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + unsigned int isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (m32c_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "m32c_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* Mach unspecified means "all". */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* Base mach is always selected. */ + machs |= 1; + /* ISA unspecified means "all". */ + if (isas == 0) + isas = (1 << MAX_ISAS) - 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "m32c_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = isas; + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = m32c_cgen_rebuild_tables; + m32c_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to m32c_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +m32c_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) +{ + return m32c_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +m32c_cgen_cpu_close (CGEN_CPU_DESC cd) +{ + unsigned int i; + const CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff -uprN binutils-2.16.91.0.1/opcodes/m32c-desc.h binutils-2.16.91.0.2/opcodes/m32c-desc.h --- binutils-2.16.91.0.1/opcodes/m32c-desc.h 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/opcodes/m32c-desc.h 2005-07-20 12:27:28.967916883 -0700 @@ -0,0 +1,485 @@ +/* CPU data header for m32c. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2005 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef M32C_CPU_H +#define M32C_CPU_H + +#define CGEN_ARCH m32c + +/* Given symbol S, return m32c_cgen_. */ +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define CGEN_SYM(s) m32c##_cgen_##s +#else +#define CGEN_SYM(s) m32c/**/_cgen_/**/s +#endif + + +/* Selected cpu families. */ +#define HAVE_CPU_M16CBF +#define HAVE_CPU_M32CBF + +#define CGEN_INSN_LSB0_P 0 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 1 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 10 + +#define CGEN_INT_INSN_P 0 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 26 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 13 + +/* Enums. */ + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_M16C, MACH_M32C, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_M16C, ISA_M32C, ISA_MAX +} ISA_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS ((int) ISA_MAX) +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* Enum declaration for m32c ifield types. */ +typedef enum ifield_type { + M32C_F_NIL, M32C_F_ANYOF, M32C_F_0_1, M32C_F_0_2 + , M32C_F_0_3, M32C_F_0_4, M32C_F_1_3, M32C_F_2_2 + , M32C_F_3_4, M32C_F_3_1, M32C_F_4_1, M32C_F_4_3 + , M32C_F_4_4, M32C_F_4_6, M32C_F_5_1, M32C_F_5_3 + , M32C_F_6_2, M32C_F_7_1, M32C_F_8_1, M32C_F_8_2 + , M32C_F_8_3, M32C_F_8_4, M32C_F_8_8, M32C_F_9_3 + , M32C_F_9_1, M32C_F_10_1, M32C_F_10_2, M32C_F_10_3 + , M32C_F_11_1, M32C_F_12_1, M32C_F_12_2, M32C_F_12_3 + , M32C_F_12_4, M32C_F_12_6, M32C_F_13_3, M32C_F_14_1 + , M32C_F_14_2, M32C_F_15_1, M32C_F_16_1, M32C_F_16_2 + , M32C_F_16_4, M32C_F_16_8, M32C_F_18_1, M32C_F_18_2 + , M32C_F_18_3, M32C_F_20_1, M32C_F_20_3, M32C_F_20_2 + , M32C_F_20_4, M32C_F_21_3, M32C_F_24_2, M32C_F_24_8 + , M32C_F_32_16, M32C_F_SRC16_RN, M32C_F_SRC16_AN, M32C_F_SRC32_AN_UNPREFIXED + , M32C_F_SRC32_AN_PREFIXED, M32C_F_SRC32_RN_UNPREFIXED_QI, M32C_F_SRC32_RN_PREFIXED_QI, M32C_F_SRC32_RN_UNPREFIXED_HI + , M32C_F_SRC32_RN_PREFIXED_HI, M32C_F_SRC32_RN_UNPREFIXED_SI, M32C_F_SRC32_RN_PREFIXED_SI, M32C_F_DST32_RN_EXT_UNPREFIXED + , M32C_F_DST16_RN, M32C_F_DST16_RN_EXT, M32C_F_DST16_RN_QI_S, M32C_F_DST16_AN + , M32C_F_DST16_AN_S, M32C_F_DST32_AN_UNPREFIXED, M32C_F_DST32_AN_PREFIXED, M32C_F_DST32_RN_UNPREFIXED_QI + , M32C_F_DST32_RN_PREFIXED_QI, M32C_F_DST32_RN_UNPREFIXED_HI, M32C_F_DST32_RN_PREFIXED_HI, M32C_F_DST32_RN_UNPREFIXED_SI + , M32C_F_DST32_RN_PREFIXED_SI, M32C_F_DST16_1_S, M32C_F_IMM_8_S4, M32C_F_IMM_12_S4 + , M32C_F_IMM_13_U3, M32C_F_IMM_20_S4, M32C_F_IMM1_S, M32C_F_IMM3_S + , M32C_F_DSP_8_U6, M32C_F_DSP_8_U8, M32C_F_DSP_8_S8, M32C_F_DSP_10_U6 + , M32C_F_DSP_16_U8, M32C_F_DSP_16_S8, M32C_F_DSP_24_U8, M32C_F_DSP_24_S8 + , M32C_F_DSP_32_U8, M32C_F_DSP_32_S8, M32C_F_DSP_40_U8, M32C_F_DSP_40_S8 + , M32C_F_DSP_48_U8, M32C_F_DSP_48_S8, M32C_F_DSP_56_U8, M32C_F_DSP_56_S8 + , M32C_F_DSP_64_U8, M32C_F_DSP_64_S8, M32C_F_DSP_8_U16, M32C_F_DSP_8_S16 + , M32C_F_DSP_16_U16, M32C_F_DSP_16_S16, M32C_F_DSP_24_U16, M32C_F_DSP_24_S16 + , M32C_F_DSP_32_U16, M32C_F_DSP_32_S16, M32C_F_DSP_40_U16, M32C_F_DSP_40_S16 + , M32C_F_DSP_48_U16, M32C_F_DSP_48_S16, M32C_F_DSP_64_U16, M32C_F_DSP_8_U24 + , M32C_F_DSP_16_U24, M32C_F_DSP_24_U24, M32C_F_DSP_32_U24, M32C_F_DSP_40_U24 + , M32C_F_DSP_40_S32, M32C_F_DSP_48_U24, M32C_F_DSP_16_S32, M32C_F_DSP_24_S32 + , M32C_F_DSP_32_S32, M32C_F_DSP_48_U32, M32C_F_DSP_48_S32, M32C_F_DSP_56_S16 + , M32C_F_DSP_64_S16, M32C_F_BITNO16_S, M32C_F_BITNO32_PREFIXED, M32C_F_BITNO32_UNPREFIXED + , M32C_F_BITBASE16_U11_S, M32C_F_BITBASE32_16_U11_UNPREFIXED, M32C_F_BITBASE32_16_S11_UNPREFIXED, M32C_F_BITBASE32_16_U19_UNPREFIXED + , M32C_F_BITBASE32_16_S19_UNPREFIXED, M32C_F_BITBASE32_16_U27_UNPREFIXED, M32C_F_BITBASE32_24_U11_PREFIXED, M32C_F_BITBASE32_24_S11_PREFIXED + , M32C_F_BITBASE32_24_U19_PREFIXED, M32C_F_BITBASE32_24_S19_PREFIXED, M32C_F_BITBASE32_24_U27_PREFIXED, M32C_F_LAB_5_3 + , M32C_F_LAB32_JMP_S, M32C_F_LAB_8_8, M32C_F_LAB_8_16, M32C_F_LAB_8_24 + , M32C_F_LAB_16_8, M32C_F_LAB_24_8, M32C_F_LAB_32_8, M32C_F_LAB_40_8 + , M32C_F_COND16, M32C_F_COND16J_5, M32C_F_COND32, M32C_F_COND32J + , M32C_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) M32C_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_ISA + , CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* Enum declaration for m32c hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_GR_QI + , HW_H_GR_HI, HW_H_GR_SI, HW_H_GR_EXT_QI, HW_H_GR_EXT_HI + , HW_H_R0L, HW_H_R0H, HW_H_R1L, HW_H_R1H + , HW_H_R0, HW_H_R1, HW_H_R2, HW_H_R3 + , HW_H_R0L_R0H, HW_H_R2R0, HW_H_R3R1, HW_H_R1R2R0 + , HW_H_AR, HW_H_AR_QI, HW_H_AR_HI, HW_H_AR_SI + , HW_H_A0, HW_H_A1, HW_H_SB, HW_H_FB + , HW_H_SP, HW_H_SBIT, HW_H_ZBIT, HW_H_OBIT + , HW_H_CBIT, HW_H_UBIT, HW_H_IBIT, HW_H_BBIT + , HW_H_DBIT, HW_H_DCT0, HW_H_DCT1, HW_H_SVF + , HW_H_DRC0, HW_H_DRC1, HW_H_DMD0, HW_H_DMD1 + , HW_H_INTB, HW_H_SVP, HW_H_VCT, HW_H_ISP + , HW_H_DMA0, HW_H_DMA1, HW_H_DRA0, HW_H_DRA1 + , HW_H_DSA0, HW_H_DSA1, HW_H_COND16, HW_H_COND16C + , HW_H_COND16J, HW_H_COND16J_5, HW_H_COND32, HW_H_CR1_32 + , HW_H_CR2_32, HW_H_CR3_32, HW_H_CR_16, HW_H_FLAGS + , HW_H_SHIMM, HW_H_BIT_INDEX, HW_H_SRC_INDEX, HW_H_DST_INDEX + , HW_H_SRC_INDIRECT, HW_H_DST_INDIRECT, HW_H_NONE, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA + , CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* Enum declaration for m32c operand types. */ +typedef enum cgen_operand_type { + M32C_OPERAND_PC, M32C_OPERAND_SRC16RNQI, M32C_OPERAND_SRC16RNHI, M32C_OPERAND_SRC32RNUNPREFIXEDQI + , M32C_OPERAND_SRC32RNUNPREFIXEDHI, M32C_OPERAND_SRC32RNUNPREFIXEDSI, M32C_OPERAND_SRC32RNPREFIXEDQI, M32C_OPERAND_SRC32RNPREFIXEDHI + , M32C_OPERAND_SRC32RNPREFIXEDSI, M32C_OPERAND_SRC16AN, M32C_OPERAND_SRC16ANQI, M32C_OPERAND_SRC16ANHI + , M32C_OPERAND_SRC32ANUNPREFIXED, M32C_OPERAND_SRC32ANUNPREFIXEDQI, M32C_OPERAND_SRC32ANUNPREFIXEDHI, M32C_OPERAND_SRC32ANUNPREFIXEDSI + , M32C_OPERAND_SRC32ANPREFIXED, M32C_OPERAND_SRC32ANPREFIXEDQI, M32C_OPERAND_SRC32ANPREFIXEDHI, M32C_OPERAND_SRC32ANPREFIXEDSI + , M32C_OPERAND_DST16RNQI, M32C_OPERAND_DST16RNHI, M32C_OPERAND_DST16RNSI, M32C_OPERAND_DST16RNEXTQI + , M32C_OPERAND_DST32R0QI_S, M32C_OPERAND_DST32R0HI_S, M32C_OPERAND_DST32RNUNPREFIXEDQI, M32C_OPERAND_DST32RNUNPREFIXEDHI + , M32C_OPERAND_DST32RNUNPREFIXEDSI, M32C_OPERAND_DST32RNEXTUNPREFIXEDQI, M32C_OPERAND_DST32RNEXTUNPREFIXEDHI, M32C_OPERAND_DST32RNPREFIXEDQI + , M32C_OPERAND_DST32RNPREFIXEDHI, M32C_OPERAND_DST32RNPREFIXEDSI, M32C_OPERAND_DST16RNQI_S, M32C_OPERAND_DST16ANQI_S + , M32C_OPERAND_BIT16RN, M32C_OPERAND_BIT32RNPREFIXED, M32C_OPERAND_BIT32RNUNPREFIXED, M32C_OPERAND_R0 + , M32C_OPERAND_R1, M32C_OPERAND_R2, M32C_OPERAND_R3, M32C_OPERAND_R0L + , M32C_OPERAND_R0H, M32C_OPERAND_R2R0, M32C_OPERAND_R3R1, M32C_OPERAND_R1R2R0 + , M32C_OPERAND_DST16AN, M32C_OPERAND_DST16ANQI, M32C_OPERAND_DST16ANHI, M32C_OPERAND_DST16ANSI + , M32C_OPERAND_DST16AN_S, M32C_OPERAND_DST32ANUNPREFIXED, M32C_OPERAND_DST32ANUNPREFIXEDQI, M32C_OPERAND_DST32ANUNPREFIXEDHI + , M32C_OPERAND_DST32ANUNPREFIXEDSI, M32C_OPERAND_DST32ANEXTUNPREFIXED, M32C_OPERAND_DST32ANPREFIXED, M32C_OPERAND_DST32ANPREFIXEDQI + , M32C_OPERAND_DST32ANPREFIXEDHI, M32C_OPERAND_DST32ANPREFIXEDSI, M32C_OPERAND_BIT16AN, M32C_OPERAND_BIT32ANPREFIXED + , M32C_OPERAND_BIT32ANUNPREFIXED, M32C_OPERAND_A0, M32C_OPERAND_A1, M32C_OPERAND_SB + , M32C_OPERAND_FB, M32C_OPERAND_SP, M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, M32C_OPERAND_REGSETPOP + , M32C_OPERAND_REGSETPUSH, M32C_OPERAND_RN16_PUSH_S, M32C_OPERAND_AN16_PUSH_S, M32C_OPERAND_DSP_8_U6 + , M32C_OPERAND_DSP_8_U8, M32C_OPERAND_DSP_8_U16, M32C_OPERAND_DSP_8_S8, M32C_OPERAND_DSP_8_U24 + , M32C_OPERAND_DSP_10_U6, M32C_OPERAND_DSP_16_U8, M32C_OPERAND_DSP_16_U16, M32C_OPERAND_DSP_16_U20 + , M32C_OPERAND_DSP_16_U24, M32C_OPERAND_DSP_16_S8, M32C_OPERAND_DSP_16_S16, M32C_OPERAND_DSP_24_U8 + , M32C_OPERAND_DSP_24_U16, M32C_OPERAND_DSP_24_U20, M32C_OPERAND_DSP_24_U24, M32C_OPERAND_DSP_24_S8 + , M32C_OPERAND_DSP_24_S16, M32C_OPERAND_DSP_32_U8, M32C_OPERAND_DSP_32_U16, M32C_OPERAND_DSP_32_U24 + , M32C_OPERAND_DSP_32_U20, M32C_OPERAND_DSP_32_S8, M32C_OPERAND_DSP_32_S16, M32C_OPERAND_DSP_40_U8 + , M32C_OPERAND_DSP_40_S8, M32C_OPERAND_DSP_40_U16, M32C_OPERAND_DSP_40_S16, M32C_OPERAND_DSP_40_U24 + , M32C_OPERAND_DSP_48_U8, M32C_OPERAND_DSP_48_S8, M32C_OPERAND_DSP_48_U16, M32C_OPERAND_DSP_48_S16 + , M32C_OPERAND_DSP_48_U24, M32C_OPERAND_IMM_8_S4, M32C_OPERAND_IMM_SH_8_S4, M32C_OPERAND_IMM_8_QI + , M32C_OPERAND_IMM_8_HI, M32C_OPERAND_IMM_12_S4, M32C_OPERAND_IMM_SH_12_S4, M32C_OPERAND_IMM_13_U3 + , M32C_OPERAND_IMM_20_S4, M32C_OPERAND_IMM_SH_20_S4, M32C_OPERAND_IMM_16_QI, M32C_OPERAND_IMM_16_HI + , M32C_OPERAND_IMM_16_SI, M32C_OPERAND_IMM_24_QI, M32C_OPERAND_IMM_24_HI, M32C_OPERAND_IMM_24_SI + , M32C_OPERAND_IMM_32_QI, M32C_OPERAND_IMM_32_SI, M32C_OPERAND_IMM_32_HI, M32C_OPERAND_IMM_40_QI + , M32C_OPERAND_IMM_40_HI, M32C_OPERAND_IMM_40_SI, M32C_OPERAND_IMM_48_QI, M32C_OPERAND_IMM_48_HI + , M32C_OPERAND_IMM_48_SI, M32C_OPERAND_IMM_56_QI, M32C_OPERAND_IMM_56_HI, M32C_OPERAND_IMM_64_HI + , M32C_OPERAND_IMM1_S, M32C_OPERAND_IMM3_S, M32C_OPERAND_BITNO16R, M32C_OPERAND_BITNO32PREFIXED + , M32C_OPERAND_BITNO32UNPREFIXED, M32C_OPERAND_BITBASE16_16_U8, M32C_OPERAND_BITBASE16_16_S8, M32C_OPERAND_BITBASE16_16_U16 + , M32C_OPERAND_BITBASE16_8_U11_S, M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED + , M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, M32C_OPERAND_BITBASE32_24_U11_PREFIXED, M32C_OPERAND_BITBASE32_24_S11_PREFIXED + , M32C_OPERAND_BITBASE32_24_U19_PREFIXED, M32C_OPERAND_BITBASE32_24_S19_PREFIXED, M32C_OPERAND_BITBASE32_24_U27_PREFIXED, M32C_OPERAND_LAB_5_3 + , M32C_OPERAND_LAB32_JMP_S, M32C_OPERAND_LAB_8_8, M32C_OPERAND_LAB_8_16, M32C_OPERAND_LAB_8_24 + , M32C_OPERAND_LAB_16_8, M32C_OPERAND_LAB_24_8, M32C_OPERAND_LAB_32_8, M32C_OPERAND_LAB_40_8 + , M32C_OPERAND_SBIT, M32C_OPERAND_OBIT, M32C_OPERAND_ZBIT, M32C_OPERAND_CBIT + , M32C_OPERAND_UBIT, M32C_OPERAND_IBIT, M32C_OPERAND_BBIT, M32C_OPERAND_DBIT + , M32C_OPERAND_COND16_16, M32C_OPERAND_COND16_24, M32C_OPERAND_COND16_32, M32C_OPERAND_COND32_16 + , M32C_OPERAND_COND32_24, M32C_OPERAND_COND32_32, M32C_OPERAND_COND32_40, M32C_OPERAND_COND16C + , M32C_OPERAND_COND16J, M32C_OPERAND_COND16J5, M32C_OPERAND_COND32, M32C_OPERAND_COND32J + , M32C_OPERAND_SCCOND32, M32C_OPERAND_FLAGS16, M32C_OPERAND_FLAGS32, M32C_OPERAND_CR16 + , M32C_OPERAND_CR1_UNPREFIXED_32, M32C_OPERAND_CR1_PREFIXED_32, M32C_OPERAND_CR2_32, M32C_OPERAND_CR3_UNPREFIXED_32 + , M32C_OPERAND_CR3_PREFIXED_32, M32C_OPERAND_Z, M32C_OPERAND_S, M32C_OPERAND_Q + , M32C_OPERAND_G, M32C_OPERAND_X, M32C_OPERAND_SIZE, M32C_OPERAND_BITINDEX + , M32C_OPERAND_SRCINDEX, M32C_OPERAND_DSTINDEX, M32C_OPERAND_NOREMAINDER, M32C_OPERAND_SRC16_RN_DIRECT_QI + , M32C_OPERAND_SRC16_RN_DIRECT_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_HI + , M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_DIRECT_QI + , M32C_OPERAND_SRC16_AN_DIRECT_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_SI + , M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_INDIRECT_QI + , M32C_OPERAND_SRC16_AN_INDIRECT_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_SI + , M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_QI + , M32C_OPERAND_SRC16_16_16_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_QI + , M32C_OPERAND_SRC16_16_8_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_16_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_HI + , M32C_OPERAND_SRC16_16_16_AN_RELATIVE_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_SI + , M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_QI + , M32C_OPERAND_SRC16_16_16_ABSOLUTE_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_SI + , M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_SRC16_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_16_ABSOLUTE_QI + , M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_HI + , M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST16_RN_DIRECT_QI, M32C_OPERAND_DST16_RN_DIRECT_HI + , M32C_OPERAND_DST16_RN_DIRECT_SI, M32C_OPERAND_DST16_RN_DIRECT_EXT_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_QI + , M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_SI + , M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_R3_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST16_AN_DIRECT_QI + , M32C_OPERAND_DST16_AN_DIRECT_HI, M32C_OPERAND_DST16_AN_DIRECT_SI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_QI + , M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_SI + , M32C_OPERAND_DST16_AN_INDIRECT_QI, M32C_OPERAND_DST16_AN_INDIRECT_HI, M32C_OPERAND_DST16_AN_INDIRECT_SI, M32C_OPERAND_DST16_AN_INDIRECT_EXT_QI + , M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_HI + , M32C_OPERAND_DST16_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_QI + , M32C_OPERAND_DST16_16_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_QI + , M32C_OPERAND_DST16_24_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_QI + , M32C_OPERAND_DST16_32_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_QI + , M32C_OPERAND_DST16_40_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_QI + , M32C_OPERAND_DST16_48_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_QI + , M32C_OPERAND_DST16_48_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_HI + , M32C_OPERAND_DST16_16_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_HI + , M32C_OPERAND_DST16_24_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_HI + , M32C_OPERAND_DST16_32_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_HI + , M32C_OPERAND_DST16_40_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_HI + , M32C_OPERAND_DST16_40_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_HI + , M32C_OPERAND_DST16_48_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_SI + , M32C_OPERAND_DST16_16_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_SI + , M32C_OPERAND_DST16_24_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_SI + , M32C_OPERAND_DST16_32_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_SI + , M32C_OPERAND_DST16_32_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_SI + , M32C_OPERAND_DST16_40_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_SI + , M32C_OPERAND_DST16_48_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_EXT_QI + , M32C_OPERAND_DST16_16_16_SB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_EXT_QI + , M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI + , M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI + , M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI + , M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_QI, M32C_OPERAND_DST16_24_16_ABSOLUTE_QI + , M32C_OPERAND_DST16_32_16_ABSOLUTE_QI, M32C_OPERAND_DST16_40_16_ABSOLUTE_QI, M32C_OPERAND_DST16_48_16_ABSOLUTE_QI, M32C_OPERAND_DST16_16_16_ABSOLUTE_HI + , M32C_OPERAND_DST16_24_16_ABSOLUTE_HI, M32C_OPERAND_DST16_32_16_ABSOLUTE_HI, M32C_OPERAND_DST16_40_16_ABSOLUTE_HI, M32C_OPERAND_DST16_48_16_ABSOLUTE_HI + , M32C_OPERAND_DST16_16_16_ABSOLUTE_SI, M32C_OPERAND_DST16_24_16_ABSOLUTE_SI, M32C_OPERAND_DST16_32_16_ABSOLUTE_SI, M32C_OPERAND_DST16_40_16_ABSOLUTE_SI + , M32C_OPERAND_DST16_48_16_ABSOLUTE_SI, M32C_OPERAND_DST16_16_16_ABSOLUTE_EXT_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_QI + , M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_HI + , M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_SI + , M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_SI + , M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_QI + , M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_SI + , M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_SI + , M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI + , M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_BIT16_RN_DIRECT, M32C_OPERAND_BIT32_RN_DIRECT_UNPREFIXED + , M32C_OPERAND_BIT32_RN_DIRECT_PREFIXED, M32C_OPERAND_BIT16_AN_DIRECT, M32C_OPERAND_BIT32_AN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_DIRECT_PREFIXED + , M32C_OPERAND_BIT16_AN_INDIRECT, M32C_OPERAND_BIT32_AN_INDIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_INDIRECT_PREFIXED, M32C_OPERAND_BIT16_16_8_SB_RELATIVE + , M32C_OPERAND_BIT16_16_16_SB_RELATIVE, M32C_OPERAND_BIT16_16_8_FB_RELATIVE, M32C_OPERAND_BIT16_16_8_AN_RELATIVE, M32C_OPERAND_BIT16_16_16_AN_RELATIVE + , M32C_OPERAND_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_FB_RELATIVE_UNPREFIXED + , M32C_OPERAND_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_24_11_SB_RELATIVE_PREFIXED + , M32C_OPERAND_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_AN_RELATIVE_PREFIXED + , M32C_OPERAND_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT16_11_SB_RELATIVE_S, M32C_OPERAND_RN16_PUSH_S_DERIVED + , M32C_OPERAND_AN16_PUSH_S_DERIVED, M32C_OPERAND_BIT16_16_16_ABSOLUTE, M32C_OPERAND_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_ABSOLUTE_UNPREFIXED + , M32C_OPERAND_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_OPERAND_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_OPERAND_DST16_3_S_R0L_DIRECT_QI, M32C_OPERAND_DST16_3_S_R0H_DIRECT_QI + , M32C_OPERAND_DST16_3_S_8_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_16_ABSOLUTE_QI, M32C_OPERAND_DST16_3_S_16_8_SB_RELATIVE_QI + , M32C_OPERAND_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_16_16_ABSOLUTE_QI, M32C_OPERAND_SRCDST16_R0L_R0H_S_DERIVED, M32C_OPERAND_DST32_2_S_R0L_DIRECT_QI + , M32C_OPERAND_DST32_2_S_R0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A1_DIRECT_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_QI + , M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_HI + , M32C_OPERAND_DST32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_SI + , M32C_OPERAND_SRC16_BASIC_QI, M32C_OPERAND_SRC16_BASIC_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_QI, M32C_OPERAND_SRC32_BASIC_PREFIXED_QI + , M32C_OPERAND_SRC32_BASIC_UNPREFIXED_HI, M32C_OPERAND_SRC32_BASIC_PREFIXED_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_SI, M32C_OPERAND_SRC32_BASIC_PREFIXED_SI + , M32C_OPERAND_SRC32_BASIC_EXTPREFIXED_QI, M32C_OPERAND_SRC16_16_8_QI, M32C_OPERAND_SRC16_16_16_QI, M32C_OPERAND_SRC16_16_8_HI + , M32C_OPERAND_SRC16_16_16_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_QI + , M32C_OPERAND_SRC32_16_8_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_SI + , M32C_OPERAND_SRC32_16_16_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_PREFIXED_QI + , M32C_OPERAND_SRC32_24_24_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_PREFIXED_HI + , M32C_OPERAND_SRC32_24_8_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_BASIC_QI + , M32C_OPERAND_DST16_BASIC_HI, M32C_OPERAND_DST16_BASIC_SI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_QI, M32C_OPERAND_DST32_BASIC_PREFIXED_QI + , M32C_OPERAND_DST32_BASIC_UNPREFIXED_HI, M32C_OPERAND_DST32_BASIC_PREFIXED_HI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_SI, M32C_OPERAND_DST32_BASIC_PREFIXED_SI + , M32C_OPERAND_DST16_16_QI, M32C_OPERAND_DST16_16_8_QI, M32C_OPERAND_DST16_16_16_QI, M32C_OPERAND_DST16_16_HI + , M32C_OPERAND_DST16_16_8_HI, M32C_OPERAND_DST16_16_16_HI, M32C_OPERAND_DST16_16_SI, M32C_OPERAND_DST16_16_8_SI + , M32C_OPERAND_DST16_16_16_SI, M32C_OPERAND_DST16_16_EXT_QI, M32C_OPERAND_DST16_AN_INDIRECT_MOVA_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_MOVA_HI + , M32C_OPERAND_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_MOVA_HI + , M32C_OPERAND_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_OPERAND_DST16_16_MOVA_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI + , M32C_OPERAND_DST32_16_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_UNPREFIXED_QI + , M32C_OPERAND_DST32_16_24_UNPREFIXED_QI, M32C_OPERAND_DST32_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_UNPREFIXED_HI + , M32C_OPERAND_DST32_16_24_UNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_UNPREFIXED_SI + , M32C_OPERAND_DST32_16_24_UNPREFIXED_SI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_MULEX_HI + , M32C_OPERAND_DST16_24_QI, M32C_OPERAND_DST16_24_HI, M32C_OPERAND_DST32_24_UNPREFIXED_QI, M32C_OPERAND_DST32_24_PREFIXED_QI + , M32C_OPERAND_DST32_24_8_PREFIXED_QI, M32C_OPERAND_DST32_24_16_PREFIXED_QI, M32C_OPERAND_DST32_24_24_PREFIXED_QI, M32C_OPERAND_DST32_24_UNPREFIXED_HI + , M32C_OPERAND_DST32_24_PREFIXED_HI, M32C_OPERAND_DST32_24_8_PREFIXED_HI, M32C_OPERAND_DST32_24_16_PREFIXED_HI, M32C_OPERAND_DST32_24_24_PREFIXED_HI + , M32C_OPERAND_DST32_24_UNPREFIXED_SI, M32C_OPERAND_DST32_24_PREFIXED_SI, M32C_OPERAND_DST32_24_8_PREFIXED_SI, M32C_OPERAND_DST32_24_16_PREFIXED_SI + , M32C_OPERAND_DST32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_32_QI, M32C_OPERAND_DST16_32_HI, M32C_OPERAND_DST32_32_UNPREFIXED_QI + , M32C_OPERAND_DST32_32_PREFIXED_QI, M32C_OPERAND_DST32_32_UNPREFIXED_HI, M32C_OPERAND_DST32_32_PREFIXED_HI, M32C_OPERAND_DST32_32_UNPREFIXED_SI + , M32C_OPERAND_DST32_32_PREFIXED_SI, M32C_OPERAND_DST32_40_UNPREFIXED_QI, M32C_OPERAND_DST32_40_PREFIXED_QI, M32C_OPERAND_DST32_40_UNPREFIXED_HI + , M32C_OPERAND_DST32_40_PREFIXED_HI, M32C_OPERAND_DST32_40_UNPREFIXED_SI, M32C_OPERAND_DST32_40_PREFIXED_SI, M32C_OPERAND_DST32_48_PREFIXED_QI + , M32C_OPERAND_DST32_48_PREFIXED_HI, M32C_OPERAND_DST32_48_PREFIXED_SI, M32C_OPERAND_BIT16_16, M32C_OPERAND_BIT16_16_BASIC + , M32C_OPERAND_BIT16_16_8, M32C_OPERAND_BIT16_16_16, M32C_OPERAND_BIT32_16_UNPREFIXED, M32C_OPERAND_BIT32_24_PREFIXED + , M32C_OPERAND_BIT32_BASIC_UNPREFIXED, M32C_OPERAND_BIT32_16_8_UNPREFIXED, M32C_OPERAND_BIT32_16_16_UNPREFIXED, M32C_OPERAND_BIT32_16_24_UNPREFIXED + , M32C_OPERAND_SRC16_2_S, M32C_OPERAND_SRC32_2_S_QI, M32C_OPERAND_SRC32_2_S_HI, M32C_OPERAND_DST16_3_S_8 + , M32C_OPERAND_DST16_3_S_16, M32C_OPERAND_SRCDST16_R0L_R0H_S, M32C_OPERAND_DST32_2_S_BASIC_QI, M32C_OPERAND_DST32_2_S_BASIC_HI + , M32C_OPERAND_DST32_2_S_8_QI, M32C_OPERAND_DST32_2_S_16_QI, M32C_OPERAND_DST32_2_S_8_HI, M32C_OPERAND_DST32_2_S_16_HI + , M32C_OPERAND_DST32_2_S_8_SI, M32C_OPERAND_DST32_2_S_16_SI, M32C_OPERAND_DST32_AN_S, M32C_OPERAND_BIT16_11_S + , M32C_OPERAND_RN16_PUSH_S_ANYOF, M32C_OPERAND_AN16_PUSH_S_ANYOF, M32C_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 870 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 + , CGEN_INSN_MACH, CGEN_INSN_ISA, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +extern const struct cgen_ifld m32c_cgen_ifld_table[]; + +/* Attributes. */ +extern const CGEN_ATTR_TABLE m32c_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE m32c_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE m32c_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE m32c_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD m32c_cgen_opval_h_gr; +extern CGEN_KEYWORD m32c_cgen_opval_h_gr_QI; +extern CGEN_KEYWORD m32c_cgen_opval_h_gr_HI; +extern CGEN_KEYWORD m32c_cgen_opval_h_gr_SI; +extern CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_QI; +extern CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_HI; +extern CGEN_KEYWORD m32c_cgen_opval_h_r0l; +extern CGEN_KEYWORD m32c_cgen_opval_h_r0h; +extern CGEN_KEYWORD m32c_cgen_opval_h_r1l; +extern CGEN_KEYWORD m32c_cgen_opval_h_r1h; +extern CGEN_KEYWORD m32c_cgen_opval_h_r0; +extern CGEN_KEYWORD m32c_cgen_opval_h_r1; +extern CGEN_KEYWORD m32c_cgen_opval_h_r2; +extern CGEN_KEYWORD m32c_cgen_opval_h_r3; +extern CGEN_KEYWORD m32c_cgen_opval_h_r0l_r0h; +extern CGEN_KEYWORD m32c_cgen_opval_h_r2r0; +extern CGEN_KEYWORD m32c_cgen_opval_h_r3r1; +extern CGEN_KEYWORD m32c_cgen_opval_h_r1r2r0; +extern CGEN_KEYWORD m32c_cgen_opval_h_ar; +extern CGEN_KEYWORD m32c_cgen_opval_h_ar_QI; +extern CGEN_KEYWORD m32c_cgen_opval_h_ar_HI; +extern CGEN_KEYWORD m32c_cgen_opval_h_ar_SI; +extern CGEN_KEYWORD m32c_cgen_opval_h_a0; +extern CGEN_KEYWORD m32c_cgen_opval_h_a1; +extern CGEN_KEYWORD m32c_cgen_opval_h_cond16; +extern CGEN_KEYWORD m32c_cgen_opval_h_cond16c; +extern CGEN_KEYWORD m32c_cgen_opval_h_cond16j; +extern CGEN_KEYWORD m32c_cgen_opval_h_cond16j_5; +extern CGEN_KEYWORD m32c_cgen_opval_h_cond32; +extern CGEN_KEYWORD m32c_cgen_opval_h_cr1_32; +extern CGEN_KEYWORD m32c_cgen_opval_h_cr2_32; +extern CGEN_KEYWORD m32c_cgen_opval_h_cr3_32; +extern CGEN_KEYWORD m32c_cgen_opval_h_cr_16; +extern CGEN_KEYWORD m32c_cgen_opval_h_flags; +extern CGEN_KEYWORD m32c_cgen_opval_h_shimm; + +extern const CGEN_HW_ENTRY m32c_cgen_hw_table[]; + + + +#endif /* M32C_CPU_H */ diff -uprN binutils-2.16.91.0.1/opcodes/m32c-dis.c binutils-2.16.91.0.2/opcodes/m32c-dis.c --- binutils-2.16.91.0.1/opcodes/m32c-dis.c 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/opcodes/m32c-dis.c 2005-07-20 12:27:28.970916388 -0700 @@ -0,0 +1,1279 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Free Software Foundation, Inc. + + This file is part of the GNU Binutils and GDB, the GNU debugger. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "libiberty.h" +#include "m32c-desc.h" +#include "m32c-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_address + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; +static void print_keyword + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; +static void print_insn_normal + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); +static int print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); +static int default_print_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; +static int read_insn + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, + unsigned long *); + +/* -- disassembler routines inserted here. */ + +/* -- dis.c */ + +#include "elf/m32c.h" +#include "elf-bfd.h" + +/* Always print the short insn format suffix as ':'. */ + +static void +print_suffix (void * dis_info, char suffix) +{ + disassemble_info *info = dis_info; + + (*info->fprintf_func) (info->stream, ":%c", suffix); +} + +static void +print_S (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_suffix (dis_info, 's'); +} + + +static void +print_G (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_suffix (dis_info, 'g'); +} + +static void +print_Q (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_suffix (dis_info, 'q'); +} + +static void +print_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_suffix (dis_info, 'z'); +} + +/* Print the empty suffix. */ + +static void +print_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info ATTRIBUTE_UNUSED, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + return; +} + +static void +print_r0l_r0h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = dis_info; + + if (value == 0) + (*info->fprintf_func) (info->stream, "r0h,r0l"); + else + (*info->fprintf_func) (info->stream, "r0l,r0h"); +} + +static void +print_unsigned_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + unsigned long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = dis_info; + + (*info->fprintf_func) (info->stream, "%ld,0x%lx", value & 0x7, value >> 3); +} + +static void +print_signed_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + signed long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = dis_info; + + (*info->fprintf_func) (info->stream, "%ld,%ld", value & 0x7, value >> 3); +} + +static void +print_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + /* Always print the size as '.w'. */ + disassemble_info *info = dis_info; + + (*info->fprintf_func) (info->stream, ".w"); +} + +#define POP 0 +#define PUSH 1 + +static void print_pop_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_push_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); + +/* Print a set of registers, R0,R1,A0,A1,SB,FB. */ + +static void +print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED, + int push) +{ + static char * m16c_register_names [] = + { + "r0", "r1", "r2", "r3", "a0", "a1", "sb", "fb" + }; + disassemble_info *info = dis_info; + int mask; + int index = 0; + char* comma = ""; + + if (push) + mask = 0x80; + else + mask = 1; + + if (value & mask) + { + (*info->fprintf_func) (info->stream, "%s", m16c_register_names [0]); + comma = ","; + } + + for (index = 1; index <= 7; ++index) + { + if (push) + mask >>= 1; + else + mask <<= 1; + + if (value & mask) + { + (*info->fprintf_func) (info->stream, "%s%s", comma, + m16c_register_names [index]); + comma = ","; + } + } +} + +static void +print_pop_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_regset (cd, dis_info, value, attrs, pc, length, POP); +} + +static void +print_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + print_regset (cd, dis_info, value, attrs, pc, length, PUSH); +} + +void m32c_cgen_print_operand + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +m32c_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case M32C_OPERAND_A0 : + print_keyword (cd, info, & m32c_cgen_opval_h_a0, 0, 0); + break; + case M32C_OPERAND_A1 : + print_keyword (cd, info, & m32c_cgen_opval_h_a1, 0, 0); + break; + case M32C_OPERAND_AN16_PUSH_S : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_4_1, 0); + break; + case M32C_OPERAND_BIT16AN : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst16_an, 0); + break; + case M32C_OPERAND_BIT16RN : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst16_rn, 0); + break; + case M32C_OPERAND_BIT32ANPREFIXED : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_prefixed, 0); + break; + case M32C_OPERAND_BIT32ANUNPREFIXED : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_unprefixed, 0); + break; + case M32C_OPERAND_BIT32RNPREFIXED : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_prefixed_QI, 0); + break; + case M32C_OPERAND_BIT32RNUNPREFIXED : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_unprefixed_QI, 0); + break; + case M32C_OPERAND_BITBASE16_16_S8 : + print_signed_bitbase (cd, info, fields->f_dsp_16_s8, 0|(1<f_dsp_16_u16, 0, pc, length); + break; + case M32C_OPERAND_BITBASE16_16_U8 : + print_unsigned_bitbase (cd, info, fields->f_dsp_16_u8, 0, pc, length); + break; + case M32C_OPERAND_BITBASE16_8_U11_S : + print_unsigned_bitbase (cd, info, fields->f_bitbase16_u11_S, 0|(1<f_bitbase32_16_s11_unprefixed, 0|(1<f_bitbase32_16_s19_unprefixed, 0|(1<f_bitbase32_16_u11_unprefixed, 0|(1<f_bitbase32_16_u19_unprefixed, 0|(1<f_bitbase32_16_u27_unprefixed, 0|(1<f_bitbase32_24_s11_prefixed, 0|(1<f_bitbase32_24_s19_prefixed, 0|(1<f_bitbase32_24_u11_prefixed, 0|(1<f_bitbase32_24_u19_prefixed, 0|(1<f_bitbase32_24_u27_prefixed, 0|(1<f_dsp_16_u8, 0, pc, length); + break; + case M32C_OPERAND_BITNO32PREFIXED : + print_normal (cd, info, fields->f_bitno32_prefixed, 0, pc, length); + break; + case M32C_OPERAND_BITNO32UNPREFIXED : + print_normal (cd, info, fields->f_bitno32_unprefixed, 0, pc, length); + break; + case M32C_OPERAND_DSP_10_U6 : + print_normal (cd, info, fields->f_dsp_10_u6, 0, pc, length); + break; + case M32C_OPERAND_DSP_16_S16 : + print_normal (cd, info, fields->f_dsp_16_s16, 0|(1<f_dsp_16_s8, 0|(1<f_dsp_16_u16, 0, pc, length); + break; + case M32C_OPERAND_DSP_16_U20 : + print_normal (cd, info, fields->f_dsp_16_u24, 0|(1<f_dsp_16_u24, 0|(1<f_dsp_16_u8, 0, pc, length); + break; + case M32C_OPERAND_DSP_24_S16 : + print_normal (cd, info, fields->f_dsp_24_s16, 0|(1<f_dsp_24_s8, 0|(1<f_dsp_24_u16, 0|(1<f_dsp_24_u24, 0|(1<f_dsp_24_u24, 0|(1<f_dsp_24_u8, 0, pc, length); + break; + case M32C_OPERAND_DSP_32_S16 : + print_normal (cd, info, fields->f_dsp_32_s16, 0|(1<f_dsp_32_s8, 0|(1<f_dsp_32_u16, 0, pc, length); + break; + case M32C_OPERAND_DSP_32_U20 : + print_normal (cd, info, fields->f_dsp_32_u24, 0, pc, length); + break; + case M32C_OPERAND_DSP_32_U24 : + print_normal (cd, info, fields->f_dsp_32_u24, 0, pc, length); + break; + case M32C_OPERAND_DSP_32_U8 : + print_normal (cd, info, fields->f_dsp_32_u8, 0, pc, length); + break; + case M32C_OPERAND_DSP_40_S16 : + print_normal (cd, info, fields->f_dsp_40_s16, 0|(1<f_dsp_40_s8, 0|(1<f_dsp_40_u16, 0, pc, length); + break; + case M32C_OPERAND_DSP_40_U24 : + print_normal (cd, info, fields->f_dsp_40_u24, 0, pc, length); + break; + case M32C_OPERAND_DSP_40_U8 : + print_normal (cd, info, fields->f_dsp_40_u8, 0, pc, length); + break; + case M32C_OPERAND_DSP_48_S16 : + print_normal (cd, info, fields->f_dsp_48_s16, 0|(1<f_dsp_48_s8, 0|(1<f_dsp_48_u16, 0, pc, length); + break; + case M32C_OPERAND_DSP_48_U24 : + print_normal (cd, info, fields->f_dsp_48_u24, 0|(1<f_dsp_48_u8, 0, pc, length); + break; + case M32C_OPERAND_DSP_8_S8 : + print_normal (cd, info, fields->f_dsp_8_s8, 0|(1<f_dsp_8_u16, 0, pc, length); + break; + case M32C_OPERAND_DSP_8_U24 : + print_normal (cd, info, fields->f_dsp_8_u24, 0, pc, length); + break; + case M32C_OPERAND_DSP_8_U6 : + print_normal (cd, info, fields->f_dsp_8_u6, 0, pc, length); + break; + case M32C_OPERAND_DSP_8_U8 : + print_normal (cd, info, fields->f_dsp_8_u8, 0, pc, length); + break; + case M32C_OPERAND_DST16AN : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst16_an, 0); + break; + case M32C_OPERAND_DST16AN_S : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_dst16_an_s, 0); + break; + case M32C_OPERAND_DST16ANHI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_dst16_an, 0); + break; + case M32C_OPERAND_DST16ANQI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_dst16_an, 0); + break; + case M32C_OPERAND_DST16ANQI_S : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_dst16_rn_QI_s, 0); + break; + case M32C_OPERAND_DST16ANSI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_SI, fields->f_dst16_an, 0); + break; + case M32C_OPERAND_DST16RNEXTQI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_ext_QI, fields->f_dst16_rn_ext, 0); + break; + case M32C_OPERAND_DST16RNHI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst16_rn, 0); + break; + case M32C_OPERAND_DST16RNQI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst16_rn, 0); + break; + case M32C_OPERAND_DST16RNQI_S : + print_keyword (cd, info, & m32c_cgen_opval_h_r0l_r0h, fields->f_dst16_rn_QI_s, 0); + break; + case M32C_OPERAND_DST16RNSI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_dst16_rn, 0); + break; + case M32C_OPERAND_DST32ANEXTUNPREFIXED : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_unprefixed, 0); + break; + case M32C_OPERAND_DST32ANPREFIXED : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_prefixed, 0); + break; + case M32C_OPERAND_DST32ANPREFIXEDHI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_dst32_an_prefixed, 0); + break; + case M32C_OPERAND_DST32ANPREFIXEDQI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_dst32_an_prefixed, 0); + break; + case M32C_OPERAND_DST32ANPREFIXEDSI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_prefixed, 0); + break; + case M32C_OPERAND_DST32ANUNPREFIXED : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_unprefixed, 0); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDHI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_dst32_an_unprefixed, 0); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDQI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_dst32_an_unprefixed, 0); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDSI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_unprefixed, 0); + break; + case M32C_OPERAND_DST32R0HI_S : + print_keyword (cd, info, & m32c_cgen_opval_h_r0, 0, 0); + break; + case M32C_OPERAND_DST32R0QI_S : + print_keyword (cd, info, & m32c_cgen_opval_h_r0l, 0, 0); + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDHI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_ext_HI, fields->f_dst32_rn_ext_unprefixed, 0); + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDQI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_ext_QI, fields->f_dst32_rn_ext_unprefixed, 0); + break; + case M32C_OPERAND_DST32RNPREFIXEDHI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst32_rn_prefixed_HI, 0); + break; + case M32C_OPERAND_DST32RNPREFIXEDQI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_prefixed_QI, 0); + break; + case M32C_OPERAND_DST32RNPREFIXEDSI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_dst32_rn_prefixed_SI, 0); + break; + case M32C_OPERAND_DST32RNUNPREFIXEDHI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst32_rn_unprefixed_HI, 0); + break; + case M32C_OPERAND_DST32RNUNPREFIXEDQI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_unprefixed_QI, 0); + break; + case M32C_OPERAND_DST32RNUNPREFIXEDSI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_dst32_rn_unprefixed_SI, 0); + break; + case M32C_OPERAND_G : + print_G (cd, info, 0, 0|(1<f_imm_12_s4, 0|(1<f_imm_13_u3, 0|(1<f_dsp_16_s16, 0|(1<f_dsp_16_s8, 0|(1<f_dsp_16_s32, 0|(1<f_imm_20_s4, 0|(1<f_dsp_24_s16, 0|(1<f_dsp_24_s8, 0|(1<f_dsp_24_s32, 0|(1<f_dsp_32_s16, 0|(1<f_dsp_32_s8, 0|(1<f_dsp_32_s32, 0|(1<f_dsp_40_s16, 0|(1<f_dsp_40_s8, 0|(1<f_dsp_40_s32, 0|(1<f_dsp_48_s16, 0|(1<f_dsp_48_s8, 0|(1<f_dsp_48_s32, 0|(1<f_dsp_56_s16, 0|(1<f_dsp_56_s8, 0|(1<f_dsp_64_s16, 0|(1<f_dsp_8_s16, 0|(1<f_dsp_8_s8, 0|(1<f_imm_8_s4, 0|(1<f_imm_12_s4, 0); + break; + case M32C_OPERAND_IMM_SH_20_S4 : + print_keyword (cd, info, & m32c_cgen_opval_h_shimm, fields->f_imm_20_s4, 0); + break; + case M32C_OPERAND_IMM_SH_8_S4 : + print_keyword (cd, info, & m32c_cgen_opval_h_shimm, fields->f_imm_8_s4, 0); + break; + case M32C_OPERAND_IMM1_S : + print_normal (cd, info, fields->f_imm1_S, 0|(1<f_imm3_S, 0|(1<f_lab_16_8, 0|(1<f_lab_24_8, 0|(1<f_lab_32_8, 0|(1<f_lab_40_8, 0|(1<f_lab_5_3, 0|(1<f_lab_8_16, 0|(1<f_lab_8_24, 0|(1<f_lab_8_8, 0|(1<f_lab32_jmp_s, 0|(1<f_8_8, 0, pc, length); + break; + case M32C_OPERAND_REGSETPUSH : + print_push_regset (cd, info, fields->f_8_8, 0, pc, length); + break; + case M32C_OPERAND_RN16_PUSH_S : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_4_1, 0); + break; + case M32C_OPERAND_S : + print_S (cd, info, 0, 0|(1<f_src16_an, 0); + break; + case M32C_OPERAND_SRC16ANHI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_src16_an, 0); + break; + case M32C_OPERAND_SRC16ANQI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_src16_an, 0); + break; + case M32C_OPERAND_SRC16RNHI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_src16_rn, 0); + break; + case M32C_OPERAND_SRC16RNQI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_src16_rn, 0); + break; + case M32C_OPERAND_SRC32ANPREFIXED : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src32_an_prefixed, 0); + break; + case M32C_OPERAND_SRC32ANPREFIXEDHI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_src32_an_prefixed, 0); + break; + case M32C_OPERAND_SRC32ANPREFIXEDQI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_src32_an_prefixed, 0); + break; + case M32C_OPERAND_SRC32ANPREFIXEDSI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src32_an_prefixed, 0); + break; + case M32C_OPERAND_SRC32ANUNPREFIXED : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src32_an_unprefixed, 0); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDHI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_src32_an_unprefixed, 0); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDQI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_src32_an_unprefixed, 0); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDSI : + print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src32_an_unprefixed, 0); + break; + case M32C_OPERAND_SRC32RNPREFIXEDHI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_src32_rn_prefixed_HI, 0); + break; + case M32C_OPERAND_SRC32RNPREFIXEDQI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_src32_rn_prefixed_QI, 0); + break; + case M32C_OPERAND_SRC32RNPREFIXEDSI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_src32_rn_prefixed_SI, 0); + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDHI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_src32_rn_unprefixed_HI, 0); + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDQI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_src32_rn_unprefixed_QI, 0); + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDSI : + print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_src32_rn_unprefixed_SI, 0); + break; + case M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL : + print_r0l_r0h (cd, info, fields->f_5_1, 0|(1<f_dsp_16_u8, 0); + break; + case M32C_OPERAND_COND16_24 : + print_keyword (cd, info, & m32c_cgen_opval_h_cond16, fields->f_dsp_24_u8, 0); + break; + case M32C_OPERAND_COND16_32 : + print_keyword (cd, info, & m32c_cgen_opval_h_cond16, fields->f_dsp_32_u8, 0); + break; + case M32C_OPERAND_COND16C : + print_keyword (cd, info, & m32c_cgen_opval_h_cond16c, fields->f_cond16, 0); + break; + case M32C_OPERAND_COND16J : + print_keyword (cd, info, & m32c_cgen_opval_h_cond16j, fields->f_cond16, 0); + break; + case M32C_OPERAND_COND16J5 : + print_keyword (cd, info, & m32c_cgen_opval_h_cond16j_5, fields->f_cond16j_5, 0); + break; + case M32C_OPERAND_COND32 : + print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_cond32, 0|(1<f_dsp_16_u8, 0); + break; + case M32C_OPERAND_COND32_24 : + print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_dsp_24_u8, 0); + break; + case M32C_OPERAND_COND32_32 : + print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_dsp_32_u8, 0); + break; + case M32C_OPERAND_COND32_40 : + print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_dsp_40_u8, 0); + break; + case M32C_OPERAND_COND32J : + print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_cond32j, 0|(1<f_21_3, 0); + break; + case M32C_OPERAND_CR1_UNPREFIXED_32 : + print_keyword (cd, info, & m32c_cgen_opval_h_cr1_32, fields->f_13_3, 0); + break; + case M32C_OPERAND_CR16 : + print_keyword (cd, info, & m32c_cgen_opval_h_cr_16, fields->f_9_3, 0); + break; + case M32C_OPERAND_CR2_32 : + print_keyword (cd, info, & m32c_cgen_opval_h_cr2_32, fields->f_13_3, 0); + break; + case M32C_OPERAND_CR3_PREFIXED_32 : + print_keyword (cd, info, & m32c_cgen_opval_h_cr3_32, fields->f_21_3, 0); + break; + case M32C_OPERAND_CR3_UNPREFIXED_32 : + print_keyword (cd, info, & m32c_cgen_opval_h_cr3_32, fields->f_13_3, 0); + break; + case M32C_OPERAND_FLAGS16 : + print_keyword (cd, info, & m32c_cgen_opval_h_flags, fields->f_9_3, 0); + break; + case M32C_OPERAND_FLAGS32 : + print_keyword (cd, info, & m32c_cgen_opval_h_flags, fields->f_13_3, 0); + break; + case M32C_OPERAND_SCCOND32 : + print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_cond16, 0); + break; + case M32C_OPERAND_SIZE : + print_size (cd, info, 0, 0|(1<print_handlers = & m32c_cgen_print_handlers[0]; + cd->print_operand = m32c_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_NORMAL + CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_ADDRESS + CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* Nothing to do. */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `void *' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + m32c_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + bfd_byte *buf, + unsigned int buflen) +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! m32c_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* Length < 0 -> error. */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* Length is in bits, result is in bytes. */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) +{ + bfd_byte buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list +{ + struct cpu_desc_list *next; + int isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_m32c (bfd_vma pc, disassemble_info *info) +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static int prev_isa; + static int prev_mach; + static int prev_endian; + int length; + int isa,mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_m32c +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + isa = CGEN_COMPUTE_ISA (info); +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (isa != prev_isa + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cl->isa == isa && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = isa; + prev_mach = mach; + prev_endian = endian; + cd = m32c_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* Save this away for future reference. */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + m32c_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff -uprN binutils-2.16.91.0.1/opcodes/m32c-ibld.c binutils-2.16.91.0.2/opcodes/m32c-ibld.c --- binutils-2.16.91.0.1/opcodes/m32c-ibld.c 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/opcodes/m32c-ibld.c 2005-07-20 12:27:28.980914739 -0700 @@ -0,0 +1,5109 @@ +/* Instruction building/extraction support for m32c. -*- C -*- + + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't + + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. + + This file is part of the GNU Binutils and GDB, the GNU debugger. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "m32c-desc.h" +#include "m32c-opc.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); +static const char * insert_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); +static int extract_normal + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); +static int extract_insn_normal + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); +#if CGEN_INT_INSN_P +static void put_insn_int_value + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); +static CGEN_INLINE int fill_cache + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); +static CGEN_INLINE long extract_1 + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + + if ((unsigned long) value > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%lu not between 0 and %lu)"), + value, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + unsigned long x; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (CGEN_CPU_DESC cd, +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info, +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, +#endif + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, +#if ! CGEN_INT_INSN_P + bfd_vma pc, +#else + bfd_vma pc ATTRIBUTE_UNUSED, +#endif + long *valuep) +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 32) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* Machine generated code added here. */ + +const char * m32c_cgen_insert_operand + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +m32c_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case M32C_OPERAND_A0 : + break; + case M32C_OPERAND_A1 : + break; + case M32C_OPERAND_AN16_PUSH_S : + errmsg = insert_normal (cd, fields->f_4_1, 0, 0, 4, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_BIT16AN : + errmsg = insert_normal (cd, fields->f_dst16_an, 0, 0, 15, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_BIT16RN : + errmsg = insert_normal (cd, fields->f_dst16_rn, 0, 0, 14, 2, 32, total_length, buffer); + break; + case M32C_OPERAND_BIT32ANPREFIXED : + errmsg = insert_normal (cd, fields->f_dst32_an_prefixed, 0, 0, 17, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_BIT32ANUNPREFIXED : + errmsg = insert_normal (cd, fields->f_dst32_an_unprefixed, 0, 0, 9, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_BIT32RNPREFIXED : + { + long value = fields->f_dst32_rn_prefixed_QI; + value = (((((((~ (value))) << (1))) & (2))) | (((((unsigned int) (value) >> (1))) & (1)))); + errmsg = insert_normal (cd, value, 0, 0, 16, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_BIT32RNUNPREFIXED : + { + long value = fields->f_dst32_rn_unprefixed_QI; + value = (((((((~ (value))) << (1))) & (2))) | (((((unsigned int) (value) >> (1))) & (1)))); + errmsg = insert_normal (cd, value, 0, 0, 8, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_BITBASE16_16_S8 : + errmsg = insert_normal (cd, fields->f_dsp_16_s8, 0|(1<f_dsp_16_u16; + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 0, 16, 16, 32, total_length, buffer); + } + break; + case M32C_OPERAND_BITBASE16_16_U8 : + errmsg = insert_normal (cd, fields->f_dsp_16_u8, 0, 0, 16, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_BITBASE16_8_U11_S : + { +{ + FLD (f_bitno16_S) = ((FLD (f_bitbase16_u11_S)) & (7)); + FLD (f_dsp_8_u8) = ((((unsigned int) (FLD (f_bitbase16_u11_S)) >> (3))) & (255)); +} + errmsg = insert_normal (cd, fields->f_bitno16_S, 0, 0, 5, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_8_u8, 0, 0, 8, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED : + { +{ + FLD (f_bitno32_unprefixed) = ((FLD (f_bitbase32_16_s11_unprefixed)) & (7)); + FLD (f_dsp_16_s8) = ((int) (FLD (f_bitbase32_16_s11_unprefixed)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_bitno32_unprefixed, 0, 0, 13, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_16_s8, 0|(1<> (3)); +} + errmsg = insert_normal (cd, fields->f_bitno32_unprefixed, 0, 0, 13, 3, 32, total_length, buffer); + if (errmsg) + break; + { + long value = fields->f_dsp_16_s16; + value = EXTHISI (((HI) (INT) (((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<> (3))) & (255)); +} + errmsg = insert_normal (cd, fields->f_bitno32_unprefixed, 0, 0, 13, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_16_u8, 0, 0, 16, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED : + { +{ + FLD (f_bitno32_unprefixed) = ((FLD (f_bitbase32_16_u19_unprefixed)) & (7)); + FLD (f_dsp_16_u16) = ((((unsigned int) (FLD (f_bitbase32_16_u19_unprefixed)) >> (3))) & (65535)); +} + errmsg = insert_normal (cd, fields->f_bitno32_unprefixed, 0, 0, 13, 3, 32, total_length, buffer); + if (errmsg) + break; + { + long value = fields->f_dsp_16_u16; + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 0, 16, 16, 32, total_length, buffer); + } + if (errmsg) + break; + } + break; + case M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED : + { +{ + FLD (f_bitno32_unprefixed) = ((FLD (f_bitbase32_16_u27_unprefixed)) & (7)); + FLD (f_dsp_16_u16) = ((((unsigned int) (FLD (f_bitbase32_16_u27_unprefixed)) >> (3))) & (65535)); + FLD (f_dsp_32_u8) = ((((unsigned int) (FLD (f_bitbase32_16_u27_unprefixed)) >> (19))) & (255)); +} + errmsg = insert_normal (cd, fields->f_bitno32_unprefixed, 0, 0, 13, 3, 32, total_length, buffer); + if (errmsg) + break; + { + long value = fields->f_dsp_16_u16; + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 0, 16, 16, 32, total_length, buffer); + } + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_32_u8, 0, 32, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_BITBASE32_24_S11_PREFIXED : + { +{ + FLD (f_bitno32_prefixed) = ((FLD (f_bitbase32_24_s11_prefixed)) & (7)); + FLD (f_dsp_24_s8) = ((int) (FLD (f_bitbase32_24_s11_prefixed)) >> (3)); +} + errmsg = insert_normal (cd, fields->f_bitno32_prefixed, 0, 0, 21, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_24_s8, 0|(1<> (3))) & (255)); + FLD (f_dsp_32_s8) = ((int) (FLD (f_bitbase32_24_s19_prefixed)) >> (11)); +} + errmsg = insert_normal (cd, fields->f_bitno32_prefixed, 0, 0, 21, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_32_s8, 0|(1<> (3))) & (255)); +} + errmsg = insert_normal (cd, fields->f_bitno32_prefixed, 0, 0, 21, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_BITBASE32_24_U19_PREFIXED : + { +{ + FLD (f_bitno32_prefixed) = ((FLD (f_bitbase32_24_u19_prefixed)) & (7)); + FLD (f_dsp_24_u8) = ((((unsigned int) (FLD (f_bitbase32_24_u19_prefixed)) >> (3))) & (255)); + FLD (f_dsp_32_u8) = ((((unsigned int) (FLD (f_bitbase32_24_u19_prefixed)) >> (11))) & (255)); +} + errmsg = insert_normal (cd, fields->f_bitno32_prefixed, 0, 0, 21, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_32_u8, 0, 32, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_BITBASE32_24_U27_PREFIXED : + { +{ + FLD (f_bitno32_prefixed) = ((FLD (f_bitbase32_24_u27_prefixed)) & (7)); + FLD (f_dsp_24_u8) = ((((unsigned int) (FLD (f_bitbase32_24_u27_prefixed)) >> (3))) & (255)); + FLD (f_dsp_32_u16) = ((((unsigned int) (FLD (f_bitbase32_24_u27_prefixed)) >> (11))) & (65535)); +} + errmsg = insert_normal (cd, fields->f_bitno32_prefixed, 0, 0, 21, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + { + long value = fields->f_dsp_32_u16; + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 32, 0, 16, 32, total_length, buffer); + } + if (errmsg) + break; + } + break; + case M32C_OPERAND_BITNO16R : + errmsg = insert_normal (cd, fields->f_dsp_16_u8, 0, 0, 16, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_BITNO32PREFIXED : + errmsg = insert_normal (cd, fields->f_bitno32_prefixed, 0, 0, 21, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_BITNO32UNPREFIXED : + errmsg = insert_normal (cd, fields->f_bitno32_unprefixed, 0, 0, 13, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_DSP_10_U6 : + errmsg = insert_normal (cd, fields->f_dsp_10_u6, 0, 0, 10, 6, 32, total_length, buffer); + break; + case M32C_OPERAND_DSP_16_S16 : + { + long value = fields->f_dsp_16_s16; + value = EXTHISI (((HI) (INT) (((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_16_s8, 0|(1<f_dsp_16_u16; + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 0, 16, 16, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DSP_16_U20 : + { +{ + FLD (f_dsp_16_u16) = ((FLD (f_dsp_16_u24)) & (65535)); + FLD (f_dsp_32_u8) = ((((unsigned int) (FLD (f_dsp_16_u24)) >> (16))) & (255)); +} + { + long value = fields->f_dsp_16_u16; + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 0, 16, 16, 32, total_length, buffer); + } + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_32_u8, 0, 32, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_DSP_16_U24 : + { +{ + FLD (f_dsp_16_u16) = ((FLD (f_dsp_16_u24)) & (65535)); + FLD (f_dsp_32_u8) = ((((unsigned int) (FLD (f_dsp_16_u24)) >> (16))) & (255)); +} + { + long value = fields->f_dsp_16_u16; + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 0, 16, 16, 32, total_length, buffer); + } + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_32_u8, 0, 32, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_DSP_16_U8 : + errmsg = insert_normal (cd, fields->f_dsp_16_u8, 0, 0, 16, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_DSP_24_S16 : + { +{ + FLD (f_dsp_24_u8) = ((FLD (f_dsp_24_s16)) & (255)); + FLD (f_dsp_32_u8) = ((((unsigned int) (FLD (f_dsp_24_s16)) >> (8))) & (255)); +} + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_32_u8, 0, 32, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_DSP_24_S8 : + errmsg = insert_normal (cd, fields->f_dsp_24_s8, 0|(1<> (8))) & (255)); +} + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_32_u8, 0, 32, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_DSP_24_U20 : + { +{ + FLD (f_dsp_24_u8) = ((FLD (f_dsp_24_u24)) & (255)); + FLD (f_dsp_32_u16) = ((((unsigned int) (FLD (f_dsp_24_u24)) >> (8))) & (65535)); +} + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + { + long value = fields->f_dsp_32_u16; + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 32, 0, 16, 32, total_length, buffer); + } + if (errmsg) + break; + } + break; + case M32C_OPERAND_DSP_24_U24 : + { +{ + FLD (f_dsp_24_u8) = ((FLD (f_dsp_24_u24)) & (255)); + FLD (f_dsp_32_u16) = ((((unsigned int) (FLD (f_dsp_24_u24)) >> (8))) & (65535)); +} + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + { + long value = fields->f_dsp_32_u16; + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 32, 0, 16, 32, total_length, buffer); + } + if (errmsg) + break; + } + break; + case M32C_OPERAND_DSP_24_U8 : + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_DSP_32_S16 : + { + long value = fields->f_dsp_32_s16; + value = EXTHISI (((HI) (INT) (((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_32_s8, 0|(1<f_dsp_32_u16; + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 32, 0, 16, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DSP_32_U20 : + { + long value = fields->f_dsp_32_u24; + value = ((((((((unsigned int) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (16711680)))); + errmsg = insert_normal (cd, value, 0, 32, 0, 24, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DSP_32_U24 : + { + long value = fields->f_dsp_32_u24; + value = ((((((((unsigned int) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (16711680)))); + errmsg = insert_normal (cd, value, 0, 32, 0, 24, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DSP_32_U8 : + errmsg = insert_normal (cd, fields->f_dsp_32_u8, 0, 32, 0, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_DSP_40_S16 : + { + long value = fields->f_dsp_40_s16; + value = EXTHISI (((HI) (INT) (((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_40_s8, 0|(1<f_dsp_40_u16; + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 32, 8, 16, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DSP_40_U24 : + { + long value = fields->f_dsp_40_u24; + value = ((((((((unsigned int) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (16711680)))); + errmsg = insert_normal (cd, value, 0, 32, 8, 24, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DSP_40_U8 : + errmsg = insert_normal (cd, fields->f_dsp_40_u8, 0, 32, 8, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_DSP_48_S16 : + { + long value = fields->f_dsp_48_s16; + value = EXTHISI (((HI) (INT) (((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_48_s8, 0|(1<f_dsp_48_u16; + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 32, 16, 16, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DSP_48_U24 : + { +{ + FLD (f_dsp_64_u8) = ((((unsigned int) (FLD (f_dsp_48_u24)) >> (16))) & (255)); + FLD (f_dsp_48_u16) = ((FLD (f_dsp_48_u24)) & (65535)); +} + { + long value = fields->f_dsp_48_u16; + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 32, 16, 16, 32, total_length, buffer); + } + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_64_u8, 0, 64, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_DSP_48_U8 : + errmsg = insert_normal (cd, fields->f_dsp_48_u8, 0, 32, 16, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_DSP_8_S8 : + errmsg = insert_normal (cd, fields->f_dsp_8_s8, 0|(1<f_dsp_8_u16; + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 0, 8, 16, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DSP_8_U24 : + { + long value = fields->f_dsp_8_u24; + value = ((((((unsigned int) (value) >> (16))) | (((value) & (65280))))) | (((((value) & (255))) << (16)))); + errmsg = insert_normal (cd, value, 0, 0, 8, 24, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DSP_8_U6 : + errmsg = insert_normal (cd, fields->f_dsp_8_u6, 0, 0, 8, 6, 32, total_length, buffer); + break; + case M32C_OPERAND_DSP_8_U8 : + errmsg = insert_normal (cd, fields->f_dsp_8_u8, 0, 0, 8, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16AN : + errmsg = insert_normal (cd, fields->f_dst16_an, 0, 0, 15, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16AN_S : + errmsg = insert_normal (cd, fields->f_dst16_an_s, 0, 0, 4, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16ANHI : + errmsg = insert_normal (cd, fields->f_dst16_an, 0, 0, 15, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16ANQI : + errmsg = insert_normal (cd, fields->f_dst16_an, 0, 0, 15, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16ANQI_S : + errmsg = insert_normal (cd, fields->f_dst16_rn_QI_s, 0, 0, 5, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16ANSI : + errmsg = insert_normal (cd, fields->f_dst16_an, 0, 0, 15, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16RNEXTQI : + errmsg = insert_normal (cd, fields->f_dst16_rn_ext, 0, 0, 14, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16RNHI : + errmsg = insert_normal (cd, fields->f_dst16_rn, 0, 0, 14, 2, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16RNQI : + errmsg = insert_normal (cd, fields->f_dst16_rn, 0, 0, 14, 2, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16RNQI_S : + errmsg = insert_normal (cd, fields->f_dst16_rn_QI_s, 0, 0, 5, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST16RNSI : + errmsg = insert_normal (cd, fields->f_dst16_rn, 0, 0, 14, 2, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32ANEXTUNPREFIXED : + errmsg = insert_normal (cd, fields->f_dst32_an_unprefixed, 0, 0, 9, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32ANPREFIXED : + errmsg = insert_normal (cd, fields->f_dst32_an_prefixed, 0, 0, 17, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32ANPREFIXEDHI : + errmsg = insert_normal (cd, fields->f_dst32_an_prefixed, 0, 0, 17, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32ANPREFIXEDQI : + errmsg = insert_normal (cd, fields->f_dst32_an_prefixed, 0, 0, 17, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32ANPREFIXEDSI : + errmsg = insert_normal (cd, fields->f_dst32_an_prefixed, 0, 0, 17, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32ANUNPREFIXED : + errmsg = insert_normal (cd, fields->f_dst32_an_unprefixed, 0, 0, 9, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDHI : + errmsg = insert_normal (cd, fields->f_dst32_an_unprefixed, 0, 0, 9, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDQI : + errmsg = insert_normal (cd, fields->f_dst32_an_unprefixed, 0, 0, 9, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDSI : + errmsg = insert_normal (cd, fields->f_dst32_an_unprefixed, 0, 0, 9, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32R0HI_S : + break; + case M32C_OPERAND_DST32R0QI_S : + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDHI : + errmsg = insert_normal (cd, fields->f_dst32_rn_ext_unprefixed, 0, 0, 9, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDQI : + errmsg = insert_normal (cd, fields->f_dst32_rn_ext_unprefixed, 0, 0, 9, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_DST32RNPREFIXEDHI : + { + long value = fields->f_dst32_rn_prefixed_HI; + value = ((((value) + (2))) % (4)); + errmsg = insert_normal (cd, value, 0, 0, 16, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DST32RNPREFIXEDQI : + { + long value = fields->f_dst32_rn_prefixed_QI; + value = (((((((~ (value))) << (1))) & (2))) | (((((unsigned int) (value) >> (1))) & (1)))); + errmsg = insert_normal (cd, value, 0, 0, 16, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DST32RNPREFIXEDSI : + { + long value = fields->f_dst32_rn_prefixed_SI; + value = ((value) + (2)); + errmsg = insert_normal (cd, value, 0, 0, 16, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DST32RNUNPREFIXEDHI : + { + long value = fields->f_dst32_rn_unprefixed_HI; + value = ((((value) + (2))) % (4)); + errmsg = insert_normal (cd, value, 0, 0, 8, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DST32RNUNPREFIXEDQI : + { + long value = fields->f_dst32_rn_unprefixed_QI; + value = (((((((~ (value))) << (1))) & (2))) | (((((unsigned int) (value) >> (1))) & (1)))); + errmsg = insert_normal (cd, value, 0, 0, 8, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_DST32RNUNPREFIXEDSI : + { + long value = fields->f_dst32_rn_unprefixed_SI; + value = ((value) + (2)); + errmsg = insert_normal (cd, value, 0, 0, 8, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_G : + break; + case M32C_OPERAND_IMM_12_S4 : + errmsg = insert_normal (cd, fields->f_imm_12_s4, 0|(1<f_imm_13_u3, 0, 0, 13, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_IMM_16_HI : + { + long value = fields->f_dsp_16_s16; + value = EXTHISI (((HI) (INT) (((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_16_s8, 0|(1<> (16))) & (65535)); + FLD (f_dsp_16_u16) = ((FLD (f_dsp_16_s32)) & (65535)); +} + { + long value = fields->f_dsp_16_u16; + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 0, 16, 16, 32, total_length, buffer); + } + if (errmsg) + break; + { + long value = fields->f_dsp_32_u16; + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 32, 0, 16, 32, total_length, buffer); + } + if (errmsg) + break; + } + break; + case M32C_OPERAND_IMM_20_S4 : + errmsg = insert_normal (cd, fields->f_imm_20_s4, 0|(1<> (8))) & (255)); +} + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_32_u8, 0, 32, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_IMM_24_QI : + errmsg = insert_normal (cd, fields->f_dsp_24_s8, 0|(1<> (8))) & (16777215)); + FLD (f_dsp_24_u8) = ((FLD (f_dsp_24_s32)) & (255)); +} + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + { + long value = fields->f_dsp_32_u24; + value = ((((((((unsigned int) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (16711680)))); + errmsg = insert_normal (cd, value, 0, 32, 0, 24, 32, total_length, buffer); + } + if (errmsg) + break; + } + break; + case M32C_OPERAND_IMM_32_HI : + { + long value = fields->f_dsp_32_s16; + value = EXTHISI (((HI) (INT) (((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_32_s8, 0|(1<f_dsp_32_s32; + value = EXTSISI (((((((((unsigned int) (value) >> (24))) & (255))) | (((((unsigned int) (value) >> (8))) & (65280))))) | (((((((value) << (8))) & (16711680))) | (((((value) << (24))) & (0xff000000))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_40_s16; + value = EXTHISI (((HI) (INT) (((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_40_s8, 0|(1<> (24))) & (255)); + FLD (f_dsp_40_u24) = ((FLD (f_dsp_40_s32)) & (16777215)); +} + { + long value = fields->f_dsp_40_u24; + value = ((((((((unsigned int) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (16711680)))); + errmsg = insert_normal (cd, value, 0, 32, 8, 24, 32, total_length, buffer); + } + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_64_u8, 0, 64, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_IMM_48_HI : + { + long value = fields->f_dsp_48_s16; + value = EXTHISI (((HI) (INT) (((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_48_s8, 0|(1<> (16))) & (65535)); + FLD (f_dsp_48_u16) = ((FLD (f_dsp_48_s32)) & (65535)); +} + { + long value = fields->f_dsp_48_u16; + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 32, 16, 16, 32, total_length, buffer); + } + if (errmsg) + break; + { + long value = fields->f_dsp_64_u16; + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + errmsg = insert_normal (cd, value, 0, 64, 0, 16, 32, total_length, buffer); + } + if (errmsg) + break; + } + break; + case M32C_OPERAND_IMM_56_HI : + { +{ + FLD (f_dsp_56_u8) = ((FLD (f_dsp_56_s16)) & (255)); + FLD (f_dsp_64_u8) = ((((unsigned int) (FLD (f_dsp_56_s16)) >> (8))) & (255)); +} + errmsg = insert_normal (cd, fields->f_dsp_56_u8, 0, 32, 24, 8, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_dsp_64_u8, 0, 64, 0, 8, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_IMM_56_QI : + errmsg = insert_normal (cd, fields->f_dsp_56_s8, 0|(1<f_dsp_64_s16; + value = EXTHISI (((HI) (INT) (((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_8_s16; + value = EXTHISI (((HI) (INT) (((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + errmsg = insert_normal (cd, value, 0|(1<f_dsp_8_s8, 0|(1<f_imm_8_s4, 0|(1<f_imm_12_s4, 0|(1<f_imm_20_s4, 0|(1<f_imm_8_s4, 0|(1<f_imm1_S; + value = ((value) - (1)); + errmsg = insert_normal (cd, value, 0, 0, 2, 1, 32, total_length, buffer); + } + break; + case M32C_OPERAND_IMM3_S : + { +{ + FLD (f_7_1) = ((((FLD (f_imm3_S)) - (1))) & (1)); + FLD (f_2_2) = ((((unsigned int) (((FLD (f_imm3_S)) - (1))) >> (1))) & (3)); +} + errmsg = insert_normal (cd, fields->f_2_2, 0, 0, 2, 2, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_7_1, 0, 0, 7, 1, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_LAB_16_8 : + { + long value = fields->f_lab_16_8; + value = ((value) - (((pc) + (2)))); + errmsg = insert_normal (cd, value, 0|(1<f_lab_24_8; + value = ((value) - (((pc) + (2)))); + errmsg = insert_normal (cd, value, 0|(1<f_lab_32_8; + value = ((value) - (((pc) + (2)))); + errmsg = insert_normal (cd, value, 0|(1<f_lab_40_8; + value = ((value) - (((pc) + (2)))); + errmsg = insert_normal (cd, value, 0|(1<f_lab_5_3; + value = ((value) - (((pc) + (2)))); + errmsg = insert_normal (cd, value, 0|(1<f_lab_8_16; + value = ((((((((value) - (((pc) + (1))))) & (255))) << (8))) | (((unsigned int) (((((value) - (((pc) + (1))))) & (65535))) >> (8)))); + errmsg = insert_normal (cd, value, 0|(1<f_lab_8_24; + value = ((((((unsigned int) (value) >> (16))) | (((value) & (65280))))) | (((((value) & (255))) << (16)))); + errmsg = insert_normal (cd, value, 0|(1<f_lab_8_8; + value = ((value) - (((pc) + (1)))); + errmsg = insert_normal (cd, value, 0|(1<> (1)); +} + errmsg = insert_normal (cd, fields->f_2_2, 0, 0, 2, 2, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_7_1, 0, 0, 7, 1, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_Q : + break; + case M32C_OPERAND_R0 : + break; + case M32C_OPERAND_R0H : + break; + case M32C_OPERAND_R0L : + break; + case M32C_OPERAND_R1 : + break; + case M32C_OPERAND_R1R2R0 : + break; + case M32C_OPERAND_R2 : + break; + case M32C_OPERAND_R2R0 : + break; + case M32C_OPERAND_R3 : + break; + case M32C_OPERAND_R3R1 : + break; + case M32C_OPERAND_REGSETPOP : + errmsg = insert_normal (cd, fields->f_8_8, 0, 0, 8, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_REGSETPUSH : + errmsg = insert_normal (cd, fields->f_8_8, 0, 0, 8, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_RN16_PUSH_S : + errmsg = insert_normal (cd, fields->f_4_1, 0, 0, 4, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_S : + break; + case M32C_OPERAND_SRC16AN : + errmsg = insert_normal (cd, fields->f_src16_an, 0, 0, 11, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC16ANHI : + errmsg = insert_normal (cd, fields->f_src16_an, 0, 0, 11, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC16ANQI : + errmsg = insert_normal (cd, fields->f_src16_an, 0, 0, 11, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC16RNHI : + errmsg = insert_normal (cd, fields->f_src16_rn, 0, 0, 10, 2, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC16RNQI : + errmsg = insert_normal (cd, fields->f_src16_rn, 0, 0, 10, 2, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC32ANPREFIXED : + errmsg = insert_normal (cd, fields->f_src32_an_prefixed, 0, 0, 19, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC32ANPREFIXEDHI : + errmsg = insert_normal (cd, fields->f_src32_an_prefixed, 0, 0, 19, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC32ANPREFIXEDQI : + errmsg = insert_normal (cd, fields->f_src32_an_prefixed, 0, 0, 19, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC32ANPREFIXEDSI : + errmsg = insert_normal (cd, fields->f_src32_an_prefixed, 0, 0, 19, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC32ANUNPREFIXED : + errmsg = insert_normal (cd, fields->f_src32_an_unprefixed, 0, 0, 11, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDHI : + errmsg = insert_normal (cd, fields->f_src32_an_unprefixed, 0, 0, 11, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDQI : + errmsg = insert_normal (cd, fields->f_src32_an_unprefixed, 0, 0, 11, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDSI : + errmsg = insert_normal (cd, fields->f_src32_an_unprefixed, 0, 0, 11, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_SRC32RNPREFIXEDHI : + { + long value = fields->f_src32_rn_prefixed_HI; + value = ((((value) + (2))) % (4)); + errmsg = insert_normal (cd, value, 0, 0, 18, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_SRC32RNPREFIXEDQI : + { + long value = fields->f_src32_rn_prefixed_QI; + value = (((((((~ (value))) << (1))) & (2))) | (((((unsigned int) (value) >> (1))) & (1)))); + errmsg = insert_normal (cd, value, 0, 0, 18, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_SRC32RNPREFIXEDSI : + { + long value = fields->f_src32_rn_prefixed_SI; + value = ((value) + (2)); + errmsg = insert_normal (cd, value, 0, 0, 18, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDHI : + { + long value = fields->f_src32_rn_unprefixed_HI; + value = ((((value) + (2))) % (4)); + errmsg = insert_normal (cd, value, 0, 0, 10, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDQI : + { + long value = fields->f_src32_rn_unprefixed_QI; + value = (((((((~ (value))) << (1))) & (2))) | (((((unsigned int) (value) >> (1))) & (1)))); + errmsg = insert_normal (cd, value, 0, 0, 10, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDSI : + { + long value = fields->f_src32_rn_unprefixed_SI; + value = ((value) + (2)); + errmsg = insert_normal (cd, value, 0, 0, 10, 2, 32, total_length, buffer); + } + break; + case M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL : + errmsg = insert_normal (cd, fields->f_5_1, 0, 0, 5, 1, 32, total_length, buffer); + break; + case M32C_OPERAND_X : + break; + case M32C_OPERAND_Z : + break; + case M32C_OPERAND_COND16_16 : + errmsg = insert_normal (cd, fields->f_dsp_16_u8, 0, 0, 16, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_COND16_24 : + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_COND16_32 : + errmsg = insert_normal (cd, fields->f_dsp_32_u8, 0, 32, 0, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_COND16C : + errmsg = insert_normal (cd, fields->f_cond16, 0, 0, 12, 4, 32, total_length, buffer); + break; + case M32C_OPERAND_COND16J : + errmsg = insert_normal (cd, fields->f_cond16, 0, 0, 12, 4, 32, total_length, buffer); + break; + case M32C_OPERAND_COND16J5 : + errmsg = insert_normal (cd, fields->f_cond16j_5, 0, 0, 5, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_COND32 : + { +{ + FLD (f_9_1) = ((((unsigned int) (FLD (f_cond32)) >> (3))) & (1)); + FLD (f_13_3) = ((FLD (f_cond32)) & (7)); +} + errmsg = insert_normal (cd, fields->f_9_1, 0, 0, 9, 1, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_13_3, 0, 0, 13, 3, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_COND32_16 : + errmsg = insert_normal (cd, fields->f_dsp_16_u8, 0, 0, 16, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_COND32_24 : + errmsg = insert_normal (cd, fields->f_dsp_24_u8, 0, 0, 24, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_COND32_32 : + errmsg = insert_normal (cd, fields->f_dsp_32_u8, 0, 32, 0, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_COND32_40 : + errmsg = insert_normal (cd, fields->f_dsp_40_u8, 0, 32, 8, 8, 32, total_length, buffer); + break; + case M32C_OPERAND_COND32J : + { +{ + FLD (f_1_3) = ((((unsigned int) (FLD (f_cond32j)) >> (1))) & (7)); + FLD (f_7_1) = ((FLD (f_cond32j)) & (1)); +} + errmsg = insert_normal (cd, fields->f_1_3, 0, 0, 1, 3, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_7_1, 0, 0, 7, 1, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case M32C_OPERAND_CR1_PREFIXED_32 : + errmsg = insert_normal (cd, fields->f_21_3, 0, 0, 21, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_CR1_UNPREFIXED_32 : + errmsg = insert_normal (cd, fields->f_13_3, 0, 0, 13, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_CR16 : + errmsg = insert_normal (cd, fields->f_9_3, 0, 0, 9, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_CR2_32 : + errmsg = insert_normal (cd, fields->f_13_3, 0, 0, 13, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_CR3_PREFIXED_32 : + errmsg = insert_normal (cd, fields->f_21_3, 0, 0, 21, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_CR3_UNPREFIXED_32 : + errmsg = insert_normal (cd, fields->f_13_3, 0, 0, 13, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_FLAGS16 : + errmsg = insert_normal (cd, fields->f_9_3, 0, 0, 9, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_FLAGS32 : + errmsg = insert_normal (cd, fields->f_13_3, 0, 0, 13, 3, 32, total_length, buffer); + break; + case M32C_OPERAND_SCCOND32 : + errmsg = insert_normal (cd, fields->f_cond16, 0, 0, 12, 4, 32, total_length, buffer); + break; + case M32C_OPERAND_SIZE : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int m32c_cgen_extract_operand + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +m32c_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case M32C_OPERAND_A0 : + break; + case M32C_OPERAND_A1 : + break; + case M32C_OPERAND_AN16_PUSH_S : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 1, 32, total_length, pc, & fields->f_4_1); + break; + case M32C_OPERAND_BIT16AN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_dst16_an); + break; + case M32C_OPERAND_BIT16RN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 2, 32, total_length, pc, & fields->f_dst16_rn); + break; + case M32C_OPERAND_BIT32ANPREFIXED : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_dst32_an_prefixed); + break; + case M32C_OPERAND_BIT32ANUNPREFIXED : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_BIT32RNPREFIXED : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 2, 32, total_length, pc, & value); + value = (((((~ (((unsigned int) (value) >> (1))))) & (1))) | (((((value) << (1))) & (2)))); + fields->f_dst32_rn_prefixed_QI = value; + } + break; + case M32C_OPERAND_BIT32RNUNPREFIXED : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 2, 32, total_length, pc, & value); + value = (((((~ (((unsigned int) (value) >> (1))))) & (1))) | (((((value) << (1))) & (2)))); + fields->f_dst32_rn_unprefixed_QI = value; + } + break; + case M32C_OPERAND_BITBASE16_16_S8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_16_s8); + break; + case M32C_OPERAND_BITBASE16_16_U16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_16_u16 = value; + } + break; + case M32C_OPERAND_BITBASE16_16_U8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 8, 32, total_length, pc, & fields->f_dsp_16_u8); + break; + case M32C_OPERAND_BITBASE16_8_U11_S : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_bitno16_S); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_dsp_8_u8); + if (length <= 0) break; +{ + FLD (f_bitbase16_u11_S) = ((((FLD (f_dsp_8_u8)) << (3))) | (FLD (f_bitno16_S))); +} + } + break; + case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_bitno32_unprefixed); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_16_s8); + if (length <= 0) break; +{ + FLD (f_bitbase32_16_s11_unprefixed) = ((((FLD (f_dsp_16_s8)) << (3))) | (FLD (f_bitno32_unprefixed))); +} + } + break; + case M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_bitno32_unprefixed); + if (length <= 0) break; + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_16_s16 = value; + } + if (length <= 0) break; +{ + FLD (f_bitbase32_16_s19_unprefixed) = ((((FLD (f_dsp_16_s16)) << (3))) | (FLD (f_bitno32_unprefixed))); +} + } + break; + case M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_bitno32_unprefixed); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 8, 32, total_length, pc, & fields->f_dsp_16_u8); + if (length <= 0) break; +{ + FLD (f_bitbase32_16_u11_unprefixed) = ((((FLD (f_dsp_16_u8)) << (3))) | (FLD (f_bitno32_unprefixed))); +} + } + break; + case M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_bitno32_unprefixed); + if (length <= 0) break; + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_16_u16 = value; + } + if (length <= 0) break; +{ + FLD (f_bitbase32_16_u19_unprefixed) = ((((FLD (f_dsp_16_u16)) << (3))) | (FLD (f_bitno32_unprefixed))); +} + } + break; + case M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_bitno32_unprefixed); + if (length <= 0) break; + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_16_u16 = value; + } + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_u8); + if (length <= 0) break; +{ + FLD (f_bitbase32_16_u27_unprefixed) = ((((FLD (f_dsp_16_u16)) << (3))) | (((((FLD (f_dsp_32_u8)) << (19))) | (FLD (f_bitno32_unprefixed))))); +} + } + break; + case M32C_OPERAND_BITBASE32_24_S11_PREFIXED : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 3, 32, total_length, pc, & fields->f_bitno32_prefixed); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_24_s8); + if (length <= 0) break; +{ + FLD (f_bitbase32_24_s11_prefixed) = ((((FLD (f_dsp_24_s8)) << (3))) | (FLD (f_bitno32_prefixed))); +} + } + break; + case M32C_OPERAND_BITBASE32_24_S19_PREFIXED : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 3, 32, total_length, pc, & fields->f_bitno32_prefixed); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_32_s8); + if (length <= 0) break; +{ + FLD (f_bitbase32_24_s19_prefixed) = ((((FLD (f_dsp_24_u8)) << (3))) | (((((FLD (f_dsp_32_s8)) << (11))) | (FLD (f_bitno32_prefixed))))); +} + } + break; + case M32C_OPERAND_BITBASE32_24_U11_PREFIXED : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 3, 32, total_length, pc, & fields->f_bitno32_prefixed); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + if (length <= 0) break; +{ + FLD (f_bitbase32_24_u11_prefixed) = ((((FLD (f_dsp_24_u8)) << (3))) | (FLD (f_bitno32_prefixed))); +} + } + break; + case M32C_OPERAND_BITBASE32_24_U19_PREFIXED : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 3, 32, total_length, pc, & fields->f_bitno32_prefixed); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_u8); + if (length <= 0) break; +{ + FLD (f_bitbase32_24_u19_prefixed) = ((((FLD (f_dsp_24_u8)) << (3))) | (((((FLD (f_dsp_32_u8)) << (11))) | (FLD (f_bitno32_prefixed))))); +} + } + break; + case M32C_OPERAND_BITBASE32_24_U27_PREFIXED : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 3, 32, total_length, pc, & fields->f_bitno32_prefixed); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + if (length <= 0) break; + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 16, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_32_u16 = value; + } + if (length <= 0) break; +{ + FLD (f_bitbase32_24_u27_prefixed) = ((((FLD (f_dsp_24_u8)) << (3))) | (((((FLD (f_dsp_32_u16)) << (11))) | (FLD (f_bitno32_prefixed))))); +} + } + break; + case M32C_OPERAND_BITNO16R : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 8, 32, total_length, pc, & fields->f_dsp_16_u8); + break; + case M32C_OPERAND_BITNO32PREFIXED : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 3, 32, total_length, pc, & fields->f_bitno32_prefixed); + break; + case M32C_OPERAND_BITNO32UNPREFIXED : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_bitno32_unprefixed); + break; + case M32C_OPERAND_DSP_10_U6 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 6, 32, total_length, pc, & fields->f_dsp_10_u6); + break; + case M32C_OPERAND_DSP_16_S16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_16_s16 = value; + } + break; + case M32C_OPERAND_DSP_16_S8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_16_s8); + break; + case M32C_OPERAND_DSP_16_U16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_16_u16 = value; + } + break; + case M32C_OPERAND_DSP_16_U20 : + { + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_16_u16 = value; + } + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_u8); + if (length <= 0) break; +{ + FLD (f_dsp_16_u24) = ((((FLD (f_dsp_32_u8)) << (16))) | (FLD (f_dsp_16_u16))); +} + } + break; + case M32C_OPERAND_DSP_16_U24 : + { + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_16_u16 = value; + } + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_u8); + if (length <= 0) break; +{ + FLD (f_dsp_16_u24) = ((((FLD (f_dsp_32_u8)) << (16))) | (FLD (f_dsp_16_u16))); +} + } + break; + case M32C_OPERAND_DSP_16_U8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 8, 32, total_length, pc, & fields->f_dsp_16_u8); + break; + case M32C_OPERAND_DSP_24_S16 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_u8); + if (length <= 0) break; +{ + FLD (f_dsp_24_s16) = EXTHISI (((HI) (UINT) (((((FLD (f_dsp_32_u8)) << (8))) | (FLD (f_dsp_24_u8)))))); +} + } + break; + case M32C_OPERAND_DSP_24_S8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_24_s8); + break; + case M32C_OPERAND_DSP_24_U16 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_u8); + if (length <= 0) break; +{ + FLD (f_dsp_24_u16) = ((((FLD (f_dsp_32_u8)) << (8))) | (FLD (f_dsp_24_u8))); +} + } + break; + case M32C_OPERAND_DSP_24_U20 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + if (length <= 0) break; + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 16, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_32_u16 = value; + } + if (length <= 0) break; +{ + FLD (f_dsp_24_u24) = ((((FLD (f_dsp_32_u16)) << (8))) | (FLD (f_dsp_24_u8))); +} + } + break; + case M32C_OPERAND_DSP_24_U24 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + if (length <= 0) break; + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 16, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_32_u16 = value; + } + if (length <= 0) break; +{ + FLD (f_dsp_24_u24) = ((((FLD (f_dsp_32_u16)) << (8))) | (FLD (f_dsp_24_u8))); +} + } + break; + case M32C_OPERAND_DSP_24_U8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + break; + case M32C_OPERAND_DSP_32_S16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_32_s16 = value; + } + break; + case M32C_OPERAND_DSP_32_S8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_32_s8); + break; + case M32C_OPERAND_DSP_32_U16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 16, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_32_u16 = value; + } + break; + case M32C_OPERAND_DSP_32_U20 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 24, 32, total_length, pc, & value); + value = ((((((((unsigned int) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (16711680)))); + fields->f_dsp_32_u24 = value; + } + break; + case M32C_OPERAND_DSP_32_U24 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 24, 32, total_length, pc, & value); + value = ((((((((unsigned int) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (16711680)))); + fields->f_dsp_32_u24 = value; + } + break; + case M32C_OPERAND_DSP_32_U8 : + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_u8); + break; + case M32C_OPERAND_DSP_40_S16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_40_s16 = value; + } + break; + case M32C_OPERAND_DSP_40_S8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_40_s8); + break; + case M32C_OPERAND_DSP_40_U16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 8, 16, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_40_u16 = value; + } + break; + case M32C_OPERAND_DSP_40_U24 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 8, 24, 32, total_length, pc, & value); + value = ((((((((unsigned int) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (16711680)))); + fields->f_dsp_40_u24 = value; + } + break; + case M32C_OPERAND_DSP_40_U8 : + length = extract_normal (cd, ex_info, insn_value, 0, 32, 8, 8, 32, total_length, pc, & fields->f_dsp_40_u8); + break; + case M32C_OPERAND_DSP_48_S16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_48_s16 = value; + } + break; + case M32C_OPERAND_DSP_48_S8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_48_s8); + break; + case M32C_OPERAND_DSP_48_U16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 16, 16, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_48_u16 = value; + } + break; + case M32C_OPERAND_DSP_48_U24 : + { + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 16, 16, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_48_u16 = value; + } + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 64, 0, 8, 32, total_length, pc, & fields->f_dsp_64_u8); + if (length <= 0) break; +{ + FLD (f_dsp_48_u24) = ((((FLD (f_dsp_48_u16)) & (65535))) | (((((FLD (f_dsp_64_u8)) << (16))) & (16711680)))); +} + } + break; + case M32C_OPERAND_DSP_48_U8 : + length = extract_normal (cd, ex_info, insn_value, 0, 32, 16, 8, 32, total_length, pc, & fields->f_dsp_48_u8); + break; + case M32C_OPERAND_DSP_8_S8 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_8_s8); + break; + case M32C_OPERAND_DSP_8_U16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 16, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_8_u16 = value; + } + break; + case M32C_OPERAND_DSP_8_U24 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 24, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (16))) | (((value) & (65280))))) | (((((value) & (255))) << (16)))); + fields->f_dsp_8_u24 = value; + } + break; + case M32C_OPERAND_DSP_8_U6 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 6, 32, total_length, pc, & fields->f_dsp_8_u6); + break; + case M32C_OPERAND_DSP_8_U8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_dsp_8_u8); + break; + case M32C_OPERAND_DST16AN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_dst16_an); + break; + case M32C_OPERAND_DST16AN_S : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 1, 32, total_length, pc, & fields->f_dst16_an_s); + break; + case M32C_OPERAND_DST16ANHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_dst16_an); + break; + case M32C_OPERAND_DST16ANQI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_dst16_an); + break; + case M32C_OPERAND_DST16ANQI_S : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 1, 32, total_length, pc, & fields->f_dst16_rn_QI_s); + break; + case M32C_OPERAND_DST16ANSI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & fields->f_dst16_an); + break; + case M32C_OPERAND_DST16RNEXTQI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 1, 32, total_length, pc, & fields->f_dst16_rn_ext); + break; + case M32C_OPERAND_DST16RNHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 2, 32, total_length, pc, & fields->f_dst16_rn); + break; + case M32C_OPERAND_DST16RNQI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 2, 32, total_length, pc, & fields->f_dst16_rn); + break; + case M32C_OPERAND_DST16RNQI_S : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 1, 32, total_length, pc, & fields->f_dst16_rn_QI_s); + break; + case M32C_OPERAND_DST16RNSI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 14, 2, 32, total_length, pc, & fields->f_dst16_rn); + break; + case M32C_OPERAND_DST32ANEXTUNPREFIXED : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_DST32ANPREFIXED : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_dst32_an_prefixed); + break; + case M32C_OPERAND_DST32ANPREFIXEDHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_dst32_an_prefixed); + break; + case M32C_OPERAND_DST32ANPREFIXEDQI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_dst32_an_prefixed); + break; + case M32C_OPERAND_DST32ANPREFIXEDSI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 1, 32, total_length, pc, & fields->f_dst32_an_prefixed); + break; + case M32C_OPERAND_DST32ANUNPREFIXED : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDQI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_DST32ANUNPREFIXEDSI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_dst32_an_unprefixed); + break; + case M32C_OPERAND_DST32R0HI_S : + break; + case M32C_OPERAND_DST32R0QI_S : + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_dst32_rn_ext_unprefixed); + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDQI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_dst32_rn_ext_unprefixed); + break; + case M32C_OPERAND_DST32RNPREFIXEDHI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 2, 32, total_length, pc, & value); + value = ((((value) + (2))) % (4)); + fields->f_dst32_rn_prefixed_HI = value; + } + break; + case M32C_OPERAND_DST32RNPREFIXEDQI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 2, 32, total_length, pc, & value); + value = (((((~ (((unsigned int) (value) >> (1))))) & (1))) | (((((value) << (1))) & (2)))); + fields->f_dst32_rn_prefixed_QI = value; + } + break; + case M32C_OPERAND_DST32RNPREFIXEDSI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 2, 32, total_length, pc, & value); + value = ((value) - (2)); + fields->f_dst32_rn_prefixed_SI = value; + } + break; + case M32C_OPERAND_DST32RNUNPREFIXEDHI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 2, 32, total_length, pc, & value); + value = ((((value) + (2))) % (4)); + fields->f_dst32_rn_unprefixed_HI = value; + } + break; + case M32C_OPERAND_DST32RNUNPREFIXEDQI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 2, 32, total_length, pc, & value); + value = (((((~ (((unsigned int) (value) >> (1))))) & (1))) | (((((value) << (1))) & (2)))); + fields->f_dst32_rn_unprefixed_QI = value; + } + break; + case M32C_OPERAND_DST32RNUNPREFIXEDSI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 2, 32, total_length, pc, & value); + value = ((value) - (2)); + fields->f_dst32_rn_unprefixed_SI = value; + } + break; + case M32C_OPERAND_G : + break; + case M32C_OPERAND_IMM_12_S4 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm_12_s4); + break; + case M32C_OPERAND_IMM_13_U3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_imm_13_u3); + break; + case M32C_OPERAND_IMM_16_HI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_16_s16 = value; + } + break; + case M32C_OPERAND_IMM_16_QI : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_16_s8); + break; + case M32C_OPERAND_IMM_16_SI : + { + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_16_u16 = value; + } + if (length <= 0) break; + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 16, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_32_u16 = value; + } + if (length <= 0) break; +{ + FLD (f_dsp_16_s32) = ((((FLD (f_dsp_16_u16)) & (65535))) | (((((FLD (f_dsp_32_u16)) << (16))) & (0xffff0000)))); +} + } + break; + case M32C_OPERAND_IMM_20_S4 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm_20_s4); + break; + case M32C_OPERAND_IMM_24_HI : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_u8); + if (length <= 0) break; +{ + FLD (f_dsp_24_s16) = EXTHISI (((HI) (UINT) (((((FLD (f_dsp_32_u8)) << (8))) | (FLD (f_dsp_24_u8)))))); +} + } + break; + case M32C_OPERAND_IMM_24_QI : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_24_s8); + break; + case M32C_OPERAND_IMM_24_SI : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + if (length <= 0) break; + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 24, 32, total_length, pc, & value); + value = ((((((((unsigned int) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (16711680)))); + fields->f_dsp_32_u24 = value; + } + if (length <= 0) break; +{ + FLD (f_dsp_24_s32) = ((((FLD (f_dsp_24_u8)) & (255))) | (((((FLD (f_dsp_32_u24)) << (8))) & (0xffffff00)))); +} + } + break; + case M32C_OPERAND_IMM_32_HI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_32_s16 = value; + } + break; + case M32C_OPERAND_IMM_32_QI : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_32_s8); + break; + case M32C_OPERAND_IMM_32_SI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (24))) & (255))) | (((((unsigned int) (value) >> (8))) & (65280))))) | (((((((value) << (8))) & (16711680))) | (((((value) << (24))) & (0xff000000))))))); + fields->f_dsp_32_s32 = value; + } + break; + case M32C_OPERAND_IMM_40_HI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_40_s16 = value; + } + break; + case M32C_OPERAND_IMM_40_QI : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_40_s8); + break; + case M32C_OPERAND_IMM_40_SI : + { + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 8, 24, 32, total_length, pc, & value); + value = ((((((((unsigned int) (value) >> (16))) & (255))) | (((value) & (65280))))) | (((((value) << (16))) & (16711680)))); + fields->f_dsp_40_u24 = value; + } + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 64, 0, 8, 32, total_length, pc, & fields->f_dsp_64_u8); + if (length <= 0) break; +{ + FLD (f_dsp_40_s32) = ((((FLD (f_dsp_40_u24)) & (16777215))) | (((((FLD (f_dsp_64_u8)) << (24))) & (0xff000000)))); +} + } + break; + case M32C_OPERAND_IMM_48_HI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_48_s16 = value; + } + break; + case M32C_OPERAND_IMM_48_QI : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_48_s8); + break; + case M32C_OPERAND_IMM_48_SI : + { + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 32, 16, 16, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_48_u16 = value; + } + if (length <= 0) break; + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 64, 0, 16, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (8))) & (255))) | (((((value) << (8))) & (65280)))); + fields->f_dsp_64_u16 = value; + } + if (length <= 0) break; +{ + FLD (f_dsp_48_s32) = ((((FLD (f_dsp_48_u16)) & (65535))) | (((((FLD (f_dsp_64_u16)) << (16))) & (0xffff0000)))); +} + } + break; + case M32C_OPERAND_IMM_56_HI : + { + length = extract_normal (cd, ex_info, insn_value, 0, 32, 24, 8, 32, total_length, pc, & fields->f_dsp_56_u8); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 64, 0, 8, 32, total_length, pc, & fields->f_dsp_64_u8); + if (length <= 0) break; +{ + FLD (f_dsp_56_s16) = EXTHISI (((HI) (UINT) (((((FLD (f_dsp_64_u8)) << (8))) | (FLD (f_dsp_56_u8)))))); +} + } + break; + case M32C_OPERAND_IMM_56_QI : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_56_s8); + break; + case M32C_OPERAND_IMM_64_HI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_64_s16 = value; + } + break; + case M32C_OPERAND_IMM_8_HI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) & (255))) | (((((value) << (8))) & (65280))))))); + fields->f_dsp_8_s16 = value; + } + break; + case M32C_OPERAND_IMM_8_QI : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_dsp_8_s8); + break; + case M32C_OPERAND_IMM_8_S4 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm_8_s4); + break; + case M32C_OPERAND_IMM_SH_12_S4 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm_12_s4); + break; + case M32C_OPERAND_IMM_SH_20_S4 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm_20_s4); + break; + case M32C_OPERAND_IMM_SH_8_S4 : + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_imm_8_s4); + break; + case M32C_OPERAND_IMM1_S : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 1, 32, total_length, pc, & value); + value = ((value) + (1)); + fields->f_imm1_S = value; + } + break; + case M32C_OPERAND_IMM3_S : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 2, 32, total_length, pc, & fields->f_2_2); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 1, 32, total_length, pc, & fields->f_7_1); + if (length <= 0) break; +{ + FLD (f_imm3_S) = ((((((FLD (f_2_2)) << (1))) | (FLD (f_7_1)))) + (1)); +} + } + break; + case M32C_OPERAND_LAB_16_8 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_lab_16_8 = value; + } + break; + case M32C_OPERAND_LAB_24_8 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_lab_24_8 = value; + } + break; + case M32C_OPERAND_LAB_32_8 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_lab_32_8 = value; + } + break; + case M32C_OPERAND_LAB_40_8 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_lab_40_8 = value; + } + break; + case M32C_OPERAND_LAB_5_3 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_lab_5_3 = value; + } + break; + case M32C_OPERAND_LAB_8_16 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (8))) | (((int) (((((value) & (255))) << (24))) >> (16))))) + (((pc) + (1)))); + fields->f_lab_8_16 = value; + } + break; + case M32C_OPERAND_LAB_8_24 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (16))) | (((value) & (65280))))) | (((((value) & (255))) << (16)))); + fields->f_lab_8_24 = value; + } + break; + case M32C_OPERAND_LAB_8_8 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_lab_8_8 = value; + } + break; + case M32C_OPERAND_LAB32_JMP_S : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 2, 32, total_length, pc, & fields->f_2_2); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 1, 32, total_length, pc, & fields->f_7_1); + if (length <= 0) break; +{ + FLD (f_lab32_jmp_s) = ((pc) + (((((((FLD (f_2_2)) << (1))) | (FLD (f_7_1)))) + (2)))); +} + } + break; + case M32C_OPERAND_Q : + break; + case M32C_OPERAND_R0 : + break; + case M32C_OPERAND_R0H : + break; + case M32C_OPERAND_R0L : + break; + case M32C_OPERAND_R1 : + break; + case M32C_OPERAND_R1R2R0 : + break; + case M32C_OPERAND_R2 : + break; + case M32C_OPERAND_R2R0 : + break; + case M32C_OPERAND_R3 : + break; + case M32C_OPERAND_R3R1 : + break; + case M32C_OPERAND_REGSETPOP : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_8_8); + break; + case M32C_OPERAND_REGSETPUSH : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_8_8); + break; + case M32C_OPERAND_RN16_PUSH_S : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 1, 32, total_length, pc, & fields->f_4_1); + break; + case M32C_OPERAND_S : + break; + case M32C_OPERAND_SRC16AN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_src16_an); + break; + case M32C_OPERAND_SRC16ANHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_src16_an); + break; + case M32C_OPERAND_SRC16ANQI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_src16_an); + break; + case M32C_OPERAND_SRC16RNHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 2, 32, total_length, pc, & fields->f_src16_rn); + break; + case M32C_OPERAND_SRC16RNQI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 2, 32, total_length, pc, & fields->f_src16_rn); + break; + case M32C_OPERAND_SRC32ANPREFIXED : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 1, 32, total_length, pc, & fields->f_src32_an_prefixed); + break; + case M32C_OPERAND_SRC32ANPREFIXEDHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 1, 32, total_length, pc, & fields->f_src32_an_prefixed); + break; + case M32C_OPERAND_SRC32ANPREFIXEDQI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 1, 32, total_length, pc, & fields->f_src32_an_prefixed); + break; + case M32C_OPERAND_SRC32ANPREFIXEDSI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 19, 1, 32, total_length, pc, & fields->f_src32_an_prefixed); + break; + case M32C_OPERAND_SRC32ANUNPREFIXED : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_src32_an_unprefixed); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDHI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_src32_an_unprefixed); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDQI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_src32_an_unprefixed); + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDSI : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_src32_an_unprefixed); + break; + case M32C_OPERAND_SRC32RNPREFIXEDHI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 18, 2, 32, total_length, pc, & value); + value = ((((value) + (2))) % (4)); + fields->f_src32_rn_prefixed_HI = value; + } + break; + case M32C_OPERAND_SRC32RNPREFIXEDQI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 18, 2, 32, total_length, pc, & value); + value = (((((~ (((unsigned int) (value) >> (1))))) & (1))) | (((((value) << (1))) & (2)))); + fields->f_src32_rn_prefixed_QI = value; + } + break; + case M32C_OPERAND_SRC32RNPREFIXEDSI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 18, 2, 32, total_length, pc, & value); + value = ((value) - (2)); + fields->f_src32_rn_prefixed_SI = value; + } + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDHI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 2, 32, total_length, pc, & value); + value = ((((value) + (2))) % (4)); + fields->f_src32_rn_unprefixed_HI = value; + } + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDQI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 2, 32, total_length, pc, & value); + value = (((((~ (((unsigned int) (value) >> (1))))) & (1))) | (((((value) << (1))) & (2)))); + fields->f_src32_rn_unprefixed_QI = value; + } + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDSI : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 2, 32, total_length, pc, & value); + value = ((value) - (2)); + fields->f_src32_rn_unprefixed_SI = value; + } + break; + case M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 1, 32, total_length, pc, & fields->f_5_1); + break; + case M32C_OPERAND_X : + break; + case M32C_OPERAND_Z : + break; + case M32C_OPERAND_COND16_16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 8, 32, total_length, pc, & fields->f_dsp_16_u8); + break; + case M32C_OPERAND_COND16_24 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + break; + case M32C_OPERAND_COND16_32 : + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_u8); + break; + case M32C_OPERAND_COND16C : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_cond16); + break; + case M32C_OPERAND_COND16J : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_cond16); + break; + case M32C_OPERAND_COND16J5 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_cond16j_5); + break; + case M32C_OPERAND_COND32 : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_9_1); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_13_3); + if (length <= 0) break; +{ + FLD (f_cond32) = ((((FLD (f_9_1)) << (3))) | (FLD (f_13_3))); +} + } + break; + case M32C_OPERAND_COND32_16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 8, 32, total_length, pc, & fields->f_dsp_16_u8); + break; + case M32C_OPERAND_COND32_24 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 8, 32, total_length, pc, & fields->f_dsp_24_u8); + break; + case M32C_OPERAND_COND32_32 : + length = extract_normal (cd, ex_info, insn_value, 0, 32, 0, 8, 32, total_length, pc, & fields->f_dsp_32_u8); + break; + case M32C_OPERAND_COND32_40 : + length = extract_normal (cd, ex_info, insn_value, 0, 32, 8, 8, 32, total_length, pc, & fields->f_dsp_40_u8); + break; + case M32C_OPERAND_COND32J : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 1, 3, 32, total_length, pc, & fields->f_1_3); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 1, 32, total_length, pc, & fields->f_7_1); + if (length <= 0) break; +{ + FLD (f_cond32j) = ((((FLD (f_1_3)) << (1))) | (FLD (f_7_1))); +} + } + break; + case M32C_OPERAND_CR1_PREFIXED_32 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 3, 32, total_length, pc, & fields->f_21_3); + break; + case M32C_OPERAND_CR1_UNPREFIXED_32 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_13_3); + break; + case M32C_OPERAND_CR16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_9_3); + break; + case M32C_OPERAND_CR2_32 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_13_3); + break; + case M32C_OPERAND_CR3_PREFIXED_32 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 21, 3, 32, total_length, pc, & fields->f_21_3); + break; + case M32C_OPERAND_CR3_UNPREFIXED_32 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_13_3); + break; + case M32C_OPERAND_FLAGS16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 3, 32, total_length, pc, & fields->f_9_3); + break; + case M32C_OPERAND_FLAGS32 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_13_3); + break; + case M32C_OPERAND_SCCOND32 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_cond16); + break; + case M32C_OPERAND_SIZE : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const m32c_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const m32c_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int m32c_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma m32c_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +m32c_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + int value; + + switch (opindex) + { + case M32C_OPERAND_A0 : + value = 0; + break; + case M32C_OPERAND_A1 : + value = 0; + break; + case M32C_OPERAND_AN16_PUSH_S : + value = fields->f_4_1; + break; + case M32C_OPERAND_BIT16AN : + value = fields->f_dst16_an; + break; + case M32C_OPERAND_BIT16RN : + value = fields->f_dst16_rn; + break; + case M32C_OPERAND_BIT32ANPREFIXED : + value = fields->f_dst32_an_prefixed; + break; + case M32C_OPERAND_BIT32ANUNPREFIXED : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_BIT32RNPREFIXED : + value = fields->f_dst32_rn_prefixed_QI; + break; + case M32C_OPERAND_BIT32RNUNPREFIXED : + value = fields->f_dst32_rn_unprefixed_QI; + break; + case M32C_OPERAND_BITBASE16_16_S8 : + value = fields->f_dsp_16_s8; + break; + case M32C_OPERAND_BITBASE16_16_U16 : + value = fields->f_dsp_16_u16; + break; + case M32C_OPERAND_BITBASE16_16_U8 : + value = fields->f_dsp_16_u8; + break; + case M32C_OPERAND_BITBASE16_8_U11_S : + value = fields->f_bitbase16_u11_S; + break; + case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED : + value = fields->f_bitbase32_16_s11_unprefixed; + break; + case M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED : + value = fields->f_bitbase32_16_s19_unprefixed; + break; + case M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED : + value = fields->f_bitbase32_16_u11_unprefixed; + break; + case M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED : + value = fields->f_bitbase32_16_u19_unprefixed; + break; + case M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED : + value = fields->f_bitbase32_16_u27_unprefixed; + break; + case M32C_OPERAND_BITBASE32_24_S11_PREFIXED : + value = fields->f_bitbase32_24_s11_prefixed; + break; + case M32C_OPERAND_BITBASE32_24_S19_PREFIXED : + value = fields->f_bitbase32_24_s19_prefixed; + break; + case M32C_OPERAND_BITBASE32_24_U11_PREFIXED : + value = fields->f_bitbase32_24_u11_prefixed; + break; + case M32C_OPERAND_BITBASE32_24_U19_PREFIXED : + value = fields->f_bitbase32_24_u19_prefixed; + break; + case M32C_OPERAND_BITBASE32_24_U27_PREFIXED : + value = fields->f_bitbase32_24_u27_prefixed; + break; + case M32C_OPERAND_BITNO16R : + value = fields->f_dsp_16_u8; + break; + case M32C_OPERAND_BITNO32PREFIXED : + value = fields->f_bitno32_prefixed; + break; + case M32C_OPERAND_BITNO32UNPREFIXED : + value = fields->f_bitno32_unprefixed; + break; + case M32C_OPERAND_DSP_10_U6 : + value = fields->f_dsp_10_u6; + break; + case M32C_OPERAND_DSP_16_S16 : + value = fields->f_dsp_16_s16; + break; + case M32C_OPERAND_DSP_16_S8 : + value = fields->f_dsp_16_s8; + break; + case M32C_OPERAND_DSP_16_U16 : + value = fields->f_dsp_16_u16; + break; + case M32C_OPERAND_DSP_16_U20 : + value = fields->f_dsp_16_u24; + break; + case M32C_OPERAND_DSP_16_U24 : + value = fields->f_dsp_16_u24; + break; + case M32C_OPERAND_DSP_16_U8 : + value = fields->f_dsp_16_u8; + break; + case M32C_OPERAND_DSP_24_S16 : + value = fields->f_dsp_24_s16; + break; + case M32C_OPERAND_DSP_24_S8 : + value = fields->f_dsp_24_s8; + break; + case M32C_OPERAND_DSP_24_U16 : + value = fields->f_dsp_24_u16; + break; + case M32C_OPERAND_DSP_24_U20 : + value = fields->f_dsp_24_u24; + break; + case M32C_OPERAND_DSP_24_U24 : + value = fields->f_dsp_24_u24; + break; + case M32C_OPERAND_DSP_24_U8 : + value = fields->f_dsp_24_u8; + break; + case M32C_OPERAND_DSP_32_S16 : + value = fields->f_dsp_32_s16; + break; + case M32C_OPERAND_DSP_32_S8 : + value = fields->f_dsp_32_s8; + break; + case M32C_OPERAND_DSP_32_U16 : + value = fields->f_dsp_32_u16; + break; + case M32C_OPERAND_DSP_32_U20 : + value = fields->f_dsp_32_u24; + break; + case M32C_OPERAND_DSP_32_U24 : + value = fields->f_dsp_32_u24; + break; + case M32C_OPERAND_DSP_32_U8 : + value = fields->f_dsp_32_u8; + break; + case M32C_OPERAND_DSP_40_S16 : + value = fields->f_dsp_40_s16; + break; + case M32C_OPERAND_DSP_40_S8 : + value = fields->f_dsp_40_s8; + break; + case M32C_OPERAND_DSP_40_U16 : + value = fields->f_dsp_40_u16; + break; + case M32C_OPERAND_DSP_40_U24 : + value = fields->f_dsp_40_u24; + break; + case M32C_OPERAND_DSP_40_U8 : + value = fields->f_dsp_40_u8; + break; + case M32C_OPERAND_DSP_48_S16 : + value = fields->f_dsp_48_s16; + break; + case M32C_OPERAND_DSP_48_S8 : + value = fields->f_dsp_48_s8; + break; + case M32C_OPERAND_DSP_48_U16 : + value = fields->f_dsp_48_u16; + break; + case M32C_OPERAND_DSP_48_U24 : + value = fields->f_dsp_48_u24; + break; + case M32C_OPERAND_DSP_48_U8 : + value = fields->f_dsp_48_u8; + break; + case M32C_OPERAND_DSP_8_S8 : + value = fields->f_dsp_8_s8; + break; + case M32C_OPERAND_DSP_8_U16 : + value = fields->f_dsp_8_u16; + break; + case M32C_OPERAND_DSP_8_U24 : + value = fields->f_dsp_8_u24; + break; + case M32C_OPERAND_DSP_8_U6 : + value = fields->f_dsp_8_u6; + break; + case M32C_OPERAND_DSP_8_U8 : + value = fields->f_dsp_8_u8; + break; + case M32C_OPERAND_DST16AN : + value = fields->f_dst16_an; + break; + case M32C_OPERAND_DST16AN_S : + value = fields->f_dst16_an_s; + break; + case M32C_OPERAND_DST16ANHI : + value = fields->f_dst16_an; + break; + case M32C_OPERAND_DST16ANQI : + value = fields->f_dst16_an; + break; + case M32C_OPERAND_DST16ANQI_S : + value = fields->f_dst16_rn_QI_s; + break; + case M32C_OPERAND_DST16ANSI : + value = fields->f_dst16_an; + break; + case M32C_OPERAND_DST16RNEXTQI : + value = fields->f_dst16_rn_ext; + break; + case M32C_OPERAND_DST16RNHI : + value = fields->f_dst16_rn; + break; + case M32C_OPERAND_DST16RNQI : + value = fields->f_dst16_rn; + break; + case M32C_OPERAND_DST16RNQI_S : + value = fields->f_dst16_rn_QI_s; + break; + case M32C_OPERAND_DST16RNSI : + value = fields->f_dst16_rn; + break; + case M32C_OPERAND_DST32ANEXTUNPREFIXED : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_DST32ANPREFIXED : + value = fields->f_dst32_an_prefixed; + break; + case M32C_OPERAND_DST32ANPREFIXEDHI : + value = fields->f_dst32_an_prefixed; + break; + case M32C_OPERAND_DST32ANPREFIXEDQI : + value = fields->f_dst32_an_prefixed; + break; + case M32C_OPERAND_DST32ANPREFIXEDSI : + value = fields->f_dst32_an_prefixed; + break; + case M32C_OPERAND_DST32ANUNPREFIXED : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDHI : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDQI : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDSI : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_DST32R0HI_S : + value = 0; + break; + case M32C_OPERAND_DST32R0QI_S : + value = 0; + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDHI : + value = fields->f_dst32_rn_ext_unprefixed; + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDQI : + value = fields->f_dst32_rn_ext_unprefixed; + break; + case M32C_OPERAND_DST32RNPREFIXEDHI : + value = fields->f_dst32_rn_prefixed_HI; + break; + case M32C_OPERAND_DST32RNPREFIXEDQI : + value = fields->f_dst32_rn_prefixed_QI; + break; + case M32C_OPERAND_DST32RNPREFIXEDSI : + value = fields->f_dst32_rn_prefixed_SI; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDHI : + value = fields->f_dst32_rn_unprefixed_HI; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDQI : + value = fields->f_dst32_rn_unprefixed_QI; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDSI : + value = fields->f_dst32_rn_unprefixed_SI; + break; + case M32C_OPERAND_G : + value = 0; + break; + case M32C_OPERAND_IMM_12_S4 : + value = fields->f_imm_12_s4; + break; + case M32C_OPERAND_IMM_13_U3 : + value = fields->f_imm_13_u3; + break; + case M32C_OPERAND_IMM_16_HI : + value = fields->f_dsp_16_s16; + break; + case M32C_OPERAND_IMM_16_QI : + value = fields->f_dsp_16_s8; + break; + case M32C_OPERAND_IMM_16_SI : + value = fields->f_dsp_16_s32; + break; + case M32C_OPERAND_IMM_20_S4 : + value = fields->f_imm_20_s4; + break; + case M32C_OPERAND_IMM_24_HI : + value = fields->f_dsp_24_s16; + break; + case M32C_OPERAND_IMM_24_QI : + value = fields->f_dsp_24_s8; + break; + case M32C_OPERAND_IMM_24_SI : + value = fields->f_dsp_24_s32; + break; + case M32C_OPERAND_IMM_32_HI : + value = fields->f_dsp_32_s16; + break; + case M32C_OPERAND_IMM_32_QI : + value = fields->f_dsp_32_s8; + break; + case M32C_OPERAND_IMM_32_SI : + value = fields->f_dsp_32_s32; + break; + case M32C_OPERAND_IMM_40_HI : + value = fields->f_dsp_40_s16; + break; + case M32C_OPERAND_IMM_40_QI : + value = fields->f_dsp_40_s8; + break; + case M32C_OPERAND_IMM_40_SI : + value = fields->f_dsp_40_s32; + break; + case M32C_OPERAND_IMM_48_HI : + value = fields->f_dsp_48_s16; + break; + case M32C_OPERAND_IMM_48_QI : + value = fields->f_dsp_48_s8; + break; + case M32C_OPERAND_IMM_48_SI : + value = fields->f_dsp_48_s32; + break; + case M32C_OPERAND_IMM_56_HI : + value = fields->f_dsp_56_s16; + break; + case M32C_OPERAND_IMM_56_QI : + value = fields->f_dsp_56_s8; + break; + case M32C_OPERAND_IMM_64_HI : + value = fields->f_dsp_64_s16; + break; + case M32C_OPERAND_IMM_8_HI : + value = fields->f_dsp_8_s16; + break; + case M32C_OPERAND_IMM_8_QI : + value = fields->f_dsp_8_s8; + break; + case M32C_OPERAND_IMM_8_S4 : + value = fields->f_imm_8_s4; + break; + case M32C_OPERAND_IMM_SH_12_S4 : + value = fields->f_imm_12_s4; + break; + case M32C_OPERAND_IMM_SH_20_S4 : + value = fields->f_imm_20_s4; + break; + case M32C_OPERAND_IMM_SH_8_S4 : + value = fields->f_imm_8_s4; + break; + case M32C_OPERAND_IMM1_S : + value = fields->f_imm1_S; + break; + case M32C_OPERAND_IMM3_S : + value = fields->f_imm3_S; + break; + case M32C_OPERAND_LAB_16_8 : + value = fields->f_lab_16_8; + break; + case M32C_OPERAND_LAB_24_8 : + value = fields->f_lab_24_8; + break; + case M32C_OPERAND_LAB_32_8 : + value = fields->f_lab_32_8; + break; + case M32C_OPERAND_LAB_40_8 : + value = fields->f_lab_40_8; + break; + case M32C_OPERAND_LAB_5_3 : + value = fields->f_lab_5_3; + break; + case M32C_OPERAND_LAB_8_16 : + value = fields->f_lab_8_16; + break; + case M32C_OPERAND_LAB_8_24 : + value = fields->f_lab_8_24; + break; + case M32C_OPERAND_LAB_8_8 : + value = fields->f_lab_8_8; + break; + case M32C_OPERAND_LAB32_JMP_S : + value = fields->f_lab32_jmp_s; + break; + case M32C_OPERAND_Q : + value = 0; + break; + case M32C_OPERAND_R0 : + value = 0; + break; + case M32C_OPERAND_R0H : + value = 0; + break; + case M32C_OPERAND_R0L : + value = 0; + break; + case M32C_OPERAND_R1 : + value = 0; + break; + case M32C_OPERAND_R1R2R0 : + value = 0; + break; + case M32C_OPERAND_R2 : + value = 0; + break; + case M32C_OPERAND_R2R0 : + value = 0; + break; + case M32C_OPERAND_R3 : + value = 0; + break; + case M32C_OPERAND_R3R1 : + value = 0; + break; + case M32C_OPERAND_REGSETPOP : + value = fields->f_8_8; + break; + case M32C_OPERAND_REGSETPUSH : + value = fields->f_8_8; + break; + case M32C_OPERAND_RN16_PUSH_S : + value = fields->f_4_1; + break; + case M32C_OPERAND_S : + value = 0; + break; + case M32C_OPERAND_SRC16AN : + value = fields->f_src16_an; + break; + case M32C_OPERAND_SRC16ANHI : + value = fields->f_src16_an; + break; + case M32C_OPERAND_SRC16ANQI : + value = fields->f_src16_an; + break; + case M32C_OPERAND_SRC16RNHI : + value = fields->f_src16_rn; + break; + case M32C_OPERAND_SRC16RNQI : + value = fields->f_src16_rn; + break; + case M32C_OPERAND_SRC32ANPREFIXED : + value = fields->f_src32_an_prefixed; + break; + case M32C_OPERAND_SRC32ANPREFIXEDHI : + value = fields->f_src32_an_prefixed; + break; + case M32C_OPERAND_SRC32ANPREFIXEDQI : + value = fields->f_src32_an_prefixed; + break; + case M32C_OPERAND_SRC32ANPREFIXEDSI : + value = fields->f_src32_an_prefixed; + break; + case M32C_OPERAND_SRC32ANUNPREFIXED : + value = fields->f_src32_an_unprefixed; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDHI : + value = fields->f_src32_an_unprefixed; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDQI : + value = fields->f_src32_an_unprefixed; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDSI : + value = fields->f_src32_an_unprefixed; + break; + case M32C_OPERAND_SRC32RNPREFIXEDHI : + value = fields->f_src32_rn_prefixed_HI; + break; + case M32C_OPERAND_SRC32RNPREFIXEDQI : + value = fields->f_src32_rn_prefixed_QI; + break; + case M32C_OPERAND_SRC32RNPREFIXEDSI : + value = fields->f_src32_rn_prefixed_SI; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDHI : + value = fields->f_src32_rn_unprefixed_HI; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDQI : + value = fields->f_src32_rn_unprefixed_QI; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDSI : + value = fields->f_src32_rn_unprefixed_SI; + break; + case M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL : + value = fields->f_5_1; + break; + case M32C_OPERAND_X : + value = 0; + break; + case M32C_OPERAND_Z : + value = 0; + break; + case M32C_OPERAND_COND16_16 : + value = fields->f_dsp_16_u8; + break; + case M32C_OPERAND_COND16_24 : + value = fields->f_dsp_24_u8; + break; + case M32C_OPERAND_COND16_32 : + value = fields->f_dsp_32_u8; + break; + case M32C_OPERAND_COND16C : + value = fields->f_cond16; + break; + case M32C_OPERAND_COND16J : + value = fields->f_cond16; + break; + case M32C_OPERAND_COND16J5 : + value = fields->f_cond16j_5; + break; + case M32C_OPERAND_COND32 : + value = fields->f_cond32; + break; + case M32C_OPERAND_COND32_16 : + value = fields->f_dsp_16_u8; + break; + case M32C_OPERAND_COND32_24 : + value = fields->f_dsp_24_u8; + break; + case M32C_OPERAND_COND32_32 : + value = fields->f_dsp_32_u8; + break; + case M32C_OPERAND_COND32_40 : + value = fields->f_dsp_40_u8; + break; + case M32C_OPERAND_COND32J : + value = fields->f_cond32j; + break; + case M32C_OPERAND_CR1_PREFIXED_32 : + value = fields->f_21_3; + break; + case M32C_OPERAND_CR1_UNPREFIXED_32 : + value = fields->f_13_3; + break; + case M32C_OPERAND_CR16 : + value = fields->f_9_3; + break; + case M32C_OPERAND_CR2_32 : + value = fields->f_13_3; + break; + case M32C_OPERAND_CR3_PREFIXED_32 : + value = fields->f_21_3; + break; + case M32C_OPERAND_CR3_UNPREFIXED_32 : + value = fields->f_13_3; + break; + case M32C_OPERAND_FLAGS16 : + value = fields->f_9_3; + break; + case M32C_OPERAND_FLAGS32 : + value = fields->f_13_3; + break; + case M32C_OPERAND_SCCOND32 : + value = fields->f_cond16; + break; + case M32C_OPERAND_SIZE : + value = 0; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +m32c_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) +{ + bfd_vma value; + + switch (opindex) + { + case M32C_OPERAND_A0 : + value = 0; + break; + case M32C_OPERAND_A1 : + value = 0; + break; + case M32C_OPERAND_AN16_PUSH_S : + value = fields->f_4_1; + break; + case M32C_OPERAND_BIT16AN : + value = fields->f_dst16_an; + break; + case M32C_OPERAND_BIT16RN : + value = fields->f_dst16_rn; + break; + case M32C_OPERAND_BIT32ANPREFIXED : + value = fields->f_dst32_an_prefixed; + break; + case M32C_OPERAND_BIT32ANUNPREFIXED : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_BIT32RNPREFIXED : + value = fields->f_dst32_rn_prefixed_QI; + break; + case M32C_OPERAND_BIT32RNUNPREFIXED : + value = fields->f_dst32_rn_unprefixed_QI; + break; + case M32C_OPERAND_BITBASE16_16_S8 : + value = fields->f_dsp_16_s8; + break; + case M32C_OPERAND_BITBASE16_16_U16 : + value = fields->f_dsp_16_u16; + break; + case M32C_OPERAND_BITBASE16_16_U8 : + value = fields->f_dsp_16_u8; + break; + case M32C_OPERAND_BITBASE16_8_U11_S : + value = fields->f_bitbase16_u11_S; + break; + case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED : + value = fields->f_bitbase32_16_s11_unprefixed; + break; + case M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED : + value = fields->f_bitbase32_16_s19_unprefixed; + break; + case M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED : + value = fields->f_bitbase32_16_u11_unprefixed; + break; + case M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED : + value = fields->f_bitbase32_16_u19_unprefixed; + break; + case M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED : + value = fields->f_bitbase32_16_u27_unprefixed; + break; + case M32C_OPERAND_BITBASE32_24_S11_PREFIXED : + value = fields->f_bitbase32_24_s11_prefixed; + break; + case M32C_OPERAND_BITBASE32_24_S19_PREFIXED : + value = fields->f_bitbase32_24_s19_prefixed; + break; + case M32C_OPERAND_BITBASE32_24_U11_PREFIXED : + value = fields->f_bitbase32_24_u11_prefixed; + break; + case M32C_OPERAND_BITBASE32_24_U19_PREFIXED : + value = fields->f_bitbase32_24_u19_prefixed; + break; + case M32C_OPERAND_BITBASE32_24_U27_PREFIXED : + value = fields->f_bitbase32_24_u27_prefixed; + break; + case M32C_OPERAND_BITNO16R : + value = fields->f_dsp_16_u8; + break; + case M32C_OPERAND_BITNO32PREFIXED : + value = fields->f_bitno32_prefixed; + break; + case M32C_OPERAND_BITNO32UNPREFIXED : + value = fields->f_bitno32_unprefixed; + break; + case M32C_OPERAND_DSP_10_U6 : + value = fields->f_dsp_10_u6; + break; + case M32C_OPERAND_DSP_16_S16 : + value = fields->f_dsp_16_s16; + break; + case M32C_OPERAND_DSP_16_S8 : + value = fields->f_dsp_16_s8; + break; + case M32C_OPERAND_DSP_16_U16 : + value = fields->f_dsp_16_u16; + break; + case M32C_OPERAND_DSP_16_U20 : + value = fields->f_dsp_16_u24; + break; + case M32C_OPERAND_DSP_16_U24 : + value = fields->f_dsp_16_u24; + break; + case M32C_OPERAND_DSP_16_U8 : + value = fields->f_dsp_16_u8; + break; + case M32C_OPERAND_DSP_24_S16 : + value = fields->f_dsp_24_s16; + break; + case M32C_OPERAND_DSP_24_S8 : + value = fields->f_dsp_24_s8; + break; + case M32C_OPERAND_DSP_24_U16 : + value = fields->f_dsp_24_u16; + break; + case M32C_OPERAND_DSP_24_U20 : + value = fields->f_dsp_24_u24; + break; + case M32C_OPERAND_DSP_24_U24 : + value = fields->f_dsp_24_u24; + break; + case M32C_OPERAND_DSP_24_U8 : + value = fields->f_dsp_24_u8; + break; + case M32C_OPERAND_DSP_32_S16 : + value = fields->f_dsp_32_s16; + break; + case M32C_OPERAND_DSP_32_S8 : + value = fields->f_dsp_32_s8; + break; + case M32C_OPERAND_DSP_32_U16 : + value = fields->f_dsp_32_u16; + break; + case M32C_OPERAND_DSP_32_U20 : + value = fields->f_dsp_32_u24; + break; + case M32C_OPERAND_DSP_32_U24 : + value = fields->f_dsp_32_u24; + break; + case M32C_OPERAND_DSP_32_U8 : + value = fields->f_dsp_32_u8; + break; + case M32C_OPERAND_DSP_40_S16 : + value = fields->f_dsp_40_s16; + break; + case M32C_OPERAND_DSP_40_S8 : + value = fields->f_dsp_40_s8; + break; + case M32C_OPERAND_DSP_40_U16 : + value = fields->f_dsp_40_u16; + break; + case M32C_OPERAND_DSP_40_U24 : + value = fields->f_dsp_40_u24; + break; + case M32C_OPERAND_DSP_40_U8 : + value = fields->f_dsp_40_u8; + break; + case M32C_OPERAND_DSP_48_S16 : + value = fields->f_dsp_48_s16; + break; + case M32C_OPERAND_DSP_48_S8 : + value = fields->f_dsp_48_s8; + break; + case M32C_OPERAND_DSP_48_U16 : + value = fields->f_dsp_48_u16; + break; + case M32C_OPERAND_DSP_48_U24 : + value = fields->f_dsp_48_u24; + break; + case M32C_OPERAND_DSP_48_U8 : + value = fields->f_dsp_48_u8; + break; + case M32C_OPERAND_DSP_8_S8 : + value = fields->f_dsp_8_s8; + break; + case M32C_OPERAND_DSP_8_U16 : + value = fields->f_dsp_8_u16; + break; + case M32C_OPERAND_DSP_8_U24 : + value = fields->f_dsp_8_u24; + break; + case M32C_OPERAND_DSP_8_U6 : + value = fields->f_dsp_8_u6; + break; + case M32C_OPERAND_DSP_8_U8 : + value = fields->f_dsp_8_u8; + break; + case M32C_OPERAND_DST16AN : + value = fields->f_dst16_an; + break; + case M32C_OPERAND_DST16AN_S : + value = fields->f_dst16_an_s; + break; + case M32C_OPERAND_DST16ANHI : + value = fields->f_dst16_an; + break; + case M32C_OPERAND_DST16ANQI : + value = fields->f_dst16_an; + break; + case M32C_OPERAND_DST16ANQI_S : + value = fields->f_dst16_rn_QI_s; + break; + case M32C_OPERAND_DST16ANSI : + value = fields->f_dst16_an; + break; + case M32C_OPERAND_DST16RNEXTQI : + value = fields->f_dst16_rn_ext; + break; + case M32C_OPERAND_DST16RNHI : + value = fields->f_dst16_rn; + break; + case M32C_OPERAND_DST16RNQI : + value = fields->f_dst16_rn; + break; + case M32C_OPERAND_DST16RNQI_S : + value = fields->f_dst16_rn_QI_s; + break; + case M32C_OPERAND_DST16RNSI : + value = fields->f_dst16_rn; + break; + case M32C_OPERAND_DST32ANEXTUNPREFIXED : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_DST32ANPREFIXED : + value = fields->f_dst32_an_prefixed; + break; + case M32C_OPERAND_DST32ANPREFIXEDHI : + value = fields->f_dst32_an_prefixed; + break; + case M32C_OPERAND_DST32ANPREFIXEDQI : + value = fields->f_dst32_an_prefixed; + break; + case M32C_OPERAND_DST32ANPREFIXEDSI : + value = fields->f_dst32_an_prefixed; + break; + case M32C_OPERAND_DST32ANUNPREFIXED : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDHI : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDQI : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDSI : + value = fields->f_dst32_an_unprefixed; + break; + case M32C_OPERAND_DST32R0HI_S : + value = 0; + break; + case M32C_OPERAND_DST32R0QI_S : + value = 0; + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDHI : + value = fields->f_dst32_rn_ext_unprefixed; + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDQI : + value = fields->f_dst32_rn_ext_unprefixed; + break; + case M32C_OPERAND_DST32RNPREFIXEDHI : + value = fields->f_dst32_rn_prefixed_HI; + break; + case M32C_OPERAND_DST32RNPREFIXEDQI : + value = fields->f_dst32_rn_prefixed_QI; + break; + case M32C_OPERAND_DST32RNPREFIXEDSI : + value = fields->f_dst32_rn_prefixed_SI; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDHI : + value = fields->f_dst32_rn_unprefixed_HI; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDQI : + value = fields->f_dst32_rn_unprefixed_QI; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDSI : + value = fields->f_dst32_rn_unprefixed_SI; + break; + case M32C_OPERAND_G : + value = 0; + break; + case M32C_OPERAND_IMM_12_S4 : + value = fields->f_imm_12_s4; + break; + case M32C_OPERAND_IMM_13_U3 : + value = fields->f_imm_13_u3; + break; + case M32C_OPERAND_IMM_16_HI : + value = fields->f_dsp_16_s16; + break; + case M32C_OPERAND_IMM_16_QI : + value = fields->f_dsp_16_s8; + break; + case M32C_OPERAND_IMM_16_SI : + value = fields->f_dsp_16_s32; + break; + case M32C_OPERAND_IMM_20_S4 : + value = fields->f_imm_20_s4; + break; + case M32C_OPERAND_IMM_24_HI : + value = fields->f_dsp_24_s16; + break; + case M32C_OPERAND_IMM_24_QI : + value = fields->f_dsp_24_s8; + break; + case M32C_OPERAND_IMM_24_SI : + value = fields->f_dsp_24_s32; + break; + case M32C_OPERAND_IMM_32_HI : + value = fields->f_dsp_32_s16; + break; + case M32C_OPERAND_IMM_32_QI : + value = fields->f_dsp_32_s8; + break; + case M32C_OPERAND_IMM_32_SI : + value = fields->f_dsp_32_s32; + break; + case M32C_OPERAND_IMM_40_HI : + value = fields->f_dsp_40_s16; + break; + case M32C_OPERAND_IMM_40_QI : + value = fields->f_dsp_40_s8; + break; + case M32C_OPERAND_IMM_40_SI : + value = fields->f_dsp_40_s32; + break; + case M32C_OPERAND_IMM_48_HI : + value = fields->f_dsp_48_s16; + break; + case M32C_OPERAND_IMM_48_QI : + value = fields->f_dsp_48_s8; + break; + case M32C_OPERAND_IMM_48_SI : + value = fields->f_dsp_48_s32; + break; + case M32C_OPERAND_IMM_56_HI : + value = fields->f_dsp_56_s16; + break; + case M32C_OPERAND_IMM_56_QI : + value = fields->f_dsp_56_s8; + break; + case M32C_OPERAND_IMM_64_HI : + value = fields->f_dsp_64_s16; + break; + case M32C_OPERAND_IMM_8_HI : + value = fields->f_dsp_8_s16; + break; + case M32C_OPERAND_IMM_8_QI : + value = fields->f_dsp_8_s8; + break; + case M32C_OPERAND_IMM_8_S4 : + value = fields->f_imm_8_s4; + break; + case M32C_OPERAND_IMM_SH_12_S4 : + value = fields->f_imm_12_s4; + break; + case M32C_OPERAND_IMM_SH_20_S4 : + value = fields->f_imm_20_s4; + break; + case M32C_OPERAND_IMM_SH_8_S4 : + value = fields->f_imm_8_s4; + break; + case M32C_OPERAND_IMM1_S : + value = fields->f_imm1_S; + break; + case M32C_OPERAND_IMM3_S : + value = fields->f_imm3_S; + break; + case M32C_OPERAND_LAB_16_8 : + value = fields->f_lab_16_8; + break; + case M32C_OPERAND_LAB_24_8 : + value = fields->f_lab_24_8; + break; + case M32C_OPERAND_LAB_32_8 : + value = fields->f_lab_32_8; + break; + case M32C_OPERAND_LAB_40_8 : + value = fields->f_lab_40_8; + break; + case M32C_OPERAND_LAB_5_3 : + value = fields->f_lab_5_3; + break; + case M32C_OPERAND_LAB_8_16 : + value = fields->f_lab_8_16; + break; + case M32C_OPERAND_LAB_8_24 : + value = fields->f_lab_8_24; + break; + case M32C_OPERAND_LAB_8_8 : + value = fields->f_lab_8_8; + break; + case M32C_OPERAND_LAB32_JMP_S : + value = fields->f_lab32_jmp_s; + break; + case M32C_OPERAND_Q : + value = 0; + break; + case M32C_OPERAND_R0 : + value = 0; + break; + case M32C_OPERAND_R0H : + value = 0; + break; + case M32C_OPERAND_R0L : + value = 0; + break; + case M32C_OPERAND_R1 : + value = 0; + break; + case M32C_OPERAND_R1R2R0 : + value = 0; + break; + case M32C_OPERAND_R2 : + value = 0; + break; + case M32C_OPERAND_R2R0 : + value = 0; + break; + case M32C_OPERAND_R3 : + value = 0; + break; + case M32C_OPERAND_R3R1 : + value = 0; + break; + case M32C_OPERAND_REGSETPOP : + value = fields->f_8_8; + break; + case M32C_OPERAND_REGSETPUSH : + value = fields->f_8_8; + break; + case M32C_OPERAND_RN16_PUSH_S : + value = fields->f_4_1; + break; + case M32C_OPERAND_S : + value = 0; + break; + case M32C_OPERAND_SRC16AN : + value = fields->f_src16_an; + break; + case M32C_OPERAND_SRC16ANHI : + value = fields->f_src16_an; + break; + case M32C_OPERAND_SRC16ANQI : + value = fields->f_src16_an; + break; + case M32C_OPERAND_SRC16RNHI : + value = fields->f_src16_rn; + break; + case M32C_OPERAND_SRC16RNQI : + value = fields->f_src16_rn; + break; + case M32C_OPERAND_SRC32ANPREFIXED : + value = fields->f_src32_an_prefixed; + break; + case M32C_OPERAND_SRC32ANPREFIXEDHI : + value = fields->f_src32_an_prefixed; + break; + case M32C_OPERAND_SRC32ANPREFIXEDQI : + value = fields->f_src32_an_prefixed; + break; + case M32C_OPERAND_SRC32ANPREFIXEDSI : + value = fields->f_src32_an_prefixed; + break; + case M32C_OPERAND_SRC32ANUNPREFIXED : + value = fields->f_src32_an_unprefixed; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDHI : + value = fields->f_src32_an_unprefixed; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDQI : + value = fields->f_src32_an_unprefixed; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDSI : + value = fields->f_src32_an_unprefixed; + break; + case M32C_OPERAND_SRC32RNPREFIXEDHI : + value = fields->f_src32_rn_prefixed_HI; + break; + case M32C_OPERAND_SRC32RNPREFIXEDQI : + value = fields->f_src32_rn_prefixed_QI; + break; + case M32C_OPERAND_SRC32RNPREFIXEDSI : + value = fields->f_src32_rn_prefixed_SI; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDHI : + value = fields->f_src32_rn_unprefixed_HI; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDQI : + value = fields->f_src32_rn_unprefixed_QI; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDSI : + value = fields->f_src32_rn_unprefixed_SI; + break; + case M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL : + value = fields->f_5_1; + break; + case M32C_OPERAND_X : + value = 0; + break; + case M32C_OPERAND_Z : + value = 0; + break; + case M32C_OPERAND_COND16_16 : + value = fields->f_dsp_16_u8; + break; + case M32C_OPERAND_COND16_24 : + value = fields->f_dsp_24_u8; + break; + case M32C_OPERAND_COND16_32 : + value = fields->f_dsp_32_u8; + break; + case M32C_OPERAND_COND16C : + value = fields->f_cond16; + break; + case M32C_OPERAND_COND16J : + value = fields->f_cond16; + break; + case M32C_OPERAND_COND16J5 : + value = fields->f_cond16j_5; + break; + case M32C_OPERAND_COND32 : + value = fields->f_cond32; + break; + case M32C_OPERAND_COND32_16 : + value = fields->f_dsp_16_u8; + break; + case M32C_OPERAND_COND32_24 : + value = fields->f_dsp_24_u8; + break; + case M32C_OPERAND_COND32_32 : + value = fields->f_dsp_32_u8; + break; + case M32C_OPERAND_COND32_40 : + value = fields->f_dsp_40_u8; + break; + case M32C_OPERAND_COND32J : + value = fields->f_cond32j; + break; + case M32C_OPERAND_CR1_PREFIXED_32 : + value = fields->f_21_3; + break; + case M32C_OPERAND_CR1_UNPREFIXED_32 : + value = fields->f_13_3; + break; + case M32C_OPERAND_CR16 : + value = fields->f_9_3; + break; + case M32C_OPERAND_CR2_32 : + value = fields->f_13_3; + break; + case M32C_OPERAND_CR3_PREFIXED_32 : + value = fields->f_21_3; + break; + case M32C_OPERAND_CR3_UNPREFIXED_32 : + value = fields->f_13_3; + break; + case M32C_OPERAND_FLAGS16 : + value = fields->f_9_3; + break; + case M32C_OPERAND_FLAGS32 : + value = fields->f_13_3; + break; + case M32C_OPERAND_SCCOND32 : + value = fields->f_cond16; + break; + case M32C_OPERAND_SIZE : + value = 0; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void m32c_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void m32c_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +m32c_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) +{ + switch (opindex) + { + case M32C_OPERAND_A0 : + break; + case M32C_OPERAND_A1 : + break; + case M32C_OPERAND_AN16_PUSH_S : + fields->f_4_1 = value; + break; + case M32C_OPERAND_BIT16AN : + fields->f_dst16_an = value; + break; + case M32C_OPERAND_BIT16RN : + fields->f_dst16_rn = value; + break; + case M32C_OPERAND_BIT32ANPREFIXED : + fields->f_dst32_an_prefixed = value; + break; + case M32C_OPERAND_BIT32ANUNPREFIXED : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_BIT32RNPREFIXED : + fields->f_dst32_rn_prefixed_QI = value; + break; + case M32C_OPERAND_BIT32RNUNPREFIXED : + fields->f_dst32_rn_unprefixed_QI = value; + break; + case M32C_OPERAND_BITBASE16_16_S8 : + fields->f_dsp_16_s8 = value; + break; + case M32C_OPERAND_BITBASE16_16_U16 : + fields->f_dsp_16_u16 = value; + break; + case M32C_OPERAND_BITBASE16_16_U8 : + fields->f_dsp_16_u8 = value; + break; + case M32C_OPERAND_BITBASE16_8_U11_S : + fields->f_bitbase16_u11_S = value; + break; + case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED : + fields->f_bitbase32_16_s11_unprefixed = value; + break; + case M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED : + fields->f_bitbase32_16_s19_unprefixed = value; + break; + case M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED : + fields->f_bitbase32_16_u11_unprefixed = value; + break; + case M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED : + fields->f_bitbase32_16_u19_unprefixed = value; + break; + case M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED : + fields->f_bitbase32_16_u27_unprefixed = value; + break; + case M32C_OPERAND_BITBASE32_24_S11_PREFIXED : + fields->f_bitbase32_24_s11_prefixed = value; + break; + case M32C_OPERAND_BITBASE32_24_S19_PREFIXED : + fields->f_bitbase32_24_s19_prefixed = value; + break; + case M32C_OPERAND_BITBASE32_24_U11_PREFIXED : + fields->f_bitbase32_24_u11_prefixed = value; + break; + case M32C_OPERAND_BITBASE32_24_U19_PREFIXED : + fields->f_bitbase32_24_u19_prefixed = value; + break; + case M32C_OPERAND_BITBASE32_24_U27_PREFIXED : + fields->f_bitbase32_24_u27_prefixed = value; + break; + case M32C_OPERAND_BITNO16R : + fields->f_dsp_16_u8 = value; + break; + case M32C_OPERAND_BITNO32PREFIXED : + fields->f_bitno32_prefixed = value; + break; + case M32C_OPERAND_BITNO32UNPREFIXED : + fields->f_bitno32_unprefixed = value; + break; + case M32C_OPERAND_DSP_10_U6 : + fields->f_dsp_10_u6 = value; + break; + case M32C_OPERAND_DSP_16_S16 : + fields->f_dsp_16_s16 = value; + break; + case M32C_OPERAND_DSP_16_S8 : + fields->f_dsp_16_s8 = value; + break; + case M32C_OPERAND_DSP_16_U16 : + fields->f_dsp_16_u16 = value; + break; + case M32C_OPERAND_DSP_16_U20 : + fields->f_dsp_16_u24 = value; + break; + case M32C_OPERAND_DSP_16_U24 : + fields->f_dsp_16_u24 = value; + break; + case M32C_OPERAND_DSP_16_U8 : + fields->f_dsp_16_u8 = value; + break; + case M32C_OPERAND_DSP_24_S16 : + fields->f_dsp_24_s16 = value; + break; + case M32C_OPERAND_DSP_24_S8 : + fields->f_dsp_24_s8 = value; + break; + case M32C_OPERAND_DSP_24_U16 : + fields->f_dsp_24_u16 = value; + break; + case M32C_OPERAND_DSP_24_U20 : + fields->f_dsp_24_u24 = value; + break; + case M32C_OPERAND_DSP_24_U24 : + fields->f_dsp_24_u24 = value; + break; + case M32C_OPERAND_DSP_24_U8 : + fields->f_dsp_24_u8 = value; + break; + case M32C_OPERAND_DSP_32_S16 : + fields->f_dsp_32_s16 = value; + break; + case M32C_OPERAND_DSP_32_S8 : + fields->f_dsp_32_s8 = value; + break; + case M32C_OPERAND_DSP_32_U16 : + fields->f_dsp_32_u16 = value; + break; + case M32C_OPERAND_DSP_32_U20 : + fields->f_dsp_32_u24 = value; + break; + case M32C_OPERAND_DSP_32_U24 : + fields->f_dsp_32_u24 = value; + break; + case M32C_OPERAND_DSP_32_U8 : + fields->f_dsp_32_u8 = value; + break; + case M32C_OPERAND_DSP_40_S16 : + fields->f_dsp_40_s16 = value; + break; + case M32C_OPERAND_DSP_40_S8 : + fields->f_dsp_40_s8 = value; + break; + case M32C_OPERAND_DSP_40_U16 : + fields->f_dsp_40_u16 = value; + break; + case M32C_OPERAND_DSP_40_U24 : + fields->f_dsp_40_u24 = value; + break; + case M32C_OPERAND_DSP_40_U8 : + fields->f_dsp_40_u8 = value; + break; + case M32C_OPERAND_DSP_48_S16 : + fields->f_dsp_48_s16 = value; + break; + case M32C_OPERAND_DSP_48_S8 : + fields->f_dsp_48_s8 = value; + break; + case M32C_OPERAND_DSP_48_U16 : + fields->f_dsp_48_u16 = value; + break; + case M32C_OPERAND_DSP_48_U24 : + fields->f_dsp_48_u24 = value; + break; + case M32C_OPERAND_DSP_48_U8 : + fields->f_dsp_48_u8 = value; + break; + case M32C_OPERAND_DSP_8_S8 : + fields->f_dsp_8_s8 = value; + break; + case M32C_OPERAND_DSP_8_U16 : + fields->f_dsp_8_u16 = value; + break; + case M32C_OPERAND_DSP_8_U24 : + fields->f_dsp_8_u24 = value; + break; + case M32C_OPERAND_DSP_8_U6 : + fields->f_dsp_8_u6 = value; + break; + case M32C_OPERAND_DSP_8_U8 : + fields->f_dsp_8_u8 = value; + break; + case M32C_OPERAND_DST16AN : + fields->f_dst16_an = value; + break; + case M32C_OPERAND_DST16AN_S : + fields->f_dst16_an_s = value; + break; + case M32C_OPERAND_DST16ANHI : + fields->f_dst16_an = value; + break; + case M32C_OPERAND_DST16ANQI : + fields->f_dst16_an = value; + break; + case M32C_OPERAND_DST16ANQI_S : + fields->f_dst16_rn_QI_s = value; + break; + case M32C_OPERAND_DST16ANSI : + fields->f_dst16_an = value; + break; + case M32C_OPERAND_DST16RNEXTQI : + fields->f_dst16_rn_ext = value; + break; + case M32C_OPERAND_DST16RNHI : + fields->f_dst16_rn = value; + break; + case M32C_OPERAND_DST16RNQI : + fields->f_dst16_rn = value; + break; + case M32C_OPERAND_DST16RNQI_S : + fields->f_dst16_rn_QI_s = value; + break; + case M32C_OPERAND_DST16RNSI : + fields->f_dst16_rn = value; + break; + case M32C_OPERAND_DST32ANEXTUNPREFIXED : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_DST32ANPREFIXED : + fields->f_dst32_an_prefixed = value; + break; + case M32C_OPERAND_DST32ANPREFIXEDHI : + fields->f_dst32_an_prefixed = value; + break; + case M32C_OPERAND_DST32ANPREFIXEDQI : + fields->f_dst32_an_prefixed = value; + break; + case M32C_OPERAND_DST32ANPREFIXEDSI : + fields->f_dst32_an_prefixed = value; + break; + case M32C_OPERAND_DST32ANUNPREFIXED : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDHI : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDQI : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDSI : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_DST32R0HI_S : + break; + case M32C_OPERAND_DST32R0QI_S : + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDHI : + fields->f_dst32_rn_ext_unprefixed = value; + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDQI : + fields->f_dst32_rn_ext_unprefixed = value; + break; + case M32C_OPERAND_DST32RNPREFIXEDHI : + fields->f_dst32_rn_prefixed_HI = value; + break; + case M32C_OPERAND_DST32RNPREFIXEDQI : + fields->f_dst32_rn_prefixed_QI = value; + break; + case M32C_OPERAND_DST32RNPREFIXEDSI : + fields->f_dst32_rn_prefixed_SI = value; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDHI : + fields->f_dst32_rn_unprefixed_HI = value; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDQI : + fields->f_dst32_rn_unprefixed_QI = value; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDSI : + fields->f_dst32_rn_unprefixed_SI = value; + break; + case M32C_OPERAND_G : + break; + case M32C_OPERAND_IMM_12_S4 : + fields->f_imm_12_s4 = value; + break; + case M32C_OPERAND_IMM_13_U3 : + fields->f_imm_13_u3 = value; + break; + case M32C_OPERAND_IMM_16_HI : + fields->f_dsp_16_s16 = value; + break; + case M32C_OPERAND_IMM_16_QI : + fields->f_dsp_16_s8 = value; + break; + case M32C_OPERAND_IMM_16_SI : + fields->f_dsp_16_s32 = value; + break; + case M32C_OPERAND_IMM_20_S4 : + fields->f_imm_20_s4 = value; + break; + case M32C_OPERAND_IMM_24_HI : + fields->f_dsp_24_s16 = value; + break; + case M32C_OPERAND_IMM_24_QI : + fields->f_dsp_24_s8 = value; + break; + case M32C_OPERAND_IMM_24_SI : + fields->f_dsp_24_s32 = value; + break; + case M32C_OPERAND_IMM_32_HI : + fields->f_dsp_32_s16 = value; + break; + case M32C_OPERAND_IMM_32_QI : + fields->f_dsp_32_s8 = value; + break; + case M32C_OPERAND_IMM_32_SI : + fields->f_dsp_32_s32 = value; + break; + case M32C_OPERAND_IMM_40_HI : + fields->f_dsp_40_s16 = value; + break; + case M32C_OPERAND_IMM_40_QI : + fields->f_dsp_40_s8 = value; + break; + case M32C_OPERAND_IMM_40_SI : + fields->f_dsp_40_s32 = value; + break; + case M32C_OPERAND_IMM_48_HI : + fields->f_dsp_48_s16 = value; + break; + case M32C_OPERAND_IMM_48_QI : + fields->f_dsp_48_s8 = value; + break; + case M32C_OPERAND_IMM_48_SI : + fields->f_dsp_48_s32 = value; + break; + case M32C_OPERAND_IMM_56_HI : + fields->f_dsp_56_s16 = value; + break; + case M32C_OPERAND_IMM_56_QI : + fields->f_dsp_56_s8 = value; + break; + case M32C_OPERAND_IMM_64_HI : + fields->f_dsp_64_s16 = value; + break; + case M32C_OPERAND_IMM_8_HI : + fields->f_dsp_8_s16 = value; + break; + case M32C_OPERAND_IMM_8_QI : + fields->f_dsp_8_s8 = value; + break; + case M32C_OPERAND_IMM_8_S4 : + fields->f_imm_8_s4 = value; + break; + case M32C_OPERAND_IMM_SH_12_S4 : + fields->f_imm_12_s4 = value; + break; + case M32C_OPERAND_IMM_SH_20_S4 : + fields->f_imm_20_s4 = value; + break; + case M32C_OPERAND_IMM_SH_8_S4 : + fields->f_imm_8_s4 = value; + break; + case M32C_OPERAND_IMM1_S : + fields->f_imm1_S = value; + break; + case M32C_OPERAND_IMM3_S : + fields->f_imm3_S = value; + break; + case M32C_OPERAND_LAB_16_8 : + fields->f_lab_16_8 = value; + break; + case M32C_OPERAND_LAB_24_8 : + fields->f_lab_24_8 = value; + break; + case M32C_OPERAND_LAB_32_8 : + fields->f_lab_32_8 = value; + break; + case M32C_OPERAND_LAB_40_8 : + fields->f_lab_40_8 = value; + break; + case M32C_OPERAND_LAB_5_3 : + fields->f_lab_5_3 = value; + break; + case M32C_OPERAND_LAB_8_16 : + fields->f_lab_8_16 = value; + break; + case M32C_OPERAND_LAB_8_24 : + fields->f_lab_8_24 = value; + break; + case M32C_OPERAND_LAB_8_8 : + fields->f_lab_8_8 = value; + break; + case M32C_OPERAND_LAB32_JMP_S : + fields->f_lab32_jmp_s = value; + break; + case M32C_OPERAND_Q : + break; + case M32C_OPERAND_R0 : + break; + case M32C_OPERAND_R0H : + break; + case M32C_OPERAND_R0L : + break; + case M32C_OPERAND_R1 : + break; + case M32C_OPERAND_R1R2R0 : + break; + case M32C_OPERAND_R2 : + break; + case M32C_OPERAND_R2R0 : + break; + case M32C_OPERAND_R3 : + break; + case M32C_OPERAND_R3R1 : + break; + case M32C_OPERAND_REGSETPOP : + fields->f_8_8 = value; + break; + case M32C_OPERAND_REGSETPUSH : + fields->f_8_8 = value; + break; + case M32C_OPERAND_RN16_PUSH_S : + fields->f_4_1 = value; + break; + case M32C_OPERAND_S : + break; + case M32C_OPERAND_SRC16AN : + fields->f_src16_an = value; + break; + case M32C_OPERAND_SRC16ANHI : + fields->f_src16_an = value; + break; + case M32C_OPERAND_SRC16ANQI : + fields->f_src16_an = value; + break; + case M32C_OPERAND_SRC16RNHI : + fields->f_src16_rn = value; + break; + case M32C_OPERAND_SRC16RNQI : + fields->f_src16_rn = value; + break; + case M32C_OPERAND_SRC32ANPREFIXED : + fields->f_src32_an_prefixed = value; + break; + case M32C_OPERAND_SRC32ANPREFIXEDHI : + fields->f_src32_an_prefixed = value; + break; + case M32C_OPERAND_SRC32ANPREFIXEDQI : + fields->f_src32_an_prefixed = value; + break; + case M32C_OPERAND_SRC32ANPREFIXEDSI : + fields->f_src32_an_prefixed = value; + break; + case M32C_OPERAND_SRC32ANUNPREFIXED : + fields->f_src32_an_unprefixed = value; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDHI : + fields->f_src32_an_unprefixed = value; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDQI : + fields->f_src32_an_unprefixed = value; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDSI : + fields->f_src32_an_unprefixed = value; + break; + case M32C_OPERAND_SRC32RNPREFIXEDHI : + fields->f_src32_rn_prefixed_HI = value; + break; + case M32C_OPERAND_SRC32RNPREFIXEDQI : + fields->f_src32_rn_prefixed_QI = value; + break; + case M32C_OPERAND_SRC32RNPREFIXEDSI : + fields->f_src32_rn_prefixed_SI = value; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDHI : + fields->f_src32_rn_unprefixed_HI = value; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDQI : + fields->f_src32_rn_unprefixed_QI = value; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDSI : + fields->f_src32_rn_unprefixed_SI = value; + break; + case M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL : + fields->f_5_1 = value; + break; + case M32C_OPERAND_X : + break; + case M32C_OPERAND_Z : + break; + case M32C_OPERAND_COND16_16 : + fields->f_dsp_16_u8 = value; + break; + case M32C_OPERAND_COND16_24 : + fields->f_dsp_24_u8 = value; + break; + case M32C_OPERAND_COND16_32 : + fields->f_dsp_32_u8 = value; + break; + case M32C_OPERAND_COND16C : + fields->f_cond16 = value; + break; + case M32C_OPERAND_COND16J : + fields->f_cond16 = value; + break; + case M32C_OPERAND_COND16J5 : + fields->f_cond16j_5 = value; + break; + case M32C_OPERAND_COND32 : + fields->f_cond32 = value; + break; + case M32C_OPERAND_COND32_16 : + fields->f_dsp_16_u8 = value; + break; + case M32C_OPERAND_COND32_24 : + fields->f_dsp_24_u8 = value; + break; + case M32C_OPERAND_COND32_32 : + fields->f_dsp_32_u8 = value; + break; + case M32C_OPERAND_COND32_40 : + fields->f_dsp_40_u8 = value; + break; + case M32C_OPERAND_COND32J : + fields->f_cond32j = value; + break; + case M32C_OPERAND_CR1_PREFIXED_32 : + fields->f_21_3 = value; + break; + case M32C_OPERAND_CR1_UNPREFIXED_32 : + fields->f_13_3 = value; + break; + case M32C_OPERAND_CR16 : + fields->f_9_3 = value; + break; + case M32C_OPERAND_CR2_32 : + fields->f_13_3 = value; + break; + case M32C_OPERAND_CR3_PREFIXED_32 : + fields->f_21_3 = value; + break; + case M32C_OPERAND_CR3_UNPREFIXED_32 : + fields->f_13_3 = value; + break; + case M32C_OPERAND_FLAGS16 : + fields->f_9_3 = value; + break; + case M32C_OPERAND_FLAGS32 : + fields->f_13_3 = value; + break; + case M32C_OPERAND_SCCOND32 : + fields->f_cond16 = value; + break; + case M32C_OPERAND_SIZE : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +m32c_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) +{ + switch (opindex) + { + case M32C_OPERAND_A0 : + break; + case M32C_OPERAND_A1 : + break; + case M32C_OPERAND_AN16_PUSH_S : + fields->f_4_1 = value; + break; + case M32C_OPERAND_BIT16AN : + fields->f_dst16_an = value; + break; + case M32C_OPERAND_BIT16RN : + fields->f_dst16_rn = value; + break; + case M32C_OPERAND_BIT32ANPREFIXED : + fields->f_dst32_an_prefixed = value; + break; + case M32C_OPERAND_BIT32ANUNPREFIXED : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_BIT32RNPREFIXED : + fields->f_dst32_rn_prefixed_QI = value; + break; + case M32C_OPERAND_BIT32RNUNPREFIXED : + fields->f_dst32_rn_unprefixed_QI = value; + break; + case M32C_OPERAND_BITBASE16_16_S8 : + fields->f_dsp_16_s8 = value; + break; + case M32C_OPERAND_BITBASE16_16_U16 : + fields->f_dsp_16_u16 = value; + break; + case M32C_OPERAND_BITBASE16_16_U8 : + fields->f_dsp_16_u8 = value; + break; + case M32C_OPERAND_BITBASE16_8_U11_S : + fields->f_bitbase16_u11_S = value; + break; + case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED : + fields->f_bitbase32_16_s11_unprefixed = value; + break; + case M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED : + fields->f_bitbase32_16_s19_unprefixed = value; + break; + case M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED : + fields->f_bitbase32_16_u11_unprefixed = value; + break; + case M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED : + fields->f_bitbase32_16_u19_unprefixed = value; + break; + case M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED : + fields->f_bitbase32_16_u27_unprefixed = value; + break; + case M32C_OPERAND_BITBASE32_24_S11_PREFIXED : + fields->f_bitbase32_24_s11_prefixed = value; + break; + case M32C_OPERAND_BITBASE32_24_S19_PREFIXED : + fields->f_bitbase32_24_s19_prefixed = value; + break; + case M32C_OPERAND_BITBASE32_24_U11_PREFIXED : + fields->f_bitbase32_24_u11_prefixed = value; + break; + case M32C_OPERAND_BITBASE32_24_U19_PREFIXED : + fields->f_bitbase32_24_u19_prefixed = value; + break; + case M32C_OPERAND_BITBASE32_24_U27_PREFIXED : + fields->f_bitbase32_24_u27_prefixed = value; + break; + case M32C_OPERAND_BITNO16R : + fields->f_dsp_16_u8 = value; + break; + case M32C_OPERAND_BITNO32PREFIXED : + fields->f_bitno32_prefixed = value; + break; + case M32C_OPERAND_BITNO32UNPREFIXED : + fields->f_bitno32_unprefixed = value; + break; + case M32C_OPERAND_DSP_10_U6 : + fields->f_dsp_10_u6 = value; + break; + case M32C_OPERAND_DSP_16_S16 : + fields->f_dsp_16_s16 = value; + break; + case M32C_OPERAND_DSP_16_S8 : + fields->f_dsp_16_s8 = value; + break; + case M32C_OPERAND_DSP_16_U16 : + fields->f_dsp_16_u16 = value; + break; + case M32C_OPERAND_DSP_16_U20 : + fields->f_dsp_16_u24 = value; + break; + case M32C_OPERAND_DSP_16_U24 : + fields->f_dsp_16_u24 = value; + break; + case M32C_OPERAND_DSP_16_U8 : + fields->f_dsp_16_u8 = value; + break; + case M32C_OPERAND_DSP_24_S16 : + fields->f_dsp_24_s16 = value; + break; + case M32C_OPERAND_DSP_24_S8 : + fields->f_dsp_24_s8 = value; + break; + case M32C_OPERAND_DSP_24_U16 : + fields->f_dsp_24_u16 = value; + break; + case M32C_OPERAND_DSP_24_U20 : + fields->f_dsp_24_u24 = value; + break; + case M32C_OPERAND_DSP_24_U24 : + fields->f_dsp_24_u24 = value; + break; + case M32C_OPERAND_DSP_24_U8 : + fields->f_dsp_24_u8 = value; + break; + case M32C_OPERAND_DSP_32_S16 : + fields->f_dsp_32_s16 = value; + break; + case M32C_OPERAND_DSP_32_S8 : + fields->f_dsp_32_s8 = value; + break; + case M32C_OPERAND_DSP_32_U16 : + fields->f_dsp_32_u16 = value; + break; + case M32C_OPERAND_DSP_32_U20 : + fields->f_dsp_32_u24 = value; + break; + case M32C_OPERAND_DSP_32_U24 : + fields->f_dsp_32_u24 = value; + break; + case M32C_OPERAND_DSP_32_U8 : + fields->f_dsp_32_u8 = value; + break; + case M32C_OPERAND_DSP_40_S16 : + fields->f_dsp_40_s16 = value; + break; + case M32C_OPERAND_DSP_40_S8 : + fields->f_dsp_40_s8 = value; + break; + case M32C_OPERAND_DSP_40_U16 : + fields->f_dsp_40_u16 = value; + break; + case M32C_OPERAND_DSP_40_U24 : + fields->f_dsp_40_u24 = value; + break; + case M32C_OPERAND_DSP_40_U8 : + fields->f_dsp_40_u8 = value; + break; + case M32C_OPERAND_DSP_48_S16 : + fields->f_dsp_48_s16 = value; + break; + case M32C_OPERAND_DSP_48_S8 : + fields->f_dsp_48_s8 = value; + break; + case M32C_OPERAND_DSP_48_U16 : + fields->f_dsp_48_u16 = value; + break; + case M32C_OPERAND_DSP_48_U24 : + fields->f_dsp_48_u24 = value; + break; + case M32C_OPERAND_DSP_48_U8 : + fields->f_dsp_48_u8 = value; + break; + case M32C_OPERAND_DSP_8_S8 : + fields->f_dsp_8_s8 = value; + break; + case M32C_OPERAND_DSP_8_U16 : + fields->f_dsp_8_u16 = value; + break; + case M32C_OPERAND_DSP_8_U24 : + fields->f_dsp_8_u24 = value; + break; + case M32C_OPERAND_DSP_8_U6 : + fields->f_dsp_8_u6 = value; + break; + case M32C_OPERAND_DSP_8_U8 : + fields->f_dsp_8_u8 = value; + break; + case M32C_OPERAND_DST16AN : + fields->f_dst16_an = value; + break; + case M32C_OPERAND_DST16AN_S : + fields->f_dst16_an_s = value; + break; + case M32C_OPERAND_DST16ANHI : + fields->f_dst16_an = value; + break; + case M32C_OPERAND_DST16ANQI : + fields->f_dst16_an = value; + break; + case M32C_OPERAND_DST16ANQI_S : + fields->f_dst16_rn_QI_s = value; + break; + case M32C_OPERAND_DST16ANSI : + fields->f_dst16_an = value; + break; + case M32C_OPERAND_DST16RNEXTQI : + fields->f_dst16_rn_ext = value; + break; + case M32C_OPERAND_DST16RNHI : + fields->f_dst16_rn = value; + break; + case M32C_OPERAND_DST16RNQI : + fields->f_dst16_rn = value; + break; + case M32C_OPERAND_DST16RNQI_S : + fields->f_dst16_rn_QI_s = value; + break; + case M32C_OPERAND_DST16RNSI : + fields->f_dst16_rn = value; + break; + case M32C_OPERAND_DST32ANEXTUNPREFIXED : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_DST32ANPREFIXED : + fields->f_dst32_an_prefixed = value; + break; + case M32C_OPERAND_DST32ANPREFIXEDHI : + fields->f_dst32_an_prefixed = value; + break; + case M32C_OPERAND_DST32ANPREFIXEDQI : + fields->f_dst32_an_prefixed = value; + break; + case M32C_OPERAND_DST32ANPREFIXEDSI : + fields->f_dst32_an_prefixed = value; + break; + case M32C_OPERAND_DST32ANUNPREFIXED : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDHI : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDQI : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_DST32ANUNPREFIXEDSI : + fields->f_dst32_an_unprefixed = value; + break; + case M32C_OPERAND_DST32R0HI_S : + break; + case M32C_OPERAND_DST32R0QI_S : + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDHI : + fields->f_dst32_rn_ext_unprefixed = value; + break; + case M32C_OPERAND_DST32RNEXTUNPREFIXEDQI : + fields->f_dst32_rn_ext_unprefixed = value; + break; + case M32C_OPERAND_DST32RNPREFIXEDHI : + fields->f_dst32_rn_prefixed_HI = value; + break; + case M32C_OPERAND_DST32RNPREFIXEDQI : + fields->f_dst32_rn_prefixed_QI = value; + break; + case M32C_OPERAND_DST32RNPREFIXEDSI : + fields->f_dst32_rn_prefixed_SI = value; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDHI : + fields->f_dst32_rn_unprefixed_HI = value; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDQI : + fields->f_dst32_rn_unprefixed_QI = value; + break; + case M32C_OPERAND_DST32RNUNPREFIXEDSI : + fields->f_dst32_rn_unprefixed_SI = value; + break; + case M32C_OPERAND_G : + break; + case M32C_OPERAND_IMM_12_S4 : + fields->f_imm_12_s4 = value; + break; + case M32C_OPERAND_IMM_13_U3 : + fields->f_imm_13_u3 = value; + break; + case M32C_OPERAND_IMM_16_HI : + fields->f_dsp_16_s16 = value; + break; + case M32C_OPERAND_IMM_16_QI : + fields->f_dsp_16_s8 = value; + break; + case M32C_OPERAND_IMM_16_SI : + fields->f_dsp_16_s32 = value; + break; + case M32C_OPERAND_IMM_20_S4 : + fields->f_imm_20_s4 = value; + break; + case M32C_OPERAND_IMM_24_HI : + fields->f_dsp_24_s16 = value; + break; + case M32C_OPERAND_IMM_24_QI : + fields->f_dsp_24_s8 = value; + break; + case M32C_OPERAND_IMM_24_SI : + fields->f_dsp_24_s32 = value; + break; + case M32C_OPERAND_IMM_32_HI : + fields->f_dsp_32_s16 = value; + break; + case M32C_OPERAND_IMM_32_QI : + fields->f_dsp_32_s8 = value; + break; + case M32C_OPERAND_IMM_32_SI : + fields->f_dsp_32_s32 = value; + break; + case M32C_OPERAND_IMM_40_HI : + fields->f_dsp_40_s16 = value; + break; + case M32C_OPERAND_IMM_40_QI : + fields->f_dsp_40_s8 = value; + break; + case M32C_OPERAND_IMM_40_SI : + fields->f_dsp_40_s32 = value; + break; + case M32C_OPERAND_IMM_48_HI : + fields->f_dsp_48_s16 = value; + break; + case M32C_OPERAND_IMM_48_QI : + fields->f_dsp_48_s8 = value; + break; + case M32C_OPERAND_IMM_48_SI : + fields->f_dsp_48_s32 = value; + break; + case M32C_OPERAND_IMM_56_HI : + fields->f_dsp_56_s16 = value; + break; + case M32C_OPERAND_IMM_56_QI : + fields->f_dsp_56_s8 = value; + break; + case M32C_OPERAND_IMM_64_HI : + fields->f_dsp_64_s16 = value; + break; + case M32C_OPERAND_IMM_8_HI : + fields->f_dsp_8_s16 = value; + break; + case M32C_OPERAND_IMM_8_QI : + fields->f_dsp_8_s8 = value; + break; + case M32C_OPERAND_IMM_8_S4 : + fields->f_imm_8_s4 = value; + break; + case M32C_OPERAND_IMM_SH_12_S4 : + fields->f_imm_12_s4 = value; + break; + case M32C_OPERAND_IMM_SH_20_S4 : + fields->f_imm_20_s4 = value; + break; + case M32C_OPERAND_IMM_SH_8_S4 : + fields->f_imm_8_s4 = value; + break; + case M32C_OPERAND_IMM1_S : + fields->f_imm1_S = value; + break; + case M32C_OPERAND_IMM3_S : + fields->f_imm3_S = value; + break; + case M32C_OPERAND_LAB_16_8 : + fields->f_lab_16_8 = value; + break; + case M32C_OPERAND_LAB_24_8 : + fields->f_lab_24_8 = value; + break; + case M32C_OPERAND_LAB_32_8 : + fields->f_lab_32_8 = value; + break; + case M32C_OPERAND_LAB_40_8 : + fields->f_lab_40_8 = value; + break; + case M32C_OPERAND_LAB_5_3 : + fields->f_lab_5_3 = value; + break; + case M32C_OPERAND_LAB_8_16 : + fields->f_lab_8_16 = value; + break; + case M32C_OPERAND_LAB_8_24 : + fields->f_lab_8_24 = value; + break; + case M32C_OPERAND_LAB_8_8 : + fields->f_lab_8_8 = value; + break; + case M32C_OPERAND_LAB32_JMP_S : + fields->f_lab32_jmp_s = value; + break; + case M32C_OPERAND_Q : + break; + case M32C_OPERAND_R0 : + break; + case M32C_OPERAND_R0H : + break; + case M32C_OPERAND_R0L : + break; + case M32C_OPERAND_R1 : + break; + case M32C_OPERAND_R1R2R0 : + break; + case M32C_OPERAND_R2 : + break; + case M32C_OPERAND_R2R0 : + break; + case M32C_OPERAND_R3 : + break; + case M32C_OPERAND_R3R1 : + break; + case M32C_OPERAND_REGSETPOP : + fields->f_8_8 = value; + break; + case M32C_OPERAND_REGSETPUSH : + fields->f_8_8 = value; + break; + case M32C_OPERAND_RN16_PUSH_S : + fields->f_4_1 = value; + break; + case M32C_OPERAND_S : + break; + case M32C_OPERAND_SRC16AN : + fields->f_src16_an = value; + break; + case M32C_OPERAND_SRC16ANHI : + fields->f_src16_an = value; + break; + case M32C_OPERAND_SRC16ANQI : + fields->f_src16_an = value; + break; + case M32C_OPERAND_SRC16RNHI : + fields->f_src16_rn = value; + break; + case M32C_OPERAND_SRC16RNQI : + fields->f_src16_rn = value; + break; + case M32C_OPERAND_SRC32ANPREFIXED : + fields->f_src32_an_prefixed = value; + break; + case M32C_OPERAND_SRC32ANPREFIXEDHI : + fields->f_src32_an_prefixed = value; + break; + case M32C_OPERAND_SRC32ANPREFIXEDQI : + fields->f_src32_an_prefixed = value; + break; + case M32C_OPERAND_SRC32ANPREFIXEDSI : + fields->f_src32_an_prefixed = value; + break; + case M32C_OPERAND_SRC32ANUNPREFIXED : + fields->f_src32_an_unprefixed = value; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDHI : + fields->f_src32_an_unprefixed = value; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDQI : + fields->f_src32_an_unprefixed = value; + break; + case M32C_OPERAND_SRC32ANUNPREFIXEDSI : + fields->f_src32_an_unprefixed = value; + break; + case M32C_OPERAND_SRC32RNPREFIXEDHI : + fields->f_src32_rn_prefixed_HI = value; + break; + case M32C_OPERAND_SRC32RNPREFIXEDQI : + fields->f_src32_rn_prefixed_QI = value; + break; + case M32C_OPERAND_SRC32RNPREFIXEDSI : + fields->f_src32_rn_prefixed_SI = value; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDHI : + fields->f_src32_rn_unprefixed_HI = value; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDQI : + fields->f_src32_rn_unprefixed_QI = value; + break; + case M32C_OPERAND_SRC32RNUNPREFIXEDSI : + fields->f_src32_rn_unprefixed_SI = value; + break; + case M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL : + fields->f_5_1 = value; + break; + case M32C_OPERAND_X : + break; + case M32C_OPERAND_Z : + break; + case M32C_OPERAND_COND16_16 : + fields->f_dsp_16_u8 = value; + break; + case M32C_OPERAND_COND16_24 : + fields->f_dsp_24_u8 = value; + break; + case M32C_OPERAND_COND16_32 : + fields->f_dsp_32_u8 = value; + break; + case M32C_OPERAND_COND16C : + fields->f_cond16 = value; + break; + case M32C_OPERAND_COND16J : + fields->f_cond16 = value; + break; + case M32C_OPERAND_COND16J5 : + fields->f_cond16j_5 = value; + break; + case M32C_OPERAND_COND32 : + fields->f_cond32 = value; + break; + case M32C_OPERAND_COND32_16 : + fields->f_dsp_16_u8 = value; + break; + case M32C_OPERAND_COND32_24 : + fields->f_dsp_24_u8 = value; + break; + case M32C_OPERAND_COND32_32 : + fields->f_dsp_32_u8 = value; + break; + case M32C_OPERAND_COND32_40 : + fields->f_dsp_40_u8 = value; + break; + case M32C_OPERAND_COND32J : + fields->f_cond32j = value; + break; + case M32C_OPERAND_CR1_PREFIXED_32 : + fields->f_21_3 = value; + break; + case M32C_OPERAND_CR1_UNPREFIXED_32 : + fields->f_13_3 = value; + break; + case M32C_OPERAND_CR16 : + fields->f_9_3 = value; + break; + case M32C_OPERAND_CR2_32 : + fields->f_13_3 = value; + break; + case M32C_OPERAND_CR3_PREFIXED_32 : + fields->f_21_3 = value; + break; + case M32C_OPERAND_CR3_UNPREFIXED_32 : + fields->f_13_3 = value; + break; + case M32C_OPERAND_FLAGS16 : + fields->f_9_3 = value; + break; + case M32C_OPERAND_FLAGS32 : + fields->f_13_3 = value; + break; + case M32C_OPERAND_SCCOND32 : + fields->f_cond16 = value; + break; + case M32C_OPERAND_SIZE : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +m32c_cgen_init_ibld_table (CGEN_CPU_DESC cd) +{ + cd->insert_handlers = & m32c_cgen_insert_handlers[0]; + cd->extract_handlers = & m32c_cgen_extract_handlers[0]; + + cd->insert_operand = m32c_cgen_insert_operand; + cd->extract_operand = m32c_cgen_extract_operand; + + cd->get_int_operand = m32c_cgen_get_int_operand; + cd->set_int_operand = m32c_cgen_set_int_operand; + cd->get_vma_operand = m32c_cgen_get_vma_operand; + cd->set_vma_operand = m32c_cgen_set_vma_operand; +} diff -uprN binutils-2.16.91.0.1/opcodes/m32c-opc.c binutils-2.16.91.0.2/opcodes/m32c-opc.c --- binutils-2.16.91.0.1/opcodes/m32c-opc.c 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/opcodes/m32c-opc.c 2005-07-20 12:27:29.192879787 -0700 @@ -0,0 +1,79406 @@ +/* Instruction opcode table for m32c. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2005 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "m32c-desc.h" +#include "m32c-opc.h" +#include "libiberty.h" + +/* -- opc.c */ +static unsigned int +m32c_asm_hash (const char *mnem) +{ + unsigned int h; + + /* The length of the mnemonic for the Jcnd insns is 1. Hash jsri. */ + if (mnem[0] == 'j' && mnem[1] != 's') + return 'j'; + + /* Don't hash scCND */ + if (mnem[0] == 's' && mnem[1] == 'c') + return 's'; + + for (h = 0; *mnem && *mnem != ' ' && *mnem != ':'; ++mnem) + h += *mnem; + return h % CGEN_ASM_HASH_SIZE; +} + +/* -- asm.c */ +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); + +/* Instruction formats. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & m32c_cgen_ifld_table[M32C_##f] +#else +#define F(f) & m32c_cgen_ifld_table[M32C_/**/f] +#endif +static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff0f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_Rn_direct_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_RN_EXT_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_An_indirect_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_An_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_An_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_24_An_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_SB_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_SB_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_FB_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_FB_relative_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_absolute_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_w_16_ExtUnprefixed_dst32_16_24_absolute_ExtUnprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_Rn_direct_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_RN_EXT_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_An_indirect_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_An_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_An_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_24_An_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_SB_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_SB_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_FB_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_FB_relative_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_absolute_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts32_b_16_ExtUnprefixed_dst32_16_24_absolute_ExtUnprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_Rn_direct_Ext_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffd, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN_EXT) }, { F (F_15_1) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_An_indirect_Ext_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_8_An_relative_Ext_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_16_An_relative_Ext_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_8_SB_relative_Ext_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_16_SB_relative_Ext_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_8_FB_relative_Ext_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_exts16_b_16_Ext_dst16_16_16_absolute_Ext_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff2f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff8f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_HI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff2f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff8f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffec00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffec0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffcc, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffec, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffec, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffce, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffce, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffce00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffce0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffec00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_24_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { F (F_12_4) }, { F (F_DSP_24_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffec0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_32_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_8_4) }, { F (F_DSP_16_U16) }, { F (F_12_4) }, { F (F_DSP_32_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffcc, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffec, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffec, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffce, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffce, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffee, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffce00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffee00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffce0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffee0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_SRC16_RN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_4) }, { F (F_8_2) }, { F (F_10_1) }, { F (F_SRC16_AN) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r3_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r3_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r3_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r3_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r0_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r0_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r0_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r0_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r0_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r0_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r0_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r0_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xchg16w_r0_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_2) }, { F (F_10_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xff000000, { { F (F_0_2) }, { F (F_DSP_24_S16) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_8_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_DSP_8_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff0f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_HI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U8) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U16) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_40_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff2f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff3f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffbf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_48_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_DSP_24_U24) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_2) }, { F (F_DSP_24_U24) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_48_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff0f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff2f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff8f, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffaf, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff8f00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffaf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffcf00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_SRC32_RN_PREFIXED_QI) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffef00, { { F (F_0_4) }, { F (F_9_3) }, { F (F_18_1) }, { F (F_SRC32_AN_PREFIXED) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_15_1) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xff2f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xff8f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_QI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xff3f0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_40_HI_Imm_56_HI_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_w_Imm_40_HI_Imm_56_HI_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S16) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_40_QI_Imm_48_QI_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx32_b_Imm_40_QI_Imm_48_QI_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_S8) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_48_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_16_U8) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_16_S8) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_16_U16) }, { F (F_4_1) }, { F (F_DSP_8_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff3f, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_dst_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_dst_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_dst_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_dst_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_dst_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_dst_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_dst_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_dst_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_w_imm4_Q_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_shl16_b_imm4_Q_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff30, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sccnd_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_24_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffb00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_4) }, { F (F_LAB_32_8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffb00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xfff00000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_LAB_40_8) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_w_imm4_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0c00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_w_imm4_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_w_imm4_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_b_imm4_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0c00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_b_imm4_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbjnz16_b_imm4_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff3f00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_w_16_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_w_16_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_w_16_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_w_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_b_16_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_b_16_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_b_16_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rorc16_b_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_An_indirect_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_24_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_SB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_SB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_FB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_FB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_absolute_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha32_16_Unprefixed_Mova_dst32_16_24_absolute_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_push16_b_s_an_An16_push_S_derived ATTRIBUTE_UNUSED = { + 8, 8, 0xf7, { { F (F_0_4) }, { F (F_4_1) }, { F (F_5_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_push16_b_s_rn_Rn16_push_S_derived ATTRIBUTE_UNUSED = { + 8, 8, 0xf7, { { F (F_0_4) }, { F (F_4_1) }, { F (F_5_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mulex_dst32_R3_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff3f, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffbf, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffbf, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffbf, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_U8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_U8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_U8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_DSP_40_U8) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_dst_dspsp_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_dst_dspsp_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_SB_relative_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_FB_relative_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_sz_dst32_2_S_16_a1_dst32_2_S_16_absolute_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_dst32_2_S_basic_r1l_dst32_2_S_R0_direct_HI ATTRIBUTE_UNUSED = { + 8, 8, 0xff, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_dst32_2_S_basic_r1l_dst32_2_S_R0l_direct_QI ATTRIBUTE_UNUSED = { + 8, 8, 0xff, { { F (F_0_2) }, { F (F_2_2) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived ATTRIBUTE_UNUSED = { + 8, 8, 0xfb, { { F (F_0_4) }, { F (F_6_2) }, { F (F_5_1) }, { F (F_4_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_S_src2_src16_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfb00, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U8) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_S_src2_src16_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfb00, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_S8) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_S_src2_src16_2_S_16_absolute_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfb0000, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U16) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xff2f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xff3f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffbf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U8) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_24_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_32_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U16) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_S16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_32_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xff2f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xff3f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffbf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_40_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_DSP_16_U24) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffff0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_2) }, { F (F_DSP_16_U24) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_40_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff2f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8f, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffaf, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xff8f00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffaf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xff8f0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffaf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffcf00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffef00, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffcf0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_SRC32_RN_UNPREFIXED_SI) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffef0000, { { F (F_0_1) }, { F (F_1_3) }, { F (F_10_1) }, { F (F_SRC32_AN_UNPREFIXED) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_S_An_src16_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfb00, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U8) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_S_An_src16_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xfb00, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_S8) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_S_An_src16_2_S_16_absolute_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfb0000, { { F (F_0_4) }, { F (F_6_2) }, { F (F_DSP_8_U16) }, { F (F_4_1) }, { F (F_DST16_RN_QI_S) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0l_direct_QI ATTRIBUTE_UNUSED = { + 8, 8, 0xff, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0h_direct_QI ATTRIBUTE_UNUSED = { + 8, 8, 0xff, { { F (F_0_4) }, { F (F_5_3) }, { F (F_4_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_U8) }, { F (F_4_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_S8) }, { F (F_4_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_16_absolute_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_5_3) }, { F (F_DSP_8_U16) }, { F (F_4_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_HI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xff3f0000, { { F (F_0_4) }, { F (F_DSP_16_S32) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_16_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_16_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_24_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_32_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 64, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 72, 0xffbf0000, { { F (F_0_4) }, { F (F_DSP_40_S32) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 72, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_40_S32) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_basic_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffc0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_basic_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste16_w_dst_dspsp_basic_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_24_U24) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_basic_dst16_Rn_direct_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffc0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_basic_dst16_An_direct_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ste16_b_dst_dspsp_basic_dst16_An_indirect_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_Rn_direct_Prefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff38, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_SI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_An_direct_Prefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_An_indirect_Prefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_8_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_16_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_24_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_8_SB_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_16_SB_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_8_FB_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_16_FB_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_16_absolute_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr3_dst32_24_24_absolute_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff38, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr2_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff38, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc32_src_cr1_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 48, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_1) }, { F (F_21_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc16_src_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc16_src_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc16_src_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff8e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc16_src_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff8e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc16_src_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff8e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc16_src_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff8f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc16_src_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff8f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc16_src_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff8f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stc16_src_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff8f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_An_relative_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_SB_relative_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_absolute_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_An_relative_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_SB_relative_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_FB_relative_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_Rn_direct_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffc, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_An_direct_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_Rn_direct_Prefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff3f, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_SI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_An_direct_Prefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffbf, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_An_indirect_Prefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffffbf, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_24_An_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_SB_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_SB_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_FB_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_FB_relative_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_absolute_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_24_absolute_Prefixed_SI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_16_absolute_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_8_SB_relative_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_8_FB_relative_QI ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_S8) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_16_absolute_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_2) }, { F (F_2_2) }, { F (F_DSP_8_U16) }, { F (F_4_3) }, { F (F_7_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp16_w_imm4_Q_16_dst16_Rn_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0c, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp16_w_imm4_Q_16_dst16_An_direct_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp16_w_imm4_Q_16_dst16_An_indirect_HI ATTRIBUTE_UNUSED = { + 16, 16, 0xff0e, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp16_w_imm4_Q_16_dst16_16_8_An_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0e00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp16_w_imm4_Q_16_dst16_16_16_An_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0e0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp16_w_imm4_Q_16_dst16_16_8_SB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp16_w_imm4_Q_16_dst16_16_16_SB_relative_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp16_w_imm4_Q_16_dst16_16_8_FB_relative_HI ATTRIBUTE_UNUSED = { + 24, 24, 0xff0f00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmp16_w_imm4_Q_16_dst16_16_16_absolute_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xff0f0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_IMM_8_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_Rn_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffff3f00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_HI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_An_direct_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_An_indirect_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_24_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 72, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_56_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S16) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_48_HI_Imm_64_HI_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 80, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_64_S16) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_w_Imm_48_HI_Imm_64_HI_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI ATTRIBUTE_UNUSED = { + 32, 80, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_64_S16) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S16) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_Rn_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffff3f00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_An_direct_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_An_indirect_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 40, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffbf00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U8) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 48, 0xffffff00, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U16) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_S16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 56, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U16) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_40_S8) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_48_QI_Imm_56_QI_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffbf00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DSP_24_U24) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_56_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_clip32_b_Imm_48_QI_Imm_56_QI_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI ATTRIBUTE_UNUSED = { + 32, 64, 0xffffff00, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_DSP_24_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_DSP_48_S8) }, { F (F_18_2) }, { F (F_20_4) }, { F (F_DSP_56_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed ATTRIBUTE_UNUSED = { + 24, 24, 0xffff38, { { F (F_0_4) }, { F (F_12_3) }, { F (F_DST32_RN_PREFIXED_QI) }, { F (F_BITNO32_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed ATTRIBUTE_UNUSED = { + 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_BITNO32_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed ATTRIBUTE_UNUSED = { + 24, 24, 0xffffb8, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_DST32_AN_PREFIXED) }, { F (F_BITNO32_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed ATTRIBUTE_UNUSED = { + 32, 32, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_BITBASE32_24_U11_PREFIXED) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed ATTRIBUTE_UNUSED = { + 32, 40, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_BITBASE32_24_U19_PREFIXED) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed ATTRIBUTE_UNUSED = { + 32, 48, 0xffffb800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_1) }, { F (F_BITBASE32_24_U27_PREFIXED) }, { F (F_DST32_AN_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed ATTRIBUTE_UNUSED = { + 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_U11_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed ATTRIBUTE_UNUSED = { + 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_U19_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed ATTRIBUTE_UNUSED = { + 32, 32, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_S11_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed ATTRIBUTE_UNUSED = { + 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_S19_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed ATTRIBUTE_UNUSED = { + 32, 40, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_U19_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed ATTRIBUTE_UNUSED = { + 32, 48, 0xfffff800, { { F (F_0_4) }, { F (F_12_3) }, { F (F_16_2) }, { F (F_BITBASE32_24_U27_PREFIXED) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_15_1) }, { F (F_18_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_Rn_direct ATTRIBUTE_UNUSED = { + 24, 24, 0xfffc00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_An_direct ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_An_indirect ATTRIBUTE_UNUSED = { + 16, 16, 0xfffe, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bxor16_X_bit16_16_bit16_16_16_absolute ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed ATTRIBUTE_UNUSED = { + 16, 16, 0xff38, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed ATTRIBUTE_UNUSED = { + 16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed ATTRIBUTE_UNUSED = { + 16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed ATTRIBUTE_UNUSED = { + 24, 24, 0xffb800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U11_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 32, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 40, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U27_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed ATTRIBUTE_UNUSED = { + 24, 24, 0xfff800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U11_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed ATTRIBUTE_UNUSED = { + 24, 24, 0xfff800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_S11_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_S19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed ATTRIBUTE_UNUSED = { + 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed ATTRIBUTE_UNUSED = { + 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U27_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S ATTRIBUTE_UNUSED = { + 16, 16, 0xf800, { { F (F_0_2) }, { F (F_BITBASE16_U11_S) }, { F (F_2_2) }, { F (F_4_1) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_Rn_direct_Unprefixed ATTRIBUTE_UNUSED = { + 24, 24, 0xff3800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_QI) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_An_direct_Unprefixed ATTRIBUTE_UNUSED = { + 24, 24, 0xffb800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_An_indirect_Unprefixed ATTRIBUTE_UNUSED = { + 24, 24, 0xffb800, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_BITNO32_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_An_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 32, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U11_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_SB_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U11_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_FB_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_S11_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_An_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 40, 0xffb80000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_SB_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_FB_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_S19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_absolute_Unprefixed ATTRIBUTE_UNUSED = { + 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U19_UNPREFIXED) }, { F (F_7_1) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_16_24_Unprefixed_cond32_40_bit32_16_27_An_relative_Unprefixed ATTRIBUTE_UNUSED = { + 32, 48, 0xffb80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_BITBASE32_16_U27_UNPREFIXED) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_U8) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_bit32_16_24_Unprefixed_cond32_40_bit32_16_27_absolute_Unprefixed ATTRIBUTE_UNUSED = { + 32, 48, 0xfff80000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_BITBASE32_16_U27_UNPREFIXED) }, { F (F_7_1) }, { F (F_DSP_40_U8) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_Rn_direct ATTRIBUTE_UNUSED = { + 32, 32, 0xfffc0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_DST16_RN) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_An_direct ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_An_relative ATTRIBUTE_UNUSED = { + 32, 32, 0xfffe0000, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U8) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_SB_relative ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_FB_relative ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_24_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_An_relative ATTRIBUTE_UNUSED = { + 32, 40, 0xfffe0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DSP_16_U16) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_SB_relative ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_absolute ATTRIBUTE_UNUSED = { + 32, 40, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U8) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { F (F_4_4) }, { F (F_8_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm16_bit16_16_basic_cond16_16_bit16_An_indirect ATTRIBUTE_UNUSED = { + 24, 24, 0xfffe00, { { F (F_0_4) }, { F (F_12_2) }, { F (F_14_1) }, { F (F_DST16_AN) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_s_imm1_S_an_dst32_1_S_A0_direct_HI ATTRIBUTE_UNUSED = { + 8, 8, 0xdf, { { F (F_0_2) }, { F (F_7_1) }, { F (F_IMM1_S) }, { F (F_3_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_s_imm1_S_an_dst32_1_S_A1_direct_HI ATTRIBUTE_UNUSED = { + 8, 8, 0xdf, { { F (F_0_2) }, { F (F_7_1) }, { F (F_IMM1_S) }, { F (F_3_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xff30, { { F (F_0_3) }, { F (F_4_3) }, { F (F_DST32_RN_UNPREFIXED_SI) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_SI ATTRIBUTE_UNUSED = { + 16, 16, 0xffb0, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xffb000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U8) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U16) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xffb00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_1) }, { F (F_DSP_16_U24) }, { F (F_DST32_AN_UNPREFIXED) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S8) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_S16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 32, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U16) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_SI ATTRIBUTE_UNUSED = { + 32, 40, 0xfff00000, { { F (F_0_3) }, { F (F_4_3) }, { F (F_8_2) }, { F (F_DSP_16_U24) }, { F (F_3_1) }, { F (F_7_1) }, { F (F_10_2) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add16_Q_sp ATTRIBUTE_UNUSED = { + 16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add16_b_G_sp ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add16_w_G_sp ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_3) }, { F (F_7_1) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm3_Q ATTRIBUTE_UNUSED = { + 8, 8, 0xce, { { F (F_0_2) }, { F (F_IMM3_S) }, { F (F_4_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm8_S ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add32_l_imm16_G ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dadc16_b_r0h_r0l ATTRIBUTE_UNUSED = { + 16, 16, 0xffff, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm16_c ATTRIBUTE_UNUSED = { + 16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_COND16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bm32_c ATTRIBUTE_UNUSED = { + 16, 16, 0xffb8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_COND32) }, { F (F_10_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_brk16 ATTRIBUTE_UNUSED = { + 8, 8, 0xff, { { F (F_0_4) }, { F (F_4_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dec16_w ATTRIBUTE_UNUSED = { + 8, 8, 0xf7, { { F (F_0_4) }, { F (F_DST16_AN_S) }, { F (F_5_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_div32_b_Imm_16_QI ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_3) }, { F (F_11_1) }, { F (F_12_4) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_div32_w_Imm_16_HI ATTRIBUTE_UNUSED = { + 32, 32, 0xffff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_3) }, { F (F_11_1) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_enter16 ATTRIBUTE_UNUSED = { + 24, 24, 0xffff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_enter32 ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_U8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fclr16 ATTRIBUTE_UNUSED = { + 16, 16, 0xff8f, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_fclr ATTRIBUTE_UNUSED = { + 16, 16, 0xfff8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_int16 ATTRIBUTE_UNUSED = { + 16, 16, 0xffc0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_2) }, { F (F_DSP_10_U6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_int32 ATTRIBUTE_UNUSED = { + 16, 16, 0xff03, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_U6) }, { F (F_14_2) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jcnd16_5 ATTRIBUTE_UNUSED = { + 16, 16, 0xf800, { { F (F_0_4) }, { F (F_4_1) }, { F (F_COND16J_5) }, { F (F_LAB_8_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jcnd16 ATTRIBUTE_UNUSED = { + 24, 24, 0xfff000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_COND16) }, { F (F_LAB_16_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jcnd32 ATTRIBUTE_UNUSED = { + 16, 16, 0x8e00, { { F (F_0_1) }, { F (F_COND32J) }, { F (F_4_3) }, { F (F_LAB_8_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmp16_s ATTRIBUTE_UNUSED = { + 8, 8, 0xf8, { { F (F_0_4) }, { F (F_4_1) }, { F (F_LAB_5_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmp16_b ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_LAB_8_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmp16_w ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_LAB_8_16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmp16_a ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_LAB_8_24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmps16 ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jmp32_s ATTRIBUTE_UNUSED = { + 8, 8, 0xce, { { F (F_0_2) }, { F (F_LAB32_JMP_S) }, { F (F_4_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldc16_imm16 ATTRIBUTE_UNUSED = { + 32, 32, 0xff8f0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { F (F_12_4) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldc32_imm16_cr1 ATTRIBUTE_UNUSED = { + 32, 32, 0xfff80000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { F (F_DSP_16_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldc32_imm16_cr2 ATTRIBUTE_UNUSED = { + 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldc32_imm16_cr3 ATTRIBUTE_UNUSED = { + 32, 40, 0xfff80000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldctx16 ATTRIBUTE_UNUSED = { + 32, 56, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_32_U24) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { F (F_DSP_16_U16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldipl16_imm ATTRIBUTE_UNUSED = { + 16, 16, 0xfff8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_IMM_13_U3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov16_w_S_imm_a0 ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S16) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mov32_l_a0 ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_U24) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_popc16_imm16 ATTRIBUTE_UNUSED = { + 16, 16, 0xff8f, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_1) }, { F (F_9_3) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_popc32_imm16_cr1 ATTRIBUTE_UNUSED = { + 16, 16, 0xfff8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_popc32_imm16_cr2 ATTRIBUTE_UNUSED = { + 16, 16, 0xfff8, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_1) }, { F (F_13_3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_popm16 ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pushm16 ATTRIBUTE_UNUSED = { + 16, 16, 0xff00, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_push32_l_imm ATTRIBUTE_UNUSED = { + 32, 48, 0xffff0000, { { F (F_0_4) }, { F (F_DSP_16_S32) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_12_4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sha16_L_imm_r2r0 ATTRIBUTE_UNUSED = { + 16, 16, 0xfff0, { { F (F_0_4) }, { F (F_4_4) }, { F (F_8_4) }, { F (F_IMM_12_S4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx16_imm8_imm8_r0h ATTRIBUTE_UNUSED = { + 24, 24, 0xff0000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx16_imm8_imm8_dsp8sb ATTRIBUTE_UNUSED = { + 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_U8) }, { F (F_DSP_24_S8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_stzx16_imm8_imm8_abs16 ATTRIBUTE_UNUSED = { + 32, 40, 0xff000000, { { F (F_0_4) }, { F (F_DSP_32_S8) }, { F (F_4_4) }, { F (F_DSP_8_S8) }, { F (F_DSP_16_U16) }, { 0 } } +}; + +#undef F + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) M32C_OPERAND_##op +#else +#define OPERAND(op) M32C_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1980b00 } + }, +/* extz ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1982b00 } + }, +/* extz ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1983b00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1908b00 } + }, +/* extz ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x190ab00 } + }, +/* extz ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x190bb00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1900b00 } + }, +/* extz ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1902b00 } + }, +/* extz ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1903b00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1920b00 } + }, +/* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1922b00 } + }, +/* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1923b00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1940b00 } + }, +/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1942b00 } + }, +/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1943b00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1960b00 } + }, +/* extz ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1962b00 } + }, +/* extz ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1963b00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1928b00 } + }, +/* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x192ab00 } + }, +/* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x192bb00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1948b00 } + }, +/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x194ab00 } + }, +/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x194bb00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192cb00 } + }, +/* extz ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192eb00 } + }, +/* extz ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192fb00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194cb00 } + }, +/* extz ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194eb00 } + }, +/* extz ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194fb00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196cb00 } + }, +/* extz ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196eb00 } + }, +/* extz ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196fb00 } + }, +/* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x1968b00 } + }, +/* extz ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x196ab00 } + }, +/* extz ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x196bb00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a80b00 } + }, +/* extz ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a82b00 } + }, +/* extz ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a83b00 } + }, +/* extz ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b83b00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a08b00 } + }, +/* extz ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a0ab00 } + }, +/* extz ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a0bb00 } + }, +/* extz ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b0bb00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a00b00 } + }, +/* extz ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a02b00 } + }, +/* extz ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a03b00 } + }, +/* extz ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b03b00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a20b00 } + }, +/* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a22b00 } + }, +/* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a23b00 } + }, +/* extz ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b23b00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a40b00 } + }, +/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a42b00 } + }, +/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a43b00 } + }, +/* extz ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b43b00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a60b00 } + }, +/* extz ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a62b00 } + }, +/* extz ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a63b00 } + }, +/* extz ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b63b00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a28b00 } + }, +/* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a2ab00 } + }, +/* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a2bb00 } + }, +/* extz ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b2bb00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a48b00 } + }, +/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a4ab00 } + }, +/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a4bb00 } + }, +/* extz ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b4bb00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2cb00 } + }, +/* extz ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2eb00 } + }, +/* extz ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2fb00 } + }, +/* extz ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b2fb00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4cb00 } + }, +/* extz ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4eb00 } + }, +/* extz ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4fb00 } + }, +/* extz ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b4fb00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6cb00 } + }, +/* extz ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6eb00 } + }, +/* extz ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6fb00 } + }, +/* extz ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1b6fb00 } + }, +/* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a68b00 } + }, +/* extz ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a6ab00 } + }, +/* extz ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a6bb00 } + }, +/* extz ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1b6bb00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b80b00 } + }, +/* extz ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b82b00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b08b00 } + }, +/* extz ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b0ab00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b00b00 } + }, +/* extz ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b02b00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b20b00 } + }, +/* extz ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b22b00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b40b00 } + }, +/* extz ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b42b00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b60b00 } + }, +/* extz ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b62b00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b28b00 } + }, +/* extz ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b2ab00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b48b00 } + }, +/* extz ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b4ab00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b2cb00 } + }, +/* extz ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b2eb00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b4cb00 } + }, +/* extz ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b4eb00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI, { 0x1b6cb00 } + }, +/* extz ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI, { 0x1b6eb00 } + }, +/* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI, { 0x1b68b00 } + }, +/* extz ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI, { 0x1b6ab00 } + }, +/* extz $Src32RnPrefixedQI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1c80b } + }, +/* extz [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1880b } + }, +/* extz $Src32RnPrefixedQI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1c08b } + }, +/* extz [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1808b } + }, +/* extz $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1c00b } + }, +/* extz [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1800b } + }, +/* extz $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c20b00 } + }, +/* extz [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI, { 0x1820b00 } + }, +/* extz $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c40b00 } + }, +/* extz [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI, { 0x1840b00 } + }, +/* extz $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c60b00 } + }, +/* extz [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI, { 0x1860b00 } + }, +/* extz $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c28b00 } + }, +/* extz [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1828b00 } + }, +/* extz $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c48b00 } + }, +/* extz [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1848b00 } + }, +/* extz $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c2cb00 } + }, +/* extz [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI, { 0x182cb00 } + }, +/* extz $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c4cb00 } + }, +/* extz [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI, { 0x184cb00 } + }, +/* extz $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI, { 0x1c6cb00 } + }, +/* extz [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI, { 0x186cb00 } + }, +/* extz $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI, { 0x1c68b00 } + }, +/* extz [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI, { 0x1868b00 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1980700 } + }, +/* exts.b ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1982700 } + }, +/* exts.b ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1983700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1908700 } + }, +/* exts.b ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x190a700 } + }, +/* exts.b ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x190b700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1900700 } + }, +/* exts.b ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1902700 } + }, +/* exts.b ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1903700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1920700 } + }, +/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1922700 } + }, +/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_HI, { 0x1923700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1940700 } + }, +/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1942700 } + }, +/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_HI, { 0x1943700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1960700 } + }, +/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1962700 } + }, +/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_HI, { 0x1963700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1928700 } + }, +/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x192a700 } + }, +/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_HI, { 0x192b700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1948700 } + }, +/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x194a700 } + }, +/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_HI, { 0x194b700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192c700 } + }, +/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192e700 } + }, +/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_HI, { 0x192f700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194c700 } + }, +/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194e700 } + }, +/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_HI, { 0x194f700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196c700 } + }, +/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196e700 } + }, +/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_HI, { 0x196f700 } + }, +/* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x1968700 } + }, +/* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x196a700 } + }, +/* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_extz32_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_HI, { 0x196b700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a80700 } + }, +/* exts.b ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a82700 } + }, +/* exts.b ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1a83700 } + }, +/* exts.b ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b83700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a08700 } + }, +/* exts.b ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a0a700 } + }, +/* exts.b ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1a0b700 } + }, +/* exts.b ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b0b700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a00700 } + }, +/* exts.b ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a02700 } + }, +/* exts.b ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1a03700 } + }, +/* exts.b ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b03700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a20700 } + }, +/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a22700 } + }, +/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a23700 } + }, +/* exts.b ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b23700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a40700 } + }, +/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a42700 } + }, +/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a43700 } + }, +/* exts.b ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b43700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a60700 } + }, +/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a62700 } + }, +/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a63700 } + }, +/* exts.b ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b63700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a28700 } + }, +/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a2a700 } + }, +/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a2b700 } + }, +/* exts.b ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b2b700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a48700 } + }, +/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a4a700 } + }, +/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a4b700 } + }, +/* exts.b ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b4b700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2c700 } + }, +/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2e700 } + }, +/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a2f700 } + }, +/* exts.b ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b2f700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4c700 } + }, +/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4e700 } + }, +/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a4f700 } + }, +/* exts.b ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b4f700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6c700 } + }, +/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6e700 } + }, +/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1a6f700 } + }, +/* exts.b ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_HI, { 0x1b6f700 } + }, +/* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a68700 } + }, +/* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a6a700 } + }, +/* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1a6b700 } + }, +/* exts.b ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_extz32_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_HI, { 0x1b6b700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b80700 } + }, +/* exts.b ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1b82700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b08700 } + }, +/* exts.b ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1b0a700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b00700 } + }, +/* exts.b ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1b02700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b20700 } + }, +/* exts.b ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b22700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b40700 } + }, +/* exts.b ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b42700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b60700 } + }, +/* exts.b ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b62700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b28700 } + }, +/* exts.b ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b2a700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b48700 } + }, +/* exts.b ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b4a700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b2c700 } + }, +/* exts.b ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b2e700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b4c700 } + }, +/* exts.b ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b4e700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI, { 0x1b6c700 } + }, +/* exts.b ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_HI, { 0x1b6e700 } + }, +/* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI, { 0x1b68700 } + }, +/* exts.b ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_extz32_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_HI, { 0x1b6a700 } + }, +/* exts.b $Src32RnPrefixedQI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x1c807 } + }, +/* exts.b [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_HI, { 0x18807 } + }, +/* exts.b $Src32RnPrefixedQI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x1c087 } + }, +/* exts.b [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_HI, { 0x18087 } + }, +/* exts.b $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x1c007 } + }, +/* exts.b [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_HI, { 0x18007 } + }, +/* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c20700 } + }, +/* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_HI, { 0x1820700 } + }, +/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c40700 } + }, +/* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_HI, { 0x1840700 } + }, +/* exts.b $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c60700 } + }, +/* exts.b [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_HI, { 0x1860700 } + }, +/* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c28700 } + }, +/* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1828700 } + }, +/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c48700 } + }, +/* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1848700 } + }, +/* exts.b $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c2c700 } + }, +/* exts.b [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_HI, { 0x182c700 } + }, +/* exts.b $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c4c700 } + }, +/* exts.b [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_HI, { 0x184c700 } + }, +/* exts.b $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI, { 0x1c6c700 } + }, +/* exts.b [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_HI, { 0x186c700 } + }, +/* exts.b $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI, { 0x1c68700 } + }, +/* exts.b [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_extz32_basic_ExtPrefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_HI, { 0x1868700 } + }, +/* exts.w $Dst32RnExtUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNEXTUNPREFIXEDHI), 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_Rn_direct_ExtUnprefixed_HI, { 0xc99e } + }, +/* exts.w $Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xc19e } + }, +/* exts.w [$Dst32AnExtUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_indirect_ExtUnprefixed_HI, { 0xc11e } + }, +/* exts.w ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_An_relative_ExtUnprefixed_HI, { 0xc31e00 } + }, +/* exts.w ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_An_relative_ExtUnprefixed_HI, { 0xc51e0000 } + }, +/* exts.w ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_24_An_relative_ExtUnprefixed_HI, { 0xc71e0000 } + }, +/* exts.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_SB_relative_ExtUnprefixed_HI, { 0xc39e00 } + }, +/* exts.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_SB_relative_ExtUnprefixed_HI, { 0xc59e0000 } + }, +/* exts.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_8_FB_relative_ExtUnprefixed_HI, { 0xc3de00 } + }, +/* exts.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_FB_relative_ExtUnprefixed_HI, { 0xc5de0000 } + }, +/* exts.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_16_absolute_ExtUnprefixed_HI, { 0xc7de0000 } + }, +/* exts.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_16_24_absolute_ExtUnprefixed_HI, { 0xc79e0000 } + }, +/* exts.b $Dst32RnExtUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNEXTUNPREFIXEDQI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_Rn_direct_ExtUnprefixed_QI, { 0xc89e } + }, +/* exts.b $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc09e } + }, +/* exts.b [$Dst32AnExtUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_indirect_ExtUnprefixed_QI, { 0xc01e } + }, +/* exts.b ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_An_relative_ExtUnprefixed_QI, { 0xc21e00 } + }, +/* exts.b ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_An_relative_ExtUnprefixed_QI, { 0xc41e0000 } + }, +/* exts.b ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANEXTUNPREFIXED), ']', 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_24_An_relative_ExtUnprefixed_QI, { 0xc61e0000 } + }, +/* exts.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_SB_relative_ExtUnprefixed_QI, { 0xc29e00 } + }, +/* exts.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_SB_relative_ExtUnprefixed_QI, { 0xc49e0000 } + }, +/* exts.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_8_FB_relative_ExtUnprefixed_QI, { 0xc2de00 } + }, +/* exts.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_FB_relative_ExtUnprefixed_QI, { 0xc4de0000 } + }, +/* exts.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_16_absolute_ExtUnprefixed_QI, { 0xc6de0000 } + }, +/* exts.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_16_24_absolute_ExtUnprefixed_QI, { 0xc69e0000 } + }, +/* exts.b $Dst16RnExtQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNEXTQI), 0 } }, + & ifmt_exts16_b_16_Ext_dst16_Rn_direct_Ext_QI, { 0x7c60 } + }, +/* exts.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_exts16_b_16_Ext_dst16_An_indirect_Ext_QI, { 0x7c66 } + }, +/* exts.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_exts16_b_16_Ext_dst16_16_8_An_relative_Ext_QI, { 0x7c6800 } + }, +/* exts.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_exts16_b_16_Ext_dst16_16_16_An_relative_Ext_QI, { 0x7c6c0000 } + }, +/* exts.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_exts16_b_16_Ext_dst16_16_8_SB_relative_Ext_QI, { 0x7c6a00 } + }, +/* exts.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_exts16_b_16_Ext_dst16_16_16_SB_relative_Ext_QI, { 0x7c6e0000 } + }, +/* exts.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_exts16_b_16_Ext_dst16_16_8_FB_relative_Ext_QI, { 0x7c6b00 } + }, +/* exts.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_exts16_b_16_Ext_dst16_16_16_absolute_Ext_QI, { 0x7c6f0000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990900 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992900 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993900 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918900 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a900 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b900 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910900 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912900 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913900 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93090000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93290000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93390000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95090000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95290000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95390000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97090000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97290000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97390000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93890000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a90000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b90000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95890000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a90000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b90000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c90000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e90000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f90000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c90000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e90000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f90000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c90000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e90000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f90000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97890000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a90000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b90000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9090000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9290000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9390000 } + }, +/* xor.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9390000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1890000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a90000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b90000 } + }, +/* xor.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b90000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1090000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1290000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1390000 } + }, +/* xor.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1390000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3090000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3290000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3390000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3390000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5090000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5290000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5390000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5390000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7090000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7290000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7390000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7390000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3890000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a90000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b90000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b90000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5890000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a90000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b90000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b90000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c90000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e90000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f90000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f90000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c90000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e90000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f90000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f90000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c90000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e90000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f90000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f90000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7890000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a90000 } + }, +/* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b90000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b90000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9090000 } + }, +/* xor.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9290000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1890000 } + }, +/* xor.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a90000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1090000 } + }, +/* xor.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1290000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3090000 } + }, +/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3290000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5090000 } + }, +/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5290000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7090000 } + }, +/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7290000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3890000 } + }, +/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a90000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5890000 } + }, +/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a90000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c90000 } + }, +/* xor.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e90000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c90000 } + }, +/* xor.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e90000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c90000 } + }, +/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e90000 } + }, +/* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7890000 } + }, +/* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a90000 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc909 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8929 } + }, +/* xor.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8909 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc189 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a9 } + }, +/* xor.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8189 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc109 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8129 } + }, +/* xor.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8109 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30900 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832900 } + }, +/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830900 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5090000 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85290000 } + }, +/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85090000 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7090000 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87290000 } + }, +/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87090000 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38900 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a900 } + }, +/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838900 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5890000 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a90000 } + }, +/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85890000 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c900 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e900 } + }, +/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c900 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c90000 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e90000 } + }, +/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c90000 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c90000 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e90000 } + }, +/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c90000 } + }, +/* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7890000 } + }, +/* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a90000 } + }, +/* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87890000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980900 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982900 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983900 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908900 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a900 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b900 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900900 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902900 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903900 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92090000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92290000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92390000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94090000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94290000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94390000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96090000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96290000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96390000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92890000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a90000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b90000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94890000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a90000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b90000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c90000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e90000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f90000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c90000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e90000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f90000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c90000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e90000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f90000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96890000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a90000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b90000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8090000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8290000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8390000 } + }, +/* xor.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8390000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0890000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a90000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b90000 } + }, +/* xor.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b90000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0090000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0290000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0390000 } + }, +/* xor.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0390000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2090000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2290000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2390000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2390000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4090000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4290000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4390000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4390000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6090000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6290000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6390000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6390000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2890000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a90000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b90000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b90000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4890000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a90000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b90000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b90000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c90000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e90000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f90000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f90000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c90000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e90000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f90000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f90000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c90000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e90000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f90000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f90000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6890000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a90000 } + }, +/* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b90000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b90000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8090000 } + }, +/* xor.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8290000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0890000 } + }, +/* xor.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a90000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0090000 } + }, +/* xor.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0290000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2090000 } + }, +/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2290000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4090000 } + }, +/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4290000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6090000 } + }, +/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6290000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2890000 } + }, +/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a90000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4890000 } + }, +/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a90000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c90000 } + }, +/* xor.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e90000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c90000 } + }, +/* xor.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e90000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c90000 } + }, +/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e90000 } + }, +/* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6890000 } + }, +/* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a90000 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc809 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8829 } + }, +/* xor.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8809 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc089 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a9 } + }, +/* xor.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8089 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc009 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8029 } + }, +/* xor.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8009 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20900 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822900 } + }, +/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820900 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4090000 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84290000 } + }, +/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84090000 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6090000 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86290000 } + }, +/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86090000 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28900 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a900 } + }, +/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828900 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4890000 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a90000 } + }, +/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84890000 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c900 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e900 } + }, +/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c900 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c90000 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e90000 } + }, +/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c90000 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c90000 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e90000 } + }, +/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c90000 } + }, +/* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6890000 } + }, +/* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a90000 } + }, +/* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86890000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x898000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x89a000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x89b000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x898400 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x89a400 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x89b400 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x898600 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x89a600 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x89b600 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x89880000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x89a80000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x89b80000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x898c0000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x89ac0000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x89bc0000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x898a0000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x89aa0000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x89ba0000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x898e0000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x89ae0000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x89be0000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x898b0000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x89ab0000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x89bb0000 } + }, +/* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x898f0000 } + }, +/* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x89af0000 } + }, +/* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x89bf0000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x89c00000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x89e00000 } + }, +/* xor.w${G} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x89f00000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x89c40000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x89e40000 } + }, +/* xor.w${G} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x89f40000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x89c60000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x89e60000 } + }, +/* xor.w${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x89f60000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x89c80000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x89e80000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x89f80000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x89cc0000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x89ec0000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x89fc0000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x89ca0000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x89ea0000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x89fa0000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x89ce0000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x89ee0000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x89fe0000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x89cb0000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x89eb0000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x89fb0000 } + }, +/* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x89cf0000 } + }, +/* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x89ef0000 } + }, +/* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x89ff0000 } + }, +/* xor.w${G} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x8900 } + }, +/* xor.w${G} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x8940 } + }, +/* xor.w${G} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x8960 } + }, +/* xor.w${G} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x8904 } + }, +/* xor.w${G} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x8944 } + }, +/* xor.w${G} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x8964 } + }, +/* xor.w${G} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x8906 } + }, +/* xor.w${G} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x8946 } + }, +/* xor.w${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x8966 } + }, +/* xor.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x890800 } + }, +/* xor.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x894800 } + }, +/* xor.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x896800 } + }, +/* xor.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x890c0000 } + }, +/* xor.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x894c0000 } + }, +/* xor.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x896c0000 } + }, +/* xor.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x890a00 } + }, +/* xor.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x894a00 } + }, +/* xor.w${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x896a00 } + }, +/* xor.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x890e0000 } + }, +/* xor.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x894e0000 } + }, +/* xor.w${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x896e0000 } + }, +/* xor.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x890b00 } + }, +/* xor.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x894b00 } + }, +/* xor.w${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x896b00 } + }, +/* xor.w${G} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x890f0000 } + }, +/* xor.w${G} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x894f0000 } + }, +/* xor.w${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x896f0000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x888000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x88a000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x88b000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x888400 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x88a400 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x88b400 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x888600 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x88a600 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x88b600 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x88880000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x88a80000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x88b80000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x888c0000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x88ac0000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x88bc0000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x888a0000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x88aa0000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x88ba0000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x888e0000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x88ae0000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x88be0000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x888b0000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x88ab0000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x88bb0000 } + }, +/* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x888f0000 } + }, +/* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x88af0000 } + }, +/* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x88bf0000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x88c00000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x88e00000 } + }, +/* xor.b${G} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x88f00000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x88c40000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x88e40000 } + }, +/* xor.b${G} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x88f40000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x88c60000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x88e60000 } + }, +/* xor.b${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x88f60000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x88c80000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x88e80000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x88f80000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x88cc0000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x88ec0000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x88fc0000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x88ca0000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x88ea0000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x88fa0000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x88ce0000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x88ee0000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x88fe0000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x88cb0000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x88eb0000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x88fb0000 } + }, +/* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x88cf0000 } + }, +/* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x88ef0000 } + }, +/* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x88ff0000 } + }, +/* xor.b${G} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x8800 } + }, +/* xor.b${G} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x8840 } + }, +/* xor.b${G} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x8860 } + }, +/* xor.b${G} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x8804 } + }, +/* xor.b${G} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x8844 } + }, +/* xor.b${G} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x8864 } + }, +/* xor.b${G} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x8806 } + }, +/* xor.b${G} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x8846 } + }, +/* xor.b${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x8866 } + }, +/* xor.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x880800 } + }, +/* xor.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x884800 } + }, +/* xor.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x886800 } + }, +/* xor.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x880c0000 } + }, +/* xor.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x884c0000 } + }, +/* xor.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x886c0000 } + }, +/* xor.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x880a00 } + }, +/* xor.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x884a00 } + }, +/* xor.b${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x886a00 } + }, +/* xor.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x880e0000 } + }, +/* xor.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x884e0000 } + }, +/* xor.b${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x886e0000 } + }, +/* xor.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x880b00 } + }, +/* xor.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x884b00 } + }, +/* xor.b${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x886b00 } + }, +/* xor.b${G} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x880f0000 } + }, +/* xor.b${G} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x884f0000 } + }, +/* xor.b${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x886f0000 } + }, +/* xor.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x990e0000 } + }, +/* xor.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x918e0000 } + }, +/* xor.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x910e0000 } + }, +/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x930e0000 } + }, +/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x938e0000 } + }, +/* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93ce0000 } + }, +/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x950e0000 } + }, +/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x958e0000 } + }, +/* xor.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95ce0000 } + }, +/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97ce0000 } + }, +/* xor.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x970e0000 } + }, +/* xor.w${G} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x978e0000 } + }, +/* xor.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x980e00 } + }, +/* xor.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x908e00 } + }, +/* xor.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x900e00 } + }, +/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x920e0000 } + }, +/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x928e0000 } + }, +/* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92ce0000 } + }, +/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x940e0000 } + }, +/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x948e0000 } + }, +/* xor.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94ce0000 } + }, +/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96ce0000 } + }, +/* xor.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x960e0000 } + }, +/* xor.b${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x968e0000 } + }, +/* xor.w${G} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77100000 } + }, +/* xor.w${G} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77140000 } + }, +/* xor.w${G} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77160000 } + }, +/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77180000 } + }, +/* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x771a0000 } + }, +/* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x771b0000 } + }, +/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x771c0000 } + }, +/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x771e0000 } + }, +/* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x771f0000 } + }, +/* xor.b${G} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x761000 } + }, +/* xor.b${G} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x761400 } + }, +/* xor.b${G} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x761600 } + }, +/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76180000 } + }, +/* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x761a0000 } + }, +/* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x761b0000 } + }, +/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x761c0000 } + }, +/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x761e0000 } + }, +/* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x761f0000 } + }, +/* xchg.w r3,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd90d } + }, +/* xchg.w r3,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd18d } + }, +/* xchg.w r3,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd10d } + }, +/* xchg.w r3,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30d00 } + }, +/* xchg.w r3,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd50d0000 } + }, +/* xchg.w r3,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd70d0000 } + }, +/* xchg.w r3,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38d00 } + }, +/* xchg.w r3,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd58d0000 } + }, +/* xchg.w r3,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3cd00 } + }, +/* xchg.w r3,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5cd0000 } + }, +/* xchg.w r3,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7cd0000 } + }, +/* xchg.w r3,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd78d0000 } + }, +/* xchg.w r2,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd90c } + }, +/* xchg.w r2,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd18c } + }, +/* xchg.w r2,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd10c } + }, +/* xchg.w r2,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30c00 } + }, +/* xchg.w r2,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd50c0000 } + }, +/* xchg.w r2,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd70c0000 } + }, +/* xchg.w r2,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38c00 } + }, +/* xchg.w r2,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd58c0000 } + }, +/* xchg.w r2,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3cc00 } + }, +/* xchg.w r2,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5cc0000 } + }, +/* xchg.w r2,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7cc0000 } + }, +/* xchg.w r2,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd78c0000 } + }, +/* xchg.w a1,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd90b } + }, +/* xchg.w a1,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd18b } + }, +/* xchg.w a1,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd10b } + }, +/* xchg.w a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30b00 } + }, +/* xchg.w a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd50b0000 } + }, +/* xchg.w a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd70b0000 } + }, +/* xchg.w a1,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38b00 } + }, +/* xchg.w a1,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd58b0000 } + }, +/* xchg.w a1,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3cb00 } + }, +/* xchg.w a1,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5cb0000 } + }, +/* xchg.w a1,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7cb0000 } + }, +/* xchg.w a1,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd78b0000 } + }, +/* xchg.w a0,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd90a } + }, +/* xchg.w a0,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd18a } + }, +/* xchg.w a0,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd10a } + }, +/* xchg.w a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30a00 } + }, +/* xchg.w a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd50a0000 } + }, +/* xchg.w a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd70a0000 } + }, +/* xchg.w a0,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38a00 } + }, +/* xchg.w a0,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd58a0000 } + }, +/* xchg.w a0,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3ca00 } + }, +/* xchg.w a0,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5ca0000 } + }, +/* xchg.w a0,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7ca0000 } + }, +/* xchg.w a0,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd78a0000 } + }, +/* xchg.w r1,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd909 } + }, +/* xchg.w r1,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd189 } + }, +/* xchg.w r1,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd109 } + }, +/* xchg.w r1,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30900 } + }, +/* xchg.w r1,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd5090000 } + }, +/* xchg.w r1,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd7090000 } + }, +/* xchg.w r1,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38900 } + }, +/* xchg.w r1,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd5890000 } + }, +/* xchg.w r1,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3c900 } + }, +/* xchg.w r1,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5c90000 } + }, +/* xchg.w r1,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7c90000 } + }, +/* xchg.w r1,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd7890000 } + }, +/* xchg.w r0,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_Rn_direct_Unprefixed_HI, { 0xd908 } + }, +/* xchg.w r0,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xchg32w_r3_dst32_An_direct_Unprefixed_HI, { 0xd188 } + }, +/* xchg.w r0,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_An_indirect_Unprefixed_HI, { 0xd108 } + }, +/* xchg.w r0,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_An_relative_Unprefixed_HI, { 0xd30800 } + }, +/* xchg.w r0,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_An_relative_Unprefixed_HI, { 0xd5080000 } + }, +/* xchg.w r0,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_An_relative_Unprefixed_HI, { 0xd7080000 } + }, +/* xchg.w r0,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd38800 } + }, +/* xchg.w r0,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd5880000 } + }, +/* xchg.w r0,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3c800 } + }, +/* xchg.w r0,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5c80000 } + }, +/* xchg.w r0,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32w_r3_dst32_16_16_absolute_Unprefixed_HI, { 0xd7c80000 } + }, +/* xchg.w r0,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32w_r3_dst32_16_24_absolute_Unprefixed_HI, { 0xd7880000 } + }, +/* xchg.b r1h,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd80d } + }, +/* xchg.b r1h,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd08d } + }, +/* xchg.b r1h,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd00d } + }, +/* xchg.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20d00 } + }, +/* xchg.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd40d0000 } + }, +/* xchg.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd60d0000 } + }, +/* xchg.b r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28d00 } + }, +/* xchg.b r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd48d0000 } + }, +/* xchg.b r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2cd00 } + }, +/* xchg.b r1h,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4cd0000 } + }, +/* xchg.b r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6cd0000 } + }, +/* xchg.b r1h,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd68d0000 } + }, +/* xchg.b r0h,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd80c } + }, +/* xchg.b r0h,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd08c } + }, +/* xchg.b r0h,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd00c } + }, +/* xchg.b r0h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20c00 } + }, +/* xchg.b r0h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd40c0000 } + }, +/* xchg.b r0h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd60c0000 } + }, +/* xchg.b r0h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28c00 } + }, +/* xchg.b r0h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd48c0000 } + }, +/* xchg.b r0h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2cc00 } + }, +/* xchg.b r0h,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4cc0000 } + }, +/* xchg.b r0h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6cc0000 } + }, +/* xchg.b r0h,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd68c0000 } + }, +/* xchg.b a1,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd80b } + }, +/* xchg.b a1,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd08b } + }, +/* xchg.b a1,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd00b } + }, +/* xchg.b a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20b00 } + }, +/* xchg.b a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd40b0000 } + }, +/* xchg.b a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd60b0000 } + }, +/* xchg.b a1,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28b00 } + }, +/* xchg.b a1,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd48b0000 } + }, +/* xchg.b a1,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2cb00 } + }, +/* xchg.b a1,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4cb0000 } + }, +/* xchg.b a1,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6cb0000 } + }, +/* xchg.b a1,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '1', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd68b0000 } + }, +/* xchg.b a0,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd80a } + }, +/* xchg.b a0,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd08a } + }, +/* xchg.b a0,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd00a } + }, +/* xchg.b a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20a00 } + }, +/* xchg.b a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd40a0000 } + }, +/* xchg.b a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd60a0000 } + }, +/* xchg.b a0,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28a00 } + }, +/* xchg.b a0,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd48a0000 } + }, +/* xchg.b a0,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2ca00 } + }, +/* xchg.b a0,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4ca0000 } + }, +/* xchg.b a0,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6ca0000 } + }, +/* xchg.b a0,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'a', '0', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd68a0000 } + }, +/* xchg.b r1l,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd809 } + }, +/* xchg.b r1l,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd089 } + }, +/* xchg.b r1l,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd009 } + }, +/* xchg.b r1l,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20900 } + }, +/* xchg.b r1l,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd4090000 } + }, +/* xchg.b r1l,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd6090000 } + }, +/* xchg.b r1l,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28900 } + }, +/* xchg.b r1l,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd4890000 } + }, +/* xchg.b r1l,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2c900 } + }, +/* xchg.b r1l,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4c90000 } + }, +/* xchg.b r1l,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6c90000 } + }, +/* xchg.b r1l,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd6890000 } + }, +/* xchg.b r0l,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_Rn_direct_Unprefixed_QI, { 0xd808 } + }, +/* xchg.b r0l,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xchg32b_r1h_dst32_An_direct_Unprefixed_QI, { 0xd088 } + }, +/* xchg.b r0l,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_An_indirect_Unprefixed_QI, { 0xd008 } + }, +/* xchg.b r0l,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_An_relative_Unprefixed_QI, { 0xd20800 } + }, +/* xchg.b r0l,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_An_relative_Unprefixed_QI, { 0xd4080000 } + }, +/* xchg.b r0l,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_An_relative_Unprefixed_QI, { 0xd6080000 } + }, +/* xchg.b r0l,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_SB_relative_Unprefixed_QI, { 0xd28800 } + }, +/* xchg.b r0l,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_SB_relative_Unprefixed_QI, { 0xd4880000 } + }, +/* xchg.b r0l,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_8_FB_relative_Unprefixed_QI, { 0xd2c800 } + }, +/* xchg.b r0l,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_FB_relative_Unprefixed_QI, { 0xd4c80000 } + }, +/* xchg.b r0l,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_16_absolute_Unprefixed_QI, { 0xd6c80000 } + }, +/* xchg.b r0l,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xchg32b_r1h_dst32_16_24_absolute_Unprefixed_QI, { 0xd6880000 } + }, +/* xchg.w r3,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DST16RNHI), 0 } }, + & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b30 } + }, +/* xchg.w r3,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DST16ANHI), 0 } }, + & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b34 } + }, +/* xchg.w r3,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b36 } + }, +/* xchg.w r3,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b3800 } + }, +/* xchg.w r3,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b3c0000 } + }, +/* xchg.w r3,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b3a00 } + }, +/* xchg.w r3,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b3e0000 } + }, +/* xchg.w r3,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b3b00 } + }, +/* xchg.w r3,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '3', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b3f0000 } + }, +/* xchg.w r2,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DST16RNHI), 0 } }, + & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b20 } + }, +/* xchg.w r2,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DST16ANHI), 0 } }, + & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b24 } + }, +/* xchg.w r2,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b26 } + }, +/* xchg.w r2,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b2800 } + }, +/* xchg.w r2,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b2c0000 } + }, +/* xchg.w r2,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b2a00 } + }, +/* xchg.w r2,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b2e0000 } + }, +/* xchg.w r2,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b2b00 } + }, +/* xchg.w r2,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '2', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b2f0000 } + }, +/* xchg.w r1,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DST16RNHI), 0 } }, + & ifmt_xchg16w_r3_dst16_Rn_direct_HI, { 0x7b10 } + }, +/* xchg.w r1,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DST16ANHI), 0 } }, + & ifmt_xchg16w_r3_dst16_An_direct_HI, { 0x7b14 } + }, +/* xchg.w r1,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_An_indirect_HI, { 0x7b16 } + }, +/* xchg.w r1,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_An_relative_HI, { 0x7b1800 } + }, +/* xchg.w r1,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_An_relative_HI, { 0x7b1c0000 } + }, +/* xchg.w r1,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_SB_relative_HI, { 0x7b1a00 } + }, +/* xchg.w r1,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_SB_relative_HI, { 0x7b1e0000 } + }, +/* xchg.w r1,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg16w_r3_dst16_16_8_FB_relative_HI, { 0x7b1b00 } + }, +/* xchg.w r1,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg16w_r3_dst16_16_16_absolute_HI, { 0x7b1f0000 } + }, +/* xchg.w r0,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DST16RNQI), 0 } }, + & ifmt_xchg16w_r0_dst16_Rn_direct_QI, { 0x7b00 } + }, +/* xchg.w r0,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DST16ANQI), 0 } }, + & ifmt_xchg16w_r0_dst16_An_direct_QI, { 0x7b04 } + }, +/* xchg.w r0,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r0_dst16_An_indirect_QI, { 0x7b06 } + }, +/* xchg.w r0,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_8_An_relative_QI, { 0x7b0800 } + }, +/* xchg.w r0,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_16_An_relative_QI, { 0x7b0c0000 } + }, +/* xchg.w r0,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_8_SB_relative_QI, { 0x7b0a00 } + }, +/* xchg.w r0,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_16_SB_relative_QI, { 0x7b0e0000 } + }, +/* xchg.w r0,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_8_FB_relative_QI, { 0x7b0b00 } + }, +/* xchg.w r0,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg16w_r0_dst16_16_16_absolute_QI, { 0x7b0f0000 } + }, +/* xchg.b r1h,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } }, + & ifmt_xchg16w_r0_dst16_Rn_direct_QI, { 0x7a30 } + }, +/* xchg.b r1h,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } }, + & ifmt_xchg16w_r0_dst16_An_direct_QI, { 0x7a34 } + }, +/* xchg.b r1h,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r0_dst16_An_indirect_QI, { 0x7a36 } + }, +/* xchg.b r1h,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_8_An_relative_QI, { 0x7a3800 } + }, +/* xchg.b r1h,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_16_An_relative_QI, { 0x7a3c0000 } + }, +/* xchg.b r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_8_SB_relative_QI, { 0x7a3a00 } + }, +/* xchg.b r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_16_SB_relative_QI, { 0x7a3e0000 } + }, +/* xchg.b r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_8_FB_relative_QI, { 0x7a3b00 } + }, +/* xchg.b r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg16w_r0_dst16_16_16_absolute_QI, { 0x7a3f0000 } + }, +/* xchg.b r1l,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST16RNQI), 0 } }, + & ifmt_xchg16w_r0_dst16_Rn_direct_QI, { 0x7a20 } + }, +/* xchg.b r1l,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DST16ANQI), 0 } }, + & ifmt_xchg16w_r0_dst16_An_direct_QI, { 0x7a24 } + }, +/* xchg.b r1l,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r0_dst16_An_indirect_QI, { 0x7a26 } + }, +/* xchg.b r1l,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_8_An_relative_QI, { 0x7a2800 } + }, +/* xchg.b r1l,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_16_An_relative_QI, { 0x7a2c0000 } + }, +/* xchg.b r1l,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_8_SB_relative_QI, { 0x7a2a00 } + }, +/* xchg.b r1l,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_16_SB_relative_QI, { 0x7a2e0000 } + }, +/* xchg.b r1l,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_8_FB_relative_QI, { 0x7a2b00 } + }, +/* xchg.b r1l,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'l', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg16w_r0_dst16_16_16_absolute_QI, { 0x7a2f0000 } + }, +/* xchg.b r0h,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST16RNQI), 0 } }, + & ifmt_xchg16w_r0_dst16_Rn_direct_QI, { 0x7a10 } + }, +/* xchg.b r0h,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DST16ANQI), 0 } }, + & ifmt_xchg16w_r0_dst16_An_direct_QI, { 0x7a14 } + }, +/* xchg.b r0h,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r0_dst16_An_indirect_QI, { 0x7a16 } + }, +/* xchg.b r0h,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_8_An_relative_QI, { 0x7a1800 } + }, +/* xchg.b r0h,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_16_An_relative_QI, { 0x7a1c0000 } + }, +/* xchg.b r0h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_8_SB_relative_QI, { 0x7a1a00 } + }, +/* xchg.b r0h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_16_SB_relative_QI, { 0x7a1e0000 } + }, +/* xchg.b r0h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_8_FB_relative_QI, { 0x7a1b00 } + }, +/* xchg.b r0h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg16w_r0_dst16_16_16_absolute_QI, { 0x7a1f0000 } + }, +/* xchg.b r0l,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } }, + & ifmt_xchg16w_r0_dst16_Rn_direct_QI, { 0x7a00 } + }, +/* xchg.b r0l,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } }, + & ifmt_xchg16w_r0_dst16_An_direct_QI, { 0x7a04 } + }, +/* xchg.b r0l,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r0_dst16_An_indirect_QI, { 0x7a06 } + }, +/* xchg.b r0l,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_8_An_relative_QI, { 0x7a0800 } + }, +/* xchg.b r0l,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_16_An_relative_QI, { 0x7a0c0000 } + }, +/* xchg.b r0l,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_8_SB_relative_QI, { 0x7a0a00 } + }, +/* xchg.b r0l,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_16_SB_relative_QI, { 0x7a0e0000 } + }, +/* xchg.b r0l,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xchg16w_r0_dst16_16_8_FB_relative_QI, { 0x7a0b00 } + }, +/* xchg.b r0l,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xchg16w_r0_dst16_16_16_absolute_QI, { 0x7a0f0000 } + }, +/* tst.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2d000000 } + }, +/* tst.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3d000000 } + }, +/* tst.w${S} #${Imm-24-HI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x1d000000 } + }, +/* tst.w${S} #${Imm-8-HI},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } }, + & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0xd0000 } + }, +/* tst.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2c0000 } + }, +/* tst.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3c0000 } + }, +/* tst.b${S} #${Imm-24-QI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x1c000000 } + }, +/* tst.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0xc00 } + }, +/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990900 } + }, +/* tst.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992900 } + }, +/* tst.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993900 } + }, +/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918900 } + }, +/* tst.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a900 } + }, +/* tst.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b900 } + }, +/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910900 } + }, +/* tst.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912900 } + }, +/* tst.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913900 } + }, +/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930900 } + }, +/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932900 } + }, +/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933900 } + }, +/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950900 } + }, +/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952900 } + }, +/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953900 } + }, +/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970900 } + }, +/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972900 } + }, +/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973900 } + }, +/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938900 } + }, +/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a900 } + }, +/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b900 } + }, +/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958900 } + }, +/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a900 } + }, +/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b900 } + }, +/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c900 } + }, +/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e900 } + }, +/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f900 } + }, +/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c900 } + }, +/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e900 } + }, +/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f900 } + }, +/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c900 } + }, +/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e900 } + }, +/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f900 } + }, +/* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978900 } + }, +/* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a900 } + }, +/* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b900 } + }, +/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90900 } + }, +/* tst.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92900 } + }, +/* tst.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93900 } + }, +/* tst.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93900 } + }, +/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18900 } + }, +/* tst.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a900 } + }, +/* tst.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b900 } + }, +/* tst.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b900 } + }, +/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10900 } + }, +/* tst.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12900 } + }, +/* tst.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13900 } + }, +/* tst.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13900 } + }, +/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30900 } + }, +/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32900 } + }, +/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33900 } + }, +/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33900 } + }, +/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50900 } + }, +/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52900 } + }, +/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53900 } + }, +/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53900 } + }, +/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70900 } + }, +/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72900 } + }, +/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73900 } + }, +/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73900 } + }, +/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38900 } + }, +/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a900 } + }, +/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b900 } + }, +/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b900 } + }, +/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58900 } + }, +/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a900 } + }, +/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b900 } + }, +/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b900 } + }, +/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c900 } + }, +/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e900 } + }, +/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f900 } + }, +/* tst.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f900 } + }, +/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c900 } + }, +/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e900 } + }, +/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f900 } + }, +/* tst.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f900 } + }, +/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c900 } + }, +/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e900 } + }, +/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f900 } + }, +/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f900 } + }, +/* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78900 } + }, +/* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a900 } + }, +/* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b900 } + }, +/* tst.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b900 } + }, +/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90900 } + }, +/* tst.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92900 } + }, +/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18900 } + }, +/* tst.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a900 } + }, +/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10900 } + }, +/* tst.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12900 } + }, +/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30900 } + }, +/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32900 } + }, +/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50900 } + }, +/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52900 } + }, +/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70900 } + }, +/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72900 } + }, +/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38900 } + }, +/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a900 } + }, +/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58900 } + }, +/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a900 } + }, +/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c900 } + }, +/* tst.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e900 } + }, +/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c900 } + }, +/* tst.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e900 } + }, +/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c900 } + }, +/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e900 } + }, +/* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78900 } + }, +/* tst.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a900 } + }, +/* tst.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c909 } + }, +/* tst.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18929 } + }, +/* tst.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18909 } + }, +/* tst.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c189 } + }, +/* tst.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a9 } + }, +/* tst.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18189 } + }, +/* tst.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c109 } + }, +/* tst.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18129 } + }, +/* tst.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18109 } + }, +/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30900 } + }, +/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832900 } + }, +/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830900 } + }, +/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50900 } + }, +/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852900 } + }, +/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850900 } + }, +/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70900 } + }, +/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872900 } + }, +/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870900 } + }, +/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38900 } + }, +/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a900 } + }, +/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838900 } + }, +/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58900 } + }, +/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a900 } + }, +/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858900 } + }, +/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c900 } + }, +/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e900 } + }, +/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c900 } + }, +/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c900 } + }, +/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e900 } + }, +/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c900 } + }, +/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c900 } + }, +/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e900 } + }, +/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c900 } + }, +/* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78900 } + }, +/* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a900 } + }, +/* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878900 } + }, +/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980900 } + }, +/* tst.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982900 } + }, +/* tst.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983900 } + }, +/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908900 } + }, +/* tst.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a900 } + }, +/* tst.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b900 } + }, +/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900900 } + }, +/* tst.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902900 } + }, +/* tst.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903900 } + }, +/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920900 } + }, +/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922900 } + }, +/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923900 } + }, +/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940900 } + }, +/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942900 } + }, +/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943900 } + }, +/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960900 } + }, +/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962900 } + }, +/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963900 } + }, +/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928900 } + }, +/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a900 } + }, +/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b900 } + }, +/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948900 } + }, +/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a900 } + }, +/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b900 } + }, +/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c900 } + }, +/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e900 } + }, +/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f900 } + }, +/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c900 } + }, +/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e900 } + }, +/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f900 } + }, +/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c900 } + }, +/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e900 } + }, +/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f900 } + }, +/* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968900 } + }, +/* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a900 } + }, +/* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b900 } + }, +/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80900 } + }, +/* tst.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82900 } + }, +/* tst.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83900 } + }, +/* tst.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83900 } + }, +/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08900 } + }, +/* tst.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a900 } + }, +/* tst.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b900 } + }, +/* tst.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b900 } + }, +/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00900 } + }, +/* tst.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02900 } + }, +/* tst.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03900 } + }, +/* tst.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03900 } + }, +/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20900 } + }, +/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22900 } + }, +/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23900 } + }, +/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23900 } + }, +/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40900 } + }, +/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42900 } + }, +/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43900 } + }, +/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43900 } + }, +/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60900 } + }, +/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62900 } + }, +/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63900 } + }, +/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63900 } + }, +/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28900 } + }, +/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a900 } + }, +/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b900 } + }, +/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b900 } + }, +/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48900 } + }, +/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a900 } + }, +/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b900 } + }, +/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b900 } + }, +/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c900 } + }, +/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e900 } + }, +/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f900 } + }, +/* tst.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f900 } + }, +/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c900 } + }, +/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e900 } + }, +/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f900 } + }, +/* tst.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f900 } + }, +/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c900 } + }, +/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e900 } + }, +/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f900 } + }, +/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f900 } + }, +/* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68900 } + }, +/* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a900 } + }, +/* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b900 } + }, +/* tst.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b900 } + }, +/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80900 } + }, +/* tst.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82900 } + }, +/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08900 } + }, +/* tst.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a900 } + }, +/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00900 } + }, +/* tst.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02900 } + }, +/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20900 } + }, +/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22900 } + }, +/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40900 } + }, +/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42900 } + }, +/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60900 } + }, +/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62900 } + }, +/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28900 } + }, +/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a900 } + }, +/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48900 } + }, +/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a900 } + }, +/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c900 } + }, +/* tst.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e900 } + }, +/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c900 } + }, +/* tst.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e900 } + }, +/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c900 } + }, +/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e900 } + }, +/* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68900 } + }, +/* tst.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a900 } + }, +/* tst.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c809 } + }, +/* tst.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18829 } + }, +/* tst.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18809 } + }, +/* tst.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c089 } + }, +/* tst.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a9 } + }, +/* tst.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18089 } + }, +/* tst.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c009 } + }, +/* tst.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18029 } + }, +/* tst.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18009 } + }, +/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20900 } + }, +/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822900 } + }, +/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820900 } + }, +/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40900 } + }, +/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842900 } + }, +/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840900 } + }, +/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60900 } + }, +/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862900 } + }, +/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860900 } + }, +/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28900 } + }, +/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a900 } + }, +/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828900 } + }, +/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48900 } + }, +/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a900 } + }, +/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848900 } + }, +/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c900 } + }, +/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e900 } + }, +/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c900 } + }, +/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c900 } + }, +/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e900 } + }, +/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c900 } + }, +/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c900 } + }, +/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e900 } + }, +/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c900 } + }, +/* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68900 } + }, +/* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a900 } + }, +/* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868900 } + }, +/* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x818000 } + }, +/* tst.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x81a000 } + }, +/* tst.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x81b000 } + }, +/* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x818400 } + }, +/* tst.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x81a400 } + }, +/* tst.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x81b400 } + }, +/* tst.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x818600 } + }, +/* tst.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x81a600 } + }, +/* tst.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x81b600 } + }, +/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x81880000 } + }, +/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x81a80000 } + }, +/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x81b80000 } + }, +/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x818c0000 } + }, +/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x81ac0000 } + }, +/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x81bc0000 } + }, +/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x818a0000 } + }, +/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x81aa0000 } + }, +/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x81ba0000 } + }, +/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x818e0000 } + }, +/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x81ae0000 } + }, +/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x81be0000 } + }, +/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x818b0000 } + }, +/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x81ab0000 } + }, +/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x81bb0000 } + }, +/* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x818f0000 } + }, +/* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x81af0000 } + }, +/* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x81bf0000 } + }, +/* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x81c00000 } + }, +/* tst.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x81e00000 } + }, +/* tst.w${X} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x81f00000 } + }, +/* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x81c40000 } + }, +/* tst.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x81e40000 } + }, +/* tst.w${X} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x81f40000 } + }, +/* tst.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x81c60000 } + }, +/* tst.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x81e60000 } + }, +/* tst.w${X} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x81f60000 } + }, +/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x81c80000 } + }, +/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x81e80000 } + }, +/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x81f80000 } + }, +/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x81cc0000 } + }, +/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x81ec0000 } + }, +/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x81fc0000 } + }, +/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x81ca0000 } + }, +/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x81ea0000 } + }, +/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x81fa0000 } + }, +/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x81ce0000 } + }, +/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x81ee0000 } + }, +/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x81fe0000 } + }, +/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x81cb0000 } + }, +/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x81eb0000 } + }, +/* tst.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x81fb0000 } + }, +/* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x81cf0000 } + }, +/* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x81ef0000 } + }, +/* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x81ff0000 } + }, +/* tst.w${X} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x8100 } + }, +/* tst.w${X} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x8140 } + }, +/* tst.w${X} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x8160 } + }, +/* tst.w${X} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x8104 } + }, +/* tst.w${X} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x8144 } + }, +/* tst.w${X} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x8164 } + }, +/* tst.w${X} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x8106 } + }, +/* tst.w${X} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x8146 } + }, +/* tst.w${X} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x8166 } + }, +/* tst.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x810800 } + }, +/* tst.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x814800 } + }, +/* tst.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x816800 } + }, +/* tst.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x810c0000 } + }, +/* tst.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x814c0000 } + }, +/* tst.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x816c0000 } + }, +/* tst.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x810a00 } + }, +/* tst.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x814a00 } + }, +/* tst.w${X} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x816a00 } + }, +/* tst.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x810e0000 } + }, +/* tst.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x814e0000 } + }, +/* tst.w${X} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x816e0000 } + }, +/* tst.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x810b00 } + }, +/* tst.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x814b00 } + }, +/* tst.w${X} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x816b00 } + }, +/* tst.w${X} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x810f0000 } + }, +/* tst.w${X} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x814f0000 } + }, +/* tst.w${X} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x816f0000 } + }, +/* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x808000 } + }, +/* tst.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x80a000 } + }, +/* tst.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x80b000 } + }, +/* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x808400 } + }, +/* tst.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x80a400 } + }, +/* tst.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x80b400 } + }, +/* tst.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x808600 } + }, +/* tst.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x80a600 } + }, +/* tst.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x80b600 } + }, +/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x80880000 } + }, +/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x80a80000 } + }, +/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x80b80000 } + }, +/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x808c0000 } + }, +/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x80ac0000 } + }, +/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x80bc0000 } + }, +/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x808a0000 } + }, +/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x80aa0000 } + }, +/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x80ba0000 } + }, +/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x808e0000 } + }, +/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x80ae0000 } + }, +/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x80be0000 } + }, +/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x808b0000 } + }, +/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x80ab0000 } + }, +/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x80bb0000 } + }, +/* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x808f0000 } + }, +/* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x80af0000 } + }, +/* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x80bf0000 } + }, +/* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x80c00000 } + }, +/* tst.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x80e00000 } + }, +/* tst.b${X} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x80f00000 } + }, +/* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x80c40000 } + }, +/* tst.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x80e40000 } + }, +/* tst.b${X} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x80f40000 } + }, +/* tst.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x80c60000 } + }, +/* tst.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x80e60000 } + }, +/* tst.b${X} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x80f60000 } + }, +/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x80c80000 } + }, +/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x80e80000 } + }, +/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x80f80000 } + }, +/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x80cc0000 } + }, +/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x80ec0000 } + }, +/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x80fc0000 } + }, +/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x80ca0000 } + }, +/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x80ea0000 } + }, +/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x80fa0000 } + }, +/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x80ce0000 } + }, +/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x80ee0000 } + }, +/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x80fe0000 } + }, +/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x80cb0000 } + }, +/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x80eb0000 } + }, +/* tst.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x80fb0000 } + }, +/* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x80cf0000 } + }, +/* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x80ef0000 } + }, +/* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x80ff0000 } + }, +/* tst.b${X} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x8000 } + }, +/* tst.b${X} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x8040 } + }, +/* tst.b${X} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x8060 } + }, +/* tst.b${X} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x8004 } + }, +/* tst.b${X} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x8044 } + }, +/* tst.b${X} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x8064 } + }, +/* tst.b${X} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x8006 } + }, +/* tst.b${X} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x8046 } + }, +/* tst.b${X} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x8066 } + }, +/* tst.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x800800 } + }, +/* tst.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x804800 } + }, +/* tst.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x806800 } + }, +/* tst.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x800c0000 } + }, +/* tst.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x804c0000 } + }, +/* tst.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x806c0000 } + }, +/* tst.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x800a00 } + }, +/* tst.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x804a00 } + }, +/* tst.b${X} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x806a00 } + }, +/* tst.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x800e0000 } + }, +/* tst.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x804e0000 } + }, +/* tst.b${X} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x806e0000 } + }, +/* tst.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x800b00 } + }, +/* tst.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x804b00 } + }, +/* tst.b${X} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x806b00 } + }, +/* tst.b${X} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x800f0000 } + }, +/* tst.b${X} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x804f0000 } + }, +/* tst.b${X} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x806f0000 } + }, +/* tst.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x993e0000 } + }, +/* tst.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91be0000 } + }, +/* tst.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x913e0000 } + }, +/* tst.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x933e0000 } + }, +/* tst.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93be0000 } + }, +/* tst.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93fe0000 } + }, +/* tst.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x953e0000 } + }, +/* tst.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95be0000 } + }, +/* tst.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95fe0000 } + }, +/* tst.w${X} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97fe0000 } + }, +/* tst.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x973e0000 } + }, +/* tst.w${X} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97be0000 } + }, +/* tst.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x983e00 } + }, +/* tst.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90be00 } + }, +/* tst.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x903e00 } + }, +/* tst.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x923e0000 } + }, +/* tst.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92be0000 } + }, +/* tst.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92fe0000 } + }, +/* tst.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x943e0000 } + }, +/* tst.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94be0000 } + }, +/* tst.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94fe0000 } + }, +/* tst.b${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96fe0000 } + }, +/* tst.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x963e0000 } + }, +/* tst.b${X} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96be0000 } + }, +/* tst.w${X} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77000000 } + }, +/* tst.w${X} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77040000 } + }, +/* tst.w${X} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77060000 } + }, +/* tst.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77080000 } + }, +/* tst.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x770a0000 } + }, +/* tst.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x770b0000 } + }, +/* tst.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x770c0000 } + }, +/* tst.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x770e0000 } + }, +/* tst.w${X} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x770f0000 } + }, +/* tst.b${X} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x760000 } + }, +/* tst.b${X} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x760400 } + }, +/* tst.b${X} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x760600 } + }, +/* tst.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76080000 } + }, +/* tst.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x760a0000 } + }, +/* tst.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x760b0000 } + }, +/* tst.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x760c0000 } + }, +/* tst.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x760e0000 } + }, +/* tst.b${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x760f0000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x980000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x982000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x983000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x908000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x90a000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x90b000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x900000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x902000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x903000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92000000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92200000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92300000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94000000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94200000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94300000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96000000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96200000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96300000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92800000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92a00000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92b00000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94800000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94a00000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94b00000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92c00000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92e00000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92f00000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94c00000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94e00000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94f00000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96c00000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96e00000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96f00000 } + }, +/* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96800000 } + }, +/* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96a00000 } + }, +/* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96b00000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8000000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8200000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8300000 } + }, +/* subx${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8300000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0800000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0a00000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0b00000 } + }, +/* subx${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0b00000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0000000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0200000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0300000 } + }, +/* subx${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0300000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2000000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2200000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2300000 } + }, +/* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb2300000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4000000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4200000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4300000 } + }, +/* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb4300000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6000000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6200000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6300000 } + }, +/* subx${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb6300000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2800000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2a00000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2b00000 } + }, +/* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb2b00000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4800000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4a00000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4b00000 } + }, +/* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb4b00000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2c00000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2e00000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2f00000 } + }, +/* subx${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb2f00000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4c00000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4e00000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4f00000 } + }, +/* subx${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb4f00000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6c00000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6e00000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6f00000 } + }, +/* subx${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xb6f00000 } + }, +/* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6800000 } + }, +/* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6a00000 } + }, +/* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6b00000 } + }, +/* subx${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xb6b00000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8000000 } + }, +/* subx${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8200000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0800000 } + }, +/* subx${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0a00000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0000000 } + }, +/* subx${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0200000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb2000000 } + }, +/* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb2200000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb4000000 } + }, +/* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb4200000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb6000000 } + }, +/* subx${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb6200000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb2800000 } + }, +/* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb2a00000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb4800000 } + }, +/* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb4a00000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb2c00000 } + }, +/* subx${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb2e00000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb4c00000 } + }, +/* subx${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb4e00000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI, { 0xb6c00000 } + }, +/* subx${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI, { 0xb6e00000 } + }, +/* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI, { 0xb6800000 } + }, +/* subx${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI, { 0xb6a00000 } + }, +/* subx${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xc800 } + }, +/* subx${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x8820 } + }, +/* subx${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x8800 } + }, +/* subx${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xc080 } + }, +/* subx${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x80a0 } + }, +/* subx${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x8080 } + }, +/* subx${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xc000 } + }, +/* subx${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x8020 } + }, +/* subx${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x8000 } + }, +/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc20000 } + }, +/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0x822000 } + }, +/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0x820000 } + }, +/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4000000 } + }, +/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0x84200000 } + }, +/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0x84000000 } + }, +/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6000000 } + }, +/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0x86200000 } + }, +/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0x86000000 } + }, +/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc28000 } + }, +/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82a000 } + }, +/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x828000 } + }, +/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4800000 } + }, +/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84a00000 } + }, +/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84800000 } + }, +/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2c000 } + }, +/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82e000 } + }, +/* subx${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82c000 } + }, +/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4c00000 } + }, +/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84e00000 } + }, +/* subx${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84c00000 } + }, +/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0xc6c00000 } + }, +/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0x86e00000 } + }, +/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0x86c00000 } + }, +/* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0xc6800000 } + }, +/* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0x86a00000 } + }, +/* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0x86800000 } + }, +/* subx${G} #${Imm-16-QI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x981100 } + }, +/* subx${G} #${Imm-16-QI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x909100 } + }, +/* subx${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x901100 } + }, +/* subx${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x92110000 } + }, +/* subx${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x92910000 } + }, +/* subx${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x92d10000 } + }, +/* subx${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x94110000 } + }, +/* subx${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x94910000 } + }, +/* subx${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x94d10000 } + }, +/* subx${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x96d10000 } + }, +/* subx${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x96110000 } + }, +/* subx${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x96910000 } + }, +/* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), ',', '#', OP (IMM_32_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x993f0000 } + }, +/* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), ',', '#', OP (IMM_32_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91bf0000 } + }, +/* stzx.w #${Imm-16-HI},#${Imm-32-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), ',', '#', OP (IMM_32_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stzx32_w_Imm_16_HI_Imm_32_HI_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x913f0000 } + }, +/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x933f0000 } + }, +/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93bf0000 } + }, +/* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stzx32_w_Imm_24_HI_Imm_40_HI_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93ff0000 } + }, +/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x953f0000 } + }, +/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95bf0000 } + }, +/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95ff0000 } + }, +/* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stzx32_w_Imm_32_HI_Imm_48_HI_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97ff0000 } + }, +/* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stzx32_w_Imm_40_HI_Imm_56_HI_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x973f0000 } + }, +/* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_stzx32_w_Imm_40_HI_Imm_56_HI_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97bf0000 } + }, +/* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), ',', '#', OP (IMM_24_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x983f0000 } + }, +/* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), ',', '#', OP (IMM_24_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90bf0000 } + }, +/* stzx.b #${Imm-16-QI},#${Imm-24-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), ',', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stzx32_b_Imm_16_QI_Imm_24_QI_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x903f0000 } + }, +/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x923f0000 } + }, +/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92bf0000 } + }, +/* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stzx32_b_Imm_24_QI_Imm_32_QI_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92ff0000 } + }, +/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x943f0000 } + }, +/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94bf0000 } + }, +/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94ff0000 } + }, +/* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stzx32_b_Imm_32_QI_Imm_40_QI_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96ff0000 } + }, +/* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stzx32_b_Imm_40_QI_Imm_48_QI_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x963f0000 } + }, +/* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_stzx32_b_Imm_40_QI_Imm_48_QI_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96bf0000 } + }, +/* stz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x990f0000 } + }, +/* stz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x918f0000 } + }, +/* stz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x910f0000 } + }, +/* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x930f0000 } + }, +/* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x938f0000 } + }, +/* stz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93cf0000 } + }, +/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x950f0000 } + }, +/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x958f0000 } + }, +/* stz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95cf0000 } + }, +/* stz.w${X} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97cf0000 } + }, +/* stz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x970f0000 } + }, +/* stz.w${X} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x978f0000 } + }, +/* stz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x980f00 } + }, +/* stz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x908f00 } + }, +/* stz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x900f00 } + }, +/* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x920f0000 } + }, +/* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x928f0000 } + }, +/* stz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92cf0000 } + }, +/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x940f0000 } + }, +/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x948f0000 } + }, +/* stz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94cf0000 } + }, +/* stz.b${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96cf0000 } + }, +/* stz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x960f0000 } + }, +/* stz.b${X} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x968f0000 } + }, +/* stz${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xcc00 } + }, +/* stz${S} #${Imm-8-QI},r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xcb00 } + }, +/* stz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xcd0000 } + }, +/* stz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xce0000 } + }, +/* stz${S} #${Imm-8-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xcf000000 } + }, +/* stnz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x991f0000 } + }, +/* stnz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x919f0000 } + }, +/* stnz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x911f0000 } + }, +/* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x931f0000 } + }, +/* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x939f0000 } + }, +/* stnz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93df0000 } + }, +/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x951f0000 } + }, +/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x959f0000 } + }, +/* stnz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95df0000 } + }, +/* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97df0000 } + }, +/* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x971f0000 } + }, +/* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x979f0000 } + }, +/* stnz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x981f00 } + }, +/* stnz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x909f00 } + }, +/* stnz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x901f00 } + }, +/* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x921f0000 } + }, +/* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x929f0000 } + }, +/* stnz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92df0000 } + }, +/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x941f0000 } + }, +/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x949f0000 } + }, +/* stnz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94df0000 } + }, +/* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96df0000 } + }, +/* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x961f0000 } + }, +/* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x969f0000 } + }, +/* stnz${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xd400 } + }, +/* stnz${S} #${Imm-8-QI},r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xd300 } + }, +/* stnz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xd50000 } + }, +/* stnz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xd60000 } + }, +/* stnz${S} #${Imm-8-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xd7000000 } + }, +/* shlnc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x882100 } + }, +/* shlnc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x80a100 } + }, +/* shlnc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x802100 } + }, +/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x82210000 } + }, +/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82a10000 } + }, +/* shlnc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82e10000 } + }, +/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x84210000 } + }, +/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84a10000 } + }, +/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84e10000 } + }, +/* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x86e10000 } + }, +/* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x86210000 } + }, +/* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x86a10000 } + }, +/* shl.l r1h,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xc801 } + }, +/* shl.l r1h,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xc081 } + }, +/* shl.l r1h,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xc001 } + }, +/* shl.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xc20100 } + }, +/* shl.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4010000 } + }, +/* shl.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6010000 } + }, +/* shl.l r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc28100 } + }, +/* shl.l r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4810000 } + }, +/* shl.l r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2c100 } + }, +/* shl.l r1h,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4c10000 } + }, +/* shl.l r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xc6c10000 } + }, +/* shl.l r1h,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xc6810000 } + }, +/* shl.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x982100 } + }, +/* shl.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x90a100 } + }, +/* shl.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x902100 } + }, +/* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x92210000 } + }, +/* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x92a10000 } + }, +/* shl.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x92e10000 } + }, +/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x94210000 } + }, +/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x94a10000 } + }, +/* shl.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x94e10000 } + }, +/* shl.l${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x96e10000 } + }, +/* shl.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x96210000 } + }, +/* shl.l${X} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x96a10000 } + }, +/* shl.w r1h,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa93e } + }, +/* shl.w r1h,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1be } + }, +/* shl.w r1h,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa13e } + }, +/* shl.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa33e00 } + }, +/* shl.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa53e0000 } + }, +/* shl.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa73e0000 } + }, +/* shl.w r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3be00 } + }, +/* shl.w r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5be0000 } + }, +/* shl.w r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3fe00 } + }, +/* shl.w r1h,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5fe0000 } + }, +/* shl.w r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7fe0000 } + }, +/* shl.w r1h,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7be0000 } + }, +/* shl.b r1h,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa83e } + }, +/* shl.b r1h,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0be } + }, +/* shl.b r1h,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa03e } + }, +/* shl.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa23e00 } + }, +/* shl.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa43e0000 } + }, +/* shl.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa63e0000 } + }, +/* shl.b r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2be00 } + }, +/* shl.b r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4be0000 } + }, +/* shl.b r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2fe00 } + }, +/* shl.b r1h,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4fe0000 } + }, +/* shl.b r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6fe0000 } + }, +/* shl.b r1h,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6be0000 } + }, +/* shl.w r1h,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNHI), 0 } }, + & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x75e0 } + }, +/* shl.w r1h,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANHI), 0 } }, + & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x75e4 } + }, +/* shl.w r1h,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x75e6 } + }, +/* shl.w r1h,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x75e800 } + }, +/* shl.w r1h,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x75ec0000 } + }, +/* shl.w r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x75ea00 } + }, +/* shl.w r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x75ee0000 } + }, +/* shl.w r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x75eb00 } + }, +/* shl.w r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x75ef0000 } + }, +/* shl.b r1h,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x74e0 } + }, +/* shl.b r1h,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x74e4 } + }, +/* shl.b r1h,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x74e6 } + }, +/* shl.b r1h,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x74e800 } + }, +/* shl.b r1h,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x74ec0000 } + }, +/* shl.b r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x74ea00 } + }, +/* shl.b r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x74ee0000 } + }, +/* shl.b r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x74eb00 } + }, +/* shl.b r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x74ef0000 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xe900 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xe180 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xe100 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xe30000 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xe5000000 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xe7000000 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xe38000 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xe5800000 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xe3c000 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xe5c00000 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xe7c00000 } + }, +/* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xe7800000 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xe800 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xe080 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xe000 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xe20000 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xe4000000 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xe6000000 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xe28000 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xe4800000 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xe2c000 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xe4c00000 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xe6c00000 } + }, +/* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xe6800000 } + }, +/* shl.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNHI), 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xe900 } + }, +/* shl.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANHI), 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_An_direct_HI, { 0xe904 } + }, +/* shl.w${Q} #${Imm-sh-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xe906 } + }, +/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xe90800 } + }, +/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xe90c0000 } + }, +/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xe90a00 } + }, +/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xe90e0000 } + }, +/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xe90b00 } + }, +/* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xe90f0000 } + }, +/* shl.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNQI), 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xe800 } + }, +/* shl.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANQI), 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_An_direct_QI, { 0xe804 } + }, +/* shl.b${Q} #${Imm-sh-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xe806 } + }, +/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xe80800 } + }, +/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xe80c0000 } + }, +/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xe80a00 } + }, +/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xe80e0000 } + }, +/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xe80b00 } + }, +/* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xe80f0000 } + }, +/* shanc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xc82100 } + }, +/* shanc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xc0a100 } + }, +/* shanc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xc02100 } + }, +/* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xc2210000 } + }, +/* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc2a10000 } + }, +/* shanc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2e10000 } + }, +/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4210000 } + }, +/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4a10000 } + }, +/* shanc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4e10000 } + }, +/* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xc6e10000 } + }, +/* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6210000 } + }, +/* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xc6a10000 } + }, +/* sha.l r1h,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xc811 } + }, +/* sha.l r1h,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xc091 } + }, +/* sha.l r1h,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xc011 } + }, +/* sha.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xc21100 } + }, +/* sha.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4110000 } + }, +/* sha.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6110000 } + }, +/* sha.l r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc29100 } + }, +/* sha.l r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4910000 } + }, +/* sha.l r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2d100 } + }, +/* sha.l r1h,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4d10000 } + }, +/* sha.l r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xc6d10000 } + }, +/* sha.l r1h,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xc6910000 } + }, +/* sha.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xa82100 } + }, +/* sha.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xa0a100 } + }, +/* sha.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xa02100 } + }, +/* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xa2210000 } + }, +/* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa2a10000 } + }, +/* sha.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2e10000 } + }, +/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xa4210000 } + }, +/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4a10000 } + }, +/* sha.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4e10000 } + }, +/* sha.l${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xa6e10000 } + }, +/* sha.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xa6210000 } + }, +/* sha.l${X} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xa6a10000 } + }, +/* sha.w r1h,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb93e } + }, +/* sha.w r1h,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb1be } + }, +/* sha.w r1h,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb13e } + }, +/* sha.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb33e00 } + }, +/* sha.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb53e0000 } + }, +/* sha.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb73e0000 } + }, +/* sha.w r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb3be00 } + }, +/* sha.w r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb5be0000 } + }, +/* sha.w r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3fe00 } + }, +/* sha.w r1h,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5fe0000 } + }, +/* sha.w r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7fe0000 } + }, +/* sha.w r1h,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb7be0000 } + }, +/* sha.b r1h,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb83e } + }, +/* sha.b r1h,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb0be } + }, +/* sha.b r1h,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb03e } + }, +/* sha.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb23e00 } + }, +/* sha.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb43e0000 } + }, +/* sha.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb63e0000 } + }, +/* sha.b r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb2be00 } + }, +/* sha.b r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb4be0000 } + }, +/* sha.b r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2fe00 } + }, +/* sha.b r1h,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4fe0000 } + }, +/* sha.b r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6fe0000 } + }, +/* sha.b r1h,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb6be0000 } + }, +/* sha.w r1h,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNHI), 0 } }, + & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x75f0 } + }, +/* sha.w r1h,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANHI), 0 } }, + & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x75f4 } + }, +/* sha.w r1h,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x75f6 } + }, +/* sha.w r1h,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x75f800 } + }, +/* sha.w r1h,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x75fc0000 } + }, +/* sha.w r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x75fa00 } + }, +/* sha.w r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x75fe0000 } + }, +/* sha.w r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x75fb00 } + }, +/* sha.w r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x75ff0000 } + }, +/* sha.b r1h,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNQI), 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x74f0 } + }, +/* sha.b r1h,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANQI), 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x74f4 } + }, +/* sha.b r1h,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x74f6 } + }, +/* sha.b r1h,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x74f800 } + }, +/* sha.b r1h,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x74fc0000 } + }, +/* sha.b r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x74fa00 } + }, +/* sha.b r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x74fe0000 } + }, +/* sha.b r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x74fb00 } + }, +/* sha.b r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x74ff0000 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf900 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf180 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf100 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf30000 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5000000 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7000000 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf38000 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5800000 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3c000 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5c00000 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7c00000 } + }, +/* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7800000 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf800 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf080 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf000 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf20000 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4000000 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6000000 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf28000 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4800000 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2c000 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4c00000 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6c00000 } + }, +/* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6800000 } + }, +/* sha.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNHI), 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xf100 } + }, +/* sha.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANHI), 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_An_direct_HI, { 0xf104 } + }, +/* sha.w${Q} #${Imm-sh-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xf106 } + }, +/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xf10800 } + }, +/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xf10c0000 } + }, +/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xf10a00 } + }, +/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xf10e0000 } + }, +/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xf10b00 } + }, +/* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xf10f0000 } + }, +/* sha.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNQI), 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xf000 } + }, +/* sha.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANQI), 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_An_direct_QI, { 0xf004 } + }, +/* sha.b${Q} #${Imm-sh-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xf006 } + }, +/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xf00800 } + }, +/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xf00c0000 } + }, +/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xf00a00 } + }, +/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xf00e0000 } + }, +/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xf00b00 } + }, +/* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xf00f0000 } + }, +/* sc${sccond32} $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_sccnd_dst32_Rn_direct_Unprefixed_HI, { 0xd930 } + }, +/* sc${sccond32} $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_sccnd_dst32_An_direct_Unprefixed_HI, { 0xd1b0 } + }, +/* sc${sccond32} [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_sccnd_dst32_An_indirect_Unprefixed_HI, { 0xd130 } + }, +/* sc${sccond32} ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_sccnd_dst32_16_8_An_relative_Unprefixed_HI, { 0xd33000 } + }, +/* sc${sccond32} ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_sccnd_dst32_16_16_An_relative_Unprefixed_HI, { 0xd5300000 } + }, +/* sc${sccond32} ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_sccnd_dst32_16_24_An_relative_Unprefixed_HI, { 0xd7300000 } + }, +/* sc${sccond32} ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sccnd_dst32_16_8_SB_relative_Unprefixed_HI, { 0xd3b000 } + }, +/* sc${sccond32} ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sccnd_dst32_16_16_SB_relative_Unprefixed_HI, { 0xd5b00000 } + }, +/* sc${sccond32} ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sccnd_dst32_16_8_FB_relative_Unprefixed_HI, { 0xd3f000 } + }, +/* sc${sccond32} ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sccnd_dst32_16_16_FB_relative_Unprefixed_HI, { 0xd5f00000 } + }, +/* sc${sccond32} ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U16), 0 } }, + & ifmt_sccnd_dst32_16_16_absolute_Unprefixed_HI, { 0xd7f00000 } + }, +/* sc${sccond32} ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SCCOND32), ' ', OP (DSP_16_U24), 0 } }, + & ifmt_sccnd_dst32_16_24_absolute_Unprefixed_HI, { 0xd7b00000 } + }, +/* sbjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf3100000 } + }, +/* sbjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf3900000 } + }, +/* sbjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3d00000 } + }, +/* sbjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5100000 } + }, +/* sbjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5900000 } + }, +/* sbjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5d00000 } + }, +/* sbjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7d00000 } + }, +/* sbjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7100000 } + }, +/* sbjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7900000 } + }, +/* sbjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf91000 } + }, +/* sbjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf19000 } + }, +/* sbjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf11000 } + }, +/* sbjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf2100000 } + }, +/* sbjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf2900000 } + }, +/* sbjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2d00000 } + }, +/* sbjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4100000 } + }, +/* sbjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4900000 } + }, +/* sbjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4d00000 } + }, +/* sbjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6d00000 } + }, +/* sbjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6100000 } + }, +/* sbjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6900000 } + }, +/* sbjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf81000 } + }, +/* sbjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf09000 } + }, +/* sbjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf01000 } + }, +/* sbjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI, { 0xf9080000 } + }, +/* sbjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI, { 0xf90a0000 } + }, +/* sbjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI, { 0xf90b0000 } + }, +/* sbjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI, { 0xf90c0000 } + }, +/* sbjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI, { 0xf90e0000 } + }, +/* sbjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_absolute_HI, { 0xf90f0000 } + }, +/* sbjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz16_w_imm4_basic_dst16_Rn_direct_HI, { 0xf90000 } + }, +/* sbjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz16_w_imm4_basic_dst16_An_direct_HI, { 0xf90400 } + }, +/* sbjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz16_w_imm4_basic_dst16_An_indirect_HI, { 0xf90600 } + }, +/* sbjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI, { 0xf8080000 } + }, +/* sbjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI, { 0xf80a0000 } + }, +/* sbjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI, { 0xf80b0000 } + }, +/* sbjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI, { 0xf80c0000 } + }, +/* sbjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI, { 0xf80e0000 } + }, +/* sbjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_absolute_QI, { 0xf80f0000 } + }, +/* sbjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz16_b_imm4_basic_dst16_Rn_direct_QI, { 0xf80000 } + }, +/* sbjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz16_b_imm4_basic_dst16_An_direct_QI, { 0xf80400 } + }, +/* sbjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz16_b_imm4_basic_dst16_An_indirect_QI, { 0xf80600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978600 } + }, +/* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a600 } + }, +/* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93600 } + }, +/* sbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b600 } + }, +/* sbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13600 } + }, +/* sbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33600 } + }, +/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53600 } + }, +/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73600 } + }, +/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b600 } + }, +/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b600 } + }, +/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f600 } + }, +/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f600 } + }, +/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f600 } + }, +/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78600 } + }, +/* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a600 } + }, +/* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b600 } + }, +/* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90600 } + }, +/* sbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18600 } + }, +/* sbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10600 } + }, +/* sbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30600 } + }, +/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50600 } + }, +/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70600 } + }, +/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38600 } + }, +/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58600 } + }, +/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c600 } + }, +/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c600 } + }, +/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c600 } + }, +/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e600 } + }, +/* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78600 } + }, +/* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a600 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c906 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18926 } + }, +/* sbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18906 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c186 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a6 } + }, +/* sbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18186 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c106 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18126 } + }, +/* sbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18106 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30600 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832600 } + }, +/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830600 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50600 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852600 } + }, +/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850600 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70600 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872600 } + }, +/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870600 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38600 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a600 } + }, +/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838600 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58600 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a600 } + }, +/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858600 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c600 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e600 } + }, +/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c600 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c600 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e600 } + }, +/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c600 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c600 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e600 } + }, +/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c600 } + }, +/* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78600 } + }, +/* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a600 } + }, +/* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968600 } + }, +/* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a600 } + }, +/* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83600 } + }, +/* sbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b600 } + }, +/* sbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03600 } + }, +/* sbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23600 } + }, +/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43600 } + }, +/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63600 } + }, +/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b600 } + }, +/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b600 } + }, +/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f600 } + }, +/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f600 } + }, +/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f600 } + }, +/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68600 } + }, +/* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a600 } + }, +/* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b600 } + }, +/* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80600 } + }, +/* sbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08600 } + }, +/* sbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00600 } + }, +/* sbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20600 } + }, +/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40600 } + }, +/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60600 } + }, +/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28600 } + }, +/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48600 } + }, +/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c600 } + }, +/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c600 } + }, +/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c600 } + }, +/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e600 } + }, +/* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68600 } + }, +/* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a600 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c806 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18826 } + }, +/* sbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18806 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c086 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a6 } + }, +/* sbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18086 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c006 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18026 } + }, +/* sbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18006 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20600 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822600 } + }, +/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820600 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40600 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842600 } + }, +/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840600 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60600 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862600 } + }, +/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860600 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28600 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a600 } + }, +/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828600 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48600 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a600 } + }, +/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848600 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c600 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e600 } + }, +/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c600 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c600 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e600 } + }, +/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c600 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c600 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e600 } + }, +/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c600 } + }, +/* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68600 } + }, +/* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a600 } + }, +/* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868600 } + }, +/* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xb98000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xb9a000 } + }, +/* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xb9b000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xb98400 } + }, +/* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xb9a400 } + }, +/* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xb9b400 } + }, +/* sbb.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xb98600 } + }, +/* sbb.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xb9a600 } + }, +/* sbb.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xb9b600 } + }, +/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xb9880000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xb9a80000 } + }, +/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xb9b80000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xb98c0000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xb9ac0000 } + }, +/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xb9bc0000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xb98a0000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xb9aa0000 } + }, +/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xb9ba0000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xb98e0000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xb9ae0000 } + }, +/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xb9be0000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xb98b0000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xb9ab0000 } + }, +/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xb9bb0000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xb98f0000 } + }, +/* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xb9af0000 } + }, +/* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xb9bf0000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xb9c00000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xb9e00000 } + }, +/* sbb.w${X} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xb9f00000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xb9c40000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xb9e40000 } + }, +/* sbb.w${X} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xb9f40000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xb9c60000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xb9e60000 } + }, +/* sbb.w${X} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xb9f60000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xb9c80000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xb9e80000 } + }, +/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xb9f80000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xb9cc0000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xb9ec0000 } + }, +/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xb9fc0000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xb9ca0000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xb9ea0000 } + }, +/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xb9fa0000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xb9ce0000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xb9ee0000 } + }, +/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xb9fe0000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xb9cb0000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xb9eb0000 } + }, +/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xb9fb0000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xb9cf0000 } + }, +/* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xb9ef0000 } + }, +/* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xb9ff0000 } + }, +/* sbb.w${X} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xb900 } + }, +/* sbb.w${X} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xb940 } + }, +/* sbb.w${X} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xb960 } + }, +/* sbb.w${X} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xb904 } + }, +/* sbb.w${X} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xb944 } + }, +/* sbb.w${X} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xb964 } + }, +/* sbb.w${X} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xb906 } + }, +/* sbb.w${X} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xb946 } + }, +/* sbb.w${X} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xb966 } + }, +/* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xb90800 } + }, +/* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xb94800 } + }, +/* sbb.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xb96800 } + }, +/* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xb90c0000 } + }, +/* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xb94c0000 } + }, +/* sbb.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xb96c0000 } + }, +/* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xb90a00 } + }, +/* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xb94a00 } + }, +/* sbb.w${X} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xb96a00 } + }, +/* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xb90e0000 } + }, +/* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xb94e0000 } + }, +/* sbb.w${X} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xb96e0000 } + }, +/* sbb.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xb90b00 } + }, +/* sbb.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xb94b00 } + }, +/* sbb.w${X} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xb96b00 } + }, +/* sbb.w${X} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xb90f0000 } + }, +/* sbb.w${X} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xb94f0000 } + }, +/* sbb.w${X} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xb96f0000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xb88000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xb8a000 } + }, +/* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xb8b000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xb88400 } + }, +/* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xb8a400 } + }, +/* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xb8b400 } + }, +/* sbb.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xb88600 } + }, +/* sbb.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xb8a600 } + }, +/* sbb.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xb8b600 } + }, +/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xb8880000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xb8a80000 } + }, +/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xb8b80000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xb88c0000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xb8ac0000 } + }, +/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xb8bc0000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xb88a0000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xb8aa0000 } + }, +/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xb8ba0000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xb88e0000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xb8ae0000 } + }, +/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xb8be0000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xb88b0000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xb8ab0000 } + }, +/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xb8bb0000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xb88f0000 } + }, +/* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xb8af0000 } + }, +/* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xb8bf0000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xb8c00000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xb8e00000 } + }, +/* sbb.b${X} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xb8f00000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xb8c40000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xb8e40000 } + }, +/* sbb.b${X} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xb8f40000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xb8c60000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xb8e60000 } + }, +/* sbb.b${X} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xb8f60000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xb8c80000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xb8e80000 } + }, +/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xb8f80000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xb8cc0000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xb8ec0000 } + }, +/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xb8fc0000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xb8ca0000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xb8ea0000 } + }, +/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xb8fa0000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xb8ce0000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xb8ee0000 } + }, +/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xb8fe0000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xb8cb0000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xb8eb0000 } + }, +/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xb8fb0000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xb8cf0000 } + }, +/* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xb8ef0000 } + }, +/* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xb8ff0000 } + }, +/* sbb.b${X} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xb800 } + }, +/* sbb.b${X} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xb840 } + }, +/* sbb.b${X} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xb860 } + }, +/* sbb.b${X} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xb804 } + }, +/* sbb.b${X} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xb844 } + }, +/* sbb.b${X} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xb864 } + }, +/* sbb.b${X} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xb806 } + }, +/* sbb.b${X} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xb846 } + }, +/* sbb.b${X} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xb866 } + }, +/* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xb80800 } + }, +/* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xb84800 } + }, +/* sbb.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xb86800 } + }, +/* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xb80c0000 } + }, +/* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xb84c0000 } + }, +/* sbb.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xb86c0000 } + }, +/* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xb80a00 } + }, +/* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xb84a00 } + }, +/* sbb.b${X} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xb86a00 } + }, +/* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xb80e0000 } + }, +/* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xb84e0000 } + }, +/* sbb.b${X} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xb86e0000 } + }, +/* sbb.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xb80b00 } + }, +/* sbb.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xb84b00 } + }, +/* sbb.b${X} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xb86b00 } + }, +/* sbb.b${X} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xb80f0000 } + }, +/* sbb.b${X} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xb84f0000 } + }, +/* sbb.b${X} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xb86f0000 } + }, +/* sbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1992e00 } + }, +/* sbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x191ae00 } + }, +/* sbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1912e00 } + }, +/* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1932e00 } + }, +/* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x193ae00 } + }, +/* sbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x193ee00 } + }, +/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1952e00 } + }, +/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x195ae00 } + }, +/* sbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x195ee00 } + }, +/* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x197ee00 } + }, +/* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1972e00 } + }, +/* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x197ae00 } + }, +/* sbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1982e00 } + }, +/* sbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x190ae00 } + }, +/* sbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1902e00 } + }, +/* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1922e00 } + }, +/* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x192ae00 } + }, +/* sbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x192ee00 } + }, +/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1942e00 } + }, +/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x194ae00 } + }, +/* sbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x194ee00 } + }, +/* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x196ee00 } + }, +/* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1962e00 } + }, +/* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x196ae00 } + }, +/* sbb.w${X} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77700000 } + }, +/* sbb.w${X} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77740000 } + }, +/* sbb.w${X} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77760000 } + }, +/* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77780000 } + }, +/* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x777a0000 } + }, +/* sbb.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x777b0000 } + }, +/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x777c0000 } + }, +/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x777e0000 } + }, +/* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x777f0000 } + }, +/* sbb.b${X} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x767000 } + }, +/* sbb.b${X} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x767400 } + }, +/* sbb.b${X} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x767600 } + }, +/* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76780000 } + }, +/* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x767a0000 } + }, +/* sbb.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x767b0000 } + }, +/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x767c0000 } + }, +/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x767e0000 } + }, +/* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x767f0000 } + }, +/* rot.w r1h,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xa93f } + }, +/* rot.w r1h,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xa1bf } + }, +/* rot.w r1h,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xa13f } + }, +/* rot.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xa33f00 } + }, +/* rot.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xa53f0000 } + }, +/* rot.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xa73f0000 } + }, +/* rot.w r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa3bf00 } + }, +/* rot.w r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa5bf0000 } + }, +/* rot.w r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa3ff00 } + }, +/* rot.w r1h,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa5ff0000 } + }, +/* rot.w r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xa7ff0000 } + }, +/* rot.w r1h,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xa7bf0000 } + }, +/* rot.b r1h,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xa83f } + }, +/* rot.b r1h,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xa0bf } + }, +/* rot.b r1h,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xa03f } + }, +/* rot.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xa23f00 } + }, +/* rot.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xa43f0000 } + }, +/* rot.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xa63f0000 } + }, +/* rot.b r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa2bf00 } + }, +/* rot.b r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4bf0000 } + }, +/* rot.b r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2ff00 } + }, +/* rot.b r1h,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4ff0000 } + }, +/* rot.b r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xa6ff0000 } + }, +/* rot.b r1h,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xa6bf0000 } + }, +/* rot.w r1h,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNHI), 0 } }, + & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7560 } + }, +/* rot.w r1h,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANHI), 0 } }, + & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7564 } + }, +/* rot.w r1h,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7566 } + }, +/* rot.w r1h,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x756800 } + }, +/* rot.w r1h,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x756c0000 } + }, +/* rot.w r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x756a00 } + }, +/* rot.w r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x756e0000 } + }, +/* rot.w r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x756b00 } + }, +/* rot.w r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x756f0000 } + }, +/* rot.b r1h,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16RNHI), 0 } }, + & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7460 } + }, +/* rot.b r1h,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DST16ANHI), 0 } }, + & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7464 } + }, +/* rot.b r1h,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7466 } + }, +/* rot.b r1h,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x746800 } + }, +/* rot.b r1h,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x746c0000 } + }, +/* rot.b r1h,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x746a00 } + }, +/* rot.b r1h,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x746e0000 } + }, +/* rot.b r1h,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x746b00 } + }, +/* rot.b r1h,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x746f0000 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xe920 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xe1a0 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xe120 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xe32000 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xe5200000 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xe7200000 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xe3a000 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xe5a00000 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xe3e000 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xe5e00000 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xe7e00000 } + }, +/* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xe7a00000 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xe820 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xe0a0 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xe020 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xe22000 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xe4200000 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xe6200000 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xe2a000 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xe4a00000 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xe2e000 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xe4e00000 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xe6e00000 } + }, +/* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xe6a00000 } + }, +/* rot.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNHI), 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xe100 } + }, +/* rot.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANHI), 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_An_direct_HI, { 0xe104 } + }, +/* rot.w${Q} #${Imm-sh-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xe106 } + }, +/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xe10800 } + }, +/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xe10c0000 } + }, +/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xe10a00 } + }, +/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xe10e0000 } + }, +/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xe10b00 } + }, +/* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xe10f0000 } + }, +/* rot.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16RNQI), 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_Rn_direct_QI, { 0xe000 } + }, +/* rot.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DST16ANQI), 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_An_direct_QI, { 0xe004 } + }, +/* rot.b${Q} #${Imm-sh-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_An_indirect_QI, { 0xe006 } + }, +/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xe00800 } + }, +/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xe00c0000 } + }, +/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xe00a00 } + }, +/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xe00e0000 } + }, +/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xe00b00 } + }, +/* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_SH_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_b_imm4_Q_16_dst16_16_16_absolute_QI, { 0xe00f0000 } + }, +/* rorc.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa92e } + }, +/* rorc.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1ae } + }, +/* rorc.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa12e } + }, +/* rorc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa32e00 } + }, +/* rorc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa52e0000 } + }, +/* rorc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa72e0000 } + }, +/* rorc.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3ae00 } + }, +/* rorc.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5ae0000 } + }, +/* rorc.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ee00 } + }, +/* rorc.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ee0000 } + }, +/* rorc.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ee0000 } + }, +/* rorc.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7ae0000 } + }, +/* rorc.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa82e } + }, +/* rorc.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0ae } + }, +/* rorc.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa02e } + }, +/* rorc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa22e00 } + }, +/* rorc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa42e0000 } + }, +/* rorc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa62e0000 } + }, +/* rorc.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2ae00 } + }, +/* rorc.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4ae0000 } + }, +/* rorc.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ee00 } + }, +/* rorc.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ee0000 } + }, +/* rorc.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ee0000 } + }, +/* rorc.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6ae0000 } + }, +/* rorc.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77b0 } + }, +/* rorc.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77b4 } + }, +/* rorc.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77b6 } + }, +/* rorc.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77b800 } + }, +/* rorc.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77bc0000 } + }, +/* rorc.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77ba00 } + }, +/* rorc.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77be0000 } + }, +/* rorc.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77bb00 } + }, +/* rorc.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77bf0000 } + }, +/* rorc.b $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76b0 } + }, +/* rorc.b $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76b4 } + }, +/* rorc.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76b6 } + }, +/* rorc.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76b800 } + }, +/* rorc.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76bc0000 } + }, +/* rorc.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76ba00 } + }, +/* rorc.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76be0000 } + }, +/* rorc.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76bb00 } + }, +/* rorc.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76bf0000 } + }, +/* rolc.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb92e } + }, +/* rolc.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb1ae } + }, +/* rolc.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb12e } + }, +/* rolc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb32e00 } + }, +/* rolc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb52e0000 } + }, +/* rolc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb72e0000 } + }, +/* rolc.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb3ae00 } + }, +/* rolc.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb5ae0000 } + }, +/* rolc.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3ee00 } + }, +/* rolc.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5ee0000 } + }, +/* rolc.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7ee0000 } + }, +/* rolc.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb7ae0000 } + }, +/* rolc.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb82e } + }, +/* rolc.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb0ae } + }, +/* rolc.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb02e } + }, +/* rolc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb22e00 } + }, +/* rolc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb42e0000 } + }, +/* rolc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb62e0000 } + }, +/* rolc.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb2ae00 } + }, +/* rolc.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb4ae0000 } + }, +/* rolc.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2ee00 } + }, +/* rolc.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4ee0000 } + }, +/* rolc.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6ee0000 } + }, +/* rolc.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb6ae0000 } + }, +/* rolc.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77a0 } + }, +/* rolc.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77a4 } + }, +/* rolc.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77a6 } + }, +/* rolc.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77a800 } + }, +/* rolc.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77ac0000 } + }, +/* rolc.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77aa00 } + }, +/* rolc.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77ae0000 } + }, +/* rolc.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77ab00 } + }, +/* rolc.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77af0000 } + }, +/* rolc.b $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76a0 } + }, +/* rolc.b $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76a4 } + }, +/* rolc.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76a6 } + }, +/* rolc.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76a800 } + }, +/* rolc.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76ac0000 } + }, +/* rolc.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76aa00 } + }, +/* rolc.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76ae0000 } + }, +/* rolc.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76ab00 } + }, +/* rolc.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76af0000 } + }, +/* pusha [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_pusha32_16_Unprefixed_Mova_dst32_An_indirect_Unprefixed_Mova_SI, { 0xb001 } + }, +/* pusha ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xb20100 } + }, +/* pusha ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xb4010000 } + }, +/* pusha ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xb6010000 } + }, +/* pusha ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xb28100 } + }, +/* pusha ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xb4810000 } + }, +/* pusha ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xb2c100 } + }, +/* pusha ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xb4c10000 } + }, +/* pusha ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xb6c10000 } + }, +/* pusha ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_pusha32_16_Unprefixed_Mova_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xb6810000 } + }, +/* pusha [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0x7d96 } + }, +/* pusha ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0x7d9800 } + }, +/* pusha ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0x7d9c0000 } + }, +/* pusha ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0x7d9a00 } + }, +/* pusha ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0x7d9e0000 } + }, +/* pusha ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0x7d9b00 } + }, +/* pusha ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0x7d9f0000 } + }, +/* push.l $Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0xa801 } + }, +/* push.l $Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0xa081 } + }, +/* push.l [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0xa001 } + }, +/* push.l ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0xa20100 } + }, +/* push.l ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0xa4010000 } + }, +/* push.l ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0xa6010000 } + }, +/* push.l ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa28100 } + }, +/* push.l ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4810000 } + }, +/* push.l ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2c100 } + }, +/* push.l ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4c10000 } + }, +/* push.l ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0xa6c10000 } + }, +/* push.l ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0xa6810000 } + }, +/* push.w${S} ${An16-push-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (AN16_PUSH_S), 0 } }, + & ifmt_push16_b_s_an_An16_push_S_derived, { 0xc2 } + }, +/* push.b${S} ${Rn16-push-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (RN16_PUSH_S), 0 } }, + & ifmt_push16_b_s_rn_Rn16_push_S_derived, { 0x82 } + }, +/* push.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc90e } + }, +/* push.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc18e } + }, +/* push.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc10e } + }, +/* push.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30e00 } + }, +/* push.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50e0000 } + }, +/* push.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70e0000 } + }, +/* push.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38e00 } + }, +/* push.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58e0000 } + }, +/* push.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3ce00 } + }, +/* push.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5ce0000 } + }, +/* push.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7ce0000 } + }, +/* push.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc78e0000 } + }, +/* push.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xc80e } + }, +/* push.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xc08e } + }, +/* push.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xc00e } + }, +/* push.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20e00 } + }, +/* push.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40e0000 } + }, +/* push.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60e0000 } + }, +/* push.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28e00 } + }, +/* push.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48e0000 } + }, +/* push.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2ce00 } + }, +/* push.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4ce0000 } + }, +/* push.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xc6ce0000 } + }, +/* push.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc68e0000 } + }, +/* push.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7540 } + }, +/* push.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7544 } + }, +/* push.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7546 } + }, +/* push.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x754800 } + }, +/* push.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x754c0000 } + }, +/* push.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x754a00 } + }, +/* push.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x754e0000 } + }, +/* push.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x754b00 } + }, +/* push.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x754f0000 } + }, +/* push.b $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7440 } + }, +/* push.b $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7444 } + }, +/* push.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7446 } + }, +/* push.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x744800 } + }, +/* push.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x744c0000 } + }, +/* push.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x744a00 } + }, +/* push.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x744e0000 } + }, +/* push.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x744b00 } + }, +/* push.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x744f0000 } + }, +/* pop.w${S} ${An16-push-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (AN16_PUSH_S), 0 } }, + & ifmt_push16_b_s_an_An16_push_S_derived, { 0xd2 } + }, +/* pop.b${S} ${Rn16-push-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (RN16_PUSH_S), 0 } }, + & ifmt_push16_b_s_rn_Rn16_push_S_derived, { 0x92 } + }, +/* pop.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb92f } + }, +/* pop.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb1af } + }, +/* pop.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb12f } + }, +/* pop.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb32f00 } + }, +/* pop.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb52f0000 } + }, +/* pop.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb72f0000 } + }, +/* pop.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb3af00 } + }, +/* pop.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb5af0000 } + }, +/* pop.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3ef00 } + }, +/* pop.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5ef0000 } + }, +/* pop.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7ef0000 } + }, +/* pop.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb7af0000 } + }, +/* pop.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb82f } + }, +/* pop.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb0af } + }, +/* pop.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb02f } + }, +/* pop.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb22f00 } + }, +/* pop.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb42f0000 } + }, +/* pop.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb62f0000 } + }, +/* pop.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb2af00 } + }, +/* pop.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb4af0000 } + }, +/* pop.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2ef00 } + }, +/* pop.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4ef0000 } + }, +/* pop.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6ef0000 } + }, +/* pop.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb6af0000 } + }, +/* pop.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x75d0 } + }, +/* pop.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x75d4 } + }, +/* pop.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x75d6 } + }, +/* pop.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x75d800 } + }, +/* pop.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x75dc0000 } + }, +/* pop.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x75da00 } + }, +/* pop.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x75de0000 } + }, +/* pop.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x75db00 } + }, +/* pop.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x75df0000 } + }, +/* pop.b $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x74d0 } + }, +/* pop.b $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x74d4 } + }, +/* pop.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x74d6 } + }, +/* pop.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x74d800 } + }, +/* pop.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x74dc0000 } + }, +/* pop.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x74da00 } + }, +/* pop.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x74de0000 } + }, +/* pop.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x74db00 } + }, +/* pop.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x74df0000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990500 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992500 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993500 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918500 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a500 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b500 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910500 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912500 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913500 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93050000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93250000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93350000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95050000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95250000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95350000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97050000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97250000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97350000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93850000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a50000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b50000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95850000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a50000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b50000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c50000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e50000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f50000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c50000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e50000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f50000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c50000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e50000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f50000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97850000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a50000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b50000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9050000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9250000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9350000 } + }, +/* or.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9350000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1850000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a50000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b50000 } + }, +/* or.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b50000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1050000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1250000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1350000 } + }, +/* or.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1350000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3050000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3250000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3350000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3350000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5050000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5250000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5350000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5350000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7050000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7250000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7350000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7350000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3850000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a50000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b50000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b50000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5850000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a50000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b50000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b50000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c50000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e50000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f50000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f50000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c50000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e50000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f50000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f50000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c50000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e50000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f50000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f50000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7850000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a50000 } + }, +/* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b50000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b50000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9050000 } + }, +/* or.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9250000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1850000 } + }, +/* or.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a50000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1050000 } + }, +/* or.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1250000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3050000 } + }, +/* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3250000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5050000 } + }, +/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5250000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7050000 } + }, +/* or.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7250000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3850000 } + }, +/* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a50000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5850000 } + }, +/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a50000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c50000 } + }, +/* or.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e50000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c50000 } + }, +/* or.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e50000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c50000 } + }, +/* or.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e50000 } + }, +/* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7850000 } + }, +/* or.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a50000 } + }, +/* or.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc905 } + }, +/* or.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8925 } + }, +/* or.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8905 } + }, +/* or.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc185 } + }, +/* or.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a5 } + }, +/* or.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8185 } + }, +/* or.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc105 } + }, +/* or.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8125 } + }, +/* or.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8105 } + }, +/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30500 } + }, +/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832500 } + }, +/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830500 } + }, +/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5050000 } + }, +/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85250000 } + }, +/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85050000 } + }, +/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7050000 } + }, +/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87250000 } + }, +/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87050000 } + }, +/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38500 } + }, +/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a500 } + }, +/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838500 } + }, +/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5850000 } + }, +/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a50000 } + }, +/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85850000 } + }, +/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c500 } + }, +/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e500 } + }, +/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c500 } + }, +/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c50000 } + }, +/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e50000 } + }, +/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c50000 } + }, +/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c50000 } + }, +/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e50000 } + }, +/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c50000 } + }, +/* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7850000 } + }, +/* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a50000 } + }, +/* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87850000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980500 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982500 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983500 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908500 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a500 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b500 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900500 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902500 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903500 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92050000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92250000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92350000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94050000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94250000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94350000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96050000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96250000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96350000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92850000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a50000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b50000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94850000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a50000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b50000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c50000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e50000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f50000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c50000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e50000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f50000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c50000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e50000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f50000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96850000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a50000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b50000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8050000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8250000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8350000 } + }, +/* or.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8350000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0850000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a50000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b50000 } + }, +/* or.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b50000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0050000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0250000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0350000 } + }, +/* or.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0350000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2050000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2250000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2350000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2350000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4050000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4250000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4350000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4350000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6050000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6250000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6350000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6350000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2850000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a50000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b50000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b50000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4850000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a50000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b50000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b50000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c50000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e50000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f50000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f50000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c50000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e50000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f50000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f50000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c50000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e50000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f50000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f50000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6850000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a50000 } + }, +/* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b50000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b50000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8050000 } + }, +/* or.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8250000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0850000 } + }, +/* or.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a50000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0050000 } + }, +/* or.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0250000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2050000 } + }, +/* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2250000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4050000 } + }, +/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4250000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6050000 } + }, +/* or.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6250000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2850000 } + }, +/* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a50000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4850000 } + }, +/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a50000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c50000 } + }, +/* or.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e50000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c50000 } + }, +/* or.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e50000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c50000 } + }, +/* or.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e50000 } + }, +/* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6850000 } + }, +/* or.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a50000 } + }, +/* or.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc805 } + }, +/* or.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8825 } + }, +/* or.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8805 } + }, +/* or.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc085 } + }, +/* or.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a5 } + }, +/* or.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8085 } + }, +/* or.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc005 } + }, +/* or.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8025 } + }, +/* or.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8005 } + }, +/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20500 } + }, +/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822500 } + }, +/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820500 } + }, +/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4050000 } + }, +/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84250000 } + }, +/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84050000 } + }, +/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6050000 } + }, +/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86250000 } + }, +/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86050000 } + }, +/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28500 } + }, +/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a500 } + }, +/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828500 } + }, +/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4850000 } + }, +/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a50000 } + }, +/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84850000 } + }, +/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c500 } + }, +/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e500 } + }, +/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c500 } + }, +/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c50000 } + }, +/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e50000 } + }, +/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c50000 } + }, +/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c50000 } + }, +/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e50000 } + }, +/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c50000 } + }, +/* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6850000 } + }, +/* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a50000 } + }, +/* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86850000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x998000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x99a000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x99b000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x998400 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x99a400 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x99b400 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x998600 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x99a600 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x99b600 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x99880000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x99a80000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x99b80000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x998c0000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x99ac0000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x99bc0000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x998a0000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x99aa0000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x99ba0000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x998e0000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x99ae0000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x99be0000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x998b0000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x99ab0000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x99bb0000 } + }, +/* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x998f0000 } + }, +/* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x99af0000 } + }, +/* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x99bf0000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x99c00000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x99e00000 } + }, +/* or.w${G} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x99f00000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x99c40000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x99e40000 } + }, +/* or.w${G} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x99f40000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x99c60000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x99e60000 } + }, +/* or.w${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x99f60000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x99c80000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x99e80000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x99f80000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x99cc0000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x99ec0000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x99fc0000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x99ca0000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x99ea0000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x99fa0000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x99ce0000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x99ee0000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x99fe0000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x99cb0000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x99eb0000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x99fb0000 } + }, +/* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x99cf0000 } + }, +/* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x99ef0000 } + }, +/* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x99ff0000 } + }, +/* or.w${G} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x9900 } + }, +/* or.w${G} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x9940 } + }, +/* or.w${G} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x9960 } + }, +/* or.w${G} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x9904 } + }, +/* or.w${G} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x9944 } + }, +/* or.w${G} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x9964 } + }, +/* or.w${G} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x9906 } + }, +/* or.w${G} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x9946 } + }, +/* or.w${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x9966 } + }, +/* or.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x990800 } + }, +/* or.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x994800 } + }, +/* or.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x996800 } + }, +/* or.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x990c0000 } + }, +/* or.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x994c0000 } + }, +/* or.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x996c0000 } + }, +/* or.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x990a00 } + }, +/* or.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x994a00 } + }, +/* or.w${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x996a00 } + }, +/* or.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x990e0000 } + }, +/* or.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x994e0000 } + }, +/* or.w${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x996e0000 } + }, +/* or.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x990b00 } + }, +/* or.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x994b00 } + }, +/* or.w${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x996b00 } + }, +/* or.w${G} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x990f0000 } + }, +/* or.w${G} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x994f0000 } + }, +/* or.w${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x996f0000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x988000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x98a000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x98b000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x988400 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x98a400 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x98b400 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x988600 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x98a600 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x98b600 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x98880000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x98a80000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x98b80000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x988c0000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x98ac0000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x98bc0000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x988a0000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x98aa0000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x98ba0000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x988e0000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x98ae0000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x98be0000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x988b0000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x98ab0000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x98bb0000 } + }, +/* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x988f0000 } + }, +/* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x98af0000 } + }, +/* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x98bf0000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x98c00000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x98e00000 } + }, +/* or.b${G} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x98f00000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x98c40000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x98e40000 } + }, +/* or.b${G} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x98f40000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x98c60000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x98e60000 } + }, +/* or.b${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x98f60000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x98c80000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x98e80000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x98f80000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x98cc0000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x98ec0000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x98fc0000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x98ca0000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x98ea0000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x98fa0000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x98ce0000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x98ee0000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x98fe0000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x98cb0000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x98eb0000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x98fb0000 } + }, +/* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x98cf0000 } + }, +/* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x98ef0000 } + }, +/* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x98ff0000 } + }, +/* or.b${G} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x9800 } + }, +/* or.b${G} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x9840 } + }, +/* or.b${G} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x9860 } + }, +/* or.b${G} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x9804 } + }, +/* or.b${G} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x9844 } + }, +/* or.b${G} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x9864 } + }, +/* or.b${G} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x9806 } + }, +/* or.b${G} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x9846 } + }, +/* or.b${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x9866 } + }, +/* or.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x980800 } + }, +/* or.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x984800 } + }, +/* or.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x986800 } + }, +/* or.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x980c0000 } + }, +/* or.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x984c0000 } + }, +/* or.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x986c0000 } + }, +/* or.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x980a00 } + }, +/* or.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x984a00 } + }, +/* or.b${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x986a00 } + }, +/* or.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x980e0000 } + }, +/* or.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x984e0000 } + }, +/* or.b${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x986e0000 } + }, +/* or.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x980b00 } + }, +/* or.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x984b00 } + }, +/* or.b${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x986b00 } + }, +/* or.b${G} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x980f0000 } + }, +/* or.b${G} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x984f0000 } + }, +/* or.b${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x986f0000 } + }, +/* or.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x65000000 } + }, +/* or.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x75000000 } + }, +/* or.w${S} #${Imm-24-HI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x55000000 } + }, +/* or.w${S} #${Imm-8-HI},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } }, + & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x450000 } + }, +/* or.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x640000 } + }, +/* or.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x740000 } + }, +/* or.b${S} #${Imm-24-QI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x54000000 } + }, +/* or.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x4400 } + }, +/* or.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0x9c00 } + }, +/* or.b${S} #${Imm-8-QI},r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0x9b00 } + }, +/* or.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0x9d0000 } + }, +/* or.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0x9e0000 } + }, +/* or.b${S} #${Imm-8-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0x9f000000 } + }, +/* or.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x892f0000 } + }, +/* or.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x81af0000 } + }, +/* or.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x812f0000 } + }, +/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x832f0000 } + }, +/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83af0000 } + }, +/* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ef0000 } + }, +/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x852f0000 } + }, +/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85af0000 } + }, +/* or.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ef0000 } + }, +/* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87ef0000 } + }, +/* or.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x872f0000 } + }, +/* or.w${G} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x87af0000 } + }, +/* or.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x882f00 } + }, +/* or.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x80af00 } + }, +/* or.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x802f00 } + }, +/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x822f0000 } + }, +/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82af0000 } + }, +/* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ef0000 } + }, +/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x842f0000 } + }, +/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84af0000 } + }, +/* or.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ef0000 } + }, +/* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86ef0000 } + }, +/* or.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x862f0000 } + }, +/* or.b${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x86af0000 } + }, +/* or.w${G} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77300000 } + }, +/* or.w${G} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77340000 } + }, +/* or.w${G} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77360000 } + }, +/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77380000 } + }, +/* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x773a0000 } + }, +/* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x773b0000 } + }, +/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x773c0000 } + }, +/* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x773e0000 } + }, +/* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x773f0000 } + }, +/* or.b${G} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x763000 } + }, +/* or.b${G} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x763400 } + }, +/* or.b${G} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x763600 } + }, +/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76380000 } + }, +/* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x763a0000 } + }, +/* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x763b0000 } + }, +/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x763c0000 } + }, +/* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x763e0000 } + }, +/* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x763f0000 } + }, +/* not.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa91e } + }, +/* not.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa19e } + }, +/* not.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa11e } + }, +/* not.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa31e00 } + }, +/* not.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa51e0000 } + }, +/* not.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa71e0000 } + }, +/* not.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa39e00 } + }, +/* not.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa59e0000 } + }, +/* not.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3de00 } + }, +/* not.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5de0000 } + }, +/* not.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7de0000 } + }, +/* not.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa79e0000 } + }, +/* not.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa81e } + }, +/* not.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa09e } + }, +/* not.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa01e } + }, +/* not.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa21e00 } + }, +/* not.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa41e0000 } + }, +/* not.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa61e0000 } + }, +/* not.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa29e00 } + }, +/* not.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa49e0000 } + }, +/* not.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2de00 } + }, +/* not.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4de0000 } + }, +/* not.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6de0000 } + }, +/* not.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa69e0000 } + }, +/* not.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7570 } + }, +/* not.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7574 } + }, +/* not.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7576 } + }, +/* not.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x757800 } + }, +/* not.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x757c0000 } + }, +/* not.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x757a00 } + }, +/* not.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x757e0000 } + }, +/* not.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x757b00 } + }, +/* not.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x757f0000 } + }, +/* not.b $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7470 } + }, +/* not.b $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7474 } + }, +/* not.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7476 } + }, +/* not.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x747800 } + }, +/* not.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x747c0000 } + }, +/* not.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x747a00 } + }, +/* not.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x747e0000 } + }, +/* not.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x747b00 } + }, +/* not.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x747f0000 } + }, +/* neg.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa92f } + }, +/* neg.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa1af } + }, +/* neg.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa12f } + }, +/* neg.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa32f00 } + }, +/* neg.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa52f0000 } + }, +/* neg.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa72f0000 } + }, +/* neg.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa3af00 } + }, +/* neg.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa5af0000 } + }, +/* neg.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ef00 } + }, +/* neg.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ef0000 } + }, +/* neg.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ef0000 } + }, +/* neg.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa7af0000 } + }, +/* neg.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa82f } + }, +/* neg.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0af } + }, +/* neg.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa02f } + }, +/* neg.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa22f00 } + }, +/* neg.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa42f0000 } + }, +/* neg.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa62f0000 } + }, +/* neg.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2af00 } + }, +/* neg.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4af0000 } + }, +/* neg.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ef00 } + }, +/* neg.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ef0000 } + }, +/* neg.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ef0000 } + }, +/* neg.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6af0000 } + }, +/* neg.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7550 } + }, +/* neg.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7554 } + }, +/* neg.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7556 } + }, +/* neg.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x755800 } + }, +/* neg.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x755c0000 } + }, +/* neg.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x755a00 } + }, +/* neg.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x755e0000 } + }, +/* neg.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x755b00 } + }, +/* neg.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x755f0000 } + }, +/* neg.b $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7450 } + }, +/* neg.b $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7454 } + }, +/* neg.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7456 } + }, +/* neg.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x745800 } + }, +/* neg.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x745c0000 } + }, +/* neg.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x745a00 } + }, +/* neg.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x745e0000 } + }, +/* neg.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x745b00 } + }, +/* neg.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x745f0000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990400 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992400 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993400 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918400 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a400 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b400 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910400 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912400 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913400 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93040000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93240000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93340000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95040000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95240000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95340000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97040000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97240000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97340000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93840000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a40000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b40000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95840000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a40000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b40000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c40000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e40000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f40000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c40000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e40000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f40000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c40000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e40000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f40000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97840000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a40000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9040000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9240000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9340000 } + }, +/* mulu.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9340000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1840000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a40000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b40000 } + }, +/* mulu.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1040000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1240000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1340000 } + }, +/* mulu.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1340000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3040000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3240000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3340000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3340000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5040000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5240000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5340000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5340000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7040000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7240000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7340000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7340000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3840000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a40000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b40000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5840000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a40000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b40000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e40000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f40000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e40000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f40000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e40000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f40000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7840000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a40000 } + }, +/* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b40000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b40000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9040000 } + }, +/* mulu.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9240000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1840000 } + }, +/* mulu.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a40000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1040000 } + }, +/* mulu.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1240000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3040000 } + }, +/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3240000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5040000 } + }, +/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5240000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7040000 } + }, +/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7240000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3840000 } + }, +/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a40000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5840000 } + }, +/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a40000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c40000 } + }, +/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e40000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c40000 } + }, +/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e40000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c40000 } + }, +/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e40000 } + }, +/* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7840000 } + }, +/* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a40000 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc904 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8924 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8904 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc184 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a4 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8184 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc104 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8124 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8104 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30400 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832400 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830400 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5040000 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85240000 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85040000 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7040000 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87240000 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87040000 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38400 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a400 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838400 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5840000 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a40000 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85840000 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c400 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e400 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c400 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c40000 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e40000 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c40000 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c40000 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e40000 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c40000 } + }, +/* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7840000 } + }, +/* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a40000 } + }, +/* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87840000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980400 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982400 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983400 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908400 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a400 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b400 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900400 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902400 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903400 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92040000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92240000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92340000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94040000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94240000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94340000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96040000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96240000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96340000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92840000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a40000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b40000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94840000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a40000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b40000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c40000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e40000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f40000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c40000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e40000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f40000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c40000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e40000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f40000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96840000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a40000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8040000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8240000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8340000 } + }, +/* mulu.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8340000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0840000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a40000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b40000 } + }, +/* mulu.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0040000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0240000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0340000 } + }, +/* mulu.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0340000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2040000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2240000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2340000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2340000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4040000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4240000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4340000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4340000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6040000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6240000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6340000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6340000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2840000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a40000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b40000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4840000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a40000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b40000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e40000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f40000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e40000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f40000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e40000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f40000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6840000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a40000 } + }, +/* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b40000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b40000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8040000 } + }, +/* mulu.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8240000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0840000 } + }, +/* mulu.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a40000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0040000 } + }, +/* mulu.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0240000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2040000 } + }, +/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2240000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4040000 } + }, +/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4240000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6040000 } + }, +/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6240000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2840000 } + }, +/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a40000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4840000 } + }, +/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a40000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c40000 } + }, +/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e40000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c40000 } + }, +/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e40000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c40000 } + }, +/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e40000 } + }, +/* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6840000 } + }, +/* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a40000 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc804 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8824 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8804 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc084 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a4 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8084 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc004 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8024 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8004 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20400 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822400 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820400 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4040000 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84240000 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84040000 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6040000 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86240000 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86040000 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28400 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a400 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828400 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4840000 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a40000 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84840000 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c400 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e400 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c400 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c40000 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e40000 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c40000 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c40000 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e40000 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c40000 } + }, +/* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6840000 } + }, +/* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a40000 } + }, +/* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86840000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x718000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x71a000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x71b000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x718400 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x71a400 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x71b400 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x718600 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x71a600 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x71b600 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x71880000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x71a80000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x71b80000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x718c0000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x71ac0000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x71bc0000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x718a0000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x71aa0000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x71ba0000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x718e0000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x71ae0000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x71be0000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x718b0000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x71ab0000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x71bb0000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x718f0000 } + }, +/* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x71af0000 } + }, +/* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x71bf0000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x71c00000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x71e00000 } + }, +/* mulu.w${G} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x71f00000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x71c40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x71e40000 } + }, +/* mulu.w${G} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x71f40000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x71c60000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x71e60000 } + }, +/* mulu.w${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x71f60000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x71c80000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x71e80000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x71f80000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x71cc0000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x71ec0000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x71fc0000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x71ca0000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x71ea0000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x71fa0000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x71ce0000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x71ee0000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x71fe0000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x71cb0000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x71eb0000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x71fb0000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x71cf0000 } + }, +/* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x71ef0000 } + }, +/* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x71ff0000 } + }, +/* mulu.w${G} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x7100 } + }, +/* mulu.w${G} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x7140 } + }, +/* mulu.w${G} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x7160 } + }, +/* mulu.w${G} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x7104 } + }, +/* mulu.w${G} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x7144 } + }, +/* mulu.w${G} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x7164 } + }, +/* mulu.w${G} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x7106 } + }, +/* mulu.w${G} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x7146 } + }, +/* mulu.w${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x7166 } + }, +/* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x710800 } + }, +/* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x714800 } + }, +/* mulu.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x716800 } + }, +/* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x710c0000 } + }, +/* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x714c0000 } + }, +/* mulu.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x716c0000 } + }, +/* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x710a00 } + }, +/* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x714a00 } + }, +/* mulu.w${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x716a00 } + }, +/* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x710e0000 } + }, +/* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x714e0000 } + }, +/* mulu.w${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x716e0000 } + }, +/* mulu.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x710b00 } + }, +/* mulu.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x714b00 } + }, +/* mulu.w${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x716b00 } + }, +/* mulu.w${G} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x710f0000 } + }, +/* mulu.w${G} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x714f0000 } + }, +/* mulu.w${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x716f0000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x708000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x70a000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x70b000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x708400 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x70a400 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x70b400 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x708600 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x70a600 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x70b600 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x70880000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x70a80000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x70b80000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x708c0000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x70ac0000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x70bc0000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x708a0000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x70aa0000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x70ba0000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x708e0000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x70ae0000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x70be0000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x708b0000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x70ab0000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x70bb0000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x708f0000 } + }, +/* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x70af0000 } + }, +/* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x70bf0000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x70c00000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x70e00000 } + }, +/* mulu.b${G} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x70f00000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x70c40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x70e40000 } + }, +/* mulu.b${G} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x70f40000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x70c60000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x70e60000 } + }, +/* mulu.b${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x70f60000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x70c80000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x70e80000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x70f80000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x70cc0000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x70ec0000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x70fc0000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x70ca0000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x70ea0000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x70fa0000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x70ce0000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x70ee0000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x70fe0000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x70cb0000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x70eb0000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x70fb0000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x70cf0000 } + }, +/* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x70ef0000 } + }, +/* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x70ff0000 } + }, +/* mulu.b${G} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x7000 } + }, +/* mulu.b${G} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x7040 } + }, +/* mulu.b${G} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x7060 } + }, +/* mulu.b${G} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x7004 } + }, +/* mulu.b${G} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x7044 } + }, +/* mulu.b${G} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x7064 } + }, +/* mulu.b${G} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x7006 } + }, +/* mulu.b${G} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x7046 } + }, +/* mulu.b${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x7066 } + }, +/* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x700800 } + }, +/* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x704800 } + }, +/* mulu.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x706800 } + }, +/* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x700c0000 } + }, +/* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x704c0000 } + }, +/* mulu.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x706c0000 } + }, +/* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x700a00 } + }, +/* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x704a00 } + }, +/* mulu.b${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x706a00 } + }, +/* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x700e0000 } + }, +/* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x704e0000 } + }, +/* mulu.b${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x706e0000 } + }, +/* mulu.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x700b00 } + }, +/* mulu.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x704b00 } + }, +/* mulu.b${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x706b00 } + }, +/* mulu.b${G} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x700f0000 } + }, +/* mulu.b${G} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x704f0000 } + }, +/* mulu.b${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x706f0000 } + }, +/* mulu.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x890f0000 } + }, +/* mulu.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x818f0000 } + }, +/* mulu.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x810f0000 } + }, +/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x830f0000 } + }, +/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838f0000 } + }, +/* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83cf0000 } + }, +/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x850f0000 } + }, +/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858f0000 } + }, +/* mulu.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85cf0000 } + }, +/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87cf0000 } + }, +/* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x870f0000 } + }, +/* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x878f0000 } + }, +/* mulu.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x880f00 } + }, +/* mulu.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x808f00 } + }, +/* mulu.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x800f00 } + }, +/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x820f0000 } + }, +/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828f0000 } + }, +/* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82cf0000 } + }, +/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x840f0000 } + }, +/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848f0000 } + }, +/* mulu.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84cf0000 } + }, +/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86cf0000 } + }, +/* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x860f0000 } + }, +/* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x868f0000 } + }, +/* mulu.w${G} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x7d400000 } + }, +/* mulu.w${G} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x7d440000 } + }, +/* mulu.w${G} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x7d460000 } + }, +/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x7d480000 } + }, +/* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x7d4a0000 } + }, +/* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x7d4b0000 } + }, +/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x7d4c0000 } + }, +/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x7d4e0000 } + }, +/* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x7d4f0000 } + }, +/* mulu.b${G} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x7c4000 } + }, +/* mulu.b${G} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x7c4400 } + }, +/* mulu.b${G} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x7c4600 } + }, +/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x7c480000 } + }, +/* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x7c4a0000 } + }, +/* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x7c4b0000 } + }, +/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x7c4c0000 } + }, +/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x7c4e0000 } + }, +/* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x7c4f0000 } + }, +/* mulex $R3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (R3), 0 } }, + & ifmt_mulex_dst32_R3_direct_Unprefixed_HI, { 0xc97e } + }, +/* mulex $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc1be } + }, +/* mulex [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc13e } + }, +/* mulex ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc33e00 } + }, +/* mulex ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc53e0000 } + }, +/* mulex ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc73e0000 } + }, +/* mulex ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc3be00 } + }, +/* mulex ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5be0000 } + }, +/* mulex ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3fe00 } + }, +/* mulex ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5fe0000 } + }, +/* mulex ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7fe0000 } + }, +/* mulex ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc7be0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990c00 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992c00 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993c00 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918c00 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91ac00 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91bc00 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910c00 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912c00 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913c00 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x930c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x932c0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x933c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x950c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x952c0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x953c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x970c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x972c0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x973c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x938c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93ac0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93bc0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x958c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95ac0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95bc0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93cc0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93ec0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93fc0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95cc0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95ec0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95fc0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97cc0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97ec0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97fc0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x978c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97ac0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97bc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa90c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa92c0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa93c0000 } + }, +/* mul.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb93c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa18c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1ac0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1bc0000 } + }, +/* mul.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1bc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa10c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa12c0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa13c0000 } + }, +/* mul.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb13c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa30c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa32c0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa33c0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb33c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa50c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa52c0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa53c0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb53c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa70c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa72c0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa73c0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb73c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa38c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3ac0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3bc0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3bc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa58c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5ac0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5bc0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5bc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3cc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3ec0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3fc0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3fc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5cc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5ec0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5fc0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5fc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7cc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7ec0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7fc0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7fc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa78c0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7ac0000 } + }, +/* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7bc0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7bc0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb90c0000 } + }, +/* mul.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb92c0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb18c0000 } + }, +/* mul.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1ac0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb10c0000 } + }, +/* mul.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb12c0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb30c0000 } + }, +/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb32c0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb50c0000 } + }, +/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb52c0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb70c0000 } + }, +/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb72c0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb38c0000 } + }, +/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3ac0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb58c0000 } + }, +/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5ac0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3cc0000 } + }, +/* mul.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3ec0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5cc0000 } + }, +/* mul.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5ec0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7cc0000 } + }, +/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7ec0000 } + }, +/* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb78c0000 } + }, +/* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7ac0000 } + }, +/* mul.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc90c } + }, +/* mul.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x892c } + }, +/* mul.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x890c } + }, +/* mul.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc18c } + }, +/* mul.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81ac } + }, +/* mul.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x818c } + }, +/* mul.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc10c } + }, +/* mul.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x812c } + }, +/* mul.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x810c } + }, +/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30c00 } + }, +/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832c00 } + }, +/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830c00 } + }, +/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50c0000 } + }, +/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x852c0000 } + }, +/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x850c0000 } + }, +/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70c0000 } + }, +/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x872c0000 } + }, +/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x870c0000 } + }, +/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38c00 } + }, +/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83ac00 } + }, +/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838c00 } + }, +/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58c0000 } + }, +/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85ac0000 } + }, +/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858c0000 } + }, +/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3cc00 } + }, +/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ec00 } + }, +/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83cc00 } + }, +/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5cc0000 } + }, +/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ec0000 } + }, +/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85cc0000 } + }, +/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7cc0000 } + }, +/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87ec0000 } + }, +/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87cc0000 } + }, +/* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc78c0000 } + }, +/* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87ac0000 } + }, +/* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x878c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980c00 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982c00 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983c00 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908c00 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90ac00 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90bc00 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900c00 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902c00 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903c00 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x920c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x922c0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x923c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x940c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x942c0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x943c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x960c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x962c0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x963c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x928c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92ac0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92bc0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x948c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94ac0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94bc0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92cc0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92ec0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92fc0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94cc0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94ec0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94fc0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96cc0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96ec0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96fc0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x968c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96ac0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96bc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa80c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa82c0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa83c0000 } + }, +/* mul.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb83c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa08c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0ac0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0bc0000 } + }, +/* mul.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0bc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa00c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa02c0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa03c0000 } + }, +/* mul.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb03c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa20c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa22c0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa23c0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb23c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa40c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa42c0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa43c0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb43c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa60c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa62c0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa63c0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb63c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa28c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2ac0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2bc0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2bc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa48c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4ac0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4bc0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4bc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2cc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2ec0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2fc0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2fc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4cc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4ec0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4fc0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4fc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6cc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6ec0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6fc0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6fc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa68c0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6ac0000 } + }, +/* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6bc0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6bc0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb80c0000 } + }, +/* mul.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb82c0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb08c0000 } + }, +/* mul.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0ac0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb00c0000 } + }, +/* mul.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb02c0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb20c0000 } + }, +/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb22c0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb40c0000 } + }, +/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb42c0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb60c0000 } + }, +/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb62c0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb28c0000 } + }, +/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2ac0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb48c0000 } + }, +/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4ac0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2cc0000 } + }, +/* mul.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2ec0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4cc0000 } + }, +/* mul.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4ec0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6cc0000 } + }, +/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6ec0000 } + }, +/* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb68c0000 } + }, +/* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6ac0000 } + }, +/* mul.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc80c } + }, +/* mul.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x882c } + }, +/* mul.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x880c } + }, +/* mul.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc08c } + }, +/* mul.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80ac } + }, +/* mul.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x808c } + }, +/* mul.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc00c } + }, +/* mul.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x802c } + }, +/* mul.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x800c } + }, +/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20c00 } + }, +/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822c00 } + }, +/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820c00 } + }, +/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40c0000 } + }, +/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x842c0000 } + }, +/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x840c0000 } + }, +/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60c0000 } + }, +/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x862c0000 } + }, +/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x860c0000 } + }, +/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28c00 } + }, +/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82ac00 } + }, +/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828c00 } + }, +/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48c0000 } + }, +/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84ac0000 } + }, +/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848c0000 } + }, +/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2cc00 } + }, +/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ec00 } + }, +/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82cc00 } + }, +/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4cc0000 } + }, +/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ec0000 } + }, +/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84cc0000 } + }, +/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6cc0000 } + }, +/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86ec0000 } + }, +/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86cc0000 } + }, +/* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc68c0000 } + }, +/* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86ac0000 } + }, +/* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x868c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x798000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x79a000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x79b000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x798400 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x79a400 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x79b400 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x798600 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x79a600 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x79b600 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x79880000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x79a80000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x79b80000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x798c0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x79ac0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x79bc0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x798a0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x79aa0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x79ba0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x798e0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x79ae0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x79be0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x798b0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x79ab0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x79bb0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x798f0000 } + }, +/* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x79af0000 } + }, +/* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x79bf0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x79c00000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x79e00000 } + }, +/* mul.w${G} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x79f00000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x79c40000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x79e40000 } + }, +/* mul.w${G} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x79f40000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x79c60000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x79e60000 } + }, +/* mul.w${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x79f60000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x79c80000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x79e80000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x79f80000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x79cc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x79ec0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x79fc0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x79ca0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x79ea0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x79fa0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x79ce0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x79ee0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x79fe0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x79cb0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x79eb0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x79fb0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x79cf0000 } + }, +/* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x79ef0000 } + }, +/* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x79ff0000 } + }, +/* mul.w${G} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x7900 } + }, +/* mul.w${G} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x7940 } + }, +/* mul.w${G} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x7960 } + }, +/* mul.w${G} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x7904 } + }, +/* mul.w${G} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x7944 } + }, +/* mul.w${G} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x7964 } + }, +/* mul.w${G} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x7906 } + }, +/* mul.w${G} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x7946 } + }, +/* mul.w${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x7966 } + }, +/* mul.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x790800 } + }, +/* mul.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x794800 } + }, +/* mul.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x796800 } + }, +/* mul.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x790c0000 } + }, +/* mul.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x794c0000 } + }, +/* mul.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x796c0000 } + }, +/* mul.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x790a00 } + }, +/* mul.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x794a00 } + }, +/* mul.w${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x796a00 } + }, +/* mul.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x790e0000 } + }, +/* mul.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x794e0000 } + }, +/* mul.w${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x796e0000 } + }, +/* mul.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x790b00 } + }, +/* mul.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x794b00 } + }, +/* mul.w${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x796b00 } + }, +/* mul.w${G} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x790f0000 } + }, +/* mul.w${G} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x794f0000 } + }, +/* mul.w${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x796f0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x788000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x78a000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x78b000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x788400 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x78a400 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x78b400 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x788600 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x78a600 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x78b600 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x78880000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x78a80000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x78b80000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x788c0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x78ac0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x78bc0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x788a0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x78aa0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x78ba0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x788e0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x78ae0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x78be0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x788b0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x78ab0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x78bb0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x788f0000 } + }, +/* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x78af0000 } + }, +/* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x78bf0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x78c00000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x78e00000 } + }, +/* mul.b${G} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x78f00000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x78c40000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x78e40000 } + }, +/* mul.b${G} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x78f40000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x78c60000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x78e60000 } + }, +/* mul.b${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x78f60000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x78c80000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x78e80000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x78f80000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x78cc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x78ec0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x78fc0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x78ca0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x78ea0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x78fa0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x78ce0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x78ee0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x78fe0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x78cb0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x78eb0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x78fb0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x78cf0000 } + }, +/* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x78ef0000 } + }, +/* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x78ff0000 } + }, +/* mul.b${G} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x7800 } + }, +/* mul.b${G} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x7840 } + }, +/* mul.b${G} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x7860 } + }, +/* mul.b${G} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x7804 } + }, +/* mul.b${G} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x7844 } + }, +/* mul.b${G} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x7864 } + }, +/* mul.b${G} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x7806 } + }, +/* mul.b${G} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x7846 } + }, +/* mul.b${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x7866 } + }, +/* mul.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x780800 } + }, +/* mul.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x784800 } + }, +/* mul.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x786800 } + }, +/* mul.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x780c0000 } + }, +/* mul.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x784c0000 } + }, +/* mul.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x786c0000 } + }, +/* mul.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x780a00 } + }, +/* mul.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x784a00 } + }, +/* mul.b${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x786a00 } + }, +/* mul.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x780e0000 } + }, +/* mul.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x784e0000 } + }, +/* mul.b${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x786e0000 } + }, +/* mul.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x780b00 } + }, +/* mul.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x784b00 } + }, +/* mul.b${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x786b00 } + }, +/* mul.b${G} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x780f0000 } + }, +/* mul.b${G} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x784f0000 } + }, +/* mul.b${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x786f0000 } + }, +/* mul.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x891f0000 } + }, +/* mul.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x819f0000 } + }, +/* mul.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x811f0000 } + }, +/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x831f0000 } + }, +/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x839f0000 } + }, +/* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83df0000 } + }, +/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x851f0000 } + }, +/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x859f0000 } + }, +/* mul.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85df0000 } + }, +/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87df0000 } + }, +/* mul.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x871f0000 } + }, +/* mul.w${G} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x879f0000 } + }, +/* mul.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x881f00 } + }, +/* mul.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x809f00 } + }, +/* mul.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x801f00 } + }, +/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x821f0000 } + }, +/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x829f0000 } + }, +/* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82df0000 } + }, +/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x841f0000 } + }, +/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x849f0000 } + }, +/* mul.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84df0000 } + }, +/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86df0000 } + }, +/* mul.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x861f0000 } + }, +/* mul.b${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x869f0000 } + }, +/* mul.w${G} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x7d500000 } + }, +/* mul.w${G} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x7d540000 } + }, +/* mul.w${G} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x7d560000 } + }, +/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x7d580000 } + }, +/* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x7d5a0000 } + }, +/* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x7d5b0000 } + }, +/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x7d5c0000 } + }, +/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x7d5e0000 } + }, +/* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x7d5f0000 } + }, +/* mul.b${G} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x7c5000 } + }, +/* mul.b${G} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x7c5400 } + }, +/* mul.b${G} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x7c5600 } + }, +/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x7c580000 } + }, +/* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x7c5a0000 } + }, +/* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x7c5b0000 } + }, +/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x7c5c0000 } + }, +/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x7c5e0000 } + }, +/* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x7c5f0000 } + }, +/* movx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xb81100 } + }, +/* movx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xb09100 } + }, +/* movx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xb01100 } + }, +/* movx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xb2110000 } + }, +/* movx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xb2910000 } + }, +/* movx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xb2d10000 } + }, +/* movx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xb4110000 } + }, +/* movx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xb4910000 } + }, +/* movx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xb4d10000 } + }, +/* movx${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xb6d10000 } + }, +/* movx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xb6110000 } + }, +/* movx${X} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xb6910000 } + }, +/* movhh $Dst32RnPrefixedQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNPREFIXEDQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1a83e } + }, +/* movhh $Dst32AnPrefixedQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANPREFIXEDQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1a0be } + }, +/* movhh [$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1a03e } + }, +/* movhh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1a23e00 } + }, +/* movhh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1a43e00 } + }, +/* movhh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1a63e00 } + }, +/* movhh ${Dsp-24-u8}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1a2be00 } + }, +/* movhh ${Dsp-24-u16}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1a4be00 } + }, +/* movhh ${Dsp-24-s8}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1a2fe00 } + }, +/* movhh ${Dsp-24-s16}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1a4fe00 } + }, +/* movhh ${Dsp-24-u16},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1a6fe00 } + }, +/* movhh ${Dsp-24-u24},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1a6be00 } + }, +/* movhl $Dst32RnPrefixedQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNPREFIXEDQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1a82e } + }, +/* movhl $Dst32AnPrefixedQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANPREFIXEDQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1a0ae } + }, +/* movhl [$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1a02e } + }, +/* movhl ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1a22e00 } + }, +/* movhl ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1a42e00 } + }, +/* movhl ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1a62e00 } + }, +/* movhl ${Dsp-24-u8}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1a2ae00 } + }, +/* movhl ${Dsp-24-u16}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1a4ae00 } + }, +/* movhl ${Dsp-24-s8}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1a2ee00 } + }, +/* movhl ${Dsp-24-s16}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1a4ee00 } + }, +/* movhl ${Dsp-24-u16},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1a6ee00 } + }, +/* movhl ${Dsp-24-u24},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1a6ae00 } + }, +/* movlh $Dst32RnPrefixedQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNPREFIXEDQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1a81e } + }, +/* movlh $Dst32AnPrefixedQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANPREFIXEDQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1a09e } + }, +/* movlh [$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1a01e } + }, +/* movlh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1a21e00 } + }, +/* movlh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1a41e00 } + }, +/* movlh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1a61e00 } + }, +/* movlh ${Dsp-24-u8}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1a29e00 } + }, +/* movlh ${Dsp-24-u16}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1a49e00 } + }, +/* movlh ${Dsp-24-s8}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1a2de00 } + }, +/* movlh ${Dsp-24-s16}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1a4de00 } + }, +/* movlh ${Dsp-24-u16},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1a6de00 } + }, +/* movlh ${Dsp-24-u24},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1a69e00 } + }, +/* movll $Dst32RnPrefixedQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNPREFIXEDQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1a80e } + }, +/* movll $Dst32AnPrefixedQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANPREFIXEDQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1a08e } + }, +/* movll [$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1a00e } + }, +/* movll ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1a20e00 } + }, +/* movll ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1a40e00 } + }, +/* movll ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1a60e00 } + }, +/* movll ${Dsp-24-u8}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1a28e00 } + }, +/* movll ${Dsp-24-u16}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1a48e00 } + }, +/* movll ${Dsp-24-s8}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1a2ce00 } + }, +/* movll ${Dsp-24-s16}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1a4ce00 } + }, +/* movll ${Dsp-24-u16},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1a6ce00 } + }, +/* movll ${Dsp-24-u24},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', 'r', '0', 'l', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1a68e00 } + }, +/* movhh r0l,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1b83e } + }, +/* movhh r0l,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1b0be } + }, +/* movhh r0l,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1b03e } + }, +/* movhh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1b23e00 } + }, +/* movhh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1b43e00 } + }, +/* movhh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1b63e00 } + }, +/* movhh r0l,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1b2be00 } + }, +/* movhh r0l,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1b4be00 } + }, +/* movhh r0l,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1b2fe00 } + }, +/* movhh r0l,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1b4fe00 } + }, +/* movhh r0l,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1b6fe00 } + }, +/* movhh r0l,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1b6be00 } + }, +/* movhl r0l,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1b82e } + }, +/* movhl r0l,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1b0ae } + }, +/* movhl r0l,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1b02e } + }, +/* movhl r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1b22e00 } + }, +/* movhl r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1b42e00 } + }, +/* movhl r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1b62e00 } + }, +/* movhl r0l,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1b2ae00 } + }, +/* movhl r0l,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1b4ae00 } + }, +/* movhl r0l,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1b2ee00 } + }, +/* movhl r0l,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1b4ee00 } + }, +/* movhl r0l,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1b6ee00 } + }, +/* movhl r0l,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1b6ae00 } + }, +/* movlh r0l,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1b81e } + }, +/* movlh r0l,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1b09e } + }, +/* movlh r0l,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1b01e } + }, +/* movlh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1b21e00 } + }, +/* movlh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1b41e00 } + }, +/* movlh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1b61e00 } + }, +/* movlh r0l,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1b29e00 } + }, +/* movlh r0l,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1b49e00 } + }, +/* movlh r0l,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1b2de00 } + }, +/* movlh r0l,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1b4de00 } + }, +/* movlh r0l,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1b6de00 } + }, +/* movlh r0l,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1b69e00 } + }, +/* movll r0l,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_movhh32_src_r0l_dst32_Rn_direct_Prefixed_QI, { 0x1b80e } + }, +/* movll r0l,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_direct_Prefixed_QI, { 0x1b08e } + }, +/* movll r0l,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_An_indirect_Prefixed_QI, { 0x1b00e } + }, +/* movll r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_An_relative_Prefixed_QI, { 0x1b20e00 } + }, +/* movll r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_An_relative_Prefixed_QI, { 0x1b40e00 } + }, +/* movll r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_An_relative_Prefixed_QI, { 0x1b60e00 } + }, +/* movll r0l,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_SB_relative_Prefixed_QI, { 0x1b28e00 } + }, +/* movll r0l,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_SB_relative_Prefixed_QI, { 0x1b48e00 } + }, +/* movll r0l,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_8_FB_relative_Prefixed_QI, { 0x1b2ce00 } + }, +/* movll r0l,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_FB_relative_Prefixed_QI, { 0x1b4ce00 } + }, +/* movll r0l,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U16), 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_16_absolute_Prefixed_QI, { 0x1b6ce00 } + }, +/* movll r0l,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_24_U24), 0 } }, + & ifmt_movhh32_src_r0l_dst32_24_24_absolute_Prefixed_QI, { 0x1b68e00 } + }, +/* movhh $Dst16RnQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c30 } + }, +/* movhh $Dst16AnQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c34 } + }, +/* movhh [$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c36 } + }, +/* movhh ${Dsp-16-u8}[$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c3800 } + }, +/* movhh ${Dsp-16-u16}[$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c3c0000 } + }, +/* movhh ${Dsp-16-u8}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c3a00 } + }, +/* movhh ${Dsp-16-u16}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c3e0000 } + }, +/* movhh ${Dsp-16-s8}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c3b00 } + }, +/* movhh ${Dsp-16-u16},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c3f0000 } + }, +/* movhl $Dst16RnQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c10 } + }, +/* movhl $Dst16AnQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c14 } + }, +/* movhl [$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c16 } + }, +/* movhl ${Dsp-16-u8}[$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c1800 } + }, +/* movhl ${Dsp-16-u16}[$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c1c0000 } + }, +/* movhl ${Dsp-16-u8}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c1a00 } + }, +/* movhl ${Dsp-16-u16}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c1e0000 } + }, +/* movhl ${Dsp-16-s8}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c1b00 } + }, +/* movhl ${Dsp-16-u16},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c1f0000 } + }, +/* movlh $Dst16RnQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c20 } + }, +/* movlh $Dst16AnQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c24 } + }, +/* movlh [$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c26 } + }, +/* movlh ${Dsp-16-u8}[$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c2800 } + }, +/* movlh ${Dsp-16-u16}[$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c2c0000 } + }, +/* movlh ${Dsp-16-u8}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c2a00 } + }, +/* movlh ${Dsp-16-u16}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c2e0000 } + }, +/* movlh ${Dsp-16-s8}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c2b00 } + }, +/* movlh ${Dsp-16-u16},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c2f0000 } + }, +/* movll $Dst16RnQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c00 } + }, +/* movll $Dst16AnQI,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c04 } + }, +/* movll [$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c06 } + }, +/* movll ${Dsp-16-u8}[$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c0800 } + }, +/* movll ${Dsp-16-u16}[$Dst16An],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c0c0000 } + }, +/* movll ${Dsp-16-u8}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c0a00 } + }, +/* movll ${Dsp-16-u16}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c0e0000 } + }, +/* movll ${Dsp-16-s8}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c0b00 } + }, +/* movll ${Dsp-16-u16},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 'l', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c0f0000 } + }, +/* movhh r0l,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7cb0 } + }, +/* movhh r0l,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7cb4 } + }, +/* movhh r0l,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7cb6 } + }, +/* movhh r0l,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7cb800 } + }, +/* movhh r0l,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7cbc0000 } + }, +/* movhh r0l,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7cba00 } + }, +/* movhh r0l,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7cbe0000 } + }, +/* movhh r0l,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7cbb00 } + }, +/* movhh r0l,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7cbf0000 } + }, +/* movhl r0l,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c90 } + }, +/* movhl r0l,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c94 } + }, +/* movhl r0l,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c96 } + }, +/* movhl r0l,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c9800 } + }, +/* movhl r0l,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c9c0000 } + }, +/* movhl r0l,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c9a00 } + }, +/* movhl r0l,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c9e0000 } + }, +/* movhl r0l,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c9b00 } + }, +/* movhl r0l,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c9f0000 } + }, +/* movlh r0l,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7ca0 } + }, +/* movlh r0l,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7ca4 } + }, +/* movlh r0l,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7ca6 } + }, +/* movlh r0l,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7ca800 } + }, +/* movlh r0l,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7cac0000 } + }, +/* movlh r0l,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7caa00 } + }, +/* movlh r0l,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7cae0000 } + }, +/* movlh r0l,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7cab00 } + }, +/* movlh r0l,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7caf0000 } + }, +/* movll r0l,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16RNQI), 0 } }, + & ifmt_shl16_b_dst_dst16_Rn_direct_QI, { 0x7c80 } + }, +/* movll r0l,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DST16ANQI), 0 } }, + & ifmt_shl16_b_dst_dst16_An_direct_QI, { 0x7c84 } + }, +/* movll r0l,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_An_indirect_QI, { 0x7c86 } + }, +/* movll r0l,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_An_relative_QI, { 0x7c8800 } + }, +/* movll r0l,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_An_relative_QI, { 0x7c8c0000 } + }, +/* movll r0l,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_SB_relative_QI, { 0x7c8a00 } + }, +/* movll r0l,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_SB_relative_QI, { 0x7c8e0000 } + }, +/* movll r0l,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_b_dst_dst16_16_8_FB_relative_QI, { 0x7c8b00 } + }, +/* movll r0l,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_b_dst_dst16_16_16_absolute_QI, { 0x7c8f0000 } + }, +/* mova [$Dst32AnUnprefixed],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI, { 0xd11b } + }, +/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xd31b00 } + }, +/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xd51b0000 } + }, +/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xd71b0000 } + }, +/* mova ${Dsp-16-u8}[sb],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'a', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xd39b00 } + }, +/* mova ${Dsp-16-u16}[sb],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'a', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xd59b0000 } + }, +/* mova ${Dsp-16-s8}[fb],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'a', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xd3db00 } + }, +/* mova ${Dsp-16-s16}[fb],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', 'a', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xd5db0000 } + }, +/* mova ${Dsp-16-u16},a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'a', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xd7db0000 } + }, +/* mova ${Dsp-16-u24},a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), ',', 'a', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xd79b0000 } + }, +/* mova [$Dst32AnUnprefixed],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI, { 0xd11a } + }, +/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xd31a00 } + }, +/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xd51a0000 } + }, +/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', 'a', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xd71a0000 } + }, +/* mova ${Dsp-16-u8}[sb],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'a', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xd39a00 } + }, +/* mova ${Dsp-16-u16}[sb],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'a', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xd59a0000 } + }, +/* mova ${Dsp-16-s8}[fb],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'a', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xd3da00 } + }, +/* mova ${Dsp-16-s16}[fb],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', 'a', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xd5da0000 } + }, +/* mova ${Dsp-16-u16},a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'a', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xd7da0000 } + }, +/* mova ${Dsp-16-u24},a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), ',', 'a', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xd79a0000 } + }, +/* mova [$Dst32AnUnprefixed],r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI, { 0xd119 } + }, +/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xd31900 } + }, +/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xd5190000 } + }, +/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xd7190000 } + }, +/* mova ${Dsp-16-u8}[sb],r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xd39900 } + }, +/* mova ${Dsp-16-u16}[sb],r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xd5990000 } + }, +/* mova ${Dsp-16-s8}[fb],r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xd3d900 } + }, +/* mova ${Dsp-16-s16}[fb],r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xd5d90000 } + }, +/* mova ${Dsp-16-u16},r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xd7d90000 } + }, +/* mova ${Dsp-16-u24},r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xd7990000 } + }, +/* mova [$Dst32AnUnprefixed],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_An_indirect_Unprefixed_Mova_SI, { 0xd118 } + }, +/* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_An_relative_Unprefixed_Mova_SI, { 0xd31800 } + }, +/* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_An_relative_Unprefixed_Mova_SI, { 0xd5180000 } + }, +/* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_24_An_relative_Unprefixed_Mova_SI, { 0xd7180000 } + }, +/* mova ${Dsp-16-u8}[sb],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_SB_relative_Unprefixed_Mova_SI, { 0xd39800 } + }, +/* mova ${Dsp-16-u16}[sb],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_SB_relative_Unprefixed_Mova_SI, { 0xd5980000 } + }, +/* mova ${Dsp-16-s8}[fb],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_8_FB_relative_Unprefixed_Mova_SI, { 0xd3d800 } + }, +/* mova ${Dsp-16-s16}[fb],r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_FB_relative_Unprefixed_Mova_SI, { 0xd5d80000 } + }, +/* mova ${Dsp-16-u16},r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_16_absolute_Unprefixed_Mova_SI, { 0xd7d80000 } + }, +/* mova ${Dsp-16-u24},r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_mova32_src_a1_dst32_16_24_absolute_Unprefixed_Mova_SI, { 0xd7980000 } + }, +/* mova [$Dst16An],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'a', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb56 } + }, +/* mova ${Dsp-16-u8}[$Dst16An],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'a', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb5800 } + }, +/* mova ${Dsp-16-u16}[$Dst16An],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'a', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb5c0000 } + }, +/* mova ${Dsp-16-u8}[sb],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'a', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb5a00 } + }, +/* mova ${Dsp-16-u16}[sb],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'a', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb5e0000 } + }, +/* mova ${Dsp-16-s8}[fb],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'a', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb5b00 } + }, +/* mova ${Dsp-16-u16},a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'a', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb5f0000 } + }, +/* mova [$Dst16An],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'a', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb46 } + }, +/* mova ${Dsp-16-u8}[$Dst16An],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'a', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb4800 } + }, +/* mova ${Dsp-16-u16}[$Dst16An],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'a', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb4c0000 } + }, +/* mova ${Dsp-16-u8}[sb],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'a', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb4a00 } + }, +/* mova ${Dsp-16-u16}[sb],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'a', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb4e0000 } + }, +/* mova ${Dsp-16-s8}[fb],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'a', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb4b00 } + }, +/* mova ${Dsp-16-u16},a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'a', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb4f0000 } + }, +/* mova [$Dst16An],r3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '3', 0 } }, + & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb36 } + }, +/* mova ${Dsp-16-u8}[$Dst16An],r3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '3', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb3800 } + }, +/* mova ${Dsp-16-u16}[$Dst16An],r3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '3', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb3c0000 } + }, +/* mova ${Dsp-16-u8}[sb],r3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '3', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb3a00 } + }, +/* mova ${Dsp-16-u16}[sb],r3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '3', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb3e0000 } + }, +/* mova ${Dsp-16-s8}[fb],r3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '3', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb3b00 } + }, +/* mova ${Dsp-16-u16},r3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '3', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb3f0000 } + }, +/* mova [$Dst16An],r2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '2', 0 } }, + & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb26 } + }, +/* mova ${Dsp-16-u8}[$Dst16An],r2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '2', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb2800 } + }, +/* mova ${Dsp-16-u16}[$Dst16An],r2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '2', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb2c0000 } + }, +/* mova ${Dsp-16-u8}[sb],r2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '2', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb2a00 } + }, +/* mova ${Dsp-16-u16}[sb],r2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '2', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb2e0000 } + }, +/* mova ${Dsp-16-s8}[fb],r2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '2', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb2b00 } + }, +/* mova ${Dsp-16-u16},r2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '2', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb2f0000 } + }, +/* mova [$Dst16An],r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb16 } + }, +/* mova ${Dsp-16-u8}[$Dst16An],r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb1800 } + }, +/* mova ${Dsp-16-u16}[$Dst16An],r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb1c0000 } + }, +/* mova ${Dsp-16-u8}[sb],r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb1a00 } + }, +/* mova ${Dsp-16-u16}[sb],r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb1e0000 } + }, +/* mova ${Dsp-16-s8}[fb],r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb1b00 } + }, +/* mova ${Dsp-16-u16},r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '1', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb1f0000 } + }, +/* mova [$Dst16An],r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', 'r', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_An_indirect_Mova_HI, { 0xeb06 } + }, +/* mova ${Dsp-16-u8}[$Dst16An],r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', 'r', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_An_relative_Mova_HI, { 0xeb0800 } + }, +/* mova ${Dsp-16-u16}[$Dst16An],r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', 'r', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_An_relative_Mova_HI, { 0xeb0c0000 } + }, +/* mova ${Dsp-16-u8}[sb],r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', 'r', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_SB_relative_Mova_HI, { 0xeb0a00 } + }, +/* mova ${Dsp-16-u16}[sb],r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', 'r', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_SB_relative_Mova_HI, { 0xeb0e0000 } + }, +/* mova ${Dsp-16-s8}[fb],r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', 'r', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_8_FB_relative_Mova_HI, { 0xeb0b00 } + }, +/* mova ${Dsp-16-u16},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', 'r', '0', 0 } }, + & ifmt_pusha16_16_Mova_dst16_16_16_absolute_Mova_HI, { 0xeb0f0000 } + }, +/* mov.w ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xa30f0000 } + }, +/* mov.w ${Dsp-16-u8}[sb],${Dsp-24-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa38f0000 } + }, +/* mov.w ${Dsp-16-s8}[fb],${Dsp-24-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3cf0000 } + }, +/* mov.w ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xa50f0000 } + }, +/* mov.w ${Dsp-16-u16}[sb],${Dsp-32-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa58f0000 } + }, +/* mov.w ${Dsp-16-s16}[fb],${Dsp-32-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5cf0000 } + }, +/* mov.w ${Dsp-16-u16},${Dsp-32-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xa7cf0000 } + }, +/* mov.w ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xa70f0000 } + }, +/* mov.w ${Dsp-16-u24},${Dsp-40-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xa78f0000 } + }, +/* mov.w $Dst32RnUnprefixedHI,${Dsp-16-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xa90f00 } + }, +/* mov.w $Dst32AnUnprefixedHI,${Dsp-16-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xa18f00 } + }, +/* mov.w [$Dst32AnUnprefixed],${Dsp-16-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xa10f00 } + }, +/* mov.b ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xa20f0000 } + }, +/* mov.b ${Dsp-16-u8}[sb],${Dsp-24-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa28f0000 } + }, +/* mov.b ${Dsp-16-s8}[fb],${Dsp-24-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2cf0000 } + }, +/* mov.b ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xa40f0000 } + }, +/* mov.b ${Dsp-16-u16}[sb],${Dsp-32-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa48f0000 } + }, +/* mov.b ${Dsp-16-s16}[fb],${Dsp-32-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4cf0000 } + }, +/* mov.b ${Dsp-16-u16},${Dsp-32-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xa6cf0000 } + }, +/* mov.b ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xa60f0000 } + }, +/* mov.b ${Dsp-16-u24},${Dsp-40-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xa68f0000 } + }, +/* mov.b $Dst32RnUnprefixedQI,${Dsp-16-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xa80f00 } + }, +/* mov.b $Dst32AnUnprefixedQI,${Dsp-16-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xa08f00 } + }, +/* mov.b [$Dst32AnUnprefixed],${Dsp-16-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xa00f00 } + }, +/* mov.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI, { 0x75380000 } + }, +/* mov.w ${Dsp-16-u8}[sb],${Dsp-24-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI, { 0x753a0000 } + }, +/* mov.w ${Dsp-16-s8}[fb],${Dsp-24-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI, { 0x753b0000 } + }, +/* mov.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI, { 0x753c0000 } + }, +/* mov.w ${Dsp-16-u16}[sb],${Dsp-32-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI, { 0x753e0000 } + }, +/* mov.w ${Dsp-16-u16},${Dsp-32-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI, { 0x753f0000 } + }, +/* mov.w $Dst16RnHI,${Dsp-16-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_basic_dst16_Rn_direct_HI, { 0x753000 } + }, +/* mov.w $Dst16AnHI,${Dsp-16-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_basic_dst16_An_direct_HI, { 0x753400 } + }, +/* mov.w [$Dst16An],${Dsp-16-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_basic_dst16_An_indirect_HI, { 0x753600 } + }, +/* mov.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI, { 0x74380000 } + }, +/* mov.b ${Dsp-16-u8}[sb],${Dsp-24-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI, { 0x743a0000 } + }, +/* mov.b ${Dsp-16-s8}[fb],${Dsp-24-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI, { 0x743b0000 } + }, +/* mov.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI, { 0x743c0000 } + }, +/* mov.b ${Dsp-16-u16}[sb],${Dsp-32-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI, { 0x743e0000 } + }, +/* mov.b ${Dsp-16-u16},${Dsp-32-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI, { 0x743f0000 } + }, +/* mov.b $Dst16RnQI,${Dsp-16-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_basic_dst16_Rn_direct_QI, { 0x743000 } + }, +/* mov.b $Dst16AnQI,${Dsp-16-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_basic_dst16_An_direct_QI, { 0x743400 } + }, +/* mov.b [$Dst16An],${Dsp-16-u8}[sp] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'p', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_basic_dst16_An_indirect_QI, { 0x743600 } + }, +/* mov.w ${Dsp-24-u8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xb30f0000 } + }, +/* mov.w ${Dsp-24-u8}[sp],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb38f0000 } + }, +/* mov.w ${Dsp-24-u8}[sp],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3cf0000 } + }, +/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xb50f0000 } + }, +/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb58f0000 } + }, +/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5cf0000 } + }, +/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_w_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xb7cf0000 } + }, +/* mov.w ${Dsp-40-u8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_40_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xb70f0000 } + }, +/* mov.w ${Dsp-40-u8}[sp],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_40_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_w_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xb78f0000 } + }, +/* mov.w ${Dsp-16-u8}[sp],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xb90f00 } + }, +/* mov.w ${Dsp-16-u8}[sp],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xb18f00 } + }, +/* mov.w ${Dsp-16-u8}[sp],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xb10f00 } + }, +/* mov.b ${Dsp-24-u8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xb20f0000 } + }, +/* mov.b ${Dsp-24-u8}[sp],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb28f0000 } + }, +/* mov.b ${Dsp-24-u8}[sp],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2cf0000 } + }, +/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xb40f0000 } + }, +/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb48f0000 } + }, +/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4cf0000 } + }, +/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_b_dst_dspsp_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xb6cf0000 } + }, +/* mov.b ${Dsp-40-u8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_40_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xb60f0000 } + }, +/* mov.b ${Dsp-40-u8}[sp],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_40_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_b_dst_dspsp_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xb68f0000 } + }, +/* mov.b ${Dsp-16-u8}[sp],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xb80f00 } + }, +/* mov.b ${Dsp-16-u8}[sp],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xb08f00 } + }, +/* mov.b ${Dsp-16-u8}[sp],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_dst_dspsp_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xb00f00 } + }, +/* mov.w ${Dsp-24-u8}[sp],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI, { 0x75b80000 } + }, +/* mov.w ${Dsp-24-u8}[sp],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI, { 0x75ba0000 } + }, +/* mov.w ${Dsp-24-u8}[sp],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI, { 0x75bb0000 } + }, +/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI, { 0x75bc0000 } + }, +/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI, { 0x75be0000 } + }, +/* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI, { 0x75bf0000 } + }, +/* mov.w ${Dsp-16-u8}[sp],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_mov16_w_dst_dspsp_basic_dst16_Rn_direct_HI, { 0x75b000 } + }, +/* mov.w ${Dsp-16-u8}[sp],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_mov16_w_dst_dspsp_basic_dst16_An_direct_HI, { 0x75b400 } + }, +/* mov.w ${Dsp-16-u8}[sp],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_dst_dspsp_basic_dst16_An_indirect_HI, { 0x75b600 } + }, +/* mov.b ${Dsp-24-u8}[sp],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI, { 0x74b80000 } + }, +/* mov.b ${Dsp-24-u8}[sp],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI, { 0x74ba0000 } + }, +/* mov.b ${Dsp-24-u8}[sp],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'p', ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI, { 0x74bb0000 } + }, +/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI, { 0x74bc0000 } + }, +/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI, { 0x74be0000 } + }, +/* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U8), '[', 's', 'p', ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI, { 0x74bf0000 } + }, +/* mov.b ${Dsp-16-u8}[sp],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_mov16_b_dst_dspsp_basic_dst16_Rn_direct_QI, { 0x74b000 } + }, +/* mov.b ${Dsp-16-u8}[sp],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_mov16_b_dst_dspsp_basic_dst16_An_direct_QI, { 0x74b400 } + }, +/* mov.b ${Dsp-16-u8}[sp],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'p', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_b_dst_dspsp_basic_dst16_An_indirect_QI, { 0x74b600 } + }, +/* mov.l${S} ${Dsp-8-u8}[sb],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'a', '1', 0 } }, + & ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_SB_relative_SI, { 0x6900 } + }, +/* mov.l${S} ${Dsp-8-s8}[fb],a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'a', '1', 0 } }, + & ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_FB_relative_SI, { 0x7900 } + }, +/* mov.l${S} ${Dsp-8-u8}[sb],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'a', '0', 0 } }, + & ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_SB_relative_SI, { 0x6800 } + }, +/* mov.l${S} ${Dsp-8-s8}[fb],a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'a', '0', 0 } }, + & ifmt_mov32_sz_dst32_2_S_8_a1_dst32_2_S_8_FB_relative_SI, { 0x7800 } + }, +/* mov.l${S} ${Dsp-8-u16},a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'a', '1', 0 } }, + & ifmt_mov32_sz_dst32_2_S_16_a1_dst32_2_S_16_absolute_SI, { 0x590000 } + }, +/* mov.l${S} ${Dsp-8-u16},a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'a', '0', 0 } }, + & ifmt_mov32_sz_dst32_2_S_16_a1_dst32_2_S_16_absolute_SI, { 0x580000 } + }, +/* mov.w${S} r0,${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', 'r', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2100 } + }, +/* mov.w${S} r0,${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', 'r', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3100 } + }, +/* mov.b${S} r0l,${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2000 } + }, +/* mov.b${S} r0l,${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3000 } + }, +/* mov.w${S} r0,${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', 'r', '0', ',', OP (DSP_8_U16), 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI, { 0x110000 } + }, +/* mov.b${S} r0l,${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', OP (DSP_8_U16), 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x100000 } + }, +/* mov.w${S} ${Dsp-8-u8}[sb],r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'r', '1', 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x6f00 } + }, +/* mov.w${S} ${Dsp-8-s8}[fb],r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'r', '1', 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x7f00 } + }, +/* mov.b${S} ${Dsp-8-u8}[sb],r1l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'r', '1', 'l', 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x6e00 } + }, +/* mov.b${S} ${Dsp-8-s8}[fb],r1l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'r', '1', 'l', 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x7e00 } + }, +/* mov.w${S} ${Dsp-8-u16},r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '1', 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI, { 0x5f0000 } + }, +/* mov.b${S} ${Dsp-8-u16},r1l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '1', 'l', 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x5e0000 } + }, +/* mov.w${S} r0,r1l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', 'r', '0', ',', 'r', '1', 'l', 0 } }, + & ifmt_mov32_w_dst32_2_S_basic_r1l_dst32_2_S_R0_direct_HI, { 0x4f } + }, +/* mov.b${S} r0l,r1l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', 'r', '1', 'l', 0 } }, + & ifmt_mov32_b_dst32_2_S_basic_r1l_dst32_2_S_R0l_direct_QI, { 0x4e } + }, +/* mov.w${S} ${Dsp-8-u8}[sb],r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'r', '0', 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2900 } + }, +/* mov.w${S} ${Dsp-8-s8}[fb],r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'r', '0', 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3900 } + }, +/* mov.b${S} ${Dsp-8-u8}[sb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2800 } + }, +/* mov.b${S} ${Dsp-8-s8}[fb],r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', 'r', '0', 'l', 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3800 } + }, +/* mov.w${S} ${Dsp-8-u16},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '0', 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI, { 0x190000 } + }, +/* mov.b${S} ${Dsp-8-u16},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', 'r', '0', 'l', 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x180000 } + }, +/* mov.b${S} ${SrcDst16-r0l-r0h-S-normal} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } }, + & ifmt_mov16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x8 } + }, +/* mov.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_mov16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x900 } + }, +/* mov.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_mov16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0xa00 } + }, +/* mov.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } }, + & ifmt_mov16_b_S_src2_src16_2_S_16_absolute_QI, { 0xb0000 } + }, +/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DST16RNQI_S), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x100 } + }, +/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DST16RNQI_S), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x200 } + }, +/* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DST16RNQI_S), ',', OP (DSP_8_U16), 0 } }, + & ifmt_mov16_b_S_src2_src16_2_S_16_absolute_QI, { 0x30000 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x990300 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x992300 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x993300 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x918300 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91a300 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91b300 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x910300 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x912300 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x913300 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93030000 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93230000 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93330000 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95030000 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95230000 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95330000 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97030000 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97230000 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97330000 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93830000 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93a30000 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93b30000 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95830000 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95a30000 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95b30000 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93c30000 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93e30000 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93f30000 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95c30000 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95e30000 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95f30000 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97c30000 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97e30000 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97f30000 } + }, +/* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97830000 } + }, +/* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97a30000 } + }, +/* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97b30000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9030000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9230000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9330000 } + }, +/* mov.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9330000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1830000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1a30000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1b30000 } + }, +/* mov.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1b30000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1030000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1230000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1330000 } + }, +/* mov.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1330000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3030000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3230000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3330000 } + }, +/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb3330000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5030000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5230000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5330000 } + }, +/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb5330000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7030000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7230000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7330000 } + }, +/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb7330000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3830000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3a30000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3b30000 } + }, +/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb3b30000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5830000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5a30000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5b30000 } + }, +/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb5b30000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3c30000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3e30000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3f30000 } + }, +/* mov.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb3f30000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5c30000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5e30000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5f30000 } + }, +/* mov.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb5f30000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7c30000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7e30000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7f30000 } + }, +/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xb7f30000 } + }, +/* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7830000 } + }, +/* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7a30000 } + }, +/* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7b30000 } + }, +/* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xb7b30000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9030000 } + }, +/* mov.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9230000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1830000 } + }, +/* mov.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1a30000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1030000 } + }, +/* mov.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1230000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3030000 } + }, +/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3230000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5030000 } + }, +/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5230000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7030000 } + }, +/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7230000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3830000 } + }, +/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3a30000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5830000 } + }, +/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5a30000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3c30000 } + }, +/* mov.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3e30000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5c30000 } + }, +/* mov.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5e30000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7c30000 } + }, +/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7e30000 } + }, +/* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7830000 } + }, +/* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7a30000 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xc903 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8923 } + }, +/* mov.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8903 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xc183 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x81a3 } + }, +/* mov.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x8183 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xc103 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8123 } + }, +/* mov.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8103 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc30300 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x832300 } + }, +/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x830300 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc5030000 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85230000 } + }, +/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85030000 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc7030000 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87230000 } + }, +/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87030000 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc38300 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x83a300 } + }, +/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x838300 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc5830000 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85a30000 } + }, +/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85830000 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc3c300 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83e300 } + }, +/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83c300 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc5c30000 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85e30000 } + }, +/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85c30000 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0xc7c30000 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87e30000 } + }, +/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87c30000 } + }, +/* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0xc7830000 } + }, +/* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87a30000 } + }, +/* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87830000 } + }, +/* mov.b${S} ${Dsp-8-u8}[sb],${Dst16AnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI_S), 0 } }, + & ifmt_mov16_b_S_An_src16_2_S_8_SB_relative_QI, { 0x3100 } + }, +/* mov.b${S} ${Dsp-8-s8}[fb],${Dst16AnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI_S), 0 } }, + & ifmt_mov16_b_S_An_src16_2_S_8_FB_relative_QI, { 0x3200 } + }, +/* mov.b${S} ${Dsp-8-u16},${Dst16AnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16ANQI_S), 0 } }, + & ifmt_mov16_b_S_An_src16_2_S_16_absolute_QI, { 0x330000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990b00 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992b00 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993b00 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918b00 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91ab00 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91bb00 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910b00 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912b00 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913b00 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x930b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x932b0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x933b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x950b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x952b0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x953b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x970b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x972b0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x973b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x938b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93ab0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93bb0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x958b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95ab0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95bb0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93cb0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93eb0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93fb0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95cb0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95eb0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95fb0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97cb0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97eb0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97fb0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x978b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97ab0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97bb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa90b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa92b0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa93b0000 } + }, +/* mov.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb93b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa18b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1ab0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1bb0000 } + }, +/* mov.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1bb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa10b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa12b0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa13b0000 } + }, +/* mov.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb13b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa30b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa32b0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa33b0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb33b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa50b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa52b0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa53b0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb53b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa70b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa72b0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa73b0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb73b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa38b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3ab0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3bb0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3bb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa58b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5ab0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5bb0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5bb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3cb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3eb0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3fb0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3fb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5cb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5eb0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5fb0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5fb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7cb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7eb0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7fb0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7fb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa78b0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7ab0000 } + }, +/* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7bb0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7bb0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb90b0000 } + }, +/* mov.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb92b0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb18b0000 } + }, +/* mov.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1ab0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb10b0000 } + }, +/* mov.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb12b0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb30b0000 } + }, +/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb32b0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb50b0000 } + }, +/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb52b0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb70b0000 } + }, +/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb72b0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb38b0000 } + }, +/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3ab0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb58b0000 } + }, +/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5ab0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3cb0000 } + }, +/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3eb0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5cb0000 } + }, +/* mov.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5eb0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7cb0000 } + }, +/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7eb0000 } + }, +/* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb78b0000 } + }, +/* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7ab0000 } + }, +/* mov.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc90b } + }, +/* mov.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x892b } + }, +/* mov.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x890b } + }, +/* mov.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc18b } + }, +/* mov.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81ab } + }, +/* mov.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x818b } + }, +/* mov.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc10b } + }, +/* mov.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x812b } + }, +/* mov.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x810b } + }, +/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30b00 } + }, +/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832b00 } + }, +/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830b00 } + }, +/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50b0000 } + }, +/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x852b0000 } + }, +/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x850b0000 } + }, +/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70b0000 } + }, +/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x872b0000 } + }, +/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x870b0000 } + }, +/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38b00 } + }, +/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83ab00 } + }, +/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838b00 } + }, +/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58b0000 } + }, +/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85ab0000 } + }, +/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858b0000 } + }, +/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3cb00 } + }, +/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83eb00 } + }, +/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83cb00 } + }, +/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5cb0000 } + }, +/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85eb0000 } + }, +/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85cb0000 } + }, +/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7cb0000 } + }, +/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87eb0000 } + }, +/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87cb0000 } + }, +/* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc78b0000 } + }, +/* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87ab0000 } + }, +/* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x878b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980b00 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982b00 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983b00 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908b00 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90ab00 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90bb00 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900b00 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902b00 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903b00 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x920b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x922b0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x923b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x940b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x942b0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x943b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x960b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x962b0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x963b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x928b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92ab0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92bb0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x948b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94ab0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94bb0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92cb0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92eb0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92fb0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94cb0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94eb0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94fb0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96cb0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96eb0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96fb0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x968b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96ab0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96bb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa80b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa82b0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa83b0000 } + }, +/* mov.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb83b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa08b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0ab0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0bb0000 } + }, +/* mov.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0bb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa00b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa02b0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa03b0000 } + }, +/* mov.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb03b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa20b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa22b0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa23b0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb23b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa40b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa42b0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa43b0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb43b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa60b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa62b0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa63b0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb63b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa28b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2ab0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2bb0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2bb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa48b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4ab0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4bb0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4bb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2cb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2eb0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2fb0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2fb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4cb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4eb0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4fb0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4fb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6cb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6eb0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6fb0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6fb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa68b0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6ab0000 } + }, +/* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6bb0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6bb0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb80b0000 } + }, +/* mov.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb82b0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb08b0000 } + }, +/* mov.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0ab0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb00b0000 } + }, +/* mov.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb02b0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb20b0000 } + }, +/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb22b0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb40b0000 } + }, +/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb42b0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb60b0000 } + }, +/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb62b0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb28b0000 } + }, +/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2ab0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb48b0000 } + }, +/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4ab0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2cb0000 } + }, +/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2eb0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4cb0000 } + }, +/* mov.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4eb0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6cb0000 } + }, +/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6eb0000 } + }, +/* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb68b0000 } + }, +/* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6ab0000 } + }, +/* mov.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc80b } + }, +/* mov.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x882b } + }, +/* mov.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x880b } + }, +/* mov.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc08b } + }, +/* mov.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80ab } + }, +/* mov.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x808b } + }, +/* mov.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc00b } + }, +/* mov.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x802b } + }, +/* mov.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x800b } + }, +/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20b00 } + }, +/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822b00 } + }, +/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820b00 } + }, +/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40b0000 } + }, +/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x842b0000 } + }, +/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x840b0000 } + }, +/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60b0000 } + }, +/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x862b0000 } + }, +/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x860b0000 } + }, +/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28b00 } + }, +/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82ab00 } + }, +/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828b00 } + }, +/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48b0000 } + }, +/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84ab0000 } + }, +/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848b0000 } + }, +/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2cb00 } + }, +/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82eb00 } + }, +/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82cb00 } + }, +/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4cb0000 } + }, +/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84eb0000 } + }, +/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84cb0000 } + }, +/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6cb0000 } + }, +/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86eb0000 } + }, +/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86cb0000 } + }, +/* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc68b0000 } + }, +/* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86ab0000 } + }, +/* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x868b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x738000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x73a000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x73b000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x738400 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x73a400 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x73b400 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x738600 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x73a600 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x73b600 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x73880000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x73a80000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x73b80000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x738c0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x73ac0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x73bc0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x738a0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x73aa0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x73ba0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x738e0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x73ae0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x73be0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x738b0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x73ab0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x73bb0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x738f0000 } + }, +/* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x73af0000 } + }, +/* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x73bf0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x73c00000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x73e00000 } + }, +/* mov.w${G} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x73f00000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x73c40000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x73e40000 } + }, +/* mov.w${G} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x73f40000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x73c60000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x73e60000 } + }, +/* mov.w${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x73f60000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x73c80000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x73e80000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x73f80000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x73cc0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x73ec0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x73fc0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x73ca0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x73ea0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x73fa0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x73ce0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x73ee0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x73fe0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x73cb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x73eb0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x73fb0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x73cf0000 } + }, +/* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x73ef0000 } + }, +/* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x73ff0000 } + }, +/* mov.w${G} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x7300 } + }, +/* mov.w${G} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x7340 } + }, +/* mov.w${G} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x7360 } + }, +/* mov.w${G} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x7304 } + }, +/* mov.w${G} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x7344 } + }, +/* mov.w${G} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x7364 } + }, +/* mov.w${G} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x7306 } + }, +/* mov.w${G} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x7346 } + }, +/* mov.w${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x7366 } + }, +/* mov.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x730800 } + }, +/* mov.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x734800 } + }, +/* mov.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x736800 } + }, +/* mov.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x730c0000 } + }, +/* mov.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x734c0000 } + }, +/* mov.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x736c0000 } + }, +/* mov.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x730a00 } + }, +/* mov.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x734a00 } + }, +/* mov.w${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x736a00 } + }, +/* mov.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x730e0000 } + }, +/* mov.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x734e0000 } + }, +/* mov.w${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x736e0000 } + }, +/* mov.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x730b00 } + }, +/* mov.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x734b00 } + }, +/* mov.w${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x736b00 } + }, +/* mov.w${G} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x730f0000 } + }, +/* mov.w${G} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x734f0000 } + }, +/* mov.w${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x736f0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x728000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x72a000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x72b000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x728400 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x72a400 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x72b400 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x728600 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x72a600 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x72b600 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x72880000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x72a80000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x72b80000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x728c0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x72ac0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x72bc0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x728a0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x72aa0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x72ba0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x728e0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x72ae0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x72be0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x728b0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x72ab0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x72bb0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x728f0000 } + }, +/* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x72af0000 } + }, +/* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x72bf0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x72c00000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x72e00000 } + }, +/* mov.b${G} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x72f00000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x72c40000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x72e40000 } + }, +/* mov.b${G} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x72f40000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x72c60000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x72e60000 } + }, +/* mov.b${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x72f60000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x72c80000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x72e80000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x72f80000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x72cc0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x72ec0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x72fc0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x72ca0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x72ea0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x72fa0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x72ce0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x72ee0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x72fe0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x72cb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x72eb0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x72fb0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x72cf0000 } + }, +/* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x72ef0000 } + }, +/* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x72ff0000 } + }, +/* mov.b${G} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x7200 } + }, +/* mov.b${G} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x7240 } + }, +/* mov.b${G} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x7260 } + }, +/* mov.b${G} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x7204 } + }, +/* mov.b${G} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x7244 } + }, +/* mov.b${G} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x7264 } + }, +/* mov.b${G} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x7206 } + }, +/* mov.b${G} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x7246 } + }, +/* mov.b${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x7266 } + }, +/* mov.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x720800 } + }, +/* mov.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x724800 } + }, +/* mov.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x726800 } + }, +/* mov.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x720c0000 } + }, +/* mov.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x724c0000 } + }, +/* mov.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x726c0000 } + }, +/* mov.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x720a00 } + }, +/* mov.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x724a00 } + }, +/* mov.b${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x726a00 } + }, +/* mov.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x720e0000 } + }, +/* mov.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x724e0000 } + }, +/* mov.b${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x726e0000 } + }, +/* mov.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x720b00 } + }, +/* mov.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x724b00 } + }, +/* mov.b${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x726b00 } + }, +/* mov.b${G} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x720f0000 } + }, +/* mov.b${G} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x724f0000 } + }, +/* mov.b${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x726f0000 } + }, +/* mov.w${Z} #0,${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2300 } + }, +/* mov.w${Z} #0,${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3300 } + }, +/* mov.w${Z} #0,${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U16), 0 } }, + & ifmt_mov32_w_r0_dst32_2_S_16_dst32_2_S_16_absolute_HI, { 0x130000 } + }, +/* mov.w${Z} #0,r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 0 } }, + & ifmt_mov32_w_dst32_2_S_basic_r1l_dst32_2_S_R0_direct_HI, { 0x3 } + }, +/* mov.b${Z} #0,${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2200 } + }, +/* mov.b${Z} #0,${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3200 } + }, +/* mov.b${Z} #0,${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U16), 0 } }, + & ifmt_mov32_b_r0l_dst32_2_S_16_dst32_2_S_16_absolute_QI, { 0x120000 } + }, +/* mov.b${Z} #0,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 'l', 0 } }, + & ifmt_mov32_b_dst32_2_S_basic_r1l_dst32_2_S_R0l_direct_QI, { 0x2 } + }, +/* mov.b${Z} #0,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 'l', 0 } }, + & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xb4 } + }, +/* mov.b${Z} #0,r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', 'r', '0', 'h', 0 } }, + & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xb3 } + }, +/* mov.b${Z} #0,${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_SB_relative_QI, { 0xb500 } + }, +/* mov.b${Z} #0,${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_FB_relative_QI, { 0xb600 } + }, +/* mov.b${Z} #0,${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U16), 0 } }, + & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_16_absolute_QI, { 0xb70000 } + }, +/* mov.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf920 } + }, +/* mov.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf1a0 } + }, +/* mov.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf120 } + }, +/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf32000 } + }, +/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5200000 } + }, +/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7200000 } + }, +/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf3a000 } + }, +/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5a00000 } + }, +/* mov.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3e000 } + }, +/* mov.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5e00000 } + }, +/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7e00000 } + }, +/* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7a00000 } + }, +/* mov.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf820 } + }, +/* mov.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf0a0 } + }, +/* mov.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf020 } + }, +/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf22000 } + }, +/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4200000 } + }, +/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6200000 } + }, +/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf2a000 } + }, +/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4a00000 } + }, +/* mov.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2e000 } + }, +/* mov.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4e00000 } + }, +/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6e00000 } + }, +/* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6a00000 } + }, +/* mov.w${Q} #${Imm-8-s4},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_QI, { 0xd900 } + }, +/* mov.w${Q} #${Imm-8-s4},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_An_direct_QI, { 0xd904 } + }, +/* mov.w${Q} #${Imm-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_QI, { 0xd906 } + }, +/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xd90800 } + }, +/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xd90c0000 } + }, +/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xd90a00 } + }, +/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xd90e0000 } + }, +/* mov.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xd90b00 } + }, +/* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_QI, { 0xd90f0000 } + }, +/* mov.b${Q} #${Imm-8-s4},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_QI, { 0xd800 } + }, +/* mov.b${Q} #${Imm-8-s4},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_An_direct_QI, { 0xd804 } + }, +/* mov.b${Q} #${Imm-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_QI, { 0xd806 } + }, +/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xd80800 } + }, +/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xd80c0000 } + }, +/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xd80a00 } + }, +/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xd80e0000 } + }, +/* mov.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xd80b00 } + }, +/* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_QI, { 0xd80f0000 } + }, +/* mov.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xc400 } + }, +/* mov.b${S} #${Imm-8-QI},r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xc300 } + }, +/* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xc50000 } + }, +/* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xc60000 } + }, +/* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xc7000000 } + }, +/* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x25000000 } + }, +/* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x35000000 } + }, +/* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x15000000 } + }, +/* mov.w${S} #${Imm-8-HI},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } }, + & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x50000 } + }, +/* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x240000 } + }, +/* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x340000 } + }, +/* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x14000000 } + }, +/* mov.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x400 } + }, +/* mov.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xb8310000 } + }, +/* mov.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xb0b10000 } + }, +/* mov.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xb0310000 } + }, +/* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xb2310000 } + }, +/* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xb2b10000 } + }, +/* mov.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xb2f10000 } + }, +/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xb4310000 } + }, +/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xb4b10000 } + }, +/* mov.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xb4f10000 } + }, +/* mov.l${G} #${Imm-32-SI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xb6f10000 } + }, +/* mov.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xb6310000 } + }, +/* mov.l${G} #${Imm-40-SI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xb6b10000 } + }, +/* mov.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x992f0000 } + }, +/* mov.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91af0000 } + }, +/* mov.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x912f0000 } + }, +/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x932f0000 } + }, +/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93af0000 } + }, +/* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93ef0000 } + }, +/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x952f0000 } + }, +/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95af0000 } + }, +/* mov.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95ef0000 } + }, +/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97ef0000 } + }, +/* mov.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x972f0000 } + }, +/* mov.w${G} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97af0000 } + }, +/* mov.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x982f00 } + }, +/* mov.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90af00 } + }, +/* mov.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x902f00 } + }, +/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x922f0000 } + }, +/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92af0000 } + }, +/* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92ef0000 } + }, +/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x942f0000 } + }, +/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94af0000 } + }, +/* mov.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94ef0000 } + }, +/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96ef0000 } + }, +/* mov.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x962f0000 } + }, +/* mov.b${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96af0000 } + }, +/* mov.w${G} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x75c00000 } + }, +/* mov.w${G} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x75c40000 } + }, +/* mov.w${G} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x75c60000 } + }, +/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x75c80000 } + }, +/* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x75ca0000 } + }, +/* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x75cb0000 } + }, +/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x75cc0000 } + }, +/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x75ce0000 } + }, +/* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x75cf0000 } + }, +/* mov.b${G} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x74c000 } + }, +/* mov.b${G} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x74c400 } + }, +/* mov.b${G} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x74c600 } + }, +/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x74c80000 } + }, +/* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x74ca0000 } + }, +/* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x74cb0000 } + }, +/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x74cc0000 } + }, +/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x74ce0000 } + }, +/* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x74cf0000 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990c00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992c00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993c00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918c00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191ac00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191bc00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910c00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912c00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913c00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930c00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932c00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933c00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950c00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952c00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953c00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970c00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972c00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973c00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938c00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193ac00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193bc00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958c00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195ac00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195bc00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193cc00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193ec00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193fc00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195cc00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195ec00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195fc00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197cc00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197ec00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197fc00 } + }, +/* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978c00 } + }, +/* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197ac00 } + }, +/* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197bc00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90c00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92c00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93c00 } + }, +/* min.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93c00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18c00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1ac00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1bc00 } + }, +/* min.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1bc00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10c00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12c00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13c00 } + }, +/* min.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13c00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30c00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32c00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33c00 } + }, +/* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33c00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50c00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52c00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53c00 } + }, +/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53c00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70c00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72c00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73c00 } + }, +/* min.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73c00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38c00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3ac00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3bc00 } + }, +/* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3bc00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58c00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5ac00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5bc00 } + }, +/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5bc00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3cc00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3ec00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3fc00 } + }, +/* min.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3fc00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5cc00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5ec00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5fc00 } + }, +/* min.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5fc00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7cc00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7ec00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7fc00 } + }, +/* min.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7fc00 } + }, +/* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78c00 } + }, +/* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7ac00 } + }, +/* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7bc00 } + }, +/* min.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7bc00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90c00 } + }, +/* min.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92c00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18c00 } + }, +/* min.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1ac00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10c00 } + }, +/* min.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12c00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30c00 } + }, +/* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32c00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50c00 } + }, +/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52c00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70c00 } + }, +/* min.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72c00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38c00 } + }, +/* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3ac00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58c00 } + }, +/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5ac00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3cc00 } + }, +/* min.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3ec00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5cc00 } + }, +/* min.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5ec00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7cc00 } + }, +/* min.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7ec00 } + }, +/* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78c00 } + }, +/* min.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7ac00 } + }, +/* min.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c90c } + }, +/* min.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1892c } + }, +/* min.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1890c } + }, +/* min.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c18c } + }, +/* min.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181ac } + }, +/* min.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1818c } + }, +/* min.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c10c } + }, +/* min.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1812c } + }, +/* min.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1810c } + }, +/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30c00 } + }, +/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832c00 } + }, +/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830c00 } + }, +/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50c00 } + }, +/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852c00 } + }, +/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850c00 } + }, +/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70c00 } + }, +/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872c00 } + }, +/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870c00 } + }, +/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38c00 } + }, +/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183ac00 } + }, +/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838c00 } + }, +/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58c00 } + }, +/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185ac00 } + }, +/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858c00 } + }, +/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3cc00 } + }, +/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ec00 } + }, +/* min.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183cc00 } + }, +/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5cc00 } + }, +/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ec00 } + }, +/* min.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185cc00 } + }, +/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7cc00 } + }, +/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187ec00 } + }, +/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187cc00 } + }, +/* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78c00 } + }, +/* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187ac00 } + }, +/* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878c00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980c00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982c00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983c00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908c00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190ac00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190bc00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900c00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902c00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903c00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920c00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922c00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923c00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940c00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942c00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943c00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960c00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962c00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963c00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928c00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192ac00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192bc00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948c00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194ac00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194bc00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192cc00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192ec00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192fc00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194cc00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194ec00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194fc00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196cc00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196ec00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196fc00 } + }, +/* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968c00 } + }, +/* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196ac00 } + }, +/* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196bc00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80c00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82c00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83c00 } + }, +/* min.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83c00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08c00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0ac00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0bc00 } + }, +/* min.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0bc00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00c00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02c00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03c00 } + }, +/* min.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03c00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20c00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22c00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23c00 } + }, +/* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23c00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40c00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42c00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43c00 } + }, +/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43c00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60c00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62c00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63c00 } + }, +/* min.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63c00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28c00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2ac00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2bc00 } + }, +/* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2bc00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48c00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4ac00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4bc00 } + }, +/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4bc00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2cc00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2ec00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2fc00 } + }, +/* min.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2fc00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4cc00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4ec00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4fc00 } + }, +/* min.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4fc00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6cc00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6ec00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6fc00 } + }, +/* min.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6fc00 } + }, +/* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68c00 } + }, +/* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6ac00 } + }, +/* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6bc00 } + }, +/* min.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6bc00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80c00 } + }, +/* min.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82c00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08c00 } + }, +/* min.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0ac00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00c00 } + }, +/* min.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02c00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20c00 } + }, +/* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22c00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40c00 } + }, +/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42c00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60c00 } + }, +/* min.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62c00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28c00 } + }, +/* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2ac00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48c00 } + }, +/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4ac00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2cc00 } + }, +/* min.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2ec00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4cc00 } + }, +/* min.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4ec00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6cc00 } + }, +/* min.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6ec00 } + }, +/* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68c00 } + }, +/* min.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6ac00 } + }, +/* min.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c80c } + }, +/* min.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1882c } + }, +/* min.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1880c } + }, +/* min.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c08c } + }, +/* min.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180ac } + }, +/* min.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1808c } + }, +/* min.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c00c } + }, +/* min.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1802c } + }, +/* min.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1800c } + }, +/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20c00 } + }, +/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822c00 } + }, +/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820c00 } + }, +/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40c00 } + }, +/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842c00 } + }, +/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840c00 } + }, +/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60c00 } + }, +/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862c00 } + }, +/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860c00 } + }, +/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28c00 } + }, +/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182ac00 } + }, +/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828c00 } + }, +/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48c00 } + }, +/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184ac00 } + }, +/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848c00 } + }, +/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2cc00 } + }, +/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ec00 } + }, +/* min.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182cc00 } + }, +/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4cc00 } + }, +/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ec00 } + }, +/* min.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184cc00 } + }, +/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6cc00 } + }, +/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186ec00 } + }, +/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186cc00 } + }, +/* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68c00 } + }, +/* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186ac00 } + }, +/* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868c00 } + }, +/* min.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1892f00 } + }, +/* min.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x181af00 } + }, +/* min.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1812f00 } + }, +/* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1832f00 } + }, +/* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x183af00 } + }, +/* min.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ef00 } + }, +/* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1852f00 } + }, +/* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x185af00 } + }, +/* min.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ef00 } + }, +/* min.w${X} #${Imm-40-HI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187ef00 } + }, +/* min.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1872f00 } + }, +/* min.w${X} #${Imm-48-HI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x187af00 } + }, +/* min.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1882f00 } + }, +/* min.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x180af00 } + }, +/* min.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1802f00 } + }, +/* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1822f00 } + }, +/* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x182af00 } + }, +/* min.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ef00 } + }, +/* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1842f00 } + }, +/* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x184af00 } + }, +/* min.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ef00 } + }, +/* min.b${X} #${Imm-40-QI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186ef00 } + }, +/* min.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1862f00 } + }, +/* min.b${X} #${Imm-48-QI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186af00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990d00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992d00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993d00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918d00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191ad00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191bd00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910d00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912d00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913d00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930d00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932d00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933d00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950d00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952d00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953d00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970d00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972d00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973d00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938d00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193ad00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193bd00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958d00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195ad00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195bd00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193cd00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193ed00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193fd00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195cd00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195ed00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195fd00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197cd00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197ed00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197fd00 } + }, +/* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978d00 } + }, +/* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197ad00 } + }, +/* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197bd00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90d00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92d00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93d00 } + }, +/* max.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93d00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18d00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1ad00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1bd00 } + }, +/* max.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1bd00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10d00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12d00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13d00 } + }, +/* max.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13d00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30d00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32d00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33d00 } + }, +/* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33d00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50d00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52d00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53d00 } + }, +/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53d00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70d00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72d00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73d00 } + }, +/* max.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73d00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38d00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3ad00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3bd00 } + }, +/* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3bd00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58d00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5ad00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5bd00 } + }, +/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5bd00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3cd00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3ed00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3fd00 } + }, +/* max.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3fd00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5cd00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5ed00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5fd00 } + }, +/* max.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5fd00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7cd00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7ed00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7fd00 } + }, +/* max.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7fd00 } + }, +/* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78d00 } + }, +/* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7ad00 } + }, +/* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7bd00 } + }, +/* max.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7bd00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90d00 } + }, +/* max.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92d00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18d00 } + }, +/* max.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1ad00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10d00 } + }, +/* max.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12d00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30d00 } + }, +/* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32d00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50d00 } + }, +/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52d00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70d00 } + }, +/* max.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72d00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38d00 } + }, +/* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3ad00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58d00 } + }, +/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5ad00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3cd00 } + }, +/* max.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3ed00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5cd00 } + }, +/* max.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5ed00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7cd00 } + }, +/* max.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7ed00 } + }, +/* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78d00 } + }, +/* max.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7ad00 } + }, +/* max.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c90d } + }, +/* max.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1892d } + }, +/* max.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1890d } + }, +/* max.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c18d } + }, +/* max.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181ad } + }, +/* max.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1818d } + }, +/* max.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c10d } + }, +/* max.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1812d } + }, +/* max.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1810d } + }, +/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30d00 } + }, +/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832d00 } + }, +/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830d00 } + }, +/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50d00 } + }, +/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852d00 } + }, +/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850d00 } + }, +/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70d00 } + }, +/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872d00 } + }, +/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870d00 } + }, +/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38d00 } + }, +/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183ad00 } + }, +/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838d00 } + }, +/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58d00 } + }, +/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185ad00 } + }, +/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858d00 } + }, +/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3cd00 } + }, +/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ed00 } + }, +/* max.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183cd00 } + }, +/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5cd00 } + }, +/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ed00 } + }, +/* max.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185cd00 } + }, +/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7cd00 } + }, +/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187ed00 } + }, +/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187cd00 } + }, +/* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78d00 } + }, +/* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187ad00 } + }, +/* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878d00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980d00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982d00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983d00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908d00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190ad00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190bd00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900d00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902d00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903d00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920d00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922d00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923d00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940d00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942d00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943d00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960d00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962d00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963d00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928d00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192ad00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192bd00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948d00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194ad00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194bd00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192cd00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192ed00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192fd00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194cd00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194ed00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194fd00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196cd00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196ed00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196fd00 } + }, +/* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968d00 } + }, +/* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196ad00 } + }, +/* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196bd00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80d00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82d00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83d00 } + }, +/* max.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83d00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08d00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0ad00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0bd00 } + }, +/* max.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0bd00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00d00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02d00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03d00 } + }, +/* max.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03d00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20d00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22d00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23d00 } + }, +/* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23d00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40d00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42d00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43d00 } + }, +/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43d00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60d00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62d00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63d00 } + }, +/* max.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63d00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28d00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2ad00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2bd00 } + }, +/* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2bd00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48d00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4ad00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4bd00 } + }, +/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4bd00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2cd00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2ed00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2fd00 } + }, +/* max.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2fd00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4cd00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4ed00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4fd00 } + }, +/* max.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4fd00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6cd00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6ed00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6fd00 } + }, +/* max.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6fd00 } + }, +/* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68d00 } + }, +/* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6ad00 } + }, +/* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6bd00 } + }, +/* max.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6bd00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80d00 } + }, +/* max.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82d00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08d00 } + }, +/* max.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0ad00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00d00 } + }, +/* max.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02d00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20d00 } + }, +/* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22d00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40d00 } + }, +/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42d00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60d00 } + }, +/* max.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62d00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28d00 } + }, +/* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2ad00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48d00 } + }, +/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4ad00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2cd00 } + }, +/* max.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2ed00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4cd00 } + }, +/* max.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4ed00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6cd00 } + }, +/* max.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6ed00 } + }, +/* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68d00 } + }, +/* max.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6ad00 } + }, +/* max.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c80d } + }, +/* max.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1882d } + }, +/* max.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1880d } + }, +/* max.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c08d } + }, +/* max.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180ad } + }, +/* max.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1808d } + }, +/* max.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c00d } + }, +/* max.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1802d } + }, +/* max.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1800d } + }, +/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20d00 } + }, +/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822d00 } + }, +/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820d00 } + }, +/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40d00 } + }, +/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842d00 } + }, +/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840d00 } + }, +/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60d00 } + }, +/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862d00 } + }, +/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860d00 } + }, +/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28d00 } + }, +/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182ad00 } + }, +/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828d00 } + }, +/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48d00 } + }, +/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184ad00 } + }, +/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848d00 } + }, +/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2cd00 } + }, +/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ed00 } + }, +/* max.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182cd00 } + }, +/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4cd00 } + }, +/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ed00 } + }, +/* max.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184cd00 } + }, +/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6cd00 } + }, +/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186ed00 } + }, +/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186cd00 } + }, +/* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68d00 } + }, +/* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186ad00 } + }, +/* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868d00 } + }, +/* max.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1893f00 } + }, +/* max.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x181bf00 } + }, +/* max.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1813f00 } + }, +/* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1833f00 } + }, +/* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x183bf00 } + }, +/* max.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ff00 } + }, +/* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1853f00 } + }, +/* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x185bf00 } + }, +/* max.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ff00 } + }, +/* max.w${X} #${Imm-40-HI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187ff00 } + }, +/* max.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1873f00 } + }, +/* max.w${X} #${Imm-48-HI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x187bf00 } + }, +/* max.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1883f00 } + }, +/* max.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x180bf00 } + }, +/* max.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1803f00 } + }, +/* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1823f00 } + }, +/* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x182bf00 } + }, +/* max.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ff00 } + }, +/* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1843f00 } + }, +/* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x184bf00 } + }, +/* max.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ff00 } + }, +/* max.b${X} #${Imm-40-QI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186ff00 } + }, +/* max.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1863f00 } + }, +/* max.b${X} #${Imm-48-QI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186bf00 } + }, +/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), 0 } }, + & ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI, { 0x75080000 } + }, +/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), 0 } }, + & ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI, { 0x750a0000 } + }, +/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), 0 } }, + & ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI, { 0x750b0000 } + }, +/* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), 0 } }, + & ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI, { 0x750c0000 } + }, +/* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), 0 } }, + & ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI, { 0x750e0000 } + }, +/* ste.w ${Dsp-16-u16},${Dsp-32-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), 0 } }, + & ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI, { 0x750f0000 } + }, +/* ste.w $Dst16RnHI,${Dsp-16-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), ',', OP (DSP_16_U20), 0 } }, + & ifmt_ste16_w_dst_dspsp_basic_dst16_Rn_direct_HI, { 0x75000000 } + }, +/* ste.w $Dst16AnHI,${Dsp-16-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), ',', OP (DSP_16_U20), 0 } }, + & ifmt_ste16_w_dst_dspsp_basic_dst16_An_direct_HI, { 0x75040000 } + }, +/* ste.w [$Dst16An],${Dsp-16-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), 0 } }, + & ifmt_ste16_w_dst_dspsp_basic_dst16_An_indirect_HI, { 0x75060000 } + }, +/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (DSP_24_U20), 0 } }, + & ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI, { 0x74080000 } + }, +/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U20), 0 } }, + & ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI, { 0x740a0000 } + }, +/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U20), 0 } }, + & ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI, { 0x740b0000 } + }, +/* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (DSP_32_U20), 0 } }, + & ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI, { 0x740c0000 } + }, +/* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U20), 0 } }, + & ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI, { 0x740e0000 } + }, +/* ste.b ${Dsp-16-u16},${Dsp-32-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U20), 0 } }, + & ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI, { 0x740f0000 } + }, +/* ste.b $Dst16RnQI,${Dsp-16-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), ',', OP (DSP_16_U20), 0 } }, + & ifmt_ste16_b_dst_dspsp_basic_dst16_Rn_direct_QI, { 0x74000000 } + }, +/* ste.b $Dst16AnQI,${Dsp-16-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), ',', OP (DSP_16_U20), 0 } }, + & ifmt_ste16_b_dst_dspsp_basic_dst16_An_direct_QI, { 0x74040000 } + }, +/* ste.b [$Dst16An],${Dsp-16-u20} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (DSP_16_U20), 0 } }, + & ifmt_ste16_b_dst_dspsp_basic_dst16_An_indirect_QI, { 0x74060000 } + }, +/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_An_relative_HI, { 0x75880000 } + }, +/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_SB_relative_HI, { 0x758a0000 } + }, +/* lde.w ${Dsp-24-u20},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_ste16_w_dst_dspsp_16_8_dst16_16_8_FB_relative_HI, { 0x758b0000 } + }, +/* lde.w ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_An_relative_HI, { 0x758c0000 } + }, +/* lde.w ${Dsp-32-u20},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_SB_relative_HI, { 0x758e0000 } + }, +/* lde.w ${Dsp-32-u20},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), 0 } }, + & ifmt_ste16_w_dst_dspsp_16_16_dst16_16_16_absolute_HI, { 0x758f0000 } + }, +/* lde.w ${Dsp-16-u20},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16RNHI), 0 } }, + & ifmt_ste16_w_dst_dspsp_basic_dst16_Rn_direct_HI, { 0x75800000 } + }, +/* lde.w ${Dsp-16-u20},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16ANHI), 0 } }, + & ifmt_ste16_w_dst_dspsp_basic_dst16_An_direct_HI, { 0x75840000 } + }, +/* lde.w ${Dsp-16-u20},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste16_w_dst_dspsp_basic_dst16_An_indirect_HI, { 0x75860000 } + }, +/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_An_relative_QI, { 0x74880000 } + }, +/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_SB_relative_QI, { 0x748a0000 } + }, +/* lde.b ${Dsp-24-u20},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U20), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_ste16_b_dst_dspsp_16_8_dst16_16_8_FB_relative_QI, { 0x748b0000 } + }, +/* lde.b ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_An_relative_QI, { 0x748c0000 } + }, +/* lde.b ${Dsp-32-u20},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_SB_relative_QI, { 0x748e0000 } + }, +/* lde.b ${Dsp-32-u20},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_32_U20), ',', OP (DSP_16_U16), 0 } }, + & ifmt_ste16_b_dst_dspsp_16_16_dst16_16_16_absolute_QI, { 0x748f0000 } + }, +/* lde.b ${Dsp-16-u20},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16RNQI), 0 } }, + & ifmt_ste16_b_dst_dspsp_basic_dst16_Rn_direct_QI, { 0x74800000 } + }, +/* lde.b ${Dsp-16-u20},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), ',', OP (DST16ANQI), 0 } }, + & ifmt_ste16_b_dst_dspsp_basic_dst16_An_direct_QI, { 0x74840000 } + }, +/* lde.b ${Dsp-16-u20},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U20), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_ste16_b_dst_dspsp_basic_dst16_An_indirect_QI, { 0x74860000 } + }, +/* stc ${cr3-Prefixed-32},$Dst32RnPrefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DST32RNPREFIXEDSI), 0 } }, + & ifmt_stc32_src_cr3_dst32_Rn_direct_Prefixed_SI, { 0x1d910 } + }, +/* stc ${cr3-Prefixed-32},$Dst32AnPrefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DST32ANPREFIXEDSI), 0 } }, + & ifmt_stc32_src_cr3_dst32_An_direct_Prefixed_SI, { 0x1d190 } + }, +/* stc ${cr3-Prefixed-32},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr3_dst32_An_indirect_Prefixed_SI, { 0x1d110 } + }, +/* stc ${cr3-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr3_dst32_24_8_An_relative_Prefixed_SI, { 0x1d31000 } + }, +/* stc ${cr3-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr3_dst32_24_16_An_relative_Prefixed_SI, { 0x1d51000 } + }, +/* stc ${cr3-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr3_dst32_24_24_An_relative_Prefixed_SI, { 0x1d71000 } + }, +/* stc ${cr3-Prefixed-32},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stc32_src_cr3_dst32_24_8_SB_relative_Prefixed_SI, { 0x1d39000 } + }, +/* stc ${cr3-Prefixed-32},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_stc32_src_cr3_dst32_24_16_SB_relative_Prefixed_SI, { 0x1d59000 } + }, +/* stc ${cr3-Prefixed-32},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stc32_src_cr3_dst32_24_8_FB_relative_Prefixed_SI, { 0x1d3d000 } + }, +/* stc ${cr3-Prefixed-32},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_stc32_src_cr3_dst32_24_16_FB_relative_Prefixed_SI, { 0x1d5d000 } + }, +/* stc ${cr3-Prefixed-32},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U16), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_16_absolute_Prefixed_SI, { 0x1d7d000 } + }, +/* stc ${cr3-Prefixed-32},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR3_PREFIXED_32), ',', OP (DSP_24_U24), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_24_absolute_Prefixed_SI, { 0x1d79000 } + }, +/* stc ${cr2-32},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_stc32_src_cr2_dst32_Rn_direct_Unprefixed_SI, { 0xd910 } + }, +/* stc ${cr2-32},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_stc32_src_cr2_dst32_An_direct_Unprefixed_SI, { 0xd190 } + }, +/* stc ${cr2-32},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr2_dst32_An_indirect_Unprefixed_SI, { 0xd110 } + }, +/* stc ${cr2-32},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr2_dst32_16_8_An_relative_Unprefixed_SI, { 0xd31000 } + }, +/* stc ${cr2-32},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr2_dst32_16_16_An_relative_Unprefixed_SI, { 0xd5100000 } + }, +/* stc ${cr2-32},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr2_dst32_16_24_An_relative_Unprefixed_SI, { 0xd7100000 } + }, +/* stc ${cr2-32},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stc32_src_cr2_dst32_16_8_SB_relative_Unprefixed_SI, { 0xd39000 } + }, +/* stc ${cr2-32},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_stc32_src_cr2_dst32_16_16_SB_relative_Unprefixed_SI, { 0xd5900000 } + }, +/* stc ${cr2-32},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stc32_src_cr2_dst32_16_8_FB_relative_Unprefixed_SI, { 0xd3d000 } + }, +/* stc ${cr2-32},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_stc32_src_cr2_dst32_16_16_FB_relative_Unprefixed_SI, { 0xd5d00000 } + }, +/* stc ${cr2-32},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_16_absolute_Unprefixed_SI, { 0xd7d00000 } + }, +/* stc ${cr2-32},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), ',', OP (DSP_16_U24), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_24_absolute_Unprefixed_SI, { 0xd7900000 } + }, +/* stc ${cr1-Prefixed-32},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_stc32_src_cr1_dst32_Rn_direct_Prefixed_HI, { 0x1d918 } + }, +/* stc ${cr1-Prefixed-32},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_stc32_src_cr1_dst32_An_direct_Prefixed_HI, { 0x1d198 } + }, +/* stc ${cr1-Prefixed-32},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr1_dst32_An_indirect_Prefixed_HI, { 0x1d118 } + }, +/* stc ${cr1-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr1_dst32_24_8_An_relative_Prefixed_HI, { 0x1d31800 } + }, +/* stc ${cr1-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr1_dst32_24_16_An_relative_Prefixed_HI, { 0x1d51800 } + }, +/* stc ${cr1-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_stc32_src_cr1_dst32_24_24_An_relative_Prefixed_HI, { 0x1d71800 } + }, +/* stc ${cr1-Prefixed-32},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stc32_src_cr1_dst32_24_8_SB_relative_Prefixed_HI, { 0x1d39800 } + }, +/* stc ${cr1-Prefixed-32},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_stc32_src_cr1_dst32_24_16_SB_relative_Prefixed_HI, { 0x1d59800 } + }, +/* stc ${cr1-Prefixed-32},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stc32_src_cr1_dst32_24_8_FB_relative_Prefixed_HI, { 0x1d3d800 } + }, +/* stc ${cr1-Prefixed-32},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_stc32_src_cr1_dst32_24_16_FB_relative_Prefixed_HI, { 0x1d5d800 } + }, +/* stc ${cr1-Prefixed-32},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U16), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_16_absolute_Prefixed_HI, { 0x1d7d800 } + }, +/* stc ${cr1-Prefixed-32},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_PREFIXED_32), ',', OP (DSP_24_U24), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_24_absolute_Prefixed_HI, { 0x1d79800 } + }, +/* stc pc,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'p', 'c', ',', OP (DST16RNHI), 0 } }, + & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7cc0 } + }, +/* stc pc,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'p', 'c', ',', OP (DST16ANHI), 0 } }, + & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7cc4 } + }, +/* stc pc,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'p', 'c', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7cc6 } + }, +/* stc pc,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x7cc800 } + }, +/* stc pc,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x7ccc0000 } + }, +/* stc pc,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x7cca00 } + }, +/* stc pc,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x7cce0000 } + }, +/* stc pc,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x7ccb00 } + }, +/* stc pc,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'p', 'c', ',', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x7ccf0000 } + }, +/* stc ${cr16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), ',', OP (DST16RNHI), 0 } }, + & ifmt_stc16_src_dst16_Rn_direct_HI, { 0x7b80 } + }, +/* stc ${cr16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), ',', OP (DST16ANHI), 0 } }, + & ifmt_stc16_src_dst16_An_direct_HI, { 0x7b84 } + }, +/* stc ${cr16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_stc16_src_dst16_An_indirect_HI, { 0x7b86 } + }, +/* stc ${cr16},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_stc16_src_dst16_16_8_An_relative_HI, { 0x7b8800 } + }, +/* stc ${cr16},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_stc16_src_dst16_16_16_An_relative_HI, { 0x7b8c0000 } + }, +/* stc ${cr16},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stc16_src_dst16_16_8_SB_relative_HI, { 0x7b8a00 } + }, +/* stc ${cr16},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_stc16_src_dst16_16_16_SB_relative_HI, { 0x7b8e0000 } + }, +/* stc ${cr16},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stc16_src_dst16_16_8_FB_relative_HI, { 0x7b8b00 } + }, +/* stc ${cr16},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stc16_src_dst16_16_16_absolute_HI, { 0x7b8f0000 } + }, +/* ldc $Dst32RnPrefixedSI,${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNPREFIXEDSI), ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_Rn_direct_Prefixed_SI, { 0x1d900 } + }, +/* ldc $Dst32AnPrefixedSI,${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANPREFIXEDSI), ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_An_direct_Prefixed_SI, { 0x1d180 } + }, +/* ldc [$Dst32AnPrefixed],${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_An_indirect_Prefixed_SI, { 0x1d100 } + }, +/* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_8_An_relative_Prefixed_SI, { 0x1d30000 } + }, +/* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_16_An_relative_Prefixed_SI, { 0x1d50000 } + }, +/* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_24_An_relative_Prefixed_SI, { 0x1d70000 } + }, +/* ldc ${Dsp-24-u8}[sb],${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_8_SB_relative_Prefixed_SI, { 0x1d38000 } + }, +/* ldc ${Dsp-24-u16}[sb],${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_16_SB_relative_Prefixed_SI, { 0x1d58000 } + }, +/* ldc ${Dsp-24-s8}[fb],${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_8_FB_relative_Prefixed_SI, { 0x1d3c000 } + }, +/* ldc ${Dsp-24-s16}[fb],${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_16_FB_relative_Prefixed_SI, { 0x1d5c000 } + }, +/* ldc ${Dsp-24-u16},${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_16_absolute_Prefixed_SI, { 0x1d7c000 } + }, +/* ldc ${Dsp-24-u24},${cr3-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (CR3_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr3_dst32_24_24_absolute_Prefixed_SI, { 0x1d78000 } + }, +/* ldc $Dst32RnUnprefixedSI,${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_Rn_direct_Unprefixed_SI, { 0xd900 } + }, +/* ldc $Dst32AnUnprefixedSI,${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_An_direct_Unprefixed_SI, { 0xd180 } + }, +/* ldc [$Dst32AnUnprefixed],${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_An_indirect_Unprefixed_SI, { 0xd100 } + }, +/* ldc ${Dsp-16-u8}[$Dst32AnUnprefixed],${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_8_An_relative_Unprefixed_SI, { 0xd30000 } + }, +/* ldc ${Dsp-16-u16}[$Dst32AnUnprefixed],${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_16_An_relative_Unprefixed_SI, { 0xd5000000 } + }, +/* ldc ${Dsp-16-u24}[$Dst32AnUnprefixed],${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_24_An_relative_Unprefixed_SI, { 0xd7000000 } + }, +/* ldc ${Dsp-16-u8}[sb],${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_8_SB_relative_Unprefixed_SI, { 0xd38000 } + }, +/* ldc ${Dsp-16-u16}[sb],${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_16_SB_relative_Unprefixed_SI, { 0xd5800000 } + }, +/* ldc ${Dsp-16-s8}[fb],${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_8_FB_relative_Unprefixed_SI, { 0xd3c000 } + }, +/* ldc ${Dsp-16-s16}[fb],${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_16_FB_relative_Unprefixed_SI, { 0xd5c00000 } + }, +/* ldc ${Dsp-16-u16},${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_16_absolute_Unprefixed_SI, { 0xd7c00000 } + }, +/* ldc ${Dsp-16-u24},${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), ',', OP (CR2_32), 0 } }, + & ifmt_stc32_src_cr2_dst32_16_24_absolute_Unprefixed_SI, { 0xd7800000 } + }, +/* ldc $Dst32RnPrefixedHI,${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNPREFIXEDHI), ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_Rn_direct_Prefixed_HI, { 0x1d908 } + }, +/* ldc $Dst32AnPrefixedHI,${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANPREFIXEDHI), ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_An_direct_Prefixed_HI, { 0x1d188 } + }, +/* ldc [$Dst32AnPrefixed],${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_An_indirect_Prefixed_HI, { 0x1d108 } + }, +/* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_8_An_relative_Prefixed_HI, { 0x1d30800 } + }, +/* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_16_An_relative_Prefixed_HI, { 0x1d50800 } + }, +/* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_24_An_relative_Prefixed_HI, { 0x1d70800 } + }, +/* ldc ${Dsp-24-u8}[sb],${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_8_SB_relative_Prefixed_HI, { 0x1d38800 } + }, +/* ldc ${Dsp-24-u16}[sb],${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_16_SB_relative_Prefixed_HI, { 0x1d58800 } + }, +/* ldc ${Dsp-24-s8}[fb],${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_8_FB_relative_Prefixed_HI, { 0x1d3c800 } + }, +/* ldc ${Dsp-24-s16}[fb],${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_16_FB_relative_Prefixed_HI, { 0x1d5c800 } + }, +/* ldc ${Dsp-24-u16},${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_16_absolute_Prefixed_HI, { 0x1d7c800 } + }, +/* ldc ${Dsp-24-u24},${cr1-Prefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), ',', OP (CR1_PREFIXED_32), 0 } }, + & ifmt_stc32_src_cr1_dst32_24_24_absolute_Prefixed_HI, { 0x1d78800 } + }, +/* ldc $Dst16RnHI,${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), ',', OP (CR16), 0 } }, + & ifmt_stc16_src_dst16_Rn_direct_HI, { 0x7a80 } + }, +/* ldc $Dst16AnHI,${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), ',', OP (CR16), 0 } }, + & ifmt_stc16_src_dst16_An_direct_HI, { 0x7a84 } + }, +/* ldc [$Dst16An],${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', ',', OP (CR16), 0 } }, + & ifmt_stc16_src_dst16_An_indirect_HI, { 0x7a86 } + }, +/* ldc ${Dsp-16-u8}[$Dst16An],${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (CR16), 0 } }, + & ifmt_stc16_src_dst16_16_8_An_relative_HI, { 0x7a8800 } + }, +/* ldc ${Dsp-16-u16}[$Dst16An],${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (CR16), 0 } }, + & ifmt_stc16_src_dst16_16_16_An_relative_HI, { 0x7a8c0000 } + }, +/* ldc ${Dsp-16-u8}[sb],${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (CR16), 0 } }, + & ifmt_stc16_src_dst16_16_8_SB_relative_HI, { 0x7a8a00 } + }, +/* ldc ${Dsp-16-u16}[sb],${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (CR16), 0 } }, + & ifmt_stc16_src_dst16_16_16_SB_relative_HI, { 0x7a8e0000 } + }, +/* ldc ${Dsp-16-s8}[fb],${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (CR16), 0 } }, + & ifmt_stc16_src_dst16_16_8_FB_relative_HI, { 0x7a8b00 } + }, +/* ldc ${Dsp-16-u16},${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (CR16), 0 } }, + & ifmt_stc16_src_dst16_16_16_absolute_HI, { 0x7a8f0000 } + }, +/* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0x96010000 } + }, +/* jsri.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0x96810000 } + }, +/* jsri.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0x94010000 } + }, +/* jsri.a ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0x94810000 } + }, +/* jsri.a ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0x94c10000 } + }, +/* jsri.a ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0x96c10000 } + }, +/* jsri.a ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_An_relative_SI, { 0x7d1c0000 } + }, +/* jsri.a ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_SB_relative_SI, { 0x7d1e0000 } + }, +/* jsri.a ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_absolute_SI, { 0x7d1f0000 } + }, +/* jsri.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0x920100 } + }, +/* jsri.a ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0x928100 } + }, +/* jsri.a ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0x92c100 } + }, +/* jsri.a ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_An_relative_SI, { 0x7d1800 } + }, +/* jsri.a ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_SB_relative_SI, { 0x7d1a00 } + }, +/* jsri.a ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_FB_relative_SI, { 0x7d1b00 } + }, +/* jsri.a $Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0x9801 } + }, +/* jsri.a $Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0x9081 } + }, +/* jsri.a [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0x9001 } + }, +/* jsri.a $Dst16RnSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNSI), 0 } }, + & ifmt_jsri16a_dst16_basic_SI_dst16_Rn_direct_SI, { 0x7d10 } + }, +/* jsri.a $Dst16AnSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANSI), 0 } }, + & ifmt_jsri16a_dst16_basic_SI_dst16_An_direct_SI, { 0x7d14 } + }, +/* jsri.a [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI, { 0x7d16 } + }, +/* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc71f0000 } + }, +/* jsri.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc79f0000 } + }, +/* jsri.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc51f0000 } + }, +/* jsri.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc59f0000 } + }, +/* jsri.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5df0000 } + }, +/* jsri.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7df0000 } + }, +/* jsri.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x7d3c0000 } + }, +/* jsri.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x7d3e0000 } + }, +/* jsri.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x7d3f0000 } + }, +/* jsri.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc31f00 } + }, +/* jsri.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc39f00 } + }, +/* jsri.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3df00 } + }, +/* jsri.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x7d3800 } + }, +/* jsri.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x7d3a00 } + }, +/* jsri.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x7d3b00 } + }, +/* jsri.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc91f } + }, +/* jsri.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc19f } + }, +/* jsri.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc11f } + }, +/* jsri.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7d30 } + }, +/* jsri.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7d34 } + }, +/* jsri.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7d36 } + }, +/* jmpi.a $Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_shl32_l_dst_dst32_Rn_direct_Unprefixed_SI, { 0x8801 } + }, +/* jmpi.a $Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_exts32_w_16_ExtUnprefixed_dst32_An_direct_Unprefixed_SI, { 0x8081 } + }, +/* jmpi.a [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_An_indirect_Unprefixed_SI, { 0x8001 } + }, +/* jmpi.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_An_relative_Unprefixed_SI, { 0x820100 } + }, +/* jmpi.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_An_relative_Unprefixed_SI, { 0x84010000 } + }, +/* jmpi.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_An_relative_Unprefixed_SI, { 0x86010000 } + }, +/* jmpi.a ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_SB_relative_Unprefixed_SI, { 0x828100 } + }, +/* jmpi.a ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84810000 } + }, +/* jmpi.a ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82c100 } + }, +/* jmpi.a ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84c10000 } + }, +/* jmpi.a ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_l_dst_dst32_16_16_absolute_Unprefixed_SI, { 0x86c10000 } + }, +/* jmpi.a ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_l_dst_dst32_16_24_absolute_Unprefixed_SI, { 0x86810000 } + }, +/* jmpi.a $Dst16RnSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNSI), 0 } }, + & ifmt_jsri16a_dst16_basic_SI_dst16_Rn_direct_SI, { 0x7d00 } + }, +/* jmpi.a $Dst16AnSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANSI), 0 } }, + & ifmt_jsri16a_dst16_basic_SI_dst16_An_direct_SI, { 0x7d04 } + }, +/* jmpi.a [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_jsri16a_dst16_basic_SI_dst16_An_indirect_SI, { 0x7d06 } + }, +/* jmpi.a ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_An_relative_SI, { 0x7d0800 } + }, +/* jmpi.a ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_An_relative_SI, { 0x7d0c0000 } + }, +/* jmpi.a ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_SB_relative_SI, { 0x7d0a00 } + }, +/* jmpi.a ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_SB_relative_SI, { 0x7d0e0000 } + }, +/* jmpi.a ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_jsri16a_dst16_16_8_SI_dst16_16_8_FB_relative_SI, { 0x7d0b00 } + }, +/* jmpi.a ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_jsri16a_dst16_16_16_SI_dst16_16_16_absolute_SI, { 0x7d0f0000 } + }, +/* jmpi.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc90f } + }, +/* jmpi.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc18f } + }, +/* jmpi.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc10f } + }, +/* jmpi.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30f00 } + }, +/* jmpi.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50f0000 } + }, +/* jmpi.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70f0000 } + }, +/* jmpi.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38f00 } + }, +/* jmpi.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58f0000 } + }, +/* jmpi.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3cf00 } + }, +/* jmpi.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5cf0000 } + }, +/* jmpi.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7cf0000 } + }, +/* jmpi.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc78f0000 } + }, +/* jmpi.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_shl16_w_dst_dst16_Rn_direct_HI, { 0x7d20 } + }, +/* jmpi.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_shl16_w_dst_dst16_An_direct_HI, { 0x7d24 } + }, +/* jmpi.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_An_indirect_HI, { 0x7d26 } + }, +/* jmpi.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_An_relative_HI, { 0x7d2800 } + }, +/* jmpi.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_An_relative_HI, { 0x7d2c0000 } + }, +/* jmpi.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_SB_relative_HI, { 0x7d2a00 } + }, +/* jmpi.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_SB_relative_HI, { 0x7d2e0000 } + }, +/* jmpi.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl16_w_dst_dst16_16_8_FB_relative_HI, { 0x7d2b00 } + }, +/* jmpi.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl16_w_dst_dst16_16_16_absolute_HI, { 0x7d2f0000 } + }, +/* indexws.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc833 } + }, +/* indexws.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc0b3 } + }, +/* indexws.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc033 } + }, +/* indexws.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc23300 } + }, +/* indexws.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc4330000 } + }, +/* indexws.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc6330000 } + }, +/* indexws.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc2b300 } + }, +/* indexws.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc4b30000 } + }, +/* indexws.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc2f300 } + }, +/* indexws.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc4f30000 } + }, +/* indexws.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc6f30000 } + }, +/* indexws.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc6b30000 } + }, +/* indexws.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xc823 } + }, +/* indexws.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xc0a3 } + }, +/* indexws.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xc023 } + }, +/* indexws.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xc22300 } + }, +/* indexws.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4230000 } + }, +/* indexws.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6230000 } + }, +/* indexws.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc2a300 } + }, +/* indexws.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4a30000 } + }, +/* indexws.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2e300 } + }, +/* indexws.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4e30000 } + }, +/* indexws.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xc6e30000 } + }, +/* indexws.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc6a30000 } + }, +/* indexwd.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa833 } + }, +/* indexwd.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa0b3 } + }, +/* indexwd.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa033 } + }, +/* indexwd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa23300 } + }, +/* indexwd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa4330000 } + }, +/* indexwd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa6330000 } + }, +/* indexwd.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa2b300 } + }, +/* indexwd.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa4b30000 } + }, +/* indexwd.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa2f300 } + }, +/* indexwd.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa4f30000 } + }, +/* indexwd.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa6f30000 } + }, +/* indexwd.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa6b30000 } + }, +/* indexwd.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa823 } + }, +/* indexwd.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa0a3 } + }, +/* indexwd.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa023 } + }, +/* indexwd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa22300 } + }, +/* indexwd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa4230000 } + }, +/* indexwd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa6230000 } + }, +/* indexwd.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa2a300 } + }, +/* indexwd.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4a30000 } + }, +/* indexwd.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2e300 } + }, +/* indexwd.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4e30000 } + }, +/* indexwd.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6e30000 } + }, +/* indexwd.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6a30000 } + }, +/* indexw.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8833 } + }, +/* indexw.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x80b3 } + }, +/* indexw.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8033 } + }, +/* indexw.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x823300 } + }, +/* indexw.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x84330000 } + }, +/* indexw.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x86330000 } + }, +/* indexw.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x82b300 } + }, +/* indexw.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x84b30000 } + }, +/* indexw.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x82f300 } + }, +/* indexw.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x84f30000 } + }, +/* indexw.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x86f30000 } + }, +/* indexw.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x86b30000 } + }, +/* indexw.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x8823 } + }, +/* indexw.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x80a3 } + }, +/* indexw.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x8023 } + }, +/* indexw.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x822300 } + }, +/* indexw.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x84230000 } + }, +/* indexw.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x86230000 } + }, +/* indexw.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a300 } + }, +/* indexw.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a30000 } + }, +/* indexw.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e300 } + }, +/* indexw.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e30000 } + }, +/* indexw.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x86e30000 } + }, +/* indexw.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x86a30000 } + }, +/* indexls.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9813 } + }, +/* indexls.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x9093 } + }, +/* indexls.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9013 } + }, +/* indexls.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x921300 } + }, +/* indexls.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x94130000 } + }, +/* indexls.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x96130000 } + }, +/* indexls.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x929300 } + }, +/* indexls.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x94930000 } + }, +/* indexls.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x92d300 } + }, +/* indexls.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x94d30000 } + }, +/* indexls.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x96d30000 } + }, +/* indexls.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x96930000 } + }, +/* indexls.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x9803 } + }, +/* indexls.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x9083 } + }, +/* indexls.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x9003 } + }, +/* indexls.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x920300 } + }, +/* indexls.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x94030000 } + }, +/* indexls.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x96030000 } + }, +/* indexls.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x928300 } + }, +/* indexls.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94830000 } + }, +/* indexls.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92c300 } + }, +/* indexls.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94c30000 } + }, +/* indexls.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x96c30000 } + }, +/* indexls.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x96830000 } + }, +/* indexld.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb833 } + }, +/* indexld.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb0b3 } + }, +/* indexld.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb033 } + }, +/* indexld.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb23300 } + }, +/* indexld.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb4330000 } + }, +/* indexld.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb6330000 } + }, +/* indexld.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb2b300 } + }, +/* indexld.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb4b30000 } + }, +/* indexld.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb2f300 } + }, +/* indexld.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb4f30000 } + }, +/* indexld.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb6f30000 } + }, +/* indexld.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb6b30000 } + }, +/* indexld.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb823 } + }, +/* indexld.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb0a3 } + }, +/* indexld.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb023 } + }, +/* indexld.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb22300 } + }, +/* indexld.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb4230000 } + }, +/* indexld.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb6230000 } + }, +/* indexld.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb2a300 } + }, +/* indexld.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb4a30000 } + }, +/* indexld.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2e300 } + }, +/* indexld.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4e30000 } + }, +/* indexld.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6e30000 } + }, +/* indexld.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb6a30000 } + }, +/* indexl.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x9833 } + }, +/* indexl.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x90b3 } + }, +/* indexl.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x9033 } + }, +/* indexl.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x923300 } + }, +/* indexl.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x94330000 } + }, +/* indexl.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x96330000 } + }, +/* indexl.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x92b300 } + }, +/* indexl.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x94b30000 } + }, +/* indexl.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x92f300 } + }, +/* indexl.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x94f30000 } + }, +/* indexl.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x96f30000 } + }, +/* indexl.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x96b30000 } + }, +/* indexl.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x9823 } + }, +/* indexl.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x90a3 } + }, +/* indexl.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x9023 } + }, +/* indexl.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x922300 } + }, +/* indexl.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x94230000 } + }, +/* indexl.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x96230000 } + }, +/* indexl.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92a300 } + }, +/* indexl.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94a30000 } + }, +/* indexl.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92e300 } + }, +/* indexl.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94e30000 } + }, +/* indexl.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x96e30000 } + }, +/* indexl.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x96a30000 } + }, +/* indexbs.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc813 } + }, +/* indexbs.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc093 } + }, +/* indexbs.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc013 } + }, +/* indexbs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc21300 } + }, +/* indexbs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc4130000 } + }, +/* indexbs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc6130000 } + }, +/* indexbs.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc29300 } + }, +/* indexbs.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc4930000 } + }, +/* indexbs.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc2d300 } + }, +/* indexbs.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc4d30000 } + }, +/* indexbs.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc6d30000 } + }, +/* indexbs.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc6930000 } + }, +/* indexbs.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xc803 } + }, +/* indexbs.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xc083 } + }, +/* indexbs.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xc003 } + }, +/* indexbs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20300 } + }, +/* indexbs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4030000 } + }, +/* indexbs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6030000 } + }, +/* indexbs.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28300 } + }, +/* indexbs.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4830000 } + }, +/* indexbs.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c300 } + }, +/* indexbs.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c30000 } + }, +/* indexbs.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c30000 } + }, +/* indexbs.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc6830000 } + }, +/* indexbd.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa813 } + }, +/* indexbd.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa093 } + }, +/* indexbd.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa013 } + }, +/* indexbd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa21300 } + }, +/* indexbd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa4130000 } + }, +/* indexbd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa6130000 } + }, +/* indexbd.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa29300 } + }, +/* indexbd.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa4930000 } + }, +/* indexbd.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa2d300 } + }, +/* indexbd.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa4d30000 } + }, +/* indexbd.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa6d30000 } + }, +/* indexbd.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa6930000 } + }, +/* indexbd.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa803 } + }, +/* indexbd.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa083 } + }, +/* indexbd.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa003 } + }, +/* indexbd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa20300 } + }, +/* indexbd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa4030000 } + }, +/* indexbd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa6030000 } + }, +/* indexbd.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa28300 } + }, +/* indexbd.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa4830000 } + }, +/* indexbd.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2c300 } + }, +/* indexbd.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4c30000 } + }, +/* indexbd.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6c30000 } + }, +/* indexbd.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa6830000 } + }, +/* indexb.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x8813 } + }, +/* indexb.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x8093 } + }, +/* indexb.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x8013 } + }, +/* indexb.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x821300 } + }, +/* indexb.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x84130000 } + }, +/* indexb.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x86130000 } + }, +/* indexb.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x829300 } + }, +/* indexb.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x84930000 } + }, +/* indexb.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x82d300 } + }, +/* indexb.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x84d30000 } + }, +/* indexb.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x86d30000 } + }, +/* indexb.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x86930000 } + }, +/* indexb.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x8803 } + }, +/* indexb.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x8083 } + }, +/* indexb.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x8003 } + }, +/* indexb.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x820300 } + }, +/* indexb.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x84030000 } + }, +/* indexb.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x86030000 } + }, +/* indexb.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828300 } + }, +/* indexb.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84830000 } + }, +/* indexb.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c300 } + }, +/* indexb.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c30000 } + }, +/* indexb.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x86c30000 } + }, +/* indexb.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x86830000 } + }, +/* inc.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa90e } + }, +/* inc.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa18e } + }, +/* inc.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa10e } + }, +/* inc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa30e00 } + }, +/* inc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa50e0000 } + }, +/* inc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa70e0000 } + }, +/* inc.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa38e00 } + }, +/* inc.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa58e0000 } + }, +/* inc.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3ce00 } + }, +/* inc.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5ce0000 } + }, +/* inc.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7ce0000 } + }, +/* inc.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa78e0000 } + }, +/* inc.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa80e } + }, +/* inc.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa08e } + }, +/* inc.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa00e } + }, +/* inc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa20e00 } + }, +/* inc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa40e0000 } + }, +/* inc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa60e0000 } + }, +/* inc.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa28e00 } + }, +/* inc.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa48e0000 } + }, +/* inc.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2ce00 } + }, +/* inc.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4ce0000 } + }, +/* inc.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6ce0000 } + }, +/* inc.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa68e0000 } + }, +/* inc.b r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', 0 } }, + & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xa4 } + }, +/* inc.b r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', 0 } }, + & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xa3 } + }, +/* inc.b ${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_SB_relative_QI, { 0xa500 } + }, +/* inc.b ${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_FB_relative_QI, { 0xa600 } + }, +/* inc.b ${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_8_U16), 0 } }, + & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_16_absolute_QI, { 0xa70000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x990000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x992000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x993000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x918000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91a000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91b000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x910000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x912000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x913000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93000000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93200000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93300000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95000000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95200000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95300000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97000000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97200000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97300000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93800000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93a00000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93b00000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95800000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95a00000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95b00000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93c00000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93e00000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93f00000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95c00000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95e00000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95f00000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97c00000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97e00000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97f00000 } + }, +/* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97800000 } + }, +/* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97a00000 } + }, +/* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97b00000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9000000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9200000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9300000 } + }, +/* sub.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9300000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1800000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1a00000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1b00000 } + }, +/* sub.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1b00000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1000000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1200000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1300000 } + }, +/* sub.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1300000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3000000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3200000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3300000 } + }, +/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb3300000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5000000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5200000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5300000 } + }, +/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb5300000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7000000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7200000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7300000 } + }, +/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb7300000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3800000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3a00000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3b00000 } + }, +/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb3b00000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5800000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5a00000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5b00000 } + }, +/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb5b00000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3c00000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3e00000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3f00000 } + }, +/* sub.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb3f00000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5c00000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5e00000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5f00000 } + }, +/* sub.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb5f00000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7c00000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7e00000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7f00000 } + }, +/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xb7f00000 } + }, +/* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7800000 } + }, +/* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7a00000 } + }, +/* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7b00000 } + }, +/* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xb7b00000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9000000 } + }, +/* sub.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9200000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1800000 } + }, +/* sub.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1a00000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1000000 } + }, +/* sub.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1200000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3000000 } + }, +/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3200000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5000000 } + }, +/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5200000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7000000 } + }, +/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7200000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3800000 } + }, +/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3a00000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5800000 } + }, +/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5a00000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3c00000 } + }, +/* sub.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3e00000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5c00000 } + }, +/* sub.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5e00000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7c00000 } + }, +/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7e00000 } + }, +/* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7800000 } + }, +/* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7a00000 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xc900 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8920 } + }, +/* sub.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8900 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xc180 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x81a0 } + }, +/* sub.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x8180 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xc100 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8120 } + }, +/* sub.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8100 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc30000 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x832000 } + }, +/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x830000 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc5000000 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85200000 } + }, +/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85000000 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc7000000 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87200000 } + }, +/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87000000 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc38000 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x83a000 } + }, +/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x838000 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc5800000 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85a00000 } + }, +/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85800000 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc3c000 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83e000 } + }, +/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83c000 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc5c00000 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85e00000 } + }, +/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85c00000 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0xc7c00000 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87e00000 } + }, +/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87c00000 } + }, +/* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0xc7800000 } + }, +/* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87a00000 } + }, +/* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87800000 } + }, +/* sub.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x2f000000 } + }, +/* sub.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x3f000000 } + }, +/* sub.w${S} #${Imm-24-HI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x1f000000 } + }, +/* sub.w${S} #${Imm-8-HI},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } }, + & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0xf0000 } + }, +/* sub.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x2e0000 } + }, +/* sub.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x3e0000 } + }, +/* sub.b${S} #${Imm-24-QI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x1e000000 } + }, +/* sub.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0xe00 } + }, +/* sub.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x98310000 } + }, +/* sub.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x90b10000 } + }, +/* sub.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x90310000 } + }, +/* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x92310000 } + }, +/* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x92b10000 } + }, +/* sub.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x92f10000 } + }, +/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x94310000 } + }, +/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x94b10000 } + }, +/* sub.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x94f10000 } + }, +/* sub.l${G} #${Imm-32-SI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x96f10000 } + }, +/* sub.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x96310000 } + }, +/* sub.l${G} #${Imm-40-SI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x96b10000 } + }, +/* sub.b${S} ${SrcDst16-r0l-r0h-S-normal} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } }, + & ifmt_mov16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x28 } + }, +/* sub.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_mov16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x2900 } + }, +/* sub.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_mov16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x2a00 } + }, +/* sub.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } }, + & ifmt_mov16_b_S_src2_src16_2_S_16_absolute_QI, { 0x2b0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990a00 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992a00 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993a00 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918a00 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91aa00 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91ba00 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910a00 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912a00 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913a00 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x930a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x932a0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x933a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x950a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x952a0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x953a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x970a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x972a0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x973a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x938a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93aa0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93ba0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x958a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95aa0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95ba0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93ca0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93ea0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93fa0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95ca0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95ea0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95fa0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97ca0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97ea0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97fa0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x978a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97aa0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97ba0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa90a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa92a0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa93a0000 } + }, +/* sub.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb93a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa18a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1aa0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1ba0000 } + }, +/* sub.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1ba0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa10a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa12a0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa13a0000 } + }, +/* sub.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb13a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa30a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa32a0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa33a0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb33a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa50a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa52a0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa53a0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb53a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa70a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa72a0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa73a0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb73a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa38a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3aa0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3ba0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3ba0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa58a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5aa0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5ba0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5ba0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3ca0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3ea0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3fa0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3fa0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5ca0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5ea0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5fa0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5fa0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7ca0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7ea0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7fa0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7fa0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa78a0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7aa0000 } + }, +/* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7ba0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7ba0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb90a0000 } + }, +/* sub.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb92a0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb18a0000 } + }, +/* sub.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1aa0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb10a0000 } + }, +/* sub.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb12a0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb30a0000 } + }, +/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb32a0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb50a0000 } + }, +/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb52a0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb70a0000 } + }, +/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb72a0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb38a0000 } + }, +/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3aa0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb58a0000 } + }, +/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5aa0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3ca0000 } + }, +/* sub.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3ea0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5ca0000 } + }, +/* sub.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5ea0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7ca0000 } + }, +/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7ea0000 } + }, +/* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb78a0000 } + }, +/* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7aa0000 } + }, +/* sub.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc90a } + }, +/* sub.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x892a } + }, +/* sub.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x890a } + }, +/* sub.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc18a } + }, +/* sub.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81aa } + }, +/* sub.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x818a } + }, +/* sub.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc10a } + }, +/* sub.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x812a } + }, +/* sub.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x810a } + }, +/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30a00 } + }, +/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832a00 } + }, +/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830a00 } + }, +/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50a0000 } + }, +/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x852a0000 } + }, +/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x850a0000 } + }, +/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70a0000 } + }, +/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x872a0000 } + }, +/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x870a0000 } + }, +/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38a00 } + }, +/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83aa00 } + }, +/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838a00 } + }, +/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58a0000 } + }, +/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85aa0000 } + }, +/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858a0000 } + }, +/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3ca00 } + }, +/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ea00 } + }, +/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ca00 } + }, +/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5ca0000 } + }, +/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ea0000 } + }, +/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ca0000 } + }, +/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7ca0000 } + }, +/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87ea0000 } + }, +/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87ca0000 } + }, +/* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc78a0000 } + }, +/* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87aa0000 } + }, +/* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x878a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980a00 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982a00 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983a00 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908a00 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90aa00 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90ba00 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900a00 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902a00 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903a00 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x920a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x922a0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x923a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x940a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x942a0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x943a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x960a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x962a0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x963a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x928a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92aa0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92ba0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x948a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94aa0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94ba0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92ca0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92ea0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92fa0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94ca0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94ea0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94fa0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96ca0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96ea0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96fa0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x968a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96aa0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96ba0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa80a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa82a0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa83a0000 } + }, +/* sub.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb83a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa08a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0aa0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0ba0000 } + }, +/* sub.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0ba0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa00a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa02a0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa03a0000 } + }, +/* sub.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb03a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa20a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa22a0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa23a0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb23a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa40a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa42a0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa43a0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb43a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa60a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa62a0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa63a0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb63a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa28a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2aa0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2ba0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2ba0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa48a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4aa0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4ba0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4ba0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2ca0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2ea0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2fa0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2fa0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4ca0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4ea0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4fa0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4fa0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6ca0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6ea0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6fa0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6fa0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa68a0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6aa0000 } + }, +/* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6ba0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6ba0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb80a0000 } + }, +/* sub.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb82a0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb08a0000 } + }, +/* sub.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0aa0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb00a0000 } + }, +/* sub.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb02a0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb20a0000 } + }, +/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb22a0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb40a0000 } + }, +/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb42a0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb60a0000 } + }, +/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb62a0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb28a0000 } + }, +/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2aa0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb48a0000 } + }, +/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4aa0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2ca0000 } + }, +/* sub.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2ea0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4ca0000 } + }, +/* sub.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4ea0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6ca0000 } + }, +/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6ea0000 } + }, +/* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb68a0000 } + }, +/* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6aa0000 } + }, +/* sub.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc80a } + }, +/* sub.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x882a } + }, +/* sub.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x880a } + }, +/* sub.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc08a } + }, +/* sub.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80aa } + }, +/* sub.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x808a } + }, +/* sub.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc00a } + }, +/* sub.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x802a } + }, +/* sub.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x800a } + }, +/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20a00 } + }, +/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822a00 } + }, +/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820a00 } + }, +/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40a0000 } + }, +/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x842a0000 } + }, +/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x840a0000 } + }, +/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60a0000 } + }, +/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x862a0000 } + }, +/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x860a0000 } + }, +/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28a00 } + }, +/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82aa00 } + }, +/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828a00 } + }, +/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48a0000 } + }, +/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84aa0000 } + }, +/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848a0000 } + }, +/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2ca00 } + }, +/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ea00 } + }, +/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ca00 } + }, +/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4ca0000 } + }, +/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ea0000 } + }, +/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ca0000 } + }, +/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6ca0000 } + }, +/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86ea0000 } + }, +/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86ca0000 } + }, +/* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc68a0000 } + }, +/* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86aa0000 } + }, +/* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x868a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xa98000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xa9a000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xa9b000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xa98400 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xa9a400 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xa9b400 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xa98600 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xa9a600 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xa9b600 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xa9880000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xa9a80000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xa9b80000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xa98c0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xa9ac0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xa9bc0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xa98a0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xa9aa0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xa9ba0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xa98e0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xa9ae0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xa9be0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xa98b0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xa9ab0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xa9bb0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xa98f0000 } + }, +/* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xa9af0000 } + }, +/* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xa9bf0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xa9c00000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xa9e00000 } + }, +/* sub.w${G} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xa9f00000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xa9c40000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xa9e40000 } + }, +/* sub.w${G} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xa9f40000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xa9c60000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xa9e60000 } + }, +/* sub.w${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xa9f60000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xa9c80000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xa9e80000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xa9f80000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xa9cc0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xa9ec0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xa9fc0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xa9ca0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xa9ea0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xa9fa0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xa9ce0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xa9ee0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xa9fe0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xa9cb0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xa9eb0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xa9fb0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xa9cf0000 } + }, +/* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xa9ef0000 } + }, +/* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xa9ff0000 } + }, +/* sub.w${G} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xa900 } + }, +/* sub.w${G} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xa940 } + }, +/* sub.w${G} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xa960 } + }, +/* sub.w${G} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xa904 } + }, +/* sub.w${G} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xa944 } + }, +/* sub.w${G} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xa964 } + }, +/* sub.w${G} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xa906 } + }, +/* sub.w${G} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xa946 } + }, +/* sub.w${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xa966 } + }, +/* sub.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xa90800 } + }, +/* sub.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xa94800 } + }, +/* sub.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xa96800 } + }, +/* sub.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xa90c0000 } + }, +/* sub.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xa94c0000 } + }, +/* sub.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xa96c0000 } + }, +/* sub.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xa90a00 } + }, +/* sub.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xa94a00 } + }, +/* sub.w${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xa96a00 } + }, +/* sub.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xa90e0000 } + }, +/* sub.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xa94e0000 } + }, +/* sub.w${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xa96e0000 } + }, +/* sub.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xa90b00 } + }, +/* sub.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xa94b00 } + }, +/* sub.w${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xa96b00 } + }, +/* sub.w${G} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xa90f0000 } + }, +/* sub.w${G} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xa94f0000 } + }, +/* sub.w${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xa96f0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xa88000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xa8a000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xa8b000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xa88400 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xa8a400 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xa8b400 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xa88600 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xa8a600 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xa8b600 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xa8880000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xa8a80000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xa8b80000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xa88c0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xa8ac0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xa8bc0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xa88a0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xa8aa0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xa8ba0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xa88e0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xa8ae0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xa8be0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xa88b0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xa8ab0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xa8bb0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xa88f0000 } + }, +/* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xa8af0000 } + }, +/* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xa8bf0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xa8c00000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xa8e00000 } + }, +/* sub.b${G} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xa8f00000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xa8c40000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xa8e40000 } + }, +/* sub.b${G} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xa8f40000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xa8c60000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xa8e60000 } + }, +/* sub.b${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xa8f60000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xa8c80000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xa8e80000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xa8f80000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xa8cc0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xa8ec0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xa8fc0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xa8ca0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xa8ea0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xa8fa0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xa8ce0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xa8ee0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xa8fe0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xa8cb0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xa8eb0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xa8fb0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xa8cf0000 } + }, +/* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xa8ef0000 } + }, +/* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xa8ff0000 } + }, +/* sub.b${G} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xa800 } + }, +/* sub.b${G} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xa840 } + }, +/* sub.b${G} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xa860 } + }, +/* sub.b${G} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xa804 } + }, +/* sub.b${G} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xa844 } + }, +/* sub.b${G} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xa864 } + }, +/* sub.b${G} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xa806 } + }, +/* sub.b${G} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xa846 } + }, +/* sub.b${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xa866 } + }, +/* sub.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xa80800 } + }, +/* sub.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xa84800 } + }, +/* sub.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xa86800 } + }, +/* sub.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xa80c0000 } + }, +/* sub.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xa84c0000 } + }, +/* sub.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xa86c0000 } + }, +/* sub.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xa80a00 } + }, +/* sub.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xa84a00 } + }, +/* sub.b${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xa86a00 } + }, +/* sub.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xa80e0000 } + }, +/* sub.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xa84e0000 } + }, +/* sub.b${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xa86e0000 } + }, +/* sub.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xa80b00 } + }, +/* sub.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xa84b00 } + }, +/* sub.b${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xa86b00 } + }, +/* sub.b${G} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xa80f0000 } + }, +/* sub.b${G} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xa84f0000 } + }, +/* sub.b${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xa86f0000 } + }, +/* sub.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0x8c00 } + }, +/* sub.b${S} #${Imm-8-QI},r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0x8b00 } + }, +/* sub.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0x8d0000 } + }, +/* sub.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0x8e0000 } + }, +/* sub.b${S} #${Imm-8-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0x8f000000 } + }, +/* sub.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x893e0000 } + }, +/* sub.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x81be0000 } + }, +/* sub.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x813e0000 } + }, +/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x833e0000 } + }, +/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83be0000 } + }, +/* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83fe0000 } + }, +/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x853e0000 } + }, +/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85be0000 } + }, +/* sub.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85fe0000 } + }, +/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87fe0000 } + }, +/* sub.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x873e0000 } + }, +/* sub.w${G} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x87be0000 } + }, +/* sub.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x883e00 } + }, +/* sub.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x80be00 } + }, +/* sub.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x803e00 } + }, +/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x823e0000 } + }, +/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82be0000 } + }, +/* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82fe0000 } + }, +/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x843e0000 } + }, +/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84be0000 } + }, +/* sub.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84fe0000 } + }, +/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86fe0000 } + }, +/* sub.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x863e0000 } + }, +/* sub.b${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x86be0000 } + }, +/* sub.w${G} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77500000 } + }, +/* sub.w${G} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77540000 } + }, +/* sub.w${G} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77560000 } + }, +/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77580000 } + }, +/* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x775a0000 } + }, +/* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x775b0000 } + }, +/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x775c0000 } + }, +/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x775e0000 } + }, +/* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x775f0000 } + }, +/* sub.b${G} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x765000 } + }, +/* sub.b${G} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x765400 } + }, +/* sub.b${G} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x765600 } + }, +/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76580000 } + }, +/* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x765a0000 } + }, +/* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x765b0000 } + }, +/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x765c0000 } + }, +/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x765e0000 } + }, +/* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x765f0000 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978200 } + }, +/* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a200 } + }, +/* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93200 } + }, +/* dsub.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b200 } + }, +/* dsub.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13200 } + }, +/* dsub.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33200 } + }, +/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53200 } + }, +/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73200 } + }, +/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b200 } + }, +/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b200 } + }, +/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f200 } + }, +/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f200 } + }, +/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f200 } + }, +/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78200 } + }, +/* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a200 } + }, +/* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b200 } + }, +/* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90200 } + }, +/* dsub.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18200 } + }, +/* dsub.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10200 } + }, +/* dsub.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30200 } + }, +/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50200 } + }, +/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70200 } + }, +/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38200 } + }, +/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58200 } + }, +/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c200 } + }, +/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c200 } + }, +/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c200 } + }, +/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e200 } + }, +/* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78200 } + }, +/* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a200 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c902 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18922 } + }, +/* dsub.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18902 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c182 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a2 } + }, +/* dsub.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18182 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c102 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18122 } + }, +/* dsub.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18102 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30200 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832200 } + }, +/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830200 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50200 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852200 } + }, +/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850200 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70200 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872200 } + }, +/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870200 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38200 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a200 } + }, +/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838200 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58200 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a200 } + }, +/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858200 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c200 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e200 } + }, +/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c200 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c200 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e200 } + }, +/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c200 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c200 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e200 } + }, +/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c200 } + }, +/* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78200 } + }, +/* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a200 } + }, +/* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968200 } + }, +/* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a200 } + }, +/* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83200 } + }, +/* dsub.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b200 } + }, +/* dsub.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03200 } + }, +/* dsub.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23200 } + }, +/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43200 } + }, +/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63200 } + }, +/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b200 } + }, +/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b200 } + }, +/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f200 } + }, +/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f200 } + }, +/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f200 } + }, +/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68200 } + }, +/* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a200 } + }, +/* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b200 } + }, +/* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80200 } + }, +/* dsub.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08200 } + }, +/* dsub.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00200 } + }, +/* dsub.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20200 } + }, +/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40200 } + }, +/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60200 } + }, +/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28200 } + }, +/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48200 } + }, +/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c200 } + }, +/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c200 } + }, +/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c200 } + }, +/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e200 } + }, +/* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68200 } + }, +/* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a200 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c802 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18822 } + }, +/* dsub.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18802 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c082 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a2 } + }, +/* dsub.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18082 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c002 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18022 } + }, +/* dsub.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18002 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20200 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822200 } + }, +/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820200 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40200 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842200 } + }, +/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840200 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60200 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862200 } + }, +/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860200 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28200 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a200 } + }, +/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828200 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48200 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a200 } + }, +/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848200 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c200 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e200 } + }, +/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c200 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c200 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e200 } + }, +/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c200 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c200 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e200 } + }, +/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c200 } + }, +/* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68200 } + }, +/* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a200 } + }, +/* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868200 } + }, +/* dsub.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1991e00 } + }, +/* dsub.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x1919e00 } + }, +/* dsub.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1911e00 } + }, +/* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1931e00 } + }, +/* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x1939e00 } + }, +/* dsub.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x193de00 } + }, +/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1951e00 } + }, +/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x1959e00 } + }, +/* dsub.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x195de00 } + }, +/* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x197de00 } + }, +/* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1971e00 } + }, +/* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x1979e00 } + }, +/* dsub.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1981e00 } + }, +/* dsub.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x1909e00 } + }, +/* dsub.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1901e00 } + }, +/* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1921e00 } + }, +/* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x1929e00 } + }, +/* dsub.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x192de00 } + }, +/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1941e00 } + }, +/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x1949e00 } + }, +/* dsub.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x194de00 } + }, +/* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x196de00 } + }, +/* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1961e00 } + }, +/* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x1969e00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992a00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191aa00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912a00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932a00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952a00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972a00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193aa00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195aa00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193ca00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193ea00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193fa00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195ca00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195ea00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195fa00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197ca00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197ea00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197fa00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978a00 } + }, +/* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197aa00 } + }, +/* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92a00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1aa00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12a00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32a00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52a00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72a00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3aa00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5aa00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3ca00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3ea00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3fa00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3fa00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5ca00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5ea00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5fa00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5fa00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7ca00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7ea00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7fa00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7fa00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78a00 } + }, +/* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7aa00 } + }, +/* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7ba00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1aa00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3aa00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5aa00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3ca00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3ea00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5ca00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5ea00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7ca00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7ea00 } + }, +/* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78a00 } + }, +/* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7aa00 } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c90a } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1892a } + }, +/* dsbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1890a } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c18a } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181aa } + }, +/* dsbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1818a } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c10a } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1812a } + }, +/* dsbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1810a } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30a00 } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832a00 } + }, +/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830a00 } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50a00 } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852a00 } + }, +/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850a00 } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70a00 } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872a00 } + }, +/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870a00 } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38a00 } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183aa00 } + }, +/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838a00 } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58a00 } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185aa00 } + }, +/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858a00 } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3ca00 } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ea00 } + }, +/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ca00 } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5ca00 } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ea00 } + }, +/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ca00 } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7ca00 } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187ea00 } + }, +/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187ca00 } + }, +/* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78a00 } + }, +/* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187aa00 } + }, +/* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982a00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190aa00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902a00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922a00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942a00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962a00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192aa00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194aa00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192ca00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192ea00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192fa00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194ca00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194ea00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194fa00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196ca00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196ea00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196fa00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968a00 } + }, +/* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196aa00 } + }, +/* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82a00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0aa00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02a00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22a00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42a00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62a00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2aa00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4aa00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2ca00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2ea00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2fa00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2fa00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4ca00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4ea00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4fa00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4fa00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6ca00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6ea00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6fa00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6fa00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68a00 } + }, +/* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6aa00 } + }, +/* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6ba00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0aa00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2aa00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4aa00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2ca00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2ea00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4ca00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4ea00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6ca00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6ea00 } + }, +/* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68a00 } + }, +/* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6aa00 } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c80a } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1882a } + }, +/* dsbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1880a } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c08a } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180aa } + }, +/* dsbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1808a } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c00a } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1802a } + }, +/* dsbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1800a } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20a00 } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822a00 } + }, +/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820a00 } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40a00 } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842a00 } + }, +/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840a00 } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60a00 } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862a00 } + }, +/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860a00 } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28a00 } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182aa00 } + }, +/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828a00 } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48a00 } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184aa00 } + }, +/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848a00 } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2ca00 } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ea00 } + }, +/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ca00 } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4ca00 } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ea00 } + }, +/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ca00 } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6ca00 } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186ea00 } + }, +/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186ca00 } + }, +/* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68a00 } + }, +/* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186aa00 } + }, +/* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868a00 } + }, +/* dsbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1990e00 } + }, +/* dsbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x1918e00 } + }, +/* dsbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1910e00 } + }, +/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1930e00 } + }, +/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x1938e00 } + }, +/* dsbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x193ce00 } + }, +/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1950e00 } + }, +/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x1958e00 } + }, +/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x195ce00 } + }, +/* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x197ce00 } + }, +/* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1970e00 } + }, +/* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x1978e00 } + }, +/* dsbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1980e00 } + }, +/* dsbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x1908e00 } + }, +/* dsbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1900e00 } + }, +/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1920e00 } + }, +/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x1928e00 } + }, +/* dsbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x192ce00 } + }, +/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1940e00 } + }, +/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x1948e00 } + }, +/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x194ce00 } + }, +/* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x196ce00 } + }, +/* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1960e00 } + }, +/* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x1968e00 } + }, +/* divx.l $Dst32RnPrefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNPREFIXEDSI), 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_Rn_direct_Prefixed_SI, { 0x1a92f } + }, +/* divx.l $Dst32AnPrefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANPREFIXEDSI), 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_An_direct_Prefixed_SI, { 0x1a1af } + }, +/* divx.l [$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_An_indirect_Prefixed_SI, { 0x1a12f } + }, +/* divx.l ${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_An_relative_Prefixed_SI, { 0x1a32f00 } + }, +/* divx.l ${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_An_relative_Prefixed_SI, { 0x1a52f00 } + }, +/* divx.l ${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_24_An_relative_Prefixed_SI, { 0x1a72f00 } + }, +/* divx.l ${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_SB_relative_Prefixed_SI, { 0x1a3af00 } + }, +/* divx.l ${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_SB_relative_Prefixed_SI, { 0x1a5af00 } + }, +/* divx.l ${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_FB_relative_Prefixed_SI, { 0x1a3ef00 } + }, +/* divx.l ${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_FB_relative_Prefixed_SI, { 0x1a5ef00 } + }, +/* divx.l ${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_absolute_Prefixed_SI, { 0x1a7ef00 } + }, +/* divx.l ${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_24_absolute_Prefixed_SI, { 0x1a7af00 } + }, +/* divu.l $Dst32RnPrefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNPREFIXEDSI), 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_Rn_direct_Prefixed_SI, { 0x1a90f } + }, +/* divu.l $Dst32AnPrefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANPREFIXEDSI), 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_An_direct_Prefixed_SI, { 0x1a18f } + }, +/* divu.l [$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_An_indirect_Prefixed_SI, { 0x1a10f } + }, +/* divu.l ${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_An_relative_Prefixed_SI, { 0x1a30f00 } + }, +/* divu.l ${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_An_relative_Prefixed_SI, { 0x1a50f00 } + }, +/* divu.l ${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_24_An_relative_Prefixed_SI, { 0x1a70f00 } + }, +/* divu.l ${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_SB_relative_Prefixed_SI, { 0x1a38f00 } + }, +/* divu.l ${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_SB_relative_Prefixed_SI, { 0x1a58f00 } + }, +/* divu.l ${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_FB_relative_Prefixed_SI, { 0x1a3cf00 } + }, +/* divu.l ${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_FB_relative_Prefixed_SI, { 0x1a5cf00 } + }, +/* divu.l ${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_absolute_Prefixed_SI, { 0x1a7cf00 } + }, +/* divu.l ${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_24_absolute_Prefixed_SI, { 0x1a78f00 } + }, +/* div.l $Dst32RnPrefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNPREFIXEDSI), 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_Rn_direct_Prefixed_SI, { 0x1a91f } + }, +/* div.l $Dst32AnPrefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANPREFIXEDSI), 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_An_direct_Prefixed_SI, { 0x1a19f } + }, +/* div.l [$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_An_indirect_Prefixed_SI, { 0x1a11f } + }, +/* div.l ${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_An_relative_Prefixed_SI, { 0x1a31f00 } + }, +/* div.l ${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_An_relative_Prefixed_SI, { 0x1a51f00 } + }, +/* div.l ${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_24_An_relative_Prefixed_SI, { 0x1a71f00 } + }, +/* div.l ${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_SB_relative_Prefixed_SI, { 0x1a39f00 } + }, +/* div.l ${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_SB_relative_Prefixed_SI, { 0x1a59f00 } + }, +/* div.l ${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_8_FB_relative_Prefixed_SI, { 0x1a3df00 } + }, +/* div.l ${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_FB_relative_Prefixed_SI, { 0x1a5df00 } + }, +/* div.l ${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U16), 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_16_absolute_Prefixed_SI, { 0x1a7df00 } + }, +/* div.l ${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_24_U24), 0 } }, + & ifmt_divx32_l_dst32_24_Prefixed_SI_dst32_24_24_absolute_Prefixed_SI, { 0x1a79f00 } + }, +/* divx.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x991e } + }, +/* divx.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x919e } + }, +/* divx.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x911e } + }, +/* divx.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x931e00 } + }, +/* divx.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x951e0000 } + }, +/* divx.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x971e0000 } + }, +/* divx.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x939e00 } + }, +/* divx.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x959e0000 } + }, +/* divx.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93de00 } + }, +/* divx.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95de0000 } + }, +/* divx.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x97de0000 } + }, +/* divx.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x979e0000 } + }, +/* divx.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x981e } + }, +/* divx.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x909e } + }, +/* divx.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x901e } + }, +/* divx.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x921e00 } + }, +/* divx.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x941e0000 } + }, +/* divx.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x961e0000 } + }, +/* divx.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x929e00 } + }, +/* divx.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x949e0000 } + }, +/* divx.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92de00 } + }, +/* divx.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94de0000 } + }, +/* divx.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x96de0000 } + }, +/* divx.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x969e0000 } + }, +/* divx.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x7790 } + }, +/* divx.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x7794 } + }, +/* divx.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x7796 } + }, +/* divx.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x779800 } + }, +/* divx.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x779c0000 } + }, +/* divx.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x779a00 } + }, +/* divx.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x779e0000 } + }, +/* divx.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x779b00 } + }, +/* divx.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x779f0000 } + }, +/* divx.b $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x7690 } + }, +/* divx.b $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x7694 } + }, +/* divx.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x7696 } + }, +/* divx.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x769800 } + }, +/* divx.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x769c0000 } + }, +/* divx.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x769a00 } + }, +/* divx.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x769e0000 } + }, +/* divx.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x769b00 } + }, +/* divx.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x769f0000 } + }, +/* divu.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x890e } + }, +/* divu.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x818e } + }, +/* divu.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x810e } + }, +/* divu.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x830e00 } + }, +/* divu.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x850e0000 } + }, +/* divu.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x870e0000 } + }, +/* divu.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838e00 } + }, +/* divu.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858e0000 } + }, +/* divu.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ce00 } + }, +/* divu.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ce0000 } + }, +/* divu.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x87ce0000 } + }, +/* divu.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x878e0000 } + }, +/* divu.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x880e } + }, +/* divu.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x808e } + }, +/* divu.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x800e } + }, +/* divu.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x820e00 } + }, +/* divu.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x840e0000 } + }, +/* divu.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x860e0000 } + }, +/* divu.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828e00 } + }, +/* divu.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848e0000 } + }, +/* divu.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ce00 } + }, +/* divu.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ce0000 } + }, +/* divu.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x86ce0000 } + }, +/* divu.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x868e0000 } + }, +/* divu.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77c0 } + }, +/* divu.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77c4 } + }, +/* divu.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77c6 } + }, +/* divu.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77c800 } + }, +/* divu.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77cc0000 } + }, +/* divu.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77ca00 } + }, +/* divu.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77ce0000 } + }, +/* divu.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77cb00 } + }, +/* divu.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77cf0000 } + }, +/* divu.b $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76c0 } + }, +/* divu.b $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76c4 } + }, +/* divu.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76c6 } + }, +/* divu.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76c800 } + }, +/* divu.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76cc0000 } + }, +/* divu.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76ca00 } + }, +/* divu.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76ce0000 } + }, +/* divu.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76cb00 } + }, +/* divu.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76cf0000 } + }, +/* div.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0x891e } + }, +/* div.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0x819e } + }, +/* div.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0x811e } + }, +/* div.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0x831e00 } + }, +/* div.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0x851e0000 } + }, +/* div.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0x871e0000 } + }, +/* div.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0x839e00 } + }, +/* div.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0x859e0000 } + }, +/* div.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83de00 } + }, +/* div.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85de0000 } + }, +/* div.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0x87de0000 } + }, +/* div.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0x879e0000 } + }, +/* div.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0x881e } + }, +/* div.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0x809e } + }, +/* div.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0x801e } + }, +/* div.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0x821e00 } + }, +/* div.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0x841e0000 } + }, +/* div.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0x861e0000 } + }, +/* div.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0x829e00 } + }, +/* div.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0x849e0000 } + }, +/* div.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82de00 } + }, +/* div.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84de0000 } + }, +/* div.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0x86de0000 } + }, +/* div.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0x869e0000 } + }, +/* div.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77d0 } + }, +/* div.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77d4 } + }, +/* div.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77d6 } + }, +/* div.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77d800 } + }, +/* div.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77dc0000 } + }, +/* div.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77da00 } + }, +/* div.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77de0000 } + }, +/* div.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77db00 } + }, +/* div.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77df0000 } + }, +/* div.b $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76d0 } + }, +/* div.b $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76d4 } + }, +/* div.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76d6 } + }, +/* div.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76d800 } + }, +/* div.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76dc0000 } + }, +/* div.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76da00 } + }, +/* div.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76de0000 } + }, +/* div.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76db00 } + }, +/* div.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76df0000 } + }, +/* dec.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb90e } + }, +/* dec.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb18e } + }, +/* dec.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb10e } + }, +/* dec.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb30e00 } + }, +/* dec.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb50e0000 } + }, +/* dec.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb70e0000 } + }, +/* dec.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb38e00 } + }, +/* dec.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb58e0000 } + }, +/* dec.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3ce00 } + }, +/* dec.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5ce0000 } + }, +/* dec.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7ce0000 } + }, +/* dec.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb78e0000 } + }, +/* dec.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb80e } + }, +/* dec.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb08e } + }, +/* dec.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb00e } + }, +/* dec.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb20e00 } + }, +/* dec.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb40e0000 } + }, +/* dec.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb60e0000 } + }, +/* dec.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb28e00 } + }, +/* dec.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb48e0000 } + }, +/* dec.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2ce00 } + }, +/* dec.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4ce0000 } + }, +/* dec.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6ce0000 } + }, +/* dec.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb68e0000 } + }, +/* dec.b r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'l', 0 } }, + & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xac } + }, +/* dec.b r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', 0 } }, + & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xab } + }, +/* dec.b ${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_SB_relative_QI, { 0xad00 } + }, +/* dec.b ${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_8_FB_relative_QI, { 0xae00 } + }, +/* dec.b ${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_8_U16), 0 } }, + & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_16_absolute_QI, { 0xaf0000 } + }, +/* cmpx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xa81100 } + }, +/* cmpx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xa09100 } + }, +/* cmpx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xa01100 } + }, +/* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xa2110000 } + }, +/* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa2910000 } + }, +/* cmpx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2d10000 } + }, +/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xa4110000 } + }, +/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4910000 } + }, +/* cmpx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4d10000 } + }, +/* cmpx${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xa6d10000 } + }, +/* cmpx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xa6110000 } + }, +/* cmpx${X} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xa6910000 } + }, +/* cmp.w${S} ${Dsp-8-u8}[sb],${Dst32R0HI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST32R0HI_S), 0 } }, + & ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_SB_relative_HI, { 0x6100 } + }, +/* cmp.w${S} ${Dsp-8-s8}[fb],${Dst32R0HI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST32R0HI_S), 0 } }, + & ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_8_FB_relative_HI, { 0x7100 } + }, +/* cmp.w${S} ${Dsp-8-u16},${Dst32R0HI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST32R0HI_S), 0 } }, + & ifmt_cmp32_w_S_src2_r0_HI_src32_2_S_16_absolute_HI, { 0x510000 } + }, +/* cmp.b${S} ${Dsp-8-u8}[sb],${Dst32R0QI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST32R0QI_S), 0 } }, + & ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_8_SB_relative_QI, { 0x6000 } + }, +/* cmp.b${S} ${Dsp-8-s8}[fb],${Dst32R0QI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST32R0QI_S), 0 } }, + & ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_8_FB_relative_QI, { 0x7000 } + }, +/* cmp.b${S} ${Dsp-8-u16},${Dst32R0QI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST32R0QI_S), 0 } }, + & ifmt_cmp32_b_S_src2_r0_QI_src32_2_S_16_absolute_QI, { 0x500000 } + }, +/* cmp.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x67000000 } + }, +/* cmp.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x77000000 } + }, +/* cmp.w${S} #${Imm-24-HI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x57000000 } + }, +/* cmp.w${S} #${Imm-8-HI},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } }, + & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x470000 } + }, +/* cmp.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x660000 } + }, +/* cmp.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x760000 } + }, +/* cmp.b${S} #${Imm-24-QI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x56000000 } + }, +/* cmp.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x4600 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x990100 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x992100 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x993100 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x918100 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91a100 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91b100 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x910100 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x912100 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x913100 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93010000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93210000 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93310000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95010000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95210000 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95310000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97010000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97210000 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97310000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93810000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93a10000 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93b10000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95810000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95a10000 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95b10000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93c10000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93e10000 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93f10000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95c10000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95e10000 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95f10000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97c10000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97e10000 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97f10000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97810000 } + }, +/* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97a10000 } + }, +/* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97b10000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9010000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9210000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9310000 } + }, +/* cmp.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9310000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1810000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1a10000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1b10000 } + }, +/* cmp.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1b10000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1010000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1210000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1310000 } + }, +/* cmp.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1310000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3010000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3210000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3310000 } + }, +/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb3310000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5010000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5210000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5310000 } + }, +/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb5310000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7010000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7210000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7310000 } + }, +/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb7310000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3810000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3a10000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3b10000 } + }, +/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb3b10000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5810000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5a10000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5b10000 } + }, +/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb5b10000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3c10000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3e10000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3f10000 } + }, +/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb3f10000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5c10000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5e10000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5f10000 } + }, +/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb5f10000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7c10000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7e10000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7f10000 } + }, +/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xb7f10000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7810000 } + }, +/* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7a10000 } + }, +/* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7b10000 } + }, +/* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xb7b10000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9010000 } + }, +/* cmp.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9210000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1810000 } + }, +/* cmp.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1a10000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1010000 } + }, +/* cmp.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1210000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3010000 } + }, +/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3210000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5010000 } + }, +/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5210000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7010000 } + }, +/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7210000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3810000 } + }, +/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3a10000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5810000 } + }, +/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5a10000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3c10000 } + }, +/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3e10000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5c10000 } + }, +/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5e10000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7c10000 } + }, +/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7e10000 } + }, +/* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7810000 } + }, +/* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7a10000 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xc901 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8921 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8901 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xc181 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x81a1 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x8181 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xc101 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8121 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8101 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc30100 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x832100 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x830100 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc5010000 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85210000 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85010000 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc7010000 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87210000 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87010000 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc38100 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x83a100 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x838100 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc5810000 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85a10000 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85810000 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc3c100 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83e100 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83c100 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc5c10000 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85e10000 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85c10000 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0xc7c10000 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87e10000 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87c10000 } + }, +/* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0xc7810000 } + }, +/* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87a10000 } + }, +/* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87810000 } + }, +/* cmp.b${S} ${SrcDst16-r0l-r0h-S-normal} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } }, + & ifmt_mov16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x38 } + }, +/* cmp.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_mov16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x3900 } + }, +/* cmp.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_mov16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x3a00 } + }, +/* cmp.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } }, + & ifmt_mov16_b_S_src2_src16_2_S_16_absolute_QI, { 0x3b0000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990600 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992600 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993600 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918600 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a600 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b600 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910600 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912600 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913600 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93060000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93260000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93360000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95060000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95260000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95360000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97060000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97260000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97360000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93860000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a60000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b60000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95860000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a60000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b60000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c60000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e60000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f60000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c60000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e60000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f60000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c60000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e60000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f60000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97860000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a60000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9060000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9260000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9360000 } + }, +/* cmp.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9360000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1860000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a60000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b60000 } + }, +/* cmp.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1060000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1260000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1360000 } + }, +/* cmp.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1360000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3060000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3260000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3360000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3360000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5060000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5260000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5360000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5360000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7060000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7260000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7360000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7360000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3860000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a60000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b60000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5860000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a60000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b60000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e60000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f60000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e60000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f60000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e60000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f60000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7860000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a60000 } + }, +/* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b60000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b60000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9060000 } + }, +/* cmp.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9260000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1860000 } + }, +/* cmp.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a60000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1060000 } + }, +/* cmp.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1260000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3060000 } + }, +/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3260000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5060000 } + }, +/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5260000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7060000 } + }, +/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7260000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3860000 } + }, +/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a60000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5860000 } + }, +/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a60000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c60000 } + }, +/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e60000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c60000 } + }, +/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e60000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c60000 } + }, +/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e60000 } + }, +/* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7860000 } + }, +/* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a60000 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc906 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8926 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8906 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc186 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a6 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8186 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc106 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8126 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8106 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30600 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832600 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830600 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5060000 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85260000 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85060000 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7060000 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87260000 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87060000 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38600 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a600 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838600 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5860000 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a60000 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85860000 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c600 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e600 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c600 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c60000 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e60000 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c60000 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c60000 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e60000 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c60000 } + }, +/* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7860000 } + }, +/* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a60000 } + }, +/* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87860000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980600 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982600 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983600 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908600 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a600 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b600 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900600 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902600 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903600 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92060000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92260000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92360000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94060000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94260000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94360000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96060000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96260000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96360000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92860000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a60000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b60000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94860000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a60000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b60000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c60000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e60000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f60000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c60000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e60000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f60000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c60000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e60000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f60000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96860000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a60000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8060000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8260000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8360000 } + }, +/* cmp.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8360000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0860000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a60000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b60000 } + }, +/* cmp.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0060000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0260000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0360000 } + }, +/* cmp.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0360000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2060000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2260000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2360000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2360000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4060000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4260000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4360000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4360000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6060000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6260000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6360000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6360000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2860000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a60000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b60000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4860000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a60000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b60000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e60000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f60000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e60000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f60000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e60000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f60000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6860000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a60000 } + }, +/* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b60000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b60000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8060000 } + }, +/* cmp.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8260000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0860000 } + }, +/* cmp.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a60000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0060000 } + }, +/* cmp.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0260000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2060000 } + }, +/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2260000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4060000 } + }, +/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4260000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6060000 } + }, +/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6260000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2860000 } + }, +/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a60000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4860000 } + }, +/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a60000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c60000 } + }, +/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e60000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c60000 } + }, +/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e60000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c60000 } + }, +/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e60000 } + }, +/* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6860000 } + }, +/* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a60000 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc806 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8826 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8806 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc086 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a6 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8086 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc006 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8026 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8006 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20600 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822600 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820600 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4060000 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84260000 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84060000 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6060000 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86260000 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86060000 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28600 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a600 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828600 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4860000 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a60000 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84860000 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c600 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e600 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c600 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c60000 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e60000 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c60000 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c60000 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e60000 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c60000 } + }, +/* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6860000 } + }, +/* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a60000 } + }, +/* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86860000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xc18000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xc1a000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xc1b000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xc18400 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xc1a400 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xc1b400 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xc18600 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xc1a600 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xc1b600 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xc1880000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xc1a80000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xc1b80000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xc18c0000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xc1ac0000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xc1bc0000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xc18a0000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xc1aa0000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xc1ba0000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xc18e0000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xc1ae0000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xc1be0000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xc18b0000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xc1ab0000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xc1bb0000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xc18f0000 } + }, +/* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xc1af0000 } + }, +/* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xc1bf0000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xc1c00000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xc1e00000 } + }, +/* cmp.w${G} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xc1f00000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xc1c40000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xc1e40000 } + }, +/* cmp.w${G} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xc1f40000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xc1c60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xc1e60000 } + }, +/* cmp.w${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xc1f60000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xc1c80000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xc1e80000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xc1f80000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xc1cc0000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xc1ec0000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xc1fc0000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xc1ca0000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xc1ea0000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xc1fa0000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xc1ce0000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xc1ee0000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xc1fe0000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xc1cb0000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xc1eb0000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xc1fb0000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xc1cf0000 } + }, +/* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xc1ef0000 } + }, +/* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xc1ff0000 } + }, +/* cmp.w${G} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xc100 } + }, +/* cmp.w${G} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xc140 } + }, +/* cmp.w${G} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xc160 } + }, +/* cmp.w${G} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xc104 } + }, +/* cmp.w${G} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xc144 } + }, +/* cmp.w${G} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xc164 } + }, +/* cmp.w${G} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xc106 } + }, +/* cmp.w${G} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xc146 } + }, +/* cmp.w${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xc166 } + }, +/* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xc10800 } + }, +/* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xc14800 } + }, +/* cmp.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xc16800 } + }, +/* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xc10c0000 } + }, +/* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xc14c0000 } + }, +/* cmp.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xc16c0000 } + }, +/* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xc10a00 } + }, +/* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xc14a00 } + }, +/* cmp.w${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xc16a00 } + }, +/* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xc10e0000 } + }, +/* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xc14e0000 } + }, +/* cmp.w${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xc16e0000 } + }, +/* cmp.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xc10b00 } + }, +/* cmp.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xc14b00 } + }, +/* cmp.w${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xc16b00 } + }, +/* cmp.w${G} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xc10f0000 } + }, +/* cmp.w${G} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xc14f0000 } + }, +/* cmp.w${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xc16f0000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xc08000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xc0a000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xc0b000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xc08400 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xc0a400 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xc0b400 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xc08600 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xc0a600 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xc0b600 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xc0880000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xc0a80000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xc0b80000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xc08c0000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xc0ac0000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xc0bc0000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xc08a0000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xc0aa0000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xc0ba0000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xc08e0000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xc0ae0000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xc0be0000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xc08b0000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xc0ab0000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xc0bb0000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xc08f0000 } + }, +/* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xc0af0000 } + }, +/* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xc0bf0000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xc0c00000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xc0e00000 } + }, +/* cmp.b${G} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xc0f00000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xc0c40000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xc0e40000 } + }, +/* cmp.b${G} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xc0f40000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xc0c60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xc0e60000 } + }, +/* cmp.b${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xc0f60000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xc0c80000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xc0e80000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xc0f80000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xc0cc0000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xc0ec0000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xc0fc0000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xc0ca0000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xc0ea0000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xc0fa0000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xc0ce0000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xc0ee0000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xc0fe0000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xc0cb0000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xc0eb0000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xc0fb0000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xc0cf0000 } + }, +/* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xc0ef0000 } + }, +/* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xc0ff0000 } + }, +/* cmp.b${G} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xc000 } + }, +/* cmp.b${G} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xc040 } + }, +/* cmp.b${G} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xc060 } + }, +/* cmp.b${G} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xc004 } + }, +/* cmp.b${G} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xc044 } + }, +/* cmp.b${G} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xc064 } + }, +/* cmp.b${G} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xc006 } + }, +/* cmp.b${G} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xc046 } + }, +/* cmp.b${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xc066 } + }, +/* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xc00800 } + }, +/* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xc04800 } + }, +/* cmp.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xc06800 } + }, +/* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xc00c0000 } + }, +/* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xc04c0000 } + }, +/* cmp.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xc06c0000 } + }, +/* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xc00a00 } + }, +/* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xc04a00 } + }, +/* cmp.b${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xc06a00 } + }, +/* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xc00e0000 } + }, +/* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xc04e0000 } + }, +/* cmp.b${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xc06e0000 } + }, +/* cmp.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xc00b00 } + }, +/* cmp.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xc04b00 } + }, +/* cmp.b${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xc06b00 } + }, +/* cmp.b${G} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xc00f0000 } + }, +/* cmp.b${G} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xc04f0000 } + }, +/* cmp.b${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xc06f0000 } + }, +/* cmp.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xe400 } + }, +/* cmp.b${S} #${Imm-8-QI},r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xe300 } + }, +/* cmp.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xe50000 } + }, +/* cmp.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xe60000 } + }, +/* cmp.b${S} #${Imm-8-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xe7000000 } + }, +/* cmp.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xe910 } + }, +/* cmp.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xe190 } + }, +/* cmp.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xe110 } + }, +/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xe31000 } + }, +/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xe5100000 } + }, +/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xe7100000 } + }, +/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xe39000 } + }, +/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xe5900000 } + }, +/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xe3d000 } + }, +/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xe5d00000 } + }, +/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xe7d00000 } + }, +/* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xe7900000 } + }, +/* cmp.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xe810 } + }, +/* cmp.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xe090 } + }, +/* cmp.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xe010 } + }, +/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xe21000 } + }, +/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xe4100000 } + }, +/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xe6100000 } + }, +/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xe29000 } + }, +/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xe4900000 } + }, +/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xe2d000 } + }, +/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xe4d00000 } + }, +/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xe6d00000 } + }, +/* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xe6900000 } + }, +/* cmp.w${Q} #${Imm-8-s4},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), 0 } }, + & ifmt_cmp16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xd100 } + }, +/* cmp.w${Q} #${Imm-8-s4},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), 0 } }, + & ifmt_cmp16_w_imm4_Q_16_dst16_An_direct_HI, { 0xd104 } + }, +/* cmp.w${Q} #${Imm-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_cmp16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xd106 } + }, +/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_cmp16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xd10800 } + }, +/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_cmp16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xd10c0000 } + }, +/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_cmp16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xd10a00 } + }, +/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_cmp16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xd10e0000 } + }, +/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_cmp16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xd10b00 } + }, +/* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_cmp16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xd10f0000 } + }, +/* cmp.b${Q} #${Imm-8-s4},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_QI, { 0xd000 } + }, +/* cmp.b${Q} #${Imm-8-s4},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_An_direct_QI, { 0xd004 } + }, +/* cmp.b${Q} #${Imm-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_QI, { 0xd006 } + }, +/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xd00800 } + }, +/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xd00c0000 } + }, +/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xd00a00 } + }, +/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xd00e0000 } + }, +/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xd00b00 } + }, +/* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_QI, { 0xd00f0000 } + }, +/* cmp.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x992e0000 } + }, +/* cmp.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x91ae0000 } + }, +/* cmp.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x912e0000 } + }, +/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x932e0000 } + }, +/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x93ae0000 } + }, +/* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x93ee0000 } + }, +/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x952e0000 } + }, +/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x95ae0000 } + }, +/* cmp.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x95ee0000 } + }, +/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x97ee0000 } + }, +/* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x972e0000 } + }, +/* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x97ae0000 } + }, +/* cmp.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x982e00 } + }, +/* cmp.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x90ae00 } + }, +/* cmp.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x902e00 } + }, +/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x922e0000 } + }, +/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x92ae0000 } + }, +/* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x92ee0000 } + }, +/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x942e0000 } + }, +/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x94ae0000 } + }, +/* cmp.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x94ee0000 } + }, +/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x96ee0000 } + }, +/* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x962e0000 } + }, +/* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x96ae0000 } + }, +/* cmp.w${G} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77800000 } + }, +/* cmp.w${G} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77840000 } + }, +/* cmp.w${G} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77860000 } + }, +/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77880000 } + }, +/* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x778a0000 } + }, +/* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x778b0000 } + }, +/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x778c0000 } + }, +/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x778e0000 } + }, +/* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x778f0000 } + }, +/* cmp.b${G} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x768000 } + }, +/* cmp.b${G} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x768400 } + }, +/* cmp.b${G} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x768600 } + }, +/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76880000 } + }, +/* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x768a0000 } + }, +/* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x768b0000 } + }, +/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x768c0000 } + }, +/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x768e0000 } + }, +/* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x768f0000 } + }, +/* cmp.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xa8310000 } + }, +/* cmp.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xa0b10000 } + }, +/* cmp.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xa0310000 } + }, +/* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xa2310000 } + }, +/* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xa2b10000 } + }, +/* cmp.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xa2f10000 } + }, +/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xa4310000 } + }, +/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xa4b10000 } + }, +/* cmp.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xa4f10000 } + }, +/* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xa6f10000 } + }, +/* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xa6310000 } + }, +/* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xa6b10000 } + }, +/* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1893e00 } + }, +/* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x181be00 } + }, +/* clip.w #${Imm-24-HI},#${Imm-40-HI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_HI), ',', '#', OP (IMM_40_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_clip32_w_Imm_24_HI_Imm_40_HI_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1813e00 } + }, +/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1833e00 } + }, +/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x183be00 } + }, +/* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_HI), ',', '#', OP (IMM_48_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_clip32_w_Imm_32_HI_Imm_48_HI_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183fe00 } + }, +/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1853e00 } + }, +/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x185be00 } + }, +/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185fe00 } + }, +/* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_HI), ',', '#', OP (IMM_56_HI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_clip32_w_Imm_40_HI_Imm_56_HI_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187fe00 } + }, +/* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_48_HI), ',', '#', OP (IMM_64_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_clip32_w_Imm_48_HI_Imm_64_HI_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1873e00 } + }, +/* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_48_HI), ',', '#', OP (IMM_64_HI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_clip32_w_Imm_48_HI_Imm_64_HI_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x187be00 } + }, +/* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1883e00 } + }, +/* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x180be00 } + }, +/* clip.b #${Imm-24-QI},#${Imm-32-QI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_24_QI), ',', '#', OP (IMM_32_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_clip32_b_Imm_24_QI_Imm_32_QI_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1803e00 } + }, +/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1823e00 } + }, +/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x182be00 } + }, +/* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_32_QI), ',', '#', OP (IMM_40_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_clip32_b_Imm_32_QI_Imm_40_QI_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182fe00 } + }, +/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1843e00 } + }, +/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x184be00 } + }, +/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184fe00 } + }, +/* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_40_QI), ',', '#', OP (IMM_48_QI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_clip32_b_Imm_40_QI_Imm_48_QI_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186fe00 } + }, +/* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_48_QI), ',', '#', OP (IMM_56_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_clip32_b_Imm_48_QI_Imm_56_QI_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1863e00 } + }, +/* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_48_QI), ',', '#', OP (IMM_56_QI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_clip32_b_Imm_48_QI_Imm_56_QI_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186be00 } + }, +/* bxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d828 } + }, +/* bxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d0a8 } + }, +/* bxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d028 } + }, +/* bxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d22800 } + }, +/* bxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d42800 } + }, +/* bxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d62800 } + }, +/* bxor${X} ${BitBase32-24-u11-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d2a800 } + }, +/* bxor${X} ${BitBase32-24-u19-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d4a800 } + }, +/* bxor${X} ${BitBase32-24-s11-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2e800 } + }, +/* bxor${X} ${BitBase32-24-s19-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4e800 } + }, +/* bxor${X} ${BitBase32-24-u19-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6e800 } + }, +/* bxor${X} ${BitBase32-24-u27-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d6a800 } + }, +/* bxor${X} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7ec000 } + }, +/* bxor${X} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7ec400 } + }, +/* bxor${X} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7ec6 } + }, +/* bxor${X} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7ec800 } + }, +/* bxor${X} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7ecc0000 } + }, +/* bxor${X} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7eca00 } + }, +/* bxor${X} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7ece0000 } + }, +/* bxor${X} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7ecb00 } + }, +/* bxor${X} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7ecf0000 } + }, +/* btsts${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd828 } + }, +/* btsts${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd0a8 } + }, +/* btsts${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd028 } + }, +/* btsts${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd22800 } + }, +/* btsts${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4280000 } + }, +/* btsts${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6280000 } + }, +/* btsts${X} ${BitBase32-16-u11-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd2a800 } + }, +/* btsts${X} ${BitBase32-16-u19-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4a80000 } + }, +/* btsts${X} ${BitBase32-16-s11-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2e800 } + }, +/* btsts${X} ${BitBase32-16-s19-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4e80000 } + }, +/* btsts${X} ${BitBase32-16-u19-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6e80000 } + }, +/* btsts${X} ${BitBase32-16-u27-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6a80000 } + }, +/* btsts${X} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e1000 } + }, +/* btsts${X} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e1400 } + }, +/* btsts${X} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e16 } + }, +/* btsts${X} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e1800 } + }, +/* btsts${X} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e1c0000 } + }, +/* btsts${X} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e1a00 } + }, +/* btsts${X} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e1e0000 } + }, +/* btsts${X} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e1b00 } + }, +/* btsts${X} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e1f0000 } + }, +/* btstc${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd820 } + }, +/* btstc${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd0a0 } + }, +/* btstc${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd020 } + }, +/* btstc${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd22000 } + }, +/* btstc${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4200000 } + }, +/* btstc${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6200000 } + }, +/* btstc${X} ${BitBase32-16-u11-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd2a000 } + }, +/* btstc${X} ${BitBase32-16-u19-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4a00000 } + }, +/* btstc${X} ${BitBase32-16-s11-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2e000 } + }, +/* btstc${X} ${BitBase32-16-s19-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4e00000 } + }, +/* btstc${X} ${BitBase32-16-u19-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6e00000 } + }, +/* btstc${X} ${BitBase32-16-u27-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6a00000 } + }, +/* btstc${X} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e0000 } + }, +/* btstc${X} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e0400 } + }, +/* btstc${X} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e06 } + }, +/* btstc${X} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e0800 } + }, +/* btstc${X} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e0c0000 } + }, +/* btstc${X} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e0a00 } + }, +/* btstc${X} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e0e0000 } + }, +/* btstc${X} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e0b00 } + }, +/* btstc${X} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e0f0000 } + }, +/* btst${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd800 } + }, +/* btst${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd080 } + }, +/* btst${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd000 } + }, +/* btst${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd20000 } + }, +/* btst${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4000000 } + }, +/* btst${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6000000 } + }, +/* btst${X} ${BitBase32-16-u11-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd28000 } + }, +/* btst${X} ${BitBase32-16-u19-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4800000 } + }, +/* btst${X} ${BitBase32-16-s11-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2c000 } + }, +/* btst${X} ${BitBase32-16-s19-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4c00000 } + }, +/* btst${X} ${BitBase32-16-u19-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6c00000 } + }, +/* btst${X} ${BitBase32-16-u27-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6800000 } + }, +/* btst${G} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7eb000 } + }, +/* btst${G} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7eb400 } + }, +/* btst${G} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7eb800 } + }, +/* btst${G} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7eba00 } + }, +/* btst${G} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7ebb00 } + }, +/* btst${S} ${BitBase16-8-u11-S}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (BITBASE16_8_U11_S), '[', 's', 'b', ']', 0 } }, + & ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S, { 0x5800 } + }, +/* btst${G} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7ebc0000 } + }, +/* btst${G} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7ebe0000 } + }, +/* btst${G} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7ebf0000 } + }, +/* btst${G} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7eb6 } + }, +/* bset${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd838 } + }, +/* bset${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd0b8 } + }, +/* bset${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd038 } + }, +/* bset${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd23800 } + }, +/* bset${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4380000 } + }, +/* bset${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6380000 } + }, +/* bset${X} ${BitBase32-16-u11-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd2b800 } + }, +/* bset${X} ${BitBase32-16-u19-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4b80000 } + }, +/* bset${X} ${BitBase32-16-s11-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2f800 } + }, +/* bset${X} ${BitBase32-16-s19-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4f80000 } + }, +/* bset${X} ${BitBase32-16-u19-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6f80000 } + }, +/* bset${X} ${BitBase32-16-u27-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6b80000 } + }, +/* bset${G} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e9000 } + }, +/* bset${G} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e9400 } + }, +/* bset${G} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e9800 } + }, +/* bset${G} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e9a00 } + }, +/* bset${G} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e9b00 } + }, +/* bset${S} ${BitBase16-8-u11-S}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (BITBASE16_8_U11_S), '[', 's', 'b', ']', 0 } }, + & ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S, { 0x4800 } + }, +/* bset${G} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e9c0000 } + }, +/* bset${G} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e9e0000 } + }, +/* bset${G} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e9f0000 } + }, +/* bset${G} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e96 } + }, +/* bor${X} $Bitno32Prefixed,$Bit32RnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d820 } + }, +/* bor${X} $Bitno32Prefixed,$Bit32AnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d0a0 } + }, +/* bor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d020 } + }, +/* bor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d22000 } + }, +/* bor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d42000 } + }, +/* bor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d62000 } + }, +/* bor${X} ${BitBase32-24-u11-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d2a000 } + }, +/* bor${X} ${BitBase32-24-u19-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d4a000 } + }, +/* bor${X} ${BitBase32-24-s11-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2e000 } + }, +/* bor${X} ${BitBase32-24-s19-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4e000 } + }, +/* bor${X} ${BitBase32-24-u19-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6e000 } + }, +/* bor${X} ${BitBase32-24-u27-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d6a000 } + }, +/* bor${X} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e6000 } + }, +/* bor${X} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e6400 } + }, +/* bor${X} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e66 } + }, +/* bor${X} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e6800 } + }, +/* bor${X} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e6c0000 } + }, +/* bor${X} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e6a00 } + }, +/* bor${X} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e6e0000 } + }, +/* bor${X} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e6b00 } + }, +/* bor${X} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e6f0000 } + }, +/* bnxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d838 } + }, +/* bnxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d0b8 } + }, +/* bnxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d038 } + }, +/* bnxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d23800 } + }, +/* bnxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d43800 } + }, +/* bnxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d63800 } + }, +/* bnxor${X} ${BitBase32-24-u11-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d2b800 } + }, +/* bnxor${X} ${BitBase32-24-u19-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d4b800 } + }, +/* bnxor${X} ${BitBase32-24-s11-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2f800 } + }, +/* bnxor${X} ${BitBase32-24-s19-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4f800 } + }, +/* bnxor${X} ${BitBase32-24-u19-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6f800 } + }, +/* bnxor${X} ${BitBase32-24-u27-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d6b800 } + }, +/* bnxor${X} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7ed000 } + }, +/* bnxor${X} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7ed400 } + }, +/* bnxor${X} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7ed6 } + }, +/* bnxor${X} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7ed800 } + }, +/* bnxor${X} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7edc0000 } + }, +/* bnxor${X} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7eda00 } + }, +/* bnxor${X} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7ede0000 } + }, +/* bnxor${X} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7edb00 } + }, +/* bnxor${X} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7edf0000 } + }, +/* bntst${X} $Bitno32Prefixed,$Bit32RnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d800 } + }, +/* bntst${X} $Bitno32Prefixed,$Bit32AnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d080 } + }, +/* bntst${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d000 } + }, +/* bntst${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d20000 } + }, +/* bntst${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d40000 } + }, +/* bntst${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d60000 } + }, +/* bntst${X} ${BitBase32-24-u11-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d28000 } + }, +/* bntst${X} ${BitBase32-24-u19-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d48000 } + }, +/* bntst${X} ${BitBase32-24-s11-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2c000 } + }, +/* bntst${X} ${BitBase32-24-s19-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4c000 } + }, +/* bntst${X} ${BitBase32-24-u19-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6c000 } + }, +/* bntst${X} ${BitBase32-24-u27-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d68000 } + }, +/* bntst${X} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e3000 } + }, +/* bntst${X} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e3400 } + }, +/* bntst${X} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e36 } + }, +/* bntst${X} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e3800 } + }, +/* bntst${X} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e3c0000 } + }, +/* bntst${X} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e3a00 } + }, +/* bntst${X} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e3e0000 } + }, +/* bntst${X} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e3b00 } + }, +/* bntst${X} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e3f0000 } + }, +/* bnot${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd818 } + }, +/* bnot${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd098 } + }, +/* bnot${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd018 } + }, +/* bnot${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd21800 } + }, +/* bnot${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4180000 } + }, +/* bnot${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6180000 } + }, +/* bnot${X} ${BitBase32-16-u11-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd29800 } + }, +/* bnot${X} ${BitBase32-16-u19-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4980000 } + }, +/* bnot${X} ${BitBase32-16-s11-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2d800 } + }, +/* bnot${X} ${BitBase32-16-s19-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4d80000 } + }, +/* bnot${X} ${BitBase32-16-u19-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6d80000 } + }, +/* bnot${X} ${BitBase32-16-u27-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6980000 } + }, +/* bnot${G} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7ea000 } + }, +/* bnot${G} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7ea400 } + }, +/* bnot${G} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7ea800 } + }, +/* bnot${G} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7eaa00 } + }, +/* bnot${G} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7eab00 } + }, +/* bnot${S} ${BitBase16-8-u11-S}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (BITBASE16_8_U11_S), '[', 's', 'b', ']', 0 } }, + & ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S, { 0x5000 } + }, +/* bnot${G} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7eac0000 } + }, +/* bnot${G} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7eae0000 } + }, +/* bnot${G} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7eaf0000 } + }, +/* bnot${G} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7ea6 } + }, +/* bnor${X} $Bitno32Prefixed,$Bit32RnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d830 } + }, +/* bnor${X} $Bitno32Prefixed,$Bit32AnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d0b0 } + }, +/* bnor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d030 } + }, +/* bnor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d23000 } + }, +/* bnor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d43000 } + }, +/* bnor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d63000 } + }, +/* bnor${X} ${BitBase32-24-u11-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d2b000 } + }, +/* bnor${X} ${BitBase32-24-u19-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d4b000 } + }, +/* bnor${X} ${BitBase32-24-s11-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2f000 } + }, +/* bnor${X} ${BitBase32-24-s19-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4f000 } + }, +/* bnor${X} ${BitBase32-24-u19-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6f000 } + }, +/* bnor${X} ${BitBase32-24-u27-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d6b000 } + }, +/* bnor${X} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e7000 } + }, +/* bnor${X} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e7400 } + }, +/* bnor${X} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e76 } + }, +/* bnor${X} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e7800 } + }, +/* bnor${X} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e7c0000 } + }, +/* bnor${X} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e7a00 } + }, +/* bnor${X} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e7e0000 } + }, +/* bnor${X} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e7b00 } + }, +/* bnor${X} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e7f0000 } + }, +/* bnand${X} $Bitno32Prefixed,$Bit32RnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d818 } + }, +/* bnand${X} $Bitno32Prefixed,$Bit32AnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d098 } + }, +/* bnand${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d018 } + }, +/* bnand${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d21800 } + }, +/* bnand${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d41800 } + }, +/* bnand${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d61800 } + }, +/* bnand${X} ${BitBase32-24-u11-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d29800 } + }, +/* bnand${X} ${BitBase32-24-u19-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d49800 } + }, +/* bnand${X} ${BitBase32-24-s11-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2d800 } + }, +/* bnand${X} ${BitBase32-24-s19-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4d800 } + }, +/* bnand${X} ${BitBase32-24-u19-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6d800 } + }, +/* bnand${X} ${BitBase32-24-u27-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d69800 } + }, +/* bnand${X} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e5000 } + }, +/* bnand${X} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e5400 } + }, +/* bnand${X} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e56 } + }, +/* bnand${X} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e5800 } + }, +/* bnand${X} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e5c0000 } + }, +/* bnand${X} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e5a00 } + }, +/* bnand${X} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e5e0000 } + }, +/* bnand${X} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e5b00 } + }, +/* bnand${X} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e5f0000 } + }, +/* bm${cond32-16} $Bitno32Unprefixed,$Bit32RnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_16), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } }, + & ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_Rn_direct_Unprefixed, { 0xd81000 } + }, +/* bm${cond32-16} $Bitno32Unprefixed,$Bit32AnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_16), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } }, + & ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_An_direct_Unprefixed, { 0xd09000 } + }, +/* bm${cond32-16} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_16), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_bm32_bit32_basic_Unprefixed_cond32_16_bit32_An_indirect_Unprefixed, { 0xd01000 } + }, +/* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_24), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_An_relative_Unprefixed, { 0xd2100000 } + }, +/* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_24), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_SB_relative_Unprefixed, { 0xd2900000 } + }, +/* bm${cond32-24} ${BitBase32-16-s11-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_24), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bm32_bit32_16_8_Unprefixed_cond32_24_bit32_16_11_FB_relative_Unprefixed, { 0xd2d00000 } + }, +/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_32), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_An_relative_Unprefixed, { 0xd4100000 } + }, +/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_32), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_SB_relative_Unprefixed, { 0xd4900000 } + }, +/* bm${cond32-32} ${BitBase32-16-s19-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_32), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_FB_relative_Unprefixed, { 0xd4d00000 } + }, +/* bm${cond32-32} ${BitBase32-16-u19-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_32), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } }, + & ifmt_bm32_bit32_16_16_Unprefixed_cond32_32_bit32_16_19_absolute_Unprefixed, { 0xd6d00000 } + }, +/* bm${cond32-40} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_40), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_bm32_bit32_16_24_Unprefixed_cond32_40_bit32_16_27_An_relative_Unprefixed, { 0xd6100000 } + }, +/* bm${cond32-40} ${BitBase32-16-u27-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32_40), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } }, + & ifmt_bm32_bit32_16_24_Unprefixed_cond32_40_bit32_16_27_absolute_Unprefixed, { 0xd6900000 } + }, +/* bm${cond16-24} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16_24), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bm16_bit16_16_8_cond16_24_bit16_Rn_direct, { 0x7e200000 } + }, +/* bm${cond16-24} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16_24), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bm16_bit16_16_8_cond16_24_bit16_An_direct, { 0x7e240000 } + }, +/* bm${cond16-24} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16_24), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_An_relative, { 0x7e280000 } + }, +/* bm${cond16-24} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16_24), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_SB_relative, { 0x7e2a0000 } + }, +/* bm${cond16-24} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16_24), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bm16_bit16_16_8_cond16_24_bit16_16_8_FB_relative, { 0x7e2b0000 } + }, +/* bm${cond16-32} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16_32), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_An_relative, { 0x7e2c0000 } + }, +/* bm${cond16-32} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16_32), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_SB_relative, { 0x7e2e0000 } + }, +/* bm${cond16-32} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16_32), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bm16_bit16_16_16_cond16_32_bit16_16_16_absolute, { 0x7e2f0000 } + }, +/* bm${cond16-16} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16_16), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bm16_bit16_16_basic_cond16_16_bit16_An_indirect, { 0x7e2600 } + }, +/* bitindex.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xc92e } + }, +/* bitindex.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xc1ae } + }, +/* bitindex.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xc12e } + }, +/* bitindex.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xc32e00 } + }, +/* bitindex.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xc52e0000 } + }, +/* bitindex.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xc72e0000 } + }, +/* bitindex.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc3ae00 } + }, +/* bitindex.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5ae0000 } + }, +/* bitindex.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3ee00 } + }, +/* bitindex.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5ee0000 } + }, +/* bitindex.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xc7ee0000 } + }, +/* bitindex.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xc7ae0000 } + }, +/* bitindex.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xc82e } + }, +/* bitindex.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xc0ae } + }, +/* bitindex.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xc02e } + }, +/* bitindex.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xc22e00 } + }, +/* bitindex.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xc42e0000 } + }, +/* bitindex.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xc62e0000 } + }, +/* bitindex.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc2ae00 } + }, +/* bitindex.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4ae0000 } + }, +/* bitindex.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2ee00 } + }, +/* bitindex.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4ee0000 } + }, +/* bitindex.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xc6ee0000 } + }, +/* bitindex.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xc6ae0000 } + }, +/* bclr${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32RNUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_Rn_direct_Unprefixed, { 0xd830 } + }, +/* bclr${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', OP (BIT32ANUNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_direct_Unprefixed, { 0xd0b0 } + }, +/* bclr${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32UNPREFIXED), ',', '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_An_indirect_Unprefixed, { 0xd030 } + }, +/* bclr${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_An_relative_Unprefixed, { 0xd23000 } + }, +/* bclr${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_An_relative_Unprefixed, { 0xd4300000 } + }, +/* bclr${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), '[', OP (BIT32ANUNPREFIXED), ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_An_relative_Unprefixed, { 0xd6300000 } + }, +/* bclr${X} ${BitBase32-16-u11-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U11_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_SB_relative_Unprefixed, { 0xd2b000 } + }, +/* bclr${X} ${BitBase32-16-u19-Unprefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_SB_relative_Unprefixed, { 0xd4b00000 } + }, +/* bclr${X} ${BitBase32-16-s11-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S11_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_11_FB_relative_Unprefixed, { 0xd2f000 } + }, +/* bclr${X} ${BitBase32-16-s19-Unprefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_S19_UNPREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_FB_relative_Unprefixed, { 0xd4f00000 } + }, +/* bclr${X} ${BitBase32-16-u19-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U19_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_19_absolute_Unprefixed, { 0xd6f00000 } + }, +/* bclr${X} ${BitBase32-16-u27-Unprefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_16_U27_UNPREFIXED), 0 } }, + & ifmt_btsts32_X_bit32_16_Unprefixed_bit32_16_27_absolute_Unprefixed, { 0xd6b00000 } + }, +/* bclr${G} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e8000 } + }, +/* bclr${G} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e8400 } + }, +/* bclr${G} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e8800 } + }, +/* bclr${G} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e8a00 } + }, +/* bclr${G} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e8b00 } + }, +/* bclr${S} ${BitBase16-8-u11-S}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (BITBASE16_8_U11_S), '[', 's', 'b', ']', 0 } }, + & ifmt_btst16_S_bit16_11_S_bit16_11_SB_relative_S, { 0x4000 } + }, +/* bclr${G} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e8c0000 } + }, +/* bclr${G} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e8e0000 } + }, +/* bclr${G} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e8f0000 } + }, +/* bclr${G} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e86 } + }, +/* band${X} $Bitno32Prefixed,$Bit32RnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32RNPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_Rn_direct_Prefixed, { 0x1d808 } + }, +/* band${X} $Bitno32Prefixed,$Bit32AnPrefixed */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', OP (BIT32ANPREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_direct_Prefixed, { 0x1d088 } + }, +/* band${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO32PREFIXED), ',', '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_An_indirect_Prefixed, { 0x1d008 } + }, +/* band${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_An_relative_Prefixed, { 0x1d20800 } + }, +/* band${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_An_relative_Prefixed, { 0x1d40800 } + }, +/* band${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), '[', OP (BIT32ANPREFIXED), ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_An_relative_Prefixed, { 0x1d60800 } + }, +/* band${X} ${BitBase32-24-u11-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U11_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_SB_relative_Prefixed, { 0x1d28800 } + }, +/* band${X} ${BitBase32-24-u19-Prefixed}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_SB_relative_Prefixed, { 0x1d48800 } + }, +/* band${X} ${BitBase32-24-s11-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S11_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_11_FB_relative_Prefixed, { 0x1d2c800 } + }, +/* band${X} ${BitBase32-24-s19-Prefixed}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_S19_PREFIXED), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_FB_relative_Prefixed, { 0x1d4c800 } + }, +/* band${X} ${BitBase32-24-u19-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U19_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_19_absolute_Prefixed, { 0x1d6c800 } + }, +/* band${X} ${BitBase32-24-u27-Prefixed} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE32_24_U27_PREFIXED), 0 } }, + & ifmt_bxor32_X_bit32_24_Prefixed_bit32_24_27_absolute_Prefixed, { 0x1d68800 } + }, +/* band${X} $Bitno16R,$Bit16Rn */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16RN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_Rn_direct, { 0x7e4000 } + }, +/* band${X} $Bitno16R,$Bit16An */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITNO16R), ',', OP (BIT16AN), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_direct, { 0x7e4400 } + }, +/* band${X} [$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_An_indirect, { 0x7e46 } + }, +/* band${X} ${Dsp-16-u8}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_An_relative, { 0x7e4800 } + }, +/* band${X} ${Dsp-16-u16}[$Bit16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (BIT16AN), ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_An_relative, { 0x7e4c0000 } + }, +/* band${X} ${BitBase16-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_SB_relative, { 0x7e4a00 } + }, +/* band${X} ${BitBase16-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_SB_relative, { 0x7e4e0000 } + }, +/* band${X} ${BitBase16-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_8_FB_relative, { 0x7e4b00 } + }, +/* band${X} ${BitBase16-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (BITBASE16_16_U16), 0 } }, + & ifmt_bxor16_X_bit16_16_bit16_16_16_absolute, { 0x7e4f0000 } + }, +/* and.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x6d000000 } + }, +/* and.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x7d000000 } + }, +/* and.w${S} #${Imm-24-HI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x5d000000 } + }, +/* and.w${S} #${Imm-8-HI},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } }, + & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x4d0000 } + }, +/* and.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x6c0000 } + }, +/* and.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x7c0000 } + }, +/* and.b${S} #${Imm-24-QI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x5c000000 } + }, +/* and.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x4c00 } + }, +/* and.b${S} ${SrcDst16-r0l-r0h-S-normal} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } }, + & ifmt_mov16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x10 } + }, +/* and.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_mov16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x1100 } + }, +/* and.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_mov16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x1200 } + }, +/* and.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } }, + & ifmt_mov16_b_S_src2_src16_2_S_16_absolute_QI, { 0x130000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990d00 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992d00 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993d00 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918d00 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91ad00 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91bd00 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910d00 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912d00 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913d00 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x930d0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x932d0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x933d0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x950d0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x952d0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x953d0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x970d0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x972d0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x973d0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x938d0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93ad0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93bd0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x958d0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95ad0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95bd0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93cd0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93ed0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93fd0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95cd0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95ed0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95fd0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97cd0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97ed0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97fd0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x978d0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97ad0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97bd0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa90d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa92d0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa93d0000 } + }, +/* and.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb93d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa18d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1ad0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1bd0000 } + }, +/* and.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1bd0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa10d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa12d0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa13d0000 } + }, +/* and.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb13d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa30d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa32d0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa33d0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb33d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa50d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa52d0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa53d0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb53d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa70d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa72d0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa73d0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb73d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa38d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3ad0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3bd0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3bd0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa58d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5ad0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5bd0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5bd0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3cd0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3ed0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3fd0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3fd0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5cd0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5ed0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5fd0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5fd0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7cd0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7ed0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7fd0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7fd0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa78d0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7ad0000 } + }, +/* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7bd0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7bd0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb90d0000 } + }, +/* and.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb92d0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb18d0000 } + }, +/* and.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1ad0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb10d0000 } + }, +/* and.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb12d0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb30d0000 } + }, +/* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb32d0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb50d0000 } + }, +/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb52d0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb70d0000 } + }, +/* and.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb72d0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb38d0000 } + }, +/* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3ad0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb58d0000 } + }, +/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5ad0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3cd0000 } + }, +/* and.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3ed0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5cd0000 } + }, +/* and.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5ed0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7cd0000 } + }, +/* and.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7ed0000 } + }, +/* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb78d0000 } + }, +/* and.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7ad0000 } + }, +/* and.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc90d } + }, +/* and.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x892d } + }, +/* and.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x890d } + }, +/* and.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc18d } + }, +/* and.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81ad } + }, +/* and.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x818d } + }, +/* and.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc10d } + }, +/* and.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x812d } + }, +/* and.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x810d } + }, +/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30d00 } + }, +/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832d00 } + }, +/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830d00 } + }, +/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc50d0000 } + }, +/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x852d0000 } + }, +/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x850d0000 } + }, +/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc70d0000 } + }, +/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x872d0000 } + }, +/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x870d0000 } + }, +/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38d00 } + }, +/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83ad00 } + }, +/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838d00 } + }, +/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc58d0000 } + }, +/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85ad0000 } + }, +/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x858d0000 } + }, +/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3cd00 } + }, +/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ed00 } + }, +/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83cd00 } + }, +/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5cd0000 } + }, +/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ed0000 } + }, +/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85cd0000 } + }, +/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7cd0000 } + }, +/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87ed0000 } + }, +/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87cd0000 } + }, +/* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc78d0000 } + }, +/* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87ad0000 } + }, +/* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x878d0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980d00 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982d00 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983d00 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908d00 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90ad00 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90bd00 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900d00 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902d00 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903d00 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x920d0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x922d0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x923d0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x940d0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x942d0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x943d0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x960d0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x962d0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x963d0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x928d0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92ad0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92bd0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x948d0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94ad0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94bd0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92cd0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92ed0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92fd0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94cd0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94ed0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94fd0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96cd0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96ed0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96fd0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x968d0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96ad0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96bd0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa80d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa82d0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa83d0000 } + }, +/* and.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb83d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa08d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0ad0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0bd0000 } + }, +/* and.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0bd0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa00d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa02d0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa03d0000 } + }, +/* and.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb03d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa20d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa22d0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa23d0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb23d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa40d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa42d0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa43d0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb43d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa60d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa62d0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa63d0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb63d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa28d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2ad0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2bd0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2bd0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa48d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4ad0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4bd0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4bd0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2cd0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2ed0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2fd0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2fd0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4cd0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4ed0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4fd0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4fd0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6cd0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6ed0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6fd0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6fd0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa68d0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6ad0000 } + }, +/* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6bd0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6bd0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb80d0000 } + }, +/* and.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb82d0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb08d0000 } + }, +/* and.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0ad0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb00d0000 } + }, +/* and.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb02d0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb20d0000 } + }, +/* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb22d0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb40d0000 } + }, +/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb42d0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb60d0000 } + }, +/* and.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb62d0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb28d0000 } + }, +/* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2ad0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb48d0000 } + }, +/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4ad0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2cd0000 } + }, +/* and.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2ed0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4cd0000 } + }, +/* and.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4ed0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6cd0000 } + }, +/* and.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6ed0000 } + }, +/* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb68d0000 } + }, +/* and.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6ad0000 } + }, +/* and.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc80d } + }, +/* and.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x882d } + }, +/* and.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x880d } + }, +/* and.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc08d } + }, +/* and.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80ad } + }, +/* and.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x808d } + }, +/* and.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc00d } + }, +/* and.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x802d } + }, +/* and.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x800d } + }, +/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20d00 } + }, +/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822d00 } + }, +/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820d00 } + }, +/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc40d0000 } + }, +/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x842d0000 } + }, +/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x840d0000 } + }, +/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc60d0000 } + }, +/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x862d0000 } + }, +/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x860d0000 } + }, +/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28d00 } + }, +/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82ad00 } + }, +/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828d00 } + }, +/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc48d0000 } + }, +/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84ad0000 } + }, +/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x848d0000 } + }, +/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2cd00 } + }, +/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ed00 } + }, +/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82cd00 } + }, +/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4cd0000 } + }, +/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ed0000 } + }, +/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84cd0000 } + }, +/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6cd0000 } + }, +/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86ed0000 } + }, +/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86cd0000 } + }, +/* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc68d0000 } + }, +/* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86ad0000 } + }, +/* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x868d0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0x918000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0x91a000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0x91b000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0x918400 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0x91a400 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0x91b400 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0x918600 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0x91a600 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0x91b600 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0x91880000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0x91a80000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0x91b80000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0x918c0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0x91ac0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0x91bc0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0x918a0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0x91aa0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0x91ba0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0x918e0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0x91ae0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0x91be0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0x918b0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0x91ab0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0x91bb0000 } + }, +/* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0x918f0000 } + }, +/* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0x91af0000 } + }, +/* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0x91bf0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0x91c00000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0x91e00000 } + }, +/* and.w${G} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0x91f00000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0x91c40000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0x91e40000 } + }, +/* and.w${G} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0x91f40000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0x91c60000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0x91e60000 } + }, +/* and.w${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0x91f60000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0x91c80000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0x91e80000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0x91f80000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0x91cc0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0x91ec0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0x91fc0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0x91ca0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0x91ea0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0x91fa0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0x91ce0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0x91ee0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0x91fe0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0x91cb0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0x91eb0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0x91fb0000 } + }, +/* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0x91cf0000 } + }, +/* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0x91ef0000 } + }, +/* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0x91ff0000 } + }, +/* and.w${G} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0x9100 } + }, +/* and.w${G} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0x9140 } + }, +/* and.w${G} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0x9160 } + }, +/* and.w${G} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0x9104 } + }, +/* and.w${G} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0x9144 } + }, +/* and.w${G} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0x9164 } + }, +/* and.w${G} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0x9106 } + }, +/* and.w${G} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0x9146 } + }, +/* and.w${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0x9166 } + }, +/* and.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0x910800 } + }, +/* and.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0x914800 } + }, +/* and.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0x916800 } + }, +/* and.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0x910c0000 } + }, +/* and.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0x914c0000 } + }, +/* and.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0x916c0000 } + }, +/* and.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0x910a00 } + }, +/* and.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0x914a00 } + }, +/* and.w${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0x916a00 } + }, +/* and.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0x910e0000 } + }, +/* and.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0x914e0000 } + }, +/* and.w${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0x916e0000 } + }, +/* and.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0x910b00 } + }, +/* and.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0x914b00 } + }, +/* and.w${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0x916b00 } + }, +/* and.w${G} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0x910f0000 } + }, +/* and.w${G} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0x914f0000 } + }, +/* and.w${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0x916f0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0x908000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0x90a000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0x90b000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0x908400 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0x90a400 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0x90b400 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0x908600 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0x90a600 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0x90b600 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0x90880000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0x90a80000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0x90b80000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0x908c0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0x90ac0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0x90bc0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0x908a0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0x90aa0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0x90ba0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0x908e0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0x90ae0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0x90be0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0x908b0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0x90ab0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0x90bb0000 } + }, +/* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0x908f0000 } + }, +/* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0x90af0000 } + }, +/* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0x90bf0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0x90c00000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0x90e00000 } + }, +/* and.b${G} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0x90f00000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0x90c40000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0x90e40000 } + }, +/* and.b${G} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0x90f40000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0x90c60000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0x90e60000 } + }, +/* and.b${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0x90f60000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0x90c80000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0x90e80000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0x90f80000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0x90cc0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0x90ec0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0x90fc0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0x90ca0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0x90ea0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0x90fa0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0x90ce0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0x90ee0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0x90fe0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0x90cb0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0x90eb0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0x90fb0000 } + }, +/* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0x90cf0000 } + }, +/* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0x90ef0000 } + }, +/* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0x90ff0000 } + }, +/* and.b${G} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0x9000 } + }, +/* and.b${G} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0x9040 } + }, +/* and.b${G} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0x9060 } + }, +/* and.b${G} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0x9004 } + }, +/* and.b${G} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0x9044 } + }, +/* and.b${G} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0x9064 } + }, +/* and.b${G} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0x9006 } + }, +/* and.b${G} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0x9046 } + }, +/* and.b${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0x9066 } + }, +/* and.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0x900800 } + }, +/* and.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0x904800 } + }, +/* and.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0x906800 } + }, +/* and.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0x900c0000 } + }, +/* and.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0x904c0000 } + }, +/* and.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0x906c0000 } + }, +/* and.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0x900a00 } + }, +/* and.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0x904a00 } + }, +/* and.b${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0x906a00 } + }, +/* and.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0x900e0000 } + }, +/* and.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0x904e0000 } + }, +/* and.b${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0x906e0000 } + }, +/* and.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0x900b00 } + }, +/* and.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0x904b00 } + }, +/* and.b${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0x906b00 } + }, +/* and.b${G} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0x900f0000 } + }, +/* and.b${G} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0x904f0000 } + }, +/* and.b${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0x906f0000 } + }, +/* and.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0x9400 } + }, +/* and.b${S} #${Imm-8-QI},r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0x9300 } + }, +/* and.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0x950000 } + }, +/* and.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0x960000 } + }, +/* and.b${S} #${Imm-8-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0x97000000 } + }, +/* and.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x893f0000 } + }, +/* and.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x81bf0000 } + }, +/* and.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x813f0000 } + }, +/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x833f0000 } + }, +/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83bf0000 } + }, +/* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ff0000 } + }, +/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x853f0000 } + }, +/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85bf0000 } + }, +/* and.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ff0000 } + }, +/* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87ff0000 } + }, +/* and.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x873f0000 } + }, +/* and.w${G} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x87bf0000 } + }, +/* and.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x883f00 } + }, +/* and.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x80bf00 } + }, +/* and.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x803f00 } + }, +/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x823f0000 } + }, +/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82bf0000 } + }, +/* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ff0000 } + }, +/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x843f0000 } + }, +/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84bf0000 } + }, +/* and.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ff0000 } + }, +/* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86ff0000 } + }, +/* and.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x863f0000 } + }, +/* and.b${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x86bf0000 } + }, +/* and.w${G} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77200000 } + }, +/* and.w${G} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77240000 } + }, +/* and.w${G} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77260000 } + }, +/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77280000 } + }, +/* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x772a0000 } + }, +/* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x772b0000 } + }, +/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x772c0000 } + }, +/* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x772e0000 } + }, +/* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x772f0000 } + }, +/* and.b${G} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x762000 } + }, +/* and.b${G} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x762400 } + }, +/* and.b${G} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x762600 } + }, +/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76280000 } + }, +/* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x762a0000 } + }, +/* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x762b0000 } + }, +/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x762c0000 } + }, +/* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x762e0000 } + }, +/* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x762f0000 } + }, +/* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xf3100000 } + }, +/* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xf3900000 } + }, +/* adjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xf3d00000 } + }, +/* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xf5100000 } + }, +/* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xf5900000 } + }, +/* adjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xf5d00000 } + }, +/* adjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xf7d00000 } + }, +/* adjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xf7100000 } + }, +/* adjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } }, + & ifmt_sbjnz32_w_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xf7900000 } + }, +/* adjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xf91000 } + }, +/* adjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xf19000 } + }, +/* adjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz32_w_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xf11000 } + }, +/* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xf2100000 } + }, +/* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xf2900000 } + }, +/* adjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xf2d00000 } + }, +/* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xf4100000 } + }, +/* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xf4900000 } + }, +/* adjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xf4d00000 } + }, +/* adjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xf6d00000 } + }, +/* adjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_40_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xf6100000 } + }, +/* adjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), ',', OP (LAB_40_8), 0 } }, + & ifmt_sbjnz32_b_imm4_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xf6900000 } + }, +/* adjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xf81000 } + }, +/* adjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xf09000 } + }, +/* adjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz32_b_imm4_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xf01000 } + }, +/* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_An_relative_HI, { 0xf9080000 } + }, +/* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_SB_relative_HI, { 0xf90a0000 } + }, +/* adjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz16_w_imm4_16_8_dst16_16_8_FB_relative_HI, { 0xf90b0000 } + }, +/* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_An_relative_HI, { 0xf90c0000 } + }, +/* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_SB_relative_HI, { 0xf90e0000 } + }, +/* adjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz16_w_imm4_16_16_dst16_16_16_absolute_HI, { 0xf90f0000 } + }, +/* adjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz16_w_imm4_basic_dst16_Rn_direct_HI, { 0xf90000 } + }, +/* adjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz16_w_imm4_basic_dst16_An_direct_HI, { 0xf90400 } + }, +/* adjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz16_w_imm4_basic_dst16_An_indirect_HI, { 0xf90600 } + }, +/* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_An_relative_QI, { 0xf8080000 } + }, +/* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_SB_relative_QI, { 0xf80a0000 } + }, +/* adjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (LAB_24_8), 0 } }, + & ifmt_sbjnz16_b_imm4_16_8_dst16_16_8_FB_relative_QI, { 0xf80b0000 } + }, +/* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_An_relative_QI, { 0xf80c0000 } + }, +/* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_SB_relative_QI, { 0xf80e0000 } + }, +/* adjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), ',', OP (LAB_32_8), 0 } }, + & ifmt_sbjnz16_b_imm4_16_16_dst16_16_16_absolute_QI, { 0xf80f0000 } + }, +/* adjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz16_b_imm4_basic_dst16_Rn_direct_QI, { 0xf80000 } + }, +/* adjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz16_b_imm4_basic_dst16_An_direct_QI, { 0xf80400 } + }, +/* adjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', ',', OP (LAB_16_8), 0 } }, + & ifmt_sbjnz16_b_imm4_basic_dst16_An_indirect_QI, { 0xf80600 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x980200 } + }, +/* addx${X} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x982200 } + }, +/* addx${X} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x983200 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x908200 } + }, +/* addx${X} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x90a200 } + }, +/* addx${X} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x90b200 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x900200 } + }, +/* addx${X} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x902200 } + }, +/* addx${X} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x903200 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92020000 } + }, +/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92220000 } + }, +/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_SI, { 0x92320000 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94020000 } + }, +/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94220000 } + }, +/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_SI, { 0x94320000 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96020000 } + }, +/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96220000 } + }, +/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_SI, { 0x96320000 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92820000 } + }, +/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92a20000 } + }, +/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x92b20000 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94820000 } + }, +/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94a20000 } + }, +/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x94b20000 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92c20000 } + }, +/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92e20000 } + }, +/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x92f20000 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94c20000 } + }, +/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94e20000 } + }, +/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x94f20000 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96c20000 } + }, +/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96e20000 } + }, +/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_SI, { 0x96f20000 } + }, +/* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96820000 } + }, +/* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96a20000 } + }, +/* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_subx32_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_SI, { 0x96b20000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8020000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8220000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xa8320000 } + }, +/* addx${X} ${Dsp-16-u16},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8320000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0820000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0a20000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xa0b20000 } + }, +/* addx${X} ${Dsp-16-u16},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0b20000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0020000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0220000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xa0320000 } + }, +/* addx${X} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0320000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2020000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2220000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa2320000 } + }, +/* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb2320000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4020000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4220000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa4320000 } + }, +/* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb4320000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6020000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6220000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa6320000 } + }, +/* addx${X} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb6320000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2820000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2a20000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa2b20000 } + }, +/* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb2b20000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4820000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4a20000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa4b20000 } + }, +/* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb4b20000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2c20000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2e20000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa2f20000 } + }, +/* addx${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb2f20000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4c20000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4e20000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa4f20000 } + }, +/* addx${X} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb4f20000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6c20000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6e20000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xa6f20000 } + }, +/* addx${X} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_SI, { 0xb6f20000 } + }, +/* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6820000 } + }, +/* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6a20000 } + }, +/* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xa6b20000 } + }, +/* addx${X} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_subx32_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_SI, { 0xb6b20000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8020000 } + }, +/* addx${X} ${Dsp-16-u24},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xb8220000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0820000 } + }, +/* addx${X} ${Dsp-16-u24},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xb0a20000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0020000 } + }, +/* addx${X} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xb0220000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb2020000 } + }, +/* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb2220000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb4020000 } + }, +/* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb4220000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb6020000 } + }, +/* addx${X} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb6220000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb2820000 } + }, +/* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb2a20000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb4820000 } + }, +/* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb4a20000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb2c20000 } + }, +/* addx${X} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb2e20000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb4c20000 } + }, +/* addx${X} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb4e20000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI, { 0xb6c20000 } + }, +/* addx${X} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_SI, { 0xb6e20000 } + }, +/* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI, { 0xb6820000 } + }, +/* addx${X} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_subx32_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_SI, { 0xb6a20000 } + }, +/* addx${X} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0xc802 } + }, +/* addx${X} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x8822 } + }, +/* addx${X} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_SI, { 0x8802 } + }, +/* addx${X} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0xc082 } + }, +/* addx${X} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x80a2 } + }, +/* addx${X} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_SI, { 0x8082 } + }, +/* addx${X} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0xc002 } + }, +/* addx${X} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x8022 } + }, +/* addx${X} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_SI, { 0x8002 } + }, +/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc20200 } + }, +/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0x822200 } + }, +/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_SI, { 0x820200 } + }, +/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc4020000 } + }, +/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0x84220000 } + }, +/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_SI, { 0x84020000 } + }, +/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc6020000 } + }, +/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0x86220000 } + }, +/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_SI, { 0x86020000 } + }, +/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc28200 } + }, +/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82a200 } + }, +/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x828200 } + }, +/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc4820000 } + }, +/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84a20000 } + }, +/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84820000 } + }, +/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc2c200 } + }, +/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82e200 } + }, +/* addx${X} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82c200 } + }, +/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc4c20000 } + }, +/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84e20000 } + }, +/* addx${X} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84c20000 } + }, +/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0xc6c20000 } + }, +/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0x86e20000 } + }, +/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_SI, { 0x86c20000 } + }, +/* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0xc6820000 } + }, +/* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0x86a20000 } + }, +/* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_SI, { 0x86820000 } + }, +/* addx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x881100 } + }, +/* addx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x809100 } + }, +/* addx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x801100 } + }, +/* addx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x82110000 } + }, +/* addx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82910000 } + }, +/* addx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82d10000 } + }, +/* addx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x84110000 } + }, +/* addx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84910000 } + }, +/* addx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84d10000 } + }, +/* addx${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_subx32_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x86d10000 } + }, +/* addx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x86110000 } + }, +/* addx${X} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_subx32_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x86910000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978000 } + }, +/* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a000 } + }, +/* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93000 } + }, +/* dadd.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b000 } + }, +/* dadd.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13000 } + }, +/* dadd.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33000 } + }, +/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53000 } + }, +/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73000 } + }, +/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b000 } + }, +/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b000 } + }, +/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f000 } + }, +/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f000 } + }, +/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f000 } + }, +/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78000 } + }, +/* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a000 } + }, +/* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b000 } + }, +/* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90000 } + }, +/* dadd.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18000 } + }, +/* dadd.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10000 } + }, +/* dadd.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30000 } + }, +/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50000 } + }, +/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70000 } + }, +/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38000 } + }, +/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58000 } + }, +/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c000 } + }, +/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c000 } + }, +/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c000 } + }, +/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e000 } + }, +/* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78000 } + }, +/* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a000 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c900 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18920 } + }, +/* dadd.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18900 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c180 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a0 } + }, +/* dadd.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18180 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c100 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18120 } + }, +/* dadd.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18100 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30000 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832000 } + }, +/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830000 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50000 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852000 } + }, +/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850000 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70000 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872000 } + }, +/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870000 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38000 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a000 } + }, +/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838000 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58000 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a000 } + }, +/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858000 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c000 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e000 } + }, +/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c000 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c000 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e000 } + }, +/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c000 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c000 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e000 } + }, +/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c000 } + }, +/* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78000 } + }, +/* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a000 } + }, +/* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968000 } + }, +/* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a000 } + }, +/* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83000 } + }, +/* dadd.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b000 } + }, +/* dadd.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03000 } + }, +/* dadd.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23000 } + }, +/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43000 } + }, +/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63000 } + }, +/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b000 } + }, +/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b000 } + }, +/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f000 } + }, +/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f000 } + }, +/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f000 } + }, +/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68000 } + }, +/* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a000 } + }, +/* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b000 } + }, +/* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80000 } + }, +/* dadd.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08000 } + }, +/* dadd.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00000 } + }, +/* dadd.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20000 } + }, +/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40000 } + }, +/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60000 } + }, +/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28000 } + }, +/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48000 } + }, +/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c000 } + }, +/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c000 } + }, +/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c000 } + }, +/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e000 } + }, +/* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68000 } + }, +/* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a000 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c800 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18820 } + }, +/* dadd.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18800 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c080 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a0 } + }, +/* dadd.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18080 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c000 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18020 } + }, +/* dadd.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18000 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20000 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822000 } + }, +/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820000 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40000 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842000 } + }, +/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840000 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60000 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862000 } + }, +/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860000 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28000 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a000 } + }, +/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828000 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48000 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a000 } + }, +/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848000 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c000 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e000 } + }, +/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c000 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c000 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e000 } + }, +/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c000 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c000 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e000 } + }, +/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c000 } + }, +/* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68000 } + }, +/* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a000 } + }, +/* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868000 } + }, +/* dadd.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1891e00 } + }, +/* dadd.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x1819e00 } + }, +/* dadd.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1811e00 } + }, +/* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1831e00 } + }, +/* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x1839e00 } + }, +/* dadd.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183de00 } + }, +/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1851e00 } + }, +/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x1859e00 } + }, +/* dadd.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185de00 } + }, +/* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187de00 } + }, +/* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1871e00 } + }, +/* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x1879e00 } + }, +/* dadd.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1881e00 } + }, +/* dadd.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x1809e00 } + }, +/* dadd.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1801e00 } + }, +/* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1821e00 } + }, +/* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x1829e00 } + }, +/* dadd.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182de00 } + }, +/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1841e00 } + }, +/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x1849e00 } + }, +/* dadd.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184de00 } + }, +/* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186de00 } + }, +/* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1861e00 } + }, +/* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x1869e00 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978800 } + }, +/* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a800 } + }, +/* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93800 } + }, +/* dadc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b800 } + }, +/* dadc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13800 } + }, +/* dadc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33800 } + }, +/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53800 } + }, +/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73800 } + }, +/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b800 } + }, +/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b800 } + }, +/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f800 } + }, +/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f800 } + }, +/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f800 } + }, +/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78800 } + }, +/* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a800 } + }, +/* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b800 } + }, +/* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90800 } + }, +/* dadc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18800 } + }, +/* dadc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10800 } + }, +/* dadc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30800 } + }, +/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50800 } + }, +/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70800 } + }, +/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38800 } + }, +/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58800 } + }, +/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c800 } + }, +/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c800 } + }, +/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c800 } + }, +/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e800 } + }, +/* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78800 } + }, +/* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a800 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c908 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18928 } + }, +/* dadc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18908 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c188 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a8 } + }, +/* dadc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18188 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c108 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18128 } + }, +/* dadc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18108 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30800 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832800 } + }, +/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830800 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50800 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852800 } + }, +/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850800 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70800 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872800 } + }, +/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870800 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38800 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a800 } + }, +/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838800 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58800 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a800 } + }, +/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858800 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c800 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e800 } + }, +/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c800 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c800 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e800 } + }, +/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c800 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c800 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e800 } + }, +/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c800 } + }, +/* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78800 } + }, +/* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a800 } + }, +/* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968800 } + }, +/* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a800 } + }, +/* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83800 } + }, +/* dadc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b800 } + }, +/* dadc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03800 } + }, +/* dadc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23800 } + }, +/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43800 } + }, +/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63800 } + }, +/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b800 } + }, +/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b800 } + }, +/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f800 } + }, +/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f800 } + }, +/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f800 } + }, +/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68800 } + }, +/* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a800 } + }, +/* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b800 } + }, +/* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80800 } + }, +/* dadc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08800 } + }, +/* dadc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00800 } + }, +/* dadc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20800 } + }, +/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40800 } + }, +/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60800 } + }, +/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28800 } + }, +/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48800 } + }, +/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c800 } + }, +/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c800 } + }, +/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c800 } + }, +/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e800 } + }, +/* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68800 } + }, +/* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a800 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c808 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18828 } + }, +/* dadc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18808 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c088 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a8 } + }, +/* dadc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18088 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c008 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18028 } + }, +/* dadc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18008 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20800 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822800 } + }, +/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820800 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40800 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842800 } + }, +/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840800 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60800 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862800 } + }, +/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860800 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28800 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a800 } + }, +/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828800 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48800 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a800 } + }, +/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848800 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c800 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e800 } + }, +/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c800 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c800 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e800 } + }, +/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c800 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c800 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e800 } + }, +/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c800 } + }, +/* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68800 } + }, +/* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a800 } + }, +/* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868800 } + }, +/* dadc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1890e00 } + }, +/* dadc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x1818e00 } + }, +/* dadc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1810e00 } + }, +/* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1830e00 } + }, +/* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838e00 } + }, +/* dadc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ce00 } + }, +/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1850e00 } + }, +/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858e00 } + }, +/* dadc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ce00 } + }, +/* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187ce00 } + }, +/* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1870e00 } + }, +/* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x1878e00 } + }, +/* dadc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1880e00 } + }, +/* dadc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x1808e00 } + }, +/* dadc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1800e00 } + }, +/* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1820e00 } + }, +/* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828e00 } + }, +/* dadc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ce00 } + }, +/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1840e00 } + }, +/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848e00 } + }, +/* dadc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ce00 } + }, +/* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186ce00 } + }, +/* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1860e00 } + }, +/* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x1868e00 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1990400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1992400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1993400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1918400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191a400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x191b400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1910400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1912400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1913400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1930400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1932400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_An_relative_Prefixed_HI, { 0x1933400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1950400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1952400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_An_relative_Prefixed_HI, { 0x1953400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1970400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1972400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_An_relative_Prefixed_HI, { 0x1973400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x1938400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193a400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_SB_relative_Prefixed_HI, { 0x193b400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x1958400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195a400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_SB_relative_Prefixed_HI, { 0x195b400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193c400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193e400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_8_FB_relative_Prefixed_HI, { 0x193f400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195c400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195e400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_FB_relative_Prefixed_HI, { 0x195f400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197c400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197e400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_16_absolute_Prefixed_HI, { 0x197f400 } + }, +/* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x1978400 } + }, +/* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197a400 } + }, +/* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_w_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_HI_dst32_32_24_absolute_Prefixed_HI, { 0x197b400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a90400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a92400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1a93400 } + }, +/* adc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b93400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a18400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1a400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1a1b400 } + }, +/* adc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1b400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a10400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a12400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1a13400 } + }, +/* adc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b13400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a30400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a32400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1a33400 } + }, +/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_An_relative_Prefixed_HI, { 0x1b33400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a50400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a52400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1a53400 } + }, +/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_An_relative_Prefixed_HI, { 0x1b53400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a70400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a72400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1a73400 } + }, +/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_An_relative_Prefixed_HI, { 0x1b73400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a38400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3a400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1a3b400 } + }, +/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_SB_relative_Prefixed_HI, { 0x1b3b400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a58400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5a400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1a5b400 } + }, +/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_SB_relative_Prefixed_HI, { 0x1b5b400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3c400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3e400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1a3f400 } + }, +/* adc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_8_FB_relative_Prefixed_HI, { 0x1b3f400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5c400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5e400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1a5f400 } + }, +/* adc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_FB_relative_Prefixed_HI, { 0x1b5f400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7c400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7e400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1a7f400 } + }, +/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_16_absolute_Prefixed_HI, { 0x1b7f400 } + }, +/* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a78400 } + }, +/* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7a400 } + }, +/* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1a7b400 } + }, +/* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_w_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_HI_dst32_40_24_absolute_Prefixed_HI, { 0x1b7b400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b90400 } + }, +/* adc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1b92400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b18400 } + }, +/* adc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1b1a400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b10400 } + }, +/* adc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1b12400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b30400 } + }, +/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_An_relative_Prefixed_HI, { 0x1b32400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b50400 } + }, +/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_An_relative_Prefixed_HI, { 0x1b52400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b70400 } + }, +/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_An_relative_Prefixed_HI, { 0x1b72400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b38400 } + }, +/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_SB_relative_Prefixed_HI, { 0x1b3a400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b58400 } + }, +/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_SB_relative_Prefixed_HI, { 0x1b5a400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3c400 } + }, +/* adc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_8_FB_relative_Prefixed_HI, { 0x1b3e400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5c400 } + }, +/* adc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_FB_relative_Prefixed_HI, { 0x1b5e400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7c400 } + }, +/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_16_absolute_Prefixed_HI, { 0x1b7e400 } + }, +/* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b78400 } + }, +/* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_w_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_HI_dst32_48_24_absolute_Prefixed_HI, { 0x1b7a400 } + }, +/* adc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x1c904 } + }, +/* adc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18924 } + }, +/* adc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_Rn_direct_Prefixed_HI, { 0x18904 } + }, +/* adc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x1c184 } + }, +/* adc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x181a4 } + }, +/* adc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_direct_Prefixed_HI, { 0x18184 } + }, +/* adc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x1c104 } + }, +/* adc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18124 } + }, +/* adc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_An_indirect_Prefixed_HI, { 0x18104 } + }, +/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1c30400 } + }, +/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1832400 } + }, +/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_An_relative_Prefixed_HI, { 0x1830400 } + }, +/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1c50400 } + }, +/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1852400 } + }, +/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_An_relative_Prefixed_HI, { 0x1850400 } + }, +/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1c70400 } + }, +/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1872400 } + }, +/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_An_relative_Prefixed_HI, { 0x1870400 } + }, +/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1c38400 } + }, +/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x183a400 } + }, +/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_SB_relative_Prefixed_HI, { 0x1838400 } + }, +/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1c58400 } + }, +/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x185a400 } + }, +/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_SB_relative_Prefixed_HI, { 0x1858400 } + }, +/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x1c3c400 } + }, +/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183e400 } + }, +/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_8_FB_relative_Prefixed_HI, { 0x183c400 } + }, +/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x1c5c400 } + }, +/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185e400 } + }, +/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_FB_relative_Prefixed_HI, { 0x185c400 } + }, +/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x1c7c400 } + }, +/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187e400 } + }, +/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_16_absolute_Prefixed_HI, { 0x187c400 } + }, +/* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1c78400 } + }, +/* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDHI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x187a400 } + }, +/* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_w_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_HI_dst32_24_24_absolute_Prefixed_HI, { 0x1878400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1980400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1982400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1983400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1908400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190a400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x190b400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1900400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1902400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1903400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1920400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1922400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_An_relative_Prefixed_QI, { 0x1923400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1940400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1942400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_An_relative_Prefixed_QI, { 0x1943400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1960400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1962400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_An_relative_Prefixed_QI, { 0x1963400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x1928400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192a400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_SB_relative_Prefixed_QI, { 0x192b400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x1948400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194a400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_SB_relative_Prefixed_QI, { 0x194b400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192c400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192e400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_8_FB_relative_Prefixed_QI, { 0x192f400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194c400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194e400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_FB_relative_Prefixed_QI, { 0x194f400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196c400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196e400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_16_absolute_Prefixed_QI, { 0x196f400 } + }, +/* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_An_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x1968400 } + }, +/* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U8), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_SB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196a400 } + }, +/* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S8), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_tst32_b_24_8_Prefixed_32_Prefixed_src32_24_8_FB_relative_Prefixed_QI_dst32_32_24_absolute_Prefixed_QI, { 0x196b400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a80400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a82400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1a83400 } + }, +/* adc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b83400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a08400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0a400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1a0b400 } + }, +/* adc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0b400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a00400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a02400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1a03400 } + }, +/* adc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b03400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a20400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a22400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1a23400 } + }, +/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_An_relative_Prefixed_QI, { 0x1b23400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a40400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a42400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1a43400 } + }, +/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_An_relative_Prefixed_QI, { 0x1b43400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a60400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a62400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1a63400 } + }, +/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_An_relative_Prefixed_QI, { 0x1b63400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a28400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2a400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1a2b400 } + }, +/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_SB_relative_Prefixed_QI, { 0x1b2b400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a48400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4a400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1a4b400 } + }, +/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_SB_relative_Prefixed_QI, { 0x1b4b400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2c400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2e400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1a2f400 } + }, +/* adc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_8_FB_relative_Prefixed_QI, { 0x1b2f400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4c400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4e400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1a4f400 } + }, +/* adc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_FB_relative_Prefixed_QI, { 0x1b4f400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6c400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6e400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1a6f400 } + }, +/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U16), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_16_absolute_Prefixed_QI, { 0x1b6f400 } + }, +/* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_An_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a68400 } + }, +/* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), '[', 's', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_SB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6a400 } + }, +/* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_S16), '[', 'f', 'b', ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_FB_relative_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1a6b400 } + }, +/* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U16), ',', OP (DSP_40_U24), 0 } }, + & ifmt_tst32_b_24_16_Prefixed_40_Prefixed_src32_24_16_absolute_Prefixed_QI_dst32_40_24_absolute_Prefixed_QI, { 0x1b6b400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b80400 } + }, +/* adc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1b82400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b08400 } + }, +/* adc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1b0a400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b00400 } + }, +/* adc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1b02400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b20400 } + }, +/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_An_relative_Prefixed_QI, { 0x1b22400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b40400 } + }, +/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_An_relative_Prefixed_QI, { 0x1b42400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b60400 } + }, +/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_An_relative_Prefixed_QI, { 0x1b62400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b28400 } + }, +/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_SB_relative_Prefixed_QI, { 0x1b2a400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b48400 } + }, +/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_SB_relative_Prefixed_QI, { 0x1b4a400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2c400 } + }, +/* adc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_8_FB_relative_Prefixed_QI, { 0x1b2e400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4c400 } + }, +/* adc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_FB_relative_Prefixed_QI, { 0x1b4e400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6c400 } + }, +/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U16), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_16_absolute_Prefixed_QI, { 0x1b6e400 } + }, +/* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_An_relative_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b68400 } + }, +/* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_24_U24), ',', OP (DSP_48_U24), 0 } }, + & ifmt_tst32_b_24_24_Prefixed_48_Prefixed_src32_24_24_absolute_Prefixed_QI_dst32_48_24_absolute_Prefixed_QI, { 0x1b6a400 } + }, +/* adc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x1c804 } + }, +/* adc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18824 } + }, +/* adc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_Rn_direct_Prefixed_QI, { 0x18804 } + }, +/* adc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x1c084 } + }, +/* adc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x180a4 } + }, +/* adc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_direct_Prefixed_QI, { 0x18084 } + }, +/* adc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x1c004 } + }, +/* adc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18024 } + }, +/* adc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_An_indirect_Prefixed_QI, { 0x18004 } + }, +/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1c20400 } + }, +/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1822400 } + }, +/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_An_relative_Prefixed_QI, { 0x1820400 } + }, +/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1c40400 } + }, +/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1842400 } + }, +/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_An_relative_Prefixed_QI, { 0x1840400 } + }, +/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1c60400 } + }, +/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1862400 } + }, +/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_An_relative_Prefixed_QI, { 0x1860400 } + }, +/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1c28400 } + }, +/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x182a400 } + }, +/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_SB_relative_Prefixed_QI, { 0x1828400 } + }, +/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1c48400 } + }, +/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x184a400 } + }, +/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_SB_relative_Prefixed_QI, { 0x1848400 } + }, +/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x1c2c400 } + }, +/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182e400 } + }, +/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_8_FB_relative_Prefixed_QI, { 0x182c400 } + }, +/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x1c4c400 } + }, +/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184e400 } + }, +/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_FB_relative_Prefixed_QI, { 0x184c400 } + }, +/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x1c6c400 } + }, +/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186e400 } + }, +/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_16_absolute_Prefixed_QI, { 0x186c400 } + }, +/* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32RNPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_Rn_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1c68400 } + }, +/* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC32ANPREFIXEDQI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_direct_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x186a400 } + }, +/* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC32ANPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_tst32_b_basic_Prefixed_24_Prefixed_src32_An_indirect_Prefixed_QI_dst32_24_24_absolute_Prefixed_QI, { 0x1868400 } + }, +/* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xb18000 } + }, +/* adc.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xb1a000 } + }, +/* adc.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xb1b000 } + }, +/* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xb18400 } + }, +/* adc.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xb1a400 } + }, +/* adc.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xb1b400 } + }, +/* adc.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xb18600 } + }, +/* adc.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xb1a600 } + }, +/* adc.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xb1b600 } + }, +/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xb1880000 } + }, +/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xb1a80000 } + }, +/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xb1b80000 } + }, +/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xb18c0000 } + }, +/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xb1ac0000 } + }, +/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xb1bc0000 } + }, +/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xb18a0000 } + }, +/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xb1aa0000 } + }, +/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xb1ba0000 } + }, +/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xb18e0000 } + }, +/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xb1ae0000 } + }, +/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xb1be0000 } + }, +/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xb18b0000 } + }, +/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xb1ab0000 } + }, +/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xb1bb0000 } + }, +/* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xb18f0000 } + }, +/* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xb1af0000 } + }, +/* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xb1bf0000 } + }, +/* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xb1c00000 } + }, +/* adc.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xb1e00000 } + }, +/* adc.w${X} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xb1f00000 } + }, +/* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xb1c40000 } + }, +/* adc.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xb1e40000 } + }, +/* adc.w${X} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xb1f40000 } + }, +/* adc.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xb1c60000 } + }, +/* adc.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xb1e60000 } + }, +/* adc.w${X} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xb1f60000 } + }, +/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xb1c80000 } + }, +/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xb1e80000 } + }, +/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xb1f80000 } + }, +/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xb1cc0000 } + }, +/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xb1ec0000 } + }, +/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xb1fc0000 } + }, +/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xb1ca0000 } + }, +/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xb1ea0000 } + }, +/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xb1fa0000 } + }, +/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xb1ce0000 } + }, +/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xb1ee0000 } + }, +/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xb1fe0000 } + }, +/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xb1cb0000 } + }, +/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xb1eb0000 } + }, +/* adc.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xb1fb0000 } + }, +/* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xb1cf0000 } + }, +/* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xb1ef0000 } + }, +/* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xb1ff0000 } + }, +/* adc.w${X} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xb100 } + }, +/* adc.w${X} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xb140 } + }, +/* adc.w${X} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xb160 } + }, +/* adc.w${X} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xb104 } + }, +/* adc.w${X} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xb144 } + }, +/* adc.w${X} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xb164 } + }, +/* adc.w${X} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xb106 } + }, +/* adc.w${X} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xb146 } + }, +/* adc.w${X} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xb166 } + }, +/* adc.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xb10800 } + }, +/* adc.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xb14800 } + }, +/* adc.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xb16800 } + }, +/* adc.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xb10c0000 } + }, +/* adc.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xb14c0000 } + }, +/* adc.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xb16c0000 } + }, +/* adc.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xb10a00 } + }, +/* adc.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xb14a00 } + }, +/* adc.w${X} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xb16a00 } + }, +/* adc.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xb10e0000 } + }, +/* adc.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xb14e0000 } + }, +/* adc.w${X} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xb16e0000 } + }, +/* adc.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xb10b00 } + }, +/* adc.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xb14b00 } + }, +/* adc.w${X} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xb16b00 } + }, +/* adc.w${X} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xb10f0000 } + }, +/* adc.w${X} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xb14f0000 } + }, +/* adc.w${X} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xb16f0000 } + }, +/* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xb08000 } + }, +/* adc.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xb0a000 } + }, +/* adc.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xb0b000 } + }, +/* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xb08400 } + }, +/* adc.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xb0a400 } + }, +/* adc.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xb0b400 } + }, +/* adc.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xb08600 } + }, +/* adc.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xb0a600 } + }, +/* adc.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xb0b600 } + }, +/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xb0880000 } + }, +/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xb0a80000 } + }, +/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xb0b80000 } + }, +/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xb08c0000 } + }, +/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xb0ac0000 } + }, +/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xb0bc0000 } + }, +/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xb08a0000 } + }, +/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xb0aa0000 } + }, +/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xb0ba0000 } + }, +/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xb08e0000 } + }, +/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xb0ae0000 } + }, +/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xb0be0000 } + }, +/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xb08b0000 } + }, +/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xb0ab0000 } + }, +/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xb0bb0000 } + }, +/* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xb08f0000 } + }, +/* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xb0af0000 } + }, +/* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xb0bf0000 } + }, +/* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xb0c00000 } + }, +/* adc.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xb0e00000 } + }, +/* adc.b${X} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xb0f00000 } + }, +/* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xb0c40000 } + }, +/* adc.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xb0e40000 } + }, +/* adc.b${X} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xb0f40000 } + }, +/* adc.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xb0c60000 } + }, +/* adc.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xb0e60000 } + }, +/* adc.b${X} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xb0f60000 } + }, +/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xb0c80000 } + }, +/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xb0e80000 } + }, +/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xb0f80000 } + }, +/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xb0cc0000 } + }, +/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xb0ec0000 } + }, +/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xb0fc0000 } + }, +/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xb0ca0000 } + }, +/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xb0ea0000 } + }, +/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xb0fa0000 } + }, +/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xb0ce0000 } + }, +/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xb0ee0000 } + }, +/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xb0fe0000 } + }, +/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xb0cb0000 } + }, +/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xb0eb0000 } + }, +/* adc.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xb0fb0000 } + }, +/* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xb0cf0000 } + }, +/* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xb0ef0000 } + }, +/* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xb0ff0000 } + }, +/* adc.b${X} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xb000 } + }, +/* adc.b${X} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xb040 } + }, +/* adc.b${X} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xb060 } + }, +/* adc.b${X} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xb004 } + }, +/* adc.b${X} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xb044 } + }, +/* adc.b${X} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xb064 } + }, +/* adc.b${X} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xb006 } + }, +/* adc.b${X} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xb046 } + }, +/* adc.b${X} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xb066 } + }, +/* adc.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xb00800 } + }, +/* adc.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xb04800 } + }, +/* adc.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xb06800 } + }, +/* adc.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xb00c0000 } + }, +/* adc.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xb04c0000 } + }, +/* adc.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xb06c0000 } + }, +/* adc.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xb00a00 } + }, +/* adc.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xb04a00 } + }, +/* adc.b${X} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xb06a00 } + }, +/* adc.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xb00e0000 } + }, +/* adc.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xb04e0000 } + }, +/* adc.b${X} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xb06e0000 } + }, +/* adc.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xb00b00 } + }, +/* adc.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xb04b00 } + }, +/* adc.b${X} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xb06b00 } + }, +/* adc.b${X} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xb00f0000 } + }, +/* adc.b${X} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xb04f0000 } + }, +/* adc.b${X} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xb06f0000 } + }, +/* adc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32RNPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_HI, { 0x1892e00 } + }, +/* adc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DST32ANPREFIXEDHI), 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_HI, { 0x181ae00 } + }, +/* adc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_HI, { 0x1812e00 } + }, +/* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_HI, { 0x1832e00 } + }, +/* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_HI, { 0x183ae00 } + }, +/* adc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_HI, { 0x183ee00 } + }, +/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_HI, { 0x1852e00 } + }, +/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_HI, { 0x185ae00 } + }, +/* adc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_HI, { 0x185ee00 } + }, +/* adc.w${X} #${Imm-40-HI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_w_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_HI, { 0x187ee00 } + }, +/* adc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_HI, { 0x1872e00 } + }, +/* adc.w${X} #${Imm-48-HI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_HI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_w_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_HI, { 0x187ae00 } + }, +/* adc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32RNPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_Rn_direct_Prefixed_QI, { 0x1882e00 } + }, +/* adc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DST32ANPREFIXEDQI), 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_direct_Prefixed_QI, { 0x180ae00 } + }, +/* adc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_basic_Prefixed_dst32_An_indirect_Prefixed_QI, { 0x1802e00 } + }, +/* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_An_relative_Prefixed_QI, { 0x1822e00 } + }, +/* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_SB_relative_Prefixed_QI, { 0x182ae00 } + }, +/* adc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_8_Prefixed_dst32_24_8_FB_relative_Prefixed_QI, { 0x182ee00 } + }, +/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_An_relative_Prefixed_QI, { 0x1842e00 } + }, +/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_SB_relative_Prefixed_QI, { 0x184ae00 } + }, +/* adc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_FB_relative_Prefixed_QI, { 0x184ee00 } + }, +/* adc.b${X} #${Imm-40-QI},${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_24_U16), 0 } }, + & ifmt_sbb32_b_imm_G_24_16_Prefixed_dst32_24_16_absolute_Prefixed_QI, { 0x186ee00 } + }, +/* adc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), '[', OP (DST32ANPREFIXED), ']', 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_An_relative_Prefixed_QI, { 0x1862e00 } + }, +/* adc.b${X} #${Imm-48-QI},${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_48_QI), ',', OP (DSP_24_U24), 0 } }, + & ifmt_sbb32_b_imm_G_24_24_Prefixed_dst32_24_24_absolute_Prefixed_QI, { 0x186ae00 } + }, +/* adc.w${X} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77600000 } + }, +/* adc.w${X} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77640000 } + }, +/* adc.w${X} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77660000 } + }, +/* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77680000 } + }, +/* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x776a0000 } + }, +/* adc.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x776b0000 } + }, +/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x776c0000 } + }, +/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x776e0000 } + }, +/* adc.w${X} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x776f0000 } + }, +/* adc.b${X} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x766000 } + }, +/* adc.b${X} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x766400 } + }, +/* adc.b${X} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x766600 } + }, +/* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76680000 } + }, +/* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x766a0000 } + }, +/* adc.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x766b0000 } + }, +/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x766c0000 } + }, +/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x766e0000 } + }, +/* adc.b${X} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (X), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x766f0000 } + }, +/* add.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x27000000 } + }, +/* add.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x37000000 } + }, +/* add.w${S} #${Imm-24-HI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x17000000 } + }, +/* add.w${S} #${Imm-8-HI},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } }, + & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x70000 } + }, +/* add.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x260000 } + }, +/* add.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x360000 } + }, +/* add.b${S} #${Imm-24-QI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x16000000 } + }, +/* add.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x600 } + }, +/* add.l${S} #${Imm1-S},a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM1_S), ',', 'a', '0', 0 } }, + & ifmt_add32_l_s_imm1_S_an_dst32_1_S_A0_direct_HI, { 0x8c } + }, +/* add.l${S} #${Imm1-S},a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM1_S), ',', 'a', '1', 0 } }, + & ifmt_add32_l_s_imm1_S_an_dst32_1_S_A1_direct_HI, { 0x8d } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x990200 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x992200 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x993200 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x918200 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91a200 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x91b200 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x910200 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x912200 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x913200 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93020000 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93220000 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_An_relative_Unprefixed_SI, { 0x93320000 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95020000 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95220000 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_An_relative_Unprefixed_SI, { 0x95320000 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97020000 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97220000 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_An_relative_Unprefixed_SI, { 0x97320000 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93820000 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93a20000 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_SB_relative_Unprefixed_SI, { 0x93b20000 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95820000 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95a20000 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_SB_relative_Unprefixed_SI, { 0x95b20000 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93c20000 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93e20000 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_8_FB_relative_Unprefixed_SI, { 0x93f20000 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95c20000 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95e20000 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_FB_relative_Unprefixed_SI, { 0x95f20000 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97c20000 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97e20000 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_16_absolute_Unprefixed_SI, { 0x97f20000 } + }, +/* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97820000 } + }, +/* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97a20000 } + }, +/* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_mov32_l_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_SI_dst32_24_24_absolute_Unprefixed_SI, { 0x97b20000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9020000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9220000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xa9320000 } + }, +/* add.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9320000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1820000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1a20000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xa1b20000 } + }, +/* add.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1b20000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1020000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1220000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xa1320000 } + }, +/* add.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1320000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3020000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3220000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xa3320000 } + }, +/* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_An_relative_Unprefixed_SI, { 0xb3320000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5020000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5220000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xa5320000 } + }, +/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_An_relative_Unprefixed_SI, { 0xb5320000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7020000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7220000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xa7320000 } + }, +/* add.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_An_relative_Unprefixed_SI, { 0xb7320000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3820000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3a20000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xa3b20000 } + }, +/* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_SB_relative_Unprefixed_SI, { 0xb3b20000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5820000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5a20000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xa5b20000 } + }, +/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_SB_relative_Unprefixed_SI, { 0xb5b20000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3c20000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3e20000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xa3f20000 } + }, +/* add.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_8_FB_relative_Unprefixed_SI, { 0xb3f20000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5c20000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5e20000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xa5f20000 } + }, +/* add.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_FB_relative_Unprefixed_SI, { 0xb5f20000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7c20000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7e20000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xa7f20000 } + }, +/* add.l${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_16_absolute_Unprefixed_SI, { 0xb7f20000 } + }, +/* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7820000 } + }, +/* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7a20000 } + }, +/* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xa7b20000 } + }, +/* add.l${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_mov32_l_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_SI_dst32_32_24_absolute_Unprefixed_SI, { 0xb7b20000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9020000 } + }, +/* add.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xb9220000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1820000 } + }, +/* add.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xb1a20000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1020000 } + }, +/* add.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xb1220000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3020000 } + }, +/* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_An_relative_Unprefixed_SI, { 0xb3220000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5020000 } + }, +/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_An_relative_Unprefixed_SI, { 0xb5220000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7020000 } + }, +/* add.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_An_relative_Unprefixed_SI, { 0xb7220000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3820000 } + }, +/* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_SB_relative_Unprefixed_SI, { 0xb3a20000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5820000 } + }, +/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_SB_relative_Unprefixed_SI, { 0xb5a20000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3c20000 } + }, +/* add.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_8_FB_relative_Unprefixed_SI, { 0xb3e20000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5c20000 } + }, +/* add.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_FB_relative_Unprefixed_SI, { 0xb5e20000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7c20000 } + }, +/* add.l${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_16_absolute_Unprefixed_SI, { 0xb7e20000 } + }, +/* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7820000 } + }, +/* add.l${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_mov32_l_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_SI_dst32_40_24_absolute_Unprefixed_SI, { 0xb7a20000 } + }, +/* add.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0xc902 } + }, +/* add.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8922 } + }, +/* add.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_Rn_direct_Unprefixed_SI, { 0x8902 } + }, +/* add.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0xc182 } + }, +/* add.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x81a2 } + }, +/* add.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_direct_Unprefixed_SI, { 0x8182 } + }, +/* add.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0xc102 } + }, +/* add.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8122 } + }, +/* add.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_An_indirect_Unprefixed_SI, { 0x8102 } + }, +/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0xc30200 } + }, +/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x832200 } + }, +/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_An_relative_Unprefixed_SI, { 0x830200 } + }, +/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0xc5020000 } + }, +/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85220000 } + }, +/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_An_relative_Unprefixed_SI, { 0x85020000 } + }, +/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0xc7020000 } + }, +/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87220000 } + }, +/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_An_relative_Unprefixed_SI, { 0x87020000 } + }, +/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0xc38200 } + }, +/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x83a200 } + }, +/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_SB_relative_Unprefixed_SI, { 0x838200 } + }, +/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0xc5820000 } + }, +/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85a20000 } + }, +/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_SB_relative_Unprefixed_SI, { 0x85820000 } + }, +/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0xc3c200 } + }, +/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83e200 } + }, +/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_8_FB_relative_Unprefixed_SI, { 0x83c200 } + }, +/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0xc5c20000 } + }, +/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85e20000 } + }, +/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_FB_relative_Unprefixed_SI, { 0x85c20000 } + }, +/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0xc7c20000 } + }, +/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87e20000 } + }, +/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_16_absolute_Unprefixed_SI, { 0x87c20000 } + }, +/* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0xc7820000 } + }, +/* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDSI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87a20000 } + }, +/* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_SI_dst32_16_24_absolute_Unprefixed_SI, { 0x87820000 } + }, +/* add.b${S} ${SrcDst16-r0l-r0h-S-normal} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (SRCDST16_R0L_R0H_S_NORMAL), 0 } }, + & ifmt_mov16_b_S_r0l_r0h_srcdst16_r0l_r0h_S_derived, { 0x20 } + }, +/* add.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_mov16_b_S_src2_src16_2_S_8_SB_relative_QI, { 0x2100 } + }, +/* add.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI_S), 0 } }, + & ifmt_mov16_b_S_src2_src16_2_S_8_FB_relative_QI, { 0x2200 } + }, +/* add.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', OP (DSP_8_U16), ',', OP (DST16RNQI_S), 0 } }, + & ifmt_mov16_b_S_src2_src16_2_S_16_absolute_QI, { 0x230000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x990800 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x992800 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x993800 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x918800 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91a800 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x91b800 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x910800 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x912800 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x913800 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93080000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93280000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_An_relative_Unprefixed_HI, { 0x93380000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95080000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95280000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_An_relative_Unprefixed_HI, { 0x95380000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97080000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97280000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_An_relative_Unprefixed_HI, { 0x97380000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93880000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93a80000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_SB_relative_Unprefixed_HI, { 0x93b80000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95880000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95a80000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_SB_relative_Unprefixed_HI, { 0x95b80000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93c80000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93e80000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_8_FB_relative_Unprefixed_HI, { 0x93f80000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95c80000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95e80000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_FB_relative_Unprefixed_HI, { 0x95f80000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97c80000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97e80000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_16_absolute_Unprefixed_HI, { 0x97f80000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97880000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97a80000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_w_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_HI_dst32_24_24_absolute_Unprefixed_HI, { 0x97b80000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9080000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9280000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xa9380000 } + }, +/* add.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9380000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1880000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1a80000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xa1b80000 } + }, +/* add.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1b80000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1080000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1280000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xa1380000 } + }, +/* add.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1380000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3080000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3280000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xa3380000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_An_relative_Unprefixed_HI, { 0xb3380000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5080000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5280000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xa5380000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_An_relative_Unprefixed_HI, { 0xb5380000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7080000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7280000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xa7380000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_An_relative_Unprefixed_HI, { 0xb7380000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3880000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3a80000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xa3b80000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_SB_relative_Unprefixed_HI, { 0xb3b80000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5880000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5a80000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xa5b80000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_SB_relative_Unprefixed_HI, { 0xb5b80000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3c80000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3e80000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xa3f80000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_8_FB_relative_Unprefixed_HI, { 0xb3f80000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5c80000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5e80000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xa5f80000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_FB_relative_Unprefixed_HI, { 0xb5f80000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7c80000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7e80000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xa7f80000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_16_absolute_Unprefixed_HI, { 0xb7f80000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7880000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7a80000 } + }, +/* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xa7b80000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_w_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_HI_dst32_32_24_absolute_Unprefixed_HI, { 0xb7b80000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9080000 } + }, +/* add.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xb9280000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1880000 } + }, +/* add.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xb1a80000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1080000 } + }, +/* add.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xb1280000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3080000 } + }, +/* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_An_relative_Unprefixed_HI, { 0xb3280000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5080000 } + }, +/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_An_relative_Unprefixed_HI, { 0xb5280000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7080000 } + }, +/* add.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_An_relative_Unprefixed_HI, { 0xb7280000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3880000 } + }, +/* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_SB_relative_Unprefixed_HI, { 0xb3a80000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5880000 } + }, +/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_SB_relative_Unprefixed_HI, { 0xb5a80000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3c80000 } + }, +/* add.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_8_FB_relative_Unprefixed_HI, { 0xb3e80000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5c80000 } + }, +/* add.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_FB_relative_Unprefixed_HI, { 0xb5e80000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7c80000 } + }, +/* add.w${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_16_absolute_Unprefixed_HI, { 0xb7e80000 } + }, +/* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7880000 } + }, +/* add.w${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_w_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_HI_dst32_40_24_absolute_Unprefixed_HI, { 0xb7a80000 } + }, +/* add.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0xc908 } + }, +/* add.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8928 } + }, +/* add.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_Rn_direct_Unprefixed_HI, { 0x8908 } + }, +/* add.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0xc188 } + }, +/* add.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x81a8 } + }, +/* add.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_direct_Unprefixed_HI, { 0x8188 } + }, +/* add.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0xc108 } + }, +/* add.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8128 } + }, +/* add.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_An_indirect_Unprefixed_HI, { 0x8108 } + }, +/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0xc30800 } + }, +/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x832800 } + }, +/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_An_relative_Unprefixed_HI, { 0x830800 } + }, +/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0xc5080000 } + }, +/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85280000 } + }, +/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_An_relative_Unprefixed_HI, { 0x85080000 } + }, +/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0xc7080000 } + }, +/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87280000 } + }, +/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_An_relative_Unprefixed_HI, { 0x87080000 } + }, +/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0xc38800 } + }, +/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83a800 } + }, +/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_SB_relative_Unprefixed_HI, { 0x838800 } + }, +/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0xc5880000 } + }, +/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85a80000 } + }, +/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85880000 } + }, +/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0xc3c800 } + }, +/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83e800 } + }, +/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83c800 } + }, +/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0xc5c80000 } + }, +/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85e80000 } + }, +/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85c80000 } + }, +/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0xc7c80000 } + }, +/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87e80000 } + }, +/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_16_absolute_Unprefixed_HI, { 0x87c80000 } + }, +/* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0xc7880000 } + }, +/* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDHI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87a80000 } + }, +/* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_HI_dst32_16_24_absolute_Unprefixed_HI, { 0x87880000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x980800 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x982800 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x983800 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x908800 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90a800 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x90b800 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x900800 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x902800 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x903800 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92080000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92280000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_An_relative_Unprefixed_QI, { 0x92380000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94080000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94280000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_An_relative_Unprefixed_QI, { 0x94380000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96080000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96280000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_An_relative_Unprefixed_QI, { 0x96380000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92880000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92a80000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_SB_relative_Unprefixed_QI, { 0x92b80000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94880000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94a80000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_SB_relative_Unprefixed_QI, { 0x94b80000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92c80000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92e80000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_8_FB_relative_Unprefixed_QI, { 0x92f80000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94c80000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94e80000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_FB_relative_Unprefixed_QI, { 0x94f80000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96c80000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96e80000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_16_absolute_Unprefixed_QI, { 0x96f80000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_An_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96880000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_SB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96a80000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U24), 0 } }, + & ifmt_xor32_b_16_8_Unprefixed_24_Unprefixed_src32_16_8_FB_relative_Unprefixed_QI_dst32_24_24_absolute_Unprefixed_QI, { 0x96b80000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8080000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8280000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xa8380000 } + }, +/* add.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8380000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0880000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0a80000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xa0b80000 } + }, +/* add.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0b80000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0080000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0280000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xa0380000 } + }, +/* add.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0380000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2080000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2280000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xa2380000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_An_relative_Unprefixed_QI, { 0xb2380000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4080000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4280000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xa4380000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_An_relative_Unprefixed_QI, { 0xb4380000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6080000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6280000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xa6380000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_An_relative_Unprefixed_QI, { 0xb6380000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2880000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2a80000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xa2b80000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_SB_relative_Unprefixed_QI, { 0xb2b80000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4880000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4a80000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xa4b80000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_SB_relative_Unprefixed_QI, { 0xb4b80000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2c80000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2e80000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xa2f80000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_8_FB_relative_Unprefixed_QI, { 0xb2f80000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4c80000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4e80000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xa4f80000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_FB_relative_Unprefixed_QI, { 0xb4f80000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6c80000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6e80000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xa6f80000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_16_absolute_Unprefixed_QI, { 0xb6f80000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_An_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6880000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_SB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6a80000 } + }, +/* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_FB_relative_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xa6b80000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_xor32_b_16_16_Unprefixed_32_Unprefixed_src32_16_16_absolute_Unprefixed_QI_dst32_32_24_absolute_Unprefixed_QI, { 0xb6b80000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8080000 } + }, +/* add.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xb8280000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0880000 } + }, +/* add.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xb0a80000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0080000 } + }, +/* add.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xb0280000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2080000 } + }, +/* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_An_relative_Unprefixed_QI, { 0xb2280000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4080000 } + }, +/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_An_relative_Unprefixed_QI, { 0xb4280000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6080000 } + }, +/* add.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_An_relative_Unprefixed_QI, { 0xb6280000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2880000 } + }, +/* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_SB_relative_Unprefixed_QI, { 0xb2a80000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4880000 } + }, +/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_SB_relative_Unprefixed_QI, { 0xb4a80000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2c80000 } + }, +/* add.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_8_FB_relative_Unprefixed_QI, { 0xb2e80000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4c80000 } + }, +/* add.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_FB_relative_Unprefixed_QI, { 0xb4e80000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6c80000 } + }, +/* add.b${G} ${Dsp-16-u24},${Dsp-40-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U16), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_16_absolute_Unprefixed_QI, { 0xb6e80000 } + }, +/* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_An_relative_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6880000 } + }, +/* add.b${G} ${Dsp-16-u24},${Dsp-40-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U24), ',', OP (DSP_40_U24), 0 } }, + & ifmt_xor32_b_16_24_Unprefixed_40_Unprefixed_src32_16_24_absolute_Unprefixed_QI_dst32_40_24_absolute_Unprefixed_QI, { 0xb6a80000 } + }, +/* add.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0xc808 } + }, +/* add.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8828 } + }, +/* add.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_Rn_direct_Unprefixed_QI, { 0x8808 } + }, +/* add.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0xc088 } + }, +/* add.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x80a8 } + }, +/* add.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_direct_Unprefixed_QI, { 0x8088 } + }, +/* add.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0xc008 } + }, +/* add.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8028 } + }, +/* add.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_An_indirect_Unprefixed_QI, { 0x8008 } + }, +/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0xc20800 } + }, +/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x822800 } + }, +/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_An_relative_Unprefixed_QI, { 0x820800 } + }, +/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0xc4080000 } + }, +/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84280000 } + }, +/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_An_relative_Unprefixed_QI, { 0x84080000 } + }, +/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0xc6080000 } + }, +/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86280000 } + }, +/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_An_relative_Unprefixed_QI, { 0x86080000 } + }, +/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0xc28800 } + }, +/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82a800 } + }, +/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_SB_relative_Unprefixed_QI, { 0x828800 } + }, +/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0xc4880000 } + }, +/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84a80000 } + }, +/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84880000 } + }, +/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0xc2c800 } + }, +/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82e800 } + }, +/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82c800 } + }, +/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0xc4c80000 } + }, +/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84e80000 } + }, +/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84c80000 } + }, +/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0xc6c80000 } + }, +/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86e80000 } + }, +/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_16_absolute_Unprefixed_QI, { 0x86c80000 } + }, +/* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32RNUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_Rn_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0xc6880000 } + }, +/* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC32ANUNPREFIXEDQI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_direct_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86a80000 } + }, +/* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC32ANUNPREFIXED), ']', ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_basic_Unprefixed_16_Unprefixed_src32_An_indirect_Unprefixed_QI_dst32_16_24_absolute_Unprefixed_QI, { 0x86880000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_Rn_direct_HI, { 0xa18000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_Rn_direct_HI, { 0xa1a000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_Rn_direct_HI, { 0xa1b000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_direct_HI, { 0xa18400 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_direct_HI, { 0xa1a400 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_direct_HI, { 0xa1b400 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_An_indirect_HI, { 0xa18600 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_An_indirect_HI, { 0xa1a600 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_An_indirect_HI, { 0xa1b600 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_An_relative_HI, { 0xa1880000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_An_relative_HI, { 0xa1a80000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_An_relative_HI, { 0xa1b80000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_An_relative_HI, { 0xa18c0000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_An_relative_HI, { 0xa1ac0000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_An_relative_HI, { 0xa1bc0000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_SB_relative_HI, { 0xa18a0000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_SB_relative_HI, { 0xa1aa0000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_SB_relative_HI, { 0xa1ba0000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_SB_relative_HI, { 0xa18e0000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_SB_relative_HI, { 0xa1ae0000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_SB_relative_HI, { 0xa1be0000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_8_FB_relative_HI, { 0xa18b0000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_8_FB_relative_HI, { 0xa1ab0000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_8_FB_relative_HI, { 0xa1bb0000 } + }, +/* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_An_relative_HI_dst16_24_16_absolute_HI, { 0xa18f0000 } + }, +/* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_SB_relative_HI_dst16_24_16_absolute_HI, { 0xa1af0000 } + }, +/* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_w_16_8_24_src16_16_8_FB_relative_HI_dst16_24_16_absolute_HI, { 0xa1bf0000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_Rn_direct_HI, { 0xa1c00000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_Rn_direct_HI, { 0xa1e00000 } + }, +/* add.w${G} ${Dsp-16-u16},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_Rn_direct_HI, { 0xa1f00000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_direct_HI, { 0xa1c40000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_direct_HI, { 0xa1e40000 } + }, +/* add.w${G} ${Dsp-16-u16},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_direct_HI, { 0xa1f40000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_An_indirect_HI, { 0xa1c60000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_An_indirect_HI, { 0xa1e60000 } + }, +/* add.w${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_An_indirect_HI, { 0xa1f60000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_An_relative_HI, { 0xa1c80000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_An_relative_HI, { 0xa1e80000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_An_relative_HI, { 0xa1f80000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_An_relative_HI, { 0xa1cc0000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_An_relative_HI, { 0xa1ec0000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_An_relative_HI, { 0xa1fc0000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_SB_relative_HI, { 0xa1ca0000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_SB_relative_HI, { 0xa1ea0000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_SB_relative_HI, { 0xa1fa0000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_SB_relative_HI, { 0xa1ce0000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_SB_relative_HI, { 0xa1ee0000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_SB_relative_HI, { 0xa1fe0000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_8_FB_relative_HI, { 0xa1cb0000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_8_FB_relative_HI, { 0xa1eb0000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_8_FB_relative_HI, { 0xa1fb0000 } + }, +/* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_An_relative_HI_dst16_32_16_absolute_HI, { 0xa1cf0000 } + }, +/* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_SB_relative_HI_dst16_32_16_absolute_HI, { 0xa1ef0000 } + }, +/* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_w_16_16_32_src16_16_16_absolute_HI_dst16_32_16_absolute_HI, { 0xa1ff0000 } + }, +/* add.w${G} $Src16RnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_Rn_direct_HI, { 0xa100 } + }, +/* add.w${G} $Src16AnHI,$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_Rn_direct_HI, { 0xa140 } + }, +/* add.w${G} [$Src16An],$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_Rn_direct_HI, { 0xa160 } + }, +/* add.w${G} $Src16RnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_direct_HI, { 0xa104 } + }, +/* add.w${G} $Src16AnHI,$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_direct_HI, { 0xa144 } + }, +/* add.w${G} [$Src16An],$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_direct_HI, { 0xa164 } + }, +/* add.w${G} $Src16RnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_An_indirect_HI, { 0xa106 } + }, +/* add.w${G} $Src16AnHI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_An_indirect_HI, { 0xa146 } + }, +/* add.w${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_An_indirect_HI, { 0xa166 } + }, +/* add.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_An_relative_HI, { 0xa10800 } + }, +/* add.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_An_relative_HI, { 0xa14800 } + }, +/* add.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_An_relative_HI, { 0xa16800 } + }, +/* add.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_An_relative_HI, { 0xa10c0000 } + }, +/* add.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_An_relative_HI, { 0xa14c0000 } + }, +/* add.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_An_relative_HI, { 0xa16c0000 } + }, +/* add.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_SB_relative_HI, { 0xa10a00 } + }, +/* add.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_SB_relative_HI, { 0xa14a00 } + }, +/* add.w${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_SB_relative_HI, { 0xa16a00 } + }, +/* add.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_SB_relative_HI, { 0xa10e0000 } + }, +/* add.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_SB_relative_HI, { 0xa14e0000 } + }, +/* add.w${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_SB_relative_HI, { 0xa16e0000 } + }, +/* add.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_8_FB_relative_HI, { 0xa10b00 } + }, +/* add.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_8_FB_relative_HI, { 0xa14b00 } + }, +/* add.w${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_8_FB_relative_HI, { 0xa16b00 } + }, +/* add.w${G} $Src16RnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_Rn_direct_HI_dst16_16_16_absolute_HI, { 0xa10f0000 } + }, +/* add.w${G} $Src16AnHI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANHI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_direct_HI_dst16_16_16_absolute_HI, { 0xa14f0000 } + }, +/* add.w${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_basic_16_src16_An_indirect_HI_dst16_16_16_absolute_HI, { 0xa16f0000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_Rn_direct_QI, { 0xa08000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_Rn_direct_QI, { 0xa0a000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_Rn_direct_QI, { 0xa0b000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_direct_QI, { 0xa08400 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_direct_QI, { 0xa0a400 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_direct_QI, { 0xa0b400 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_An_indirect_QI, { 0xa08600 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_An_indirect_QI, { 0xa0a600 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_An_indirect_QI, { 0xa0b600 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_An_relative_QI, { 0xa0880000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_An_relative_QI, { 0xa0a80000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_An_relative_QI, { 0xa0b80000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_An_relative_QI, { 0xa08c0000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_An_relative_QI, { 0xa0ac0000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_An_relative_QI, { 0xa0bc0000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_SB_relative_QI, { 0xa08a0000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_SB_relative_QI, { 0xa0aa0000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_SB_relative_QI, { 0xa0ba0000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_SB_relative_QI, { 0xa08e0000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_SB_relative_QI, { 0xa0ae0000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_SB_relative_QI, { 0xa0be0000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_8_FB_relative_QI, { 0xa08b0000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_8_FB_relative_QI, { 0xa0ab0000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_8_FB_relative_QI, { 0xa0bb0000 } + }, +/* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', OP (SRC16AN), ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_An_relative_QI_dst16_24_16_absolute_QI, { 0xa08f0000 } + }, +/* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U8), '[', 's', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_SB_relative_QI_dst16_24_16_absolute_QI, { 0xa0af0000 } + }, +/* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', ',', OP (DSP_24_U16), 0 } }, + & ifmt_xor16_b_16_8_24_src16_16_8_FB_relative_QI_dst16_24_16_absolute_QI, { 0xa0bf0000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_Rn_direct_QI, { 0xa0c00000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_Rn_direct_QI, { 0xa0e00000 } + }, +/* add.b${G} ${Dsp-16-u16},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_Rn_direct_QI, { 0xa0f00000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_direct_QI, { 0xa0c40000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_direct_QI, { 0xa0e40000 } + }, +/* add.b${G} ${Dsp-16-u16},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_direct_QI, { 0xa0f40000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_An_indirect_QI, { 0xa0c60000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_An_indirect_QI, { 0xa0e60000 } + }, +/* add.b${G} ${Dsp-16-u16},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_An_indirect_QI, { 0xa0f60000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_An_relative_QI, { 0xa0c80000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_An_relative_QI, { 0xa0e80000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_An_relative_QI, { 0xa0f80000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_An_relative_QI, { 0xa0cc0000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_An_relative_QI, { 0xa0ec0000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_An_relative_QI, { 0xa0fc0000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_SB_relative_QI, { 0xa0ca0000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_SB_relative_QI, { 0xa0ea0000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_SB_relative_QI, { 0xa0fa0000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_SB_relative_QI, { 0xa0ce0000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_SB_relative_QI, { 0xa0ee0000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_SB_relative_QI, { 0xa0fe0000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_8_FB_relative_QI, { 0xa0cb0000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_8_FB_relative_QI, { 0xa0eb0000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_8_FB_relative_QI, { 0xa0fb0000 } + }, +/* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', OP (SRC16AN), ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_An_relative_QI_dst16_32_16_absolute_QI, { 0xa0cf0000 } + }, +/* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), '[', 's', 'b', ']', ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_SB_relative_QI_dst16_32_16_absolute_QI, { 0xa0ef0000 } + }, +/* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (DSP_16_U16), ',', OP (DSP_32_U16), 0 } }, + & ifmt_xor16_b_16_16_32_src16_16_16_absolute_QI_dst16_32_16_absolute_QI, { 0xa0ff0000 } + }, +/* add.b${G} $Src16RnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_Rn_direct_QI, { 0xa000 } + }, +/* add.b${G} $Src16AnQI,$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_Rn_direct_QI, { 0xa040 } + }, +/* add.b${G} [$Src16An],$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_Rn_direct_QI, { 0xa060 } + }, +/* add.b${G} $Src16RnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_direct_QI, { 0xa004 } + }, +/* add.b${G} $Src16AnQI,$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_direct_QI, { 0xa044 } + }, +/* add.b${G} [$Src16An],$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_direct_QI, { 0xa064 } + }, +/* add.b${G} $Src16RnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_An_indirect_QI, { 0xa006 } + }, +/* add.b${G} $Src16AnQI,[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_An_indirect_QI, { 0xa046 } + }, +/* add.b${G} [$Src16An],[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_An_indirect_QI, { 0xa066 } + }, +/* add.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_An_relative_QI, { 0xa00800 } + }, +/* add.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_An_relative_QI, { 0xa04800 } + }, +/* add.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_An_relative_QI, { 0xa06800 } + }, +/* add.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_An_relative_QI, { 0xa00c0000 } + }, +/* add.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_An_relative_QI, { 0xa04c0000 } + }, +/* add.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_An_relative_QI, { 0xa06c0000 } + }, +/* add.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_SB_relative_QI, { 0xa00a00 } + }, +/* add.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_SB_relative_QI, { 0xa04a00 } + }, +/* add.b${G} [$Src16An],${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_SB_relative_QI, { 0xa06a00 } + }, +/* add.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_SB_relative_QI, { 0xa00e0000 } + }, +/* add.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_SB_relative_QI, { 0xa04e0000 } + }, +/* add.b${G} [$Src16An],${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_SB_relative_QI, { 0xa06e0000 } + }, +/* add.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_8_FB_relative_QI, { 0xa00b00 } + }, +/* add.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_8_FB_relative_QI, { 0xa04b00 } + }, +/* add.b${G} [$Src16An],${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_8_FB_relative_QI, { 0xa06b00 } + }, +/* add.b${G} $Src16RnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16RNQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_Rn_direct_QI_dst16_16_16_absolute_QI, { 0xa00f0000 } + }, +/* add.b${G} $Src16AnQI,${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', OP (SRC16ANQI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_direct_QI_dst16_16_16_absolute_QI, { 0xa04f0000 } + }, +/* add.b${G} [$Src16An],${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '[', OP (SRC16AN), ']', ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_basic_16_src16_An_indirect_QI_dst16_16_16_absolute_QI, { 0xa06f0000 } + }, +/* add.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0x8400 } + }, +/* add.b${S} #${Imm-8-QI},r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0x8300 } + }, +/* add.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0x850000 } + }, +/* add.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0x860000 } + }, +/* add.b${S} #${Imm-8-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0x87000000 } + }, +/* add.l${Q} #${Imm-12-s4},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0xf830 } + }, +/* add.l${Q} #${Imm-12-s4},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0xf0b0 } + }, +/* add.l${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0xf030 } + }, +/* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0xf23000 } + }, +/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0xf4300000 } + }, +/* add.l${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0xf6300000 } + }, +/* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0xf2b000 } + }, +/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0xf4b00000 } + }, +/* add.l${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0xf2f000 } + }, +/* add.l${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0xf4f00000 } + }, +/* add.l${Q} #${Imm-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0xf6f00000 } + }, +/* add.l${Q} #${Imm-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_add32_l_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0xf6b00000 } + }, +/* add.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0xe930 } + }, +/* add.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0xe1b0 } + }, +/* add.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0xe130 } + }, +/* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0xe33000 } + }, +/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0xe5300000 } + }, +/* add.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0xe7300000 } + }, +/* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0xe3b000 } + }, +/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0xe5b00000 } + }, +/* add.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0xe3f000 } + }, +/* add.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0xe5f00000 } + }, +/* add.w${Q} #${Imm-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0xe7f00000 } + }, +/* add.w${Q} #${Imm-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_w_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0xe7b00000 } + }, +/* add.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0xe830 } + }, +/* add.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0xe0b0 } + }, +/* add.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0xe030 } + }, +/* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0xe23000 } + }, +/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0xe4300000 } + }, +/* add.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0xe6300000 } + }, +/* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0xe2b000 } + }, +/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0xe4b00000 } + }, +/* add.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0xe2f000 } + }, +/* add.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0xe4f00000 } + }, +/* add.b${Q} #${Imm-12-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0xe6f00000 } + }, +/* add.b${Q} #${Imm-12-s4},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_12_S4), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_b_imm4_Q_16_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0xe6b00000 } + }, +/* add.w${Q} #${Imm-8-s4},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNHI), 0 } }, + & ifmt_cmp16_w_imm4_Q_16_dst16_Rn_direct_HI, { 0xc900 } + }, +/* add.w${Q} #${Imm-8-s4},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANHI), 0 } }, + & ifmt_cmp16_w_imm4_Q_16_dst16_An_direct_HI, { 0xc904 } + }, +/* add.w${Q} #${Imm-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_cmp16_w_imm4_Q_16_dst16_An_indirect_HI, { 0xc906 } + }, +/* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_cmp16_w_imm4_Q_16_dst16_16_8_An_relative_HI, { 0xc90800 } + }, +/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_cmp16_w_imm4_Q_16_dst16_16_16_An_relative_HI, { 0xc90c0000 } + }, +/* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_cmp16_w_imm4_Q_16_dst16_16_8_SB_relative_HI, { 0xc90a00 } + }, +/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_cmp16_w_imm4_Q_16_dst16_16_16_SB_relative_HI, { 0xc90e0000 } + }, +/* add.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_cmp16_w_imm4_Q_16_dst16_16_8_FB_relative_HI, { 0xc90b00 } + }, +/* add.w${Q} #${Imm-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_cmp16_w_imm4_Q_16_dst16_16_16_absolute_HI, { 0xc90f0000 } + }, +/* add.b${Q} #${Imm-8-s4},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16RNQI), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_Rn_direct_QI, { 0xc800 } + }, +/* add.b${Q} #${Imm-8-s4},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DST16ANQI), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_An_direct_QI, { 0xc804 } + }, +/* add.b${Q} #${Imm-8-s4},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_An_indirect_QI, { 0xc806 } + }, +/* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_An_relative_QI, { 0xc80800 } + }, +/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_An_relative_QI, { 0xc80c0000 } + }, +/* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_SB_relative_QI, { 0xc80a00 } + }, +/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_SB_relative_QI, { 0xc80e0000 } + }, +/* add.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_8_FB_relative_QI, { 0xc80b00 } + }, +/* add.b${Q} #${Imm-8-s4},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_QI, { 0xc80f0000 } + }, +/* add.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_HI, { 0x892e0000 } + }, +/* add.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_HI, { 0x81ae0000 } + }, +/* add.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_HI, { 0x812e0000 } + }, +/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_HI, { 0x832e0000 } + }, +/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_HI, { 0x83ae0000 } + }, +/* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_HI, { 0x83ee0000 } + }, +/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_HI, { 0x852e0000 } + }, +/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_HI, { 0x85ae0000 } + }, +/* add.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_HI, { 0x85ee0000 } + }, +/* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_w_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_HI, { 0x87ee0000 } + }, +/* add.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_HI, { 0x872e0000 } + }, +/* add.w${G} #${Imm-40-HI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_HI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_w_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_HI, { 0x87ae0000 } + }, +/* add.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_QI, { 0x882e00 } + }, +/* add.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_QI, { 0x80ae00 } + }, +/* add.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_QI, { 0x802e00 } + }, +/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_QI, { 0x822e0000 } + }, +/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_QI, { 0x82ae0000 } + }, +/* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_QI, { 0x82ee0000 } + }, +/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_QI, { 0x842e0000 } + }, +/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_QI, { 0x84ae0000 } + }, +/* add.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_QI, { 0x84ee0000 } + }, +/* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor32_b_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_QI, { 0x86ee0000 } + }, +/* add.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_QI, { 0x862e0000 } + }, +/* add.b${G} #${Imm-40-QI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_QI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_xor32_b_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_QI, { 0x86ae0000 } + }, +/* add.w${G} #${Imm-16-HI},$Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16RNHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_Rn_direct_HI, { 0x77400000 } + }, +/* add.w${G} #${Imm-16-HI},$Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', OP (DST16ANHI), 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_direct_HI, { 0x77440000 } + }, +/* add.w${G} #${Imm-16-HI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_basic_dst16_An_indirect_HI, { 0x77460000 } + }, +/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_An_relative_HI, { 0x77480000 } + }, +/* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_SB_relative_HI, { 0x774a0000 } + }, +/* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_8_dst16_16_8_FB_relative_HI, { 0x774b0000 } + }, +/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_An_relative_HI, { 0x774c0000 } + }, +/* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_SB_relative_HI, { 0x774e0000 } + }, +/* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_HI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_w_imm_G_16_16_dst16_16_16_absolute_HI, { 0x774f0000 } + }, +/* add.b${G} #${Imm-16-QI},$Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16RNQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_Rn_direct_QI, { 0x764000 } + }, +/* add.b${G} #${Imm-16-QI},$Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', OP (DST16ANQI), 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_direct_QI, { 0x764400 } + }, +/* add.b${G} #${Imm-16-QI},[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_basic_dst16_An_indirect_QI, { 0x764600 } + }, +/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_An_relative_QI, { 0x76480000 } + }, +/* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_SB_relative_QI, { 0x764a0000 } + }, +/* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_8_dst16_16_8_FB_relative_QI, { 0x764b0000 } + }, +/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_An_relative_QI, { 0x764c0000 } + }, +/* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_SB_relative_QI, { 0x764e0000 } + }, +/* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_xor16_b_imm_G_16_16_dst16_16_16_absolute_QI, { 0x764f0000 } + }, +/* add.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32RNUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_Rn_direct_Unprefixed_SI, { 0x88310000 } + }, +/* add.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', OP (DST32ANUNPREFIXEDSI), 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_direct_Unprefixed_SI, { 0x80b10000 } + }, +/* add.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_SI), ',', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_basic_Unprefixed_dst32_An_indirect_Unprefixed_SI, { 0x80310000 } + }, +/* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_An_relative_Unprefixed_SI, { 0x82310000 } + }, +/* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_SB_relative_Unprefixed_SI, { 0x82b10000 } + }, +/* add.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_24_SI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_8_Unprefixed_dst32_16_8_FB_relative_Unprefixed_SI, { 0x82f10000 } + }, +/* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_An_relative_Unprefixed_SI, { 0x84310000 } + }, +/* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_SB_relative_Unprefixed_SI, { 0x84b10000 } + }, +/* add.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_FB_relative_Unprefixed_SI, { 0x84f10000 } + }, +/* add.l${G} #${Imm-32-SI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_32_SI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_mov32_l_imm_G_16_16_Unprefixed_dst32_16_16_absolute_Unprefixed_SI, { 0x86f10000 } + }, +/* add.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_An_relative_Unprefixed_SI, { 0x86310000 } + }, +/* add.l${G} #${Imm-40-SI},${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_40_SI), ',', OP (DSP_16_U24), 0 } }, + & ifmt_mov32_l_imm_G_16_24_Unprefixed_dst32_16_24_absolute_Unprefixed_SI, { 0x86b10000 } + }, +/* adcf.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xb91e } + }, +/* adcf.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xb19e } + }, +/* adcf.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xb11e } + }, +/* adcf.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xb31e00 } + }, +/* adcf.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xb51e0000 } + }, +/* adcf.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xb71e0000 } + }, +/* adcf.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xb39e00 } + }, +/* adcf.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xb59e0000 } + }, +/* adcf.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xb3de00 } + }, +/* adcf.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xb5de0000 } + }, +/* adcf.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xb7de0000 } + }, +/* adcf.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xb79e0000 } + }, +/* adcf.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xb81e } + }, +/* adcf.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xb09e } + }, +/* adcf.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xb01e } + }, +/* adcf.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xb21e00 } + }, +/* adcf.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xb41e0000 } + }, +/* adcf.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xb61e0000 } + }, +/* adcf.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xb29e00 } + }, +/* adcf.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xb49e0000 } + }, +/* adcf.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xb2de00 } + }, +/* adcf.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xb4de0000 } + }, +/* adcf.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xb6de0000 } + }, +/* adcf.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xb69e0000 } + }, +/* adcf.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77e0 } + }, +/* adcf.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77e4 } + }, +/* adcf.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77e6 } + }, +/* adcf.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77e800 } + }, +/* adcf.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77ec0000 } + }, +/* adcf.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77ea00 } + }, +/* adcf.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77ee0000 } + }, +/* adcf.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77eb00 } + }, +/* adcf.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77ef0000 } + }, +/* adcf.b $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76e0 } + }, +/* adcf.b $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76e4 } + }, +/* adcf.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76e6 } + }, +/* adcf.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76e800 } + }, +/* adcf.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76ec0000 } + }, +/* adcf.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76ea00 } + }, +/* adcf.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76ee0000 } + }, +/* adcf.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76eb00 } + }, +/* adcf.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76ef0000 } + }, +/* abs.w $Dst32RnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDHI), 0 } }, + & ifmt_shl32_w_dst_dst32_Rn_direct_Unprefixed_HI, { 0xa91f } + }, +/* abs.w $Dst32AnUnprefixedHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDHI), 0 } }, + & ifmt_exts32_b_16_ExtUnprefixed_dst32_An_direct_Unprefixed_HI, { 0xa19f } + }, +/* abs.w [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_An_indirect_Unprefixed_HI, { 0xa11f } + }, +/* abs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_An_relative_Unprefixed_HI, { 0xa31f00 } + }, +/* abs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_An_relative_Unprefixed_HI, { 0xa51f0000 } + }, +/* abs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_An_relative_Unprefixed_HI, { 0xa71f0000 } + }, +/* abs.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_SB_relative_Unprefixed_HI, { 0xa39f00 } + }, +/* abs.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_SB_relative_Unprefixed_HI, { 0xa59f0000 } + }, +/* abs.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_8_FB_relative_Unprefixed_HI, { 0xa3df00 } + }, +/* abs.w ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_FB_relative_Unprefixed_HI, { 0xa5df0000 } + }, +/* abs.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_w_dst_dst32_16_16_absolute_Unprefixed_HI, { 0xa7df0000 } + }, +/* abs.w ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_w_dst_dst32_16_24_absolute_Unprefixed_HI, { 0xa79f0000 } + }, +/* abs.b $Dst32RnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32RNUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_Rn_direct_Unprefixed_QI, { 0xa81f } + }, +/* abs.b $Dst32AnUnprefixedQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST32ANUNPREFIXEDQI), 0 } }, + & ifmt_shl32_b_dst_dst32_An_direct_Unprefixed_QI, { 0xa09f } + }, +/* abs.b [$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_An_indirect_Unprefixed_QI, { 0xa01f } + }, +/* abs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_An_relative_Unprefixed_QI, { 0xa21f00 } + }, +/* abs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_An_relative_Unprefixed_QI, { 0xa41f0000 } + }, +/* abs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), '[', OP (DST32ANUNPREFIXED), ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_An_relative_Unprefixed_QI, { 0xa61f0000 } + }, +/* abs.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_SB_relative_Unprefixed_QI, { 0xa29f00 } + }, +/* abs.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_SB_relative_Unprefixed_QI, { 0xa49f0000 } + }, +/* abs.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_8_FB_relative_Unprefixed_QI, { 0xa2df00 } + }, +/* abs.b ${Dsp-16-s16}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S16), '[', 'f', 'b', ']', 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_FB_relative_Unprefixed_QI, { 0xa4df0000 } + }, +/* abs.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_shl32_b_dst_dst32_16_16_absolute_Unprefixed_QI, { 0xa6df0000 } + }, +/* abs.b ${Dsp-16-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U24), 0 } }, + & ifmt_shl32_b_dst_dst32_16_24_absolute_Unprefixed_QI, { 0xa69f0000 } + }, +/* abs.w $Dst16RnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNHI), 0 } }, + & ifmt_rorc16_w_16_dst16_Rn_direct_HI, { 0x77f0 } + }, +/* abs.w $Dst16AnHI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANHI), 0 } }, + & ifmt_rorc16_w_16_dst16_An_direct_HI, { 0x77f4 } + }, +/* abs.w [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_An_indirect_HI, { 0x77f6 } + }, +/* abs.w ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_An_relative_HI, { 0x77f800 } + }, +/* abs.w ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_An_relative_HI, { 0x77fc0000 } + }, +/* abs.w ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_SB_relative_HI, { 0x77fa00 } + }, +/* abs.w ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_SB_relative_HI, { 0x77fe0000 } + }, +/* abs.w ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_w_16_dst16_16_8_FB_relative_HI, { 0x77fb00 } + }, +/* abs.w ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_w_16_dst16_16_16_absolute_HI, { 0x77ff0000 } + }, +/* abs.b $Dst16RnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16RNQI), 0 } }, + & ifmt_rorc16_b_16_dst16_Rn_direct_QI, { 0x76f0 } + }, +/* abs.b $Dst16AnQI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16ANQI), 0 } }, + & ifmt_rorc16_b_16_dst16_An_direct_QI, { 0x76f4 } + }, +/* abs.b [$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_An_indirect_QI, { 0x76f6 } + }, +/* abs.b ${Dsp-16-u8}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_An_relative_QI, { 0x76f800 } + }, +/* abs.b ${Dsp-16-u16}[$Dst16An] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', OP (DST16AN), ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_An_relative_QI, { 0x76fc0000 } + }, +/* abs.b ${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_SB_relative_QI, { 0x76fa00 } + }, +/* abs.b ${Dsp-16-u16}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), '[', 's', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_SB_relative_QI, { 0x76fe0000 } + }, +/* abs.b ${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_rorc16_b_16_dst16_16_8_FB_relative_QI, { 0x76fb00 } + }, +/* abs.b ${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), 0 } }, + & ifmt_rorc16_b_16_dst16_16_16_absolute_QI, { 0x76ff0000 } + }, +/* add${size}$Q #${Imm-12-s4},sp */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (SIZE), OP (Q), ' ', '#', OP (IMM_12_S4), ',', 's', 'p', 0 } }, + & ifmt_add16_Q_sp, { 0x7db0 } + }, +/* add.b$G #${Imm-16-QI},sp */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), ',', 's', 'p', 0 } }, + & ifmt_add16_b_G_sp, { 0x7ceb00 } + }, +/* add.w$G #${Imm-16-HI},sp */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', 's', 'p', 0 } }, + & ifmt_add16_w_G_sp, { 0x7deb0000 } + }, +/* add.l$Q #${Imm3-S},sp */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (Q), ' ', '#', OP (IMM3_S), ',', 's', 'p', 0 } }, + & ifmt_add32_l_imm3_Q, { 0x42 } + }, +/* add.l$S #${Imm-16-QI},sp */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', 's', 'p', 0 } }, + & ifmt_add32_l_imm8_S, { 0xb60300 } + }, +/* add.l$G #${Imm-16-HI},sp */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), ',', 's', 'p', 0 } }, + & ifmt_add32_l_imm16_G, { 0xb6130000 } + }, +/* dadc.b #${Imm-16-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } }, + & ifmt_add32_l_imm8_S, { 0x7cee00 } + }, +/* dadc.w #${Imm-16-HI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } }, + & ifmt_add32_l_imm16_G, { 0x7dee0000 } + }, +/* dadc.b r0h,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', 'r', '0', 'l', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7ce6 } + }, +/* dadc.w r1,r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', 'r', '0', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7de6 } + }, +/* dadd.b #${Imm-16-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } }, + & ifmt_add32_l_imm8_S, { 0x7cec00 } + }, +/* dadd.w #${Imm-16-HI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } }, + & ifmt_add32_l_imm16_G, { 0x7dec0000 } + }, +/* dadd.b r0h,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', 'r', '0', 'l', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7ce4 } + }, +/* dadd.w r1,r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', 'r', '0', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7de4 } + }, +/* bm$cond16c c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16C), ' ', 'c', 0 } }, + & ifmt_bm16_c, { 0x7dd0 } + }, +/* bm$cond32 c */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32), ' ', 'c', 0 } }, + & ifmt_bm32_c, { 0xd928 } + }, +/* brk */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0x0 } + }, +/* brk */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0x0 } + }, +/* brk2 */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0x8 } + }, +/* dec.w ${Dst16An-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16AN_S), 0 } }, + & ifmt_dec16_w, { 0xf2 } + }, +/* div.b #${Imm-16-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } }, + & ifmt_add16_b_G_sp, { 0x7ce100 } + }, +/* div.w #${Imm-16-HI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } }, + & ifmt_add16_w_G_sp, { 0x7de10000 } + }, +/* div.b #${Imm-16-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } }, + & ifmt_div32_b_Imm_16_QI, { 0xb04300 } + }, +/* div.w #${Imm-16-HI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } }, + & ifmt_div32_w_Imm_16_HI, { 0xb0530000 } + }, +/* divu.b #${Imm-16-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } }, + & ifmt_add16_b_G_sp, { 0x7ce000 } + }, +/* divu.w #${Imm-16-HI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } }, + & ifmt_add16_w_G_sp, { 0x7de00000 } + }, +/* divu.b #${Imm-16-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } }, + & ifmt_div32_b_Imm_16_QI, { 0xb00300 } + }, +/* divu.w #${Imm-16-HI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } }, + & ifmt_div32_w_Imm_16_HI, { 0xb0130000 } + }, +/* divx.b #${Imm-16-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } }, + & ifmt_add16_b_G_sp, { 0x7ce300 } + }, +/* divx.w #${Imm-16-HI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } }, + & ifmt_add16_w_G_sp, { 0x7de30000 } + }, +/* divx.b #${Imm-16-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } }, + & ifmt_div32_b_Imm_16_QI, { 0xb24300 } + }, +/* divx.w #${Imm-16-HI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } }, + & ifmt_div32_w_Imm_16_HI, { 0xb2530000 } + }, +/* dsbb.b #${Imm-16-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } }, + & ifmt_add32_l_imm8_S, { 0x7cef00 } + }, +/* dsbb.w #${Imm-16-HI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } }, + & ifmt_add32_l_imm16_G, { 0x7def0000 } + }, +/* dsbb.b r0h,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', 'r', '0', 'l', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7ce7 } + }, +/* dsbb.w r1,r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', 'r', '0', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7de7 } + }, +/* dsub.b #${Imm-16-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_QI), 0 } }, + & ifmt_add32_l_imm8_S, { 0x7ced00 } + }, +/* dsub.w #${Imm-16-HI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), 0 } }, + & ifmt_add32_l_imm16_G, { 0x7ded0000 } + }, +/* dsub.b r0h,r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 'h', ',', 'r', '0', 'l', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7ce5 } + }, +/* dsub.w r1,r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', ',', 'r', '0', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7de5 } + }, +/* enter #${Dsp-16-u8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (DSP_16_U8), 0 } }, + & ifmt_enter16, { 0x7cf200 } + }, +/* exitd */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7df2 } + }, +/* enter #${Dsp-8-u8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (DSP_8_U8), 0 } }, + & ifmt_enter32, { 0xec00 } + }, +/* exitd */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0xfc } + }, +/* fclr ${flags16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FLAGS16), 0 } }, + & ifmt_fclr16, { 0xeb05 } + }, +/* fset ${flags16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FLAGS16), 0 } }, + & ifmt_fclr16, { 0xeb04 } + }, +/* fclr ${flags32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FLAGS32), 0 } }, + & ifmt_fclr, { 0xd3e8 } + }, +/* fset ${flags32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FLAGS32), 0 } }, + & ifmt_fclr, { 0xd1e8 } + }, +/* inc.w ${Dst16An-S} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DST16AN_S), 0 } }, + & ifmt_dec16_w, { 0xb2 } + }, +/* freit */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0x9f } + }, +/* int #${Dsp-10-u6} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (DSP_10_U6), 0 } }, + & ifmt_int16, { 0xebc0 } + }, +/* into */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0xf6 } + }, +/* int #${Dsp-8-u6} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (DSP_8_U6), 0 } }, + & ifmt_int32, { 0xbe00 } + }, +/* into */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0xbf } + }, +/* j$cond16j5 ${Lab-8-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16J5), ' ', OP (LAB_8_8), 0 } }, + & ifmt_jcnd16_5, { 0x6800 } + }, +/* j$cond16j ${Lab-16-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND16J), ' ', OP (LAB_16_8), 0 } }, + & ifmt_jcnd16, { 0x7dc000 } + }, +/* j$cond32j ${Lab-8-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (COND32J), ' ', OP (LAB_8_8), 0 } }, + & ifmt_jcnd32, { 0x8a00 } + }, +/* jmp.s ${Lab-5-3} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_5_3), 0 } }, + & ifmt_jmp16_s, { 0x60 } + }, +/* jmp.b ${Lab-8-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_8_8), 0 } }, + & ifmt_jmp16_b, { 0xfe00 } + }, +/* jmp.w ${Lab-8-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_8_16), 0 } }, + & ifmt_jmp16_w, { 0xf40000 } + }, +/* jmp.a ${Lab-8-24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_8_24), 0 } }, + & ifmt_jmp16_a, { 0xfc000000 } + }, +/* jmps #${Imm-8-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } }, + & ifmt_jmps16, { 0xee00 } + }, +/* jmp.s ${Lab32-jmp-s} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB32_JMP_S), 0 } }, + & ifmt_jmp32_s, { 0x4a } + }, +/* jmp.b ${Lab-8-8} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_8_8), 0 } }, + & ifmt_jmp16_b, { 0xbb00 } + }, +/* jmp.w ${Lab-8-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_8_16), 0 } }, + & ifmt_jmp16_w, { 0xce0000 } + }, +/* jmp.a ${Lab-8-24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_8_24), 0 } }, + & ifmt_jmp16_a, { 0xcc000000 } + }, +/* jmps #${Imm-8-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } }, + & ifmt_jmps16, { 0xdc00 } + }, +/* jsr.w ${Lab-8-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_8_16), 0 } }, + & ifmt_jmp16_w, { 0xf50000 } + }, +/* jsr.a ${Lab-8-24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_8_24), 0 } }, + & ifmt_jmp16_a, { 0xfd000000 } + }, +/* jsr.w ${Lab-8-16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_8_16), 0 } }, + & ifmt_jmp16_w, { 0xcf0000 } + }, +/* jsr.a ${Lab-8-24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (LAB_8_24), 0 } }, + & ifmt_jmp16_a, { 0xcd000000 } + }, +/* jsrs #${Imm-8-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } }, + & ifmt_jmps16, { 0xef00 } + }, +/* jsrs #${Imm-8-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_QI), 0 } }, + & ifmt_jmps16, { 0xdd00 } + }, +/* ldc #${Imm-16-HI},${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), ',', OP (CR16), 0 } }, + & ifmt_ldc16_imm16, { 0xeb000000 } + }, +/* ldc #${Imm-16-HI},${cr1-Unprefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_HI), ',', OP (CR1_UNPREFIXED_32), 0 } }, + & ifmt_ldc32_imm16_cr1, { 0xd5a80000 } + }, +/* ldc #${Dsp-16-u24},${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (DSP_16_U24), ',', OP (CR2_32), 0 } }, + & ifmt_ldc32_imm16_cr2, { 0xd5280000 } + }, +/* ldc #${Dsp-16-u24},${cr3-Unprefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (DSP_16_U24), ',', OP (CR3_UNPREFIXED_32), 0 } }, + & ifmt_ldc32_imm16_cr3, { 0xd5680000 } + }, +/* ldctx ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_ldctx16, { 0x7cf00000 } + }, +/* ldctx ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_ldctx16, { 0xb6c30000 } + }, +/* stctx ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_ldctx16, { 0x7df00000 } + }, +/* stctx ${Dsp-16-u16},${Dsp-32-u24} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (DSP_16_U16), ',', OP (DSP_32_U24), 0 } }, + & ifmt_ldctx16, { 0xb6d30000 } + }, +/* ldipl #${Imm-13-u3} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_13_U3), 0 } }, + & ifmt_ldipl16_imm, { 0x7da0 } + }, +/* ldipl #${Imm-13-u3} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_13_U3), 0 } }, + & ifmt_ldipl16_imm, { 0xd5e8 } + }, +/* mov.b$S #${Imm-8-QI},a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'a', '0', 0 } }, + & ifmt_jmps16, { 0xe200 } + }, +/* mov.b$S #${Imm-8-QI},a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'a', '1', 0 } }, + & ifmt_jmps16, { 0xea00 } + }, +/* mov.w$S #${Imm-8-HI},a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '0', 0 } }, + & ifmt_mov16_w_S_imm_a0, { 0xa20000 } + }, +/* mov.w$S #${Imm-8-HI},a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '1', 0 } }, + & ifmt_mov16_w_S_imm_a0, { 0xaa0000 } + }, +/* mov.w$S #${Imm-8-HI},a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '0', 0 } }, + & ifmt_mov16_w_S_imm_a0, { 0x9c0000 } + }, +/* mov.w$S #${Imm-8-HI},a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '1', 0 } }, + & ifmt_mov16_w_S_imm_a0, { 0x9d0000 } + }, +/* mov.l$S #${Dsp-8-u24},a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (DSP_8_U24), ',', 'a', '0', 0 } }, + & ifmt_mov32_l_a0, { 0xbc000000 } + }, +/* mov.l$S #${Dsp-8-u24},a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (DSP_8_U24), ',', 'a', '1', 0 } }, + & ifmt_mov32_l_a0, { 0xbd000000 } + }, +/* mov.b$S r0l,a1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', 'r', '0', 'l', ',', 'a', '1', 0 } }, + & ifmt_brk16, { 0x34 } + }, +/* mov.b$S r0h,a0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', 'r', '0', 'h', ',', 'a', '0', 0 } }, + & ifmt_brk16, { 0x30 } + }, +/* nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0x4 } + }, +/* nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0xde } + }, +/* popc ${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), 0 } }, + & ifmt_popc16_imm16, { 0xeb03 } + }, +/* popc ${cr1-Unprefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_UNPREFIXED_32), 0 } }, + & ifmt_popc32_imm16_cr1, { 0xd3a8 } + }, +/* popc ${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), 0 } }, + & ifmt_popc32_imm16_cr2, { 0xd328 } + }, +/* pushc ${cr16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR16), 0 } }, + & ifmt_popc16_imm16, { 0xeb02 } + }, +/* pushc ${cr1-Unprefixed-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR1_UNPREFIXED_32), 0 } }, + & ifmt_popc32_imm16_cr1, { 0xd1a8 } + }, +/* pushc ${cr2-32} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (CR2_32), 0 } }, + & ifmt_popc32_imm16_cr2, { 0xd128 } + }, +/* popm ${Regsetpop} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGSETPOP), 0 } }, + & ifmt_popm16, { 0xed00 } + }, +/* pushm ${Regsetpush} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGSETPUSH), 0 } }, + & ifmt_pushm16, { 0xec00 } + }, +/* popm ${Regsetpop} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGSETPOP), 0 } }, + & ifmt_popm16, { 0x8e00 } + }, +/* pushm ${Regsetpush} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (REGSETPUSH), 0 } }, + & ifmt_pushm16, { 0x8f00 } + }, +/* push.b$G #${Imm-16-QI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_QI), 0 } }, + & ifmt_add32_l_imm8_S, { 0x7ce200 } + }, +/* push.w$G #${Imm-16-HI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (G), ' ', '#', OP (IMM_16_HI), 0 } }, + & ifmt_add32_l_imm16_G, { 0x7de20000 } + }, +/* push.b #Imm-8-QI */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', 'I', 'm', 'm', '-', '8', '-', 'Q', 'I', 0 } }, + & ifmt_jmps16, { 0xae00 } + }, +/* push.w #${Imm-8-HI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_HI), 0 } }, + & ifmt_mov16_w_S_imm_a0, { 0xaf0000 } + }, +/* push.l #${Imm-16-SI} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_16_SI), 0 } }, + & ifmt_push32_l_imm, { 0xb6530000 } + }, +/* reit */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0xfb } + }, +/* reit */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0x9e } + }, +/* rmpa.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7cf1 } + }, +/* rmpa.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7df1 } + }, +/* rmpa.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb843 } + }, +/* rmpa.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb853 } + }, +/* rts */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0xf3 } + }, +/* rts */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0xdf } + }, +/* scmpu.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb8c3 } + }, +/* scmpu.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb8d3 } + }, +/* sha.l #${Imm-sh-12-s4},r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_SH_12_S4), ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_sha16_L_imm_r2r0, { 0xeba0 } + }, +/* sha.l #${Imm-sh-12-s4},r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_SH_12_S4), ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_sha16_L_imm_r2r0, { 0xebb0 } + }, +/* sha.l r1h,r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xeb21 } + }, +/* sha.l r1h,r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xeb31 } + }, +/* shl.l #${Imm-sh-12-s4},r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_SH_12_S4), ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_sha16_L_imm_r2r0, { 0xeb80 } + }, +/* shl.l #${Imm-sh-12-s4},r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_SH_12_S4), ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_sha16_L_imm_r2r0, { 0xeb90 } + }, +/* shl.l r1h,r2r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', 'r', '2', 'r', '0', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xeb01 } + }, +/* shl.l r1h,r3r1 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '1', 'h', ',', 'r', '3', 'r', '1', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xeb11 } + }, +/* sin.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb283 } + }, +/* sin.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb293 } + }, +/* smovb.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7ce9 } + }, +/* smovb.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7de9 } + }, +/* smovb.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb683 } + }, +/* smovb.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb693 } + }, +/* smovf.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7ce8 } + }, +/* smovf.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7de8 } + }, +/* smovf.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb083 } + }, +/* smovf.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb093 } + }, +/* smovu.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb883 } + }, +/* smovu.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb893 } + }, +/* sout.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb483 } + }, +/* sout.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb493 } + }, +/* sstr.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7cea } + }, +/* sstr.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7dea } + }, +/* sstr.b */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb803 } + }, +/* sstr.w */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb813 } + }, +/* stzx #${Imm-8-QI},#${Imm-16-QI},r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_16_QI), ',', 'r', '0', 'h', 0 } }, + & ifmt_stzx16_imm8_imm8_r0h, { 0xdb0000 } + }, +/* stzx #${Imm-8-QI},#${Imm-16-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_16_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_stzx16_imm8_imm8_r0h, { 0xdc0000 } + }, +/* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_16_QI), ',', 'D', 's', 'p', '-', '2', '4', '-', 'u', '8', '[', 's', 'b', ']', 0 } }, + & ifmt_stzx16_imm8_imm8_dsp8sb, { 0xdd000000 } + }, +/* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_16_QI), ',', 'D', 's', 'p', '-', '2', '4', '-', 'u', '8', '[', 'f', 'b', ']', 0 } }, + & ifmt_stzx16_imm8_imm8_dsp8sb, { 0xde000000 } + }, +/* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (IMM_8_QI), ',', '#', OP (IMM_16_QI), ',', 'D', 's', 'p', '-', '2', '4', '-', 'u', '1', '6', 0 } }, + & ifmt_stzx16_imm8_imm8_abs16, { 0xde000000 } + }, +/* und */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0xff } + }, +/* und */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0xff } + }, +/* wait */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7df3 } + }, +/* wait */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0xb203 } + }, +/* exts.w r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'r', '0', 0 } }, + & ifmt_dadc16_b_r0h_r0l, { 0x7cf3 } + }, +/* src-indirect */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0x41 } + }, +/* dest-indirect */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0x9 } + }, +/* src-dest-indirect */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_brk16, { 0x49 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & m32c_cgen_ifld_table[M32C_##f] +#else +#define F(f) & m32c_cgen_ifld_table[M32C_/**/f] +#endif +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) M32C_OPERAND_##op +#else +#define OPERAND(op) M32C_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE m32c_cgen_macro_insn_table[] = +{ +}; + +/* The macro instruction opcode table. */ + +static const CGEN_OPCODE m32c_cgen_macro_insn_opcode_table[] = +{ +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +#ifndef CGEN_ASM_HASH_P +#define CGEN_ASM_HASH_P(insn) 1 +#endif + +#ifndef CGEN_DIS_HASH_P +#define CGEN_DIS_HASH_P(insn) 1 +#endif + +/* Return non-zero if INSN is to be added to the hash table. + Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ + +static int +asm_hash_insn_p (insn) + const CGEN_INSN *insn ATTRIBUTE_UNUSED; +{ + return CGEN_ASM_HASH_P (insn); +} + +static int +dis_hash_insn_p (insn) + const CGEN_INSN *insn; +{ + /* If building the hash table and the NO-DIS attribute is present, + ignore. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS)) + return 0; + return CGEN_DIS_HASH_P (insn); +} + +#ifndef CGEN_ASM_HASH +#define CGEN_ASM_HASH_SIZE 127 +#ifdef CGEN_MNEMONIC_OPERANDS +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) +#else +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/ +#endif +#endif + +/* It doesn't make much sense to provide a default here, + but while this is under development we do. + BUFFER is a pointer to the bytes of the insn, target order. + VALUE is the first base_insn_bitsize bits as an int in host order. */ + +#ifndef CGEN_DIS_HASH +#define CGEN_DIS_HASH_SIZE 256 +#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf)) +#endif + +/* The result is the hash value of the insn. + Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ + +static unsigned int +asm_hash_insn (mnem) + const char * mnem; +{ + return CGEN_ASM_HASH (mnem); +} + +/* BUF is a pointer to the bytes of the insn, target order. + VALUE is the first base_insn_bitsize bits as an int in host order. */ + +static unsigned int +dis_hash_insn (buf, value) + const char * buf ATTRIBUTE_UNUSED; + CGEN_INSN_INT value ATTRIBUTE_UNUSED; +{ + return CGEN_DIS_HASH (buf, value); +} + +/* Set the recorded length of the insn in the CGEN_FIELDS struct. */ + +static void +set_fields_bitsize (CGEN_FIELDS *fields, int size) +{ + CGEN_FIELDS_BITSIZE (fields) = size; +} + +/* Function to call before using the operand instance table. + This plugs the opcode entries and macro instructions into the cpu table. */ + +void +m32c_cgen_init_opcode_table (CGEN_CPU_DESC cd) +{ + int i; + int num_macros = (sizeof (m32c_cgen_macro_insn_table) / + sizeof (m32c_cgen_macro_insn_table[0])); + const CGEN_IBASE *ib = & m32c_cgen_macro_insn_table[0]; + const CGEN_OPCODE *oc = & m32c_cgen_macro_insn_opcode_table[0]; + CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); + + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); + for (i = 0; i < num_macros; ++i) + { + insns[i].base = &ib[i]; + insns[i].opcode = &oc[i]; + m32c_cgen_build_insn_regex (& insns[i]); + } + cd->macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & m32c_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + m32c_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff -uprN binutils-2.16.91.0.1/opcodes/m32c-opc.h binutils-2.16.91.0.2/opcodes/m32c-opc.h --- binutils-2.16.91.0.1/opcodes/m32c-opc.h 1969-12-31 16:00:00.000000000 -0800 +++ binutils-2.16.91.0.2/opcodes/m32c-opc.h 2005-07-20 12:27:29.253869729 -0700 @@ -0,0 +1,3214 @@ +/* Instruction opcode header for m32c. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996-2005 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +*/ + +#ifndef M32C_OPC_H +#define M32C_OPC_H + +/* -- opc.h */ + +/* Needed for RTL's 'ext' and 'trunc' operators. */ +#include "cgen-types.h" +#include "cgen-ops.h" + +/* We can't use the default hash size because many bits are used by + operands. */ +#define CGEN_DIS_HASH_SIZE 1 +#define CGEN_DIS_HASH(buf, value) 0 +#define CGEN_VERBOSE_ASSEMBLER_ERRORS +#define CGEN_VALIDATE_INSN_SUPPORTED + +extern int m32c_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); + +#define CGEN_ASM_HASH_SIZE 0xffff +#define CGEN_ASM_HASH(mnem) m32c_asm_hash ((mnem)) + +/* -- */ +/* Enum declaration for m32c instruction types. */ +typedef enum cgen_insn_type { + M32C_INSN_INVALID, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_HI, M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_HI + , M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI + , M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI, M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI + , M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_QI, M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_QI + , M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI + , M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI + , M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, M32C_INSN_EXTS16_B_16_EXT_DST16_RN_DIRECT_EXT_QI, M32C_INSN_EXTS16_B_16_EXT_DST16_AN_INDIRECT_EXT_QI, M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_AN_RELATIVE_EXT_QI + , M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_AN_RELATIVE_EXT_QI, M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_SB_RELATIVE_EXT_QI, M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_SB_RELATIVE_EXT_QI, M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_FB_RELATIVE_EXT_QI + , M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_ABSOLUTE_EXT_QI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI + , M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI + , M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI + , M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI + , M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI + , M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI + , M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI + , M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI + , M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI + , M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI + , M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI + , M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI + , M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI + , M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI + , M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI + , M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI + , M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI + , M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI + , M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI + , M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI + , M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI + , M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI + , M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI + , M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XCHG32W_R3_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_R3_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_R3_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R3_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R3_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R3_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R3_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R3_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R3_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R3_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R3_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R3_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R2_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_R2_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_R2_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R2_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R2_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R2_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R2_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R2_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R2_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R2_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R2_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R2_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A1_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_A1_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_A1_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_XCHG32W_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A0_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_A0_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_A0_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_XCHG32W_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R1_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_R1_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_R1_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R0_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_R0_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_XCHG32W_R0_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_XCHG32W_R0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_XCHG32W_R0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_XCHG32B_R1H_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1H_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1H_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R1H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R1H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R1H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0H_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0H_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0H_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R0H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R0H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R0H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A1_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_A1_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_A1_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_XCHG32B_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A0_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_A0_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_A0_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_XCHG32B_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1L_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1L_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1L_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R1L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R1L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R1L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R1L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0L_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0L_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0L_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R0L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R0L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_XCHG32B_R0L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_XCHG32B_R0L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_XCHG16W_R3_DST16_RN_DIRECT_HI, M32C_INSN_XCHG16W_R3_DST16_AN_DIRECT_HI, M32C_INSN_XCHG16W_R3_DST16_AN_INDIRECT_HI + , M32C_INSN_XCHG16W_R3_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R3_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R3_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R3_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_XCHG16W_R3_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XCHG16W_R3_DST16_16_16_ABSOLUTE_HI, M32C_INSN_XCHG16W_R2_DST16_RN_DIRECT_HI, M32C_INSN_XCHG16W_R2_DST16_AN_DIRECT_HI + , M32C_INSN_XCHG16W_R2_DST16_AN_INDIRECT_HI, M32C_INSN_XCHG16W_R2_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R2_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R2_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_XCHG16W_R2_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R2_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XCHG16W_R2_DST16_16_16_ABSOLUTE_HI, M32C_INSN_XCHG16W_R1_DST16_RN_DIRECT_HI + , M32C_INSN_XCHG16W_R1_DST16_AN_DIRECT_HI, M32C_INSN_XCHG16W_R1_DST16_AN_INDIRECT_HI, M32C_INSN_XCHG16W_R1_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_XCHG16W_R1_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_QI, M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI + , M32C_INSN_XCHG16B_R1H_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_XCHG16B_R1H_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XCHG16B_R1L_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R1L_DST16_AN_DIRECT_QI + , M32C_INSN_XCHG16B_R1L_DST16_AN_INDIRECT_QI, M32C_INSN_XCHG16B_R1L_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1L_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_XCHG16B_R1L_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_XCHG16B_R1L_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_XCHG16B_R1L_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XCHG16B_R0H_DST16_RN_DIRECT_QI + , M32C_INSN_XCHG16B_R0H_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16B_R0H_DST16_AN_INDIRECT_QI, M32C_INSN_XCHG16B_R0H_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R0H_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_XCHG16B_R0H_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XCHG16B_R0H_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_XCHG16B_R0H_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_XCHG16B_R0H_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_XCHG16B_R0L_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R0L_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16B_R0L_DST16_AN_INDIRECT_QI, M32C_INSN_XCHG16B_R0L_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_XCHG16B_R0L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R0L_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XCHG16B_R0L_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_XCHG16B_R0L_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_XCHG16B_R0L_DST16_16_16_ABSOLUTE_QI, M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_TST32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI + , M32C_INSN_TST32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_TST32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI + , M32C_INSN_TST32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI + , M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI + , M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI + , M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI + , M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI + , M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI + , M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI + , M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI + , M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI + , M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI + , M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI + , M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI + , M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI + , M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI + , M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI + , M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI + , M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI + , M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI + , M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI + , M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI + , M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI + , M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI + , M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_TST16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI + , M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_TST16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI + , M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI + , M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHL32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SHL32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SHL32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SHL32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHL32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHL32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHL32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHL32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHL32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHL32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHL32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHL32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHL32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_SHL32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SHL32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SHL32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SHL32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SHL32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SHL32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SHL32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_SHL32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SHL32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SHL32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SHL32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SHL32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SHL32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SHL16_W_DST_DST16_RN_DIRECT_HI + , M32C_INSN_SHL16_W_DST_DST16_AN_DIRECT_HI, M32C_INSN_SHL16_W_DST_DST16_AN_INDIRECT_HI, M32C_INSN_SHL16_W_DST_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SHL16_W_DST_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_SHL16_W_DST_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SHL16_W_DST_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SHL16_W_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SHL16_W_DST_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_SHL16_B_DST_DST16_RN_DIRECT_QI, M32C_INSN_SHL16_B_DST_DST16_AN_DIRECT_QI, M32C_INSN_SHL16_B_DST_DST16_AN_INDIRECT_QI, M32C_INSN_SHL16_B_DST_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_SHL16_B_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SHL16_B_DST_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SHL16_B_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SHL16_B_DST_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_SHL16_B_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SHL16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI + , M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SHL16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_DIRECT_QI + , M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHA32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SHA32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SHA32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SHA32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHA32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHA32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHA32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHA32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHA32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHA32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHA32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHA32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SHA32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_SHA32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SHA32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SHA32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SHA32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SHA32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SHA32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SHA32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_SHA32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SHA32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SHA32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SHA32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SHA32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SHA32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SHA16_W_DST_DST16_RN_DIRECT_HI + , M32C_INSN_SHA16_W_DST_DST16_AN_DIRECT_HI, M32C_INSN_SHA16_W_DST_DST16_AN_INDIRECT_HI, M32C_INSN_SHA16_W_DST_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SHA16_W_DST_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_SHA16_W_DST_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SHA16_W_DST_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SHA16_W_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SHA16_W_DST_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_SHA16_B_DST_DST16_RN_DIRECT_QI, M32C_INSN_SHA16_B_DST_DST16_AN_DIRECT_QI, M32C_INSN_SHA16_B_DST_DST16_AN_INDIRECT_QI, M32C_INSN_SHA16_B_DST_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_SHA16_B_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SHA16_B_DST_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SHA16_B_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SHA16_B_DST_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_SHA16_B_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SHA16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI + , M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SHA16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_DIRECT_QI + , M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SCCND_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_SCCND_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SCCND_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SCCND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SCCND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SCCND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SCCND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SCCND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SCCND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SCCND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SCCND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SCCND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI + , M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI + , M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI + , M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI + , M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI + , M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI + , M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI + , M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI + , M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI + , M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI + , M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI + , M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI + , M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI + , M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI + , M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI + , M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI + , M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI + , M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI + , M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI + , M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI + , M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI + , M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI + , M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI + , M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI + , M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI + , M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI + , M32C_INSN_ROT16_W_DST_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_HI, M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_HI + , M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_HI, M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ROT16_W_IMM4_Q_16_DST16_RN_DIRECT_HI + , M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_ROT16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_RORC16_W_16_DST16_RN_DIRECT_HI, M32C_INSN_RORC16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_RORC16_W_16_DST16_AN_INDIRECT_HI + , M32C_INSN_RORC16_W_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_RORC16_W_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_RORC16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_RORC16_W_16_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_RORC16_W_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_RORC16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_RORC16_B_16_DST16_RN_DIRECT_QI, M32C_INSN_RORC16_B_16_DST16_AN_DIRECT_QI + , M32C_INSN_RORC16_B_16_DST16_AN_INDIRECT_QI, M32C_INSN_RORC16_B_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_RORC16_B_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_RORC16_B_16_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_RORC16_B_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_RORC16_B_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_RORC16_B_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ROLC16_W_16_DST16_RN_DIRECT_HI + , M32C_INSN_ROLC16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_ROLC16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_ROLC16_W_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ROLC16_W_16_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_ROLC16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ROLC16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ROLC16_W_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROLC16_W_16_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_ROLC16_B_16_DST16_RN_DIRECT_QI, M32C_INSN_ROLC16_B_16_DST16_AN_DIRECT_QI, M32C_INSN_ROLC16_B_16_DST16_AN_INDIRECT_QI, M32C_INSN_ROLC16_B_16_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_ROLC16_B_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ROLC16_B_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ROLC16_B_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ROLC16_B_16_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_ROLC16_B_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_PUSHA16_16_MOVA_DST16_AN_INDIRECT_MOVA_HI + , M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_SB_RELATIVE_MOVA_HI + , M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_PUSH16_B_S_AN_AN16_PUSH_S_DERIVED, M32C_INSN_PUSH16_B_S_RN_RN16_PUSH_S_DERIVED + , M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_PUSH16_W_16_DST16_RN_DIRECT_HI, M32C_INSN_PUSH16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_PUSH16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_PUSH16_W_16_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_PUSH16_W_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_PUSH16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_PUSH16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_PUSH16_W_16_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_PUSH16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_PUSH16_B_16_DST16_RN_DIRECT_QI, M32C_INSN_PUSH16_B_16_DST16_AN_DIRECT_QI, M32C_INSN_PUSH16_B_16_DST16_AN_INDIRECT_QI + , M32C_INSN_PUSH16_B_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_PUSH16_B_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_PUSH16_B_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_PUSH16_B_16_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_PUSH16_B_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_PUSH16_B_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_POP16_B_S_AN_AN16_PUSH_S_DERIVED, M32C_INSN_POP16_B_S_RN_RN16_PUSH_S_DERIVED + , M32C_INSN_POP32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_POP32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_POP16_W_16_DST16_RN_DIRECT_HI, M32C_INSN_POP16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_POP16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_POP16_W_16_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_POP16_W_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_POP16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_POP16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_POP16_W_16_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_POP16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_POP16_B_16_DST16_RN_DIRECT_QI, M32C_INSN_POP16_B_16_DST16_AN_DIRECT_QI, M32C_INSN_POP16_B_16_DST16_AN_INDIRECT_QI + , M32C_INSN_POP16_B_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_POP16_B_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_POP16_B_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_POP16_B_16_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_POP16_B_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_POP16_B_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI + , M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI + , M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI + , M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI + , M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI + , M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI + , M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI + , M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI + , M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI + , M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI + , M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI + , M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI + , M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI + , M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI + , M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI + , M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI + , M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI + , M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI + , M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI + , M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI + , M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI + , M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_OR32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_OR32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI + , M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_OR32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_OR32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI + , M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI + , M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_OR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI + , M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_OR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI + , M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_NOT16_W_16_DST16_RN_DIRECT_HI + , M32C_INSN_NOT16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_NOT16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_NOT16_W_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_NOT16_W_16_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_NOT16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_NOT16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_NOT16_W_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_NOT16_W_16_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_NOT16_B_16_DST16_RN_DIRECT_QI, M32C_INSN_NOT16_B_16_DST16_AN_DIRECT_QI, M32C_INSN_NOT16_B_16_DST16_AN_INDIRECT_QI, M32C_INSN_NOT16_B_16_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_NOT16_B_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_NOT16_B_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_NOT16_B_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_NOT16_B_16_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_NOT16_B_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_NEG16_W_16_DST16_RN_DIRECT_HI, M32C_INSN_NEG16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_NEG16_W_16_DST16_AN_INDIRECT_HI + , M32C_INSN_NEG16_W_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_NEG16_W_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_NEG16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_NEG16_W_16_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_NEG16_W_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_NEG16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_NEG16_B_16_DST16_RN_DIRECT_QI, M32C_INSN_NEG16_B_16_DST16_AN_DIRECT_QI + , M32C_INSN_NEG16_B_16_DST16_AN_INDIRECT_QI, M32C_INSN_NEG16_B_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_NEG16_B_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_NEG16_B_16_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_NEG16_B_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_NEG16_B_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_NEG16_B_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI + , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI + , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI + , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI + , M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI + , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI + , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI + , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI + , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI + , M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI + , M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI + , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI + , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI + , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI + , M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI + , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI + , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI + , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI + , M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI + , M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI + , M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI + , M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI + , M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MULEX_DST32_R3_DIRECT_UNPREFIXED_HI + , M32C_INSN_MULEX_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULEX_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MULEX_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MULEX_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI + , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI + , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI + , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI + , M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI + , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI + , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI + , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI + , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI + , M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI + , M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI + , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI + , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI + , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI + , M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI + , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI + , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI + , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI + , M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI + , M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI + , M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI + , M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI + , M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOVHH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MOVHH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MOVHL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MOVLH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MOVLL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_RN_DIRECT_QI + , M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_DIRECT_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_INDIRECT_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_MOVHL16_SRC_R0L_DST16_RN_DIRECT_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_DIRECT_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_INDIRECT_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_RN_DIRECT_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_DIRECT_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_INDIRECT_QI + , M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_RN_DIRECT_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_DIRECT_QI + , M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_INDIRECT_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_RN_DIRECT_QI + , M32C_INSN_MOVHH16_R0L_DST_DST16_AN_DIRECT_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_AN_INDIRECT_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_MOVHL16_R0L_DST_DST16_RN_DIRECT_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_AN_DIRECT_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_AN_INDIRECT_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_RN_DIRECT_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_AN_DIRECT_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_AN_INDIRECT_QI + , M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_RN_DIRECT_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_AN_DIRECT_QI + , M32C_INSN_MOVLL16_R0L_DST_DST16_AN_INDIRECT_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOVA32_SRC_A1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI + , M32C_INSN_MOVA32_SRC_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_INSN_MOVA32_SRC_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI + , M32C_INSN_MOVA32_SRC_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_INSN_MOVA32_SRC_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_INSN_MOVA32_SRC_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI + , M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI + , M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_INSN_MOVA16_SRC_A1_DST16_AN_INDIRECT_MOVA_HI + , M32C_INSN_MOVA16_SRC_A1_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A1_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A1_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A1_DST16_16_16_SB_RELATIVE_MOVA_HI + , M32C_INSN_MOVA16_SRC_A1_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A1_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_MOVA16_SRC_A0_DST16_AN_INDIRECT_MOVA_HI, M32C_INSN_MOVA16_SRC_A0_DST16_16_8_AN_RELATIVE_MOVA_HI + , M32C_INSN_MOVA16_SRC_A0_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A0_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A0_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_A0_DST16_16_8_FB_RELATIVE_MOVA_HI + , M32C_INSN_MOVA16_SRC_A0_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_AN_INDIRECT_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_16_16_AN_RELATIVE_MOVA_HI + , M32C_INSN_MOVA16_SRC_R3_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R3_DST16_16_16_ABSOLUTE_MOVA_HI + , M32C_INSN_MOVA16_SRC_R2_DST16_AN_INDIRECT_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_16_8_SB_RELATIVE_MOVA_HI + , M32C_INSN_MOVA16_SRC_R2_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R2_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_MOVA16_SRC_R1_DST16_AN_INDIRECT_MOVA_HI + , M32C_INSN_MOVA16_SRC_R1_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R1_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R1_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R1_DST16_16_16_SB_RELATIVE_MOVA_HI + , M32C_INSN_MOVA16_SRC_R1_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R1_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_MOVA16_SRC_R0_DST16_AN_INDIRECT_MOVA_HI, M32C_INSN_MOVA16_SRC_R0_DST16_16_8_AN_RELATIVE_MOVA_HI + , M32C_INSN_MOVA16_SRC_R0_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R0_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R0_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_INSN_MOVA16_SRC_R0_DST16_16_8_FB_RELATIVE_MOVA_HI + , M32C_INSN_MOVA16_SRC_R0_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI + , M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_INDIRECT_HI + , M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_DIRECT_QI + , M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_SB_RELATIVE_SI, M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_FB_RELATIVE_SI, M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_SB_RELATIVE_SI + , M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_FB_RELATIVE_SI, M32C_INSN_MOV32_SZ_DST32_2_S_16_A1_DST32_2_S_16_ABSOLUTE_SI, M32C_INSN_MOV32_SZ_DST32_2_S_16_A0_DST32_2_S_16_ABSOLUTE_SI, M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_HI + , M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_W_R0_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_HI + , M32C_INSN_MOV32_B_R0L_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_SB_RELATIVE_QI + , M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_W_DST32_2_S_16_R1_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_B_DST32_2_S_16_R1L_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_DST32_2_S_BASIC_R1L_DST32_2_S_R0_DIRECT_HI + , M32C_INSN_MOV32_B_DST32_2_S_BASIC_R1L_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_SB_RELATIVE_QI + , M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_W_DST32_2_S_16_R0_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_B_DST32_2_S_16_R0L_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED + , M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_SB_RELATIVE_QI + , M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_FB_RELATIVE_QI + , M32C_INSN_MOV16_B_S_AN_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI + , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI + , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI + , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI + , M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI + , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI + , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI + , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI + , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI + , M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI + , M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI + , M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI + , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI + , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI + , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI + , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI + , M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI + , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI + , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI + , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI + , M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI + , M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI + , M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_HI + , M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_W_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_W_IMM_Z_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_QI + , M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_B_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_B_IMM_Z_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI + , M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_16_ABSOLUTE_QI + , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MOV16_W_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI + , M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI + , M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI + , M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI + , M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI + , M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI + , M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI + , M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI + , M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_STC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI + , M32C_INSN_STC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI + , M32C_INSN_STC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI + , M32C_INSN_STC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_STC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_STC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_STC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_STC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_STC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_STC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_STC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_STC16_PC_DST16_RN_DIRECT_HI, M32C_INSN_STC16_PC_DST16_AN_DIRECT_HI, M32C_INSN_STC16_PC_DST16_AN_INDIRECT_HI + , M32C_INSN_STC16_PC_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STC16_PC_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STC16_PC_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STC16_PC_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_STC16_PC_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_STC16_PC_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STC16_SRC_DST16_RN_DIRECT_HI, M32C_INSN_STC16_SRC_DST16_AN_DIRECT_HI + , M32C_INSN_STC16_SRC_DST16_AN_INDIRECT_HI, M32C_INSN_STC16_SRC_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STC16_SRC_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STC16_SRC_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_STC16_SRC_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STC16_SRC_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_STC16_SRC_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI + , M32C_INSN_LDC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI + , M32C_INSN_LDC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI + , M32C_INSN_LDC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_LDC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_LDC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_LDC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_LDC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_LDC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_LDC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_LDC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_LDC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_LDC16_DST_DST16_RN_DIRECT_HI + , M32C_INSN_LDC16_DST_DST16_AN_DIRECT_HI, M32C_INSN_LDC16_DST_DST16_AN_INDIRECT_HI, M32C_INSN_LDC16_DST_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_LDC16_DST_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_LDC16_DST_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDC16_DST_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_LDC16_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDC16_DST_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_JSRI32_A_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32_A_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_AN_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_SB_RELATIVE_SI + , M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_ABSOLUTE_SI, M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_AN_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_SB_RELATIVE_SI, M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_FB_RELATIVE_SI, M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_RN_DIRECT_SI, M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_DIRECT_SI + , M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_INDIRECT_SI, M32C_INSN_JSRI32_W_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32_W_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_RN_DIRECT_HI + , M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_DIRECT_HI, M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_INDIRECT_HI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_JMPI16_A_16_DST16_RN_DIRECT_SI, M32C_INSN_JMPI16_A_16_DST16_AN_DIRECT_SI + , M32C_INSN_JMPI16_A_16_DST16_AN_INDIRECT_SI, M32C_INSN_JMPI16_A_16_DST16_16_8_AN_RELATIVE_SI, M32C_INSN_JMPI16_A_16_DST16_16_16_AN_RELATIVE_SI, M32C_INSN_JMPI16_A_16_DST16_16_8_SB_RELATIVE_SI + , M32C_INSN_JMPI16_A_16_DST16_16_16_SB_RELATIVE_SI, M32C_INSN_JMPI16_A_16_DST16_16_8_FB_RELATIVE_SI, M32C_INSN_JMPI16_A_16_DST16_16_16_ABSOLUTE_SI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_JMPI16_W_16_DST16_RN_DIRECT_HI + , M32C_INSN_JMPI16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_JMPI16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_JMPI16_W_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_JMPI16_W_16_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_JMPI16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_JMPI16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_JMPI16_W_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_JMPI16_W_16_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_INC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_INC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_INC16_B_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_INC16_B_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_INC16_B_DST16_3_S_8_8_SB_RELATIVE_QI, M32C_INSN_INC16_B_DST16_3_S_8_8_FB_RELATIVE_QI + , M32C_INSN_INC16_B_DST16_3_S_8_16_ABSOLUTE_QI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_SUB32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI + , M32C_INSN_SUB32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_SUB32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI + , M32C_INSN_SUB32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_SUB16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI + , M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI + , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI + , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI + , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI + , M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI + , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI + , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI + , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI + , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI + , M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI + , M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI + , M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI + , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI + , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI + , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI + , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI + , M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI + , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI + , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI + , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI + , M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI + , M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI + , M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI + , M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI + , M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI + , M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI + , M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI + , M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI + , M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI + , M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI + , M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI + , M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI + , M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI + , M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI + , M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_RN_DIRECT_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_DIRECT_HI + , M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_RN_DIRECT_QI + , M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_DIRECT_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_DIVU16_W_DST16_16_HI_DST16_RN_DIRECT_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_DIRECT_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_RN_DIRECT_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_DIRECT_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_RN_DIRECT_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_DIRECT_HI + , M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_RN_DIRECT_QI + , M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_DIRECT_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_DEC16_B_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_DEC16_B_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_DEC16_B_DST16_3_S_8_8_SB_RELATIVE_QI, M32C_INSN_DEC16_B_DST16_3_S_8_8_FB_RELATIVE_QI + , M32C_INSN_DEC16_B_DST16_3_S_8_16_ABSOLUTE_QI, M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_SB_RELATIVE_HI, M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_FB_RELATIVE_HI, M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_16_ABSOLUTE_HI + , M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_SB_RELATIVE_QI, M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_FB_RELATIVE_QI, M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_16_ABSOLUTE_QI, M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI + , M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_CMP32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_CMP32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI + , M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_CMP32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_CMP32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CMP16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED + , M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI + , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI + , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI + , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI + , M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI + , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI + , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI + , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI + , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI + , M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI + , M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI + , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI + , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI + , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI + , M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI + , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI + , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI + , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI + , M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI + , M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI + , M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI + , M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_DIRECT_HI + , M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_RN_DIRECT_QI + , M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI + , M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED + , M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED + , M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED + , M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BXOR16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_DIRECT + , M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE + , M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED + , M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED + , M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED + , M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_RN_DIRECT + , M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_AN_RELATIVE + , M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_ABSOLUTE + , M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED + , M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED + , M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED + , M32C_INSN_BTSTC16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_AN_RELATIVE + , M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_FB_RELATIVE + , M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED + , M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED + , M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED + , M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_INSN_BTST16_G_BIT16_16_8_BIT16_RN_DIRECT, M32C_INSN_BTST16_G_BIT16_16_8_BIT16_AN_DIRECT, M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE + , M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, M32C_INSN_BTST16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE + , M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BTST16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED + , M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED + , M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED + , M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_INSN_BSET16_G_BIT16_16_8_BIT16_RN_DIRECT + , M32C_INSN_BSET16_G_BIT16_16_8_BIT16_AN_DIRECT, M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE + , M32C_INSN_BSET16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE + , M32C_INSN_BSET16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED + , M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED + , M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED + , M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BOR16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_INDIRECT + , M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE + , M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED + , M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED + , M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED + , M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_DIRECT + , M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE + , M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED + , M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED + , M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED + , M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BNTST16_X_BIT16_16_BIT16_RN_DIRECT + , M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_AN_RELATIVE + , M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_ABSOLUTE + , M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED + , M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED + , M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED + , M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_RN_DIRECT, M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_AN_DIRECT, M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE + , M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, M32C_INSN_BNOT16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE + , M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BNOT16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED + , M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED + , M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED + , M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BNOR16_X_BIT16_16_BIT16_RN_DIRECT, M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_DIRECT + , M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE + , M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED + , M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED + , M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED + , M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BNAND16_X_BIT16_16_BIT16_RN_DIRECT + , M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE + , M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE + , M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_INDIRECT_UNPREFIXED, M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_AN_RELATIVE_UNPREFIXED + , M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_SB_RELATIVE_UNPREFIXED + , M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_ABSOLUTE_UNPREFIXED + , M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_RN_DIRECT, M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_AN_DIRECT, M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_AN_RELATIVE, M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_SB_RELATIVE + , M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_FB_RELATIVE, M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_AN_RELATIVE, M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_SB_RELATIVE, M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_ABSOLUTE + , M32C_INSN_BM16_BIT16_16_BASIC_COND16_16_BIT16_AN_INDIRECT, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED + , M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED + , M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED + , M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_RN_DIRECT, M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_AN_DIRECT, M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE + , M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, M32C_INSN_BCLR16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE + , M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, M32C_INSN_BCLR16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED + , M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED + , M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED + , M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_INSN_BAND16_X_BIT16_16_BIT16_RN_DIRECT + , M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_DIRECT, M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_INDIRECT, M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE + , M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE + , M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_AND32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_AND32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI + , M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_AND32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_AND32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI + , M32C_INSN_AND16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI + , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI + , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI + , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI + , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI + , M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI + , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI + , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI + , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI + , M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI + , M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI + , M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI + , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI + , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI + , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI + , M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI + , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI + , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI + , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI + , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI + , M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI + , M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI + , M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI + , M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_AND16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI + , M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_AND16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI + , M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI + , M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI + , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI + , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI + , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI + , M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI + , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI + , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI + , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI + , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI + , M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI + , M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI + , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI + , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI + , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI + , M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI + , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI + , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI + , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI + , M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI + , M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI + , M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI + , M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI + , M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI + , M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI + , M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI + , M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_ADD32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_ADD32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI + , M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_ADD32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_ADD32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A0_DIRECT_HI + , M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A1_DIRECT_HI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI + , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI + , M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI + , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI + , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI + , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI + , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI + , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI + , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI + , M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI + , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI + , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI + , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI + , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI + , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI + , M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI + , M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI + , M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI + , M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI + , M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI + , M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI + , M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI + , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI + , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI + , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI + , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI + , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI + , M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI + , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI + , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI + , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI + , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI + , M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI + , M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI + , M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI + , M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI + , M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI + , M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ADD16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI + , M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI + , M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI + , M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI + , M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI + , M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_ADCF16_W_16_DST16_RN_DIRECT_HI, M32C_INSN_ADCF16_W_16_DST16_AN_DIRECT_HI, M32C_INSN_ADCF16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_ADCF16_W_16_DST16_16_8_AN_RELATIVE_HI + , M32C_INSN_ADCF16_W_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ADCF16_W_16_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ADCF16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ADCF16_W_16_DST16_16_8_FB_RELATIVE_HI + , M32C_INSN_ADCF16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ADCF16_B_16_DST16_RN_DIRECT_QI, M32C_INSN_ADCF16_B_16_DST16_AN_DIRECT_QI, M32C_INSN_ADCF16_B_16_DST16_AN_INDIRECT_QI + , M32C_INSN_ADCF16_B_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ADCF16_B_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ADCF16_B_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ADCF16_B_16_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_ADCF16_B_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ADCF16_B_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI + , M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI + , M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ABS16_W_16_DST16_RN_DIRECT_HI, M32C_INSN_ABS16_W_16_DST16_AN_DIRECT_HI + , M32C_INSN_ABS16_W_16_DST16_AN_INDIRECT_HI, M32C_INSN_ABS16_W_16_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ABS16_W_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ABS16_W_16_DST16_16_8_SB_RELATIVE_HI + , M32C_INSN_ABS16_W_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ABS16_W_16_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ABS16_W_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ABS16_B_16_DST16_RN_DIRECT_QI + , M32C_INSN_ABS16_B_16_DST16_AN_DIRECT_QI, M32C_INSN_ABS16_B_16_DST16_AN_INDIRECT_QI, M32C_INSN_ABS16_B_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ABS16_B_16_DST16_16_16_AN_RELATIVE_QI + , M32C_INSN_ABS16_B_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_ABS16_B_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ABS16_B_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ABS16_B_16_DST16_16_16_ABSOLUTE_QI + , M32C_INSN_ADD16_Q_SP, M32C_INSN_ADD16_B_G_SP, M32C_INSN_ADD16_W_G_SP, M32C_INSN_ADD32_L_IMM3_Q + , M32C_INSN_ADD32_L_IMM8_S, M32C_INSN_ADD32_L_IMM16_G, M32C_INSN_DADC16_B_IMM8, M32C_INSN_DADC16_W_IMM16 + , M32C_INSN_DADC16_B_R0H_R0L, M32C_INSN_DADC16_W_R1_R0, M32C_INSN_DADD16_B_IMM8, M32C_INSN_DADD16_W_IMM16 + , M32C_INSN_DADD16_B_R0H_R0L, M32C_INSN_DADD16_W_R1_R0, M32C_INSN_BM16_C, M32C_INSN_BM32_C + , M32C_INSN_BRK16, M32C_INSN_BRK32, M32C_INSN_BRK232, M32C_INSN_DEC16_W + , M32C_INSN_DIV16_B_IMM_16_QI, M32C_INSN_DIV16_W_IMM_16_HI, M32C_INSN_DIV32_B_IMM_16_QI, M32C_INSN_DIV32_W_IMM_16_HI + , M32C_INSN_DIVU16_B_IMM_16_QI, M32C_INSN_DIVU16_W_IMM_16_HI, M32C_INSN_DIVU32_B_IMM_16_QI, M32C_INSN_DIVU32_W_IMM_16_HI + , M32C_INSN_DIVX16_B_IMM_16_QI, M32C_INSN_DIVX16_W_IMM_16_HI, M32C_INSN_DIVX32_B_IMM_16_QI, M32C_INSN_DIVX32_W_IMM_16_HI + , M32C_INSN_DSBB16_B_IMM8, M32C_INSN_DSBB16_W_IMM16, M32C_INSN_DSBB16_B_R0H_R0L, M32C_INSN_DSBB16_W_R1_R0 + , M32C_INSN_DSUB16_B_IMM8, M32C_INSN_DSUB16_W_IMM16, M32C_INSN_DSUB16_B_R0H_R0L, M32C_INSN_DSUB16_W_R1_R0 + , M32C_INSN_ENTER16, M32C_INSN_EXITD16, M32C_INSN_ENTER32, M32C_INSN_EXITD32 + , M32C_INSN_FCLR16, M32C_INSN_FSET16, M32C_INSN_FCLR, M32C_INSN_FSET + , M32C_INSN_INC16_W, M32C_INSN_FREIT32, M32C_INSN_INT16, M32C_INSN_INTO16 + , M32C_INSN_INT32, M32C_INSN_INTO32, M32C_INSN_JCND16_5, M32C_INSN_JCND16 + , M32C_INSN_JCND32, M32C_INSN_JMP16_S, M32C_INSN_JMP16_B, M32C_INSN_JMP16_W + , M32C_INSN_JMP16_A, M32C_INSN_JMPS16, M32C_INSN_JMP32_S, M32C_INSN_JMP32_B + , M32C_INSN_JMP32_W, M32C_INSN_JMP32_A, M32C_INSN_JMPS32, M32C_INSN_JSR16_W + , M32C_INSN_JSR16_A, M32C_INSN_JSR32_W, M32C_INSN_JSR32_A, M32C_INSN_JSRS16 + , M32C_INSN_JSRS, M32C_INSN_LDC16_IMM16, M32C_INSN_LDC32_IMM16_CR1, M32C_INSN_LDC32_IMM16_CR2 + , M32C_INSN_LDC32_IMM16_CR3, M32C_INSN_LDCTX16, M32C_INSN_LDCTX32, M32C_INSN_STCTX16 + , M32C_INSN_STCTX32, M32C_INSN_LDIPL16_IMM, M32C_INSN_LDIPL32_IMM, M32C_INSN_MOV16_B_S_IMM_A0 + , M32C_INSN_MOV16_B_S_IMM_A1, M32C_INSN_MOV16_W_S_IMM_A0, M32C_INSN_MOV16_W_S_IMM_A1, M32C_INSN_MOV32_W_A0 + , M32C_INSN_MOV32_W_A1, M32C_INSN_MOV32_L_A0, M32C_INSN_MOV32_L_A1, M32C_INSN_MOV16_B_S_R0L_A1 + , M32C_INSN_MOV16_B_S_R0H_A0, M32C_INSN_NOP16, M32C_INSN_NOP32, M32C_INSN_POPC16_IMM16 + , M32C_INSN_POPC32_IMM16_CR1, M32C_INSN_POPC32_IMM16_CR2, M32C_INSN_PUSHC16_IMM16, M32C_INSN_PUSHC32_IMM16_CR1 + , M32C_INSN_PUSHC32_IMM16_CR2, M32C_INSN_POPM16, M32C_INSN_PUSHM16, M32C_INSN_POPM + , M32C_INSN_PUSHM, M32C_INSN_PUSH16_B_G_IMM, M32C_INSN_PUSH16_W_G_IMM, M32C_INSN_PUSH32_B_IMM + , M32C_INSN_PUSH32_W_IMM, M32C_INSN_PUSH32_L_IMM, M32C_INSN_REIT16, M32C_INSN_REIT32 + , M32C_INSN_RMPA16_B, M32C_INSN_RMPA16_W, M32C_INSN_RMPA32_B, M32C_INSN_RMPA32_W + , M32C_INSN_RTS16, M32C_INSN_RTS32, M32C_INSN_SCMPU_B, M32C_INSN_SCMPU_W + , M32C_INSN_SHA16_L_IMM_R2R0, M32C_INSN_SHA16_L_IMM_R3R1, M32C_INSN_SHA16_L_R1H_R2R0, M32C_INSN_SHA16_L_R1H_R3R1 + , M32C_INSN_SHL16_L_IMM_R2R0, M32C_INSN_SHL16_L_IMM_R3R1, M32C_INSN_SHL16_L_R1H_R2R0, M32C_INSN_SHL16_L_R1H_R3R1 + , M32C_INSN_SIN32_B, M32C_INSN_SIN32_W, M32C_INSN_SMOVB16_B, M32C_INSN_SMOVB16_W + , M32C_INSN_SMOVB32_B, M32C_INSN_SMOVB32_W, M32C_INSN_SMOVF16_B, M32C_INSN_SMOVF16_W + , M32C_INSN_SMOVF32_B, M32C_INSN_SMOVF32_W, M32C_INSN_SMOVU_B, M32C_INSN_SMOVU_W + , M32C_INSN_SOUT_B, M32C_INSN_SOUT_W, M32C_INSN_SSTR16_B, M32C_INSN_SSTR16_W + , M32C_INSN_SSTR_B, M32C_INSN_SSTR_W, M32C_INSN_STZX16_IMM8_IMM8_R0H, M32C_INSN_STZX16_IMM8_IMM8_R0L + , M32C_INSN_STZX16_IMM8_IMM8_DSP8SB, M32C_INSN_STZX16_IMM8_IMM8_DSP8FB, M32C_INSN_STZX16_IMM8_IMM8_ABS16, M32C_INSN_UND16 + , M32C_INSN_UND32, M32C_INSN_WAIT16, M32C_INSN_WAIT, M32C_INSN_EXTS16_W_R0 + , M32C_INSN_SRCIND, M32C_INSN_DESTIND, M32C_INSN_SRCDESTIND +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID M32C_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) M32C_INSN_SRCDESTIND + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_0_1; + long f_0_2; + long f_0_3; + long f_0_4; + long f_1_3; + long f_2_2; + long f_3_4; + long f_3_1; + long f_4_1; + long f_4_3; + long f_4_4; + long f_4_6; + long f_5_1; + long f_5_3; + long f_6_2; + long f_7_1; + long f_8_1; + long f_8_2; + long f_8_3; + long f_8_4; + long f_8_8; + long f_9_3; + long f_9_1; + long f_10_1; + long f_10_2; + long f_10_3; + long f_11_1; + long f_12_1; + long f_12_2; + long f_12_3; + long f_12_4; + long f_12_6; + long f_13_3; + long f_14_1; + long f_14_2; + long f_15_1; + long f_16_1; + long f_16_2; + long f_16_4; + long f_16_8; + long f_18_1; + long f_18_2; + long f_18_3; + long f_20_1; + long f_20_3; + long f_20_2; + long f_20_4; + long f_21_3; + long f_24_2; + long f_24_8; + long f_32_16; + long f_src16_rn; + long f_src16_an; + long f_src32_an_unprefixed; + long f_src32_an_prefixed; + long f_src32_rn_unprefixed_QI; + long f_src32_rn_prefixed_QI; + long f_src32_rn_unprefixed_HI; + long f_src32_rn_prefixed_HI; + long f_src32_rn_unprefixed_SI; + long f_src32_rn_prefixed_SI; + long f_dst32_rn_ext_unprefixed; + long f_dst16_rn; + long f_dst16_rn_ext; + long f_dst16_rn_QI_s; + long f_dst16_an; + long f_dst16_an_s; + long f_dst32_an_unprefixed; + long f_dst32_an_prefixed; + long f_dst32_rn_unprefixed_QI; + long f_dst32_rn_prefixed_QI; + long f_dst32_rn_unprefixed_HI; + long f_dst32_rn_prefixed_HI; + long f_dst32_rn_unprefixed_SI; + long f_dst32_rn_prefixed_SI; + long f_dst16_1_S; + long f_imm_8_s4; + long f_imm_12_s4; + long f_imm_13_u3; + long f_imm_20_s4; + long f_imm1_S; + long f_imm3_S; + long f_dsp_8_u6; + long f_dsp_8_u8; + long f_dsp_8_s8; + long f_dsp_10_u6; + long f_dsp_16_u8; + long f_dsp_16_s8; + long f_dsp_24_u8; + long f_dsp_24_s8; + long f_dsp_32_u8; + long f_dsp_32_s8; + long f_dsp_40_u8; + long f_dsp_40_s8; + long f_dsp_48_u8; + long f_dsp_48_s8; + long f_dsp_56_u8; + long f_dsp_56_s8; + long f_dsp_64_u8; + long f_dsp_64_s8; + long f_dsp_8_u16; + long f_dsp_8_s16; + long f_dsp_16_u16; + long f_dsp_16_s16; + long f_dsp_24_u16; + long f_dsp_24_s16; + long f_dsp_32_u16; + long f_dsp_32_s16; + long f_dsp_40_u16; + long f_dsp_40_s16; + long f_dsp_48_u16; + long f_dsp_48_s16; + long f_dsp_64_u16; + long f_dsp_8_u24; + long f_dsp_16_u24; + long f_dsp_24_u24; + long f_dsp_32_u24; + long f_dsp_40_u24; + long f_dsp_40_s32; + long f_dsp_48_u24; + long f_dsp_16_s32; + long f_dsp_24_s32; + long f_dsp_32_s32; + long f_dsp_48_u32; + long f_dsp_48_s32; + long f_dsp_56_s16; + long f_dsp_64_s16; + long f_bitno16_S; + long f_bitno32_prefixed; + long f_bitno32_unprefixed; + long f_bitbase16_u11_S; + long f_bitbase32_16_u11_unprefixed; + long f_bitbase32_16_s11_unprefixed; + long f_bitbase32_16_u19_unprefixed; + long f_bitbase32_16_s19_unprefixed; + long f_bitbase32_16_u27_unprefixed; + long f_bitbase32_24_u11_prefixed; + long f_bitbase32_24_s11_prefixed; + long f_bitbase32_24_u19_prefixed; + long f_bitbase32_24_s19_prefixed; + long f_bitbase32_24_u27_prefixed; + long f_lab_5_3; + long f_lab32_jmp_s; + long f_lab_8_8; + long f_lab_8_16; + long f_lab_8_24; + long f_lab_16_8; + long f_lab_24_8; + long f_lab_32_8; + long f_lab_40_8; + long f_cond16; + long f_cond16j_5; + long f_cond32; + long f_cond32j; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* M32C_OPC_H */ diff -uprN binutils-2.16.91.0.1/opcodes/m32r-asm.c binutils-2.16.91.0.2/opcodes/m32r-asm.c --- binutils-2.16.91.0.1/opcodes/m32r-asm.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/m32r-asm.c 2005-07-20 12:27:29.256869235 -0700 @@ -1,26 +1,27 @@ /* Assembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-asm.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -48,23 +49,15 @@ static const char * parse_insn_normal /* -- assembler routines inserted here. */ /* -- asm.c */ -static const char * parse_hash - PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); -static const char * parse_hi16 - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_slo16 - PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); -static const char * parse_ulo16 - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'"); /* Handle '#' prefixes (i.e. skip over them). */ static const char * -parse_hash (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - const char **strp; - int opindex ATTRIBUTE_UNUSED; - long *valuep ATTRIBUTE_UNUSED; +parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + long *valuep ATTRIBUTE_UNUSED) { if (**strp == '#') ++*strp; @@ -74,11 +67,10 @@ parse_hash (cd, strp, opindex, valuep) /* Handle shigh(), high(). */ static const char * -parse_hi16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_hi16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -91,9 +83,9 @@ parse_hi16 (cd, strp, opindex, valuep) { *strp += 5; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_ULO, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return "missing `)'"; + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) @@ -105,9 +97,9 @@ parse_hi16 (cd, strp, opindex, valuep) { *strp += 6; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_SLO, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return "missing `)'"; + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) @@ -127,11 +119,10 @@ parse_hi16 (cd, strp, opindex, valuep) handles the case where low() isn't present. */ static const char * -parse_slo16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - long *valuep; +parse_slo16 (CGEN_CPU_DESC cd, + const char ** strp, + int opindex, + long * valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -144,9 +135,9 @@ parse_slo16 (cd, strp, opindex, valuep) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return "missing `)'"; + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) @@ -163,9 +154,9 @@ parse_slo16 (cd, strp, opindex, valuep) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_SDA16, - NULL, &value); + NULL, & value); if (**strp != ')') - return "missing `)'"; + return MISSING_CLOSING_PARENTHESIS; ++*strp; *valuep = value; return errmsg; @@ -179,11 +170,10 @@ parse_slo16 (cd, strp, opindex, valuep) handles the case where low() isn't present. */ static const char * -parse_ulo16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_ulo16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -196,9 +186,9 @@ parse_ulo16 (cd, strp, opindex, valuep) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return "missing `)'"; + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) @@ -213,7 +203,7 @@ parse_ulo16 (cd, strp, opindex, valuep) /* -- */ const char * m32r_cgen_parse_operand - PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); /* Main entry point for operand parsing. @@ -229,11 +219,10 @@ const char * m32r_cgen_parse_operand the handlers. */ const char * -m32r_cgen_parse_operand (cd, opindex, strp, fields) - CGEN_CPU_DESC cd; - int opindex; - const char ** strp; - CGEN_FIELDS * fields; +m32r_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) { const char * errmsg = NULL; /* Used by scalar operands that still need to be parsed. */ @@ -348,8 +337,7 @@ cgen_parse_fn * const m32r_cgen_parse_ha }; void -m32r_cgen_init_asm (cd) - CGEN_CPU_DESC cd; +m32r_cgen_init_asm (CGEN_CPU_DESC cd) { m32r_cgen_init_opcode_table (cd); m32r_cgen_init_ibld_table (cd); @@ -732,30 +720,3 @@ m32r_cgen_assemble_insn (CGEN_CPU_DESC c return NULL; } } - -#if 0 /* This calls back to GAS which we can't do without care. */ - -/* Record each member of OPVALS in the assembler's symbol table. - This lets GAS parse registers for us. - ??? Interesting idea but not currently used. */ - -/* Record each member of OPVALS in the assembler's symbol table. - FIXME: Not currently used. */ - -void -m32r_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) -{ - CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); - const CGEN_KEYWORD_ENTRY * ke; - - while ((ke = cgen_keyword_search_next (& search)) != NULL) - { -#if 0 /* Unnecessary, should be done in the search routine. */ - if (! m32r_cgen_opval_supported (ke)) - continue; -#endif - cgen_asm_record_register (cd, ke->name, ke->value); - } -} - -#endif /* 0 */ diff -uprN binutils-2.16.91.0.1/opcodes/m32r-desc.c binutils-2.16.91.0.2/opcodes/m32r-desc.c --- binutils-2.16.91.0.1/opcodes/m32r-desc.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/m32r-desc.c 2005-07-20 12:27:29.258868905 -0700 @@ -1209,27 +1209,23 @@ static const CGEN_IBASE m32r_cgen_insn_t #undef A /* Initialize anything needed to be done once, before any cpu_open call. */ -static void init_tables PARAMS ((void)); static void -init_tables () +init_tables (void) { } -static const CGEN_MACH * lookup_mach_via_bfd_name - PARAMS ((const CGEN_MACH *, const char *)); -static void build_hw_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_operand_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_insn_table PARAMS ((CGEN_CPU_TABLE *)); -static void m32r_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *)); +static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); +static void build_hw_table (CGEN_CPU_TABLE *); +static void build_ifield_table (CGEN_CPU_TABLE *); +static void build_operand_table (CGEN_CPU_TABLE *); +static void build_insn_table (CGEN_CPU_TABLE *); +static void m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *); /* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name. */ static const CGEN_MACH * -lookup_mach_via_bfd_name (table, name) - const CGEN_MACH *table; - const char *name; +lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) { while (table->name) { @@ -1243,8 +1239,7 @@ lookup_mach_via_bfd_name (table, name) /* Subroutine of m32r_cgen_cpu_open to build the hardware table. */ static void -build_hw_table (cd) - CGEN_CPU_TABLE *cd; +build_hw_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; @@ -1270,8 +1265,7 @@ build_hw_table (cd) /* Subroutine of m32r_cgen_cpu_open to build the hardware table. */ static void -build_ifield_table (cd) - CGEN_CPU_TABLE *cd; +build_ifield_table (CGEN_CPU_TABLE *cd) { cd->ifld_table = & m32r_cgen_ifld_table[0]; } @@ -1279,8 +1273,7 @@ build_ifield_table (cd) /* Subroutine of m32r_cgen_cpu_open to build the hardware table. */ static void -build_operand_table (cd) - CGEN_CPU_TABLE *cd; +build_operand_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; @@ -1288,8 +1281,7 @@ build_operand_table (cd) /* MAX_OPERANDS is only an upper bound on the number of selected entries. However each entry is indexed by it's enum so there can be holes in the table. */ - const CGEN_OPERAND **selected = - (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); cd->operand_table.init_entries = init; cd->operand_table.entry_size = sizeof (CGEN_OPERAND); @@ -1312,12 +1304,11 @@ build_operand_table (cd) operand elements to be in the table [which they mightn't be]. */ static void -build_insn_table (cd) - CGEN_CPU_TABLE *cd; +build_insn_table (CGEN_CPU_TABLE *cd) { int i; const CGEN_IBASE *ib = & m32r_cgen_insn_table[0]; - CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); for (i = 0; i < MAX_INSNS; ++i) @@ -1330,8 +1321,7 @@ build_insn_table (cd) /* Subroutine of m32r_cgen_cpu_open to rebuild the tables. */ static void -m32r_cgen_rebuild_tables (cd) - CGEN_CPU_TABLE *cd; +m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) { int i; unsigned int isas = cd->isas; @@ -1343,7 +1333,7 @@ m32r_cgen_rebuild_tables (cd) #define UNSET (CGEN_SIZE_UNKNOWN + 1) cd->default_insn_bitsize = UNSET; cd->base_insn_bitsize = UNSET; - cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) if (((1 << i) & isas) != 0) @@ -1355,7 +1345,7 @@ m32r_cgen_rebuild_tables (cd) if (cd->default_insn_bitsize == UNSET) cd->default_insn_bitsize = isa->default_insn_bitsize; else if (isa->default_insn_bitsize == cd->default_insn_bitsize) - ; /* this is ok */ + ; /* This is ok. */ else cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; @@ -1364,7 +1354,7 @@ m32r_cgen_rebuild_tables (cd) if (cd->base_insn_bitsize == UNSET) cd->base_insn_bitsize = isa->base_insn_bitsize; else if (isa->base_insn_bitsize == cd->base_insn_bitsize) - ; /* this is ok */ + ; /* This is ok. */ else cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; @@ -1476,12 +1466,12 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_a } va_end (ap); - /* mach unspecified means "all" */ + /* Mach unspecified means "all". */ if (machs == 0) machs = (1 << MAX_MACHS) - 1; - /* base mach is always selected */ + /* Base mach is always selected. */ machs |= 1; - /* isa unspecified means "all" */ + /* ISA unspecified means "all". */ if (isas == 0) isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) @@ -1514,9 +1504,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_a MACH_NAME is the bfd name of the mach. */ CGEN_CPU_DESC -m32r_cgen_cpu_open_1 (mach_name, endian) - const char *mach_name; - enum cgen_endian endian; +m32r_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) { return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, CGEN_CPU_OPEN_ENDIAN, endian, @@ -1529,8 +1517,7 @@ m32r_cgen_cpu_open_1 (mach_name, endian) place as some simulator ports use this but they don't use libopcodes. */ void -m32r_cgen_cpu_close (cd) - CGEN_CPU_DESC cd; +m32r_cgen_cpu_close (CGEN_CPU_DESC cd) { unsigned int i; const CGEN_INSN *insns; @@ -1539,23 +1526,17 @@ m32r_cgen_cpu_close (cd) { insns = cd->macro_insn_table.init_entries; for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) - { - if (CGEN_INSN_RX ((insns))) - regfree (CGEN_INSN_RX (insns)); - } + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); } if (cd->insn_table.init_entries) { insns = cd->insn_table.init_entries; for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) - { - if (CGEN_INSN_RX (insns)) - regfree (CGEN_INSN_RX (insns)); - } - } - - + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } if (cd->macro_insn_table.init_entries) free ((CGEN_INSN *) cd->macro_insn_table.init_entries); diff -uprN binutils-2.16.91.0.1/opcodes/m32r-dis.c binutils-2.16.91.0.2/opcodes/m32r-dis.c --- binutils-2.16.91.0.1/opcodes/m32r-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/m32r-dis.c 2005-07-20 12:27:29.259868740 -0700 @@ -1,27 +1,27 @@ /* Disassembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-dis.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 -Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -56,12 +56,9 @@ static int read_insn (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, unsigned long *); -/* -- disassembler routines inserted here */ +/* -- disassembler routines inserted here. */ /* -- dis.c */ -static void print_hash PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); -static int my_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); - /* Immediate values are prefixed with '#'. */ #define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length) \ @@ -75,15 +72,15 @@ static int my_print_insn PARAMS ((CGEN_C /* Handle '#' prefixes as operands. */ static void -print_hash (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value ATTRIBUTE_UNUSED; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + long value ATTRIBUTE_UNUSED, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; + (*info->fprintf_func) (info->stream, "#"); } @@ -91,10 +88,9 @@ print_hash (cd, dis_info, value, attrs, #define CGEN_PRINT_INSN my_print_insn static int -my_print_insn (cd, pc, info) - CGEN_CPU_DESC cd; - bfd_vma pc; - disassemble_info *info; +my_print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info) { bfd_byte buffer[CGEN_MAX_INSN_SIZE]; bfd_byte *buf = buffer; @@ -149,8 +145,7 @@ my_print_insn (cd, pc, info) /* -- */ void m32r_cgen_print_operand - PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, - void const *, bfd_vma, int)); + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); /* Main entry point for printing operands. XINFO is a `void *' and not a `disassemble_info *' to not put a requirement @@ -168,16 +163,15 @@ void m32r_cgen_print_operand the handlers. */ void -m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) - CGEN_CPU_DESC cd; - int opindex; - PTR xinfo; - CGEN_FIELDS *fields; - void const *attrs ATTRIBUTE_UNUSED; - bfd_vma pc; - int length; +m32r_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) { - disassemble_info *info = (disassemble_info *) xinfo; + disassemble_info *info = (disassemble_info *) xinfo; switch (opindex) { @@ -272,8 +266,7 @@ cgen_print_fn * const m32r_cgen_print_ha void -m32r_cgen_init_dis (cd) - CGEN_CPU_DESC cd; +m32r_cgen_init_dis (CGEN_CPU_DESC cd) { m32r_cgen_init_opcode_table (cd); m32r_cgen_init_ibld_table (cd); @@ -325,7 +318,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUT /* Print the operand as directed by the attributes. */ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) - ; /* nothing to do */ + ; /* Nothing to do. */ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) (*info->print_address_func) (value, info); else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) @@ -407,6 +400,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UN unsigned long *insn_value) { int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) { (*info->memory_error_func) (status, pc, info); @@ -511,13 +505,13 @@ print_insn (CGEN_CPU_DESC cd, length = CGEN_EXTRACT_FN (cd, insn) (cd, insn, &ex_info, insn_value_cropped, &fields, pc); - /* length < 0 -> error */ + /* Length < 0 -> error. */ if (length < 0) return length; if (length > 0) { CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); - /* length is in bits, result is in bytes */ + /* Length is in bits, result is in bytes. */ return length / 8; } } @@ -567,7 +561,8 @@ default_print_insn (CGEN_CPU_DESC cd, bf Print one instruction from PC on INFO->STREAM. Return the size of the instruction (in bytes). */ -typedef struct cpu_desc_list { +typedef struct cpu_desc_list +{ struct cpu_desc_list *next; int isa; int mach; @@ -652,7 +647,7 @@ print_insn_m32r (bfd_vma pc, disassemble if (!cd) abort (); - /* save this away for future reference */ + /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; cl->isa = isa; diff -uprN binutils-2.16.91.0.1/opcodes/m32r-ibld.c binutils-2.16.91.0.2/opcodes/m32r-ibld.c --- binutils-2.16.91.0.1/opcodes/m32r-ibld.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/m32r-ibld.c 2005-07-20 12:27:29.261868410 -0700 @@ -1,25 +1,26 @@ /* Instruction building/extraction support for m32r. -*- C -*- -THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. -- the resultant file is machine generated, cgen-ibld.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -35,9 +36,9 @@ along with this program; if not, write t #include "opintl.h" #include "safe-ctype.h" -#undef min +#undef min #define min(a,b) ((a) < (b) ? (a) : (b)) -#undef max +#undef max #define max(a,b) ((a) > (b) ? (a) : (b)) /* Used by the ifield rtx function. */ @@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd, if (length == 0) return NULL; -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - if (word_length > 32) abort (); @@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd, #if CGEN_INT_INSN_P /* Cover function to store an insn value into an integral insn. Must go here - because it needs -desc.h for CGEN_INT_INSN_P. */ + because it needs -desc.h for CGEN_INT_INSN_P. */ static void put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, @@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATT int shift = insn_length - length; /* Written this way to avoid undefined behaviour. */ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); } } @@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd, { unsigned long x; int shift; -#if 0 - int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; -#endif + x = cgen_get_insn_value (cd, bufp, word_length); if (CGEN_INSN_LSB0_P) @@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd, return 1; } -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - if (word_length > 32) abort (); @@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd, return CGEN_INSN_BITSIZE (insn); } -/* machine generated code added here */ +/* Machine generated code added here. */ const char * m32r_cgen_insert_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); /* Main entry point for operand insertion. @@ -559,12 +547,11 @@ const char * m32r_cgen_insert_operand resolved during parsing. */ const char * -m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc) - CGEN_CPU_DESC cd; - int opindex; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc ATTRIBUTE_UNUSED; +m32r_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) { const char * errmsg = NULL; unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); @@ -673,8 +660,7 @@ m32r_cgen_insert_operand (cd, opindex, f } int m32r_cgen_extract_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - CGEN_FIELDS *, bfd_vma)); + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); /* Main entry point for operand extraction. The result is <= 0 for error, >0 for success. @@ -692,13 +678,12 @@ int m32r_cgen_extract_operand the handlers. */ int -m32r_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) - CGEN_CPU_DESC cd; - int opindex; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS * fields; - bfd_vma pc; +m32r_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) { /* Assume success (for those operands that are nops). */ int length = 1; @@ -821,10 +806,8 @@ cgen_extract_fn * const m32r_cgen_extrac extract_insn_normal, }; -int m32r_cgen_get_int_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); -bfd_vma m32r_cgen_get_vma_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +int m32r_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma m32r_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); /* Getting values from cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they return. @@ -832,10 +815,9 @@ bfd_vma m32r_cgen_get_vma_operand not appropriate. */ int -m32r_cgen_get_int_operand (cd, opindex, fields) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - const CGEN_FIELDS * fields; +m32r_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) { int value; @@ -928,10 +910,9 @@ m32r_cgen_get_int_operand (cd, opindex, } bfd_vma -m32r_cgen_get_vma_operand (cd, opindex, fields) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - const CGEN_FIELDS * fields; +m32r_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) { bfd_vma value; @@ -1023,10 +1004,8 @@ m32r_cgen_get_vma_operand (cd, opindex, return value; } -void m32r_cgen_set_int_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); -void m32r_cgen_set_vma_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); +void m32r_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void m32r_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); /* Stuffing values in cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they accept. @@ -1034,11 +1013,10 @@ void m32r_cgen_set_vma_operand not appropriate. */ void -m32r_cgen_set_int_operand (cd, opindex, fields, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - CGEN_FIELDS * fields; - int value; +m32r_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) { switch (opindex) { @@ -1126,11 +1104,10 @@ m32r_cgen_set_int_operand (cd, opindex, } void -m32r_cgen_set_vma_operand (cd, opindex, fields, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - CGEN_FIELDS * fields; - bfd_vma value; +m32r_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) { switch (opindex) { @@ -1220,8 +1197,7 @@ m32r_cgen_set_vma_operand (cd, opindex, /* Function to call before using the instruction builder tables. */ void -m32r_cgen_init_ibld_table (cd) - CGEN_CPU_DESC cd; +m32r_cgen_init_ibld_table (CGEN_CPU_DESC cd) { cd->insert_handlers = & m32r_cgen_insert_handlers[0]; cd->extract_handlers = & m32r_cgen_extract_handlers[0]; diff -uprN binutils-2.16.91.0.1/opcodes/m32r-opc.c binutils-2.16.91.0.2/opcodes/m32r-opc.c --- binutils-2.16.91.0.1/opcodes/m32r-opc.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/m32r-opc.c 2005-07-20 12:27:29.263868081 -0700 @@ -32,36 +32,34 @@ with this program; if not, write to the /* -- opc.c */ unsigned int -m32r_cgen_dis_hash (buf, value) - const char * buf ATTRIBUTE_UNUSED; - CGEN_INSN_INT value; +m32r_cgen_dis_hash (const char * buf ATTRIBUTE_UNUSED, CGEN_INSN_INT value) { unsigned int x; - - if (value & 0xffff0000) /* 32bit instructions */ + + if (value & 0xffff0000) /* 32bit instructions. */ value = (value >> 16) & 0xffff; - - x = (value>>8) & 0xf0; + + x = (value >> 8) & 0xf0; if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50) return x; - + if (x == 0x70 || x == 0xf0) - return x | ((value>>8) & 0x0f); - + return x | ((value >> 8) & 0x0f); + if (x == 0x30) return x | ((value & 0x70) >> 4); else return x | ((value & 0xf0) >> 4); } - + /* -- */ /* The hash functions are recorded here to help keep assembler code out of the disassembler and vice versa. */ -static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int asm_hash_insn PARAMS ((const char *)); -static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); /* Instruction formats. */ @@ -1778,14 +1776,10 @@ dis_hash_insn (buf, value) return CGEN_DIS_HASH (buf, value); } -static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int)); - /* Set the recorded length of the insn in the CGEN_FIELDS struct. */ static void -set_fields_bitsize (fields, size) - CGEN_FIELDS *fields; - int size; +set_fields_bitsize (CGEN_FIELDS *fields, int size) { CGEN_FIELDS_BITSIZE (fields) = size; } @@ -1794,15 +1788,15 @@ set_fields_bitsize (fields, size) This plugs the opcode entries and macro instructions into the cpu table. */ void -m32r_cgen_init_opcode_table (cd) - CGEN_CPU_DESC cd; +m32r_cgen_init_opcode_table (CGEN_CPU_DESC cd) { int i; int num_macros = (sizeof (m32r_cgen_macro_insn_table) / sizeof (m32r_cgen_macro_insn_table[0])); const CGEN_IBASE *ib = & m32r_cgen_macro_insn_table[0]; const CGEN_OPCODE *oc = & m32r_cgen_macro_insn_opcode_table[0]; - CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN)); + CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); for (i = 0; i < num_macros; ++i) { diff -uprN binutils-2.16.91.0.1/opcodes/m32r-opc.h binutils-2.16.91.0.2/opcodes/m32r-opc.h --- binutils-2.16.91.0.1/opcodes/m32r-opc.h 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/m32r-opc.h 2005-07-20 12:27:29.263868081 -0700 @@ -39,8 +39,8 @@ with this program; if not, write to the : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \ : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4))) #else -#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash(buffer, value) -extern unsigned int m32r_cgen_dis_hash(const char *, CGEN_INSN_INT); +#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash (buffer, value) +extern unsigned int m32r_cgen_dis_hash (const char *, CGEN_INSN_INT); #endif /* -- */ diff -uprN binutils-2.16.91.0.1/opcodes/m68k-dis.c binutils-2.16.91.0.2/opcodes/m68k-dis.c --- binutils-2.16.91.0.1/opcodes/m68k-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/m68k-dis.c 2005-07-20 12:27:29.267867421 -0700 @@ -1,6 +1,6 @@ /* Print Motorola 68k instructions. Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, - 1998, 1999, 2000, 2001, 2002, 2003, 2004 + 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify @@ -15,7 +15,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "sysdep.h" #include "dis-asm.h" @@ -25,49 +26,28 @@ #include "opcode/m68k.h" -/* Local function prototypes */ - -static int -fetch_data PARAMS ((struct disassemble_info *, bfd_byte *)); - -static void -dummy_print_address PARAMS ((bfd_vma, struct disassemble_info *)); - -static int -fetch_arg PARAMS ((unsigned char *, int, int, disassemble_info *)); - -static void -print_base PARAMS ((int, bfd_vma, disassemble_info *)); - -static unsigned char * -print_indexed PARAMS ((int, unsigned char *, bfd_vma, disassemble_info *)); - -static int -print_insn_arg PARAMS ((const char *, unsigned char *, unsigned char *, - bfd_vma, disassemble_info *)); - -static bfd_boolean m68k_valid_ea (char code, int val); +/* Local function prototypes. */ const char * const fpcr_names[] = { - "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr", - "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr" + "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr", + "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr" }; static char *const reg_names[] = { - "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", - "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp", - "%ps", "%pc" + "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", + "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp", + "%ps", "%pc" }; /* Name of register halves for MAC/EMAC. Seperate from reg_names since 'spu', 'fpl' look weird. */ static char *const reg_half_names[] = { - "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", - "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%a7", - "%ps", "%pc" + "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", + "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%a7", + "%ps", "%pc" }; /* Sign-extend an (unsigned char). */ @@ -124,7 +104,8 @@ static char *const reg_half_names[] = #include -struct private { +struct private +{ /* Points to first byte not fetched. */ bfd_byte *max_fetched; bfd_byte the_buffer[MAXLEN]; @@ -140,9 +121,7 @@ struct private { ? 1 : fetch_data ((info), (addr))) static int -fetch_data (info, addr) - struct disassemble_info *info; - bfd_byte *addr; +fetch_data (struct disassemble_info *info, bfd_byte *addr) { int status; struct private *priv = (struct private *)info->private_data; @@ -162,349 +141,437 @@ fetch_data (info, addr) return 1; } -/* This function is used to print to the bit-bucket. */ +/* This function is used to print to the bit-bucket. */ static int -#ifdef __STDC__ dummy_printer (FILE *file ATTRIBUTE_UNUSED, - const char *format ATTRIBUTE_UNUSED, ...) -#else -dummy_printer (file) - FILE *file ATTRIBUTE_UNUSED; -#endif + const char *format ATTRIBUTE_UNUSED, + ...) { return 0; } static void -dummy_print_address (vma, info) - bfd_vma vma ATTRIBUTE_UNUSED; - struct disassemble_info *info ATTRIBUTE_UNUSED; +dummy_print_address (bfd_vma vma ATTRIBUTE_UNUSED, + struct disassemble_info *info ATTRIBUTE_UNUSED) { } -/* Try to match the current instruction to best and if so, return the - number of bytes consumed from the instruction stream, else zero. */ +/* Fetch BITS bits from a position in the instruction specified by CODE. + CODE is a "place to put an argument", or 'x' for a destination + that is a general address (mode and register). + BUFFER contains the instruction. */ static int -match_insn_m68k (bfd_vma memaddr, disassemble_info * info, - const struct m68k_opcode * best, struct private * priv) +fetch_arg (unsigned char *buffer, + int code, + int bits, + disassemble_info *info) { - unsigned char *save_p; - unsigned char *p; - const char *d; - - bfd_byte *buffer = priv->the_buffer; - fprintf_ftype save_printer = info->fprintf_func; - void (* save_print_address) (bfd_vma, struct disassemble_info *) - = info->print_address_func; - - /* Point at first word of argument data, - and at descriptor for first argument. */ - p = buffer + 2; + int val = 0; - /* Figure out how long the fixed-size portion of the instruction is. - The only place this is stored in the opcode table is - in the arguments--look for arguments which specify fields in the 2nd - or 3rd words of the instruction. */ - for (d = best->args; *d; d += 2) + switch (code) { - /* I don't think it is necessary to be checking d[0] here; - I suspect all this could be moved to the case statement below. */ - if (d[0] == '#') - { - if (d[1] == 'l' && p - buffer < 6) - p = buffer + 6; - else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8') - p = buffer + 4; - } - - if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4) - p = buffer + 4; + case '/': /* MAC/EMAC mask bit. */ + val = buffer[3] >> 5; + break; - switch (d[1]) - { - case '1': - case '2': - case '3': - case '7': - case '8': - case '9': - case 'i': - if (p - buffer < 4) - p = buffer + 4; - break; - case '4': - case '5': - case '6': - if (p - buffer < 6) - p = buffer + 6; - break; - default: - break; - } - } + case 'G': /* EMAC ACC load. */ + val = ((buffer[3] >> 3) & 0x2) | ((~buffer[1] >> 7) & 0x1); + break; - /* pflusha is an exceptions. It takes no arguments but is two words - long. Recognize it by looking at the lower 16 bits of the mask. */ - if (p - buffer < 4 && (best->match & 0xFFFF) != 0) - p = buffer + 4; + case 'H': /* EMAC ACC !load. */ + val = ((buffer[3] >> 3) & 0x2) | ((buffer[1] >> 7) & 0x1); + break; - /* lpstop is another exception. It takes a one word argument but is - three words long. */ - if (p - buffer < 6 - && (best->match & 0xffff) == 0xffff - && best->args[0] == '#' - && best->args[1] == 'w') - { - /* Copy the one word argument into the usual location for a one - word argument, to simplify printing it. We can get away with - this because we know exactly what the second word is, and we - aren't going to print anything based on it. */ - p = buffer + 6; - FETCH_DATA (info, p); - buffer[2] = buffer[4]; - buffer[3] = buffer[5]; - } + case ']': /* EMAC ACCEXT bit. */ + val = buffer[0] >> 2; + break; - FETCH_DATA (info, p); + case 'I': /* MAC/EMAC scale factor. */ + val = buffer[2] >> 1; + break; - d = best->args; + case 'F': /* EMAC ACCx. */ + val = buffer[0] >> 1; + break; - save_p = p; - info->print_address_func = dummy_print_address; - info->fprintf_func = (fprintf_ftype) dummy_printer; + case 'f': + val = buffer[1]; + break; - /* We scan the operands twice. The first time we don't print anything, - but look for errors. */ - for (; *d; d += 2) - { - int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info); + case 's': + val = buffer[1]; + break; - if (eaten >= 0) - p += eaten; - else if (eaten == -1) - { - info->fprintf_func = save_printer; - info->print_address_func = save_print_address; - return 0; - } - else - { - info->fprintf_func (info->stream, - /* xgettext:c-format */ - _("\n"), - best->name, best->args); - info->fprintf_func = save_printer; - info->print_address_func = save_print_address; - return 2; - } - } + case 'd': /* Destination, for register or quick. */ + val = (buffer[0] << 8) + buffer[1]; + val >>= 9; + break; - p = save_p; - info->fprintf_func = save_printer; - info->print_address_func = save_print_address; + case 'x': /* Destination, for general arg. */ + val = (buffer[0] << 8) + buffer[1]; + val >>= 6; + break; - d = best->args; + case 'k': + FETCH_DATA (info, buffer + 3); + val = (buffer[3] >> 4); + break; - info->fprintf_func (info->stream, "%s", best->name); + case 'C': + FETCH_DATA (info, buffer + 3); + val = buffer[3]; + break; - if (*d) - info->fprintf_func (info->stream, " "); + case '1': + FETCH_DATA (info, buffer + 3); + val = (buffer[2] << 8) + buffer[3]; + val >>= 12; + break; - while (*d) - { - p += print_insn_arg (d, buffer, p, memaddr + (p - buffer), info); - d += 2; + case '2': + FETCH_DATA (info, buffer + 3); + val = (buffer[2] << 8) + buffer[3]; + val >>= 6; + break; - if (*d && *(d - 2) != 'I' && *d != 'k') - info->fprintf_func (info->stream, ","); - } + case '3': + case 'j': + FETCH_DATA (info, buffer + 3); + val = (buffer[2] << 8) + buffer[3]; + break; - return p - buffer; -} + case '4': + FETCH_DATA (info, buffer + 5); + val = (buffer[4] << 8) + buffer[5]; + val >>= 12; + break; -/* Print the m68k instruction at address MEMADDR in debugged memory, - on INFO->STREAM. Returns length of the instruction, in bytes. */ + case '5': + FETCH_DATA (info, buffer + 5); + val = (buffer[4] << 8) + buffer[5]; + val >>= 6; + break; -int -print_insn_m68k (memaddr, info) - bfd_vma memaddr; - disassemble_info *info; -{ - int i; - const char *d; - unsigned int arch_mask; - struct private priv; - bfd_byte *buffer = priv.the_buffer; - int major_opcode; - static int numopcodes[16]; - static const struct m68k_opcode **opcodes[16]; - int val; + case '6': + FETCH_DATA (info, buffer + 5); + val = (buffer[4] << 8) + buffer[5]; + break; - if (!opcodes[0]) - { - /* Speed up the matching by sorting the opcode - table on the upper four bits of the opcode. */ - const struct m68k_opcode **opc_pointer[16]; + case '7': + FETCH_DATA (info, buffer + 3); + val = (buffer[2] << 8) + buffer[3]; + val >>= 7; + break; - /* First count how many opcodes are in each of the sixteen buckets. */ - for (i = 0; i < m68k_numopcodes; i++) - numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++; + case '8': + FETCH_DATA (info, buffer + 3); + val = (buffer[2] << 8) + buffer[3]; + val >>= 10; + break; - /* Then create a sorted table of pointers - that point into the unsorted table. */ - opc_pointer[0] = xmalloc (sizeof (struct m68k_opcode *) - * m68k_numopcodes); - opcodes[0] = opc_pointer[0]; + case '9': + FETCH_DATA (info, buffer + 3); + val = (buffer[2] << 8) + buffer[3]; + val >>= 5; + break; - for (i = 1; i < 16; i++) - { - opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1]; - opcodes[i] = opc_pointer[i]; - } + case 'e': + val = (buffer[1] >> 6); + break; - for (i = 0; i < m68k_numopcodes; i++) - *opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i]; - } + case 'm': + val = (buffer[1] & 0x40 ? 0x8 : 0) + | ((buffer[0] >> 1) & 0x7) + | (buffer[3] & 0x80 ? 0x10 : 0); + break; - info->private_data = (PTR) &priv; - /* Tell objdump to use two bytes per chunk - and six bytes per line for displaying raw data. */ - info->bytes_per_chunk = 2; - info->bytes_per_line = 6; - info->display_endian = BFD_ENDIAN_BIG; - priv.max_fetched = priv.the_buffer; - priv.insn_start = memaddr; + case 'n': + val = (buffer[1] & 0x40 ? 0x8 : 0) | ((buffer[0] >> 1) & 0x7); + break; - if (setjmp (priv.bailout) != 0) - /* Error return. */ - return -1; + case 'o': + val = (buffer[2] >> 4) | (buffer[3] & 0x80 ? 0x10 : 0); + break; - switch (info->mach) + case 'M': + val = (buffer[1] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0); + break; + + case 'N': + val = (buffer[3] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0); + break; + + case 'h': + val = buffer[2] >> 2; + break; + + default: + abort (); + } + + switch (bits) { + case 1: + return val & 1; + case 2: + return val & 3; + case 3: + return val & 7; + case 4: + return val & 017; + case 5: + return val & 037; + case 6: + return val & 077; + case 7: + return val & 0177; + case 8: + return val & 0377; + case 12: + return val & 07777; default: - case 0: - arch_mask = (unsigned int) -1; + abort (); + } +} + +/* Check if an EA is valid for a particular code. This is required + for the EMAC instructions since the type of source address determines + if it is a EMAC-load instruciton if the EA is mode 2-5, otherwise it + is a non-load EMAC instruction and the bits mean register Ry. + A similar case exists for the movem instructions where the register + mask is interpreted differently for different EAs. */ + +static bfd_boolean +m68k_valid_ea (char code, int val) +{ + int mode, mask; +#define M(n0,n1,n2,n3,n4,n5,n6,n70,n71,n72,n73,n74) \ + (n0 | n1 << 1 | n2 << 2 | n3 << 3 | n4 << 4 | n5 << 5 | n6 << 6 \ + | n70 << 7 | n71 << 8 | n72 << 9 | n73 << 10 | n74 << 11) + + switch (code) + { + case '*': + mask = M (1,1,1,1,1,1,1,1,1,1,1,1); break; - case bfd_mach_m68000: - arch_mask = m68000|m68881|m68851; + case '~': + mask = M (0,0,1,1,1,1,1,1,1,0,0,0); break; - case bfd_mach_m68008: - arch_mask = m68008|m68881|m68851; + case '%': + mask = M (1,1,1,1,1,1,1,1,1,0,0,0); break; - case bfd_mach_m68010: - arch_mask = m68010|m68881|m68851; + case ';': + mask = M (1,0,1,1,1,1,1,1,1,1,1,1); break; - case bfd_mach_m68020: - arch_mask = m68020|m68881|m68851; + case '@': + mask = M (1,0,1,1,1,1,1,1,1,1,1,0); break; - case bfd_mach_m68030: - arch_mask = m68030|m68881|m68851; + case '!': + mask = M (0,0,1,0,0,1,1,1,1,1,1,0); break; - case bfd_mach_m68040: - arch_mask = m68040|m68881|m68851; + case '&': + mask = M (0,0,1,0,0,1,1,1,1,0,0,0); break; - case bfd_mach_m68060: - arch_mask = m68060|m68881|m68851; + case '$': + mask = M (1,0,1,1,1,1,1,1,1,0,0,0); break; - case bfd_mach_mcf5200: - arch_mask = mcfisa_a; + case '?': + mask = M (1,0,1,0,0,1,1,1,1,0,0,0); break; - case bfd_mach_mcf521x: - case bfd_mach_mcf528x: - arch_mask = mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp|mcfemac; + case '/': + mask = M (1,0,1,0,0,1,1,1,1,1,1,0); break; - case bfd_mach_mcf5206e: - arch_mask = mcfisa_a|mcfhwdiv|mcfmac; + case '|': + mask = M (0,0,1,0,0,1,1,1,1,1,1,0); break; - case bfd_mach_mcf5249: - arch_mask = mcfisa_a|mcfhwdiv|mcfemac; + case '>': + mask = M (0,0,1,0,1,1,1,1,1,0,0,0); break; - case bfd_mach_mcf5307: - arch_mask = mcfisa_a|mcfhwdiv|mcfmac; + case '<': + mask = M (0,0,1,1,0,1,1,1,1,1,1,0); break; - case bfd_mach_mcf5407: - arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac; + case 'm': + mask = M (1,1,1,1,1,0,0,0,0,0,0,0); break; - case bfd_mach_mcf547x: - case bfd_mach_mcf548x: - case bfd_mach_mcfv4e: - arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp|cfloat|mcfemac; + case 'n': + mask = M (0,0,0,0,0,1,0,0,0,1,0,0); + break; + case 'o': + mask = M (0,0,0,0,0,0,1,1,1,0,1,1); + break; + case 'p': + mask = M (1,1,1,1,1,1,0,0,0,0,0,0); + break; + case 'q': + mask = M (1,0,1,1,1,1,0,0,0,0,0,0); + break; + case 'v': + mask = M (1,0,1,1,1,1,0,1,1,0,0,0); + break; + case 'b': + mask = M (1,0,1,1,1,1,0,0,0,1,0,0); break; + case 'w': + mask = M (0,0,1,1,1,1,0,0,0,1,0,0); + break; + case 'y': + mask = M (0,0,1,0,0,1,0,0,0,0,0,0); + break; + case 'z': + mask = M (0,0,1,0,0,1,0,0,0,1,0,0); + break; + case '4': + mask = M (0,0,1,1,1,1,0,0,0,0,0,0); + break; + default: + abort (); } +#undef M - FETCH_DATA (info, buffer + 2); - major_opcode = (buffer[0] >> 4) & 15; - - for (i = 0; i < numopcodes[major_opcode]; i++) - { - const struct m68k_opcode *opc = opcodes[major_opcode][i]; - unsigned long opcode = opc->opcode; - unsigned long match = opc->match; + mode = (val >> 3) & 7; + if (mode == 7) + mode += val & 7; + return (mask & (1 << mode)) != 0; +} - if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24))) - && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16))) - /* Only fetch the next two bytes if we need to. */ - && (((0xffff & match) == 0) - || - (FETCH_DATA (info, buffer + 4) - && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8))) - && ((0xff & buffer[3] & match) == (0xff & opcode))) - ) - && (opc->arch & arch_mask) != 0) - { - /* Don't use for printout the variants of divul and divsl - that have the same register number in two places. - The more general variants will match instead. */ - for (d = opc->args; *d; d += 2) - if (d[1] == 'D') - break; +/* Print a base register REGNO and displacement DISP, on INFO->STREAM. + REGNO = -1 for pc, -2 for none (suppressed). */ - /* Don't use for printout the variants of most floating - point coprocessor instructions which use the same - register number in two places, as above. */ - if (*d == '\0') - for (d = opc->args; *d; d += 2) - if (d[1] == 't') - break; +static void +print_base (int regno, bfd_vma disp, disassemble_info *info) +{ + if (regno == -1) + { + (*info->fprintf_func) (info->stream, "%%pc@("); + (*info->print_address_func) (disp, info); + } + else + { + char buf[50]; - /* Don't match fmovel with more than one register; - wait for fmoveml. */ - if (*d == '\0') - { - for (d = opc->args; *d; d += 2) - { - if (d[0] == 's' && d[1] == '8') - { - val = fetch_arg (buffer, d[1], 3, info); - if ((val & (val - 1)) != 0) - break; - } - } - } + if (regno == -2) + (*info->fprintf_func) (info->stream, "@("); + else if (regno == -3) + (*info->fprintf_func) (info->stream, "%%zpc@("); + else + (*info->fprintf_func) (info->stream, "%s@(", reg_names[regno]); - if (*d == '\0') - if ((val = match_insn_m68k (memaddr, info, opc, & priv))) - return val; - } + sprintf_vma (buf, disp); + (*info->fprintf_func) (info->stream, "%s", buf); } - - /* Handle undefined instructions. */ - info->fprintf_func (info->stream, "0%o", (buffer[0] << 8) + buffer[1]); - return 2; } -/* Returns number of bytes "eaten" by the operand, or - return -1 if an invalid operand was found, or -2 if - an opcode tabe error was found. */ +/* Print an indexed argument. The base register is BASEREG (-1 for pc). + P points to extension word, in buffer. + ADDR is the nominal core address of that extension word. */ + +static unsigned char * +print_indexed (int basereg, + unsigned char *p, + bfd_vma addr, + disassemble_info *info) +{ + int word; + static char *const scales[] = { "", ":2", ":4", ":8" }; + bfd_vma base_disp; + bfd_vma outer_disp; + char buf[40]; + char vmabuf[50]; + + word = NEXTWORD (p); + + /* Generate the text for the index register. + Where this will be output is not yet determined. */ + sprintf (buf, "%s:%c%s", + reg_names[(word >> 12) & 0xf], + (word & 0x800) ? 'l' : 'w', + scales[(word >> 9) & 3]); + + /* Handle the 68000 style of indexing. */ + + if ((word & 0x100) == 0) + { + base_disp = word & 0xff; + if ((base_disp & 0x80) != 0) + base_disp -= 0x100; + if (basereg == -1) + base_disp += addr; + print_base (basereg, base_disp, info); + (*info->fprintf_func) (info->stream, ",%s)", buf); + return p; + } + + /* Handle the generalized kind. */ + /* First, compute the displacement to add to the base register. */ + if (word & 0200) + { + if (basereg == -1) + basereg = -3; + else + basereg = -2; + } + if (word & 0100) + buf[0] = '\0'; + base_disp = 0; + switch ((word >> 4) & 3) + { + case 2: + base_disp = NEXTWORD (p); + break; + case 3: + base_disp = NEXTLONG (p); + } + if (basereg == -1) + base_disp += addr; + + /* Handle single-level case (not indirect). */ + if ((word & 7) == 0) + { + print_base (basereg, base_disp, info); + if (buf[0] != '\0') + (*info->fprintf_func) (info->stream, ",%s", buf); + (*info->fprintf_func) (info->stream, ")"); + return p; + } + + /* Two level. Compute displacement to add after indirection. */ + outer_disp = 0; + switch (word & 3) + { + case 2: + outer_disp = NEXTWORD (p); + break; + case 3: + outer_disp = NEXTLONG (p); + } + + print_base (basereg, base_disp, info); + if ((word & 4) == 0 && buf[0] != '\0') + { + (*info->fprintf_func) (info->stream, ",%s", buf); + buf[0] = '\0'; + } + sprintf_vma (vmabuf, outer_disp); + (*info->fprintf_func) (info->stream, ")@(%s", vmabuf); + if (buf[0] != '\0') + (*info->fprintf_func) (info->stream, ",%s", buf); + (*info->fprintf_func) (info->stream, ")"); + + return p; +} + +/* Returns number of bytes "eaten" by the operand, or + return -1 if an invalid operand was found, or -2 if + an opcode tabe error was found. + ADDR is the pc for this arg to be relative to. */ static int -print_insn_arg (d, buffer, p0, addr, info) - const char *d; - unsigned char *buffer; - unsigned char *p0; - bfd_vma addr; /* PC for this arg to be relative to. */ - disassemble_info *info; +print_insn_arg (const char *d, + unsigned char *buffer, + unsigned char *p0, + bfd_vma addr, + disassemble_info *info) { int val = 0; int place = d[1]; @@ -693,7 +760,7 @@ print_insn_arg (d, buffer, p0, addr, inf else if (place == 'C') { val = fetch_arg (buffer, place, 7, info); - if (val > 63) /* This is a signed constant. */ + if (val > 63) /* This is a signed constant. */ val -= 128; (*info->fprintf_func) (info->stream, "{#%d}", val); } @@ -742,7 +809,7 @@ print_insn_arg (d, buffer, p0, addr, inf } else if (place == 'c') { - if (buffer[1] & 0x40) /* If bit six is one, long offset */ + if (buffer[1] & 0x40) /* If bit six is one, long offset. */ disp = NEXTLONG (p); else disp = NEXTWORD (p); @@ -774,7 +841,7 @@ print_insn_arg (d, buffer, p0, addr, inf val = fetch_arg(buffer, place, 1, info); (*info->fprintf_func) (info->stream, "%%accext%s", val==0 ? "01" : "23"); break; - + case 'i': val = fetch_arg(buffer, place, 2, info); if (val == 1) @@ -789,7 +856,7 @@ print_insn_arg (d, buffer, p0, addr, inf /* Get coprocessor ID... */ val = fetch_arg (buffer, 'd', 3, info); - if (val != 1) /* Unusual coprocessor ID? */ + if (val != 1) /* Unusual coprocessor ID? */ (*info->fprintf_func) (info->stream, "(cpid=%d) ", val); break; @@ -964,7 +1031,8 @@ print_insn_arg (d, buffer, p0, addr, inf } if (*d == 'l') { - register int newval = 0; + int newval = 0; + for (regno = 0; regno < 16; ++regno) if (val & (0x8000 >> regno)) newval |= 1 << regno; @@ -976,6 +1044,7 @@ print_insn_arg (d, buffer, p0, addr, inf if (val & (1 << regno)) { int first_regno; + if (doneany) (*info->fprintf_func) (info->stream, "/"); doneany = 1; @@ -1000,7 +1069,8 @@ print_insn_arg (d, buffer, p0, addr, inf } if (*d == 'l') { - register int newval = 0; + int newval = 0; + for (regno = 0; regno < 8; ++regno) if (val & (0x80 >> regno)) newval |= 1 << regno; @@ -1025,7 +1095,7 @@ print_insn_arg (d, buffer, p0, addr, inf } else if (place == '8') { - /* fmoveml for FP status registers */ + /* fmoveml for FP status registers. */ (*info->fprintf_func) (info->stream, "%s", fpcr_names[fetch_arg (buffer, place, 3, info)]); @@ -1046,6 +1116,7 @@ print_insn_arg (d, buffer, p0, addr, inf { int val = fetch_arg (buffer, place, 5, info); char *name = 0; + switch (val) { case 2: name = "%tt0"; break; @@ -1064,6 +1135,7 @@ print_insn_arg (d, buffer, p0, addr, inf case 0x1d: { int break_reg = ((buffer[3] >> 2) & 7); + (*info->fprintf_func) (info->stream, val == 0x1c ? "%%bad%d" : "%%bac%d", break_reg); @@ -1080,6 +1152,7 @@ print_insn_arg (d, buffer, p0, addr, inf case 'f': { int fc = fetch_arg (buffer, place, 5, info); + if (fc == 1) (*info->fprintf_func) (info->stream, "%%dfc"); else if (fc == 0) @@ -1097,6 +1170,7 @@ print_insn_arg (d, buffer, p0, addr, inf case 't': { int level = fetch_arg (buffer, place, 3, info); + (*info->fprintf_func) (info->stream, "%d", level); } break; @@ -1124,415 +1198,314 @@ print_insn_arg (d, buffer, p0, addr, inf return p - p0; } -/* Check if an EA is valid for a particular code. This is required - for the EMAC instructions since the type of source address determines - if it is a EMAC-load instruciton if the EA is mode 2-5, otherwise it - is a non-load EMAC instruction and the bits mean register Ry. - A similar case exists for the movem instructions where the register - mask is interpreted differently for different EAs. */ - -static bfd_boolean -m68k_valid_ea (char code, int val) -{ - int mode, mask; -#define M(n0,n1,n2,n3,n4,n5,n6,n70,n71,n72,n73,n74) \ - (n0 | n1 << 1 | n2 << 2 | n3 << 3 | n4 << 4 | n5 << 5 | n6 << 6 \ - | n70 << 7 | n71 << 8 | n72 << 9 | n73 << 10 | n74 << 11) - - switch (code) - { - case '*': - mask = M (1,1,1,1,1,1,1,1,1,1,1,1); - break; - case '~': - mask = M (0,0,1,1,1,1,1,1,1,0,0,0); - break; - case '%': - mask = M (1,1,1,1,1,1,1,1,1,0,0,0); - break; - case ';': - mask = M (1,0,1,1,1,1,1,1,1,1,1,1); - break; - case '@': - mask = M (1,0,1,1,1,1,1,1,1,1,1,0); - break; - case '!': - mask = M (0,0,1,0,0,1,1,1,1,1,1,0); - break; - case '&': - mask = M (0,0,1,0,0,1,1,1,1,0,0,0); - break; - case '$': - mask = M (1,0,1,1,1,1,1,1,1,0,0,0); - break; - case '?': - mask = M (1,0,1,0,0,1,1,1,1,0,0,0); - break; - case '/': - mask = M (1,0,1,0,0,1,1,1,1,1,1,0); - break; - case '|': - mask = M (0,0,1,0,0,1,1,1,1,1,1,0); - break; - case '>': - mask = M (0,0,1,0,1,1,1,1,1,0,0,0); - break; - case '<': - mask = M (0,0,1,1,0,1,1,1,1,1,1,0); - break; - case 'm': - mask = M (1,1,1,1,1,0,0,0,0,0,0,0); - break; - case 'n': - mask = M (0,0,0,0,0,1,0,0,0,1,0,0); - break; - case 'o': - mask = M (0,0,0,0,0,0,1,1,1,0,1,1); - break; - case 'p': - mask = M (1,1,1,1,1,1,0,0,0,0,0,0); - break; - case 'q': - mask = M (1,0,1,1,1,1,0,0,0,0,0,0); - break; - case 'v': - mask = M (1,0,1,1,1,1,0,1,1,0,0,0); - break; - case 'b': - mask = M (1,0,1,1,1,1,0,0,0,1,0,0); - break; - case 'w': - mask = M (0,0,1,1,1,1,0,0,0,1,0,0); - break; - case 'y': - mask = M (0,0,1,0,0,1,0,0,0,0,0,0); - break; - case 'z': - mask = M (0,0,1,0,0,1,0,0,0,1,0,0); - break; - case '4': - mask = M (0,0,1,1,1,1,0,0,0,0,0,0); - break; - default: - abort (); - } -#undef M - - mode = (val >> 3) & 7; - if (mode == 7) - mode += val & 7; - return (mask & (1 << mode)) != 0; -} - -/* Fetch BITS bits from a position in the instruction specified by CODE. - CODE is a "place to put an argument", or 'x' for a destination - that is a general address (mode and register). - BUFFER contains the instruction. */ +/* Try to match the current instruction to best and if so, return the + number of bytes consumed from the instruction stream, else zero. */ static int -fetch_arg (buffer, code, bits, info) - unsigned char *buffer; - int code; - int bits; - disassemble_info *info; +match_insn_m68k (bfd_vma memaddr, + disassemble_info * info, + const struct m68k_opcode * best, + struct private * priv) { - int val = 0; - - switch (code) - { - case '/': /* MAC/EMAC mask bit. */ - val = buffer[3] >> 5; - break; + unsigned char *save_p; + unsigned char *p; + const char *d; - case 'G': /* EMAC ACC load. */ - val = ((buffer[3] >> 3) & 0x2) | ((~buffer[1] >> 7) & 0x1); - break; + bfd_byte *buffer = priv->the_buffer; + fprintf_ftype save_printer = info->fprintf_func; + void (* save_print_address) (bfd_vma, struct disassemble_info *) + = info->print_address_func; - case 'H': /* EMAC ACC !load. */ - val = ((buffer[3] >> 3) & 0x2) | ((buffer[1] >> 7) & 0x1); - break; + /* Point at first word of argument data, + and at descriptor for first argument. */ + p = buffer + 2; - case ']': /* EMAC ACCEXT bit. */ - val = buffer[0] >> 2; - break; + /* Figure out how long the fixed-size portion of the instruction is. + The only place this is stored in the opcode table is + in the arguments--look for arguments which specify fields in the 2nd + or 3rd words of the instruction. */ + for (d = best->args; *d; d += 2) + { + /* I don't think it is necessary to be checking d[0] here; + I suspect all this could be moved to the case statement below. */ + if (d[0] == '#') + { + if (d[1] == 'l' && p - buffer < 6) + p = buffer + 6; + else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8') + p = buffer + 4; + } - case 'I': /* MAC/EMAC scale factor. */ - val = buffer[2] >> 1; - break; + if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4) + p = buffer + 4; - case 'F': /* EMAC ACCx. */ - val = buffer[0] >> 1; - break; - - case 'f': - val = buffer[1]; - break; - - case 's': - val = buffer[1]; - break; - - case 'd': /* Destination, for register or quick. */ - val = (buffer[0] << 8) + buffer[1]; - val >>= 9; - break; - - case 'x': /* Destination, for general arg */ - val = (buffer[0] << 8) + buffer[1]; - val >>= 6; - break; - - case 'k': - FETCH_DATA (info, buffer + 3); - val = (buffer[3] >> 4); - break; - - case 'C': - FETCH_DATA (info, buffer + 3); - val = buffer[3]; - break; - - case '1': - FETCH_DATA (info, buffer + 3); - val = (buffer[2] << 8) + buffer[3]; - val >>= 12; - break; - - case '2': - FETCH_DATA (info, buffer + 3); - val = (buffer[2] << 8) + buffer[3]; - val >>= 6; - break; - - case '3': - case 'j': - FETCH_DATA (info, buffer + 3); - val = (buffer[2] << 8) + buffer[3]; - break; - - case '4': - FETCH_DATA (info, buffer + 5); - val = (buffer[4] << 8) + buffer[5]; - val >>= 12; - break; + switch (d[1]) + { + case '1': + case '2': + case '3': + case '7': + case '8': + case '9': + case 'i': + if (p - buffer < 4) + p = buffer + 4; + break; + case '4': + case '5': + case '6': + if (p - buffer < 6) + p = buffer + 6; + break; + default: + break; + } + } - case '5': - FETCH_DATA (info, buffer + 5); - val = (buffer[4] << 8) + buffer[5]; - val >>= 6; - break; + /* pflusha is an exceptions. It takes no arguments but is two words + long. Recognize it by looking at the lower 16 bits of the mask. */ + if (p - buffer < 4 && (best->match & 0xFFFF) != 0) + p = buffer + 4; - case '6': - FETCH_DATA (info, buffer + 5); - val = (buffer[4] << 8) + buffer[5]; - break; + /* lpstop is another exception. It takes a one word argument but is + three words long. */ + if (p - buffer < 6 + && (best->match & 0xffff) == 0xffff + && best->args[0] == '#' + && best->args[1] == 'w') + { + /* Copy the one word argument into the usual location for a one + word argument, to simplify printing it. We can get away with + this because we know exactly what the second word is, and we + aren't going to print anything based on it. */ + p = buffer + 6; + FETCH_DATA (info, p); + buffer[2] = buffer[4]; + buffer[3] = buffer[5]; + } - case '7': - FETCH_DATA (info, buffer + 3); - val = (buffer[2] << 8) + buffer[3]; - val >>= 7; - break; + FETCH_DATA (info, p); - case '8': - FETCH_DATA (info, buffer + 3); - val = (buffer[2] << 8) + buffer[3]; - val >>= 10; - break; + d = best->args; - case '9': - FETCH_DATA (info, buffer + 3); - val = (buffer[2] << 8) + buffer[3]; - val >>= 5; - break; + save_p = p; + info->print_address_func = dummy_print_address; + info->fprintf_func = (fprintf_ftype) dummy_printer; - case 'e': - val = (buffer[1] >> 6); - break; + /* We scan the operands twice. The first time we don't print anything, + but look for errors. */ + for (; *d; d += 2) + { + int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info); - case 'm': - val = (buffer[1] & 0x40 ? 0x8 : 0) - | ((buffer[0] >> 1) & 0x7) - | (buffer[3] & 0x80 ? 0x10 : 0); - break; + if (eaten >= 0) + p += eaten; + else if (eaten == -1) + { + info->fprintf_func = save_printer; + info->print_address_func = save_print_address; + return 0; + } + else + { + info->fprintf_func (info->stream, + /* xgettext:c-format */ + _("\n"), + best->name, best->args); + info->fprintf_func = save_printer; + info->print_address_func = save_print_address; + return 2; + } + } - case 'n': - val = (buffer[1] & 0x40 ? 0x8 : 0) | ((buffer[0] >> 1) & 0x7); - break; + p = save_p; + info->fprintf_func = save_printer; + info->print_address_func = save_print_address; - case 'o': - val = (buffer[2] >> 4) | (buffer[3] & 0x80 ? 0x10 : 0); - break; + d = best->args; - case 'M': - val = (buffer[1] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0); - break; + info->fprintf_func (info->stream, "%s", best->name); - case 'N': - val = (buffer[3] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0); - break; + if (*d) + info->fprintf_func (info->stream, " "); - case 'h': - val = buffer[2] >> 2; - break; + while (*d) + { + p += print_insn_arg (d, buffer, p, memaddr + (p - buffer), info); + d += 2; - default: - abort (); + if (*d && *(d - 2) != 'I' && *d != 'k') + info->fprintf_func (info->stream, ","); } - switch (bits) - { - case 1: - return val & 1; - case 2: - return val & 3; - case 3: - return val & 7; - case 4: - return val & 017; - case 5: - return val & 037; - case 6: - return val & 077; - case 7: - return val & 0177; - case 8: - return val & 0377; - case 12: - return val & 07777; - default: - abort (); - } + return p - buffer; } -/* Print an indexed argument. The base register is BASEREG (-1 for pc). - P points to extension word, in buffer. - ADDR is the nominal core address of that extension word. */ +/* Print the m68k instruction at address MEMADDR in debugged memory, + on INFO->STREAM. Returns length of the instruction, in bytes. */ -static unsigned char * -print_indexed (basereg, p, addr, info) - int basereg; - unsigned char *p; - bfd_vma addr; - disassemble_info *info; +int +print_insn_m68k (bfd_vma memaddr, disassemble_info *info) { - int word; - static char *const scales[] = { "", ":2", ":4", ":8" }; - bfd_vma base_disp; - bfd_vma outer_disp; - char buf[40]; - char vmabuf[50]; - - word = NEXTWORD (p); - - /* Generate the text for the index register. - Where this will be output is not yet determined. */ - sprintf (buf, "%s:%c%s", - reg_names[(word >> 12) & 0xf], - (word & 0x800) ? 'l' : 'w', - scales[(word >> 9) & 3]); - - /* Handle the 68000 style of indexing. */ + int i; + const char *d; + unsigned int arch_mask; + struct private priv; + bfd_byte *buffer = priv.the_buffer; + int major_opcode; + static int numopcodes[16]; + static const struct m68k_opcode **opcodes[16]; + int val; - if ((word & 0x100) == 0) + if (!opcodes[0]) { - base_disp = word & 0xff; - if ((base_disp & 0x80) != 0) - base_disp -= 0x100; - if (basereg == -1) - base_disp += addr; - print_base (basereg, base_disp, info); - (*info->fprintf_func) (info->stream, ",%s)", buf); - return p; - } + /* Speed up the matching by sorting the opcode + table on the upper four bits of the opcode. */ + const struct m68k_opcode **opc_pointer[16]; - /* Handle the generalized kind. */ - /* First, compute the displacement to add to the base register. */ + /* First count how many opcodes are in each of the sixteen buckets. */ + for (i = 0; i < m68k_numopcodes; i++) + numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++; - if (word & 0200) - { - if (basereg == -1) - basereg = -3; - else - basereg = -2; - } - if (word & 0100) - buf[0] = '\0'; - base_disp = 0; - switch ((word >> 4) & 3) - { - case 2: - base_disp = NEXTWORD (p); - break; - case 3: - base_disp = NEXTLONG (p); - } - if (basereg == -1) - base_disp += addr; + /* Then create a sorted table of pointers + that point into the unsorted table. */ + opc_pointer[0] = xmalloc (sizeof (struct m68k_opcode *) + * m68k_numopcodes); + opcodes[0] = opc_pointer[0]; - /* Handle single-level case (not indirect) */ + for (i = 1; i < 16; i++) + { + opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1]; + opcodes[i] = opc_pointer[i]; + } - if ((word & 7) == 0) - { - print_base (basereg, base_disp, info); - if (buf[0] != '\0') - (*info->fprintf_func) (info->stream, ",%s", buf); - (*info->fprintf_func) (info->stream, ")"); - return p; + for (i = 0; i < m68k_numopcodes; i++) + *opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i]; } - /* Two level. Compute displacement to add after indirection. */ + info->private_data = (PTR) &priv; + /* Tell objdump to use two bytes per chunk + and six bytes per line for displaying raw data. */ + info->bytes_per_chunk = 2; + info->bytes_per_line = 6; + info->display_endian = BFD_ENDIAN_BIG; + priv.max_fetched = priv.the_buffer; + priv.insn_start = memaddr; - outer_disp = 0; - switch (word & 3) + if (setjmp (priv.bailout) != 0) + /* Error return. */ + return -1; + + switch (info->mach) { - case 2: - outer_disp = NEXTWORD (p); + default: + case 0: + arch_mask = (unsigned int) -1; + break; + case bfd_mach_m68000: + arch_mask = m68000|m68881|m68851; + break; + case bfd_mach_m68008: + arch_mask = m68008|m68881|m68851; + break; + case bfd_mach_m68010: + arch_mask = m68010|m68881|m68851; + break; + case bfd_mach_m68020: + arch_mask = m68020|m68881|m68851; + break; + case bfd_mach_m68030: + arch_mask = m68030|m68881|m68851; + break; + case bfd_mach_m68040: + arch_mask = m68040|m68881|m68851; + break; + case bfd_mach_m68060: + arch_mask = m68060|m68881|m68851; + break; + case bfd_mach_mcf5200: + arch_mask = mcfisa_a; + break; + case bfd_mach_mcf521x: + case bfd_mach_mcf528x: + arch_mask = mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp|mcfemac; + break; + case bfd_mach_mcf5206e: + arch_mask = mcfisa_a|mcfhwdiv|mcfmac; + break; + case bfd_mach_mcf5249: + arch_mask = mcfisa_a|mcfhwdiv|mcfemac; + break; + case bfd_mach_mcf5307: + arch_mask = mcfisa_a|mcfhwdiv|mcfmac; + break; + case bfd_mach_mcf5407: + arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac; + break; + case bfd_mach_mcf547x: + case bfd_mach_mcf548x: + case bfd_mach_mcfv4e: + arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp|cfloat|mcfemac; break; - case 3: - outer_disp = NEXTLONG (p); } - print_base (basereg, base_disp, info); - if ((word & 4) == 0 && buf[0] != '\0') - { - (*info->fprintf_func) (info->stream, ",%s", buf); - buf[0] = '\0'; - } - sprintf_vma (vmabuf, outer_disp); - (*info->fprintf_func) (info->stream, ")@(%s", vmabuf); - if (buf[0] != '\0') - (*info->fprintf_func) (info->stream, ",%s", buf); - (*info->fprintf_func) (info->stream, ")"); + FETCH_DATA (info, buffer + 2); + major_opcode = (buffer[0] >> 4) & 15; - return p; -} + for (i = 0; i < numopcodes[major_opcode]; i++) + { + const struct m68k_opcode *opc = opcodes[major_opcode][i]; + unsigned long opcode = opc->opcode; + unsigned long match = opc->match; -/* Print a base register REGNO and displacement DISP, on INFO->STREAM. - REGNO = -1 for pc, -2 for none (suppressed). */ + if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24))) + && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16))) + /* Only fetch the next two bytes if we need to. */ + && (((0xffff & match) == 0) + || + (FETCH_DATA (info, buffer + 4) + && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8))) + && ((0xff & buffer[3] & match) == (0xff & opcode))) + ) + && (opc->arch & arch_mask) != 0) + { + /* Don't use for printout the variants of divul and divsl + that have the same register number in two places. + The more general variants will match instead. */ + for (d = opc->args; *d; d += 2) + if (d[1] == 'D') + break; -static void -print_base (regno, disp, info) - int regno; - bfd_vma disp; - disassemble_info *info; -{ - if (regno == -1) - { - (*info->fprintf_func) (info->stream, "%%pc@("); - (*info->print_address_func) (disp, info); - } - else - { - char buf[50]; + /* Don't use for printout the variants of most floating + point coprocessor instructions which use the same + register number in two places, as above. */ + if (*d == '\0') + for (d = opc->args; *d; d += 2) + if (d[1] == 't') + break; - if (regno == -2) - (*info->fprintf_func) (info->stream, "@("); - else if (regno == -3) - (*info->fprintf_func) (info->stream, "%%zpc@("); - else - (*info->fprintf_func) (info->stream, "%s@(", reg_names[regno]); + /* Don't match fmovel with more than one register; + wait for fmoveml. */ + if (*d == '\0') + { + for (d = opc->args; *d; d += 2) + { + if (d[0] == 's' && d[1] == '8') + { + val = fetch_arg (buffer, d[1], 3, info); + if ((val & (val - 1)) != 0) + break; + } + } + } - sprintf_vma (buf, disp); - (*info->fprintf_func) (info->stream, "%s", buf); + if (*d == '\0') + if ((val = match_insn_m68k (memaddr, info, opc, & priv))) + return val; + } } + + /* Handle undefined instructions. */ + info->fprintf_func (info->stream, "0%o", (buffer[0] << 8) + buffer[1]); + return 2; } diff -uprN binutils-2.16.91.0.1/opcodes/m68k-opc.c binutils-2.16.91.0.2/opcodes/m68k-opc.c --- binutils-2.16.91.0.1/opcodes/m68k-opc.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/m68k-opc.c 2005-07-20 12:27:29.271866762 -0700 @@ -1,6 +1,6 @@ /* Opcode table for m680[012346]0/m6888[12]/m68851/mcf5200. Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2003, 2004 + 2000, 2001, 2003, 2004, 2005 Free Software Foundation, Inc. This file is part of GDB, GAS, and the GNU binutils. @@ -94,11 +94,11 @@ const struct m68k_opcode m68k_opcodes[] {"andl", 6, one(0001200), one(0177700), "#lDs", mcfisa_a }, {"andl", 2, one(0140200), one(0170700), ";lDd", m68000up | mcfisa_a }, {"andl", 2, one(0140600), one(0170700), "Dd~l", m68000up | mcfisa_a }, -{"and", 4, one(0001100), one(0177700), "#w$w", m68000up }, -{"and", 4, one(0001074), one(0177777), "#bCs", m68000up }, -{"and", 4, one(0001174), one(0177777), "#wSs", m68000up }, -{"and", 2, one(0140100), one(0170700), ";wDd", m68000up }, -{"and", 2, one(0140500), one(0170700), "Dd~w", m68000up }, +{"and", 4, one(0001100), one(0177700), "#w$w", m68000up }, +{"and", 4, one(0001074), one(0177777), "#bCs", m68000up }, +{"and", 4, one(0001174), one(0177777), "#wSs", m68000up }, +{"and", 2, one(0140100), one(0170700), ";wDd", m68000up }, +{"and", 2, one(0140500), one(0170700), "Dd~w", m68000up }, {"aslb", 2, one(0160400), one(0170770), "QdDs", m68000up }, {"aslb", 2, one(0160440), one(0170770), "DdDs", m68000up }, diff -uprN binutils-2.16.91.0.1/opcodes/m88k-dis.c binutils-2.16.91.0.2/opcodes/m88k-dis.c --- binutils-2.16.91.0.1/opcodes/m88k-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/m88k-dis.c 2005-07-20 12:27:29.274866267 -0700 @@ -1,24 +1,25 @@ /* Print instructions for the Motorola 88000, for GDB and GNU Binutils. Copyright 1986, 1987, 1988, 1989, 1990, 1991, 1993, 1998, 2000, 2001, - 2002 Free Software Foundation, Inc. + 2002, 2005 Free Software Foundation, Inc. Contributed by Data General Corporation, November 1989. Partially derived from an earlier printcmd.c. -This file is part of GDB and the GNU Binutils. + This file is part of GDB and the GNU Binutils. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "sysdep.h" #include "dis-asm.h" @@ -26,14 +27,16 @@ Foundation, Inc., 51 Franklin Street - F #include "opintl.h" #include "libiberty.h" -typedef struct HASHTAB { +typedef struct HASHTAB +{ const INSTAB *instr; struct HASHTAB *next; } HASHTAB; /* Opcode Mnemonic Op 1 Spec Op 2 Spec Op 3 Spec Simflags Next */ -const INSTAB instructions[] = { +const INSTAB instructions[] = +{ {0xf400c800,"jsr ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {2,2,NA,JSR , 0,0,1,0,0,0,0,1,0,0,0,0} }, {0xf400cc00,"jsr.n ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {1,1,NA,JSR , 0,0,1,0,0,0,1,1,0,0,0,0} }, {0xf400c000,"jmp ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {2,2,NA,JMP , 0,0,1,0,0,0,0,1,0,0,0,0} }, @@ -517,134 +520,64 @@ const INSTAB instructions[] = { }; HASHTAB *hashtable[HASHVAL] = {0}; - -static int -m88kdis PARAMS ((bfd_vma, unsigned long, struct disassemble_info *)); - -static void -printop PARAMS ((struct disassemble_info *, const OPSPEC *, unsigned long, bfd_vma, int)); - -static void -init_disasm PARAMS ((void)); -/* Disassemble an M88000 instruction at `memaddr'. */ - -int -print_insn_m88k (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - bfd_byte buffer[4]; - int status; - - /* Instruction addresses may have low two bits set. Clear them. */ - memaddr &=~ (bfd_vma) 3; - - status = (*info->read_memory_func) (memaddr, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - - return m88kdis (memaddr, bfd_getb32 (buffer), info); -} +/* Initialize the disassembler instruction table. + + Initialize the hash table and instruction table for the + disassembler. This should be called once before the first call to + disasm(). */ -/* - * Disassemble the instruction in `instruction'. - * `pc' should be the address of this instruction, it will be used to - * print the target address if this is a relative jump or call the - * disassembled instruction is written to `info'. - * - * The function returns the length of this instruction in bytes. - */ - -static int -m88kdis (pc, instruction, info) - bfd_vma pc; - unsigned long instruction; - struct disassemble_info *info; +static void +init_disasm (void) { - static int ihashtab_initialized = 0; - unsigned int opcode; - const HASHTAB *entry_ptr; - int opmask; - unsigned int class; - - if (! ihashtab_initialized) - { - init_disasm (); - ihashtab_initialized = 1; - } + unsigned int hashvalue, hashsize; + struct HASHTAB *hashentries; + unsigned int i; - /* Create the appropriate mask to isolate the opcode. */ - opmask = DEFMASK; - class = instruction & DEFMASK; - if ((class >= SFU0) && (class <= SFU7)) - { - if (instruction < SFU1) - opmask = CTRLMASK; - else - opmask = SFUMASK; - } - else if (class == RRR) - opmask = RRRMASK; - else if (class == RRI10) - opmask = RRI10MASK; + hashsize = sizeof (instructions) / sizeof (INSTAB); - /* Isolate the opcode. */ - opcode = instruction & opmask; + hashentries = xmalloc (hashsize * sizeof (struct HASHTAB)); - /* Search the hash table with the isolated opcode. */ - for (entry_ptr = hashtable[opcode % HASHVAL]; - (entry_ptr != NULL) && (entry_ptr->instr->opcode != opcode); - entry_ptr = entry_ptr->next) - ; + for (i = 0; i < HASHVAL; i++) + hashtable[i] = NULL; - if (entry_ptr == NULL) - (*info->fprintf_func) (info->stream, "word\t%08x", instruction); - else + for (i = 0; i < hashsize; i++) { - (*info->fprintf_func) (info->stream, "%s", entry_ptr->instr->mnemonic); - printop (info, &(entry_ptr->instr->op1), instruction, pc, 1); - printop (info, &(entry_ptr->instr->op2), instruction, pc, 0); - printop (info, &(entry_ptr->instr->op3), instruction, pc, 0); + hashvalue = (instructions[i].opcode) % HASHVAL; + hashentries[i].instr = &instructions[i]; + hashentries[i].next = hashtable[hashvalue]; + hashtable[hashvalue] = &hashentries[i]; } - - return 4; } - -/* - * Decode an Operand of an instruction. - * - * This function formats and writes an operand of an instruction to - * info based on the operand specification. When the `first' flag is - * set this is the first operand of an instruction. Undefined operand - * types cause a message. - * - * Parameters: - * disassemble_info where the operand may be printed - * OPSPEC *opptr pointer to an operand specification - * UINT inst instruction from which operand is extracted - * UINT pc pc of instruction; used for pc-relative disp. - * int first flag which if nonzero indicates the first - * operand of an instruction - * - * The operand specified is extracted from the instruction and is - * written to buf in the format specified. The operand is preceded by - * a comma if it is not the first operand of an instruction and it is - * not a register indirect form. Registers are preceded by 'r' and - * hex values by '0x'. - */ + +/* Decode an Operand of an instruction. + + This function formats and writes an operand of an instruction to + info based on the operand specification. When the `first' flag is + set this is the first operand of an instruction. Undefined operand + types cause a message. + + Parameters: + disassemble_info where the operand may be printed + OPSPEC *opptr pointer to an operand specification + UINT inst instruction from which operand is extracted + UINT pc pc of instruction; used for pc-relative disp. + int first flag which if nonzero indicates the first + operand of an instruction + + The operand specified is extracted from the instruction and is + written to buf in the format specified. The operand is preceded by + a comma if it is not the first operand of an instruction and it is + not a register indirect form. Registers are preceded by 'r' and + hex values by '0x'. */ static void -printop (info, opptr, inst, pc, first) - struct disassemble_info *info; - const OPSPEC *opptr; - unsigned long inst; - bfd_vma pc; - int first; +printop (struct disassemble_info *info, + const OPSPEC *opptr, + unsigned long inst, + bfd_vma pc, + int first) { int extracted_field; char *cond_mask_sym; @@ -743,38 +676,88 @@ printop (info, opptr, inst, pc, first) default: /* xgettext:c-format */ - (*info->fprintf_func) (info->stream, _("# "), inst); + (*info->fprintf_func) (info->stream, _("# "), inst); } } -/* - * Initialize the disassembler instruction table. - * - * Initialize the hash table and instruction table for the - * disassembler. This should be called once before the first call to - * disasm(). - */ +/* Disassemble the instruction in `instruction'. + `pc' should be the address of this instruction, it will be used to + print the target address if this is a relative jump or call the + disassembled instruction is written to `info'. + + The function returns the length of this instruction in bytes. */ -static void -init_disasm () +static int +m88kdis (bfd_vma pc, + unsigned long instruction, + struct disassemble_info *info) { - unsigned int hashvalue, hashsize; - struct HASHTAB *hashentries; - unsigned int i; + static int ihashtab_initialized = 0; + unsigned int opcode; + const HASHTAB *entry_ptr; + int opmask; + unsigned int class; - hashsize = sizeof (instructions) / sizeof (INSTAB); + if (! ihashtab_initialized) + { + init_disasm (); + ihashtab_initialized = 1; + } - hashentries = (struct HASHTAB *) xmalloc (hashsize * sizeof (struct HASHTAB)); + /* Create the appropriate mask to isolate the opcode. */ + opmask = DEFMASK; + class = instruction & DEFMASK; + if ((class >= SFU0) && (class <= SFU7)) + { + if (instruction < SFU1) + opmask = CTRLMASK; + else + opmask = SFUMASK; + } + else if (class == RRR) + opmask = RRRMASK; + else if (class == RRI10) + opmask = RRI10MASK; - for (i = 0; i < HASHVAL; i++) - hashtable[i] = NULL; + /* Isolate the opcode. */ + opcode = instruction & opmask; - for (i = 0; i < hashsize; i++) + /* Search the hash table with the isolated opcode. */ + for (entry_ptr = hashtable[opcode % HASHVAL]; + (entry_ptr != NULL) && (entry_ptr->instr->opcode != opcode); + entry_ptr = entry_ptr->next) + ; + + if (entry_ptr == NULL) + (*info->fprintf_func) (info->stream, "word\t%08lx", instruction); + else { - hashvalue = (instructions[i].opcode) % HASHVAL; - hashentries[i].instr = &instructions[i]; - hashentries[i].next = hashtable[hashvalue]; - hashtable[hashvalue] = &hashentries[i]; + (*info->fprintf_func) (info->stream, "%s", entry_ptr->instr->mnemonic); + printop (info, &(entry_ptr->instr->op1), instruction, pc, 1); + printop (info, &(entry_ptr->instr->op2), instruction, pc, 0); + printop (info, &(entry_ptr->instr->op3), instruction, pc, 0); } + + return 4; +} + +/* Disassemble an M88000 instruction at `memaddr'. */ + +int +print_insn_m88k (bfd_vma memaddr, struct disassemble_info *info) +{ + bfd_byte buffer[4]; + int status; + + /* Instruction addresses may have low two bits set. Clear them. */ + memaddr &=~ (bfd_vma) 3; + + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + return m88kdis (memaddr, bfd_getb32 (buffer), info); } - diff -uprN binutils-2.16.91.0.1/opcodes/Makefile.am binutils-2.16.91.0.2/opcodes/Makefile.am --- binutils-2.16.91.0.1/opcodes/Makefile.am 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/Makefile.am 2005-07-20 12:27:28.528989261 -0700 @@ -25,6 +25,7 @@ LIBIBERTY = ../libiberty/libiberty.a # Header files. HFILES = \ + cgen-ops.h cgen-types.h \ fr30-desc.h fr30-opc.h \ frv-desc.h frv-opc.h \ h8500-opc.h \ @@ -32,6 +33,7 @@ HFILES = \ ia64-opc.h \ ip2k-desc.h ip2k-opc.h \ iq2000-desc.h iq2000-opc.h \ + m32c-desc.h m32c-opc.h \ m32r-desc.h m32r-opc.h \ mcore-opc.h \ ms1-desc.h ms1-opc.h \ @@ -106,6 +108,11 @@ CFILES = \ iq2000-dis.c \ iq2000-ibld.c \ iq2000-opc.c \ + m32c-asm.c \ + m32c-desc.c \ + m32c-dis.c \ + m32c-ibld.c \ + m32c-opc.c \ m32r-asm.c \ m32r-desc.c \ m32r-dis.c \ @@ -225,6 +232,11 @@ ALL_MACHINES = \ iq2000-dis.lo \ iq2000-ibld.lo \ iq2000-opc.lo \ + m32c-asm.lo \ + m32c-desc.lo \ + m32c-dis.lo \ + m32c-ibld.lo \ + m32c-opc.lo \ m32r-asm.lo \ m32r-desc.lo \ m32r-dis.lo \ @@ -361,8 +373,8 @@ uninstall_libopcodes: rm -f $(DESTDIR)$(bfdincludedir)/dis-asm.h CLEANFILES = \ - stamp-ip2k stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \ - stamp-iq2000 stamp-ms1 stamp-xstormy16 \ + stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \ + stamp-openrisc stamp-iq2000 stamp-ms1 stamp-xstormy16 \ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 @@ -378,10 +390,11 @@ CGENDEPS = \ $(CGENDIR)/opc-opinst.scm \ cgen-asm.in cgen-dis.in cgen-ibld.in -CGEN_CPUS = fr30 frv ip2k m32r ms1 openrisc xstormy16 +CGEN_CPUS = fr30 frv ip2k m32c m32r ms1 openrisc xstormy16 if CGEN_MAINT IP2K_DEPS = stamp-ip2k +M32C_DEPS = stamp-m32c M32R_DEPS = stamp-m32r FR30_DEPS = stamp-fr30 FRV_DEPS = stamp-frv @@ -391,6 +404,7 @@ IQ2000_DEPS = stamp-iq2000 XSTORMY16_DEPS = stamp-xstormy16 else IP2K_DEPS = +M32C_DEPS = M32R_DEPS = FR30_DEPS = FRV_DEPS = @@ -422,11 +436,37 @@ stamp-ip2k: $(CGENDEPS) $(CPUDIR)/ip2k.c $(MAKE) run-cgen arch=ip2k prefix=ip2k options= \ archfile=$(CPUDIR)/ip2k.cpu opcfile=$(CPUDIR)/ip2k.opc extrafiles= +$(srcdir)/m32c-desc.h $(srcdir)/m32c-desc.c $(srcdir)/m32c-opc.h $(srcdir)/m32c-opc.c $(srcdir)/m32c-ibld.c $(srcdir)/m32c-asm.c $(srcdir)/m32c-dis.c: $(M32C_DEPS) +# @true +stamp-m32c: $(CGENDEPS) $(srcdir)/../cpu/m32c.cpu $(srcdir)/../cpu/m32c.opc + $(MAKE) run-cgen arch=m32c prefix=m32c options= \ + archfile=$(srcdir)/../cpu/m32c.cpu \ + opcfile=$(srcdir)/../cpu/m32c.opc extrafiles= +m32c_opc_h = m32c-opc.h cgen-types.h cgen-ops.h +m32c-asm.lo: m32c-asm.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h m32c-desc.h \ + $(INCDIR)/opcode/cgen.h $(m32c_opc_h) opintl.h +m32c-desc.lo: m32c-desc.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h m32c-desc.h \ + $(INCDIR)/opcode/cgen.h $(m32c_opc_h) opintl.h +m32c-dis.lo: m32c-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \ + $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h m32c-desc.h $(INCDIR)/opcode/cgen.h \ + $(m32c_opc_h) opintl.h +m32c-ibld.lo: m32c-ibld.c sysdep.h config.h $(INCDIR)/dis-asm.h \ + $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h m32c-desc.h $(INCDIR)/opcode/cgen.h \ + $(m32c_opc_h) opintl.h +m32c-opc.lo: m32c-opc.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h m32c-desc.h \ + $(INCDIR)/opcode/cgen.h $(m32c_opc_h) + $(srcdir)/m32r-desc.h $(srcdir)/m32r-desc.c $(srcdir)/m32r-opc.h $(srcdir)/m32r-opc.c $(srcdir)/m32r-ibld.c $(srcdir)/m32r-opinst.c $(srcdir)/m32r-asm.c $(srcdir)/m32r-dis.c: $(M32R_DEPS) @true -stamp-m32r: $(CGENDEPS) $(CPUDIR)/m32r.cpu $(CPUDIR)/m32r.opc +stamp-m32r: $(CGENDEPS) $(srcdir)/../cpu/m32r.cpu $(srcdir)/../cpu/m32r.opc $(MAKE) run-cgen arch=m32r prefix=m32r options=opinst \ - archfile=$(CPUDIR)/m32r.cpu opcfile=$(CPUDIR)/m32r.opc extrafiles=opinst + archfile=$(srcdir)/../cpu/m32r.cpu \ + opcfile=$(srcdir)/../cpu/m32r.opc extrafiles=opinst $(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS) @true @@ -442,9 +482,10 @@ stamp-frv: $(CGENDEPS) $(srcdir)/../cpu/ $(srcdir)/ms1-desc.h $(srcdir)/ms1-desc.c $(srcdir)/ms1-opc.h $(srcdir)/ms1-opc.c $(srcdir)/ms1-ibld.c $(srcdir)/ms1-asm.c $(srcdir)/ms1-dis.c: $(MS1_DEPS) @true -stamp-ms1: $(CGENDEPS) $(CPUDIR)/ms1.cpu $(CPUDIR)/ms1.opc +stamp-ms1: $(CGENDEPS) $(srcdir)/../cpu/ms1.cpu $(srcdir)/../cpu/ms1.opc $(MAKE) run-cgen arch=ms1 prefix=ms1 options= \ - archfile=$(CPUDIR)/ms1.cpu opcfile=$(CPUDIR)/ms1.opc extrafiles= + archfile=$(srcdir)/../cpu/ms1.cpu \ + opcfile=$(srcdir)/../cpu/ms1.opc extrafiles= $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) @true @@ -454,10 +495,12 @@ stamp-openrisc: $(CGENDEPS) $(CPUDIR)/op $(srcdir)/iq2000-desc.h $(srcdir)/iq2000-desc.c $(srcdir)/iq2000-opc.h $(srcdir)/iq2000-opc.c $(srcdir)/iq2000-ibld.c $(srcdir)/iq2000-asm.c $(srcdir)/iq2000-dis.c: $(IQ2000_DEPS) @true -stamp-iq2000: $(CGENDEPS) $(CPUDIR)/iq2000.cpu $(CPUDIR)/iq2000.opc \ - $(CPUDIR)/iq2000m.cpu $(CPUDIR)/iq10.cpu +stamp-iq2000: $(CGENDEPS) $(srcdir)/../cpu/iq2000.cpu \ + $(srcdir)/../cpu/iq2000.opc $(srcdir)/../cpu/iq2000m.cpu \ + $(srcdir)/../cpu/iq10.cpu $(MAKE) run-cgen arch=iq2000 prefix=iq2000 options= \ - archfile=$(CPUDIR)/iq2000.cpu opcfile=$(CPUDIR)/iq2000.opc extrafiles= + archfile=$(srcdir)/../cpu/iq2000.cpu \ + opcfile=$(srcdir)/../cpu/iq2000.opc extrafiles= $(srcdir)/xstormy16-desc.h $(srcdir)/xstormy16-desc.c $(srcdir)/xstormy16-opc.h $(srcdir)/xstormy16-opc.c $(srcdir)/xstormy16-ibld.c $(srcdir)/xstormy16-asm.c $(srcdir)/xstormy16-dis.c: $(XSTORMY16_DEPS) @true @@ -544,7 +587,8 @@ arc-dis.lo: arc-dis.c $(INCDIR)/ansidecl $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h \ $(INCDIR)/elf/reloc-macros.h opintl.h arc-dis.h arc-ext.h arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h + $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \ + opintl.h arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h arc-ext.h $(INCDIR)/libiberty.h arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ @@ -703,6 +747,27 @@ iq2000-ibld.lo: iq2000-ibld.c sysdep.h c iq2000-opc.lo: iq2000-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h $(INCDIR)/opcode/cgen.h \ iq2000-opc.h $(INCDIR)/libiberty.h +m32c-asm.lo: m32c-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h m32c-desc.h $(INCDIR)/opcode/cgen.h \ + m32c-opc.h cgen-types.h cgen-ops.h opintl.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +m32c-desc.lo: m32c-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h m32c-desc.h $(INCDIR)/opcode/cgen.h \ + m32c-opc.h cgen-types.h cgen-ops.h opintl.h $(INCDIR)/libiberty.h \ + $(INCDIR)/xregex.h $(INCDIR)/xregex2.h +m32c-dis.lo: m32c-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + m32c-desc.h $(INCDIR)/opcode/cgen.h m32c-opc.h cgen-types.h \ + cgen-ops.h opintl.h $(INCDIR)/elf/m32c.h $(INCDIR)/elf/reloc-macros.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h +m32c-ibld.lo: m32c-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h m32c-desc.h \ + $(INCDIR)/opcode/cgen.h m32c-opc.h cgen-types.h cgen-ops.h \ + opintl.h $(INCDIR)/safe-ctype.h +m32c-opc.lo: m32c-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h m32c-desc.h $(INCDIR)/opcode/cgen.h \ + m32c-opc.h cgen-types.h cgen-ops.h $(INCDIR)/libiberty.h m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ m32r-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ @@ -763,25 +828,23 @@ mmix-dis.lo: mmix-dis.c $(INCDIR)/opcode $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ opintl.h mmix-opc.lo: mmix-opc.c $(INCDIR)/opcode/mmix.h $(INCDIR)/symcat.h -ms1-asm.lo: ms1-asm.c sysdep.h config.h \ - $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h \ - $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h $(INCDIR)/xregex.h \ - $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h -ms1-desc.lo: ms1-desc.c sysdep.h config.h \ - $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h \ - $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h $(INCDIR)/libiberty.h \ - $(INCDIR)/xregex.h $(INCDIR)/xregex2.h -ms1-dis.lo: ms1-dis.c sysdep.h config.h \ - $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ - $(INCDIR)/libiberty.h ms1-desc.h $(INCDIR)/opcode/cgen.h \ - ms1-opc.h opintl.h -ms1-ibld.lo: ms1-ibld.c sysdep.h config.h \ - $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ - ms1-desc.h $(INCDIR)/opcode/cgen.h ms1-opc.h \ - opintl.h $(INCDIR)/safe-ctype.h -ms1-opc.lo: ms1-opc.c sysdep.h config.h \ - $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h \ - $(INCDIR)/opcode/cgen.h ms1-opc.h $(INCDIR)/libiberty.h +ms1-asm.lo: ms1-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h $(INCDIR)/opcode/cgen.h \ + ms1-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +ms1-desc.lo: ms1-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h $(INCDIR)/opcode/cgen.h \ + ms1-opc.h opintl.h $(INCDIR)/libiberty.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h +ms1-dis.lo: ms1-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + ms1-desc.h $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h +ms1-ibld.lo: ms1-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h \ + $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h $(INCDIR)/safe-ctype.h +ms1-opc.lo: ms1-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h $(INCDIR)/opcode/cgen.h \ + ms1-opc.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \ $(INCDIR)/symcat.h sysdep.h config.h $(INCDIR)/dis-asm.h \ $(INCDIR)/opcode/ns32k.h opintl.h diff -uprN binutils-2.16.91.0.1/opcodes/Makefile.in binutils-2.16.91.0.2/opcodes/Makefile.in --- binutils-2.16.91.0.1/opcodes/Makefile.in 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/Makefile.in 2005-07-20 12:27:28.531988767 -0700 @@ -1,8 +1,8 @@ -# Makefile.in generated by automake 1.9.3 from Makefile.am. +# Makefile.in generated by automake 1.9.5 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, -# 2003, 2004 Free Software Foundation, Inc. +# 2003, 2004, 2005 Free Software Foundation, Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. @@ -246,6 +246,7 @@ LIBIBERTY = ../libiberty/libiberty.a # Header files. HFILES = \ + cgen-ops.h cgen-types.h \ fr30-desc.h fr30-opc.h \ frv-desc.h frv-opc.h \ h8500-opc.h \ @@ -253,6 +254,7 @@ HFILES = \ ia64-opc.h \ ip2k-desc.h ip2k-opc.h \ iq2000-desc.h iq2000-opc.h \ + m32c-desc.h m32c-opc.h \ m32r-desc.h m32r-opc.h \ mcore-opc.h \ ms1-desc.h ms1-opc.h \ @@ -328,6 +330,11 @@ CFILES = \ iq2000-dis.c \ iq2000-ibld.c \ iq2000-opc.c \ + m32c-asm.c \ + m32c-desc.c \ + m32c-dis.c \ + m32c-ibld.c \ + m32c-opc.c \ m32r-asm.c \ m32r-desc.c \ m32r-dis.c \ @@ -447,6 +454,11 @@ ALL_MACHINES = \ iq2000-dis.lo \ iq2000-ibld.lo \ iq2000-opc.lo \ + m32c-asm.lo \ + m32c-desc.lo \ + m32c-dis.lo \ + m32c-ibld.lo \ + m32c-opc.lo \ m32r-asm.lo \ m32r-desc.lo \ m32r-dis.lo \ @@ -537,8 +549,8 @@ libopcodes_la_LDFLAGS = -release $(VERSI noinst_LIBRARIES = libopcodes.a POTFILES = $(HFILES) $(CFILES) CLEANFILES = \ - stamp-ip2k stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \ - stamp-iq2000 stamp-ms1 stamp-xstormy16 \ + stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \ + stamp-openrisc stamp-iq2000 stamp-ms1 stamp-xstormy16 \ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 CGENDIR = @cgendir@ @@ -552,9 +564,11 @@ CGENDEPS = \ $(CGENDIR)/opc-opinst.scm \ cgen-asm.in cgen-dis.in cgen-ibld.in -CGEN_CPUS = fr30 frv ip2k m32r ms1 openrisc xstormy16 +CGEN_CPUS = fr30 frv ip2k m32c m32r ms1 openrisc xstormy16 @CGEN_MAINT_FALSE@IP2K_DEPS = @CGEN_MAINT_TRUE@IP2K_DEPS = stamp-ip2k +@CGEN_MAINT_FALSE@M32C_DEPS = +@CGEN_MAINT_TRUE@M32C_DEPS = stamp-m32c @CGEN_MAINT_FALSE@M32R_DEPS = @CGEN_MAINT_TRUE@M32R_DEPS = stamp-m32r @CGEN_MAINT_FALSE@FR30_DEPS = @@ -569,6 +583,7 @@ CGEN_CPUS = fr30 frv ip2k m32r ms1 openr @CGEN_MAINT_TRUE@IQ2000_DEPS = stamp-iq2000 @CGEN_MAINT_FALSE@XSTORMY16_DEPS = @CGEN_MAINT_TRUE@XSTORMY16_DEPS = stamp-xstormy16 +m32c_opc_h = m32c-opc.h cgen-types.h cgen-ops.h all: config.h $(MAKE) $(AM_MAKEFLAGS) all-recursive @@ -673,7 +688,13 @@ uninstall-info-am: # (which will cause the Makefiles to be regenerated when you run `make'); # (2) otherwise, pass the desired values on the `make' command line. $(RECURSIVE_TARGETS): - @set fnord $$MAKEFLAGS; amf=$$2; \ + @failcom='exit 1'; \ + for f in x $$MAKEFLAGS; do \ + case $$f in \ + *=* | --[!k]*);; \ + *k*) failcom='fail=yes';; \ + esac; \ + done; \ dot_seen=no; \ target=`echo $@ | sed s/-recursive//`; \ list='$(SUBDIRS)'; for subdir in $$list; do \ @@ -685,7 +706,7 @@ $(RECURSIVE_TARGETS): local_target="$$target"; \ fi; \ (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \ - || case "$$amf" in *=*) exit 1;; *k*) fail=yes;; *) exit 1;; esac; \ + || eval $$failcom; \ done; \ if test "$$dot_seen" = "no"; then \ $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \ @@ -693,7 +714,13 @@ $(RECURSIVE_TARGETS): mostlyclean-recursive clean-recursive distclean-recursive \ maintainer-clean-recursive: - @set fnord $$MAKEFLAGS; amf=$$2; \ + @failcom='exit 1'; \ + for f in x $$MAKEFLAGS; do \ + case $$f in \ + *=* | --[!k]*);; \ + *k*) failcom='fail=yes';; \ + esac; \ + done; \ dot_seen=no; \ case "$@" in \ distclean-* | maintainer-clean-*) list='$(DIST_SUBDIRS)' ;; \ @@ -714,7 +741,7 @@ maintainer-clean-recursive: local_target="$$target"; \ fi; \ (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \ - || case "$$amf" in *=*) exit 1;; *k*) fail=yes;; *) exit 1;; esac; \ + || eval $$failcom; \ done && test -z "$$fail" tags-recursive: list='$(SUBDIRS)'; for subdir in $$list; do \ @@ -952,11 +979,36 @@ stamp-ip2k: $(CGENDEPS) $(CPUDIR)/ip2k.c $(MAKE) run-cgen arch=ip2k prefix=ip2k options= \ archfile=$(CPUDIR)/ip2k.cpu opcfile=$(CPUDIR)/ip2k.opc extrafiles= +$(srcdir)/m32c-desc.h $(srcdir)/m32c-desc.c $(srcdir)/m32c-opc.h $(srcdir)/m32c-opc.c $(srcdir)/m32c-ibld.c $(srcdir)/m32c-asm.c $(srcdir)/m32c-dis.c: $(M32C_DEPS) +# @true +stamp-m32c: $(CGENDEPS) $(srcdir)/../cpu/m32c.cpu $(srcdir)/../cpu/m32c.opc + $(MAKE) run-cgen arch=m32c prefix=m32c options= \ + archfile=$(srcdir)/../cpu/m32c.cpu \ + opcfile=$(srcdir)/../cpu/m32c.opc extrafiles= +m32c-asm.lo: m32c-asm.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h m32c-desc.h \ + $(INCDIR)/opcode/cgen.h $(m32c_opc_h) opintl.h +m32c-desc.lo: m32c-desc.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h m32c-desc.h \ + $(INCDIR)/opcode/cgen.h $(m32c_opc_h) opintl.h +m32c-dis.lo: m32c-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \ + $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h m32c-desc.h $(INCDIR)/opcode/cgen.h \ + $(m32c_opc_h) opintl.h +m32c-ibld.lo: m32c-ibld.c sysdep.h config.h $(INCDIR)/dis-asm.h \ + $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h m32c-desc.h $(INCDIR)/opcode/cgen.h \ + $(m32c_opc_h) opintl.h +m32c-opc.lo: m32c-opc.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h m32c-desc.h \ + $(INCDIR)/opcode/cgen.h $(m32c_opc_h) + $(srcdir)/m32r-desc.h $(srcdir)/m32r-desc.c $(srcdir)/m32r-opc.h $(srcdir)/m32r-opc.c $(srcdir)/m32r-ibld.c $(srcdir)/m32r-opinst.c $(srcdir)/m32r-asm.c $(srcdir)/m32r-dis.c: $(M32R_DEPS) @true -stamp-m32r: $(CGENDEPS) $(CPUDIR)/m32r.cpu $(CPUDIR)/m32r.opc +stamp-m32r: $(CGENDEPS) $(srcdir)/../cpu/m32r.cpu $(srcdir)/../cpu/m32r.opc $(MAKE) run-cgen arch=m32r prefix=m32r options=opinst \ - archfile=$(CPUDIR)/m32r.cpu opcfile=$(CPUDIR)/m32r.opc extrafiles=opinst + archfile=$(srcdir)/../cpu/m32r.cpu \ + opcfile=$(srcdir)/../cpu/m32r.opc extrafiles=opinst $(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS) @true @@ -974,7 +1026,8 @@ $(srcdir)/ms1-desc.h $(srcdir)/ms1-desc. @true stamp-ms1: $(CGENDEPS) $(srcdir)/../cpu/ms1.cpu $(srcdir)/../cpu/ms1.opc $(MAKE) run-cgen arch=ms1 prefix=ms1 options= \ - archfile=$(srcdir)/../cpu/ms1.cpu opcfile=$(srcdir)/../cpu/ms1.opc extrafiles= + archfile=$(srcdir)/../cpu/ms1.cpu \ + opcfile=$(srcdir)/../cpu/ms1.opc extrafiles= $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) @true @@ -984,10 +1037,12 @@ stamp-openrisc: $(CGENDEPS) $(CPUDIR)/op $(srcdir)/iq2000-desc.h $(srcdir)/iq2000-desc.c $(srcdir)/iq2000-opc.h $(srcdir)/iq2000-opc.c $(srcdir)/iq2000-ibld.c $(srcdir)/iq2000-asm.c $(srcdir)/iq2000-dis.c: $(IQ2000_DEPS) @true -stamp-iq2000: $(CGENDEPS) $(CPUDIR)/iq2000.cpu $(CPUDIR)/iq2000.opc \ - $(CPUDIR)/iq2000m.cpu $(CPUDIR)/iq10.cpu +stamp-iq2000: $(CGENDEPS) $(srcdir)/../cpu/iq2000.cpu \ + $(srcdir)/../cpu/iq2000.opc $(srcdir)/../cpu/iq2000m.cpu \ + $(srcdir)/../cpu/iq10.cpu $(MAKE) run-cgen arch=iq2000 prefix=iq2000 options= \ - archfile=$(CPUDIR)/iq2000.cpu opcfile=$(CPUDIR)/iq2000.opc extrafiles= + archfile=$(srcdir)/../cpu/iq2000.cpu \ + opcfile=$(srcdir)/../cpu/iq2000.opc extrafiles= $(srcdir)/xstormy16-desc.h $(srcdir)/xstormy16-desc.c $(srcdir)/xstormy16-opc.h $(srcdir)/xstormy16-opc.c $(srcdir)/xstormy16-ibld.c $(srcdir)/xstormy16-asm.c $(srcdir)/xstormy16-dis.c: $(XSTORMY16_DEPS) @true @@ -1074,7 +1129,8 @@ arc-dis.lo: arc-dis.c $(INCDIR)/ansidecl $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h \ $(INCDIR)/elf/reloc-macros.h opintl.h arc-dis.h arc-ext.h arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h + $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h \ + opintl.h arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h arc-ext.h $(INCDIR)/libiberty.h arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ @@ -1233,6 +1289,27 @@ iq2000-ibld.lo: iq2000-ibld.c sysdep.h c iq2000-opc.lo: iq2000-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h $(INCDIR)/opcode/cgen.h \ iq2000-opc.h $(INCDIR)/libiberty.h +m32c-asm.lo: m32c-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h m32c-desc.h $(INCDIR)/opcode/cgen.h \ + m32c-opc.h cgen-types.h cgen-ops.h opintl.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +m32c-desc.lo: m32c-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h m32c-desc.h $(INCDIR)/opcode/cgen.h \ + m32c-opc.h cgen-types.h cgen-ops.h opintl.h $(INCDIR)/libiberty.h \ + $(INCDIR)/xregex.h $(INCDIR)/xregex2.h +m32c-dis.lo: m32c-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + m32c-desc.h $(INCDIR)/opcode/cgen.h m32c-opc.h cgen-types.h \ + cgen-ops.h opintl.h $(INCDIR)/elf/m32c.h $(INCDIR)/elf/reloc-macros.h \ + $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \ + $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h +m32c-ibld.lo: m32c-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h m32c-desc.h \ + $(INCDIR)/opcode/cgen.h m32c-opc.h cgen-types.h cgen-ops.h \ + opintl.h $(INCDIR)/safe-ctype.h +m32c-opc.lo: m32c-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h m32c-desc.h $(INCDIR)/opcode/cgen.h \ + m32c-opc.h cgen-types.h cgen-ops.h $(INCDIR)/libiberty.h m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ m32r-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ @@ -1293,25 +1370,23 @@ mmix-dis.lo: mmix-dis.c $(INCDIR)/opcode $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ opintl.h mmix-opc.lo: mmix-opc.c $(INCDIR)/opcode/mmix.h $(INCDIR)/symcat.h -ms1-asm.lo: ms1-asm.c sysdep.h config.h \ - $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h \ - $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h $(INCDIR)/xregex.h \ - $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h -ms1-desc.lo: ms1-desc.c sysdep.h config.h \ - $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h \ - $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h $(INCDIR)/libiberty.h \ - $(INCDIR)/xregex.h $(INCDIR)/xregex2.h -ms1-dis.lo: ms1-dis.c sysdep.h config.h \ - $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ - $(INCDIR)/libiberty.h ms1-desc.h $(INCDIR)/opcode/cgen.h \ - ms1-opc.h opintl.h -ms1-ibld.lo: ms1-ibld.c sysdep.h config.h \ - $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ - ms1-desc.h $(INCDIR)/opcode/cgen.h ms1-opc.h \ - opintl.h $(INCDIR)/safe-ctype.h -ms1-opc.lo: ms1-opc.c sysdep.h config.h \ - $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h \ - $(INCDIR)/opcode/cgen.h ms1-opc.h $(INCDIR)/libiberty.h +ms1-asm.lo: ms1-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h $(INCDIR)/opcode/cgen.h \ + ms1-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +ms1-desc.lo: ms1-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h $(INCDIR)/opcode/cgen.h \ + ms1-opc.h opintl.h $(INCDIR)/libiberty.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h +ms1-dis.lo: ms1-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + ms1-desc.h $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h +ms1-ibld.lo: ms1-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h \ + $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h $(INCDIR)/safe-ctype.h +ms1-opc.lo: ms1-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h $(INCDIR)/opcode/cgen.h \ + ms1-opc.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \ $(INCDIR)/symcat.h sysdep.h config.h $(INCDIR)/dis-asm.h \ $(INCDIR)/opcode/ns32k.h opintl.h diff -uprN binutils-2.16.91.0.1/opcodes/mcore-dis.c binutils-2.16.91.0.2/opcodes/mcore-dis.c --- binutils-2.16.91.0.1/opcodes/mcore-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/mcore-dis.c 2005-07-20 12:27:29.274866267 -0700 @@ -198,7 +198,7 @@ print_insn_mcore (memaddr, info) if (inst & 0x400) val |= 0xFFFFFC00; - fprintf (stream, "\t0x%x", memaddr + 2 + (val << 1)); + fprintf (stream, "\t0x%lx", (long)(memaddr + 2 + (val << 1))); if (strcmp (op->name, "bsr") == 0) { @@ -218,8 +218,8 @@ print_insn_mcore (memaddr, info) { long val; val = (inst & 0x000F); - fprintf (stream, "\t%s, 0x%x", - grname[(inst >> 4) & 0xF], memaddr - (val << 1)); + fprintf (stream, "\t%s, 0x%lx", + grname[(inst >> 4) & 0xF], (long)(memaddr - (val << 1))); } break; @@ -244,11 +244,11 @@ print_insn_mcore (memaddr, info) | (ibytes[2] << 8) | (ibytes[3]); /* Removed [] around literal value to match ABI syntax 12/95. */ - fprintf (stream, "\t%s, 0x%X", grname[(inst >> 8) & 0xF], val); + fprintf (stream, "\t%s, 0x%lX", grname[(inst >> 8) & 0xF], val); if (val == 0) - fprintf (stream, "\t// from address pool at 0x%x", - (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); + fprintf (stream, "\t// from address pool at 0x%lx", + (long)(memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); } break; @@ -273,7 +273,7 @@ print_insn_mcore (memaddr, info) | (ibytes[2] << 8) | (ibytes[3]); /* Removed [] around literal value to match ABI syntax 12/95. */ - fprintf (stream, "\t0x%X", val); + fprintf (stream, "\t0x%lX", val); /* For jmpi/jsri, we'll try to get a symbol for the target. */ if (info->print_address_func && val != 0) { @@ -282,8 +282,8 @@ print_insn_mcore (memaddr, info) } else { - fprintf (stream, "\t// from address pool at 0x%x", - (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); + fprintf (stream, "\t// from address pool at 0x%lx", + (long)(memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); } } break; diff -uprN binutils-2.16.91.0.1/opcodes/mips-dis.c binutils-2.16.91.0.2/opcodes/mips-dis.c --- binutils-2.16.91.0.1/opcodes/mips-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/mips-dis.c 2005-07-20 12:27:29.278865608 -0700 @@ -4,21 +4,22 @@ Free Software Foundation, Inc. Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp). -This file is part of GDB, GAS, and the GNU binutils. + This file is part of GDB, GAS, and the GNU binutils. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "sysdep.h" #include "dis-asm.h" @@ -40,96 +41,88 @@ Foundation, Inc., 51 Franklin Street - F /* Mips instructions are at maximum this many bytes long. */ #define INSNLEN 4 -static void set_default_mips_dis_options - PARAMS ((struct disassemble_info *)); -static void parse_mips_dis_option - PARAMS ((const char *, unsigned int)); -static void parse_mips_dis_options - PARAMS ((const char *)); -static int _print_insn_mips - PARAMS ((bfd_vma, struct disassemble_info *, enum bfd_endian)); -static int print_insn_mips - PARAMS ((bfd_vma, unsigned long int, struct disassemble_info *)); -static void print_insn_args - PARAMS ((const char *, unsigned long, bfd_vma, struct disassemble_info *)); -static int print_insn_mips16 - PARAMS ((bfd_vma, struct disassemble_info *)); -static int is_newabi - PARAMS ((Elf_Internal_Ehdr *)); -static void print_mips16_insn_arg - PARAMS ((int, const struct mips_opcode *, int, bfd_boolean, int, bfd_vma, - struct disassemble_info *)); /* FIXME: These should be shared with gdb somehow. */ -struct mips_cp0sel_name { - unsigned int cp0reg; - unsigned int sel; - const char * const name; +struct mips_cp0sel_name +{ + unsigned int cp0reg; + unsigned int sel; + const char * const name; }; /* The mips16 register names. */ -static const char * const mips16_reg_names[] = { +static const char * const mips16_reg_names[] = +{ "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3" }; -static const char * const mips_gpr_names_numeric[32] = { +static const char * const mips_gpr_names_numeric[32] = +{ "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" }; -static const char * const mips_gpr_names_oldabi[32] = { +static const char * const mips_gpr_names_oldabi[32] = +{ "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" }; -static const char * const mips_gpr_names_newabi[32] = { +static const char * const mips_gpr_names_newabi[32] = +{ "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" }; -static const char * const mips_fpr_names_numeric[32] = { +static const char * const mips_fpr_names_numeric[32] = +{ "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" }; -static const char * const mips_fpr_names_32[32] = { +static const char * const mips_fpr_names_32[32] = +{ "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" }; -static const char * const mips_fpr_names_n32[32] = { +static const char * const mips_fpr_names_n32[32] = +{ "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" }; -static const char * const mips_fpr_names_64[32] = { +static const char * const mips_fpr_names_64[32] = +{ "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" }; -static const char * const mips_cp0_names_numeric[32] = { +static const char * const mips_cp0_names_numeric[32] = +{ "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" }; -static const char * const mips_cp0_names_mips3264[32] = { +static const char * const mips_cp0_names_mips3264[32] = +{ "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", "c0_context", "c0_pagemask", "c0_wired", "$7", "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", @@ -140,7 +133,8 @@ static const char * const mips_cp0_names "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", }; -static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = { +static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = +{ { 16, 1, "c0_config1" }, { 16, 2, "c0_config2" }, { 16, 3, "c0_config3" }, @@ -172,7 +166,8 @@ static const struct mips_cp0sel_name mip { 29, 1, "c0_datahi" } }; -static const char * const mips_cp0_names_mips3264r2[32] = { +static const char * const mips_cp0_names_mips3264r2[32] = +{ "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena", "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", @@ -183,7 +178,8 @@ static const char * const mips_cp0_names "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", }; -static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = { +static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = +{ { 4, 1, "c0_contextconfig" }, { 5, 1, "c0_pagegrain" }, { 12, 1, "c0_intctl" }, @@ -238,7 +234,8 @@ static const struct mips_cp0sel_name mip }; /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ -static const char * const mips_cp0_names_sb1[32] = { +static const char * const mips_cp0_names_sb1[32] = +{ "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", "c0_context", "c0_pagemask", "c0_wired", "$7", "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", @@ -249,7 +246,8 @@ static const char * const mips_cp0_names "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", }; -static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = { +static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = +{ { 16, 1, "c0_config1" }, { 18, 1, "c0_watchlo,1" }, { 19, 1, "c0_watchhi,1" }, @@ -273,14 +271,16 @@ static const struct mips_cp0sel_name mip { 29, 3, "c0_datahi_d" }, }; -static const char * const mips_hwr_names_numeric[32] = { +static const char * const mips_hwr_names_numeric[32] = +{ "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" }; -static const char * const mips_hwr_names_mips3264r2[32] = { +static const char * const mips_hwr_names_mips3264r2[32] = +{ "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", @@ -288,20 +288,23 @@ static const char * const mips_hwr_names "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" }; -struct mips_abi_choice { - const char *name; +struct mips_abi_choice +{ + const char * name; const char * const *gpr_names; const char * const *fpr_names; }; -struct mips_abi_choice mips_abi_choices[] = { +struct mips_abi_choice mips_abi_choices[] = +{ { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, { "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, { "64", mips_gpr_names_newabi, mips_fpr_names_64 }, }; -struct mips_arch_choice { +struct mips_arch_choice +{ const char *name; int bfd_mach_valid; unsigned long bfd_mach; @@ -313,7 +316,8 @@ struct mips_arch_choice { const char * const *hwr_names; }; -const struct mips_arch_choice mips_arch_choices[] = { +const struct mips_arch_choice mips_arch_choices[] = +{ { "numeric", 0, 0, 0, 0, mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, @@ -415,55 +419,38 @@ static int mips_cp0sel_names_len; static const char * const *mips_hwr_names; /* Other options */ -static int no_aliases; /* If set disassemble as most general inst. */ - -static const struct mips_abi_choice *choose_abi_by_name - PARAMS ((const char *, unsigned int)); -static const struct mips_arch_choice *choose_arch_by_name - PARAMS ((const char *, unsigned int)); -static const struct mips_arch_choice *choose_arch_by_number - PARAMS ((unsigned long)); -static const struct mips_cp0sel_name *lookup_mips_cp0sel_name - PARAMS ((const struct mips_cp0sel_name *, unsigned int, unsigned int, - unsigned int)); +static int no_aliases; /* If set disassemble as most general inst. */ static const struct mips_abi_choice * -choose_abi_by_name (name, namelen) - const char *name; - unsigned int namelen; +choose_abi_by_name (const char *name, unsigned int namelen) { const struct mips_abi_choice *c; unsigned int i; for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) - { - if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 - && strlen (mips_abi_choices[i].name) == namelen) - c = &mips_abi_choices[i]; - } + if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 + && strlen (mips_abi_choices[i].name) == namelen) + c = &mips_abi_choices[i]; + return c; } static const struct mips_arch_choice * -choose_arch_by_name (name, namelen) - const char *name; - unsigned int namelen; +choose_arch_by_name (const char *name, unsigned int namelen) { const struct mips_arch_choice *c = NULL; unsigned int i; for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) - { - if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 - && strlen (mips_arch_choices[i].name) == namelen) - c = &mips_arch_choices[i]; - } + if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 + && strlen (mips_arch_choices[i].name) == namelen) + c = &mips_arch_choices[i]; + return c; } static const struct mips_arch_choice * -choose_arch_by_number (mach) - unsigned long mach; +choose_arch_by_number (unsigned long mach) { static unsigned long hint_bfd_mach; static const struct mips_arch_choice *hint_arch_choice; @@ -490,9 +477,24 @@ choose_arch_by_number (mach) return c; } -void -set_default_mips_dis_options (info) - struct disassemble_info *info; +/* Check if the object uses NewABI conventions. */ + +static int +is_newabi (Elf_Internal_Ehdr *header) +{ + /* There are no old-style ABIs which use 64-bit ELF. */ + if (header->e_ident[EI_CLASS] == ELFCLASS64) + return 1; + + /* If a 32-bit ELF file, n32 is a new-style ABI. */ + if ((header->e_flags & EF_MIPS_ABI2) != 0) + return 1; + + return 0; +} + +static void +set_default_mips_dis_options (struct disassemble_info *info) { const struct mips_arch_choice *chosen_arch; @@ -538,10 +540,8 @@ set_default_mips_dis_options (info) #endif } -void -parse_mips_dis_option (option, len) - const char *option; - unsigned int len; +static void +parse_mips_dis_option (const char *option, unsigned int len) { unsigned int i, optionlen, vallen; const char *val; @@ -557,10 +557,9 @@ parse_mips_dis_option (option, len) /* Look for the = that delimits the end of the option name. */ for (i = 0; i < len; i++) - { - if (option[i] == '=') - break; - } + if (option[i] == '=') + break; + if (i == 0) /* Invalid option: no name before '='. */ return; if (i == len) /* Invalid option: no '='. */ @@ -572,8 +571,8 @@ parse_mips_dis_option (option, len) val = option + (optionlen + 1); vallen = len - (optionlen + 1); - if (strncmp("gpr-names", option, optionlen) == 0 - && strlen("gpr-names") == optionlen) + if (strncmp ("gpr-names", option, optionlen) == 0 + && strlen ("gpr-names") == optionlen) { chosen_abi = choose_abi_by_name (val, vallen); if (chosen_abi != NULL) @@ -581,8 +580,8 @@ parse_mips_dis_option (option, len) return; } - if (strncmp("fpr-names", option, optionlen) == 0 - && strlen("fpr-names") == optionlen) + if (strncmp ("fpr-names", option, optionlen) == 0 + && strlen ("fpr-names") == optionlen) { chosen_abi = choose_abi_by_name (val, vallen); if (chosen_abi != NULL) @@ -590,8 +589,8 @@ parse_mips_dis_option (option, len) return; } - if (strncmp("cp0-names", option, optionlen) == 0 - && strlen("cp0-names") == optionlen) + if (strncmp ("cp0-names", option, optionlen) == 0 + && strlen ("cp0-names") == optionlen) { chosen_arch = choose_arch_by_name (val, vallen); if (chosen_arch != NULL) @@ -603,8 +602,8 @@ parse_mips_dis_option (option, len) return; } - if (strncmp("hwr-names", option, optionlen) == 0 - && strlen("hwr-names") == optionlen) + if (strncmp ("hwr-names", option, optionlen) == 0 + && strlen ("hwr-names") == optionlen) { chosen_arch = choose_arch_by_name (val, vallen); if (chosen_arch != NULL) @@ -612,8 +611,8 @@ parse_mips_dis_option (option, len) return; } - if (strncmp("reg-names", option, optionlen) == 0 - && strlen("reg-names") == optionlen) + if (strncmp ("reg-names", option, optionlen) == 0 + && strlen ("reg-names") == optionlen) { /* We check both ABI and ARCH here unconditionally, so that "numeric" will do the desirable thing: select @@ -639,9 +638,8 @@ parse_mips_dis_option (option, len) /* Invalid option. */ } -void -parse_mips_dis_options (options) - const char *options; +static void +parse_mips_dis_options (const char *options) { const char *option_end; @@ -671,9 +669,10 @@ parse_mips_dis_options (options) } static const struct mips_cp0sel_name * -lookup_mips_cp0sel_name(names, len, cp0reg, sel) - const struct mips_cp0sel_name *names; - unsigned int len, cp0reg, sel; +lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names, + unsigned int len, + unsigned int cp0reg, + unsigned int sel) { unsigned int i; @@ -686,11 +685,10 @@ lookup_mips_cp0sel_name(names, len, cp0r /* Print insn arguments for 32/64-bit code. */ static void -print_insn_args (d, l, pc, info) - const char *d; - register unsigned long int l; - bfd_vma pc; - struct disassemble_info *info; +print_insn_args (const char *d, + register unsigned long int l, + bfd_vma pc, + struct disassemble_info *info) { int op, delta; unsigned int lsb, msb, msbd; @@ -798,7 +796,7 @@ print_insn_args (d, l, pc, info) case 'i': case 'u': - (*info->fprintf_func) (info->stream, "0x%x", + (*info->fprintf_func) (info->stream, "0x%lx", (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); break; @@ -872,32 +870,33 @@ print_insn_args (d, l, pc, info) break; case '<': - (*info->fprintf_func) (info->stream, "0x%x", + (*info->fprintf_func) (info->stream, "0x%lx", (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); break; case 'c': - (*info->fprintf_func) (info->stream, "0x%x", + (*info->fprintf_func) (info->stream, "0x%lx", (l >> OP_SH_CODE) & OP_MASK_CODE); break; case 'q': - (*info->fprintf_func) (info->stream, "0x%x", + (*info->fprintf_func) (info->stream, "0x%lx", (l >> OP_SH_CODE2) & OP_MASK_CODE2); break; case 'C': - (*info->fprintf_func) (info->stream, "0x%x", + (*info->fprintf_func) (info->stream, "0x%lx", (l >> OP_SH_COPZ) & OP_MASK_COPZ); break; case 'B': - (*info->fprintf_func) (info->stream, "0x%x", + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_CODE20) & OP_MASK_CODE20); break; case 'J': - (*info->fprintf_func) (info->stream, "0x%x", + (*info->fprintf_func) (info->stream, "0x%lx", (l >> OP_SH_CODE19) & OP_MASK_CODE19); break; @@ -931,7 +930,7 @@ print_insn_args (d, l, pc, info) 'T' format. Therefore, until we gain understanding of cp2 register names, we can simply print the register numbers. */ - (*info->fprintf_func) (info->stream, "$%d", + (*info->fprintf_func) (info->stream, "$%ld", (l >> OP_SH_RT) & OP_MASK_RT); break; @@ -945,7 +944,7 @@ print_insn_args (d, l, pc, info) (*info->fprintf_func) (info->stream, "%s", mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]); else - (*info->fprintf_func) (info->stream, "$%d", + (*info->fprintf_func) (info->stream, "$%ld", (l >> OP_SH_RD) & OP_MASK_RD); break; @@ -955,79 +954,81 @@ print_insn_args (d, l, pc, info) break; case 'N': - (*info->fprintf_func) (info->stream, "$fcc%d", + (*info->fprintf_func) (info->stream, "$fcc%ld", (l >> OP_SH_BCC) & OP_MASK_BCC); break; case 'M': - (*info->fprintf_func) (info->stream, "$fcc%d", + (*info->fprintf_func) (info->stream, "$fcc%ld", (l >> OP_SH_CCC) & OP_MASK_CCC); break; case 'P': - (*info->fprintf_func) (info->stream, "%d", + (*info->fprintf_func) (info->stream, "%ld", (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); break; case 'e': - (*info->fprintf_func) (info->stream, "%d", + (*info->fprintf_func) (info->stream, "%ld", (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE); break; case '%': - (*info->fprintf_func) (info->stream, "%d", + (*info->fprintf_func) (info->stream, "%ld", (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN); break; case 'H': - (*info->fprintf_func) (info->stream, "%d", + (*info->fprintf_func) (info->stream, "%ld", (l >> OP_SH_SEL) & OP_MASK_SEL); break; case 'O': - (*info->fprintf_func) (info->stream, "%d", + (*info->fprintf_func) (info->stream, "%ld", (l >> OP_SH_ALN) & OP_MASK_ALN); break; case 'Q': { unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL; + if ((vsel & 0x10) == 0) { int fmt; + vsel &= 0x0f; for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) if ((vsel & 1) == 0) break; - (*info->fprintf_func) (info->stream, "$v%d[%d]", + (*info->fprintf_func) (info->stream, "$v%ld[%d]", (l >> OP_SH_FT) & OP_MASK_FT, vsel >> 1); } else if ((vsel & 0x08) == 0) { - (*info->fprintf_func) (info->stream, "$v%d", + (*info->fprintf_func) (info->stream, "$v%ld", (l >> OP_SH_FT) & OP_MASK_FT); } else { - (*info->fprintf_func) (info->stream, "0x%x", + (*info->fprintf_func) (info->stream, "0x%lx", (l >> OP_SH_FT) & OP_MASK_FT); } } break; case 'X': - (*info->fprintf_func) (info->stream, "$v%d", + (*info->fprintf_func) (info->stream, "$v%ld", (l >> OP_SH_FD) & OP_MASK_FD); break; case 'Y': - (*info->fprintf_func) (info->stream, "$v%d", + (*info->fprintf_func) (info->stream, "$v%ld", (l >> OP_SH_FS) & OP_MASK_FS); break; case 'Z': - (*info->fprintf_func) (info->stream, "$v%d", + (*info->fprintf_func) (info->stream, "$v%ld", (l >> OP_SH_FT) & OP_MASK_FT); break; @@ -1041,35 +1042,17 @@ print_insn_args (d, l, pc, info) } } -/* Check if the object uses NewABI conventions. */ - -static int -is_newabi (header) - Elf_Internal_Ehdr *header; -{ - /* There are no old-style ABIs which use 64-bit ELF. */ - if (header->e_ident[EI_CLASS] == ELFCLASS64) - return 1; - - /* If a 32-bit ELF file, n32 is a new-style ABI. */ - if ((header->e_flags & EF_MIPS_ABI2) != 0) - return 1; - - return 0; -} - /* Print the mips instruction at address MEMADDR in debugged memory, on using INFO. Returns length of the instruction, in bytes, which is always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if this is little-endian code. */ static int -print_insn_mips (memaddr, word, info) - bfd_vma memaddr; - unsigned long int word; - struct disassemble_info *info; +print_insn_mips (bfd_vma memaddr, + unsigned long int word, + struct disassemble_info *info) { - register const struct mips_opcode *op; + const struct mips_opcode *op; static bfd_boolean init = 0; static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; @@ -1114,7 +1097,7 @@ print_insn_mips (memaddr, word, info) && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) && (word & op->mask) == op->match) { - register const char *d; + const char *d; /* We always allow to disassemble the jalx instruction. */ if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor) @@ -1159,334 +1142,106 @@ print_insn_mips (memaddr, word, info) /* Handle undefined instructions. */ info->insn_type = dis_noninsn; - (*info->fprintf_func) (info->stream, "0x%x", word); + (*info->fprintf_func) (info->stream, "0x%lx", word); return INSNLEN; } -/* In an environment where we do not know the symbol type of the - instruction we are forced to assume that the low order bit of the - instructions' address may mark it as a mips16 instruction. If we - are single stepping, or the pc is within the disassembled function, - this works. Otherwise, we need a clue. Sometimes. */ +/* Disassemble an operand for a mips16 instruction. */ -static int -_print_insn_mips (memaddr, info, endianness) - bfd_vma memaddr; - struct disassemble_info *info; - enum bfd_endian endianness; +static void +print_mips16_insn_arg (char type, + const struct mips_opcode *op, + int l, + bfd_boolean use_extend, + int extend, + bfd_vma memaddr, + struct disassemble_info *info) { - bfd_byte buffer[INSNLEN]; - int status; - - set_default_mips_dis_options (info); - parse_mips_dis_options (info->disassembler_options); - -#if 1 - /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */ - /* Only a few tools will work this way. */ - if (memaddr & 0x01) - return print_insn_mips16 (memaddr, info); -#endif - -#if SYMTAB_AVAILABLE - if (info->mach == bfd_mach_mips16 - || (info->flavour == bfd_target_elf_flavour - && info->symbols != NULL - && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other - == STO_MIPS16))) - return print_insn_mips16 (memaddr, info); -#endif - - status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); - if (status == 0) + switch (type) { - unsigned long insn; + case ',': + case '(': + case ')': + (*info->fprintf_func) (info->stream, "%c", type); + break; - if (endianness == BFD_ENDIAN_BIG) - insn = (unsigned long) bfd_getb32 (buffer); - else - insn = (unsigned long) bfd_getl32 (buffer); + case 'y': + case 'w': + (*info->fprintf_func) (info->stream, "%s", + mips16_reg_names[((l >> MIPS16OP_SH_RY) + & MIPS16OP_MASK_RY)]); + break; - return print_insn_mips (memaddr, insn, info); - } - else - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } -} + case 'x': + case 'v': + (*info->fprintf_func) (info->stream, "%s", + mips16_reg_names[((l >> MIPS16OP_SH_RX) + & MIPS16OP_MASK_RX)]); + break; -int -print_insn_big_mips (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); -} + case 'z': + (*info->fprintf_func) (info->stream, "%s", + mips16_reg_names[((l >> MIPS16OP_SH_RZ) + & MIPS16OP_MASK_RZ)]); + break; -int -print_insn_little_mips (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); -} - -/* Disassemble mips16 instructions. */ + case 'Z': + (*info->fprintf_func) (info->stream, "%s", + mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z) + & MIPS16OP_MASK_MOVE32Z)]); + break; -static int -print_insn_mips16 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - int status; - bfd_byte buffer[2]; - int length; - int insn; - bfd_boolean use_extend; - int extend = 0; - const struct mips_opcode *op, *opend; + case '0': + (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); + break; - info->bytes_per_chunk = 2; - info->display_endian = info->endian; - info->insn_info_valid = 1; - info->branch_delay_insns = 0; - info->data_size = 0; - info->insn_type = dis_nonbranch; - info->target = 0; - info->target2 = 0; + case 'S': + (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]); + break; - status = (*info->read_memory_func) (memaddr, buffer, 2, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } + case 'P': + (*info->fprintf_func) (info->stream, "$pc"); + break; - length = 2; + case 'R': + (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]); + break; - if (info->endian == BFD_ENDIAN_BIG) - insn = bfd_getb16 (buffer); - else - insn = bfd_getl16 (buffer); + case 'X': + (*info->fprintf_func) (info->stream, "%s", + mips_gpr_names[((l >> MIPS16OP_SH_REGR32) + & MIPS16OP_MASK_REGR32)]); + break; - /* Handle the extend opcode specially. */ - use_extend = FALSE; - if ((insn & 0xf800) == 0xf000) - { - use_extend = TRUE; - extend = insn & 0x7ff; + case 'Y': + (*info->fprintf_func) (info->stream, "%s", + mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]); + break; - memaddr += 2; - - status = (*info->read_memory_func) (memaddr, buffer, 2, info); - if (status != 0) - { - (*info->fprintf_func) (info->stream, "extend 0x%x", - (unsigned int) extend); - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - - if (info->endian == BFD_ENDIAN_BIG) - insn = bfd_getb16 (buffer); - else - insn = bfd_getl16 (buffer); - - /* Check for an extend opcode followed by an extend opcode. */ - if ((insn & 0xf800) == 0xf000) - { - (*info->fprintf_func) (info->stream, "extend 0x%x", - (unsigned int) extend); - info->insn_type = dis_noninsn; - return length; - } - - length += 2; - } - - /* FIXME: Should probably use a hash table on the major opcode here. */ - - opend = mips16_opcodes + bfd_mips16_num_opcodes; - for (op = mips16_opcodes; op < opend; op++) - { - if (op->pinfo != INSN_MACRO - && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) - && (insn & op->mask) == op->match) - { - const char *s; - - if (strchr (op->args, 'a') != NULL) - { - if (use_extend) - { - (*info->fprintf_func) (info->stream, "extend 0x%x", - (unsigned int) extend); - info->insn_type = dis_noninsn; - return length - 2; - } - - use_extend = FALSE; - - memaddr += 2; - - status = (*info->read_memory_func) (memaddr, buffer, 2, - info); - if (status == 0) - { - use_extend = TRUE; - if (info->endian == BFD_ENDIAN_BIG) - extend = bfd_getb16 (buffer); - else - extend = bfd_getl16 (buffer); - length += 2; - } - } - - (*info->fprintf_func) (info->stream, "%s", op->name); - if (op->args[0] != '\0') - (*info->fprintf_func) (info->stream, "\t"); - - for (s = op->args; *s != '\0'; s++) - { - if (*s == ',' - && s[1] == 'w' - && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) - == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) - { - /* Skip the register and the comma. */ - ++s; - continue; - } - if (*s == ',' - && s[1] == 'v' - && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) - == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) - { - /* Skip the register and the comma. */ - ++s; - continue; - } - print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, - info); - } - - if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) - { - info->branch_delay_insns = 1; - if (info->insn_type != dis_jsr) - info->insn_type = dis_branch; - } - - return length; - } - } - - if (use_extend) - (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); - (*info->fprintf_func) (info->stream, "0x%x", insn); - info->insn_type = dis_noninsn; - - return length; -} - -/* Disassemble an operand for a mips16 instruction. */ - -static void -print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info) - char type; - const struct mips_opcode *op; - int l; - bfd_boolean use_extend; - int extend; - bfd_vma memaddr; - struct disassemble_info *info; -{ - switch (type) - { - case ',': - case '(': - case ')': - (*info->fprintf_func) (info->stream, "%c", type); - break; - - case 'y': - case 'w': - (*info->fprintf_func) (info->stream, "%s", - mips16_reg_names[((l >> MIPS16OP_SH_RY) - & MIPS16OP_MASK_RY)]); - break; - - case 'x': - case 'v': - (*info->fprintf_func) (info->stream, "%s", - mips16_reg_names[((l >> MIPS16OP_SH_RX) - & MIPS16OP_MASK_RX)]); - break; - - case 'z': - (*info->fprintf_func) (info->stream, "%s", - mips16_reg_names[((l >> MIPS16OP_SH_RZ) - & MIPS16OP_MASK_RZ)]); - break; - - case 'Z': - (*info->fprintf_func) (info->stream, "%s", - mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z) - & MIPS16OP_MASK_MOVE32Z)]); - break; - - case '0': - (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); - break; - - case 'S': - (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]); - break; - - case 'P': - (*info->fprintf_func) (info->stream, "$pc"); - break; - - case 'R': - (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]); - break; - - case 'X': - (*info->fprintf_func) (info->stream, "%s", - mips_gpr_names[((l >> MIPS16OP_SH_REGR32) - & MIPS16OP_MASK_REGR32)]); - break; - - case 'Y': - (*info->fprintf_func) (info->stream, "%s", - mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]); - break; - - case '<': - case '>': - case '[': - case ']': - case '4': - case '5': - case 'H': - case 'W': - case 'D': - case 'j': - case '6': - case '8': - case 'V': - case 'C': - case 'U': - case 'k': - case 'K': - case 'p': - case 'q': - case 'A': - case 'B': - case 'E': - { - int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; + case '<': + case '>': + case '[': + case ']': + case '4': + case '5': + case 'H': + case 'W': + case 'D': + case 'j': + case '6': + case '8': + case 'V': + case 'C': + case 'U': + case 'k': + case 'K': + case 'p': + case 'q': + case 'A': + case 'B': + case 'E': + { + int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; shift = 0; signedp = 0; @@ -1796,9 +1551,228 @@ print_mips16_insn_arg (type, op, l, use_ } } +/* Disassemble mips16 instructions. */ + +static int +print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) +{ + int status; + bfd_byte buffer[2]; + int length; + int insn; + bfd_boolean use_extend; + int extend = 0; + const struct mips_opcode *op, *opend; + + info->bytes_per_chunk = 2; + info->display_endian = info->endian; + info->insn_info_valid = 1; + info->branch_delay_insns = 0; + info->data_size = 0; + info->insn_type = dis_nonbranch; + info->target = 0; + info->target2 = 0; + + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + length = 2; + + if (info->endian == BFD_ENDIAN_BIG) + insn = bfd_getb16 (buffer); + else + insn = bfd_getl16 (buffer); + + /* Handle the extend opcode specially. */ + use_extend = FALSE; + if ((insn & 0xf800) == 0xf000) + { + use_extend = TRUE; + extend = insn & 0x7ff; + + memaddr += 2; + + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->fprintf_func) (info->stream, "extend 0x%x", + (unsigned int) extend); + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + if (info->endian == BFD_ENDIAN_BIG) + insn = bfd_getb16 (buffer); + else + insn = bfd_getl16 (buffer); + + /* Check for an extend opcode followed by an extend opcode. */ + if ((insn & 0xf800) == 0xf000) + { + (*info->fprintf_func) (info->stream, "extend 0x%x", + (unsigned int) extend); + info->insn_type = dis_noninsn; + return length; + } + + length += 2; + } + + /* FIXME: Should probably use a hash table on the major opcode here. */ + + opend = mips16_opcodes + bfd_mips16_num_opcodes; + for (op = mips16_opcodes; op < opend; op++) + { + if (op->pinfo != INSN_MACRO + && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) + && (insn & op->mask) == op->match) + { + const char *s; + + if (strchr (op->args, 'a') != NULL) + { + if (use_extend) + { + (*info->fprintf_func) (info->stream, "extend 0x%x", + (unsigned int) extend); + info->insn_type = dis_noninsn; + return length - 2; + } + + use_extend = FALSE; + + memaddr += 2; + + status = (*info->read_memory_func) (memaddr, buffer, 2, + info); + if (status == 0) + { + use_extend = TRUE; + if (info->endian == BFD_ENDIAN_BIG) + extend = bfd_getb16 (buffer); + else + extend = bfd_getl16 (buffer); + length += 2; + } + } + + (*info->fprintf_func) (info->stream, "%s", op->name); + if (op->args[0] != '\0') + (*info->fprintf_func) (info->stream, "\t"); + + for (s = op->args; *s != '\0'; s++) + { + if (*s == ',' + && s[1] == 'w' + && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) + == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) + { + /* Skip the register and the comma. */ + ++s; + continue; + } + if (*s == ',' + && s[1] == 'v' + && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) + == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) + { + /* Skip the register and the comma. */ + ++s; + continue; + } + print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, + info); + } + + if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) + { + info->branch_delay_insns = 1; + if (info->insn_type != dis_jsr) + info->insn_type = dis_branch; + } + + return length; + } + } + + if (use_extend) + (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); + (*info->fprintf_func) (info->stream, "0x%x", insn); + info->insn_type = dis_noninsn; + + return length; +} + +/* In an environment where we do not know the symbol type of the + instruction we are forced to assume that the low order bit of the + instructions' address may mark it as a mips16 instruction. If we + are single stepping, or the pc is within the disassembled function, + this works. Otherwise, we need a clue. Sometimes. */ + +static int +_print_insn_mips (bfd_vma memaddr, + struct disassemble_info *info, + enum bfd_endian endianness) +{ + bfd_byte buffer[INSNLEN]; + int status; + + set_default_mips_dis_options (info); + parse_mips_dis_options (info->disassembler_options); + +#if 1 + /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */ + /* Only a few tools will work this way. */ + if (memaddr & 0x01) + return print_insn_mips16 (memaddr, info); +#endif + +#if SYMTAB_AVAILABLE + if (info->mach == bfd_mach_mips16 + || (info->flavour == bfd_target_elf_flavour + && info->symbols != NULL + && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other + == STO_MIPS16))) + return print_insn_mips16 (memaddr, info); +#endif + + status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); + if (status == 0) + { + unsigned long insn; + + if (endianness == BFD_ENDIAN_BIG) + insn = (unsigned long) bfd_getb32 (buffer); + else + insn = (unsigned long) bfd_getl32 (buffer); + + return print_insn_mips (memaddr, insn, info); + } + else + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } +} + +int +print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info) +{ + return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); +} + +int +print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info) +{ + return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); +} + void -print_mips_disassembler_options (stream) - FILE *stream; +print_mips_disassembler_options (FILE *stream) { unsigned int i; diff -uprN binutils-2.16.91.0.1/opcodes/mmix-dis.c binutils-2.16.91.0.2/opcodes/mmix-dis.c --- binutils-2.16.91.0.1/opcodes/mmix-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/mmix-dis.c 2005-07-20 12:27:29.291863464 -0700 @@ -2,21 +2,22 @@ Copyright 2000, 2001, 2002 Free Software Foundation, Inc. Written by Hans-Peter Nilsson (hp@bitrange.com) -This file is part of GDB and the GNU binutils. + This file is part of GDB and the GNU binutils. -GDB and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version 2, -or (at your option) any later version. - -GDB and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + GDB and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version 2, + or (at your option) any later version. + + GDB and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include #include @@ -37,14 +38,14 @@ Software Foundation, 51 Franklin Street } \ while (0) -#define FATAL_DEBUG \ - do \ - { \ - fprintf (stderr, \ - _("Internal: Non-debugged code (test-case missing): %s:%d"), \ - __FILE__, __LINE__); \ - abort (); \ - } \ +#define FATAL_DEBUG \ + do \ + { \ + fprintf (stderr, \ + _("Internal: Non-debugged code (test-case missing): %s:%d"),\ + __FILE__, __LINE__); \ + abort (); \ + } \ while (0) #define ROUND_MODE(n) \ @@ -66,17 +67,10 @@ struct mmix_dis_info char basic_reg_name[256][sizeof ("$255")]; }; -static bfd_boolean initialize_mmix_dis_info - PARAMS ((struct disassemble_info *)); -static const struct mmix_opcode *get_opcode - PARAMS ((unsigned long)); - - /* Initialize a target-specific array in INFO. */ static bfd_boolean -initialize_mmix_dis_info (info) - struct disassemble_info *info; +initialize_mmix_dis_info (struct disassemble_info *info) { struct mmix_dis_info *minfop = malloc (sizeof (struct mmix_dis_info)); int i; @@ -107,7 +101,8 @@ initialize_mmix_dis_info (info) long i; if (syms == NULL) - { FATAL_DEBUG; + { + FATAL_DEBUG; free (minfop); return FALSE; } @@ -138,7 +133,7 @@ initialize_mmix_dis_info (info) for (i = 0; mmix_spec_regs[i].name != NULL; i++) minfop->spec_reg_name[mmix_spec_regs[i].number] = mmix_spec_regs[i].name; - info->private_data = (PTR) minfop; + info->private_data = (void *) minfop; return TRUE; } @@ -150,12 +145,12 @@ initialize_mmix_dis_info (info) "further entry" will just show that there was no other match. */ static const struct mmix_opcode * -get_opcode (insn) - unsigned long insn; +get_opcode (unsigned long insn) { static const struct mmix_opcode **opcodes = NULL; const struct mmix_opcode *opcodep = mmix_opcodes; unsigned int opcode_part = (insn >> 24) & 255; + if (opcodes == NULL) opcodes = xcalloc (256, sizeof (struct mmix_opcode *)); @@ -213,6 +208,7 @@ get_opcode (insn) case mmix_operands_roundregs: { int midbyte = (insn >> 8) & 255; + if (midbyte <= 4) return opcodep; } @@ -248,9 +244,7 @@ get_opcode (insn) /* The main disassembly function. */ int -print_insn_mmix (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_mmix (bfd_vma memaddr, struct disassemble_info *info) { unsigned char buffer[4]; unsigned long insn; diff -uprN binutils-2.16.91.0.1/opcodes/ms1-asm.c binutils-2.16.91.0.2/opcodes/ms1-asm.c --- binutils-2.16.91.0.1/opcodes/ms1-asm.c 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/ms1-asm.c 2005-07-20 12:27:29.300861980 -0700 @@ -1,26 +1,27 @@ /* Assembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-asm.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -48,16 +49,6 @@ static const char * parse_insn_normal /* -- assembler routines inserted here. */ /* -- asm.c */ -static int signed_out_of_bounds (long); -static const char * parse_imm16 (CGEN_CPU_DESC, const char **, int, long *); -static const char * parse_dup (CGEN_CPU_DESC, const char **, int, long *); -static const char * parse_ball (CGEN_CPU_DESC, const char **, int, long *); -static const char * parse_xmode (CGEN_CPU_DESC, const char **, int, long *); -static const char * parse_rc (CGEN_CPU_DESC, const char **, int, long *); -static const char * parse_cbrb (CGEN_CPU_DESC, const char **, int, long *); -static const char * parse_rbbc (CGEN_CPU_DESC, const char **, int, long *); -static const char * parse_type (CGEN_CPU_DESC, const char **, int, long *); - /* Range checking for signed numbers. Returns 0 if acceptable and 1 if the value is out of bounds for a signed quantity. */ @@ -73,8 +64,9 @@ static const char * parse_imm16 (CGEN_CPU_DESC cd, const char **strp, int opindex, - long *valuep) + void *arg) { + signed long * valuep = (signed long *) arg; const char *errmsg; enum cgen_parse_operand_result result_type; bfd_reloc_code_real_type code = BFD_RELOC_NONE; @@ -177,9 +169,9 @@ parse_imm16 (CGEN_CPU_DESC cd, else { /* MS1_OPERAND_IMM16Z. Parse as an unsigned integer. */ - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) valuep); - if (opindex == (CGEN_OPERAND_TYPE)MS1_OPERAND_IMM16 + if (opindex == (CGEN_OPERAND_TYPE) MS1_OPERAND_IMM16 && *valuep >= 0x8000 && *valuep <= 0xffff) *valuep -= 0x10000; @@ -194,7 +186,7 @@ static const char * parse_dup (CGEN_CPU_DESC cd, const char **strp, int opindex, - long *valuep) + unsigned long *valuep) { const char *errmsg = NULL; @@ -219,7 +211,7 @@ static const char * parse_ball (CGEN_CPU_DESC cd, const char **strp, int opindex, - long *valuep) + unsigned long *valuep) { const char *errmsg = NULL; @@ -243,7 +235,7 @@ static const char * parse_xmode (CGEN_CPU_DESC cd, const char **strp, int opindex, - long *valuep) + unsigned long *valuep) { const char *errmsg = NULL; @@ -267,7 +259,7 @@ static const char * parse_rc (CGEN_CPU_DESC cd, const char **strp, int opindex, - long *valuep) + unsigned long *valuep) { const char *errmsg = NULL; @@ -291,7 +283,7 @@ static const char * parse_cbrb (CGEN_CPU_DESC cd, const char **strp, int opindex, - long *valuep) + unsigned long *valuep) { const char *errmsg = NULL; @@ -315,7 +307,7 @@ static const char * parse_rbbc (CGEN_CPU_DESC cd, const char **strp, int opindex, - long *valuep) + unsigned long *valuep) { const char *errmsg = NULL; @@ -349,7 +341,7 @@ static const char * parse_type (CGEN_CPU_DESC cd, const char **strp, int opindex, - long *valuep) + unsigned long *valuep) { const char *errmsg = NULL; @@ -380,7 +372,7 @@ parse_type (CGEN_CPU_DESC cd, /* -- dis.c */ const char * ms1_cgen_parse_operand - PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); /* Main entry point for operand parsing. @@ -396,11 +388,10 @@ const char * ms1_cgen_parse_operand the handlers. */ const char * -ms1_cgen_parse_operand (cd, opindex, strp, fields) - CGEN_CPU_DESC cd; - int opindex; - const char ** strp; - CGEN_FIELDS * fields; +ms1_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) { const char * errmsg = NULL; /* Used by scalar operands that still need to be parsed. */ @@ -565,8 +556,7 @@ cgen_parse_fn * const ms1_cgen_parse_han }; void -ms1_cgen_init_asm (cd) - CGEN_CPU_DESC cd; +ms1_cgen_init_asm (CGEN_CPU_DESC cd) { ms1_cgen_init_opcode_table (cd); ms1_cgen_init_ibld_table (cd); @@ -949,30 +939,3 @@ ms1_cgen_assemble_insn (CGEN_CPU_DESC cd return NULL; } } - -#if 0 /* This calls back to GAS which we can't do without care. */ - -/* Record each member of OPVALS in the assembler's symbol table. - This lets GAS parse registers for us. - ??? Interesting idea but not currently used. */ - -/* Record each member of OPVALS in the assembler's symbol table. - FIXME: Not currently used. */ - -void -ms1_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) -{ - CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); - const CGEN_KEYWORD_ENTRY * ke; - - while ((ke = cgen_keyword_search_next (& search)) != NULL) - { -#if 0 /* Unnecessary, should be done in the search routine. */ - if (! ms1_cgen_opval_supported (ke)) - continue; -#endif - cgen_asm_record_register (cd, ke->name, ke->value); - } -} - -#endif /* 0 */ diff -uprN binutils-2.16.91.0.1/opcodes/ms1-desc.c binutils-2.16.91.0.2/opcodes/ms1-desc.c --- binutils-2.16.91.0.1/opcodes/ms1-desc.c 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/ms1-desc.c 2005-07-20 12:27:29.302861651 -0700 @@ -919,27 +919,23 @@ static const CGEN_IBASE ms1_cgen_insn_ta #undef A /* Initialize anything needed to be done once, before any cpu_open call. */ -static void init_tables PARAMS ((void)); static void -init_tables () +init_tables (void) { } -static const CGEN_MACH * lookup_mach_via_bfd_name - PARAMS ((const CGEN_MACH *, const char *)); -static void build_hw_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_operand_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_insn_table PARAMS ((CGEN_CPU_TABLE *)); -static void ms1_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *)); +static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); +static void build_hw_table (CGEN_CPU_TABLE *); +static void build_ifield_table (CGEN_CPU_TABLE *); +static void build_operand_table (CGEN_CPU_TABLE *); +static void build_insn_table (CGEN_CPU_TABLE *); +static void ms1_cgen_rebuild_tables (CGEN_CPU_TABLE *); /* Subroutine of ms1_cgen_cpu_open to look up a mach via its bfd name. */ static const CGEN_MACH * -lookup_mach_via_bfd_name (table, name) - const CGEN_MACH *table; - const char *name; +lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) { while (table->name) { @@ -953,8 +949,7 @@ lookup_mach_via_bfd_name (table, name) /* Subroutine of ms1_cgen_cpu_open to build the hardware table. */ static void -build_hw_table (cd) - CGEN_CPU_TABLE *cd; +build_hw_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; @@ -980,8 +975,7 @@ build_hw_table (cd) /* Subroutine of ms1_cgen_cpu_open to build the hardware table. */ static void -build_ifield_table (cd) - CGEN_CPU_TABLE *cd; +build_ifield_table (CGEN_CPU_TABLE *cd) { cd->ifld_table = & ms1_cgen_ifld_table[0]; } @@ -989,8 +983,7 @@ build_ifield_table (cd) /* Subroutine of ms1_cgen_cpu_open to build the hardware table. */ static void -build_operand_table (cd) - CGEN_CPU_TABLE *cd; +build_operand_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; @@ -998,8 +991,7 @@ build_operand_table (cd) /* MAX_OPERANDS is only an upper bound on the number of selected entries. However each entry is indexed by it's enum so there can be holes in the table. */ - const CGEN_OPERAND **selected = - (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); cd->operand_table.init_entries = init; cd->operand_table.entry_size = sizeof (CGEN_OPERAND); @@ -1022,12 +1014,11 @@ build_operand_table (cd) operand elements to be in the table [which they mightn't be]. */ static void -build_insn_table (cd) - CGEN_CPU_TABLE *cd; +build_insn_table (CGEN_CPU_TABLE *cd) { int i; const CGEN_IBASE *ib = & ms1_cgen_insn_table[0]; - CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); for (i = 0; i < MAX_INSNS; ++i) @@ -1040,8 +1031,7 @@ build_insn_table (cd) /* Subroutine of ms1_cgen_cpu_open to rebuild the tables. */ static void -ms1_cgen_rebuild_tables (cd) - CGEN_CPU_TABLE *cd; +ms1_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) { int i; unsigned int isas = cd->isas; @@ -1053,7 +1043,7 @@ ms1_cgen_rebuild_tables (cd) #define UNSET (CGEN_SIZE_UNKNOWN + 1) cd->default_insn_bitsize = UNSET; cd->base_insn_bitsize = UNSET; - cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) if (((1 << i) & isas) != 0) @@ -1065,7 +1055,7 @@ ms1_cgen_rebuild_tables (cd) if (cd->default_insn_bitsize == UNSET) cd->default_insn_bitsize = isa->default_insn_bitsize; else if (isa->default_insn_bitsize == cd->default_insn_bitsize) - ; /* this is ok */ + ; /* This is ok. */ else cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; @@ -1074,7 +1064,7 @@ ms1_cgen_rebuild_tables (cd) if (cd->base_insn_bitsize == UNSET) cd->base_insn_bitsize = isa->base_insn_bitsize; else if (isa->base_insn_bitsize == cd->base_insn_bitsize) - ; /* this is ok */ + ; /* This is ok. */ else cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; @@ -1186,12 +1176,12 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_ar } va_end (ap); - /* mach unspecified means "all" */ + /* Mach unspecified means "all". */ if (machs == 0) machs = (1 << MAX_MACHS) - 1; - /* base mach is always selected */ + /* Base mach is always selected. */ machs |= 1; - /* isa unspecified means "all" */ + /* ISA unspecified means "all". */ if (isas == 0) isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) @@ -1224,9 +1214,7 @@ ms1_cgen_cpu_open (enum cgen_cpu_open_ar MACH_NAME is the bfd name of the mach. */ CGEN_CPU_DESC -ms1_cgen_cpu_open_1 (mach_name, endian) - const char *mach_name; - enum cgen_endian endian; +ms1_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) { return ms1_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, CGEN_CPU_OPEN_ENDIAN, endian, @@ -1239,8 +1227,7 @@ ms1_cgen_cpu_open_1 (mach_name, endian) place as some simulator ports use this but they don't use libopcodes. */ void -ms1_cgen_cpu_close (cd) - CGEN_CPU_DESC cd; +ms1_cgen_cpu_close (CGEN_CPU_DESC cd) { unsigned int i; const CGEN_INSN *insns; @@ -1249,23 +1236,17 @@ ms1_cgen_cpu_close (cd) { insns = cd->macro_insn_table.init_entries; for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) - { - if (CGEN_INSN_RX ((insns))) - regfree (CGEN_INSN_RX (insns)); - } + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); } if (cd->insn_table.init_entries) { insns = cd->insn_table.init_entries; for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) - { - if (CGEN_INSN_RX (insns)) - regfree (CGEN_INSN_RX (insns)); - } - } - - + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } if (cd->macro_insn_table.init_entries) free ((CGEN_INSN *) cd->macro_insn_table.init_entries); diff -uprN binutils-2.16.91.0.1/opcodes/ms1-dis.c binutils-2.16.91.0.2/opcodes/ms1-dis.c --- binutils-2.16.91.0.1/opcodes/ms1-dis.c 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/ms1-dis.c 2005-07-20 12:27:29.304861321 -0700 @@ -1,27 +1,27 @@ /* Disassembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-dis.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 -Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -56,7 +56,7 @@ static int read_insn (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, unsigned long *); -/* -- disassembler routines inserted here */ +/* -- disassembler routines inserted here. */ /* -- dis.c */ static void print_dollarhex (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int); @@ -71,7 +71,7 @@ print_dollarhex (CGEN_CPU_DESC cd ATTRIB { disassemble_info *info = (disassemble_info *) dis_info; - info->fprintf_func (info->stream, "$%x", value); + info->fprintf_func (info->stream, "$%lx", value); if (0) print_normal (cd, dis_info, value, attrs, pc, length); @@ -81,8 +81,7 @@ print_dollarhex (CGEN_CPU_DESC cd ATTRIB /* -- */ void ms1_cgen_print_operand - PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, - void const *, bfd_vma, int)); + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); /* Main entry point for printing operands. XINFO is a `void *' and not a `disassemble_info *' to not put a requirement @@ -100,16 +99,15 @@ void ms1_cgen_print_operand the handlers. */ void -ms1_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) - CGEN_CPU_DESC cd; - int opindex; - PTR xinfo; - CGEN_FIELDS *fields; - void const *attrs ATTRIBUTE_UNUSED; - bfd_vma pc; - int length; +ms1_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) { - disassemble_info *info = (disassemble_info *) xinfo; + disassemble_info *info = (disassemble_info *) xinfo; switch (opindex) { @@ -270,8 +268,7 @@ cgen_print_fn * const ms1_cgen_print_han void -ms1_cgen_init_dis (cd) - CGEN_CPU_DESC cd; +ms1_cgen_init_dis (CGEN_CPU_DESC cd) { ms1_cgen_init_opcode_table (cd); ms1_cgen_init_ibld_table (cd); @@ -323,7 +320,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUT /* Print the operand as directed by the attributes. */ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) - ; /* nothing to do */ + ; /* Nothing to do. */ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) (*info->print_address_func) (value, info); else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) @@ -405,6 +402,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UN unsigned long *insn_value) { int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) { (*info->memory_error_func) (status, pc, info); @@ -509,13 +507,13 @@ print_insn (CGEN_CPU_DESC cd, length = CGEN_EXTRACT_FN (cd, insn) (cd, insn, &ex_info, insn_value_cropped, &fields, pc); - /* length < 0 -> error */ + /* Length < 0 -> error. */ if (length < 0) return length; if (length > 0) { CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); - /* length is in bits, result is in bytes */ + /* Length is in bits, result is in bytes. */ return length / 8; } } @@ -565,7 +563,8 @@ default_print_insn (CGEN_CPU_DESC cd, bf Print one instruction from PC on INFO->STREAM. Return the size of the instruction (in bytes). */ -typedef struct cpu_desc_list { +typedef struct cpu_desc_list +{ struct cpu_desc_list *next; int isa; int mach; @@ -650,7 +649,7 @@ print_insn_ms1 (bfd_vma pc, disassemble_ if (!cd) abort (); - /* save this away for future reference */ + /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; cl->isa = isa; diff -uprN binutils-2.16.91.0.1/opcodes/ms1-ibld.c binutils-2.16.91.0.2/opcodes/ms1-ibld.c --- binutils-2.16.91.0.1/opcodes/ms1-ibld.c 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/ms1-ibld.c 2005-07-20 12:27:29.306860991 -0700 @@ -1,25 +1,26 @@ /* Instruction building/extraction support for ms1. -*- C -*- -THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. -- the resultant file is machine generated, cgen-ibld.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -35,9 +36,9 @@ along with this program; if not, write t #include "opintl.h" #include "safe-ctype.h" -#undef min +#undef min #define min(a,b) ((a) < (b) ? (a) : (b)) -#undef max +#undef max #define max(a,b) ((a) > (b) ? (a) : (b)) /* Used by the ifield rtx function. */ @@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd, if (length == 0) return NULL; -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - if (word_length > 32) abort (); @@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd, #if CGEN_INT_INSN_P /* Cover function to store an insn value into an integral insn. Must go here - because it needs -desc.h for CGEN_INT_INSN_P. */ + because it needs -desc.h for CGEN_INT_INSN_P. */ static void put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, @@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATT int shift = insn_length - length; /* Written this way to avoid undefined behaviour. */ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); } } @@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd, { unsigned long x; int shift; -#if 0 - int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; -#endif + x = cgen_get_insn_value (cd, bufp, word_length); if (CGEN_INSN_LSB0_P) @@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd, return 1; } -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - if (word_length > 32) abort (); @@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd, return CGEN_INSN_BITSIZE (insn); } -/* machine generated code added here */ +/* Machine generated code added here. */ const char * ms1_cgen_insert_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); /* Main entry point for operand insertion. @@ -559,12 +547,11 @@ const char * ms1_cgen_insert_operand resolved during parsing. */ const char * -ms1_cgen_insert_operand (cd, opindex, fields, buffer, pc) - CGEN_CPU_DESC cd; - int opindex; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc ATTRIBUTE_UNUSED; +ms1_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) { const char * errmsg = NULL; unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); @@ -732,8 +719,7 @@ ms1_cgen_insert_operand (cd, opindex, fi } int ms1_cgen_extract_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - CGEN_FIELDS *, bfd_vma)); + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); /* Main entry point for operand extraction. The result is <= 0 for error, >0 for success. @@ -751,13 +737,12 @@ int ms1_cgen_extract_operand the handlers. */ int -ms1_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) - CGEN_CPU_DESC cd; - int opindex; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS * fields; - bfd_vma pc; +ms1_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) { /* Assume success (for those operands that are nops). */ int length = 1; @@ -937,10 +922,8 @@ cgen_extract_fn * const ms1_cgen_extract extract_insn_normal, }; -int ms1_cgen_get_int_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); -bfd_vma ms1_cgen_get_vma_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +int ms1_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma ms1_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); /* Getting values from cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they return. @@ -948,10 +931,9 @@ bfd_vma ms1_cgen_get_vma_operand not appropriate. */ int -ms1_cgen_get_int_operand (cd, opindex, fields) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - const CGEN_FIELDS * fields; +ms1_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) { int value; @@ -1110,10 +1092,9 @@ ms1_cgen_get_int_operand (cd, opindex, f } bfd_vma -ms1_cgen_get_vma_operand (cd, opindex, fields) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - const CGEN_FIELDS * fields; +ms1_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) { bfd_vma value; @@ -1271,10 +1252,8 @@ ms1_cgen_get_vma_operand (cd, opindex, f return value; } -void ms1_cgen_set_int_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); -void ms1_cgen_set_vma_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); +void ms1_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void ms1_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); /* Stuffing values in cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they accept. @@ -1282,11 +1261,10 @@ void ms1_cgen_set_vma_operand not appropriate. */ void -ms1_cgen_set_int_operand (cd, opindex, fields, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - CGEN_FIELDS * fields; - int value; +ms1_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) { switch (opindex) { @@ -1441,11 +1419,10 @@ ms1_cgen_set_int_operand (cd, opindex, f } void -ms1_cgen_set_vma_operand (cd, opindex, fields, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - CGEN_FIELDS * fields; - bfd_vma value; +ms1_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) { switch (opindex) { @@ -1602,8 +1579,7 @@ ms1_cgen_set_vma_operand (cd, opindex, f /* Function to call before using the instruction builder tables. */ void -ms1_cgen_init_ibld_table (cd) - CGEN_CPU_DESC cd; +ms1_cgen_init_ibld_table (CGEN_CPU_DESC cd) { cd->insert_handlers = & ms1_cgen_insert_handlers[0]; cd->extract_handlers = & ms1_cgen_extract_handlers[0]; diff -uprN binutils-2.16.91.0.1/opcodes/ms1-opc.c binutils-2.16.91.0.2/opcodes/ms1-opc.c --- binutils-2.16.91.0.1/opcodes/ms1-opc.c 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/ms1-opc.c 2005-07-20 12:27:29.307860826 -0700 @@ -69,10 +69,10 @@ ms1_asm_hash (const char* insn) /* The hash functions are recorded here to help keep assembler code out of the disassembler and vice versa. */ -static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int asm_hash_insn PARAMS ((const char *)); -static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); /* Instruction formats. */ @@ -839,14 +839,10 @@ dis_hash_insn (buf, value) return CGEN_DIS_HASH (buf, value); } -static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int)); - /* Set the recorded length of the insn in the CGEN_FIELDS struct. */ static void -set_fields_bitsize (fields, size) - CGEN_FIELDS *fields; - int size; +set_fields_bitsize (CGEN_FIELDS *fields, int size) { CGEN_FIELDS_BITSIZE (fields) = size; } @@ -855,15 +851,15 @@ set_fields_bitsize (fields, size) This plugs the opcode entries and macro instructions into the cpu table. */ void -ms1_cgen_init_opcode_table (cd) - CGEN_CPU_DESC cd; +ms1_cgen_init_opcode_table (CGEN_CPU_DESC cd) { int i; int num_macros = (sizeof (ms1_cgen_macro_insn_table) / sizeof (ms1_cgen_macro_insn_table[0])); const CGEN_IBASE *ib = & ms1_cgen_macro_insn_table[0]; const CGEN_OPCODE *oc = & ms1_cgen_macro_insn_opcode_table[0]; - CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN)); + CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); for (i = 0; i < num_macros; ++i) { diff -uprN binutils-2.16.91.0.1/opcodes/msp430-dis.c binutils-2.16.91.0.2/opcodes/msp430-dis.c --- binutils-2.16.91.0.1/opcodes/msp430-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/msp430-dis.c 2005-07-20 12:27:29.308860661 -0700 @@ -1,5 +1,5 @@ /* Disassemble MSP430 instructions. - Copyright (C) 2002, 2004 Free Software Foundation, Inc. + Copyright (C) 2002, 2004, 2005 Free Software Foundation, Inc. Contributed by Dmitry Diky @@ -15,7 +15,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include #include @@ -31,28 +32,10 @@ #undef DASM_SECTION -static unsigned short msp430dis_opcode - PARAMS ((bfd_vma, disassemble_info *)); -int print_insn_msp430 - PARAMS ((bfd_vma, disassemble_info *)); -int msp430_nooperands - PARAMS ((struct msp430_opcode_s *, bfd_vma, unsigned short, char *, int *)); -int msp430_singleoperand - PARAMS ((disassemble_info *, struct msp430_opcode_s *, bfd_vma, unsigned short, - char *, char *, int *)); -int msp430_doubleoperand - PARAMS ((disassemble_info *, struct msp430_opcode_s *, bfd_vma, unsigned short, - char *, char *, char *, char *, int *)); -int msp430_branchinstr - PARAMS ((disassemble_info *, struct msp430_opcode_s *, bfd_vma, unsigned short, - char *, char *, int *)); - #define PS(x) (0xffff & (x)) static unsigned short -msp430dis_opcode (addr, info) - bfd_vma addr; - disassemble_info *info; +msp430dis_opcode (bfd_vma addr, disassemble_info *info) { bfd_byte buffer[2]; int status; @@ -66,138 +49,12 @@ msp430dis_opcode (addr, info) return bfd_getl16 (buffer); } -int -print_insn_msp430 (addr, info) - bfd_vma addr; - disassemble_info *info; -{ - void *stream = info->stream; - fprintf_ftype prin = info->fprintf_func; - struct msp430_opcode_s *opcode; - char op1[32], op2[32], comm1[64], comm2[64]; - int cmd_len = 0; - unsigned short insn; - int cycles = 0; - char *bc = ""; - char dinfo[32]; /* Debug purposes. */ - - insn = msp430dis_opcode (addr, info); - sprintf (dinfo, "0x%04x", insn); - - if (((int) addr & 0xffff) > 0xffdf) - { - (*prin) (stream, "interrupt service routine at 0x%04x", 0xffff & insn); - return 2; - } - - *comm1 = 0; - *comm2 = 0; - - for (opcode = msp430_opcodes; opcode->name; opcode++) - { - if ((insn & opcode->bin_mask) == opcode->bin_opcode - && opcode->bin_opcode != 0x9300) - { - *op1 = 0; - *op2 = 0; - *comm1 = 0; - *comm2 = 0; - - /* r0 as destination. Ad should be zero. */ - if (opcode->insn_opnumb == 3 && (insn & 0x000f) == 0 - && (0x0080 & insn) == 0) - { - cmd_len = - msp430_branchinstr (info, opcode, addr, insn, op1, comm1, - &cycles); - if (cmd_len) - break; - } - - switch (opcode->insn_opnumb) - { - case 0: - cmd_len = msp430_nooperands (opcode, addr, insn, comm1, &cycles); - break; - case 2: - cmd_len = - msp430_doubleoperand (info, opcode, addr, insn, op1, op2, - comm1, comm2, &cycles); - if (insn & BYTE_OPERATION) - bc = ".b"; - break; - case 1: - cmd_len = - msp430_singleoperand (info, opcode, addr, insn, op1, comm1, - &cycles); - if (insn & BYTE_OPERATION && opcode->fmt != 3) - bc = ".b"; - break; - default: - break; - } - } - - if (cmd_len) - break; - } - - dinfo[5] = 0; - - if (cmd_len < 1) - { - /* Unknown opcode, or invalid combination of operands. */ - (*prin) (stream, ".word 0x%04x; ????", PS (insn)); - return 2; - } - - (*prin) (stream, "%s%s", opcode->name, bc); - - if (*op1) - (*prin) (stream, "\t%s", op1); - if (*op2) - (*prin) (stream, ","); - - if (strlen (op1) < 7) - (*prin) (stream, "\t"); - if (!strlen (op1)) - (*prin) (stream, "\t"); - - if (*op2) - (*prin) (stream, "%s", op2); - if (strlen (op2) < 8) - (*prin) (stream, "\t"); - - if (*comm1 || *comm2) - (*prin) (stream, ";"); - else if (cycles) - { - if (*op2) - (*prin) (stream, ";"); - else - { - if (strlen (op1) < 7) - (*prin) (stream, ";"); - else - (*prin) (stream, "\t;"); - } - } - if (*comm1) - (*prin) (stream, "%s", comm1); - if (*comm1 && *comm2) - (*prin) (stream, ","); - if (*comm2) - (*prin) (stream, " %s", comm2); - return cmd_len; -} - -int -msp430_nooperands (opcode, addr, insn, comm, cycles) - struct msp430_opcode_s *opcode; - bfd_vma addr ATTRIBUTE_UNUSED; - unsigned short insn ATTRIBUTE_UNUSED; - char *comm; - int *cycles; +static int +msp430_nooperands (struct msp430_opcode_s *opcode, + bfd_vma addr ATTRIBUTE_UNUSED, + unsigned short insn ATTRIBUTE_UNUSED, + char *comm, + int *cycles) { /* Pop with constant. */ if (insn == 0x43b2) @@ -222,16 +79,14 @@ msp430_nooperands (opcode, addr, insn, c return 2; } - -int -msp430_singleoperand (info, opcode, addr, insn, op, comm, cycles) - disassemble_info *info; - struct msp430_opcode_s *opcode; - bfd_vma addr; - unsigned short insn; - char *op; - char *comm; - int *cycles; +static int +msp430_singleoperand (disassemble_info *info, + struct msp430_opcode_s *opcode, + bfd_vma addr, + unsigned short insn, + char *op, + char *comm, + int *cycles) { int regs = 0, regd = 0; int ad = 0, as = 0; @@ -277,7 +132,7 @@ msp430_singleoperand (info, opcode, addr else sprintf (op, "r%d", regd); } - else /* ad == 1 msp430dis_opcode. */ + else /* ad == 1 msp430dis_opcode. */ { if (regd == 0) { @@ -308,7 +163,6 @@ msp430_singleoperand (info, opcode, addr break; case 2: /* rrc, push, call, swpb, rra, sxt, push, call, reti etc... */ - if (as == 0) { if (regd == 3) @@ -427,15 +281,16 @@ msp430_singleoperand (info, opcode, addr return cmd_len; } -int -msp430_doubleoperand (info, opcode, addr, insn, op1, op2, comm1, comm2, cycles) - disassemble_info *info; - struct msp430_opcode_s *opcode; - bfd_vma addr; - unsigned short insn; - char *op1, *op2; - char *comm1, *comm2; - int *cycles; +static int +msp430_doubleoperand (disassemble_info *info, + struct msp430_opcode_s *opcode, + bfd_vma addr, + unsigned short insn, + char *op1, + char *op2, + char *comm1, + char *comm2, + int *cycles) { int regs = 0, regd = 0; int ad = 0, as = 0; @@ -467,7 +322,7 @@ msp430_doubleoperand (info, opcode, addr /* Register mode. */ if (regd == 3) { - strcpy (comm1, "Illegal as emulation instr"); + strcpy (comm1, _("Illegal as emulation instr")); return -1; } @@ -518,7 +373,7 @@ msp430_doubleoperand (info, opcode, addr if (ad == 0 && regd == 3) { /* R2/R3 are illegal as dest: may be data section. */ - strcpy (comm1, "Illegal as 2-op instr"); + strcpy (comm1, _("Illegal as 2-op instr")); return -1; } @@ -579,7 +434,7 @@ msp430_doubleoperand (info, opcode, addr else if (regs == 0) { *cycles = 3; - /* Absolute. @pc+ */ + /* Absolute. @pc+. */ dst = msp430dis_opcode (addr + 2, info); cmd_len += 2; sprintf (op1, "#%d", dst); @@ -647,7 +502,7 @@ msp430_doubleoperand (info, opcode, addr else sprintf (op2, "r%d", regd); } - else /* ad == 1. */ + else /* ad == 1. */ { * cycles += 3; @@ -679,16 +534,14 @@ msp430_doubleoperand (info, opcode, addr return cmd_len; } - -int -msp430_branchinstr (info, opcode, addr, insn, op1, comm1, cycles) - disassemble_info *info; - struct msp430_opcode_s *opcode ATTRIBUTE_UNUSED; - bfd_vma addr ATTRIBUTE_UNUSED; - unsigned short insn; - char *op1; - char *comm1; - int *cycles; +static int +msp430_branchinstr (disassemble_info *info, + struct msp430_opcode_s *opcode ATTRIBUTE_UNUSED, + bfd_vma addr ATTRIBUTE_UNUSED, + unsigned short insn, + char *op1, + char *comm1, + int *cycles) { int regs = 0, regd = 0; int ad = 0, as = 0; @@ -807,3 +660,126 @@ msp430_branchinstr (info, opcode, addr, return cmd_len; } + +int +print_insn_msp430 (bfd_vma addr, disassemble_info *info) +{ + void *stream = info->stream; + fprintf_ftype prin = info->fprintf_func; + struct msp430_opcode_s *opcode; + char op1[32], op2[32], comm1[64], comm2[64]; + int cmd_len = 0; + unsigned short insn; + int cycles = 0; + char *bc = ""; + char dinfo[32]; /* Debug purposes. */ + + insn = msp430dis_opcode (addr, info); + sprintf (dinfo, "0x%04x", insn); + + if (((int) addr & 0xffff) > 0xffdf) + { + (*prin) (stream, "interrupt service routine at 0x%04x", 0xffff & insn); + return 2; + } + + *comm1 = 0; + *comm2 = 0; + + for (opcode = msp430_opcodes; opcode->name; opcode++) + { + if ((insn & opcode->bin_mask) == opcode->bin_opcode + && opcode->bin_opcode != 0x9300) + { + *op1 = 0; + *op2 = 0; + *comm1 = 0; + *comm2 = 0; + + /* r0 as destination. Ad should be zero. */ + if (opcode->insn_opnumb == 3 && (insn & 0x000f) == 0 + && (0x0080 & insn) == 0) + { + cmd_len = + msp430_branchinstr (info, opcode, addr, insn, op1, comm1, + &cycles); + if (cmd_len) + break; + } + + switch (opcode->insn_opnumb) + { + case 0: + cmd_len = msp430_nooperands (opcode, addr, insn, comm1, &cycles); + break; + case 2: + cmd_len = + msp430_doubleoperand (info, opcode, addr, insn, op1, op2, + comm1, comm2, &cycles); + if (insn & BYTE_OPERATION) + bc = ".b"; + break; + case 1: + cmd_len = + msp430_singleoperand (info, opcode, addr, insn, op1, comm1, + &cycles); + if (insn & BYTE_OPERATION && opcode->fmt != 3) + bc = ".b"; + break; + default: + break; + } + } + + if (cmd_len) + break; + } + + dinfo[5] = 0; + + if (cmd_len < 1) + { + /* Unknown opcode, or invalid combination of operands. */ + (*prin) (stream, ".word 0x%04x; ????", PS (insn)); + return 2; + } + + (*prin) (stream, "%s%s", opcode->name, bc); + + if (*op1) + (*prin) (stream, "\t%s", op1); + if (*op2) + (*prin) (stream, ","); + + if (strlen (op1) < 7) + (*prin) (stream, "\t"); + if (!strlen (op1)) + (*prin) (stream, "\t"); + + if (*op2) + (*prin) (stream, "%s", op2); + if (strlen (op2) < 8) + (*prin) (stream, "\t"); + + if (*comm1 || *comm2) + (*prin) (stream, ";"); + else if (cycles) + { + if (*op2) + (*prin) (stream, ";"); + else + { + if (strlen (op1) < 7) + (*prin) (stream, ";"); + else + (*prin) (stream, "\t;"); + } + } + if (*comm1) + (*prin) (stream, "%s", comm1); + if (*comm1 && *comm2) + (*prin) (stream, ","); + if (*comm2) + (*prin) (stream, " %s", comm2); + return cmd_len; +} diff -uprN binutils-2.16.91.0.1/opcodes/ns32k-dis.c binutils-2.16.91.0.2/opcodes/ns32k-dis.c --- binutils-2.16.91.0.1/opcodes/ns32k-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/ns32k-dis.c 2005-07-20 12:27:29.321858518 -0700 @@ -2,21 +2,22 @@ Copyright 1986, 1988, 1991, 1992, 1994, 1998, 2001, 2002, 2005 Free Software Foundation, Inc. -This file is part of opcodes library. + This file is part of opcodes library. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "bfd.h" @@ -30,43 +31,26 @@ Foundation, Inc., 51 Franklin Street - F static disassemble_info *dis_info; -/* - * Hacks to get it to compile <= READ THESE AS FIXES NEEDED - */ -#define INVALID_FLOAT(val, size) invalid_float((bfd_byte *)val, size) - -static int print_insn_arg - PARAMS ((int, int, int *, bfd_byte *, bfd_vma, char *, int)); -static int get_displacement PARAMS ((bfd_byte *, int *)); -static int invalid_float PARAMS ((bfd_byte *, int)); -static long int read_memory_integer PARAMS ((unsigned char *, int)); -static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *)); -struct ns32k_option; -static void optlist PARAMS ((int, const struct ns32k_option *, char *)); -static void list_search PARAMS ((int, const struct ns32k_option *, char *)); -static int bit_extract PARAMS ((bfd_byte *, int, int)); -static int bit_extract_simple PARAMS ((bfd_byte *, int, int)); -static void bit_copy PARAMS ((bfd_byte *, int, int, char *)); -static int sign_extend PARAMS ((int, int)); -static void flip_bytes PARAMS ((char *, int)); - -static long read_memory_integer(addr, nr) - unsigned char *addr; - int nr; +/* Hacks to get it to compile <= READ THESE AS FIXES NEEDED. */ +#define INVALID_FLOAT(val, size) invalid_float ((bfd_byte *) val, size) + +static long +read_memory_integer (unsigned char * addr, int nr) { long val; int i; - for (val = 0, i = nr - 1; i >= 0; i--) { - val = (val << 8); - val |= (0xff & *(addr + i)); - } + + for (val = 0, i = nr - 1; i >= 0; i--) + { + val = (val << 8); + val |= (0xff & *(addr + i)); + } return val; } /* 32000 instructions are never longer than this. */ #define MAXLEN 62 - #include struct private @@ -87,12 +71,10 @@ struct private ? 1 : fetch_data ((info), (addr))) static int -fetch_data (info, addr) - struct disassemble_info *info; - bfd_byte *addr; +fetch_data (struct disassemble_info *info, bfd_byte *addr) { int status; - struct private *priv = (struct private *)info->private_data; + struct private *priv = (struct private *) info->private_data; bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); status = (*info->read_memory_func) (start, @@ -108,20 +90,22 @@ fetch_data (info, addr) priv->max_fetched = addr; return 1; } + /* Number of elements in the opcode table. */ #define NOPCODES (sizeof ns32k_opcodes / sizeof ns32k_opcodes[0]) #define NEXT_IS_ADDR '|' -struct ns32k_option { - char *pattern; /* the option itself */ - unsigned long value; /* binary value of the option */ - unsigned long match; /* these bits must match */ +struct ns32k_option +{ + char *pattern; /* The option itself. */ + unsigned long value; /* Binary value of the option. */ + unsigned long match; /* These bits must match. */ }; -static const struct ns32k_option opt_u[]= /* restore, exit */ +static const struct ns32k_option opt_u[]= /* Restore, exit. */ { { "r0", 0x80, 0x80 }, { "r1", 0x40, 0x40 }, @@ -134,7 +118,7 @@ static const struct ns32k_option opt_u[] { 0 , 0x00, 0x00 } }; -static const struct ns32k_option opt_U[]= /* save, enter */ +static const struct ns32k_option opt_U[]= /* Save, enter. */ { { "r0", 0x01, 0x01 }, { "r1", 0x02, 0x02 }, @@ -147,7 +131,7 @@ static const struct ns32k_option opt_U[] { 0 , 0x00, 0x00 } }; -static const struct ns32k_option opt_O[]= /* setcfg */ +static const struct ns32k_option opt_O[]= /* Setcfg. */ { { "c", 0x8, 0x8 }, { "m", 0x4, 0x4 }, @@ -156,7 +140,7 @@ static const struct ns32k_option opt_O[] { 0 , 0x0, 0x0 } }; -static const struct ns32k_option opt_C[]= /* cinv */ +static const struct ns32k_option opt_C[]= /* Cinv. */ { { "a", 0x4, 0x4 }, { "i", 0x2, 0x2 }, @@ -164,7 +148,7 @@ static const struct ns32k_option opt_C[] { 0 , 0x0, 0x0 } }; -static const struct ns32k_option opt_S[]= /* string inst */ +static const struct ns32k_option opt_S[]= /* String inst. */ { { "b", 0x1, 0x1 }, { "u", 0x6, 0x6 }, @@ -172,7 +156,7 @@ static const struct ns32k_option opt_S[] { 0 , 0x0, 0x0 } }; -static const struct ns32k_option list_P532[]= /* lpr spr */ +static const struct ns32k_option list_P532[]= /* Lpr spr. */ { { "us", 0x0, 0xf }, { "dcr", 0x1, 0xf }, @@ -190,7 +174,7 @@ static const struct ns32k_option list_P5 { 0 , 0x00, 0xf } }; -static const struct ns32k_option list_M532[]= /* lmr smr */ +static const struct ns32k_option list_M532[]= /* Lmr smr. */ { { "mcr", 0x9, 0xf }, { "msr", 0xa, 0xf }, @@ -202,7 +186,7 @@ static const struct ns32k_option list_M5 { 0 , 0x0, 0xf } }; -static const struct ns32k_option list_P032[]= /* lpr spr */ +static const struct ns32k_option list_P032[]= /* Lpr spr. */ { { "upsr", 0x0, 0xf }, { "fp", 0x8, 0xf }, @@ -214,7 +198,7 @@ static const struct ns32k_option list_P0 { 0 , 0x0, 0xf } }; -static const struct ns32k_option list_M032[]= /* lmr smr */ +static const struct ns32k_option list_M032[]= /* Lmr smr. */ { { "bpr0", 0x0, 0xf }, { "bpr1", 0x1, 0xf }, @@ -230,61 +214,55 @@ static const struct ns32k_option list_M0 }; -/* - * figure out which options are present - */ +/* Figure out which options are present. */ + static void -optlist(options, optionP, result) - int options; - const struct ns32k_option *optionP; - char *result; -{ - if (options == 0) { - sprintf(result, "[]"); - return; - } - sprintf(result, "["); - - for (; (options != 0) && optionP->pattern; optionP++) { - if ((options & optionP->match) == optionP->value) { - /* we found a match, update result and options */ - strcat(result, optionP->pattern); - options &= ~optionP->value; - if (options != 0) /* more options to come */ - strcat(result, ","); +optlist (int options, const struct ns32k_option * optionP, char * result) +{ + if (options == 0) + { + sprintf (result, "[]"); + return; + } + + sprintf (result, "["); + + for (; (options != 0) && optionP->pattern; optionP++) + { + if ((options & optionP->match) == optionP->value) + { + /* We found a match, update result and options. */ + strcat (result, optionP->pattern); + options &= ~optionP->value; + if (options != 0) /* More options to come. */ + strcat (result, ","); } } - if (options != 0) - strcat(result, "undefined"); - strcat(result, "]"); + if (options != 0) + strcat (result, "undefined"); + + strcat (result, "]"); } static void -list_search (reg_value, optionP, result) - int reg_value; - const struct ns32k_option *optionP; - char *result; -{ - for (; optionP->pattern; optionP++) { - if ((reg_value & optionP->match) == optionP->value) { - sprintf(result, "%s", optionP->pattern); - return; +list_search (int reg_value, const struct ns32k_option *optionP, char *result) +{ + for (; optionP->pattern; optionP++) + { + if ((reg_value & optionP->match) == optionP->value) + { + sprintf (result, "%s", optionP->pattern); + return; } } - sprintf(result, "undefined"); + sprintf (result, "undefined"); } -/* - * extract "count" bits starting "offset" bits - * into buffer - */ +/* Extract "count" bits starting "offset" bits into buffer. */ static int -bit_extract (buffer, offset, count) - bfd_byte *buffer; - int offset; - int count; +bit_extract (bfd_byte *buffer, int offset, int count) { int result; int bit; @@ -295,7 +273,7 @@ bit_extract (buffer, offset, count) result = 0; while (count--) { - FETCH_DATA(dis_info, buffer + 1); + FETCH_DATA (dis_info, buffer + 1); if ((*buffer & (1 << offset))) result |= bit; if (++offset == 8) @@ -308,14 +286,10 @@ bit_extract (buffer, offset, count) return result; } -/* Like bit extract but the buffer is valid and doen't need to be - * fetched - */ +/* Like bit extract but the buffer is valid and doen't need to be fetched. */ + static int -bit_extract_simple (buffer, offset, count) - bfd_byte *buffer; - int offset; - int count; +bit_extract_simple (bfd_byte *buffer, int offset, int count) { int result; int bit; @@ -339,40 +313,32 @@ bit_extract_simple (buffer, offset, coun } static void -bit_copy (buffer, offset, count, to) - bfd_byte *buffer; - int offset; - int count; - char *to; +bit_copy (bfd_byte *buffer, int offset, int count, char *to) { - for(; count > 8; count -= 8, to++, offset += 8) + for (; count > 8; count -= 8, to++, offset += 8) *to = bit_extract (buffer, offset, 8); *to = bit_extract (buffer, offset, count); } - static int -sign_extend (value, bits) - int value, bits; +sign_extend (int value, int bits) { value = value & ((1 << bits) - 1); - return (value & (1 << (bits-1)) + return (value & (1 << (bits - 1)) ? value | (~((1 << bits) - 1)) : value); } static void -flip_bytes (ptr, count) - char *ptr; - int count; +flip_bytes (char *ptr, int count) { char tmp; while (count > 0) { tmp = ptr[0]; - ptr[0] = ptr[count-1]; - ptr[count-1] = tmp; + ptr[0] = ptr[count - 1]; + ptr[count - 1] = tmp; ptr++; count -= 2; } @@ -384,158 +350,94 @@ flip_bytes (ptr, count) || (c) == 'W' || (c) == 'D' || (c) == 'A' || (c) == 'I' || (c) == 'Z') /* Adressing modes. */ -#define Adrmod_index_byte 0x1c -#define Adrmod_index_word 0x1d -#define Adrmod_index_doubleword 0x1e -#define Adrmod_index_quadword 0x1f +#define Adrmod_index_byte 0x1c +#define Adrmod_index_word 0x1d +#define Adrmod_index_doubleword 0x1e +#define Adrmod_index_quadword 0x1f /* Is MODE an indexed addressing mode? */ #define Adrmod_is_index(mode) \ - (mode == Adrmod_index_byte \ + ( mode == Adrmod_index_byte \ || mode == Adrmod_index_word \ || mode == Adrmod_index_doubleword \ || mode == Adrmod_index_quadword) -/* Print the 32000 instruction at address MEMADDR in debugged memory, - on STREAM. Returns length of the instruction, in bytes. */ - -int -print_insn_ns32k (memaddr, info) - bfd_vma memaddr; - disassemble_info *info; +static int +get_displacement (bfd_byte *buffer, int *aoffsetp) { - unsigned int i; - const char *d; - unsigned short first_word; - int ioffset; /* bits into instruction */ - int aoffset; /* bits into arguments */ - char arg_bufs[MAX_ARGS+1][ARG_LEN]; - int argnum; - int maxarg; - struct private priv; - bfd_byte *buffer = priv.the_buffer; - dis_info = info; - - info->private_data = (PTR) &priv; - priv.max_fetched = priv.the_buffer; - priv.insn_start = memaddr; - if (setjmp (priv.bailout) != 0) - /* Error return. */ - return -1; - - /* Look for 8bit opcodes first. Other wise, fetching two bytes could take - * us over the end of accessible data unnecessarilly - */ - FETCH_DATA(info, buffer + 1); - for (i = 0; i < NOPCODES; i++) - if (ns32k_opcodes[i].opcode_id_size <= 8 - && ((buffer[0] - & (((unsigned long) 1 << ns32k_opcodes[i].opcode_id_size) - 1)) - == ns32k_opcodes[i].opcode_seed)) - break; - if (i == NOPCODES) { - /* Maybe it is 9 to 16 bits big */ - FETCH_DATA(info, buffer + 2); - first_word = read_memory_integer(buffer, 2); - - for (i = 0; i < NOPCODES; i++) - if ((first_word - & (((unsigned long) 1 << ns32k_opcodes[i].opcode_id_size) - 1)) - == ns32k_opcodes[i].opcode_seed) - break; - - /* Handle undefined instructions. */ - if (i == NOPCODES) - { - (*dis_info->fprintf_func)(dis_info->stream, "0%o", buffer[0]); - return 1; - } - } - - (*dis_info->fprintf_func)(dis_info->stream, "%s", ns32k_opcodes[i].name); - - ioffset = ns32k_opcodes[i].opcode_size; - aoffset = ns32k_opcodes[i].opcode_size; - d = ns32k_opcodes[i].operands; + int Ivalue; + short Ivalue2; - if (*d) + Ivalue = bit_extract (buffer, *aoffsetp, 8); + switch (Ivalue & 0xc0) { - /* Offset in bits of the first thing beyond each index byte. - Element 0 is for operand A and element 1 is for operand B. - The rest are irrelevant, but we put them here so we don't - index outside the array. */ - int index_offset[MAX_ARGS]; - - /* 0 for operand A, 1 for operand B, greater for other args. */ - int whicharg = 0; - - (*dis_info->fprintf_func)(dis_info->stream, "\t"); - - maxarg = 0; + case 0x00: + case 0x40: + Ivalue = sign_extend (Ivalue, 7); + *aoffsetp += 8; + break; + case 0x80: + Ivalue2 = bit_extract (buffer, *aoffsetp, 16); + flip_bytes ((char *) & Ivalue2, 2); + Ivalue = sign_extend (Ivalue2, 14); + *aoffsetp += 16; + break; + case 0xc0: + Ivalue = bit_extract (buffer, *aoffsetp, 32); + flip_bytes ((char *) & Ivalue, 4); + Ivalue = sign_extend (Ivalue, 30); + *aoffsetp += 32; + break; + } + return Ivalue; +} - /* First we have to find and keep track of the index bytes, - if we are using scaled indexed addressing mode, since the index - bytes occur right after the basic instruction, not as part - of the addressing extension. */ - if (Is_gen(d[1])) - { - int addr_mode = bit_extract (buffer, ioffset - 5, 5); +#if 1 /* A version that should work on ns32k f's&d's on any machine. */ +static int +invalid_float (bfd_byte *p, int len) +{ + int val; - if (Adrmod_is_index (addr_mode)) - { - aoffset += 8; - index_offset[0] = aoffset; - } - } - if (d[2] && Is_gen(d[3])) - { - int addr_mode = bit_extract (buffer, ioffset - 10, 5); + if (len == 4) + val = (bit_extract_simple (p, 23, 8)/*exponent*/ == 0xff + || (bit_extract_simple (p, 23, 8)/*exponent*/ == 0 + && bit_extract_simple (p, 0, 23)/*mantisa*/ != 0)); + else if (len == 8) + val = (bit_extract_simple (p, 52, 11)/*exponent*/ == 0x7ff + || (bit_extract_simple (p, 52, 11)/*exponent*/ == 0 + && (bit_extract_simple (p, 0, 32)/*low mantisa*/ != 0 + || bit_extract_simple (p, 32, 20)/*high mantisa*/ != 0))); + else + val = 1; + return (val); +} +#else +/* Assumes the bytes have been swapped to local order. */ +typedef union +{ + double d; + float f; + struct { unsigned m:23, e:8, :1;} sf; + struct { unsigned lm; unsigned m:20, e:11, :1;} sd; +} float_type_u; - if (Adrmod_is_index (addr_mode)) - { - aoffset += 8; - index_offset[1] = aoffset; - } - } +static int +invalid_float (float_type_u *p, int len) +{ + int val; - while (*d) - { - argnum = *d - '1'; - d++; - if (argnum > maxarg && argnum < MAX_ARGS) - maxarg = argnum; - ioffset = print_insn_arg (*d, ioffset, &aoffset, buffer, - memaddr, arg_bufs[argnum], - index_offset[whicharg]); - d++; - whicharg++; - } - for (argnum = 0; argnum <= maxarg; argnum++) - { - bfd_vma addr; - char *ch; - for (ch = arg_bufs[argnum]; *ch;) - { - if (*ch == NEXT_IS_ADDR) - { - ++ch; - addr = bfd_scan_vma (ch, NULL, 16); - (*dis_info->print_address_func) (addr, dis_info); - while (*ch && *ch != NEXT_IS_ADDR) - ++ch; - if (*ch) - ++ch; - } - else - (*dis_info->fprintf_func)(dis_info->stream, "%c", *ch++); - } - if (argnum < maxarg) - (*dis_info->fprintf_func)(dis_info->stream, ", "); - } - } - return aoffset / 8; + if (len == sizeof (float)) + val = (p->sf.e == 0xff + || (p->sf.e == 0 && p->sf.m != 0)); + else if (len == sizeof (double)) + val = (p->sd.e == 0x7ff + || (p->sd.e == 0 && (p->sd.m != 0 || p->sd.lm != 0))); + else + val = 1; + return val; } +#endif /* Print an instruction operand of category given by d. IOFFSET is the bit position below which small (<1 byte) parts of the operand can @@ -548,15 +450,16 @@ print_insn_ns32k (memaddr, info) general operand using scaled indexed addressing mode). */ static int -print_insn_arg (d, ioffset, aoffsetp, buffer, addr, result, index_offset) - int d; - int ioffset, *aoffsetp; - bfd_byte *buffer; - bfd_vma addr; - char *result; - int index_offset; +print_insn_arg (int d, + int ioffset, + int *aoffsetp, + bfd_byte *buffer, + bfd_vma addr, + char *result, + int index_offset) { - union { + union + { float f; double d; int i[2]; @@ -570,7 +473,7 @@ print_insn_arg (d, ioffset, aoffsetp, bu switch (d) { case 'f': - /* a "gen" operand but 5 bits from the end of instruction */ + /* A "gen" operand but 5 bits from the end of instruction. */ ioffset -= 5; case 'Z': case 'F': @@ -580,13 +483,13 @@ print_insn_arg (d, ioffset, aoffsetp, bu case 'W': case 'D': case 'A': - addr_mode = bit_extract (buffer, ioffset-5, 5); + addr_mode = bit_extract (buffer, ioffset - 5, 5); ioffset -= 5; switch (addr_mode) { case 0x0: case 0x1: case 0x2: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7: - /* register mode R0 -- R7 */ + /* Register mode R0 -- R7. */ switch (d) { case 'F': @@ -600,34 +503,35 @@ print_insn_arg (d, ioffset, aoffsetp, bu break; case 0x8: case 0x9: case 0xa: case 0xb: case 0xc: case 0xd: case 0xe: case 0xf: - /* Register relative disp(R0 -- R7) */ + /* Register relative disp(R0 -- R7). */ disp1 = get_displacement (buffer, aoffsetp); sprintf (result, "%d(r%d)", disp1, addr_mode & 7); break; case 0x10: case 0x11: case 0x12: - /* Memory relative disp2(disp1(FP, SP, SB)) */ + /* Memory relative disp2(disp1(FP, SP, SB)). */ disp1 = get_displacement (buffer, aoffsetp); disp2 = get_displacement (buffer, aoffsetp); sprintf (result, "%d(%d(%s))", disp2, disp1, - addr_mode==0x10?"fp":addr_mode==0x11?"sp":"sb"); + addr_mode == 0x10 ? "fp" : addr_mode == 0x11 ? "sp" : "sb"); break; case 0x13: - /* reserved */ + /* Reserved. */ sprintf (result, "reserved"); break; case 0x14: - /* Immediate */ + /* Immediate. */ switch (d) { - case 'I': case 'Z': case 'A': + case 'I': + case 'Z': + case 'A': /* I and Z are output operands and can`t be immediate - * A is an address and we can`t have the address of - * an immediate either. We don't know how much to increase - * aoffsetp by since whatever generated this is broken - * anyway! - */ + A is an address and we can`t have the address of + an immediate either. We don't know how much to increase + aoffsetp by since whatever generated this is broken + anyway! */ sprintf (result, _("$")); break; case 'B': @@ -655,7 +559,7 @@ print_insn_arg (d, ioffset, aoffsetp, bu *aoffsetp += 32; if (INVALID_FLOAT (&value.f, 4)) sprintf (result, "<>", value.i[0]); - else /* assume host has ieee float */ + else /* Assume host has ieee float. */ sprintf (result, "$%g", value.f); break; case 'L': @@ -665,43 +569,43 @@ print_insn_arg (d, ioffset, aoffsetp, bu if (INVALID_FLOAT (&value.d, 8)) sprintf (result, "<>", value.i[1], value.i[0]); - else /* assume host has ieee float */ + else /* Assume host has ieee float. */ sprintf (result, "$%g", value.d); break; } break; case 0x15: - /* Absolute @disp */ + /* Absolute @disp. */ disp1 = get_displacement (buffer, aoffsetp); sprintf (result, "@|%d|", disp1); break; case 0x16: - /* External EXT(disp1) + disp2 (Mod table stuff) */ + /* External EXT(disp1) + disp2 (Mod table stuff). */ disp1 = get_displacement (buffer, aoffsetp); disp2 = get_displacement (buffer, aoffsetp); sprintf (result, "EXT(%d) + %d", disp1, disp2); break; case 0x17: - /* Top of stack tos */ + /* Top of stack tos. */ sprintf (result, "tos"); break; case 0x18: - /* Memory space disp(FP) */ + /* Memory space disp(FP). */ disp1 = get_displacement (buffer, aoffsetp); sprintf (result, "%d(fp)", disp1); break; case 0x19: - /* Memory space disp(SP) */ + /* Memory space disp(SP). */ disp1 = get_displacement (buffer, aoffsetp); sprintf (result, "%d(sp)", disp1); break; case 0x1a: - /* Memory space disp(SB) */ + /* Memory space disp(SB). */ disp1 = get_displacement (buffer, aoffsetp); sprintf (result, "%d(sb)", disp1); break; case 0x1b: - /* Memory space disp(PC) */ + /* Memory space disp(PC). */ disp1 = get_displacement (buffer, aoffsetp); *result++ = NEXT_IS_ADDR; sprintf_vma (result, addr + disp1); @@ -713,7 +617,7 @@ print_insn_arg (d, ioffset, aoffsetp, bu case 0x1d: case 0x1e: case 0x1f: - /* Scaled index basemode[R0 -- R7:B,W,D,Q] */ + /* Scaled index basemode[R0 -- R7:B,W,D,Q]. */ index = bit_extract (buffer, index_offset - 8, 3); print_insn_arg (d, index_offset, aoffsetp, buffer, addr, result, 0); @@ -745,22 +649,19 @@ print_insn_arg (d, ioffset, aoffsetp, bu break; case 'b': Ivalue = get_displacement (buffer, aoffsetp); - /* - * Warning!! HACK ALERT! - * Operand type 'b' is only used by the cmp{b,w,d} and - * movm{b,w,d} instructions; we need to know whether - * it's a `b' or `w' or `d' instruction; and for both - * cmpm and movm it's stored at the same place so we - * just grab two bits of the opcode and look at it... - * - */ + /* Warning!! HACK ALERT! + Operand type 'b' is only used by the cmp{b,w,d} and + movm{b,w,d} instructions; we need to know whether + it's a `b' or `w' or `d' instruction; and for both + cmpm and movm it's stored at the same place so we + just grab two bits of the opcode and look at it... */ size = bit_extract(buffer, ioffset-6, 2); - if (size == 0) /* 00 => b */ + if (size == 0) /* 00 => b. */ size = 1; - else if (size == 1) /* 01 => w */ + else if (size == 1) /* 01 => w. */ size = 2; else - size = 4; /* 11 => d */ + size = 4; /* 11 => d. */ sprintf (result, "%d", (Ivalue / size) + 1); break; @@ -778,130 +679,190 @@ print_insn_arg (d, ioffset, aoffsetp, bu break; case 'u': Ivalue = bit_extract (buffer, *aoffsetp, 8); - optlist(Ivalue, opt_u, result); + optlist (Ivalue, opt_u, result); *aoffsetp += 8; break; case 'U': - Ivalue = bit_extract(buffer, *aoffsetp, 8); - optlist(Ivalue, opt_U, result); + Ivalue = bit_extract (buffer, *aoffsetp, 8); + optlist (Ivalue, opt_U, result); *aoffsetp += 8; break; case 'O': - Ivalue = bit_extract(buffer, ioffset-9, 9); - optlist(Ivalue, opt_O, result); + Ivalue = bit_extract (buffer, ioffset - 9, 9); + optlist (Ivalue, opt_O, result); ioffset -= 9; break; case 'C': - Ivalue = bit_extract(buffer, ioffset-4, 4); - optlist(Ivalue, opt_C, result); + Ivalue = bit_extract (buffer, ioffset - 4, 4); + optlist (Ivalue, opt_C, result); ioffset -= 4; break; case 'S': - Ivalue = bit_extract(buffer, ioffset - 8, 8); - optlist(Ivalue, opt_S, result); + Ivalue = bit_extract (buffer, ioffset - 8, 8); + optlist (Ivalue, opt_S, result); ioffset -= 8; break; case 'M': - Ivalue = bit_extract(buffer, ioffset-4, 4); - list_search(Ivalue, 0 ? list_M032 : list_M532, result); + Ivalue = bit_extract (buffer, ioffset - 4, 4); + list_search (Ivalue, 0 ? list_M032 : list_M532, result); ioffset -= 4; break; case 'P': - Ivalue = bit_extract(buffer, ioffset-4, 4); - list_search(Ivalue, 0 ? list_P032 : list_P532, result); + Ivalue = bit_extract (buffer, ioffset - 4, 4); + list_search (Ivalue, 0 ? list_P032 : list_P532, result); ioffset -= 4; break; case 'g': - Ivalue = bit_extract(buffer, *aoffsetp, 3); - sprintf(result, "%d", Ivalue); + Ivalue = bit_extract (buffer, *aoffsetp, 3); + sprintf (result, "%d", Ivalue); *aoffsetp += 3; break; case 'G': Ivalue = bit_extract(buffer, *aoffsetp, 5); - sprintf(result, "%d", Ivalue + 1); + sprintf (result, "%d", Ivalue + 1); *aoffsetp += 5; break; } return ioffset; } -static int -get_displacement (buffer, aoffsetp) - bfd_byte *buffer; - int *aoffsetp; + +/* Print the 32000 instruction at address MEMADDR in debugged memory, + on STREAM. Returns length of the instruction, in bytes. */ + +int +print_insn_ns32k (bfd_vma memaddr, disassemble_info *info) { - int Ivalue; - short Ivalue2; + unsigned int i; + const char *d; + unsigned short first_word; + int ioffset; /* Bits into instruction. */ + int aoffset; /* Bits into arguments. */ + char arg_bufs[MAX_ARGS+1][ARG_LEN]; + int argnum; + int maxarg; + struct private priv; + bfd_byte *buffer = priv.the_buffer; + dis_info = info; - Ivalue = bit_extract (buffer, *aoffsetp, 8); - switch (Ivalue & 0xc0) - { - case 0x00: - case 0x40: - Ivalue = sign_extend (Ivalue, 7); - *aoffsetp += 8; - break; - case 0x80: - Ivalue2 = bit_extract (buffer, *aoffsetp, 16); - flip_bytes ((char *) & Ivalue2, 2); - Ivalue = sign_extend (Ivalue2, 14); - *aoffsetp += 16; - break; - case 0xc0: - Ivalue = bit_extract (buffer, *aoffsetp, 32); - flip_bytes ((char *) & Ivalue, 4); - Ivalue = sign_extend (Ivalue, 30); - *aoffsetp += 32; + info->private_data = & priv; + priv.max_fetched = priv.the_buffer; + priv.insn_start = memaddr; + if (setjmp (priv.bailout) != 0) + /* Error return. */ + return -1; + + /* Look for 8bit opcodes first. Other wise, fetching two bytes could take + us over the end of accessible data unnecessarilly. */ + FETCH_DATA (info, buffer + 1); + for (i = 0; i < NOPCODES; i++) + if (ns32k_opcodes[i].opcode_id_size <= 8 + && ((buffer[0] + & (((unsigned long) 1 << ns32k_opcodes[i].opcode_id_size) - 1)) + == ns32k_opcodes[i].opcode_seed)) break; + if (i == NOPCODES) + { + /* Maybe it is 9 to 16 bits big. */ + FETCH_DATA (info, buffer + 2); + first_word = read_memory_integer(buffer, 2); + + for (i = 0; i < NOPCODES; i++) + if ((first_word + & (((unsigned long) 1 << ns32k_opcodes[i].opcode_id_size) - 1)) + == ns32k_opcodes[i].opcode_seed) + break; + + /* Handle undefined instructions. */ + if (i == NOPCODES) + { + (*dis_info->fprintf_func)(dis_info->stream, "0%o", buffer[0]); + return 1; + } } - return Ivalue; -} - -#if 1 /* a version that should work on ns32k f's&d's on any machine */ -static int -invalid_float (p, len) - register bfd_byte *p; - register int len; -{ - register int val; - - if ( len == 4 ) - val = (bit_extract_simple(p, 23, 8)/*exponent*/ == 0xff - || (bit_extract_simple(p, 23, 8)/*exponent*/ == 0 && - bit_extract_simple(p, 0, 23)/*mantisa*/ != 0)); - else if ( len == 8 ) - val = (bit_extract_simple(p, 52, 11)/*exponent*/ == 0x7ff - || (bit_extract_simple(p, 52, 11)/*exponent*/ == 0 - && (bit_extract_simple(p, 0, 32)/*low mantisa*/ != 0 - || bit_extract_simple(p, 32, 20)/*high mantisa*/ != 0))); - else - val = 1; - return (val); -} -#else + (*dis_info->fprintf_func)(dis_info->stream, "%s", ns32k_opcodes[i].name); -/* assumes the bytes have been swapped to local order */ -typedef union { double d; - float f; - struct { unsigned m:23, e:8, :1;} sf; - struct { unsigned lm; unsigned m:20, e:11, :1;} sd; - } float_type_u; + ioffset = ns32k_opcodes[i].opcode_size; + aoffset = ns32k_opcodes[i].opcode_size; + d = ns32k_opcodes[i].operands; -static int -invalid_float (p, len) - register float_type_u *p; - register int len; -{ - register int val; - if ( len == sizeof (float) ) - val = (p->sf.e == 0xff - || (p->sf.e == 0 && p->sf.m != 0)); - else if ( len == sizeof (double) ) - val = (p->sd.e == 0x7ff - || (p->sd.e == 0 && (p->sd.m != 0 || p->sd.lm != 0))); - else - val = 1; - return (val); + if (*d) + { + /* Offset in bits of the first thing beyond each index byte. + Element 0 is for operand A and element 1 is for operand B. + The rest are irrelevant, but we put them here so we don't + index outside the array. */ + int index_offset[MAX_ARGS]; + + /* 0 for operand A, 1 for operand B, greater for other args. */ + int whicharg = 0; + + (*dis_info->fprintf_func)(dis_info->stream, "\t"); + + maxarg = 0; + + /* First we have to find and keep track of the index bytes, + if we are using scaled indexed addressing mode, since the index + bytes occur right after the basic instruction, not as part + of the addressing extension. */ + if (Is_gen(d[1])) + { + int addr_mode = bit_extract (buffer, ioffset - 5, 5); + + if (Adrmod_is_index (addr_mode)) + { + aoffset += 8; + index_offset[0] = aoffset; + } + } + + if (d[2] && Is_gen(d[3])) + { + int addr_mode = bit_extract (buffer, ioffset - 10, 5); + + if (Adrmod_is_index (addr_mode)) + { + aoffset += 8; + index_offset[1] = aoffset; + } + } + + while (*d) + { + argnum = *d - '1'; + d++; + if (argnum > maxarg && argnum < MAX_ARGS) + maxarg = argnum; + ioffset = print_insn_arg (*d, ioffset, &aoffset, buffer, + memaddr, arg_bufs[argnum], + index_offset[whicharg]); + d++; + whicharg++; + } + for (argnum = 0; argnum <= maxarg; argnum++) + { + bfd_vma addr; + char *ch; + + for (ch = arg_bufs[argnum]; *ch;) + { + if (*ch == NEXT_IS_ADDR) + { + ++ch; + addr = bfd_scan_vma (ch, NULL, 16); + (*dis_info->print_address_func) (addr, dis_info); + while (*ch && *ch != NEXT_IS_ADDR) + ++ch; + if (*ch) + ++ch; + } + else + (*dis_info->fprintf_func)(dis_info->stream, "%c", *ch++); + } + if (argnum < maxarg) + (*dis_info->fprintf_func)(dis_info->stream, ", "); + } + } + return aoffset / 8; } -#endif diff -uprN binutils-2.16.91.0.1/opcodes/openrisc-asm.c binutils-2.16.91.0.2/opcodes/openrisc-asm.c --- binutils-2.16.91.0.1/opcodes/openrisc-asm.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/openrisc-asm.c 2005-07-20 12:27:29.323858188 -0700 @@ -1,26 +1,27 @@ /* Assembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-asm.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -49,16 +50,12 @@ static const char * parse_insn_normal /* -- asm.c */ -#define CGEN_VERBOSE_ASSEMBLER_ERRORS +static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'"); -static const char * parse_hi16 - PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); -static const char * parse_lo16 - PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +#define CGEN_VERBOSE_ASSEMBLER_ERRORS long -openrisc_sign_extend_16bit (value) - long value; +openrisc_sign_extend_16bit (long value) { return ((value & 0xffff) ^ 0x8000) - 0x8000; } @@ -66,11 +63,7 @@ openrisc_sign_extend_16bit (value) /* Handle hi(). */ static const char * -parse_hi16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - long *valuep; +parse_hi16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -85,9 +78,9 @@ parse_hi16 (cd, strp, opindex, valuep) *strp += 3; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return _("missing `)'"); + return MISSING_CLOSING_PARENTHESIS; ++*strp; if (errmsg == NULL @@ -120,11 +113,7 @@ parse_hi16 (cd, strp, opindex, valuep) /* Handle lo(). */ static const char * -parse_lo16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - long *valuep; +parse_lo16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; @@ -139,9 +128,9 @@ parse_lo16 (cd, strp, opindex, valuep) *strp += 3; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, - &result_type, &value); + & result_type, & value); if (**strp != ')') - return _("missing `)'"); + return MISSING_CLOSING_PARENTHESIS; ++*strp; ret = value; @@ -171,7 +160,7 @@ parse_lo16 (cd, strp, opindex, valuep) /* -- */ const char * openrisc_cgen_parse_operand - PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); /* Main entry point for operand parsing. @@ -187,11 +176,10 @@ const char * openrisc_cgen_parse_operand the handlers. */ const char * -openrisc_cgen_parse_operand (cd, opindex, strp, fields) - CGEN_CPU_DESC cd; - int opindex; - const char ** strp; - CGEN_FIELDS * fields; +openrisc_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) { const char * errmsg = NULL; /* Used by scalar operands that still need to be parsed. */ @@ -262,8 +250,7 @@ cgen_parse_fn * const openrisc_cgen_pars }; void -openrisc_cgen_init_asm (cd) - CGEN_CPU_DESC cd; +openrisc_cgen_init_asm (CGEN_CPU_DESC cd) { openrisc_cgen_init_opcode_table (cd); openrisc_cgen_init_ibld_table (cd); @@ -646,30 +633,3 @@ openrisc_cgen_assemble_insn (CGEN_CPU_DE return NULL; } } - -#if 0 /* This calls back to GAS which we can't do without care. */ - -/* Record each member of OPVALS in the assembler's symbol table. - This lets GAS parse registers for us. - ??? Interesting idea but not currently used. */ - -/* Record each member of OPVALS in the assembler's symbol table. - FIXME: Not currently used. */ - -void -openrisc_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) -{ - CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); - const CGEN_KEYWORD_ENTRY * ke; - - while ((ke = cgen_keyword_search_next (& search)) != NULL) - { -#if 0 /* Unnecessary, should be done in the search routine. */ - if (! openrisc_cgen_opval_supported (ke)) - continue; -#endif - cgen_asm_record_register (cd, ke->name, ke->value); - } -} - -#endif /* 0 */ diff -uprN binutils-2.16.91.0.1/opcodes/openrisc-desc.c binutils-2.16.91.0.2/opcodes/openrisc-desc.c --- binutils-2.16.91.0.1/opcodes/openrisc-desc.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/openrisc-desc.c 2005-07-20 12:27:29.324858023 -0700 @@ -699,27 +699,23 @@ static const CGEN_IBASE openrisc_cgen_in #undef A /* Initialize anything needed to be done once, before any cpu_open call. */ -static void init_tables PARAMS ((void)); static void -init_tables () +init_tables (void) { } -static const CGEN_MACH * lookup_mach_via_bfd_name - PARAMS ((const CGEN_MACH *, const char *)); -static void build_hw_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_operand_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_insn_table PARAMS ((CGEN_CPU_TABLE *)); -static void openrisc_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *)); +static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); +static void build_hw_table (CGEN_CPU_TABLE *); +static void build_ifield_table (CGEN_CPU_TABLE *); +static void build_operand_table (CGEN_CPU_TABLE *); +static void build_insn_table (CGEN_CPU_TABLE *); +static void openrisc_cgen_rebuild_tables (CGEN_CPU_TABLE *); /* Subroutine of openrisc_cgen_cpu_open to look up a mach via its bfd name. */ static const CGEN_MACH * -lookup_mach_via_bfd_name (table, name) - const CGEN_MACH *table; - const char *name; +lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) { while (table->name) { @@ -733,8 +729,7 @@ lookup_mach_via_bfd_name (table, name) /* Subroutine of openrisc_cgen_cpu_open to build the hardware table. */ static void -build_hw_table (cd) - CGEN_CPU_TABLE *cd; +build_hw_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; @@ -760,8 +755,7 @@ build_hw_table (cd) /* Subroutine of openrisc_cgen_cpu_open to build the hardware table. */ static void -build_ifield_table (cd) - CGEN_CPU_TABLE *cd; +build_ifield_table (CGEN_CPU_TABLE *cd) { cd->ifld_table = & openrisc_cgen_ifld_table[0]; } @@ -769,8 +763,7 @@ build_ifield_table (cd) /* Subroutine of openrisc_cgen_cpu_open to build the hardware table. */ static void -build_operand_table (cd) - CGEN_CPU_TABLE *cd; +build_operand_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; @@ -778,8 +771,7 @@ build_operand_table (cd) /* MAX_OPERANDS is only an upper bound on the number of selected entries. However each entry is indexed by it's enum so there can be holes in the table. */ - const CGEN_OPERAND **selected = - (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); cd->operand_table.init_entries = init; cd->operand_table.entry_size = sizeof (CGEN_OPERAND); @@ -802,12 +794,11 @@ build_operand_table (cd) operand elements to be in the table [which they mightn't be]. */ static void -build_insn_table (cd) - CGEN_CPU_TABLE *cd; +build_insn_table (CGEN_CPU_TABLE *cd) { int i; const CGEN_IBASE *ib = & openrisc_cgen_insn_table[0]; - CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); for (i = 0; i < MAX_INSNS; ++i) @@ -820,8 +811,7 @@ build_insn_table (cd) /* Subroutine of openrisc_cgen_cpu_open to rebuild the tables. */ static void -openrisc_cgen_rebuild_tables (cd) - CGEN_CPU_TABLE *cd; +openrisc_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) { int i; unsigned int isas = cd->isas; @@ -833,7 +823,7 @@ openrisc_cgen_rebuild_tables (cd) #define UNSET (CGEN_SIZE_UNKNOWN + 1) cd->default_insn_bitsize = UNSET; cd->base_insn_bitsize = UNSET; - cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) if (((1 << i) & isas) != 0) @@ -845,7 +835,7 @@ openrisc_cgen_rebuild_tables (cd) if (cd->default_insn_bitsize == UNSET) cd->default_insn_bitsize = isa->default_insn_bitsize; else if (isa->default_insn_bitsize == cd->default_insn_bitsize) - ; /* this is ok */ + ; /* This is ok. */ else cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; @@ -854,7 +844,7 @@ openrisc_cgen_rebuild_tables (cd) if (cd->base_insn_bitsize == UNSET) cd->base_insn_bitsize = isa->base_insn_bitsize; else if (isa->base_insn_bitsize == cd->base_insn_bitsize) - ; /* this is ok */ + ; /* This is ok. */ else cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; @@ -966,12 +956,12 @@ openrisc_cgen_cpu_open (enum cgen_cpu_op } va_end (ap); - /* mach unspecified means "all" */ + /* Mach unspecified means "all". */ if (machs == 0) machs = (1 << MAX_MACHS) - 1; - /* base mach is always selected */ + /* Base mach is always selected. */ machs |= 1; - /* isa unspecified means "all" */ + /* ISA unspecified means "all". */ if (isas == 0) isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) @@ -1004,9 +994,7 @@ openrisc_cgen_cpu_open (enum cgen_cpu_op MACH_NAME is the bfd name of the mach. */ CGEN_CPU_DESC -openrisc_cgen_cpu_open_1 (mach_name, endian) - const char *mach_name; - enum cgen_endian endian; +openrisc_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) { return openrisc_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, CGEN_CPU_OPEN_ENDIAN, endian, @@ -1019,8 +1007,7 @@ openrisc_cgen_cpu_open_1 (mach_name, end place as some simulator ports use this but they don't use libopcodes. */ void -openrisc_cgen_cpu_close (cd) - CGEN_CPU_DESC cd; +openrisc_cgen_cpu_close (CGEN_CPU_DESC cd) { unsigned int i; const CGEN_INSN *insns; @@ -1029,23 +1016,17 @@ openrisc_cgen_cpu_close (cd) { insns = cd->macro_insn_table.init_entries; for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) - { - if (CGEN_INSN_RX ((insns))) - regfree (CGEN_INSN_RX (insns)); - } + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); } if (cd->insn_table.init_entries) { insns = cd->insn_table.init_entries; for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) - { - if (CGEN_INSN_RX (insns)) - regfree (CGEN_INSN_RX (insns)); - } - } - - + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } if (cd->macro_insn_table.init_entries) free ((CGEN_INSN *) cd->macro_insn_table.init_entries); diff -uprN binutils-2.16.91.0.1/opcodes/openrisc-dis.c binutils-2.16.91.0.2/opcodes/openrisc-dis.c --- binutils-2.16.91.0.1/opcodes/openrisc-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/openrisc-dis.c 2005-07-20 12:27:29.326857694 -0700 @@ -1,27 +1,27 @@ /* Disassembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-dis.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 -Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -56,12 +56,11 @@ static int read_insn (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, unsigned long *); -/* -- disassembler routines inserted here */ +/* -- disassembler routines inserted here. */ void openrisc_cgen_print_operand - PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, - void const *, bfd_vma, int)); + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); /* Main entry point for printing operands. XINFO is a `void *' and not a `disassemble_info *' to not put a requirement @@ -79,16 +78,15 @@ void openrisc_cgen_print_operand the handlers. */ void -openrisc_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) - CGEN_CPU_DESC cd; - int opindex; - PTR xinfo; - CGEN_FIELDS *fields; - void const *attrs ATTRIBUTE_UNUSED; - bfd_vma pc; - int length; +openrisc_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) { - disassemble_info *info = (disassemble_info *) xinfo; + disassemble_info *info = (disassemble_info *) xinfo; switch (opindex) { @@ -147,8 +145,7 @@ cgen_print_fn * const openrisc_cgen_prin void -openrisc_cgen_init_dis (cd) - CGEN_CPU_DESC cd; +openrisc_cgen_init_dis (CGEN_CPU_DESC cd) { openrisc_cgen_init_opcode_table (cd); openrisc_cgen_init_ibld_table (cd); @@ -200,7 +197,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUT /* Print the operand as directed by the attributes. */ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) - ; /* nothing to do */ + ; /* Nothing to do. */ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) (*info->print_address_func) (value, info); else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) @@ -282,6 +279,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UN unsigned long *insn_value) { int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) { (*info->memory_error_func) (status, pc, info); @@ -386,13 +384,13 @@ print_insn (CGEN_CPU_DESC cd, length = CGEN_EXTRACT_FN (cd, insn) (cd, insn, &ex_info, insn_value_cropped, &fields, pc); - /* length < 0 -> error */ + /* Length < 0 -> error. */ if (length < 0) return length; if (length > 0) { CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); - /* length is in bits, result is in bytes */ + /* Length is in bits, result is in bytes. */ return length / 8; } } @@ -442,7 +440,8 @@ default_print_insn (CGEN_CPU_DESC cd, bf Print one instruction from PC on INFO->STREAM. Return the size of the instruction (in bytes). */ -typedef struct cpu_desc_list { +typedef struct cpu_desc_list +{ struct cpu_desc_list *next; int isa; int mach; @@ -527,7 +526,7 @@ print_insn_openrisc (bfd_vma pc, disasse if (!cd) abort (); - /* save this away for future reference */ + /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; cl->isa = isa; diff -uprN binutils-2.16.91.0.1/opcodes/openrisc-ibld.c binutils-2.16.91.0.2/opcodes/openrisc-ibld.c --- binutils-2.16.91.0.1/opcodes/openrisc-ibld.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/openrisc-ibld.c 2005-07-20 12:27:29.327857529 -0700 @@ -1,25 +1,26 @@ /* Instruction building/extraction support for openrisc. -*- C -*- -THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. -- the resultant file is machine generated, cgen-ibld.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -35,9 +36,9 @@ along with this program; if not, write t #include "opintl.h" #include "safe-ctype.h" -#undef min +#undef min #define min(a,b) ((a) < (b) ? (a) : (b)) -#undef max +#undef max #define max(a,b) ((a) > (b) ? (a) : (b)) /* Used by the ifield rtx function. */ @@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd, if (length == 0) return NULL; -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - if (word_length > 32) abort (); @@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd, #if CGEN_INT_INSN_P /* Cover function to store an insn value into an integral insn. Must go here - because it needs -desc.h for CGEN_INT_INSN_P. */ + because it needs -desc.h for CGEN_INT_INSN_P. */ static void put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, @@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATT int shift = insn_length - length; /* Written this way to avoid undefined behaviour. */ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); } } @@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd, { unsigned long x; int shift; -#if 0 - int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; -#endif + x = cgen_get_insn_value (cd, bufp, word_length); if (CGEN_INSN_LSB0_P) @@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd, return 1; } -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - if (word_length > 32) abort (); @@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd, return CGEN_INSN_BITSIZE (insn); } -/* machine generated code added here */ +/* Machine generated code added here. */ const char * openrisc_cgen_insert_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); /* Main entry point for operand insertion. @@ -559,12 +547,11 @@ const char * openrisc_cgen_insert_operan resolved during parsing. */ const char * -openrisc_cgen_insert_operand (cd, opindex, fields, buffer, pc) - CGEN_CPU_DESC cd; - int opindex; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc ATTRIBUTE_UNUSED; +openrisc_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) { const char * errmsg = NULL; unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); @@ -641,8 +628,7 @@ openrisc_cgen_insert_operand (cd, opinde } int openrisc_cgen_extract_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - CGEN_FIELDS *, bfd_vma)); + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); /* Main entry point for operand extraction. The result is <= 0 for error, >0 for success. @@ -660,13 +646,12 @@ int openrisc_cgen_extract_operand the handlers. */ int -openrisc_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) - CGEN_CPU_DESC cd; - int opindex; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS * fields; - bfd_vma pc; +openrisc_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) { /* Assume success (for those operands that are nops). */ int length = 1; @@ -752,10 +737,8 @@ cgen_extract_fn * const openrisc_cgen_ex extract_insn_normal, }; -int openrisc_cgen_get_int_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); -bfd_vma openrisc_cgen_get_vma_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +int openrisc_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma openrisc_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); /* Getting values from cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they return. @@ -763,10 +746,9 @@ bfd_vma openrisc_cgen_get_vma_operand not appropriate. */ int -openrisc_cgen_get_int_operand (cd, opindex, fields) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - const CGEN_FIELDS * fields; +openrisc_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) { int value; @@ -823,10 +805,9 @@ openrisc_cgen_get_int_operand (cd, opind } bfd_vma -openrisc_cgen_get_vma_operand (cd, opindex, fields) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - const CGEN_FIELDS * fields; +openrisc_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) { bfd_vma value; @@ -882,10 +863,8 @@ openrisc_cgen_get_vma_operand (cd, opind return value; } -void openrisc_cgen_set_int_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); -void openrisc_cgen_set_vma_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); +void openrisc_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void openrisc_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); /* Stuffing values in cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they accept. @@ -893,11 +872,10 @@ void openrisc_cgen_set_vma_operand not appropriate. */ void -openrisc_cgen_set_int_operand (cd, opindex, fields, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - CGEN_FIELDS * fields; - int value; +openrisc_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) { switch (opindex) { @@ -950,11 +928,10 @@ openrisc_cgen_set_int_operand (cd, opind } void -openrisc_cgen_set_vma_operand (cd, opindex, fields, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - CGEN_FIELDS * fields; - bfd_vma value; +openrisc_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) { switch (opindex) { @@ -1009,8 +986,7 @@ openrisc_cgen_set_vma_operand (cd, opind /* Function to call before using the instruction builder tables. */ void -openrisc_cgen_init_ibld_table (cd) - CGEN_CPU_DESC cd; +openrisc_cgen_init_ibld_table (CGEN_CPU_DESC cd) { cd->insert_handlers = & openrisc_cgen_insert_handlers[0]; cd->extract_handlers = & openrisc_cgen_extract_handlers[0]; diff -uprN binutils-2.16.91.0.1/opcodes/openrisc-opc.c binutils-2.16.91.0.2/opcodes/openrisc-opc.c --- binutils-2.16.91.0.1/opcodes/openrisc-opc.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/openrisc-opc.c 2005-07-20 12:27:29.339855550 -0700 @@ -35,10 +35,10 @@ with this program; if not, write to the /* The hash functions are recorded here to help keep assembler code out of the disassembler and vice versa. */ -static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int asm_hash_insn PARAMS ((const char *)); -static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); /* Instruction formats. */ @@ -650,14 +650,10 @@ dis_hash_insn (buf, value) return CGEN_DIS_HASH (buf, value); } -static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int)); - /* Set the recorded length of the insn in the CGEN_FIELDS struct. */ static void -set_fields_bitsize (fields, size) - CGEN_FIELDS *fields; - int size; +set_fields_bitsize (CGEN_FIELDS *fields, int size) { CGEN_FIELDS_BITSIZE (fields) = size; } @@ -666,15 +662,15 @@ set_fields_bitsize (fields, size) This plugs the opcode entries and macro instructions into the cpu table. */ void -openrisc_cgen_init_opcode_table (cd) - CGEN_CPU_DESC cd; +openrisc_cgen_init_opcode_table (CGEN_CPU_DESC cd) { int i; int num_macros = (sizeof (openrisc_cgen_macro_insn_table) / sizeof (openrisc_cgen_macro_insn_table[0])); const CGEN_IBASE *ib = & openrisc_cgen_macro_insn_table[0]; const CGEN_OPCODE *oc = & openrisc_cgen_macro_insn_opcode_table[0]; - CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN)); + CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); for (i = 0; i < num_macros; ++i) { diff -uprN binutils-2.16.91.0.1/opcodes/openrisc-opc.h binutils-2.16.91.0.2/opcodes/openrisc-opc.h --- binutils-2.16.91.0.1/opcodes/openrisc-opc.h 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/openrisc-opc.h 2005-07-20 12:27:29.339855550 -0700 @@ -31,7 +31,7 @@ with this program; if not, write to the #undef CGEN_DIS_HASH #define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2) -extern long openrisc_sign_extend_16bit PARAMS ((long)); +extern long openrisc_sign_extend_16bit (long); /* -- */ /* Enum declaration for openrisc instruction types. */ typedef enum cgen_insn_type { diff -uprN binutils-2.16.91.0.1/opcodes/or32-dis.c binutils-2.16.91.0.2/opcodes/or32-dis.c --- binutils-2.16.91.0.1/opcodes/or32-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/or32-dis.c 2005-07-20 12:27:29.340855386 -0700 @@ -1,5 +1,5 @@ /* Instruction printing code for the OpenRISC 1000 - Copyright (C) 2002 Free Software Foundation, Inc. + Copyright (C) 2002, 2005 Free Software Foundation, Inc. Contributed by Damjan Lampret . Modified from a29k port. @@ -17,7 +17,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #define DEBUG 0 @@ -29,20 +30,10 @@ #define EXTEND29(x) ((x) & (unsigned long) 0x10000000 ? ((x) | (unsigned long) 0xf0000000) : ((x))) -static void find_bytes_big PARAMS ((unsigned char *, unsigned long *)); -static void find_bytes_little PARAMS ((unsigned char *, unsigned long *)); -static unsigned long or32_extract PARAMS ((char, char *, unsigned long)); -static int or32_opcode_match PARAMS ((unsigned long, char *)); -static void or32_print_register PARAMS ((char, char *, unsigned long, struct disassemble_info *)); -static void or32_print_immediate PARAMS ((char, char *, unsigned long, struct disassemble_info *)); -static int print_insn PARAMS ((bfd_vma, struct disassemble_info *)); - /* Now find the four bytes of INSN_CH and put them in *INSN. */ static void -find_bytes_big (insn_ch, insn) - unsigned char *insn_ch; - unsigned long *insn; +find_bytes_big (unsigned char *insn_ch, unsigned long *insn) { *insn = ((unsigned long) insn_ch[0] << 24) + @@ -55,9 +46,7 @@ find_bytes_big (insn_ch, insn) } static void -find_bytes_little (insn_ch, insn) - unsigned char *insn_ch; - unsigned long *insn; +find_bytes_little (unsigned char *insn_ch, unsigned long *insn) { *insn = ((unsigned long) insn_ch[3] << 24) + @@ -66,14 +55,10 @@ find_bytes_little (insn_ch, insn) ((unsigned long) insn_ch[0]); } -typedef void (*find_byte_func_type) - PARAMS ((unsigned char *, unsigned long *)); +typedef void (*find_byte_func_type) (unsigned char *, unsigned long *); static unsigned long -or32_extract (param_ch, enc_initial, insn) - char param_ch; - char *enc_initial; - unsigned long insn; +or32_extract (char param_ch, char *enc_initial, unsigned long insn) { char *enc; unsigned long ret = 0; @@ -162,9 +147,7 @@ or32_extract (param_ch, enc_initial, ins } static int -or32_opcode_match (insn, encoding) - unsigned long insn; - char *encoding; +or32_opcode_match (unsigned long insn, char *encoding) { unsigned long ones, zeros; @@ -203,11 +186,10 @@ or32_opcode_match (insn, encoding) /* Print register to INFO->STREAM. Used only by print_insn. */ static void -or32_print_register (param_ch, encoding, insn, info) - char param_ch; - char *encoding; - unsigned long insn; - struct disassemble_info *info; +or32_print_register (char param_ch, + char *encoding, + unsigned long insn, + struct disassemble_info *info) { int regnum = or32_extract (param_ch, encoding, insn); @@ -231,11 +213,10 @@ or32_print_register (param_ch, encoding, /* Print immediate to INFO->STREAM. Used only by print_insn. */ static void -or32_print_immediate (param_ch, encoding, insn, info) - char param_ch; - char *encoding; - unsigned long insn; - struct disassemble_info *info; +or32_print_immediate (char param_ch, + char *encoding, + unsigned long insn, + struct disassemble_info *info) { int imm = or32_extract(param_ch, encoding, insn); @@ -250,9 +231,7 @@ or32_print_immediate (param_ch, encoding Return the size of the instruction (always 4 on or32). */ static int -print_insn (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn (bfd_vma memaddr, struct disassemble_info *info) { /* The raw instruction. */ unsigned char insn_ch[4]; @@ -260,7 +239,7 @@ print_insn (memaddr, info) unsigned long addr; /* The four bytes of the instruction. */ unsigned long insn; - find_byte_func_type find_byte_func = (find_byte_func_type)info->private_data; + find_byte_func_type find_byte_func = (find_byte_func_type) info->private_data; struct or32_opcode const * opcode; { @@ -321,28 +300,25 @@ print_insn (memaddr, info) /* This used to be %8x for binutils. */ (*info->fprintf_func) - (info->stream, ".word 0x%08x", insn); + (info->stream, ".word 0x%08lx", insn); return 4; } /* Disassemble a big-endian or32 instruction. */ int -print_insn_big_or32 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_big_or32 (bfd_vma memaddr, struct disassemble_info *info) { - info->private_data = (PTR) find_bytes_big; + info->private_data = find_bytes_big; + return print_insn (memaddr, info); } /* Disassemble a little-endian or32 instruction. */ int -print_insn_little_or32 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_little_or32 (bfd_vma memaddr, struct disassemble_info *info) { - info->private_data = (PTR) find_bytes_little; + info->private_data = find_bytes_little; return print_insn (memaddr, info); } diff -uprN binutils-2.16.91.0.1/opcodes/or32-opc.c binutils-2.16.91.0.2/opcodes/or32-opc.c --- binutils-2.16.91.0.1/opcodes/or32-opc.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/or32-opc.c 2005-07-20 12:27:29.361851923 -0700 @@ -1,5 +1,5 @@ /* Table of opcodes for the OpenRISC 1000 ISA. - Copyright 2002, 2004 Free Software Foundation, Inc. + Copyright 2002, 2004, 2005 Free Software Foundation, Inc. Contributed by Damjan Lampret (lampret@opencores.org). This file is part of gen_or1k_isa, or1k, GDB and GAS. @@ -16,7 +16,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ /* We treat all letters the same in encode/decode routines so we need to assign some characteristics to them like signess etc. */ @@ -30,27 +31,18 @@ #endif #include "opcode/or32.h" -static unsigned long insn_extract PARAMS ((char, char *)); -static unsigned long * cover_insn PARAMS ((unsigned long *, int, unsigned int)); -static int num_ones PARAMS ((unsigned long)); -static struct insn_op_struct * parse_params PARAMS ((const struct or32_opcode *, struct insn_op_struct *)); -static unsigned long or32_extract PARAMS ((char, char *, unsigned long)); -static void or32_print_register PARAMS ((char, char *, unsigned long)); -static void or32_print_immediate PARAMS ((char, char *, unsigned long)); -static unsigned long extend_imm PARAMS ((unsigned long, char)); - const struct or32_letter or32_letters[] = - { - { 'A', NUM_UNSIGNED }, - { 'B', NUM_UNSIGNED }, - { 'D', NUM_UNSIGNED }, - { 'I', NUM_SIGNED }, - { 'K', NUM_UNSIGNED }, - { 'L', NUM_UNSIGNED }, - { 'N', NUM_SIGNED }, - { '0', NUM_UNSIGNED }, - { '\0', 0 } /* Dummy entry. */ - }; +{ + { 'A', NUM_UNSIGNED }, + { 'B', NUM_UNSIGNED }, + { 'D', NUM_UNSIGNED }, + { 'I', NUM_SIGNED }, + { 'K', NUM_UNSIGNED }, + { 'L', NUM_UNSIGNED }, + { 'N', NUM_SIGNED }, + { '0', NUM_UNSIGNED }, + { '\0', 0 } /* Dummy entry. */ +}; /* Opcode encoding: machine[31:30]: first two bits of opcode @@ -76,263 +68,263 @@ const struct or32_letter or32_letters[] #endif /* HAS_EXECUTION */ const struct or32_opcode or32_opcodes[] = - { - { "l.j", "N", "00 0x0 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_j), OR32_IF_DELAY }, - { "l.jal", "N", "00 0x1 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_jal), OR32_IF_DELAY }, - { "l.bnf", "N", "00 0x3 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bnf), OR32_IF_DELAY | OR32_R_FLAG}, - { "l.bf", "N", "00 0x4 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bf), OR32_IF_DELAY | OR32_R_FLAG }, - { "l.nop", "K", "00 0x5 01--- ----- KKKK KKKK KKKK KKKK", EF(l_nop), 0 }, - { "l.movhi", "rD,K", "00 0x6 DDDDD ----0 KKKK KKKK KKKK KKKK", EF(l_movhi), 0 }, /*MM*/ - { "l.macrc", "rD", "00 0x6 DDDDD ----1 0000 0000 0000 0000", EF(l_macrc), 0 }, /*MM*/ - - { "l.sys", "K", "00 0x8 00000 00000 KKKK KKKK KKKK KKKK", EF(l_sys), 0 }, - { "l.trap", "K", "00 0x8 01000 00000 KKKK KKKK KKKK KKKK", EF(l_trap), 0 }, /* CZ 21/06/01 */ - { "l.msync", "", "00 0x8 10000 00000 0000 0000 0000 0000", EFN, 0 }, - { "l.psync", "", "00 0x8 10100 00000 0000 0000 0000 0000", EFN, 0 }, - { "l.csync", "", "00 0x8 11000 00000 0000 0000 0000 0000", EFN, 0 }, - { "l.rfe", "", "00 0x9 ----- ----- ---- ---- ---- ----", EF(l_rfe), OR32_IF_DELAY }, - - { "lv.all_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, - { "lv.all_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, - { "lv.all_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 }, - { "lv.all_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 }, - { "lv.all_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 }, - { "lv.all_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 }, - { "lv.all_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 }, - { "lv.all_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 }, - { "lv.all_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x8", EFI, 0 }, - { "lv.all_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x9", EFI, 0 }, - { "lv.all_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xA", EFI, 0 }, - { "lv.all_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xB", EFI, 0 }, - { "lv.any_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x0", EFI, 0 }, - { "lv.any_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x1", EFI, 0 }, - { "lv.any_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x2", EFI, 0 }, - { "lv.any_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x3", EFI, 0 }, - { "lv.any_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x4", EFI, 0 }, - { "lv.any_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x5", EFI, 0 }, - { "lv.any_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x6", EFI, 0 }, - { "lv.any_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x7", EFI, 0 }, - { "lv.any_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x8", EFI, 0 }, - { "lv.any_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x9", EFI, 0 }, - { "lv.any_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xA", EFI, 0 }, - { "lv.any_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xB", EFI, 0 }, - { "lv.add.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x0", EFI, 0 }, - { "lv.add.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x1", EFI, 0 }, - { "lv.adds.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x2", EFI, 0 }, - { "lv.adds.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x3", EFI, 0 }, - { "lv.addu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x4", EFI, 0 }, - { "lv.addu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x5", EFI, 0 }, - { "lv.addus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x6", EFI, 0 }, - { "lv.addus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x7", EFI, 0 }, - { "lv.and", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x8", EFI, 0 }, - { "lv.avg.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x9", EFI, 0 }, - { "lv.avg.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0xA", EFI, 0 }, - { "lv.cmp_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x0", EFI, 0 }, - { "lv.cmp_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x1", EFI, 0 }, - { "lv.cmp_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x2", EFI, 0 }, - { "lv.cmp_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x3", EFI, 0 }, - { "lv.cmp_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x4", EFI, 0 }, - { "lv.cmp_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x5", EFI, 0 }, - { "lv.cmp_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x6", EFI, 0 }, - { "lv.cmp_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x7", EFI, 0 }, - { "lv.cmp_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x8", EFI, 0 }, - { "lv.cmp_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x9", EFI, 0 }, - { "lv.cmp_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xA", EFI, 0 }, - { "lv.cmp_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xB", EFI, 0 }, - { "lv.madds.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x4", EFI, 0 }, - { "lv.max.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x5", EFI, 0 }, - { "lv.max.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x6", EFI, 0 }, - { "lv.merge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x7", EFI, 0 }, - { "lv.merge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x8", EFI, 0 }, - { "lv.min.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x9", EFI, 0 }, - { "lv.min.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xA", EFI, 0 }, - { "lv.msubs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xB", EFI, 0 }, - { "lv.muls.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xC", EFI, 0 }, - { "lv.nand", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xD", EFI, 0 }, - { "lv.nor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xE", EFI, 0 }, - { "lv.or", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xF", EFI, 0 }, - { "lv.pack.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x0", EFI, 0 }, - { "lv.pack.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x1", EFI, 0 }, - { "lv.packs.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x2", EFI, 0 }, - { "lv.packs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x3", EFI, 0 }, - { "lv.packus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x4", EFI, 0 }, - { "lv.packus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x5", EFI, 0 }, - { "lv.perm.n", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x6", EFI, 0 }, - { "lv.rl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x7", EFI, 0 }, - { "lv.rl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x8", EFI, 0 }, - { "lv.sll.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x9", EFI, 0 }, - { "lv.sll.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xA", EFI, 0 }, - { "lv.sll", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xB", EFI, 0 }, - { "lv.srl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xC", EFI, 0 }, - { "lv.srl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xD", EFI, 0 }, - { "lv.sra.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xE", EFI, 0 }, - { "lv.sra.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xF", EFI, 0 }, - { "lv.srl", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x0", EFI, 0 }, - { "lv.sub.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x1", EFI, 0 }, - { "lv.sub.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x2", EFI, 0 }, - { "lv.subs.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x3", EFI, 0 }, - { "lv.subs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x4", EFI, 0 }, - { "lv.subu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x5", EFI, 0 }, - { "lv.subu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x6", EFI, 0 }, - { "lv.subus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x7", EFI, 0 }, - { "lv.subus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x8", EFI, 0 }, - { "lv.unpack.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x9", EFI, 0 }, - { "lv.unpack.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xA", EFI, 0 }, - { "lv.xor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xB", EFI, 0 }, - { "lv.cust1", "", "00 0xA ----- ----- ---- ---- 0xC ----", EFI, 0 }, - { "lv.cust2", "", "00 0xA ----- ----- ---- ---- 0xD ----", EFI, 0 }, - { "lv.cust3", "", "00 0xA ----- ----- ---- ---- 0xE ----", EFI, 0 }, - { "lv.cust4", "", "00 0xA ----- ----- ---- ---- 0xF ----", EFI, 0 }, - - { "lf.add.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, - { "lf.sub.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, - { "lf.mul.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 }, - { "lf.div.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 }, - { "lf.itof.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 }, - { "lf.ftoi.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 }, - { "lf.rem.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 }, - { "lf.madd.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 }, - { "lf.sfeq.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 }, - { "lf.sfne.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 }, - { "lf.sfgt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 }, - { "lf.sfge.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 }, - { "lf.sflt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 }, - { "lf.sfle.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 }, - { "lf.cust1.s", "", "00 0xB ----- ----- ---- ---- 0xE ----", EFI, 0 }, - - { "lf.add.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, - { "lf.sub.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, - { "lf.mul.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 }, - { "lf.div.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 }, - { "lf.itof.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 }, - { "lf.ftoi.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 }, - { "lf.rem.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 }, - { "lf.madd.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 }, - { "lf.sfeq.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 }, - { "lf.sfne.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 }, - { "lf.sfgt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 }, - { "lf.sfge.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 }, - { "lf.sflt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 }, - { "lf.sfle.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 }, - { "lf.cust1.d", "", "00 0xC ----- ----- ---- ---- 0xE ----", EFI, 0 }, - - { "lvf.ld", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x0", EFI, 0 }, - { "lvf.lw", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x1", EFI, 0 }, - { "lvf.sd", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, - { "lvf.sw", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, - - { "l.jr", "rB", "01 0x1 ----- ----- BBBB B--- ---- ----", EF(l_jr), OR32_IF_DELAY }, - { "l.jalr", "rB", "01 0x2 ----- ----- BBBB B--- ---- ----", EF(l_jalr), OR32_IF_DELAY }, - { "l.maci", "rB,I", "01 0x3 IIIII ----- BBBB BIII IIII IIII", EF(l_mac), 0 }, - { "l.cust1", "", "01 0xC ----- ----- ---- ---- ---- ----", EF(l_cust1), 0 }, - { "l.cust2", "", "01 0xD ----- ----- ---- ---- ---- ----", EF(l_cust2), 0 }, - { "l.cust3", "", "01 0xE ----- ----- ---- ---- ---- ----", EF(l_cust3), 0 }, - { "l.cust4", "", "01 0xF ----- ----- ---- ---- ---- ----", EF(l_cust4), 0 }, - - { "l.ld", "rD,I(rA)", "10 0x0 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, - { "l.lwz", "rD,I(rA)", "10 0x1 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lwz), 0 }, - { "l.lws", "rD,I(rA)", "10 0x2 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, - { "l.lbz", "rD,I(rA)", "10 0x3 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbz), 0 }, - { "l.lbs", "rD,I(rA)", "10 0x4 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbs), 0 }, - { "l.lhz", "rD,I(rA)", "10 0x5 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhz), 0 }, - { "l.lhs", "rD,I(rA)", "10 0x6 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhs), 0 }, - - { "l.addi", "rD,rA,I", "10 0x7 DDDDD AAAAA IIII IIII IIII IIII", EF(l_add), 0 }, - { "l.addic", "rD,rA,I", "10 0x8 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, - { "l.andi", "rD,rA,K", "10 0x9 DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_and), 0 }, - { "l.ori", "rD,rA,K", "10 0xA DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_or), 0 }, - { "l.xori", "rD,rA,I", "10 0xB DDDDD AAAAA IIII IIII IIII IIII", EF(l_xor), 0 }, - { "l.muli", "rD,rA,I", "10 0xC DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, - { "l.mfspr", "rD,rA,K", "10 0xD DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_mfspr), 0 }, - { "l.slli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 00LL LLLL", EF(l_sll), 0 }, - { "l.srli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 01LL LLLL", EF(l_srl), 0 }, - { "l.srai", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 10LL LLLL", EF(l_sra), 0 }, - { "l.rori", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 11LL LLLL", EFI, 0 }, - - { "l.sfeqi", "rA,I", "10 0xF 00000 AAAAA IIII IIII IIII IIII", EF(l_sfeq), OR32_W_FLAG }, - { "l.sfnei", "rA,I", "10 0xF 00001 AAAAA IIII IIII IIII IIII", EF(l_sfne), OR32_W_FLAG }, - { "l.sfgtui", "rA,I", "10 0xF 00010 AAAAA IIII IIII IIII IIII", EF(l_sfgtu), OR32_W_FLAG }, - { "l.sfgeui", "rA,I", "10 0xF 00011 AAAAA IIII IIII IIII IIII", EF(l_sfgeu), OR32_W_FLAG }, - { "l.sfltui", "rA,I", "10 0xF 00100 AAAAA IIII IIII IIII IIII", EF(l_sfltu), OR32_W_FLAG }, - { "l.sfleui", "rA,I", "10 0xF 00101 AAAAA IIII IIII IIII IIII", EF(l_sfleu), OR32_W_FLAG }, - { "l.sfgtsi", "rA,I", "10 0xF 01010 AAAAA IIII IIII IIII IIII", EF(l_sfgts), OR32_W_FLAG }, - { "l.sfgesi", "rA,I", "10 0xF 01011 AAAAA IIII IIII IIII IIII", EF(l_sfges), OR32_W_FLAG }, - { "l.sfltsi", "rA,I", "10 0xF 01100 AAAAA IIII IIII IIII IIII", EF(l_sflts), OR32_W_FLAG }, - { "l.sflesi", "rA,I", "10 0xF 01101 AAAAA IIII IIII IIII IIII", EF(l_sfles), OR32_W_FLAG }, - - { "l.mtspr", "rA,rB,K", "11 0x0 KKKKK AAAAA BBBB BKKK KKKK KKKK", EF(l_mtspr), 0 }, - { "l.mac", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x1", EF(l_mac), 0 }, /*MM*/ - { "l.msb", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x2", EF(l_msb), 0 }, /*MM*/ - - { "l.sd", "I(rA),rB", "11 0x4 IIIII AAAAA BBBB BIII IIII IIII", EFI, 0 }, - { "l.sw", "I(rA),rB", "11 0x5 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sw), 0 }, - { "l.sb", "I(rA),rB", "11 0x6 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sb), 0 }, - { "l.sh", "I(rA),rB", "11 0x7 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sh), 0 }, +{ + { "l.j", "N", "00 0x0 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_j), OR32_IF_DELAY }, + { "l.jal", "N", "00 0x1 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_jal), OR32_IF_DELAY }, + { "l.bnf", "N", "00 0x3 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bnf), OR32_IF_DELAY | OR32_R_FLAG}, + { "l.bf", "N", "00 0x4 NNNNN NNNNN NNNN NNNN NNNN NNNN", EF(l_bf), OR32_IF_DELAY | OR32_R_FLAG }, + { "l.nop", "K", "00 0x5 01--- ----- KKKK KKKK KKKK KKKK", EF(l_nop), 0 }, + { "l.movhi", "rD,K", "00 0x6 DDDDD ----0 KKKK KKKK KKKK KKKK", EF(l_movhi), 0 }, /*MM*/ + { "l.macrc", "rD", "00 0x6 DDDDD ----1 0000 0000 0000 0000", EF(l_macrc), 0 }, /*MM*/ + + { "l.sys", "K", "00 0x8 00000 00000 KKKK KKKK KKKK KKKK", EF(l_sys), 0 }, + { "l.trap", "K", "00 0x8 01000 00000 KKKK KKKK KKKK KKKK", EF(l_trap), 0 }, /* CZ 21/06/01 */ + { "l.msync", "", "00 0x8 10000 00000 0000 0000 0000 0000", EFN, 0 }, + { "l.psync", "", "00 0x8 10100 00000 0000 0000 0000 0000", EFN, 0 }, + { "l.csync", "", "00 0x8 11000 00000 0000 0000 0000 0000", EFN, 0 }, + { "l.rfe", "", "00 0x9 ----- ----- ---- ---- ---- ----", EF(l_rfe), OR32_IF_DELAY }, + + { "lv.all_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, + { "lv.all_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, + { "lv.all_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 }, + { "lv.all_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 }, + { "lv.all_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 }, + { "lv.all_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 }, + { "lv.all_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 }, + { "lv.all_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 }, + { "lv.all_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x8", EFI, 0 }, + { "lv.all_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x9", EFI, 0 }, + { "lv.all_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xA", EFI, 0 }, + { "lv.all_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xB", EFI, 0 }, + { "lv.any_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x0", EFI, 0 }, + { "lv.any_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x1", EFI, 0 }, + { "lv.any_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x2", EFI, 0 }, + { "lv.any_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x3", EFI, 0 }, + { "lv.any_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x4", EFI, 0 }, + { "lv.any_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x5", EFI, 0 }, + { "lv.any_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x6", EFI, 0 }, + { "lv.any_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x7", EFI, 0 }, + { "lv.any_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x8", EFI, 0 }, + { "lv.any_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x9", EFI, 0 }, + { "lv.any_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xA", EFI, 0 }, + { "lv.any_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xB", EFI, 0 }, + { "lv.add.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x0", EFI, 0 }, + { "lv.add.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x1", EFI, 0 }, + { "lv.adds.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x2", EFI, 0 }, + { "lv.adds.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x3", EFI, 0 }, + { "lv.addu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x4", EFI, 0 }, + { "lv.addu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x5", EFI, 0 }, + { "lv.addus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x6", EFI, 0 }, + { "lv.addus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x7", EFI, 0 }, + { "lv.and", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x8", EFI, 0 }, + { "lv.avg.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x9", EFI, 0 }, + { "lv.avg.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0xA", EFI, 0 }, + { "lv.cmp_eq.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x0", EFI, 0 }, + { "lv.cmp_eq.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x1", EFI, 0 }, + { "lv.cmp_ge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x2", EFI, 0 }, + { "lv.cmp_ge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x3", EFI, 0 }, + { "lv.cmp_gt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x4", EFI, 0 }, + { "lv.cmp_gt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x5", EFI, 0 }, + { "lv.cmp_le.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x6", EFI, 0 }, + { "lv.cmp_le.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x7", EFI, 0 }, + { "lv.cmp_lt.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x8", EFI, 0 }, + { "lv.cmp_lt.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x9", EFI, 0 }, + { "lv.cmp_ne.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xA", EFI, 0 }, + { "lv.cmp_ne.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xB", EFI, 0 }, + { "lv.madds.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x4", EFI, 0 }, + { "lv.max.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x5", EFI, 0 }, + { "lv.max.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x6", EFI, 0 }, + { "lv.merge.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x7", EFI, 0 }, + { "lv.merge.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x8", EFI, 0 }, + { "lv.min.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x9", EFI, 0 }, + { "lv.min.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xA", EFI, 0 }, + { "lv.msubs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xB", EFI, 0 }, + { "lv.muls.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xC", EFI, 0 }, + { "lv.nand", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xD", EFI, 0 }, + { "lv.nor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xE", EFI, 0 }, + { "lv.or", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xF", EFI, 0 }, + { "lv.pack.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x0", EFI, 0 }, + { "lv.pack.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x1", EFI, 0 }, + { "lv.packs.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x2", EFI, 0 }, + { "lv.packs.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x3", EFI, 0 }, + { "lv.packus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x4", EFI, 0 }, + { "lv.packus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x5", EFI, 0 }, + { "lv.perm.n", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x6", EFI, 0 }, + { "lv.rl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x7", EFI, 0 }, + { "lv.rl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x8", EFI, 0 }, + { "lv.sll.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x9", EFI, 0 }, + { "lv.sll.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xA", EFI, 0 }, + { "lv.sll", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xB", EFI, 0 }, + { "lv.srl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xC", EFI, 0 }, + { "lv.srl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xD", EFI, 0 }, + { "lv.sra.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xE", EFI, 0 }, + { "lv.sra.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xF", EFI, 0 }, + { "lv.srl", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x0", EFI, 0 }, + { "lv.sub.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x1", EFI, 0 }, + { "lv.sub.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x2", EFI, 0 }, + { "lv.subs.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x3", EFI, 0 }, + { "lv.subs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x4", EFI, 0 }, + { "lv.subu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x5", EFI, 0 }, + { "lv.subu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x6", EFI, 0 }, + { "lv.subus.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x7", EFI, 0 }, + { "lv.subus.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x8", EFI, 0 }, + { "lv.unpack.b","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x9", EFI, 0 }, + { "lv.unpack.h","rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xA", EFI, 0 }, + { "lv.xor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xB", EFI, 0 }, + { "lv.cust1", "", "00 0xA ----- ----- ---- ---- 0xC ----", EFI, 0 }, + { "lv.cust2", "", "00 0xA ----- ----- ---- ---- 0xD ----", EFI, 0 }, + { "lv.cust3", "", "00 0xA ----- ----- ---- ---- 0xE ----", EFI, 0 }, + { "lv.cust4", "", "00 0xA ----- ----- ---- ---- 0xF ----", EFI, 0 }, + + { "lf.add.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, + { "lf.sub.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, + { "lf.mul.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 }, + { "lf.div.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 }, + { "lf.itof.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 }, + { "lf.ftoi.s", "rD,rA", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 }, + { "lf.rem.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 }, + { "lf.madd.s", "rD,rA,rB", "00 0xB DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 }, + { "lf.sfeq.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 }, + { "lf.sfne.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 }, + { "lf.sfgt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 }, + { "lf.sfge.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 }, + { "lf.sflt.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 }, + { "lf.sfle.s", "rA,rB", "00 0xB ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 }, + { "lf.cust1.s", "", "00 0xB ----- ----- ---- ---- 0xE ----", EFI, 0 }, + + { "lf.add.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, + { "lf.sub.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, + { "lf.mul.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0 }, + { "lf.div.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0 }, + { "lf.itof.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0 }, + { "lf.ftoi.d", "rD,rA", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0 }, + { "lf.rem.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0 }, + { "lf.madd.d", "rD,rA,rB", "00 0xC DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0 }, + { "lf.sfeq.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0 }, + { "lf.sfne.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0 }, + { "lf.sfgt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0 }, + { "lf.sfge.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0 }, + { "lf.sflt.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0 }, + { "lf.sfle.d", "rA,rB", "00 0xC ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0 }, + { "lf.cust1.d", "", "00 0xC ----- ----- ---- ---- 0xE ----", EFI, 0 }, + + { "lvf.ld", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x0", EFI, 0 }, + { "lvf.lw", "rD,0(rA)", "00 0xD DDDDD AAAAA ---- ---- 0x0 0x1", EFI, 0 }, + { "lvf.sd", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x0", EFI, 0 }, + { "lvf.sw", "0(rA),rB", "00 0xD ----- AAAAA BBBB B--- 0x1 0x1", EFI, 0 }, + + { "l.jr", "rB", "01 0x1 ----- ----- BBBB B--- ---- ----", EF(l_jr), OR32_IF_DELAY }, + { "l.jalr", "rB", "01 0x2 ----- ----- BBBB B--- ---- ----", EF(l_jalr), OR32_IF_DELAY }, + { "l.maci", "rB,I", "01 0x3 IIIII ----- BBBB BIII IIII IIII", EF(l_mac), 0 }, + { "l.cust1", "", "01 0xC ----- ----- ---- ---- ---- ----", EF(l_cust1), 0 }, + { "l.cust2", "", "01 0xD ----- ----- ---- ---- ---- ----", EF(l_cust2), 0 }, + { "l.cust3", "", "01 0xE ----- ----- ---- ---- ---- ----", EF(l_cust3), 0 }, + { "l.cust4", "", "01 0xF ----- ----- ---- ---- ---- ----", EF(l_cust4), 0 }, + + { "l.ld", "rD,I(rA)", "10 0x0 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, + { "l.lwz", "rD,I(rA)", "10 0x1 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lwz), 0 }, + { "l.lws", "rD,I(rA)", "10 0x2 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, + { "l.lbz", "rD,I(rA)", "10 0x3 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbz), 0 }, + { "l.lbs", "rD,I(rA)", "10 0x4 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lbs), 0 }, + { "l.lhz", "rD,I(rA)", "10 0x5 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhz), 0 }, + { "l.lhs", "rD,I(rA)", "10 0x6 DDDDD AAAAA IIII IIII IIII IIII", EF(l_lhs), 0 }, + + { "l.addi", "rD,rA,I", "10 0x7 DDDDD AAAAA IIII IIII IIII IIII", EF(l_add), 0 }, + { "l.addic", "rD,rA,I", "10 0x8 DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, + { "l.andi", "rD,rA,K", "10 0x9 DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_and), 0 }, + { "l.ori", "rD,rA,K", "10 0xA DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_or), 0 }, + { "l.xori", "rD,rA,I", "10 0xB DDDDD AAAAA IIII IIII IIII IIII", EF(l_xor), 0 }, + { "l.muli", "rD,rA,I", "10 0xC DDDDD AAAAA IIII IIII IIII IIII", EFI, 0 }, + { "l.mfspr", "rD,rA,K", "10 0xD DDDDD AAAAA KKKK KKKK KKKK KKKK", EF(l_mfspr), 0 }, + { "l.slli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 00LL LLLL", EF(l_sll), 0 }, + { "l.srli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 01LL LLLL", EF(l_srl), 0 }, + { "l.srai", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 10LL LLLL", EF(l_sra), 0 }, + { "l.rori", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 11LL LLLL", EFI, 0 }, + + { "l.sfeqi", "rA,I", "10 0xF 00000 AAAAA IIII IIII IIII IIII", EF(l_sfeq), OR32_W_FLAG }, + { "l.sfnei", "rA,I", "10 0xF 00001 AAAAA IIII IIII IIII IIII", EF(l_sfne), OR32_W_FLAG }, + { "l.sfgtui", "rA,I", "10 0xF 00010 AAAAA IIII IIII IIII IIII", EF(l_sfgtu), OR32_W_FLAG }, + { "l.sfgeui", "rA,I", "10 0xF 00011 AAAAA IIII IIII IIII IIII", EF(l_sfgeu), OR32_W_FLAG }, + { "l.sfltui", "rA,I", "10 0xF 00100 AAAAA IIII IIII IIII IIII", EF(l_sfltu), OR32_W_FLAG }, + { "l.sfleui", "rA,I", "10 0xF 00101 AAAAA IIII IIII IIII IIII", EF(l_sfleu), OR32_W_FLAG }, + { "l.sfgtsi", "rA,I", "10 0xF 01010 AAAAA IIII IIII IIII IIII", EF(l_sfgts), OR32_W_FLAG }, + { "l.sfgesi", "rA,I", "10 0xF 01011 AAAAA IIII IIII IIII IIII", EF(l_sfges), OR32_W_FLAG }, + { "l.sfltsi", "rA,I", "10 0xF 01100 AAAAA IIII IIII IIII IIII", EF(l_sflts), OR32_W_FLAG }, + { "l.sflesi", "rA,I", "10 0xF 01101 AAAAA IIII IIII IIII IIII", EF(l_sfles), OR32_W_FLAG }, + + { "l.mtspr", "rA,rB,K", "11 0x0 KKKKK AAAAA BBBB BKKK KKKK KKKK", EF(l_mtspr), 0 }, + { "l.mac", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x1", EF(l_mac), 0 }, /*MM*/ + { "l.msb", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x2", EF(l_msb), 0 }, /*MM*/ + + { "l.sd", "I(rA),rB", "11 0x4 IIIII AAAAA BBBB BIII IIII IIII", EFI, 0 }, + { "l.sw", "I(rA),rB", "11 0x5 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sw), 0 }, + { "l.sb", "I(rA),rB", "11 0x6 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sb), 0 }, + { "l.sh", "I(rA),rB", "11 0x7 IIIII AAAAA BBBB BIII IIII IIII", EF(l_sh), 0 }, - { "l.add", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x0", EF(l_add), 0 }, - { "l.addc", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x1", EFI, 0 }, - { "l.sub", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x2", EF(l_sub), 0 }, - { "l.and", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x3", EF(l_and), 0 }, - { "l.or", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x4", EF(l_or), 0 }, - { "l.xor", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x5", EF(l_xor), 0 }, - { "l.mul", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x6", EF(l_mul), 0 }, - - { "l.sll", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0x8", EF(l_sll), 0 }, - { "l.srl", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0x8", EF(l_srl), 0 }, - { "l.sra", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0x8", EF(l_sra), 0 }, - { "l.ror", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0x8", EFI, 0 }, - { "l.div", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x9", EF(l_div), 0 }, - { "l.divu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xA", EF(l_divu), 0 }, - { "l.mulu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xB", EFI, 0 }, - { "l.exths", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xC", EFI, 0 }, - { "l.extbs", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xC", EFI, 0 }, - { "l.exthz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0xC", EFI, 0 }, - { "l.extbz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0xC", EFI, 0 }, - { "l.extws", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xD", EFI, 0 }, - { "l.extwz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xD", EFI, 0 }, - { "l.cmov", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xE", EFI, 0 }, - { "l.ff1", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xF", EFI, 0 }, - - { "l.sfeq", "rA,rB", "11 0x9 00000 AAAAA BBBB B--- ---- ----", EF(l_sfeq), OR32_W_FLAG }, - { "l.sfne", "rA,rB", "11 0x9 00001 AAAAA BBBB B--- ---- ----", EF(l_sfne), OR32_W_FLAG }, - { "l.sfgtu", "rA,rB", "11 0x9 00010 AAAAA BBBB B--- ---- ----", EF(l_sfgtu), OR32_W_FLAG }, - { "l.sfgeu", "rA,rB", "11 0x9 00011 AAAAA BBBB B--- ---- ----", EF(l_sfgeu), OR32_W_FLAG }, - { "l.sfltu", "rA,rB", "11 0x9 00100 AAAAA BBBB B--- ---- ----", EF(l_sfltu), OR32_W_FLAG }, - { "l.sfleu", "rA,rB", "11 0x9 00101 AAAAA BBBB B--- ---- ----", EF(l_sfleu), OR32_W_FLAG }, - { "l.sfgts", "rA,rB", "11 0x9 01010 AAAAA BBBB B--- ---- ----", EF(l_sfgts), OR32_W_FLAG }, - { "l.sfges", "rA,rB", "11 0x9 01011 AAAAA BBBB B--- ---- ----", EF(l_sfges), OR32_W_FLAG }, - { "l.sflts", "rA,rB", "11 0x9 01100 AAAAA BBBB B--- ---- ----", EF(l_sflts), OR32_W_FLAG }, - { "l.sfles", "rA,rB", "11 0x9 01101 AAAAA BBBB B--- ---- ----", EF(l_sfles), OR32_W_FLAG }, - - { "l.cust5", "", "11 0xC ----- ----- ---- ---- ---- ----", EFI, 0 }, - { "l.cust6", "", "11 0xD ----- ----- ---- ---- ---- ----", EFI, 0 }, - { "l.cust7", "", "11 0xE ----- ----- ---- ---- ---- ----", EFI, 0 }, - { "l.cust8", "", "11 0xF ----- ----- ---- ---- ---- ----", EFI, 0 }, + { "l.add", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x0", EF(l_add), 0 }, + { "l.addc", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x1", EFI, 0 }, + { "l.sub", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x2", EF(l_sub), 0 }, + { "l.and", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x3", EF(l_and), 0 }, + { "l.or", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x4", EF(l_or), 0 }, + { "l.xor", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x5", EF(l_xor), 0 }, + { "l.mul", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x6", EF(l_mul), 0 }, + + { "l.sll", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0x8", EF(l_sll), 0 }, + { "l.srl", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0x8", EF(l_srl), 0 }, + { "l.sra", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0x8", EF(l_sra), 0 }, + { "l.ror", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0x8", EFI, 0 }, + { "l.div", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x9", EF(l_div), 0 }, + { "l.divu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xA", EF(l_divu), 0 }, + { "l.mulu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xB", EFI, 0 }, + { "l.exths", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xC", EFI, 0 }, + { "l.extbs", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xC", EFI, 0 }, + { "l.exthz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0xC", EFI, 0 }, + { "l.extbz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0xC", EFI, 0 }, + { "l.extws", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0xD", EFI, 0 }, + { "l.extwz", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0xD", EFI, 0 }, + { "l.cmov", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xE", EFI, 0 }, + { "l.ff1", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xF", EFI, 0 }, + + { "l.sfeq", "rA,rB", "11 0x9 00000 AAAAA BBBB B--- ---- ----", EF(l_sfeq), OR32_W_FLAG }, + { "l.sfne", "rA,rB", "11 0x9 00001 AAAAA BBBB B--- ---- ----", EF(l_sfne), OR32_W_FLAG }, + { "l.sfgtu", "rA,rB", "11 0x9 00010 AAAAA BBBB B--- ---- ----", EF(l_sfgtu), OR32_W_FLAG }, + { "l.sfgeu", "rA,rB", "11 0x9 00011 AAAAA BBBB B--- ---- ----", EF(l_sfgeu), OR32_W_FLAG }, + { "l.sfltu", "rA,rB", "11 0x9 00100 AAAAA BBBB B--- ---- ----", EF(l_sfltu), OR32_W_FLAG }, + { "l.sfleu", "rA,rB", "11 0x9 00101 AAAAA BBBB B--- ---- ----", EF(l_sfleu), OR32_W_FLAG }, + { "l.sfgts", "rA,rB", "11 0x9 01010 AAAAA BBBB B--- ---- ----", EF(l_sfgts), OR32_W_FLAG }, + { "l.sfges", "rA,rB", "11 0x9 01011 AAAAA BBBB B--- ---- ----", EF(l_sfges), OR32_W_FLAG }, + { "l.sflts", "rA,rB", "11 0x9 01100 AAAAA BBBB B--- ---- ----", EF(l_sflts), OR32_W_FLAG }, + { "l.sfles", "rA,rB", "11 0x9 01101 AAAAA BBBB B--- ---- ----", EF(l_sfles), OR32_W_FLAG }, + + { "l.cust5", "", "11 0xC ----- ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust6", "", "11 0xD ----- ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust7", "", "11 0xE ----- ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust8", "", "11 0xF ----- ----- ---- ---- ---- ----", EFI, 0 }, - /* This section should not be defined in or1ksim, since it contains duplicates, - which would cause machine builder to complain. */ + /* This section should not be defined in or1ksim, since it contains duplicates, + which would cause machine builder to complain. */ #ifdef HAS_CUST - { "l.cust5_1", "rD", "11 0xC DDDDD ----- ---- ---- ---- ----", EFI, 0 }, - { "l.cust5_2", "rD,rA" , "11 0xC DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, - { "l.cust5_3", "rD,rA,rB", "11 0xC DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, - - { "l.cust6_1", "rD", "11 0xD DDDDD ----- ---- ---- ---- ----", EFI, 0 }, - { "l.cust6_2", "rD,rA" , "11 0xD DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, - { "l.cust6_3", "rD,rA,rB", "11 0xD DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, - - { "l.cust7_1", "rD", "11 0xE DDDDD ----- ---- ---- ---- ----", EFI, 0 }, - { "l.cust7_2", "rD,rA" , "11 0xE DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, - { "l.cust7_3", "rD,rA,rB", "11 0xE DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, - - { "l.cust8_1", "rD", "11 0xF DDDDD ----- ---- ---- ---- ----", EFI, 0 }, - { "l.cust8_2", "rD,rA" , "11 0xF DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, - { "l.cust8_3", "rD,rA,rB", "11 0xF DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, + { "l.cust5_1", "rD", "11 0xC DDDDD ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust5_2", "rD,rA" , "11 0xC DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, + { "l.cust5_3", "rD,rA,rB", "11 0xC DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, + + { "l.cust6_1", "rD", "11 0xD DDDDD ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust6_2", "rD,rA" , "11 0xD DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, + { "l.cust6_3", "rD,rA,rB", "11 0xD DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, + + { "l.cust7_1", "rD", "11 0xE DDDDD ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust7_2", "rD,rA" , "11 0xE DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, + { "l.cust7_3", "rD,rA,rB", "11 0xE DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, + + { "l.cust8_1", "rD", "11 0xF DDDDD ----- ---- ---- ---- ----", EFI, 0 }, + { "l.cust8_2", "rD,rA" , "11 0xF DDDDD AAAAA ---- ---- ---- ----", EFI, 0 }, + { "l.cust8_3", "rD,rA,rB", "11 0xF DDDDD AAAAA BBBB B--- ---- ----", EFI, 0 }, #endif - /* Dummy entry, not included in num_opcodes. This - lets code examine entry i+1 without checking - if we've run off the end of the table. */ - { "", "", "", EFI, 0 } + /* Dummy entry, not included in num_opcodes. This + lets code examine entry i+1 without checking + if we've run off the end of the table. */ + { "", "", "", EFI, 0 } }; #undef EFI @@ -342,9 +334,7 @@ const struct or32_opcode or32_opcodes[] /* Define dummy, if debug is not defined. */ #if !defined HAS_DEBUG -static void debug PARAMS ((int, const char *, ...)); - -static void +static void ATTRIBUTE_PRINTF_2 debug (int level ATTRIBUTE_UNUSED, const char *format ATTRIBUTE_UNUSED, ...) { } @@ -355,8 +345,7 @@ const unsigned int or32_num_opcodes = (( /* Calculates instruction length in bytes. Always 4 for OR32. */ int -insn_len (insn_index) - int insn_index ATTRIBUTE_UNUSED; +insn_len (int insn_index ATTRIBUTE_UNUSED) { return 4; } @@ -364,8 +353,7 @@ insn_len (insn_index) /* Is individual insn's operand signed or unsigned? */ int -letter_signed (l) - char l; +letter_signed (char l) { const struct or32_letter *pletter; @@ -380,19 +368,18 @@ letter_signed (l) /* Number of letters in the individual lettered operand. */ int -letter_range (l) - char l; +letter_range (char l) { const struct or32_opcode *pinsn; char *enc; int range = 0; - for (pinsn = or32_opcodes; strlen(pinsn->name); pinsn++) + for (pinsn = or32_opcodes; strlen (pinsn->name); pinsn ++) { if (strchr (pinsn->encoding,l)) { - for (enc = pinsn->encoding; *enc != '\0'; enc++) - if ((*enc == '0') && (*(enc+1) == 'x')) + for (enc = pinsn->encoding; *enc != '\0'; enc ++) + if ((*enc == '0') && (*(enc + 1) == 'x')) enc += 2; else if (*enc == l) range++; @@ -422,8 +409,7 @@ insn_index (char *insn) } const char * -insn_name (index) - int index; +insn_name (int index) { if (index >= 0 && index < (int) or32_num_opcodes) return or32_opcodes[index].name; @@ -432,17 +418,16 @@ insn_name (index) } void -l_none () +l_none (void) { } /* Finite automata for instruction decoding building code. */ /* Find simbols in encoding. */ + static unsigned long -insn_extract (param_ch, enc_initial) - char param_ch; - char *enc_initial; +insn_extract (char param_ch, char *enc_initial) { char *enc; unsigned long ret = 0; @@ -475,13 +460,13 @@ insn_extract (param_ch, enc_initial) return ret; } -#define MAX_AUTOMATA_SIZE (1200) -#define MAX_OP_TABLE_SIZE (1200) -#define LEAF_FLAG (0x80000000) -#define MAX_LEN (8) +#define MAX_AUTOMATA_SIZE 1200 +#define MAX_OP_TABLE_SIZE 1200 +#define LEAF_FLAG 0x80000000 +#define MAX_LEN 8 #ifndef MIN -# define MIN(x,y) ((x) < (y) ? (x) : (y)) +#define MIN(x, y) ((x) < (y) ? (x) : (y)) #endif unsigned long *automata; @@ -501,10 +486,7 @@ struct insn_op_struct *op_data, **op_sta /* Recursive utility function used to find best match and to build automata. */ static unsigned long * -cover_insn (cur, pass, mask) - unsigned long * cur; - int pass; - unsigned int mask; +cover_insn (unsigned long * cur, int pass, unsigned int mask) { int best_first = 0, last_match = -1, ninstr = 0; unsigned int best_len = 0; @@ -520,7 +502,7 @@ cover_insn (cur, pass, mask) last_match = i; } - debug (8, "%08X %08X\n", mask, cur_mask); + debug (8, "%08X %08lX\n", mask, cur_mask); if (ninstr == 0) return 0; @@ -528,8 +510,8 @@ cover_insn (cur, pass, mask) if (ninstr == 1) { /* Leaf holds instruction index. */ - debug (8, "%i>I%i %s\n", - cur - automata, last_match, or32_opcodes[last_match].name); + debug (8, "%li>I%i %s\n", + (long)(cur - automata), last_match, or32_opcodes[last_match].name); *cur = LEAF_FLAG | last_match; cur++; @@ -544,13 +526,13 @@ cover_insn (cur, pass, mask) for (len = best_len + 1; len < MIN (MAX_LEN, 33 - i); len++) { - unsigned long m = (1UL << ((unsigned long)len)) - 1; + unsigned long m = (1UL << ((unsigned long) len)) - 1; - debug (9, " (%i(%08X & %08X>>%i = %08X, %08X)", + debug (9, " (%i(%08lX & %08lX>>%i = %08lX, %08lX)", len,m, cur_mask, i, (cur_mask >> (unsigned)i), - (cur_mask >> (unsigned)i) & m); + (cur_mask >> (unsigned) i) & m); - if ((m & (cur_mask >> (unsigned)i)) == m) + if ((m & (cur_mask >> (unsigned) i)) == m) { best_len = len; best_first = i; @@ -575,8 +557,8 @@ cover_insn (cur, pass, mask) exit (1); } - debug (8, "%i> #### %i << %i (%i) ####\n", - cur - automata, best_len, best_first, ninstr); + debug (8, "%li> #### %i << %i (%i) ####\n", + (long)(cur - automata), best_len, best_first, ninstr); *cur = best_first; cur++; @@ -586,7 +568,7 @@ cover_insn (cur, pass, mask) /* Allocate space for pointers. */ cur += 1 << best_len; - cur_mask = (1 << (unsigned long)best_len) - 1; + cur_mask = (1 << (unsigned long) best_len) - 1; for (i = 0; i < ((unsigned) 1 << best_len); i++) { @@ -600,17 +582,17 @@ cover_insn (cur, pass, mask) && ((ti[j].insn_mask >> best_first) & cur_mask) == cur_mask) ti[j].in_pass = curpass; - debug (9, "%08X %08X %i\n", mask, cur_mask, best_first); + debug (9, "%08X %08lX %i\n", mask, cur_mask, best_first); c = cover_insn (cur, curpass, mask & (~(cur_mask << best_first))); if (c) { - debug (8, "%i> #%X -> %u\n", next - automata, i, cur - automata); + debug (8, "%li> #%X -> %lu\n", (long)(next - automata), i, (long)(cur - automata)); *next = cur - automata; cur = c; } else { - debug (8, "%i> N/A\n", next - automata); + debug (8, "%li> N/A\n", (long)(next - automata)); *next = 0; } next++; @@ -622,8 +604,7 @@ cover_insn (cur, pass, mask) /* Returns number of nonzero bits. */ static int -num_ones (value) - unsigned long value; +num_ones (unsigned long value) { int c = 0; @@ -636,13 +617,12 @@ num_ones (value) return c; } -/* Utility function, which converts parameters from or32_opcode format to more binary form. - Parameters are stored in ti struct. */ +/* Utility function, which converts parameters from or32_opcode + format to more binary form. Parameters are stored in ti struct. */ static struct insn_op_struct * -parse_params (opcode, cur) - const struct or32_opcode * opcode; - struct insn_op_struct * cur; +parse_params (const struct or32_opcode * opcode, + struct insn_op_struct * cur) { char *args = opcode->args; int i, type; @@ -655,7 +635,7 @@ parse_params (opcode, cur) { cur->type = OPTYPE_REG | OPTYPE_OP | OPTYPE_LAST; cur->data = 0; - debug (9, "#%08X %08X\n", cur->type, cur->data); + debug (9, "#%08lX %08lX\n", cur->type, cur->data); cur++; return cur; } @@ -672,7 +652,7 @@ parse_params (opcode, cur) unsigned long arg; arg = insn_extract (*args, opcode->encoding); - debug (9, "%s : %08X ------\n", opcode->name, arg); + debug (9, "%s : %08lX ------\n", opcode->name, arg); if (letter_signed (*args)) { type |= OPTYPE_SIG; @@ -698,17 +678,18 @@ parse_params (opcode, cur) cur->type = type | shr; cur->data = mask; arg &= ~(((1 << mask) - 1) << shr); - debug (6, "|%08X %08X\n", cur->type, cur->data); + debug (6, "|%08lX %08lX\n", cur->type, cur->data); cur++; } args++; } else if (*args == '(') { - /* Next param is displacement. Later we will treat them as one operand. */ + /* Next param is displacement. + Later we will treat them as one operand. */ cur--; cur->type = type | cur->type | OPTYPE_DIS | OPTYPE_OP; - debug (9, ">%08X %08X\n", cur->type, cur->data); + debug (9, ">%08lX %08lX\n", cur->type, cur->data); cur++; type = 0; i++; @@ -718,7 +699,7 @@ parse_params (opcode, cur) { cur--; cur->type = type | cur->type | OPTYPE_OP; - debug (9, ">%08X %08X\n", cur->type, cur->data); + debug (9, ">%08lX %08lX\n", cur->type, cur->data); cur++; type = 0; i++; @@ -728,7 +709,7 @@ parse_params (opcode, cur) { cur->type = type; cur->data = 0; - debug (9, ">%08X %08X\n", cur->type, cur->data); + debug (9, ">%08lX %08lX\n", cur->type, cur->data); cur++; type = 0; i++; @@ -745,7 +726,7 @@ parse_params (opcode, cur) cur--; cur->type = type | cur->type | OPTYPE_OP | OPTYPE_LAST; - debug (9, "#%08X %08X\n", cur->type, cur->data); + debug (9, "#%08lX %08lX\n", cur->type, cur->data); cur++; return cur; @@ -754,14 +735,14 @@ parse_params (opcode, cur) /* Constructs new automata based on or32_opcodes array. */ void -build_automata () +build_automata (void) { unsigned int i; unsigned long *end; struct insn_op_struct *cur; - automata = (unsigned long *) malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long)); - ti = (struct temp_insn_struct *) malloc (sizeof (struct temp_insn_struct) * or32_num_opcodes); + automata = malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long)); + ti = malloc (sizeof (struct temp_insn_struct) * or32_num_opcodes); nuncovered = or32_num_opcodes; printf ("Building automata... "); @@ -794,8 +775,8 @@ build_automata () printf ("done, num uncovered: %i/%i.\n", nuncovered, or32_num_opcodes); printf ("Parsing operands data... "); - op_data = (struct insn_op_struct *) malloc (MAX_OP_TABLE_SIZE * sizeof (struct insn_op_struct)); - op_start = (struct insn_op_struct **) malloc (or32_num_opcodes * sizeof (struct insn_op_struct *)); + op_data = malloc (MAX_OP_TABLE_SIZE * sizeof (struct insn_op_struct)); + op_start = malloc (or32_num_opcodes * sizeof (struct insn_op_struct *)); cur = op_data; for (i = 0; i < or32_num_opcodes; i++) @@ -813,7 +794,7 @@ build_automata () } void -destruct_automata () +destruct_automata (void) { free (ti); free (automata); @@ -824,8 +805,7 @@ destruct_automata () /* Decodes instruction and returns instruction index. */ int -insn_decode (insn) - unsigned int insn; +insn_decode (unsigned int insn) { unsigned long *a = automata; int i; @@ -834,7 +814,7 @@ insn_decode (insn) { unsigned int first = *a; - debug (9, "%i ", a - automata); + debug (9, "%li ", (long)(a - automata)); a++; i = (insn >> first) & *a; @@ -842,7 +822,7 @@ insn_decode (insn) if (!*(a + i)) { /* Invalid instruction found? */ - debug (9, "XXX\n", i); + debug (9, "XXX\n"); return -1; } a = automata + *(a + i); @@ -869,9 +849,7 @@ char *disassembled = &disassembled_str[0 is proper is figured out from letter description. */ static unsigned long -extend_imm (imm, l) - unsigned long imm; - char l; +extend_imm (unsigned long imm, char l) { unsigned long mask; int letter_bits; @@ -890,10 +868,7 @@ extend_imm (imm, l) } static unsigned long -or32_extract (param_ch, enc_initial, insn) - char param_ch; - char *enc_initial; - unsigned long insn; +or32_extract (char param_ch, char *enc_initial, unsigned long insn) { char *enc; unsigned long ret = 0; @@ -972,10 +947,7 @@ or32_extract (param_ch, enc_initial, ins /* Print register. Used only by print_insn. */ static void -or32_print_register (param_ch, encoding, insn) - char param_ch; - char *encoding; - unsigned long insn; +or32_print_register (char param_ch, char *encoding, unsigned long insn) { int regnum = or32_extract(param_ch, encoding, insn); @@ -985,10 +957,7 @@ or32_print_register (param_ch, encoding, /* Print immediate. Used only by print_insn. */ static void -or32_print_immediate (param_ch, encoding, insn) - char param_ch; - char *encoding; - unsigned long insn; +or32_print_immediate (char param_ch, char *encoding, unsigned long insn) { int imm = or32_extract (param_ch, encoding, insn); @@ -1009,8 +978,7 @@ or32_print_immediate (param_ch, encoding Return the size of the instruction. */ int -disassemble_insn (insn) - unsigned long insn; +disassemble_insn (unsigned long insn) { int index; index = insn_decode (insn); diff -uprN binutils-2.16.91.0.1/opcodes/pdp11-dis.c binutils-2.16.91.0.2/opcodes/pdp11-dis.c --- binutils-2.16.91.0.1/opcodes/pdp11-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/pdp11-dis.c 2005-07-20 12:27:29.362851758 -0700 @@ -1,19 +1,20 @@ /* Print DEC PDP-11 instructions. - Copyright 2001, 2002, 2004 Free Software Foundation, Inc. + Copyright 2001, 2002, 2004, 2005 Free Software Foundation, Inc. -This file is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "sysdep.h" #include "dis-asm.h" @@ -22,31 +23,17 @@ Foundation, Inc., 51 Franklin Street - F #define AFTER_INSTRUCTION "\t" #define OPERAND_SEPARATOR ", " -#define JUMP 0x1000 /* flag that this operand is used in a jump */ +#define JUMP 0x1000 /* Flag that this operand is used in a jump. */ #define FPRINTF (*info->fprintf_func) #define F info->stream -/* sign-extend a 16-bit number in an int */ +/* Sign-extend a 16-bit number in an int. */ #define SIGN_BITS (8 * sizeof (int) - 16) #define sign_extend(x) (((x) << SIGN_BITS) >> SIGN_BITS) -static int read_word PARAMS ((bfd_vma memaddr, int *word, - disassemble_info *info)); -static void print_signed_octal PARAMS ((int n, disassemble_info *info)); -static void print_reg PARAMS ((int reg, disassemble_info *info)); -static void print_freg PARAMS ((int freg, disassemble_info *info)); -static int print_operand PARAMS ((bfd_vma *memaddr, int code, - disassemble_info *info)); -static int print_foperand PARAMS ((bfd_vma *memaddr, int code, - disassemble_info *info)); -int print_insn_pdp11 PARAMS ((bfd_vma memaddr, disassemble_info *info)); - static int -read_word (memaddr, word, info) - bfd_vma memaddr; - int *word; - disassemble_info *info; +read_word (bfd_vma memaddr, int *word, disassemble_info *info) { int status; bfd_byte x[2]; @@ -60,9 +47,7 @@ read_word (memaddr, word, info) } static void -print_signed_octal (n, info) - int n; - disassemble_info *info; +print_signed_octal (int n, disassemble_info *info) { if (n < 0) FPRINTF (F, "-%o", -n); @@ -71,11 +56,9 @@ print_signed_octal (n, info) } static void -print_reg (reg, info) - int reg; - disassemble_info *info; +print_reg (int reg, disassemble_info *info) { - /* mask off the addressing mode, if any */ + /* Mask off the addressing mode, if any. */ reg &= 7; switch (reg) @@ -89,18 +72,13 @@ print_reg (reg, info) } static void -print_freg (freg, info) - int freg; - disassemble_info *info; +print_freg (int freg, disassemble_info *info) { FPRINTF (F, "fr%d", freg); } static int -print_operand (memaddr, code, info) - bfd_vma *memaddr; - int code; - disassemble_info *info; +print_operand (bfd_vma *memaddr, int code, disassemble_info *info) { int mode = (code >> 3) & 7; int reg = code & 7; @@ -120,6 +98,7 @@ print_operand (memaddr, code, info) if (reg == 7) { int data; + if (read_word (*memaddr, &data, info) < 0) return -1; FPRINTF (F, "$"); @@ -137,6 +116,7 @@ print_operand (memaddr, code, info) if (reg == 7) { int address; + if (read_word (*memaddr, &address, info) < 0) return -1; FPRINTF (F, "*$%o", address); @@ -167,6 +147,7 @@ print_operand (memaddr, code, info) if (reg == 7) { bfd_vma address = *memaddr + sign_extend (disp); + if (mode == 7) FPRINTF (F, "*"); if (!(code & JUMP)) @@ -189,10 +170,7 @@ print_operand (memaddr, code, info) } static int -print_foperand (memaddr, code, info) - bfd_vma *memaddr; - int code; - disassemble_info *info; +print_foperand (bfd_vma *memaddr, int code, disassemble_info *info) { int mode = (code >> 3) & 7; int reg = code & 7; @@ -209,9 +187,7 @@ print_foperand (memaddr, code, info) on INFO->STREAM. Returns length of the instruction, in bytes. */ int -print_insn_pdp11 (memaddr, info) - bfd_vma memaddr; - disassemble_info *info; +print_insn_pdp11 (bfd_vma memaddr, disassemble_info *info) { bfd_vma start_memaddr = memaddr; int opcode; diff -uprN binutils-2.16.91.0.1/opcodes/pj-dis.c binutils-2.16.91.0.2/opcodes/pj-dis.c --- binutils-2.16.91.0.1/opcodes/pj-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/pj-dis.c 2005-07-20 12:27:29.363851593 -0700 @@ -1,20 +1,21 @@ /* pj-dis.c -- Disassemble picoJava instructions. - Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + Copyright 1999, 2000, 2001, 2002, 2005 Free Software Foundation, Inc. Contributed by Steve Chamberlain, of Transmeta (sac@pobox.com). -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include #include "sysdep.h" @@ -23,17 +24,10 @@ Foundation, Inc., 51 Franklin Street - F extern const pj_opc_info_t pj_opc_info[512]; -static int get_int PARAMS ((bfd_vma, int *, struct disassemble_info *)); - - static int -get_int (memaddr, iptr, info) - bfd_vma memaddr; - int *iptr; - struct disassemble_info *info; +get_int (bfd_vma memaddr, int *iptr, struct disassemble_info *info) { unsigned char ival[4]; - int status = info->read_memory_func (memaddr, ival, 4, info); *iptr = (ival[0] << 24) @@ -45,9 +39,7 @@ get_int (memaddr, iptr, info) } int -print_insn_pj (addr, info) - bfd_vma addr; - struct disassemble_info *info; +print_insn_pj (bfd_vma addr, struct disassemble_info *info) { fprintf_ftype fprintf_fn = info->fprintf_func; void *stream = info->stream; @@ -60,6 +52,7 @@ print_insn_pj (addr, info) if (opcode == 0xff) { unsigned char byte_2; + if ((status = info->read_memory_func (addr + 1, &byte_2, 1, info))) goto fail; fprintf_fn (stream, "%s\t", pj_opc_info[opcode + byte_2].u.name); @@ -71,6 +64,7 @@ print_insn_pj (addr, info) int insn_start = addr; const pj_opc_info_t *op = &pj_opc_info[opcode]; int a; + addr++; fprintf_fn (stream, "%s", op->u.name); @@ -115,7 +109,6 @@ print_insn_pj (addr, info) /* The lookupswitch instruction is followed by the default address, element count and pairs of values and addresses. */ - if (strcmp (op->u.name, "lookupswitch") == 0) { int count; @@ -149,6 +142,7 @@ print_insn_pj (addr, info) } return addr - insn_start; } + for (a = 0; op->arg[a]; a++) { unsigned char data[4]; diff -uprN binutils-2.16.91.0.1/opcodes/po/opcodes.pot binutils-2.16.91.0.2/opcodes/po/opcodes.pot --- binutils-2.16.91.0.1/opcodes/po/opcodes.pot 2005-04-09 12:03:36.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/po/opcodes.pot 2005-07-20 12:27:29.434839888 -0700 @@ -7,7 +7,8 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" -"POT-Creation-Date: 2005-03-18 16:21+0000\n" +"Report-Msgid-Bugs-To: \n" +"POT-Creation-Date: 2005-07-11 09:24-0500\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME \n" "Language-Team: LANGUAGE \n" @@ -15,56 +16,142 @@ msgstr "" "Content-Type: text/plain; charset=CHARSET\n" "Content-Transfer-Encoding: 8bit\n" -#: alpha-opc.c:331 +#: alpha-opc.c:155 msgid "branch operand unaligned" msgstr "" -#: alpha-opc.c:353 alpha-opc.c:374 +#: alpha-opc.c:171 alpha-opc.c:187 msgid "jump hint unaligned" msgstr "" -#: arc-dis.c:76 +#: arc-dis.c:75 msgid "Illegal limm reference in last instruction!\n" msgstr "" -#: arm-dis.c:1293 +#: arc-opc.c:384 +msgid "unable to fit different valued constants into instruction" +msgstr "" + +#: arc-opc.c:393 +msgid "auxiliary register not allowed here" +msgstr "" + +#: arc-opc.c:399 arc-opc.c:416 +msgid "attempt to set readonly register" +msgstr "" + +#: arc-opc.c:404 arc-opc.c:421 +msgid "attempt to read writeonly register" +msgstr "" + +#: arc-opc.c:426 +#, c-format +msgid "invalid register number `%d'" +msgstr "" + +#: arc-opc.c:592 arc-opc.c:643 arc-opc.c:671 +msgid "too many long constants" +msgstr "" + +#: arc-opc.c:666 +msgid "to many shimms in load" +msgstr "" + +#. Do we have a limm already? +#: arc-opc.c:779 +msgid "impossible store" +msgstr "" + +#: arc-opc.c:812 +msgid "st operand error" +msgstr "" + +#: arc-opc.c:816 arc-opc.c:858 +msgid "address writeback not allowed" +msgstr "" + +#: arc-opc.c:820 +msgid "store value must be zero" +msgstr "" + +#: arc-opc.c:845 +msgid "invalid load/shimm insn" +msgstr "" + +#: arc-opc.c:854 +msgid "ld operand error" +msgstr "" + +#: arc-opc.c:941 +msgid "jump flags, but no .f seen" +msgstr "" + +#: arc-opc.c:944 +msgid "jump flags, but no limm addr" +msgstr "" + +#: arc-opc.c:947 +msgid "flag bits of jump address limm lost" +msgstr "" + +#: arc-opc.c:950 +msgid "attempt to set HR bits" +msgstr "" + +#: arc-opc.c:953 +msgid "bad jump flags value" +msgstr "" + +#: arc-opc.c:986 +msgid "branch address not on 4 byte boundary" +msgstr "" + +#: arc-opc.c:1022 +msgid "must specify .jd or no nullify suffix" +msgstr "" + +#: arm-dis.c:1505 msgid "" msgstr "" #. XXX - should break 'option' at following delimiter. -#: arm-dis.c:1964 +#: arm-dis.c:2551 #, c-format msgid "Unrecognised register name set: %s\n" msgstr "" #. XXX - should break 'option' at following delimiter. -#: arm-dis.c:1972 +#: arm-dis.c:2559 #, c-format msgid "Unrecognised disassembler option: %s\n" msgstr "" -#: arm-dis.c:2145 +#: arm-dis.c:2721 +#, c-format msgid "" "\n" "The following ARM specific disassembler options are supported for use with\n" "the -M switch:\n" msgstr "" -#: avr-dis.c:112 avr-dis.c:122 +#: avr-dis.c:109 avr-dis.c:119 +#, c-format msgid "undefined" msgstr "" -#: avr-dis.c:179 +#: avr-dis.c:176 +#, c-format msgid "Internal disassembler error" msgstr "" -#: avr-dis.c:227 +#: avr-dis.c:225 #, c-format msgid "unknown constraint `%c'" msgstr "" -#: cgen-asm.c:336 fr30-ibld.c:197 frv-ibld.c:197 ip2k-ibld.c:197 -#: iq2000-ibld.c:197 m32r-ibld.c:197 openrisc-ibld.c:197 xstormy16-ibld.c:197 +#: cgen-asm.c:336 fr30-ibld.c:192 frv-ibld.c:192 ip2k-ibld.c:192 +#: iq2000-ibld.c:192 m32c-ibld.c:197 m32r-ibld.c:192 ms1-ibld.c:192 +#: openrisc-ibld.c:192 xstormy16-ibld.c:192 #, c-format msgid "operand out of range (%ld not between %ld and %ld)" msgstr "" @@ -74,7 +161,7 @@ msgstr "" msgid "operand out of range (%lu not between %lu and %lu)" msgstr "" -#: d30v-dis.c:312 +#: d30v-dis.c:252 #, c-format msgid "" msgstr "" @@ -90,148 +177,201 @@ msgstr "" msgid "Address 0x%s is out of bounds.\n" msgstr "" -#: fr30-asm.c:323 frv-asm.c:1298 ip2k-asm.c:530 iq2000-asm.c:466 -#: m32r-asm.c:338 openrisc-asm.c:252 xstormy16-asm.c:284 +#: fr30-asm.c:92 m32c-asm.c:872 m32c-asm.c:879 +msgid "Register number is not valid" +msgstr "" + +#: fr30-asm.c:94 +msgid "Register must be between r0 and r7" +msgstr "" + +#: fr30-asm.c:96 +msgid "Register must be between r8 and r15" +msgstr "" + +#: fr30-asm.c:115 m32c-asm.c:910 +msgid "Register list is not valid" +msgstr "" + +#: fr30-asm.c:309 frv-asm.c:1262 ip2k-asm.c:510 iq2000-asm.c:456 +#: m32c-asm.c:1564 m32r-asm.c:327 ms1-asm.c:546 openrisc-asm.c:240 +#: xstormy16-asm.c:275 #, c-format msgid "Unrecognized field %d while parsing.\n" msgstr "" -#: fr30-asm.c:372 frv-asm.c:1347 ip2k-asm.c:579 iq2000-asm.c:515 -#: m32r-asm.c:387 openrisc-asm.c:301 xstormy16-asm.c:333 +#: fr30-asm.c:357 frv-asm.c:1310 ip2k-asm.c:558 iq2000-asm.c:504 +#: m32c-asm.c:1613 m32r-asm.c:375 ms1-asm.c:594 openrisc-asm.c:288 +#: xstormy16-asm.c:323 msgid "missing mnemonic in syntax string" msgstr "" #. We couldn't parse it. -#: fr30-asm.c:507 fr30-asm.c:511 fr30-asm.c:598 fr30-asm.c:699 frv-asm.c:1482 -#: frv-asm.c:1486 frv-asm.c:1573 frv-asm.c:1674 ip2k-asm.c:714 ip2k-asm.c:718 -#: ip2k-asm.c:805 ip2k-asm.c:906 iq2000-asm.c:650 iq2000-asm.c:654 -#: iq2000-asm.c:741 iq2000-asm.c:842 m32r-asm.c:522 m32r-asm.c:526 -#: m32r-asm.c:613 m32r-asm.c:714 openrisc-asm.c:436 openrisc-asm.c:440 -#: openrisc-asm.c:527 openrisc-asm.c:628 xstormy16-asm.c:468 -#: xstormy16-asm.c:472 xstormy16-asm.c:559 xstormy16-asm.c:660 +#: fr30-asm.c:492 fr30-asm.c:496 fr30-asm.c:583 fr30-asm.c:684 frv-asm.c:1445 +#: frv-asm.c:1449 frv-asm.c:1536 frv-asm.c:1637 ip2k-asm.c:693 ip2k-asm.c:697 +#: ip2k-asm.c:784 ip2k-asm.c:885 iq2000-asm.c:639 iq2000-asm.c:643 +#: iq2000-asm.c:730 iq2000-asm.c:831 m32c-asm.c:1748 m32c-asm.c:1752 +#: m32c-asm.c:1839 m32c-asm.c:1940 m32r-asm.c:510 m32r-asm.c:514 +#: m32r-asm.c:601 m32r-asm.c:702 ms1-asm.c:729 ms1-asm.c:733 ms1-asm.c:820 +#: ms1-asm.c:921 openrisc-asm.c:423 openrisc-asm.c:427 openrisc-asm.c:514 +#: openrisc-asm.c:615 xstormy16-asm.c:458 xstormy16-asm.c:462 +#: xstormy16-asm.c:549 xstormy16-asm.c:650 msgid "unrecognized instruction" msgstr "" -#: fr30-asm.c:554 frv-asm.c:1529 ip2k-asm.c:761 iq2000-asm.c:697 -#: m32r-asm.c:569 openrisc-asm.c:483 xstormy16-asm.c:515 +#: fr30-asm.c:539 frv-asm.c:1492 ip2k-asm.c:740 iq2000-asm.c:686 +#: m32c-asm.c:1795 m32r-asm.c:557 ms1-asm.c:776 openrisc-asm.c:470 +#: xstormy16-asm.c:505 #, c-format msgid "syntax error (expected char `%c', found `%c')" msgstr "" -#: fr30-asm.c:564 frv-asm.c:1539 ip2k-asm.c:771 iq2000-asm.c:707 -#: m32r-asm.c:579 openrisc-asm.c:493 xstormy16-asm.c:525 +#: fr30-asm.c:549 frv-asm.c:1502 ip2k-asm.c:750 iq2000-asm.c:696 +#: m32c-asm.c:1805 m32r-asm.c:567 ms1-asm.c:786 openrisc-asm.c:480 +#: xstormy16-asm.c:515 #, c-format msgid "syntax error (expected char `%c', found end of instruction)" msgstr "" -#: fr30-asm.c:592 frv-asm.c:1567 ip2k-asm.c:799 iq2000-asm.c:735 -#: m32r-asm.c:607 openrisc-asm.c:521 xstormy16-asm.c:553 +#: fr30-asm.c:577 frv-asm.c:1530 ip2k-asm.c:778 iq2000-asm.c:724 +#: m32c-asm.c:1833 m32r-asm.c:595 ms1-asm.c:814 openrisc-asm.c:508 +#: xstormy16-asm.c:543 msgid "junk at end of line" msgstr "" -#: fr30-asm.c:698 frv-asm.c:1673 ip2k-asm.c:905 iq2000-asm.c:841 -#: m32r-asm.c:713 openrisc-asm.c:627 xstormy16-asm.c:659 +#: fr30-asm.c:683 frv-asm.c:1636 ip2k-asm.c:884 iq2000-asm.c:830 +#: m32c-asm.c:1939 m32r-asm.c:701 ms1-asm.c:920 openrisc-asm.c:614 +#: xstormy16-asm.c:649 msgid "unrecognized form of instruction" msgstr "" -#: fr30-asm.c:710 frv-asm.c:1685 ip2k-asm.c:917 iq2000-asm.c:853 -#: m32r-asm.c:725 openrisc-asm.c:639 xstormy16-asm.c:671 +#: fr30-asm.c:695 frv-asm.c:1648 ip2k-asm.c:896 iq2000-asm.c:842 +#: m32c-asm.c:1951 m32r-asm.c:713 ms1-asm.c:932 openrisc-asm.c:626 +#: xstormy16-asm.c:661 #, c-format msgid "bad instruction `%.50s...'" msgstr "" -#: fr30-asm.c:713 frv-asm.c:1688 ip2k-asm.c:920 iq2000-asm.c:856 -#: m32r-asm.c:728 openrisc-asm.c:642 xstormy16-asm.c:674 +#: fr30-asm.c:698 frv-asm.c:1651 ip2k-asm.c:899 iq2000-asm.c:845 +#: m32c-asm.c:1954 m32r-asm.c:716 ms1-asm.c:935 openrisc-asm.c:629 +#: xstormy16-asm.c:664 #, c-format msgid "bad instruction `%.50s'" msgstr "" #. Default text to print if an instruction isn't recognized. -#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41 -#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41 +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32c-dis.c:41 +#: m32r-dis.c:41 mmix-dis.c:278 ms1-dis.c:41 openrisc-dis.c:41 +#: xstormy16-dis.c:41 msgid "*unknown*" msgstr "" -#: fr30-dis.c:319 frv-dis.c:410 ip2k-dis.c:313 iq2000-dis.c:191 m32r-dis.c:262 -#: openrisc-dis.c:137 xstormy16-dis.c:170 +#: fr30-dis.c:299 frv-dis.c:396 ip2k-dis.c:288 iq2000-dis.c:189 m32c-dis.c:868 +#: m32r-dis.c:256 ms1-dis.c:258 openrisc-dis.c:135 xstormy16-dis.c:168 #, c-format msgid "Unrecognized field %d while printing insn.\n" msgstr "" -#: fr30-ibld.c:168 frv-ibld.c:168 ip2k-ibld.c:168 iq2000-ibld.c:168 -#: m32r-ibld.c:168 openrisc-ibld.c:168 xstormy16-ibld.c:168 +#: fr30-ibld.c:163 frv-ibld.c:163 ip2k-ibld.c:163 iq2000-ibld.c:163 +#: m32c-ibld.c:168 m32r-ibld.c:163 ms1-ibld.c:163 openrisc-ibld.c:163 +#: xstormy16-ibld.c:163 #, c-format msgid "operand out of range (%ld not between %ld and %lu)" msgstr "" -#: fr30-ibld.c:181 frv-ibld.c:181 ip2k-ibld.c:181 iq2000-ibld.c:181 -#: m32r-ibld.c:181 openrisc-ibld.c:181 xstormy16-ibld.c:181 +#: fr30-ibld.c:176 frv-ibld.c:176 ip2k-ibld.c:176 iq2000-ibld.c:176 +#: m32c-ibld.c:181 m32r-ibld.c:176 ms1-ibld.c:176 openrisc-ibld.c:176 +#: xstormy16-ibld.c:176 #, c-format msgid "operand out of range (%lu not between 0 and %lu)" msgstr "" -#: fr30-ibld.c:732 frv-ibld.c:858 ip2k-ibld.c:609 iq2000-ibld.c:715 -#: m32r-ibld.c:667 openrisc-ibld.c:635 xstormy16-ibld.c:680 +#: fr30-ibld.c:719 frv-ibld.c:845 ip2k-ibld.c:596 iq2000-ibld.c:702 +#: m32c-ibld.c:1672 m32r-ibld.c:654 ms1-ibld.c:713 openrisc-ibld.c:622 +#: xstormy16-ibld.c:667 #, c-format msgid "Unrecognized field %d while building insn.\n" msgstr "" -#: fr30-ibld.c:939 frv-ibld.c:1177 ip2k-ibld.c:686 iq2000-ibld.c:892 -#: m32r-ibld.c:806 openrisc-ibld.c:737 xstormy16-ibld.c:828 +#: fr30-ibld.c:924 frv-ibld.c:1162 ip2k-ibld.c:671 iq2000-ibld.c:877 +#: m32c-ibld.c:2778 m32r-ibld.c:791 ms1-ibld.c:907 openrisc-ibld.c:722 +#: xstormy16-ibld.c:813 #, c-format msgid "Unrecognized field %d while decoding insn.\n" msgstr "" -#: fr30-ibld.c:1088 frv-ibld.c:1458 ip2k-ibld.c:763 iq2000-ibld.c:1026 -#: m32r-ibld.c:922 openrisc-ibld.c:817 xstormy16-ibld.c:941 +#: fr30-ibld.c:1070 frv-ibld.c:1440 ip2k-ibld.c:745 iq2000-ibld.c:1008 +#: m32c-ibld.c:3377 m32r-ibld.c:904 ms1-ibld.c:1086 openrisc-ibld.c:799 +#: xstormy16-ibld.c:923 #, c-format msgid "Unrecognized field %d while getting int operand.\n" msgstr "" -#: fr30-ibld.c:1217 frv-ibld.c:1719 ip2k-ibld.c:820 iq2000-ibld.c:1140 -#: m32r-ibld.c:1018 openrisc-ibld.c:877 xstormy16-ibld.c:1034 +#: fr30-ibld.c:1198 frv-ibld.c:1700 ip2k-ibld.c:801 iq2000-ibld.c:1121 +#: m32c-ibld.c:3956 m32r-ibld.c:999 ms1-ibld.c:1247 openrisc-ibld.c:858 +#: xstormy16-ibld.c:1015 #, c-format msgid "Unrecognized field %d while getting vma operand.\n" msgstr "" -#: fr30-ibld.c:1351 frv-ibld.c:1989 ip2k-ibld.c:882 iq2000-ibld.c:1263 -#: m32r-ibld.c:1122 openrisc-ibld.c:946 xstormy16-ibld.c:1136 +#: fr30-ibld.c:1329 frv-ibld.c:1967 ip2k-ibld.c:860 iq2000-ibld.c:1241 +#: m32c-ibld.c:4525 m32r-ibld.c:1100 ms1-ibld.c:1415 openrisc-ibld.c:924 +#: xstormy16-ibld.c:1114 #, c-format msgid "Unrecognized field %d while setting int operand.\n" msgstr "" -#: fr30-ibld.c:1473 frv-ibld.c:2247 ip2k-ibld.c:932 iq2000-ibld.c:1374 -#: m32r-ibld.c:1214 openrisc-ibld.c:1003 xstormy16-ibld.c:1226 +#: fr30-ibld.c:1450 frv-ibld.c:2224 ip2k-ibld.c:909 iq2000-ibld.c:1351 +#: m32c-ibld.c:5082 m32r-ibld.c:1191 ms1-ibld.c:1573 openrisc-ibld.c:980 +#: xstormy16-ibld.c:1203 #, c-format msgid "Unrecognized field %d while setting vma operand.\n" msgstr "" -#: frv-asm.c:978 +#: frv-asm.c:607 +msgid "missing `]'" +msgstr "" + +#: frv-asm.c:610 frv-asm.c:620 +msgid "Special purpose register number is out of range" +msgstr "" + +#: frv-asm.c:907 +msgid "Value of A operand must be 0 or 1" +msgstr "" + +#: frv-asm.c:943 msgid "register number must be even" msgstr "" -#: h8300-dis.c:358 +#. -- assembler routines inserted here. +#. -- asm.c +#: frv-asm.c:971 iq2000-asm.c:55 m32r-asm.c:52 openrisc-asm.c:53 +msgid "missing `)'" +msgstr "" + +#: h8300-dis.c:325 #, c-format msgid "Hmmmm 0x%x" msgstr "" -#: h8300-dis.c:744 +#: h8300-dis.c:706 #, c-format msgid "Don't understand 0x%x \n" msgstr "" -#: h8500-dis.c:143 +#: h8500-dis.c:122 #, c-format msgid "can't cope with insert %d\n" msgstr "" #. Couldn't understand anything. -#: h8500-dis.c:342 +#: h8500-dis.c:322 #, c-format msgid "%02x\t\t*unknown*" msgstr "" -#: i386-dis.c:1733 +#: i386-dis.c:1737 msgid "" msgstr "" @@ -343,144 +483,178 @@ msgstr "" #. We've been passed a w. Return with an error message so that #. cgen will try the next parsing option. -#: ip2k-asm.c:92 +#: ip2k-asm.c:80 msgid "W keyword invalid in FR operand slot." msgstr "" #. Invalid offset present. -#: ip2k-asm.c:117 +#: ip2k-asm.c:105 msgid "offset(IP) is not a valid form" msgstr "" #. Found something there in front of (DP) but it's out #. of range. -#: ip2k-asm.c:165 +#: ip2k-asm.c:153 msgid "(DP) offset out of range." msgstr "" #. Found something there in front of (SP) but it's out #. of range. -#: ip2k-asm.c:206 +#: ip2k-asm.c:194 msgid "(SP) offset out of range." msgstr "" -#: ip2k-asm.c:222 +#: ip2k-asm.c:210 msgid "illegal use of parentheses" msgstr "" -#: ip2k-asm.c:229 +#: ip2k-asm.c:217 msgid "operand out of range (not between 1 and 255)" msgstr "" #. Something is very wrong. opindex has to be one of the above. -#: ip2k-asm.c:254 +#: ip2k-asm.c:241 msgid "parse_addr16: invalid opindex." msgstr "" -#: ip2k-asm.c:309 +#: ip2k-asm.c:295 msgid "Byte address required. - must be even." msgstr "" -#: ip2k-asm.c:318 +#: ip2k-asm.c:304 msgid "cgen_parse_address returned a symbol. Literal required." msgstr "" -#: ip2k-asm.c:376 +#: ip2k-asm.c:359 msgid "percent-operator operand is not a symbol" msgstr "" -#: ip2k-asm.c:430 +#: ip2k-asm.c:412 msgid "Attempt to find bit index of 0" msgstr "" -#: iq2000-asm.c:115 iq2000-asm.c:146 +#: iq2000-asm.c:111 iq2000-asm.c:141 msgid "immediate value cannot be register" msgstr "" -#: iq2000-asm.c:126 iq2000-asm.c:156 +#: iq2000-asm.c:122 iq2000-asm.c:152 msgid "immediate value out of range" msgstr "" -#: iq2000-asm.c:185 +#: iq2000-asm.c:181 msgid "21-bit offset out of range" msgstr "" -#: iq2000-asm.c:210 iq2000-asm.c:240 iq2000-asm.c:277 iq2000-asm.c:310 -#: openrisc-asm.c:90 openrisc-asm.c:144 -msgid "missing `)'" +#: m10200-dis.c:156 m10300-dis.c:580 +#, c-format +msgid "unknown\t0x%04lx" msgstr "" -#: m10200-dis.c:199 +#: m10200-dis.c:326 #, c-format -msgid "unknown\t0x%02x" +msgid "unknown\t0x%02lx" msgstr "" -#: m10200-dis.c:339 -#, c-format -msgid "unknown\t0x%04lx" +#: m32c-asm.c:100 +msgid "imm:6 immediate is out of range" msgstr "" -#: m10300-dis.c:767 -#, c-format -msgid "unknown\t0x%04x" +#: m32c-asm.c:127 m32c-asm.c:131 m32c-asm.c:187 +msgid "dsp:8 immediate is out of range" msgstr "" -#: m68k-dis.c:295 -#, c-format -msgid "\n" +#: m32c-asm.c:158 m32c-asm.c:162 +msgid "Immediate is out of range -8 to 7" +msgstr "" + +#: m32c-asm.c:218 m32c-asm.c:225 m32c-asm.c:250 +msgid "dsp:16 immediate is out of range" +msgstr "" + +#: m32c-asm.c:276 +msgid "dsp:20 immediate is out of range" +msgstr "" + +#: m32c-asm.c:302 +msgid "dsp:24 immediate is out of range" +msgstr "" + +#: m32c-asm.c:355 +msgid "immediate is out of range 1-2" +msgstr "" + +#: m32c-asm.c:383 +msgid "immediate is out of range 1-8" +msgstr "" + +#: m32c-asm.c:407 +msgid "Bit number for indexing general register is out of range 0-15" +msgstr "" + +#: m32c-asm.c:445 m32c-asm.c:486 +msgid "bit,base is out of range" msgstr "" -#: m68k-dis.c:1089 +#: m68k-dis.c:1162 #, c-format msgid "" msgstr "" -#: m88k-dis.c:746 +#: m68k-dis.c:1313 +#, c-format +msgid "\n" +msgstr "" + +#: m88k-dis.c:679 #, c-format -msgid "# " +msgid "# " msgstr "" -#: mips-dis.c:720 +#: mips-dis.c:718 msgid "# internal error, incomplete extension sequence (+)" msgstr "" -#: mips-dis.c:779 +#: mips-dis.c:777 #, c-format msgid "# internal error, undefined extension sequence (+%c)" msgstr "" -#: mips-dis.c:1037 +#: mips-dis.c:1038 #, c-format msgid "# internal error, undefined modifier(%c)" msgstr "" -#: mips-dis.c:1793 +#: mips-dis.c:1548 #, c-format msgid "# internal disassembler error, unrecognised modifier (%c)" msgstr "" -#: mips-dis.c:1805 +#: mips-dis.c:1779 +#, c-format msgid "" "\n" "The following MIPS specific disassembler options are supported for use\n" "with the -M switch (multiple options should be separated by commas):\n" msgstr "" -#: mips-dis.c:1809 +#: mips-dis.c:1783 +#, c-format msgid "" "\n" " gpr-names=ABI Print GPR names according to specified ABI.\n" " Default: based on binary being disassembled.\n" msgstr "" -#: mips-dis.c:1813 +#: mips-dis.c:1787 +#, c-format msgid "" "\n" " fpr-names=ABI Print FPR names according to specified ABI.\n" " Default: numeric.\n" msgstr "" -#: mips-dis.c:1817 +#: mips-dis.c:1791 +#, c-format msgid "" "\n" " cp0-names=ARCH Print CP0 register names according to\n" @@ -488,7 +662,8 @@ msgid "" " Default: based on binary being disassembled.\n" msgstr "" -#: mips-dis.c:1822 +#: mips-dis.c:1796 +#, c-format msgid "" "\n" " hwr-names=ARCH Print HWR names according to specified \n" @@ -496,181 +671,203 @@ msgid "" " Default: based on binary being disassembled.\n" msgstr "" -#: mips-dis.c:1827 +#: mips-dis.c:1801 +#, c-format msgid "" "\n" " reg-names=ABI Print GPR and FPR names according to\n" " specified ABI.\n" msgstr "" -#: mips-dis.c:1831 +#: mips-dis.c:1805 +#, c-format msgid "" "\n" " reg-names=ARCH Print CP0 register and HWR names according to\n" " specified architecture.\n" msgstr "" -#: mips-dis.c:1835 +#: mips-dis.c:1809 +#, c-format msgid "" "\n" " For the options above, the following values are supported for \"ABI\":\n" " " msgstr "" -#: mips-dis.c:1840 mips-dis.c:1848 mips-dis.c:1850 +#: mips-dis.c:1814 mips-dis.c:1822 mips-dis.c:1824 +#, c-format msgid "\n" msgstr "" -#: mips-dis.c:1842 +#: mips-dis.c:1816 +#, c-format msgid "" "\n" " For the options above, The following values are supported for \"ARCH\":\n" " " msgstr "" -#: mmix-dis.c:34 +#: mmix-dis.c:35 #, c-format msgid "Bad case %d (%s) in %s:%d\n" msgstr "" -#: mmix-dis.c:44 +#: mmix-dis.c:45 #, c-format msgid "Internal: Non-debugged code (test-case missing): %s:%d" msgstr "" -#: mmix-dis.c:53 +#: mmix-dis.c:54 msgid "(unknown)" msgstr "" -#: mmix-dis.c:519 +#: mmix-dis.c:513 #, c-format msgid "*unknown operands type: %d*" msgstr "" +#: ms1-asm.c:84 ms1-asm.c:162 +msgid "Operand out of range. Must be between -32768 and 32767." +msgstr "" + +#: ms1-asm.c:121 +msgid "Biiiig Trouble in parse_imm16!" +msgstr "" + +#: ms1-asm.c:129 +#, c-format +msgid "%operator operand is not a symbol" +msgstr "" + +#: ms1-asm.c:367 +msgid "invalid operand. type may have values 0,1,2 only." +msgstr "" + #. I and Z are output operands and can`t be immediate -#. * A is an address and we can`t have the address of -#. * an immediate either. We don't know how much to increase -#. * aoffsetp by since whatever generated this is broken -#. * anyway! -#. -#: ns32k-dis.c:631 +#. A is an address and we can`t have the address of +#. an immediate either. We don't know how much to increase +#. aoffsetp by since whatever generated this is broken +#. anyway! +#: ns32k-dis.c:535 +#, c-format msgid "$" msgstr "" -#: ppc-opc.c:795 ppc-opc.c:823 +#: ppc-opc.c:800 ppc-opc.c:828 msgid "invalid conditional option" msgstr "" -#: ppc-opc.c:825 +#: ppc-opc.c:830 msgid "attempt to set y bit when using + or - modifier" msgstr "" -#: ppc-opc.c:853 +#: ppc-opc.c:858 msgid "offset not a multiple of 16" msgstr "" -#: ppc-opc.c:872 +#: ppc-opc.c:877 msgid "offset not a multiple of 2" msgstr "" -#: ppc-opc.c:874 +#: ppc-opc.c:879 msgid "offset greater than 62" msgstr "" -#: ppc-opc.c:893 ppc-opc.c:938 ppc-opc.c:982 +#: ppc-opc.c:898 ppc-opc.c:943 ppc-opc.c:987 msgid "offset not a multiple of 4" msgstr "" -#: ppc-opc.c:895 +#: ppc-opc.c:900 msgid "offset greater than 124" msgstr "" -#: ppc-opc.c:914 +#: ppc-opc.c:919 msgid "offset not a multiple of 8" msgstr "" -#: ppc-opc.c:916 +#: ppc-opc.c:921 msgid "offset greater than 248" msgstr "" -#: ppc-opc.c:959 +#: ppc-opc.c:964 msgid "offset not between -2048 and 2047" msgstr "" -#: ppc-opc.c:980 +#: ppc-opc.c:985 msgid "offset not between -8192 and 8191" msgstr "" -#: ppc-opc.c:1008 +#: ppc-opc.c:1013 msgid "invalid mask field" msgstr "" -#: ppc-opc.c:1034 +#: ppc-opc.c:1039 msgid "ignoring invalid mfcr mask" msgstr "" -#: ppc-opc.c:1076 +#: ppc-opc.c:1081 msgid "ignoring least significant bits in branch offset" msgstr "" -#: ppc-opc.c:1106 ppc-opc.c:1141 +#: ppc-opc.c:1111 ppc-opc.c:1146 msgid "illegal bitmask" msgstr "" -#: ppc-opc.c:1206 +#: ppc-opc.c:1211 msgid "value out of range" msgstr "" -#: ppc-opc.c:1274 +#: ppc-opc.c:1279 msgid "index register in load range" msgstr "" -#: ppc-opc.c:1290 +#: ppc-opc.c:1295 msgid "source and target register operands must be different" msgstr "" -#: ppc-opc.c:1305 +#: ppc-opc.c:1310 msgid "invalid register operand when updating" msgstr "" -#: ppc-opc.c:1344 +#: ppc-opc.c:1349 msgid "target register operand must be even" msgstr "" -#: ppc-opc.c:1358 +#: ppc-opc.c:1363 msgid "source register operand must be even" msgstr "" -#: ppc-opc.c:1415 +#: ppc-opc.c:1420 msgid "invalid sprg number" msgstr "" -#. Mark as non-valid instruction. -#: sparc-dis.c:760 -msgid "unknown" -msgstr "" - -#: sparc-dis.c:835 +#: sparc-dis.c:269 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "" -#: sparc-dis.c:846 +#: sparc-dis.c:280 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "" -#: sparc-dis.c:895 +#: sparc-dis.c:330 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" msgstr "" -#: v850-dis.c:225 +#. Mark as non-valid instruction. +#: sparc-dis.c:984 +msgid "unknown" +msgstr "" + +#: v850-dis.c:237 #, c-format msgid "unknown operand shift: %x\n" msgstr "" -#: v850-dis.c:237 +#: v850-dis.c:251 #, c-format msgid "unknown pop reg: %d\n" msgstr "" @@ -680,86 +877,86 @@ msgstr "" #. v850_insert_operand() in gas/config/tc-v850.c. Error messages #. containing the string 'out of range' will be ignored unless a #. specific command line option is given to GAS. -#: v850-opc.c:69 +#: v850-opc.c:46 msgid "displacement value is not in range and is not aligned" msgstr "" -#: v850-opc.c:70 +#: v850-opc.c:47 msgid "displacement value is out of range" msgstr "" -#: v850-opc.c:71 +#: v850-opc.c:48 msgid "displacement value is not aligned" msgstr "" -#: v850-opc.c:73 +#: v850-opc.c:50 msgid "immediate value is out of range" msgstr "" -#: v850-opc.c:84 +#: v850-opc.c:58 msgid "branch value not in range and to odd offset" msgstr "" -#: v850-opc.c:86 v850-opc.c:118 +#: v850-opc.c:60 v850-opc.c:87 msgid "branch value out of range" msgstr "" -#: v850-opc.c:89 v850-opc.c:121 +#: v850-opc.c:63 v850-opc.c:90 msgid "branch to odd offset" msgstr "" -#: v850-opc.c:116 +#: v850-opc.c:85 msgid "branch value not in range and to an odd offset" msgstr "" -#: v850-opc.c:347 +#: v850-opc.c:277 msgid "invalid register for stack adjustment" msgstr "" -#: v850-opc.c:371 +#: v850-opc.c:297 msgid "immediate value not in range and not even" msgstr "" -#: v850-opc.c:376 +#: v850-opc.c:302 msgid "immediate value must be even" msgstr "" -#: xstormy16-asm.c:76 +#: xstormy16-asm.c:70 msgid "Bad register in preincrement" msgstr "" -#: xstormy16-asm.c:81 +#: xstormy16-asm.c:75 msgid "Bad register in postincrement" msgstr "" -#: xstormy16-asm.c:83 +#: xstormy16-asm.c:77 msgid "Bad register name" msgstr "" -#: xstormy16-asm.c:87 +#: xstormy16-asm.c:81 msgid "Label conflicts with register name" msgstr "" -#: xstormy16-asm.c:91 +#: xstormy16-asm.c:85 msgid "Label conflicts with `Rx'" msgstr "" -#: xstormy16-asm.c:93 +#: xstormy16-asm.c:87 msgid "Bad immediate expression" msgstr "" -#: xstormy16-asm.c:115 +#: xstormy16-asm.c:108 msgid "No relocation for small immediate" msgstr "" -#: xstormy16-asm.c:125 +#: xstormy16-asm.c:118 msgid "Small operand was not an immediate number" msgstr "" -#: xstormy16-asm.c:164 +#: xstormy16-asm.c:156 msgid "Operand is not a symbol" msgstr "" -#: xstormy16-asm.c:172 +#: xstormy16-asm.c:164 msgid "Syntax error: No trailing ')'" msgstr "" diff -uprN binutils-2.16.91.0.1/opcodes/po/POTFILES.in binutils-2.16.91.0.2/opcodes/po/POTFILES.in --- binutils-2.16.91.0.1/opcodes/po/POTFILES.in 2004-11-22 12:33:34.000000000 -0800 +++ binutils-2.16.91.0.2/opcodes/po/POTFILES.in 2005-07-20 12:27:29.430840547 -0700 @@ -5,11 +5,12 @@ arc-dis.c arc-ext.c arc-opc.c arm-dis.c -arm-opc.h avr-dis.c cgen-asm.c cgen-dis.c cgen-opc.c +cgen-ops.h +cgen-types.h cris-dis.c cris-opc.c crx-dis.c @@ -75,6 +76,13 @@ m10200-dis.c m10200-opc.c m10300-dis.c m10300-opc.c +m32c-asm.c +m32c-desc.c +m32c-desc.h +m32c-dis.c +m32c-ibld.c +m32c-opc.c +m32c-opc.h m32r-asm.c m32r-desc.c m32r-desc.h @@ -96,6 +104,13 @@ mips-dis.c mips-opc.c mmix-dis.c mmix-opc.c +ms1-asm.c +ms1-desc.c +ms1-desc.h +ms1-dis.c +ms1-ibld.c +ms1-opc.c +ms1-opc.h ns32k-dis.c openrisc-asm.c openrisc-desc.c diff -uprN binutils-2.16.91.0.1/opcodes/ppc-dis.c binutils-2.16.91.0.2/opcodes/ppc-dis.c --- binutils-2.16.91.0.1/opcodes/ppc-dis.c 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/ppc-dis.c 2005-07-20 12:27:29.364851429 -0700 @@ -249,7 +249,7 @@ print_insn_powerpc (bfd_vma memaddr, else { if (operand->bits == 3) - (*info->fprintf_func) (info->stream, "cr%d", value); + (*info->fprintf_func) (info->stream, "cr%ld", value); else { static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; diff -uprN binutils-2.16.91.0.1/opcodes/s390-dis.c binutils-2.16.91.0.2/opcodes/s390-dis.c --- binutils-2.16.91.0.1/opcodes/s390-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/s390-dis.c 2005-07-20 12:27:29.364851429 -0700 @@ -1,5 +1,5 @@ /* s390-dis.c -- Disassemble S390 instructions - Copyright 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + Copyright 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). This file is part of GDB, GAS and the GNU binutils. @@ -29,15 +29,10 @@ static int init_flag = 0; static int opc_index[256]; static int current_arch_mask = 0; -static void init_disasm PARAMS ((struct disassemble_info *)); -static unsigned int s390_extract_operand - PARAMS ((unsigned char *, const struct s390_operand *)); - /* Set up index table for first opcode byte. */ static void -init_disasm (info) - struct disassemble_info *info; +init_disasm (struct disassemble_info *info) { const struct s390_opcode *opcode; const struct s390_opcode *opcode_end; @@ -68,9 +63,7 @@ init_disasm (info) /* Extracts an operand value from an instruction. */ static inline unsigned int -s390_extract_operand (insn, operand) - unsigned char *insn; - const struct s390_operand *operand; +s390_extract_operand (unsigned char *insn, const struct s390_operand *operand) { unsigned int val; int bits; @@ -102,7 +95,7 @@ s390_extract_operand (insn, operand) if (operand->flags & S390_OPERAND_PCREL) val <<= 1; - /* Length x in an instructions has real length x+1. */ + /* Length x in an instructions has real length x + 1. */ if (operand->flags & S390_OPERAND_LENGTH) val++; return val; @@ -111,9 +104,7 @@ s390_extract_operand (insn, operand) /* Print a S390 instruction. */ int -print_insn_s390 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info) { bfd_byte buffer[6]; const struct s390_opcode *opcode; diff -uprN binutils-2.16.91.0.1/opcodes/sh64-dis.c binutils-2.16.91.0.2/opcodes/sh64-dis.c --- binutils-2.16.91.0.1/opcodes/sh64-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/sh64-dis.c 2005-07-20 12:27:29.373849945 -0700 @@ -1,5 +1,5 @@ /* Disassemble SH64 instructions. - Copyright 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + Copyright 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -21,7 +21,6 @@ #include "sysdep.h" #include "sh64-opc.h" #include "libiberty.h" - /* We need to refer to the ELF header structure. */ #include "elf-bfd.h" #include "elf/sh.h" @@ -54,18 +53,11 @@ struct sh64_disassemble_info Note that some archs have this as a field in the opcode table. */ static unsigned long *shmedia_opcode_mask_table; -static void initialize_shmedia_opcode_mask_table PARAMS ((void)); -static int print_insn_shmedia PARAMS ((bfd_vma, disassemble_info *)); -static const char *creg_name PARAMS ((int)); -static bfd_boolean init_sh64_disasm_info PARAMS ((struct disassemble_info *)); -static enum sh64_elf_cr_type sh64_get_contents_type_disasm - PARAMS ((bfd_vma, struct disassemble_info *)); - /* Initialize the SH64 opcode mask table for each instruction in SHmedia mode. */ static void -initialize_shmedia_opcode_mask_table () +initialize_shmedia_opcode_mask_table (void) { int n_opc; int n; @@ -163,19 +155,16 @@ initialize_shmedia_opcode_mask_table () /* Get a predefined control-register-name, or return NULL. */ -const char * -creg_name (cregno) - int cregno; +static const char * +creg_name (int cregno) { const shmedia_creg_info *cregp; /* If control register usage is common enough, change this to search a hash-table. */ for (cregp = shmedia_creg_table; cregp->name != NULL; cregp++) - { - if (cregp->cregno == cregno) - return cregp->name; - } + if (cregp->cregno == cregno) + return cregp->name; return NULL; } @@ -183,13 +172,10 @@ creg_name (cregno) /* Main function to disassemble SHmedia instructions. */ static int -print_insn_shmedia (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_shmedia (bfd_vma memaddr, struct disassemble_info *info) { fprintf_ftype fprintf_fn = info->fprintf_func; void *stream = info->stream; - unsigned char insn[4]; unsigned long instruction; int status; @@ -238,7 +224,7 @@ print_insn_shmedia (memaddr, info) /* FIXME: We should also check register number constraints. */ if (op->name == NULL) { - fprintf_fn (stream, ".long 0x%08x", instruction); + fprintf_fn (stream, ".long 0x%08lx", instruction); return 4; } @@ -289,6 +275,7 @@ print_insn_shmedia (memaddr, info) case A_CREG_J: { const char *name; + r = temp & 0x3f; name = creg_name (r); @@ -325,7 +312,7 @@ print_insn_shmedia (memaddr, info) imm = temp & 0x3f; if (imm & (unsigned long) 0x20) imm |= ~(unsigned long) 0x3f; - fprintf_fn (stream, "%d", imm); + fprintf_fn (stream, "%ld", imm); break; /* A signed 6-bit number, multiplied by 32 when used. */ @@ -333,7 +320,7 @@ print_insn_shmedia (memaddr, info) imm = temp & 0x3f; if (imm & (unsigned long) 0x20) imm |= ~(unsigned long) 0x3f; - fprintf_fn (stream, "%d", imm * 32); + fprintf_fn (stream, "%ld", imm * 32); break; /* A signed 10-bit number, multiplied by 8 when used. */ @@ -358,7 +345,7 @@ print_insn_shmedia (memaddr, info) if (imm & (unsigned long) 0x200) imm |= ~(unsigned long) 0x3ff; imm <<= by_number; - fprintf_fn (stream, "%d", imm); + fprintf_fn (stream, "%ld", imm); break; /* A signed 16-bit number. */ @@ -366,7 +353,7 @@ print_insn_shmedia (memaddr, info) imm = temp & 0xffff; if (imm & (unsigned long) 0x8000) imm |= ~((unsigned long) 0xffff); - fprintf_fn (stream, "%d", imm); + fprintf_fn (stream, "%ld", imm); break; /* A PC-relative signed 16-bit number, multiplied by 4 when @@ -383,19 +370,19 @@ print_insn_shmedia (memaddr, info) /* An unsigned 5-bit number. */ case A_IMMU5: imm = temp & 0x1f; - fprintf_fn (stream, "%d", imm); + fprintf_fn (stream, "%ld", imm); break; /* An unsigned 6-bit number. */ case A_IMMU6: imm = temp & 0x3f; - fprintf_fn (stream, "%d", imm); + fprintf_fn (stream, "%ld", imm); break; /* An unsigned 16-bit number. */ case A_IMMU16: imm = temp & 0xffff; - fprintf_fn (stream, "%d", imm); + fprintf_fn (stream, "%ld", imm); break; default: @@ -457,9 +444,7 @@ print_insn_shmedia (memaddr, info) no section is available. */ static enum sh64_elf_cr_type -sh64_get_contents_type_disasm (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +sh64_get_contents_type_disasm (bfd_vma memaddr, struct disassemble_info *info) { struct sh64_disassemble_info *sh64_infop = info->private_data; @@ -513,8 +498,7 @@ sh64_get_contents_type_disasm (memaddr, /* Initialize static and dynamic disassembly state. */ static bfd_boolean -init_sh64_disasm_info (info) - struct disassemble_info *info; +init_sh64_disasm_info (struct disassemble_info *info) { struct sh64_disassemble_info *sh64_infop = calloc (sizeof (*sh64_infop), 1); @@ -538,9 +522,7 @@ init_sh64_disasm_info (info) use any of the functions further below. */ int -print_insn_sh64x_media (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_sh64x_media (bfd_vma memaddr, struct disassemble_info *info) { if (info->private_data == NULL && ! init_sh64_disasm_info (info)) return -1; @@ -556,9 +538,7 @@ print_insn_sh64x_media (memaddr, info) If we see an SHcompact instruction, return -2. */ int -print_insn_sh64 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_sh64 (bfd_vma memaddr, struct disassemble_info *info) { enum bfd_endian endian = info->endian; enum sh64_elf_cr_type cr_type; diff -uprN binutils-2.16.91.0.1/opcodes/sh-dis.c binutils-2.16.91.0.2/opcodes/sh-dis.c --- binutils-2.16.91.0.1/opcodes/sh-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/sh-dis.c 2005-07-20 12:27:29.366851099 -0700 @@ -1,5 +1,5 @@ /* Disassemble SH instructions. - Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003, 2004 + Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify @@ -14,7 +14,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include #include "sysdep.h" @@ -28,18 +29,12 @@ #define INCLUDE_SHMEDIA #endif -static void print_movxy - PARAMS ((const sh_opcode_info *, int, int, fprintf_ftype, void *)); -static void print_insn_ddt PARAMS ((int, struct disassemble_info *)); -static void print_dsp_reg PARAMS ((int, fprintf_ftype, void *)); -static void print_insn_ppi PARAMS ((int, struct disassemble_info *)); - static void -print_movxy (op, rn, rm, fprintf_fn, stream) - const sh_opcode_info *op; - int rn, rm; - fprintf_ftype fprintf_fn; - void *stream; +print_movxy (const sh_opcode_info *op, + int rn, + int rm, + fprintf_ftype fprintf_fn, + void *stream) { int n; @@ -113,9 +108,7 @@ print_movxy (op, rn, rm, fprintf_fn, str Return nonzero if a field b of a parallel processing insns follows. */ static void -print_insn_ddt (insn, info) - int insn; - struct disassemble_info *info; +print_insn_ddt (int insn, struct disassemble_info *info) { fprintf_ftype fprintf_fn = info->fprintf_func; void *stream = info->stream; @@ -202,10 +195,7 @@ print_insn_ddt (insn, info) } static void -print_dsp_reg (rm, fprintf_fn, stream) - int rm; - fprintf_ftype fprintf_fn; - void *stream; +print_dsp_reg (int rm, fprintf_ftype fprintf_fn, void *stream) { switch (rm) { @@ -246,9 +236,7 @@ print_dsp_reg (rm, fprintf_fn, stream) } static void -print_insn_ppi (field_b, info) - int field_b; - struct disassemble_info *info; +print_insn_ppi (int field_b, struct disassemble_info *info) { static char *sx_tab[] = { "x0", "x1", "a0", "a1" }; static char *sy_tab[] = { "y0", "y1", "m0", "m1" }; @@ -275,23 +263,20 @@ print_insn_ppi (field_b, info) static char *sg_tab[] = { "m0", "m1", "a0", "a1" }; if (field_b & 0x2000) - { - fprintf_fn (stream, "p%s %s,%s,%s\t", - (field_b & 0x1000) ? "add" : "sub", - sx_tab[(field_b >> 6) & 3], - sy_tab[(field_b >> 4) & 3], - du_tab[(field_b >> 0) & 3]); - } + fprintf_fn (stream, "p%s %s,%s,%s\t", + (field_b & 0x1000) ? "add" : "sub", + sx_tab[(field_b >> 6) & 3], + sy_tab[(field_b >> 4) & 3], + du_tab[(field_b >> 0) & 3]); + else if ((field_b & 0xf0) == 0x10 && info->mach != bfd_mach_sh_dsp && info->mach != bfd_mach_sh3_dsp) - { - fprintf_fn (stream, "pclr %s \t", du_tab[(field_b >> 0) & 3]); - } + fprintf_fn (stream, "pclr %s \t", du_tab[(field_b >> 0) & 3]); + else if ((field_b & 0xf3) != 0) - { - fprintf_fn (stream, ".word 0x%x\t", field_b); - } + fprintf_fn (stream, ".word 0x%x\t", field_b); + fprintf_fn (stream, "pmuls%c%s,%s,%s", field_b & 0x2000 ? ' ' : '\t', se_tab[(field_b >> 10) & 3], @@ -392,10 +377,9 @@ print_insn_ppi (field_b, info) /* FIXME mvs: movx insns print as ".word 0x%03x", insn & 0xfff (ie. the upper nibble is missing). */ + int -print_insn_sh (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_sh (bfd_vma memaddr, struct disassemble_info *info) { fprintf_ftype fprintf_fn = info->fprintf_func; void *stream = info->stream; @@ -648,7 +632,7 @@ print_insn_sh (memaddr, info) case REG_N_D: if ((nibs[n] & 1) != 0) goto fail; - /* fall through */ + /* Fall through. */ case REG_N: rn = nibs[n]; break; diff -uprN binutils-2.16.91.0.1/opcodes/sparc-dis.c binutils-2.16.91.0.2/opcodes/sparc-dis.c --- binutils-2.16.91.0.1/opcodes/sparc-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/sparc-dis.c 2005-07-20 12:27:29.386847801 -0700 @@ -1,6 +1,6 @@ /* Print SPARC instructions. Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2002, 2003, 2004 Free Software Foundation, Inc. + 2000, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -14,7 +14,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include @@ -34,7 +35,7 @@ #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0) /* The sorted opcode table. */ -static const struct sparc_opcode **sorted_opcodes; +static const sparc_opcode **sorted_opcodes; /* For faster lookup, after insns are sorted they are hashed. */ /* ??? I think there is room for even more improvement. */ @@ -46,18 +47,13 @@ static const struct sparc_opcode **sorte static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 }; #define HASH_INSN(INSN) \ ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19)) -struct opcode_hash +typedef struct sparc_opcode_hash { - struct opcode_hash *next; - const struct sparc_opcode *opcode; -}; -static struct opcode_hash *opcode_hash_table[HASH_SIZE]; + struct sparc_opcode_hash *next; + const sparc_opcode *opcode; +} sparc_opcode_hash; -static void build_hash_table - PARAMS ((const struct sparc_opcode **, struct opcode_hash **, int)); -static int is_delayed_branch PARAMS ((unsigned long)); -static int compare_opcodes PARAMS ((const PTR, const PTR)); -static int compute_arch_mask PARAMS ((unsigned long)); +static sparc_opcode_hash *opcode_hash_table[HASH_SIZE]; /* Sign-extend a value which is N bits long. */ #define SEX(value, bits) \ @@ -65,16 +61,16 @@ static int compute_arch_mask PARAMS ((un >> ((8 * sizeof (int)) - bits) ) static char *reg_names[] = -{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", - "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", - "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", - "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", +{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", + "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", + "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", + "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", - "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", - "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", + "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", + "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", /* psr, wim, tbr, fpsr, cpsr are v8 only. */ @@ -104,21 +100,21 @@ static char *v9a_asr_reg_names[] = /* Macros used to extract instruction fields. Not all fields have macros defined here, only those which are actually used. */ -#define X_RD(i) (((i) >> 25) & 0x1f) -#define X_RS1(i) (((i) >> 14) & 0x1f) -#define X_LDST_I(i) (((i) >> 13) & 1) -#define X_ASI(i) (((i) >> 5) & 0xff) -#define X_RS2(i) (((i) >> 0) & 0x1f) -#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1)) -#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n)) -#define X_DISP22(i) (((i) >> 0) & 0x3fffff) -#define X_IMM22(i) X_DISP22 (i) -#define X_DISP30(i) (((i) >> 0) & 0x3fffffff) +#define X_RD(i) (((i) >> 25) & 0x1f) +#define X_RS1(i) (((i) >> 14) & 0x1f) +#define X_LDST_I(i) (((i) >> 13) & 1) +#define X_ASI(i) (((i) >> 5) & 0xff) +#define X_RS2(i) (((i) >> 0) & 0x1f) +#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1)) +#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n)) +#define X_DISP22(i) (((i) >> 0) & 0x3fffff) +#define X_IMM22(i) X_DISP22 (i) +#define X_DISP30(i) (((i) >> 0) & 0x3fffffff) /* These are for v9. */ -#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff)) -#define X_DISP19(i) (((i) >> 0) & 0x7ffff) -#define X_MEMBAR(i) ((i) & 0x7f) +#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff)) +#define X_DISP19(i) (((i) >> 0) & 0x7ffff) +#define X_MEMBAR(i) ((i) & 0x7f) /* Here is the union which was used to extract instruction fields before the shift and mask macros were written. @@ -176,23 +172,22 @@ static char *v9a_asr_reg_names[] = unsigned int adisp30:30; #define disp30 call.adisp30 } call; - }; - - */ + }; */ /* Nonzero if INSN is the opcode for a delayed branch. */ + static int -is_delayed_branch (insn) - unsigned long insn; +is_delayed_branch (unsigned long insn) { - struct opcode_hash *op; + sparc_opcode_hash *op; for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) { - const struct sparc_opcode *opcode = op->opcode; + const sparc_opcode *opcode = op->opcode; + if ((opcode->match & insn) == opcode->match && (opcode->lose & insn) == 0) - return (opcode->flags & F_DELAYED); + return opcode->flags & F_DELAYED; } return 0; } @@ -203,6 +198,236 @@ is_delayed_branch (insn) to compare_opcodes. */ static unsigned int current_arch_mask; +/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */ + +static int +compute_arch_mask (unsigned long mach) +{ + switch (mach) + { + case 0 : + case bfd_mach_sparc : + return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8); + case bfd_mach_sparc_sparclet : + return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET); + case bfd_mach_sparc_sparclite : + case bfd_mach_sparc_sparclite_le : + /* sparclites insns are recognized by default (because that's how + they've always been treated, for better or worse). Kludge this by + indicating generic v8 is also selected. */ + return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) + | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)); + case bfd_mach_sparc_v8plus : + case bfd_mach_sparc_v9 : + return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); + case bfd_mach_sparc_v8plusa : + case bfd_mach_sparc_v9a : + return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A); + case bfd_mach_sparc_v8plusb : + case bfd_mach_sparc_v9b : + return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B); + } + abort (); +} + +/* Compare opcodes A and B. */ + +static int +compare_opcodes (const void * a, const void * b) +{ + sparc_opcode *op0 = * (sparc_opcode **) a; + sparc_opcode *op1 = * (sparc_opcode **) b; + unsigned long int match0 = op0->match, match1 = op1->match; + unsigned long int lose0 = op0->lose, lose1 = op1->lose; + register unsigned int i; + + /* If one (and only one) insn isn't supported by the current architecture, + prefer the one that is. If neither are supported, but they're both for + the same architecture, continue processing. Otherwise (both unsupported + and for different architectures), prefer lower numbered arch's (fudged + by comparing the bitmasks). */ + if (op0->architecture & current_arch_mask) + { + if (! (op1->architecture & current_arch_mask)) + return -1; + } + else + { + if (op1->architecture & current_arch_mask) + return 1; + else if (op0->architecture != op1->architecture) + return op0->architecture - op1->architecture; + } + + /* If a bit is set in both match and lose, there is something + wrong with the opcode table. */ + if (match0 & lose0) + { + fprintf + (stderr, + /* xgettext:c-format */ + _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), + op0->name, match0, lose0); + op0->lose &= ~op0->match; + lose0 = op0->lose; + } + + if (match1 & lose1) + { + fprintf + (stderr, + /* xgettext:c-format */ + _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), + op1->name, match1, lose1); + op1->lose &= ~op1->match; + lose1 = op1->lose; + } + + /* Because the bits that are variable in one opcode are constant in + another, it is important to order the opcodes in the right order. */ + for (i = 0; i < 32; ++i) + { + unsigned long int x = 1 << i; + int x0 = (match0 & x) != 0; + int x1 = (match1 & x) != 0; + + if (x0 != x1) + return x1 - x0; + } + + for (i = 0; i < 32; ++i) + { + unsigned long int x = 1 << i; + int x0 = (lose0 & x) != 0; + int x1 = (lose1 & x) != 0; + + if (x0 != x1) + return x1 - x0; + } + + /* They are functionally equal. So as long as the opcode table is + valid, we can put whichever one first we want, on aesthetic grounds. */ + + /* Our first aesthetic ground is that aliases defer to real insns. */ + { + int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS); + + if (alias_diff != 0) + /* Put the one that isn't an alias first. */ + return alias_diff; + } + + /* Except for aliases, two "identical" instructions had + better have the same opcode. This is a sanity check on the table. */ + i = strcmp (op0->name, op1->name); + if (i) + { + if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */ + return i; + else + fprintf (stderr, + /* xgettext:c-format */ + _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"), + op0->name, op1->name); + } + + /* Fewer arguments are preferred. */ + { + int length_diff = strlen (op0->args) - strlen (op1->args); + + if (length_diff != 0) + /* Put the one with fewer arguments first. */ + return length_diff; + } + + /* Put 1+i before i+1. */ + { + char *p0 = (char *) strchr (op0->args, '+'); + char *p1 = (char *) strchr (op1->args, '+'); + + if (p0 && p1) + { + /* There is a plus in both operands. Note that a plus + sign cannot be the first character in args, + so the following [-1]'s are valid. */ + if (p0[-1] == 'i' && p1[1] == 'i') + /* op0 is i+1 and op1 is 1+i, so op1 goes first. */ + return 1; + if (p0[1] == 'i' && p1[-1] == 'i') + /* op0 is 1+i and op1 is i+1, so op0 goes first. */ + return -1; + } + } + + /* Put 1,i before i,1. */ + { + int i0 = strncmp (op0->args, "i,1", 3) == 0; + int i1 = strncmp (op1->args, "i,1", 3) == 0; + + if (i0 ^ i1) + return i0 - i1; + } + + /* They are, as far as we can tell, identical. + Since qsort may have rearranged the table partially, there is + no way to tell which one was first in the opcode table as + written, so just say there are equal. */ + /* ??? This is no longer true now that we sort a vector of pointers, + not the table itself. */ + return 0; +} + +/* Build a hash table from the opcode table. + OPCODE_TABLE is a sorted list of pointers into the opcode table. */ + +static void +build_hash_table (const sparc_opcode **opcode_table, + sparc_opcode_hash **hash_table, + int num_opcodes) +{ + int i; + int hash_count[HASH_SIZE]; + static sparc_opcode_hash *hash_buf = NULL; + + /* Start at the end of the table and work backwards so that each + chain is sorted. */ + + memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0])); + memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0])); + if (hash_buf != NULL) + free (hash_buf); + hash_buf = xmalloc (sizeof (* hash_buf) * num_opcodes); + for (i = num_opcodes - 1; i >= 0; --i) + { + int hash = HASH_INSN (opcode_table[i]->match); + sparc_opcode_hash *h = &hash_buf[i]; + + h->next = hash_table[hash]; + h->opcode = opcode_table[i]; + hash_table[hash] = h; + ++hash_count[hash]; + } + +#if 0 /* for debugging */ + { + int min_count = num_opcodes, max_count = 0; + int total; + + for (i = 0; i < HASH_SIZE; ++i) + { + if (hash_count[i] < min_count) + min_count = hash_count[i]; + if (hash_count[i] > max_count) + max_count = hash_count[i]; + total += hash_count[i]; + } + + printf ("Opcode hash table stats: min %d, max %d, ave %f\n", + min_count, max_count, (double) total / HASH_SIZE); + } +#endif +} + /* Print one instruction from MEMADDR on INFO->STREAM. We suffix the instruction with a comment that gives the absolute @@ -212,14 +437,12 @@ static unsigned int current_arch_mask; on that register. */ int -print_insn_sparc (memaddr, info) - bfd_vma memaddr; - disassemble_info *info; +print_insn_sparc (bfd_vma memaddr, disassemble_info *info) { FILE *stream = info->stream; bfd_byte buffer[4]; unsigned long insn; - register struct opcode_hash *op; + sparc_opcode_hash *op; /* Nonzero of opcode table has been initialized. */ static int opcodes_initialized = 0; /* bfd mach number of last call. */ @@ -234,8 +457,8 @@ print_insn_sparc (memaddr, info) current_arch_mask = compute_arch_mask (info->mach); if (!opcodes_initialized) - sorted_opcodes = (const struct sparc_opcode **) - xmalloc (sparc_num_opcodes * sizeof (struct sparc_opcode *)); + sorted_opcodes = + xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *)); /* Reset the sorted table so we can resort it. */ for (i = 0; i < sparc_num_opcodes; ++i) sorted_opcodes[i] = &sparc_opcodes[i]; @@ -250,6 +473,7 @@ print_insn_sparc (memaddr, info) { int status = (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); + if (status != 0) { (*info->memory_error_func) (status, memaddr, info); @@ -273,7 +497,7 @@ print_insn_sparc (memaddr, info) for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) { - const struct sparc_opcode *opcode = op->opcode; + const sparc_opcode *opcode = op->opcode; /* If the insn isn't supported by the current architecture, skip it. */ if (! (opcode->architecture & current_arch_mask)) @@ -290,7 +514,7 @@ print_insn_sparc (memaddr, info) /* Nonzero means that we have found a plus sign in the args field of the opcode table. */ int found_plus = 0; - + /* Nonzero means we have an annulled branch. */ int is_annulled = 0; @@ -313,7 +537,7 @@ print_insn_sparc (memaddr, info) (*info->fprintf_func) (stream, opcode->name); { - register const char *s; + const char *s; if (opcode->args[0] != ',') (*info->fprintf_func) (stream, " "); @@ -347,13 +571,13 @@ print_insn_sparc (memaddr, info) } (*info->fprintf_func) (stream, " "); - + switch (*s) { case '+': found_plus = 1; + /* Fall through. */ - /* note fall-through */ default: (*info->fprintf_func) (stream, "%c", *s); break; @@ -383,24 +607,24 @@ print_insn_sparc (memaddr, info) case 'e': freg (X_RS1 (insn)); break; - case 'v': /* double/even */ - case 'V': /* quad/multiple of 4 */ + case 'v': /* Double/even. */ + case 'V': /* Quad/multiple of 4. */ fregx (X_RS1 (insn)); break; case 'f': freg (X_RS2 (insn)); break; - case 'B': /* double/even */ - case 'R': /* quad/multiple of 4 */ + case 'B': /* Double/even. */ + case 'R': /* Quad/multiple of 4. */ fregx (X_RS2 (insn)); break; case 'g': freg (X_RD (insn)); break; - case 'H': /* double/even */ - case 'J': /* quad/multiple of 4 */ + case 'H': /* Double/even. */ + case 'J': /* Quad/multiple of 4. */ fregx (X_RD (insn)); break; #undef freg @@ -426,9 +650,9 @@ print_insn_sparc (memaddr, info) & ((int) X_IMM22 (insn) << 10))); break; - case 'i': /* 13 bit immediate */ - case 'I': /* 11 bit immediate */ - case 'j': /* 10 bit immediate */ + case 'i': /* 13 bit immediate. */ + case 'I': /* 11 bit immediate. */ + case 'j': /* 10 bit immediate. */ { int imm; @@ -448,7 +672,7 @@ print_insn_sparc (memaddr, info) not before it. */ if (found_plus) imm_added_to_rs1 = 1; - + if (imm <= 9) (*info->fprintf_func) (stream, "%d", imm); else @@ -456,8 +680,8 @@ print_insn_sparc (memaddr, info) } break; - case 'X': /* 5 bit unsigned immediate */ - case 'Y': /* 6 bit unsigned immediate */ + case 'X': /* 5 bit unsigned immediate. */ + case 'Y': /* 6 bit unsigned immediate. */ { int imm = X_IMM (insn, *s == 'X' ? 5 : 6); @@ -469,7 +693,7 @@ print_insn_sparc (memaddr, info) break; case '3': - (info->fprintf_func) (stream, "%d", X_IMM (insn, 3)); + (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3)); break; case 'K': @@ -532,7 +756,7 @@ print_insn_sparc (memaddr, info) case 'o': (*info->fprintf_func) (stream, "%%asi"); break; - + case 'W': (*info->fprintf_func) (stream, "%%tick"); break; @@ -582,18 +806,18 @@ print_insn_sparc (memaddr, info) if (name) (*info->fprintf_func) (stream, "%s", name); else - (*info->fprintf_func) (stream, "%d", X_RD (insn)); + (*info->fprintf_func) (stream, "%ld", X_RD (insn)); break; } - + case 'M': - (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn)); + (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn)); break; - + case 'm': - (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn)); + (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn)); break; - + case 'L': info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4; (*info->print_address_func) (info->target, info); @@ -616,7 +840,7 @@ print_insn_sparc (memaddr, info) if (name) (*info->fprintf_func) (stream, "%s", name); else - (*info->fprintf_func) (stream, "(%d)", X_ASI (insn)); + (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn)); break; } @@ -649,7 +873,7 @@ print_insn_sparc (memaddr, info) break; case 'x': - (*info->fprintf_func) (stream, "%d", + (*info->fprintf_func) (stream, "%ld", ((X_LDST_I (insn) << 8) + X_ASI (insn))); break; @@ -725,7 +949,7 @@ print_insn_sparc (memaddr, info) && X_RD (prev_insn) == X_RS1 (insn)) { (*info->fprintf_func) (stream, "\t! "); - info->target = + info->target = ((unsigned) 0xFFFFFFFF & ((int) X_IMM22 (prev_insn) << 10)); if (imm_added_to_rs1) @@ -741,7 +965,7 @@ print_insn_sparc (memaddr, info) if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR)) { - /* FIXME -- check is_annulled flag */ + /* FIXME -- check is_annulled flag. */ if (opcode->flags & F_UNBR) info->insn_type = dis_branch; if (opcode->flags & F_CONDBR) @@ -760,234 +984,3 @@ print_insn_sparc (memaddr, info) (*info->fprintf_func) (stream, _("unknown")); return sizeof (buffer); } - -/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */ - -static int -compute_arch_mask (mach) - unsigned long mach; -{ - switch (mach) - { - case 0 : - case bfd_mach_sparc : - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8); - case bfd_mach_sparc_sparclet : - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET); - case bfd_mach_sparc_sparclite : - case bfd_mach_sparc_sparclite_le : - /* sparclites insns are recognized by default (because that's how - they've always been treated, for better or worse). Kludge this by - indicating generic v8 is also selected. */ - return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) - | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)); - case bfd_mach_sparc_v8plus : - case bfd_mach_sparc_v9 : - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); - case bfd_mach_sparc_v8plusa : - case bfd_mach_sparc_v9a : - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A); - case bfd_mach_sparc_v8plusb : - case bfd_mach_sparc_v9b : - return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B); - } - abort (); -} - -/* Compare opcodes A and B. */ - -static int -compare_opcodes (a, b) - const PTR a; - const PTR b; -{ - struct sparc_opcode *op0 = * (struct sparc_opcode **) a; - struct sparc_opcode *op1 = * (struct sparc_opcode **) b; - unsigned long int match0 = op0->match, match1 = op1->match; - unsigned long int lose0 = op0->lose, lose1 = op1->lose; - register unsigned int i; - - /* If one (and only one) insn isn't supported by the current architecture, - prefer the one that is. If neither are supported, but they're both for - the same architecture, continue processing. Otherwise (both unsupported - and for different architectures), prefer lower numbered arch's (fudged - by comparing the bitmasks). */ - if (op0->architecture & current_arch_mask) - { - if (! (op1->architecture & current_arch_mask)) - return -1; - } - else - { - if (op1->architecture & current_arch_mask) - return 1; - else if (op0->architecture != op1->architecture) - return op0->architecture - op1->architecture; - } - - /* If a bit is set in both match and lose, there is something - wrong with the opcode table. */ - if (match0 & lose0) - { - fprintf - (stderr, - /* xgettext:c-format */ - _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), - op0->name, match0, lose0); - op0->lose &= ~op0->match; - lose0 = op0->lose; - } - - if (match1 & lose1) - { - fprintf - (stderr, - /* xgettext:c-format */ - _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), - op1->name, match1, lose1); - op1->lose &= ~op1->match; - lose1 = op1->lose; - } - - /* Because the bits that are variable in one opcode are constant in - another, it is important to order the opcodes in the right order. */ - for (i = 0; i < 32; ++i) - { - unsigned long int x = 1 << i; - int x0 = (match0 & x) != 0; - int x1 = (match1 & x) != 0; - - if (x0 != x1) - return x1 - x0; - } - - for (i = 0; i < 32; ++i) - { - unsigned long int x = 1 << i; - int x0 = (lose0 & x) != 0; - int x1 = (lose1 & x) != 0; - - if (x0 != x1) - return x1 - x0; - } - - /* They are functionally equal. So as long as the opcode table is - valid, we can put whichever one first we want, on aesthetic grounds. */ - - /* Our first aesthetic ground is that aliases defer to real insns. */ - { - int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS); - if (alias_diff != 0) - /* Put the one that isn't an alias first. */ - return alias_diff; - } - - /* Except for aliases, two "identical" instructions had - better have the same opcode. This is a sanity check on the table. */ - i = strcmp (op0->name, op1->name); - if (i) - { - if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */ - return i; - else - fprintf (stderr, - /* xgettext:c-format */ - _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"), - op0->name, op1->name); - } - - /* Fewer arguments are preferred. */ - { - int length_diff = strlen (op0->args) - strlen (op1->args); - if (length_diff != 0) - /* Put the one with fewer arguments first. */ - return length_diff; - } - - /* Put 1+i before i+1. */ - { - char *p0 = (char *) strchr (op0->args, '+'); - char *p1 = (char *) strchr (op1->args, '+'); - - if (p0 && p1) - { - /* There is a plus in both operands. Note that a plus - sign cannot be the first character in args, - so the following [-1]'s are valid. */ - if (p0[-1] == 'i' && p1[1] == 'i') - /* op0 is i+1 and op1 is 1+i, so op1 goes first. */ - return 1; - if (p0[1] == 'i' && p1[-1] == 'i') - /* op0 is 1+i and op1 is i+1, so op0 goes first. */ - return -1; - } - } - - /* Put 1,i before i,1. */ - { - int i0 = strncmp (op0->args, "i,1", 3) == 0; - int i1 = strncmp (op1->args, "i,1", 3) == 0; - - if (i0 ^ i1) - return i0 - i1; - } - - /* They are, as far as we can tell, identical. - Since qsort may have rearranged the table partially, there is - no way to tell which one was first in the opcode table as - written, so just say there are equal. */ - /* ??? This is no longer true now that we sort a vector of pointers, - not the table itself. */ - return 0; -} - -/* Build a hash table from the opcode table. - OPCODE_TABLE is a sorted list of pointers into the opcode table. */ - -static void -build_hash_table (opcode_table, hash_table, num_opcodes) - const struct sparc_opcode **opcode_table; - struct opcode_hash **hash_table; - int num_opcodes; -{ - register int i; - int hash_count[HASH_SIZE]; - static struct opcode_hash *hash_buf = NULL; - - /* Start at the end of the table and work backwards so that each - chain is sorted. */ - - memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0])); - memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0])); - if (hash_buf != NULL) - free (hash_buf); - hash_buf = (struct opcode_hash *) xmalloc (sizeof (struct opcode_hash) * num_opcodes); - for (i = num_opcodes - 1; i >= 0; --i) - { - register int hash = HASH_INSN (opcode_table[i]->match); - register struct opcode_hash *h = &hash_buf[i]; - h->next = hash_table[hash]; - h->opcode = opcode_table[i]; - hash_table[hash] = h; - ++hash_count[hash]; - } - -#if 0 /* for debugging */ - { - int min_count = num_opcodes, max_count = 0; - int total; - - for (i = 0; i < HASH_SIZE; ++i) - { - if (hash_count[i] < min_count) - min_count = hash_count[i]; - if (hash_count[i] > max_count) - max_count = hash_count[i]; - total += hash_count[i]; - } - - printf ("Opcode hash table stats: min %d, max %d, ave %f\n", - min_count, max_count, (double) total / HASH_SIZE); - } -#endif -} diff -uprN binutils-2.16.91.0.1/opcodes/sparc-opc.c binutils-2.16.91.0.2/opcodes/sparc-opc.c --- binutils-2.16.91.0.1/opcodes/sparc-opc.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/sparc-opc.c 2005-07-20 12:27:29.390847142 -0700 @@ -1,24 +1,24 @@ /* Table of opcodes for the sparc. Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2002, 2004 + 2000, 2002, 2004, 2005 Free Software Foundation, Inc. -This file is part of the BFD library. + This file is part of the BFD library. -BFD is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 2, or (at your option) any later -version. - -BFD is distributed in the hope that it will be useful, but WITHOUT ANY -WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -for more details. - -You should have received a copy of the GNU General Public License -along with this software; see the file COPYING. If not, write to -the Free Software Foundation, 51 Franklin Street - Fifth Floor, -Boston, MA 02110-1301, USA. */ + BFD is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2, or (at your option) any later + version. + + BFD is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + for more details. + + You should have received a copy of the GNU General Public License + along with this software; see the file COPYING. If not, write to + the Free Software Foundation, 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ /* FIXME-someday: perhaps the ,a's and such should be embedded in the instruction's name rather than the args. This would make gas faster, pinsn @@ -42,7 +42,7 @@ Boston, MA 02110-1301, USA. */ #define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \ | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) -/* v6 insns not supported on the sparclet */ +/* v6 insns not supported on the sparclet. */ #define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \ | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) #define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \ @@ -60,17 +60,18 @@ Boston, MA 02110-1301, USA. */ #define v9 (MASK_V9 | MASK_V9A | MASK_V9B) #define v9a (MASK_V9A | MASK_V9B) #define v9b (MASK_V9B) -/* v6 insns not supported by v9 */ +/* v6 insns not supported by v9. */ #define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \ | MASK_SPARCLET | MASK_SPARCLITE) /* v9a instructions which would appear to be aliases to v9's impdep's - otherwise */ + otherwise. */ #define v9notv9a (MASK_V9) /* Table of opcode architectures. The order is defined in opcode/sparc.h. */ -const struct sparc_opcode_arch sparc_opcode_archs[] = { +const struct sparc_opcode_arch sparc_opcode_archs[] = +{ { "v6", MASK_V6 }, { "v7", MASK_V6 | MASK_V7 }, { "v8", MASK_V6 | MASK_V7 | MASK_V8 }, @@ -88,84 +89,79 @@ const struct sparc_opcode_arch sparc_opc /* Given NAME, return it's architecture entry. */ enum sparc_opcode_arch_val -sparc_opcode_lookup_arch (name) - const char *name; +sparc_opcode_lookup_arch (const char *name) { const struct sparc_opcode_arch *p; for (p = &sparc_opcode_archs[0]; p->name; ++p) - { - if (strcmp (name, p->name) == 0) - return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]); - } + if (strcmp (name, p->name) == 0) + return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]); return SPARC_OPCODE_ARCH_BAD; } /* Branch condition field. */ -#define COND(x) (((x)&0xf)<<25) +#define COND(x) (((x) & 0xf) << 25) /* v9: Move (MOVcc and FMOVcc) condition field. */ -#define MCOND(x,i_or_f) ((((i_or_f)&1)<<18)|(((x)>>11)&(0xf<<14))) /* v9 */ +#define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */ /* v9: Move register (MOVRcc and FMOVRcc) condition field. */ -#define RCOND(x) (((x)&0x7)<<10) /* v9 */ +#define RCOND(x) (((x) & 0x7) << 10) /* v9 */ -#define CONDA (COND(0x8)) -#define CONDCC (COND(0xd)) -#define CONDCS (COND(0x5)) -#define CONDE (COND(0x1)) -#define CONDG (COND(0xa)) -#define CONDGE (COND(0xb)) -#define CONDGU (COND(0xc)) -#define CONDL (COND(0x3)) -#define CONDLE (COND(0x2)) -#define CONDLEU (COND(0x4)) -#define CONDN (COND(0x0)) -#define CONDNE (COND(0x9)) -#define CONDNEG (COND(0x6)) -#define CONDPOS (COND(0xe)) -#define CONDVC (COND(0xf)) -#define CONDVS (COND(0x7)) +#define CONDA (COND (0x8)) +#define CONDCC (COND (0xd)) +#define CONDCS (COND (0x5)) +#define CONDE (COND (0x1)) +#define CONDG (COND (0xa)) +#define CONDGE (COND (0xb)) +#define CONDGU (COND (0xc)) +#define CONDL (COND (0x3)) +#define CONDLE (COND (0x2)) +#define CONDLEU (COND (0x4)) +#define CONDN (COND (0x0)) +#define CONDNE (COND (0x9)) +#define CONDNEG (COND (0x6)) +#define CONDPOS (COND (0xe)) +#define CONDVC (COND (0xf)) +#define CONDVS (COND (0x7)) #define CONDNZ CONDNE #define CONDZ CONDE #define CONDGEU CONDCC #define CONDLU CONDCS -#define FCONDA (COND(0x8)) -#define FCONDE (COND(0x9)) -#define FCONDG (COND(0x6)) -#define FCONDGE (COND(0xb)) -#define FCONDL (COND(0x4)) -#define FCONDLE (COND(0xd)) -#define FCONDLG (COND(0x2)) -#define FCONDN (COND(0x0)) -#define FCONDNE (COND(0x1)) -#define FCONDO (COND(0xf)) -#define FCONDU (COND(0x7)) -#define FCONDUE (COND(0xa)) -#define FCONDUG (COND(0x5)) -#define FCONDUGE (COND(0xc)) -#define FCONDUL (COND(0x3)) -#define FCONDULE (COND(0xe)) +#define FCONDA (COND (0x8)) +#define FCONDE (COND (0x9)) +#define FCONDG (COND (0x6)) +#define FCONDGE (COND (0xb)) +#define FCONDL (COND (0x4)) +#define FCONDLE (COND (0xd)) +#define FCONDLG (COND (0x2)) +#define FCONDN (COND (0x0)) +#define FCONDNE (COND (0x1)) +#define FCONDO (COND (0xf)) +#define FCONDU (COND (0x7)) +#define FCONDUE (COND (0xa)) +#define FCONDUG (COND (0x5)) +#define FCONDUGE (COND (0xc)) +#define FCONDUL (COND (0x3)) +#define FCONDULE (COND (0xe)) #define FCONDNZ FCONDNE #define FCONDZ FCONDE -#define ICC (0) /* v9 */ -#define XCC (1<<12) /* v9 */ -#define FCC(x) (((x)&0x3)<<11) /* v9 */ -#define FBFCC(x) (((x)&0x3)<<20) /* v9 */ +#define ICC (0) /* v9 */ +#define XCC (1 << 12) /* v9 */ +#define FCC(x) (((x) & 0x3) << 11) /* v9 */ +#define FBFCC(x) (((x) & 0x3) << 20) /* v9 */ /* The order of the opcodes in the table is significant: - + * The assembler requires that all instances of the same mnemonic must be consecutive. If they aren't, the assembler will bomb at runtime. - * The disassembler should not care about the order of the opcodes. - -*/ + * The disassembler should not care about the order of the opcodes. */ /* Entries for commutative arithmetic operations. */ /* ??? More entries can make use of this. */ @@ -1348,13 +1344,13 @@ fmovccx("fmovs" suffix, FM_SF, "f,g", co /* Coprocessor branches. */ #define CBR(opcode, mask, lose, flags, arch) \ - { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED, arch }, \ - { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED, arch } + { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED, arch }, \ + { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, arch } /* Floating point branches. */ #define FBR(opcode, mask, lose, flags) \ - { opcode, (mask), ANNUL|(lose), "l", flags|F_DELAYED|F_FBR, v6 }, \ - { opcode, (mask)|ANNUL, (lose), ",a l", flags|F_DELAYED|F_FBR, v6 } + { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED | F_FBR, v6 }, \ + { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, v6 } /* V9 extended floating point branches. */ #define FBRX(opcode, mask, lose, flags) /* v9 */ \ @@ -1829,13 +1825,8 @@ typedef struct /* Look up NAME in TABLE. */ -static int lookup_name PARAMS ((const arg *, const char *)); -static const char *lookup_value PARAMS ((const arg *, int)); - static int -lookup_name (table, name) - const arg *table; - const char *name; +lookup_name (const arg *table, const char *name) { const arg *p; @@ -1849,9 +1840,7 @@ lookup_name (table, name) /* Look up VALUE in TABLE. */ static const char * -lookup_value (table, value) - const arg *table; - int value; +lookup_value (const arg *table, int value) { const arg *p; @@ -1859,7 +1848,7 @@ lookup_value (table, value) if (value == p->value) return p->name; - return (char *) 0; + return NULL; } /* Handle ASI's. */ @@ -1907,8 +1896,7 @@ static arg asi_table[] = /* Return the value for ASI NAME, or -1 if not found. */ int -sparc_encode_asi (name) - const char *name; +sparc_encode_asi (const char *name) { return lookup_name (asi_table, name); } @@ -1916,8 +1904,7 @@ sparc_encode_asi (name) /* Return the name for ASI value VALUE or NULL if not found. */ const char * -sparc_decode_asi (value) - int value; +sparc_decode_asi (int value) { return lookup_value (asi_table, value); } @@ -1939,8 +1926,7 @@ static arg membar_table[] = /* Return the value for membar arg NAME, or -1 if not found. */ int -sparc_encode_membar (name) - const char *name; +sparc_encode_membar (const char *name) { return lookup_name (membar_table, name); } @@ -1948,8 +1934,7 @@ sparc_encode_membar (name) /* Return the name for membar value VALUE or NULL if not found. */ const char * -sparc_decode_membar (value) - int value; +sparc_decode_membar (int value) { return lookup_value (membar_table, value); } @@ -1970,8 +1955,7 @@ static arg prefetch_table[] = /* Return the value for prefetch arg NAME, or -1 if not found. */ int -sparc_encode_prefetch (name) - const char *name; +sparc_encode_prefetch (const char *name) { return lookup_name (prefetch_table, name); } @@ -1979,8 +1963,7 @@ sparc_encode_prefetch (name) /* Return the name for prefetch value VALUE or NULL if not found. */ const char * -sparc_decode_prefetch (value) - int value; +sparc_decode_prefetch (int value) { return lookup_value (prefetch_table, value); } @@ -2002,8 +1985,7 @@ static arg sparclet_cpreg_table[] = /* Return the value for sparclet cpreg arg NAME, or -1 if not found. */ int -sparc_encode_sparclet_cpreg (name) - const char *name; +sparc_encode_sparclet_cpreg (const char *name) { return lookup_name (sparclet_cpreg_table, name); } @@ -2011,8 +1993,7 @@ sparc_encode_sparclet_cpreg (name) /* Return the name for sparclet cpreg value VALUE or NULL if not found. */ const char * -sparc_decode_sparclet_cpreg (value) - int value; +sparc_decode_sparclet_cpreg (int value) { return lookup_value (sparclet_cpreg_table, value); } diff -uprN binutils-2.16.91.0.1/opcodes/sysdep.h binutils-2.16.91.0.2/opcodes/sysdep.h --- binutils-2.16.91.0.1/opcodes/sysdep.h 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/sysdep.h 2005-07-20 12:27:29.391846977 -0700 @@ -2,21 +2,22 @@ Copyright 1995, 1997, 2000 Free Software Foundation, Inc. Written by Ken Raeburn. -This file is part of libopcodes, the opcodes library. + This file is part of libopcodes, the opcodes library. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ /* Do system-dependent stuff, mainly driven by autoconf-detected info. diff -uprN binutils-2.16.91.0.1/opcodes/tic30-dis.c binutils-2.16.91.0.2/opcodes/tic30-dis.c --- binutils-2.16.91.0.1/opcodes/tic30-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/tic30-dis.c 2005-07-20 12:27:29.393846647 -0700 @@ -1,5 +1,5 @@ /* Disassembly routines for TMS320C30 architecture - Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc. + Copyright 1998, 1999, 2000, 2002, 2005 Free Software Foundation, Inc. Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) This program is free software; you can redistribute it and/or modify @@ -66,63 +66,8 @@ struct instruction partemplate *ptm; }; -int get_tic30_instruction PARAMS ((unsigned long, struct instruction *)); -int print_two_operand - PARAMS ((disassemble_info *, unsigned long, struct instruction *)); -int print_three_operand - PARAMS ((disassemble_info *, unsigned long, struct instruction *)); -int print_par_insn - PARAMS ((disassemble_info *, unsigned long, struct instruction *)); -int print_branch - PARAMS ((disassemble_info *, unsigned long, struct instruction *)); -int get_indirect_operand PARAMS ((unsigned short, int, char *)); -int get_register_operand PARAMS ((unsigned char, char *)); -int cnvt_tmsfloat_ieee PARAMS ((unsigned long, int, float *)); - -int -print_insn_tic30 (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - unsigned long insn_word; - struct instruction insn = { 0, NULL, NULL }; - bfd_vma bufaddr = pc - info->buffer_vma; - /* Obtain the current instruction word from the buffer. */ - insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) | - (*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3); - _pc = pc / 4; - /* Get the instruction refered to by the current instruction word - and print it out based on its type. */ - if (!get_tic30_instruction (insn_word, &insn)) - return -1; - switch (GET_TYPE (insn_word)) - { - case TWO_OPERAND_1: - case TWO_OPERAND_2: - if (!print_two_operand (info, insn_word, &insn)) - return -1; - break; - case THREE_OPERAND: - if (!print_three_operand (info, insn_word, &insn)) - return -1; - break; - case PAR_STORE: - case MUL_ADDS: - if (!print_par_insn (info, insn_word, &insn)) - return -1; - break; - case BRANCHES: - if (!print_branch (info, insn_word, &insn)) - return -1; - break; - } - return 4; -} - -int -get_tic30_instruction (insn_word, insn) - unsigned long insn_word; - struct instruction *insn; +static int +get_tic30_instruction (unsigned long insn_word, struct instruction *insn) { switch (GET_TYPE (insn_word)) { @@ -132,6 +77,7 @@ get_tic30_instruction (insn_word, insn) insn->type = NORMAL_INSN; { template *current_optab = (template *) tic30_optab; + for (; current_optab < tic30_optab_end; current_optab++) { if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) @@ -153,15 +99,18 @@ get_tic30_instruction (insn_word, insn) } } break; + case PAR_STORE: insn->type = PARALLEL_INSN; { partemplate *current_optab = (partemplate *) tic30_paroptab; + for (; current_optab < tic30_paroptab_end; current_optab++) { if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) { - if ((current_optab->base_opcode & PAR_STORE_IDEN) == (insn_word & PAR_STORE_IDEN)) + if ((current_optab->base_opcode & PAR_STORE_IDEN) + == (insn_word & PAR_STORE_IDEN)) { insn->ptm = current_optab; break; @@ -170,15 +119,18 @@ get_tic30_instruction (insn_word, insn) } } break; + case MUL_ADDS: insn->type = PARALLEL_INSN; { partemplate *current_optab = (partemplate *) tic30_paroptab; + for (; current_optab < tic30_paroptab_end; current_optab++) { if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) { - if ((current_optab->base_opcode & MUL_ADD_IDEN) == (insn_word & MUL_ADD_IDEN)) + if ((current_optab->base_opcode & MUL_ADD_IDEN) + == (insn_word & MUL_ADD_IDEN)) { insn->ptm = current_optab; break; @@ -187,17 +139,20 @@ get_tic30_instruction (insn_word, insn) } } break; + case BRANCHES: insn->type = NORMAL_INSN; { template *current_optab = (template *) tic30_optab; + for (; current_optab < tic30_optab_end; current_optab++) { if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) { if (current_optab->operand_types[0] & Imm24) { - if ((current_optab->base_opcode & BR_IMM_IDEN) == (insn_word & BR_IMM_IDEN)) + if ((current_optab->base_opcode & BR_IMM_IDEN) + == (insn_word & BR_IMM_IDEN)) { insn->tm = current_optab; break; @@ -205,7 +160,8 @@ get_tic30_instruction (insn_word, insn) } else if (current_optab->operands > 0) { - if ((current_optab->base_opcode & BR_COND_IDEN) == (insn_word & BR_COND_IDEN)) + if ((current_optab->base_opcode & BR_COND_IDEN) + == (insn_word & BR_COND_IDEN)) { insn->tm = current_optab; break; @@ -213,7 +169,8 @@ get_tic30_instruction (insn_word, insn) } else { - if ((current_optab->base_opcode & (BR_COND_IDEN | 0x00800000)) == (insn_word & (BR_COND_IDEN | 0x00800000))) + if ((current_optab->base_opcode & (BR_COND_IDEN | 0x00800000)) + == (insn_word & (BR_COND_IDEN | 0x00800000))) { insn->tm = current_optab; break; @@ -229,17 +186,163 @@ get_tic30_instruction (insn_word, insn) return 1; } -int -print_two_operand (info, insn_word, insn) - disassemble_info *info; - unsigned long insn_word; - struct instruction *insn; +static int +get_register_operand (unsigned char fragment, char *buffer) +{ + const reg *current_reg = tic30_regtab; + + if (buffer == NULL) + return 0; + for (; current_reg < tic30_regtab_end; current_reg++) + { + if ((fragment & 0x1F) == current_reg->opcode) + { + strcpy (buffer, current_reg->name); + return 1; + } + } + return 0; +} + +static int +get_indirect_operand (unsigned short fragment, + int size, + char *buffer) +{ + unsigned char mod; + unsigned arnum; + unsigned char disp; + + if (buffer == NULL) + return 0; + /* Determine which bits identify the sections of the indirect + operand based on the size in bytes. */ + switch (size) + { + case 1: + mod = (fragment & 0x00F8) >> 3; + arnum = (fragment & 0x0007); + disp = 0; + break; + case 2: + mod = (fragment & 0xF800) >> 11; + arnum = (fragment & 0x0700) >> 8; + disp = (fragment & 0x00FF); + break; + default: + return 0; + } + { + const ind_addr_type *current_ind = tic30_indaddr_tab; + + for (; current_ind < tic30_indaddrtab_end; current_ind++) + { + if (current_ind->modfield == mod) + { + if (current_ind->displacement == IMPLIED_DISP && size == 2) + continue; + + else + { + size_t i, len; + int bufcnt; + + len = strlen (current_ind->syntax); + for (i = 0, bufcnt = 0; i < len; i++, bufcnt++) + { + buffer[bufcnt] = current_ind->syntax[i]; + if (buffer[bufcnt - 1] == 'a' && buffer[bufcnt] == 'r') + buffer[++bufcnt] = arnum + '0'; + if (buffer[bufcnt] == '(' + && current_ind->displacement == DISP_REQUIRED) + { + sprintf (&buffer[bufcnt + 1], "%u", disp); + bufcnt += strlen (&buffer[bufcnt + 1]); + } + } + buffer[bufcnt + 1] = '\0'; + break; + } + } + } + } + return 1; +} + +static int +cnvt_tmsfloat_ieee (unsigned long tmsfloat, int size, float *ieeefloat) +{ + unsigned long exp, sign, mant; + union + { + unsigned long l; + float f; + } val; + + if (size == 2) + { + if ((tmsfloat & 0x0000F000) == 0x00008000) + tmsfloat = 0x80000000; + else + { + tmsfloat <<= 16; + tmsfloat = (long) tmsfloat >> 4; + } + } + exp = tmsfloat & 0xFF000000; + if (exp == 0x80000000) + { + *ieeefloat = 0.0; + return 1; + } + exp += 0x7F000000; + sign = (tmsfloat & 0x00800000) << 8; + mant = tmsfloat & 0x007FFFFF; + if (exp == 0xFF000000) + { + if (mant == 0) + *ieeefloat = ERANGE; +#ifdef HUGE_VALF + if (sign == 0) + *ieeefloat = HUGE_VALF; + else + *ieeefloat = -HUGE_VALF; +#else + if (sign == 0) + *ieeefloat = 1.0 / 0.0; + else + *ieeefloat = -1.0 / 0.0; +#endif + return 1; + } + exp >>= 1; + if (sign) + { + mant = (~mant) & 0x007FFFFF; + mant += 1; + exp += mant & 0x00800000; + exp &= 0x7F800000; + mant &= 0x007FFFFF; + } + if (tmsfloat == 0x80000000) + sign = mant = exp = 0; + tmsfloat = sign | exp | mant; + val.l = tmsfloat; + *ieeefloat = val.f; + return 1; +} + +static int +print_two_operand (disassemble_info *info, + unsigned long insn_word, + struct instruction *insn) { char name[12]; char operand[2][13] = { {0}, - {0}}; + {0} + }; float f_number; if (insn->tm == NULL) @@ -249,7 +352,8 @@ print_two_operand (info, insn_word, insn { int src_op, dest_op; /* Determine whether instruction is a store or a normal instruction. */ - if ((insn->tm->operand_types[1] & (Direct | Indirect)) == (Direct | Indirect)) + if ((insn->tm->operand_types[1] & (Direct | Indirect)) + == (Direct | Indirect)) { src_op = 1; dest_op = 0; @@ -306,9 +410,7 @@ print_two_operand (info, insn_word, insn else if (insn->tm->operands == 1) { if (insn->tm->opcode_modifier == StackOp) - { - get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]); - } + get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]); } /* Output instruction to stream. */ info->fprintf_func (info->stream, " %s %s%c%s", name, @@ -318,17 +420,17 @@ print_two_operand (info, insn_word, insn return 1; } -int -print_three_operand (info, insn_word, insn) - disassemble_info *info; - unsigned long insn_word; - struct instruction *insn; +static int +print_three_operand (disassemble_info *info, + unsigned long insn_word, + struct instruction *insn) { char operand[3][13] = { {0}, {0}, - {0}}; + {0} + }; if (insn->tm == NULL) return 0; @@ -362,11 +464,10 @@ print_three_operand (info, insn_word, in return 1; } -int -print_par_insn (info, insn_word, insn) - disassemble_info *info; - unsigned long insn_word; - struct instruction *insn; +static int +print_par_insn (disassemble_info *info, + unsigned long insn_word, + struct instruction *insn) { size_t i, len; char *name1, *name2; @@ -375,11 +476,14 @@ print_par_insn (info, insn_word, insn) { {0}, {0}, - {0}}, + {0} + }, { {0}, {0}, - {0}}}; + {0} + } + }; if (insn->ptm == NULL) return 0; @@ -484,16 +588,16 @@ print_par_insn (info, insn_word, insn) return 1; } -int -print_branch (info, insn_word, insn) - disassemble_info *info; - unsigned long insn_word; - struct instruction *insn; +static int +print_branch (disassemble_info *info, + unsigned long insn_word, + struct instruction *insn) { char operand[2][13] = { {0}, - {0}}; + {0} + }; unsigned long address; int print_label = 0; @@ -571,145 +675,40 @@ print_branch (info, insn_word, insn) } int -get_indirect_operand (fragment, size, buffer) - unsigned short fragment; - int size; - char *buffer; +print_insn_tic30 (bfd_vma pc, disassemble_info *info) { - unsigned char mod; - unsigned arnum; - unsigned char disp; + unsigned long insn_word; + struct instruction insn = { 0, NULL, NULL }; + bfd_vma bufaddr = pc - info->buffer_vma; - if (buffer == NULL) - return 0; - /* Determine which bits identify the sections of the indirect - operand based on the size in bytes. */ - switch (size) + /* Obtain the current instruction word from the buffer. */ + insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) | + (*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3); + _pc = pc / 4; + /* Get the instruction refered to by the current instruction word + and print it out based on its type. */ + if (!get_tic30_instruction (insn_word, &insn)) + return -1; + switch (GET_TYPE (insn_word)) { - case 1: - mod = (fragment & 0x00F8) >> 3; - arnum = (fragment & 0x0007); - disp = 0; + case TWO_OPERAND_1: + case TWO_OPERAND_2: + if (!print_two_operand (info, insn_word, &insn)) + return -1; break; - case 2: - mod = (fragment & 0xF800) >> 11; - arnum = (fragment & 0x0700) >> 8; - disp = (fragment & 0x00FF); + case THREE_OPERAND: + if (!print_three_operand (info, insn_word, &insn)) + return -1; + break; + case PAR_STORE: + case MUL_ADDS: + if (!print_par_insn (info, insn_word, &insn)) + return -1; + break; + case BRANCHES: + if (!print_branch (info, insn_word, &insn)) + return -1; break; - default: - return 0; - } - { - const ind_addr_type *current_ind = tic30_indaddr_tab; - for (; current_ind < tic30_indaddrtab_end; current_ind++) - { - if (current_ind->modfield == mod) - { - if (current_ind->displacement == IMPLIED_DISP && size == 2) - { - continue; - } - else - { - size_t i, len; - int bufcnt; - - len = strlen (current_ind->syntax); - for (i = 0, bufcnt = 0; i < len; i++, bufcnt++) - { - buffer[bufcnt] = current_ind->syntax[i]; - if (buffer[bufcnt - 1] == 'a' && buffer[bufcnt] == 'r') - buffer[++bufcnt] = arnum + '0'; - if (buffer[bufcnt] == '(' - && current_ind->displacement == DISP_REQUIRED) - { - sprintf (&buffer[bufcnt + 1], "%u", disp); - bufcnt += strlen (&buffer[bufcnt + 1]); - } - } - buffer[bufcnt + 1] = '\0'; - break; - } - } - } - } - return 1; -} - -int -get_register_operand (fragment, buffer) - unsigned char fragment; - char *buffer; -{ - const reg *current_reg = tic30_regtab; - - if (buffer == NULL) - return 0; - for (; current_reg < tic30_regtab_end; current_reg++) - { - if ((fragment & 0x1F) == current_reg->opcode) - { - strcpy (buffer, current_reg->name); - return 1; - } - } - return 0; -} - -int -cnvt_tmsfloat_ieee (tmsfloat, size, ieeefloat) - unsigned long tmsfloat; - int size; - float *ieeefloat; -{ - unsigned long exp, sign, mant; - union { - unsigned long l; - float f; - } val; - - if (size == 2) - { - if ((tmsfloat & 0x0000F000) == 0x00008000) - tmsfloat = 0x80000000; - else - { - tmsfloat <<= 16; - tmsfloat = (long) tmsfloat >> 4; - } - } - exp = tmsfloat & 0xFF000000; - if (exp == 0x80000000) - { - *ieeefloat = 0.0; - return 1; - } - exp += 0x7F000000; - sign = (tmsfloat & 0x00800000) << 8; - mant = tmsfloat & 0x007FFFFF; - if (exp == 0xFF000000) - { - if (mant == 0) - *ieeefloat = ERANGE; - if (sign == 0) - *ieeefloat = 1.0 / 0.0; - else - *ieeefloat = -1.0 / 0.0; - return 1; - } - exp >>= 1; - if (sign) - { - mant = (~mant) & 0x007FFFFF; - mant += 1; - exp += mant & 0x00800000; - exp &= 0x7F800000; - mant &= 0x007FFFFF; } - if (tmsfloat == 0x80000000) - sign = mant = exp = 0; - tmsfloat = sign | exp | mant; - val.l = tmsfloat; - *ieeefloat = val.f; - return 1; + return 4; } diff -uprN binutils-2.16.91.0.1/opcodes/tic4x-dis.c binutils-2.16.91.0.2/opcodes/tic4x-dis.c --- binutils-2.16.91.0.1/opcodes/tic4x-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/tic4x-dis.c 2005-07-20 12:27:29.395846318 -0700 @@ -1,9 +1,9 @@ /* Print instructions for the Texas TMS320C[34]X, for GDB and GNU Binutils. - Copyright 2002, 2003 Free Software Foundation, Inc. + Copyright 2002, 2003, 2005 Free Software Foundation, Inc. Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz) - + This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or @@ -16,7 +16,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include #include "libiberty.h" @@ -26,67 +27,32 @@ #define TIC4X_DEBUG 0 #define TIC4X_HASH_SIZE 11 /* 11 (bits) and above should give unique entries. */ -#define TIC4X_SPESOP_SIZE 8 /* Max 8. ops for special instructions */ +#define TIC4X_SPESOP_SIZE 8 /* Max 8. ops for special instructions. */ typedef enum - { - IMMED_SINT, - IMMED_SUINT, - IMMED_SFLOAT, - IMMED_INT, - IMMED_UINT, - IMMED_FLOAT - } +{ + IMMED_SINT, + IMMED_SUINT, + IMMED_SFLOAT, + IMMED_INT, + IMMED_UINT, + IMMED_FLOAT +} immed_t; typedef enum - { - INDIRECT_SHORT, - INDIRECT_LONG, - INDIRECT_TIC4X - } +{ + INDIRECT_SHORT, + INDIRECT_LONG, + INDIRECT_TIC4X +} indirect_t; static int tic4x_version = 0; static int tic4x_dp = 0; -static int tic4x_pc_offset - PARAMS ((unsigned int)); -static int tic4x_print_char - PARAMS ((struct disassemble_info *, char)); -static int tic4x_print_str - PARAMS ((struct disassemble_info *, char *)); -static int tic4x_print_register - PARAMS ((struct disassemble_info *, unsigned long)); -static int tic4x_print_addr - PARAMS ((struct disassemble_info *, unsigned long)); -static int tic4x_print_relative - PARAMS ((struct disassemble_info *, unsigned long, long, unsigned long)); -void tic4x_print_ftoa - PARAMS ((unsigned int, FILE *, fprintf_ftype)); -static int tic4x_print_direct - PARAMS ((struct disassemble_info *, unsigned long)); -static int tic4x_print_immed - PARAMS ((struct disassemble_info *, immed_t, unsigned long)); -static int tic4x_print_cond - PARAMS ((struct disassemble_info *, unsigned int)); -static int tic4x_print_indirect - PARAMS ((struct disassemble_info *, indirect_t, unsigned long)); -static int tic4x_print_op - PARAMS ((struct disassemble_info *, unsigned long, tic4x_inst_t *, unsigned long)); -static void tic4x_hash_opcode_special - PARAMS ((tic4x_inst_t **, const tic4x_inst_t *)); -static void tic4x_hash_opcode - PARAMS ((tic4x_inst_t **, tic4x_inst_t **, const tic4x_inst_t *, unsigned long)); -static int tic4x_disassemble - PARAMS ((unsigned long, unsigned long, struct disassemble_info *)); -int print_insn_tic4x - PARAMS ((bfd_vma, struct disassemble_info *)); - - static int -tic4x_pc_offset (op) - unsigned int op; +tic4x_pc_offset (unsigned int op) { /* Determine the PC offset for a C[34]x instruction. This could be simplified using some boolean algebra @@ -107,14 +73,14 @@ tic4x_pc_offset (op) default: break; } - + switch ((op & 0xffe00000) >> 20) { case 0x6a0: /* bB */ case 0x720: /* callB */ case 0x740: /* trapB */ return 1; - + case 0x6a2: /* bBd */ case 0x6a6: /* bBat */ case 0x6aa: /* bBaf */ @@ -122,30 +88,28 @@ tic4x_pc_offset (op) case 0x748: /* latB */ case 0x798: /* rptbd */ return 3; - + default: break; } - + switch ((op & 0xfe200000) >> 20) { case 0x6e0: /* dbB */ return 1; - + case 0x6e2: /* dbBd */ return 3; - + default: break; } - + return 0; } static int -tic4x_print_char (info, ch) - struct disassemble_info * info; - char ch; +tic4x_print_char (struct disassemble_info * info, char ch) { if (info != NULL) (*info->fprintf_func) (info->stream, "%c", ch); @@ -153,9 +117,7 @@ tic4x_print_char (info, ch) } static int -tic4x_print_str (info, str) - struct disassemble_info *info; - char *str; +tic4x_print_str (struct disassemble_info *info, char *str) { if (info != NULL) (*info->fprintf_func) (info->stream, "%s", str); @@ -163,25 +125,23 @@ tic4x_print_str (info, str) } static int -tic4x_print_register (info, regno) - struct disassemble_info *info; - unsigned long regno; +tic4x_print_register (struct disassemble_info *info, unsigned long regno) { - static tic4x_register_t **registertable = NULL; + static tic4x_register_t ** registertable = NULL; unsigned int i; - + if (registertable == NULL) { - registertable = (tic4x_register_t **) - xmalloc (sizeof (tic4x_register_t *) * REG_TABLE_SIZE); + registertable = xmalloc (sizeof (tic4x_register_t *) * REG_TABLE_SIZE); for (i = 0; i < tic3x_num_registers; i++) - registertable[tic3x_registers[i].regno] = (void *)&tic3x_registers[i]; + registertable[tic3x_registers[i].regno] = (tic4x_register_t *) (tic3x_registers + i); if (IS_CPU_TIC4X (tic4x_version)) { /* Add C4x additional registers, overwriting any C3x registers if necessary. */ for (i = 0; i < tic4x_num_registers; i++) - registertable[tic4x_registers[i].regno] = (void *)&tic4x_registers[i]; + registertable[tic4x_registers[i].regno] = + (tic4x_register_t *)(tic4x_registers + i); } } if ((int) regno > (IS_CPU_TIC4X (tic4x_version) ? TIC4X_REG_MAX : TIC3X_REG_MAX)) @@ -192,9 +152,7 @@ tic4x_print_register (info, regno) } static int -tic4x_print_addr (info, addr) - struct disassemble_info *info; - unsigned long addr; +tic4x_print_addr (struct disassemble_info *info, unsigned long addr) { if (info != NULL) (*info->print_address_func)(addr, info); @@ -202,19 +160,16 @@ tic4x_print_addr (info, addr) } static int -tic4x_print_relative (info, pc, offset, opcode) - struct disassemble_info *info; - unsigned long pc; - long offset; - unsigned long opcode; +tic4x_print_relative (struct disassemble_info *info, + unsigned long pc, + long offset, + unsigned long opcode) { return tic4x_print_addr (info, pc + offset + tic4x_pc_offset (opcode)); } static int -tic4x_print_direct (info, arg) - struct disassemble_info *info; - unsigned long arg; +tic4x_print_direct (struct disassemble_info *info, unsigned long arg) { if (info != NULL) { @@ -223,60 +178,58 @@ tic4x_print_direct (info, arg) } return 1; } - +#if 0 /* FIXME: make the floating point stuff not rely on host floating point arithmetic. */ -void -tic4x_print_ftoa (val, stream, pfunc) - unsigned int val; - FILE *stream; - fprintf_ftype pfunc; + +static void +tic4x_print_ftoa (unsigned int val, FILE *stream, fprintf_ftype pfunc) { int e; int s; int f; double num = 0.0; - - e = EXTRS (val, 31, 24); /* exponent */ + + e = EXTRS (val, 31, 24); /* Exponent. */ if (e != -128) { - s = EXTRU (val, 23, 23); /* sign bit */ - f = EXTRU (val, 22, 0); /* mantissa */ + s = EXTRU (val, 23, 23); /* Sign bit. */ + f = EXTRU (val, 22, 0); /* Mantissa. */ if (s) f += -2 * (1 << 23); else f += (1 << 23); num = f / (double)(1 << 23); num = ldexp (num, e); - } + } (*pfunc)(stream, "%.9g", num); } +#endif static int -tic4x_print_immed (info, type, arg) - struct disassemble_info *info; - immed_t type; - unsigned long arg; +tic4x_print_immed (struct disassemble_info *info, + immed_t type, + unsigned long arg) { int s; int f; int e; double num = 0.0; - + if (info == NULL) return 1; switch (type) { case IMMED_SINT: case IMMED_INT: - (*info->fprintf_func) (info->stream, "%d", (long)arg); + (*info->fprintf_func) (info->stream, "%ld", (long) arg); break; - + case IMMED_SUINT: case IMMED_UINT: - (*info->fprintf_func) (info->stream, "%u", arg); + (*info->fprintf_func) (info->stream, "%lu", arg); break; - + case IMMED_SFLOAT: e = EXTRS (arg, 15, 12); if (e != -8) @@ -312,18 +265,16 @@ tic4x_print_immed (info, type, arg) } static int -tic4x_print_cond (info, cond) - struct disassemble_info *info; - unsigned int cond; +tic4x_print_cond (struct disassemble_info *info, unsigned int cond) { static tic4x_cond_t **condtable = NULL; unsigned int i; - + if (condtable == NULL) { - condtable = (tic4x_cond_t **)xmalloc (sizeof (tic4x_cond_t *) * 32); + condtable = xmalloc (sizeof (tic4x_cond_t *) * 32); for (i = 0; i < tic4x_num_conds; i++) - condtable[tic4x_conds[i].cond] = (void *)&tic4x_conds[i]; + condtable[tic4x_conds[i].cond] = (tic4x_cond_t *)(tic4x_conds + i); } if (cond > 31 || condtable[cond] == NULL) return 0; @@ -333,10 +284,9 @@ tic4x_print_cond (info, cond) } static int -tic4x_print_indirect (info, type, arg) - struct disassemble_info *info; - indirect_t type; - unsigned long arg; +tic4x_print_indirect (struct disassemble_info *info, + indirect_t type, + unsigned long arg) { unsigned int aregno; unsigned int modn; @@ -398,11 +348,10 @@ tic4x_print_indirect (info, type, arg) } static int -tic4x_print_op (info, instruction, p, pc) - struct disassemble_info *info; - unsigned long instruction; - tic4x_inst_t *p; - unsigned long pc; +tic4x_print_op (struct disassemble_info *info, + unsigned long instruction, + tic4x_inst_t *p, + unsigned long pc) { int val; char *s; @@ -423,7 +372,7 @@ tic4x_print_op (info, instruction, p, pc return 0; break; case '_': - parallel = s + 1; /* Skip past `_' in name */ + parallel = s + 1; /* Skip past `_' in name. */ break; default: tic4x_print_char (info, *s); @@ -431,7 +380,7 @@ tic4x_print_op (info, instruction, p, pc } s++; } - + /* Print arguments. */ s = p->args; if (*s) @@ -441,23 +390,23 @@ tic4x_print_op (info, instruction, p, pc { switch (*s) { - case '*': /* indirect 0--15 */ + case '*': /* Indirect 0--15. */ if (! tic4x_print_indirect (info, INDIRECT_LONG, - EXTRU (instruction, 15, 0))) + EXTRU (instruction, 15, 0))) return 0; break; - case '#': /* only used for ldp, ldpk */ + case '#': /* Only used for ldp, ldpk. */ tic4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0)); break; - case '@': /* direct 0--15 */ + case '@': /* Direct 0--15. */ tic4x_print_direct (info, EXTRU (instruction, 15, 0)); break; - case 'A': /* address register 24--22 */ + case 'A': /* Address register 24--22. */ if (! tic4x_print_register (info, EXTRU (instruction, 24, 22) + - REG_AR0)) + REG_AR0)) return 0; break; @@ -465,16 +414,16 @@ tic4x_print_op (info, instruction, p, pc address 0--23. */ if (IS_CPU_TIC4X (tic4x_version)) tic4x_print_relative (info, pc, EXTRS (instruction, 23, 0), - p->opcode); + p->opcode); else tic4x_print_addr (info, EXTRU (instruction, 23, 0)); break; - case 'C': /* indirect (short C4x) 0--7 */ + case 'C': /* Indirect (short C4x) 0--7. */ if (! IS_CPU_TIC4X (tic4x_version)) return 0; if (! tic4x_print_indirect (info, INDIRECT_TIC4X, - EXTRU (instruction, 7, 0))) + EXTRU (instruction, 7, 0))) return 0; break; @@ -482,131 +431,131 @@ tic4x_print_op (info, instruction, p, pc /* Cockup if get here... */ break; - case 'E': /* register 0--7 */ + case 'E': /* Register 0--7. */ case 'e': if (! tic4x_print_register (info, EXTRU (instruction, 7, 0))) return 0; break; - case 'F': /* 16-bit float immediate 0--15 */ + case 'F': /* 16-bit float immediate 0--15. */ tic4x_print_immed (info, IMMED_SFLOAT, - EXTRU (instruction, 15, 0)); + EXTRU (instruction, 15, 0)); break; - case 'i': /* Extended indirect 0--7 */ - if ( EXTRU (instruction, 7, 5) == 7 ) + case 'i': /* Extended indirect 0--7. */ + if (EXTRU (instruction, 7, 5) == 7) { - if( !tic4x_print_register (info, EXTRU (instruction, 4, 0)) ) + if (!tic4x_print_register (info, EXTRU (instruction, 4, 0))) return 0; break; } /* Fallthrough */ - case 'I': /* indirect (short) 0--7 */ + case 'I': /* Indirect (short) 0--7. */ if (! tic4x_print_indirect (info, INDIRECT_SHORT, - EXTRU (instruction, 7, 0))) + EXTRU (instruction, 7, 0))) return 0; break; case 'j': /* Extended indirect 8--15 */ - if ( EXTRU (instruction, 15, 13) == 7 ) + if (EXTRU (instruction, 15, 13) == 7) { - if( !tic4x_print_register (info, EXTRU (instruction, 12, 8)) ) + if (! tic4x_print_register (info, EXTRU (instruction, 12, 8))) return 0; break; } - case 'J': /* indirect (short) 8--15 */ + case 'J': /* Indirect (short) 8--15. */ if (! tic4x_print_indirect (info, INDIRECT_SHORT, - EXTRU (instruction, 15, 8))) + EXTRU (instruction, 15, 8))) return 0; break; - case 'G': /* register 8--15 */ + case 'G': /* Register 8--15. */ case 'g': if (! tic4x_print_register (info, EXTRU (instruction, 15, 8))) return 0; break; - case 'H': /* register 16--18 */ + case 'H': /* Register 16--18. */ if (! tic4x_print_register (info, EXTRU (instruction, 18, 16))) return 0; break; - case 'K': /* register 19--21 */ + case 'K': /* Register 19--21. */ if (! tic4x_print_register (info, EXTRU (instruction, 21, 19))) return 0; break; - case 'L': /* register 22--24 */ + case 'L': /* Register 22--24. */ if (! tic4x_print_register (info, EXTRU (instruction, 24, 22))) return 0; break; - case 'M': /* register 22--22 */ + case 'M': /* Register 22--22. */ tic4x_print_register (info, EXTRU (instruction, 22, 22) + REG_R2); break; - case 'N': /* register 23--23 */ + case 'N': /* Register 23--23. */ tic4x_print_register (info, EXTRU (instruction, 23, 23) + REG_R0); break; - case 'O': /* indirect (short C4x) 8--15 */ + case 'O': /* Indirect (short C4x) 8--15. */ if (! IS_CPU_TIC4X (tic4x_version)) return 0; if (! tic4x_print_indirect (info, INDIRECT_TIC4X, - EXTRU (instruction, 15, 8))) + EXTRU (instruction, 15, 8))) return 0; break; - case 'P': /* displacement 0--15 (used by Bcond and BcondD) */ + case 'P': /* Displacement 0--15 (used by Bcond and BcondD). */ tic4x_print_relative (info, pc, EXTRS (instruction, 15, 0), - p->opcode); + p->opcode); break; - case 'Q': /* register 0--15 */ + case 'Q': /* Register 0--15. */ case 'q': if (! tic4x_print_register (info, EXTRU (instruction, 15, 0))) return 0; break; - case 'R': /* register 16--20 */ + case 'R': /* Register 16--20. */ case 'r': if (! tic4x_print_register (info, EXTRU (instruction, 20, 16))) return 0; break; - case 'S': /* 16-bit signed immediate 0--15 */ + case 'S': /* 16-bit signed immediate 0--15. */ tic4x_print_immed (info, IMMED_SINT, - EXTRS (instruction, 15, 0)); + EXTRS (instruction, 15, 0)); break; - case 'T': /* 5-bit signed immediate 16--20 (C4x stik) */ + case 'T': /* 5-bit signed immediate 16--20 (C4x stik). */ if (! IS_CPU_TIC4X (tic4x_version)) return 0; if (! tic4x_print_immed (info, IMMED_SUINT, - EXTRU (instruction, 20, 16))) + EXTRU (instruction, 20, 16))) return 0; break; - case 'U': /* 16-bit unsigned int immediate 0--15 */ + case 'U': /* 16-bit unsigned int immediate 0--15. */ tic4x_print_immed (info, IMMED_SUINT, EXTRU (instruction, 15, 0)); break; - case 'V': /* 5/9-bit unsigned vector 0--4/8 */ + case 'V': /* 5/9-bit unsigned vector 0--4/8. */ tic4x_print_immed (info, IMMED_SUINT, - IS_CPU_TIC4X (tic4x_version) ? - EXTRU (instruction, 8, 0) : - EXTRU (instruction, 4, 0) & ~0x20); + IS_CPU_TIC4X (tic4x_version) ? + EXTRU (instruction, 8, 0) : + EXTRU (instruction, 4, 0) & ~0x20); break; - case 'W': /* 8-bit signed immediate 0--7 */ + case 'W': /* 8-bit signed immediate 0--7. */ if (! IS_CPU_TIC4X (tic4x_version)) return 0; tic4x_print_immed (info, IMMED_SINT, EXTRS (instruction, 7, 0)); break; - case 'X': /* expansion register 4--0 */ + case 'X': /* Expansion register 4--0. */ val = EXTRU (instruction, 4, 0) + REG_IVTP; if (val < REG_IVTP || val > REG_TVTP) return 0; @@ -614,7 +563,7 @@ tic4x_print_op (info, instruction, p, pc return 0; break; - case 'Y': /* address register 16--20 */ + case 'Y': /* Address register 16--20. */ val = EXTRU (instruction, 20, 16); if (val < REG_AR0 || val > REG_SP) return 0; @@ -622,7 +571,7 @@ tic4x_print_op (info, instruction, p, pc return 0; break; - case 'Z': /* expansion register 16--20 */ + case 'Z': /* Expansion register 16--20. */ val = EXTRU (instruction, 20, 16) + REG_IVTP; if (val < REG_IVTP || val > REG_TVTP) return 0; @@ -630,7 +579,7 @@ tic4x_print_op (info, instruction, p, pc return 0; break; - case '|': /* Parallel instruction */ + case '|': /* Parallel instruction. */ tic4x_print_str (info, " || "); tic4x_print_str (info, parallel); tic4x_print_char (info, ' '); @@ -650,26 +599,25 @@ tic4x_print_op (info, instruction, p, pc } static void -tic4x_hash_opcode_special (optable_special, inst) - tic4x_inst_t **optable_special; - const tic4x_inst_t *inst; +tic4x_hash_opcode_special (tic4x_inst_t **optable_special, + const tic4x_inst_t *inst) { int i; - for( i=0; iopcode == inst->opcode ) + for (i = 0;i < TIC4X_SPESOP_SIZE; i++) + if (optable_special[i] != NULL + && optable_special[i]->opcode == inst->opcode) { - /* Collision (we have it already) - overwrite */ - optable_special[i] = (void *)inst; + /* Collision (we have it already) - overwrite. */ + optable_special[i] = (tic4x_inst_t *) inst; return; } - for( i=0; iopcode >> (32 - TIC4X_HASH_SIZE); int opmask = inst->opmask >> (32 - TIC4X_HASH_SIZE); - + /* Use a TIC4X_HASH_SIZE bit index as a hash index. We should have unique entries so there's no point having a linked list - for each entry? */ + for each entry? */ for (j = opcode; j < opmask; j++) - if ( (j & opmask) == opcode - && inst->oplevel & tic4x_oplevel ) + if ((j & opmask) == opcode + && inst->oplevel & tic4x_oplevel) { #if TIC4X_DEBUG /* We should only have collisions for synonyms like ldp for ldi. */ if (optable[j] != NULL) - printf("Collision at index %d, %s and %s\n", - j, optable[j]->name, inst->name); + printf ("Collision at index %d, %s and %s\n", + j, optable[j]->name, inst->name); #endif /* Catch those ops that collide with others already inside the hash, and have a opmask greater than the one we use in the hash. Store them in a special-list, that will handle full 32-bit INSN, not only the first 11-bit (or so). */ - if ( optable[j] != NULL - && inst->opmask & ~(opmask << (32 - TIC4X_HASH_SIZE)) ) + if (optable[j] != NULL + && inst->opmask & ~(opmask << (32 - TIC4X_HASH_SIZE))) { - /* Add the instruction already on the list */ - tic4x_hash_opcode_special(optable_special, optable[j]); + /* Add the instruction already on the list. */ + tic4x_hash_opcode_special (optable_special, optable[j]); - /* Add the new instruction */ - tic4x_hash_opcode_special(optable_special, inst); + /* Add the new instruction. */ + tic4x_hash_opcode_special (optable_special, inst); } - optable[j] = (void *)inst; + optable[j] = (tic4x_inst_t *) inst; } } @@ -731,92 +678,87 @@ tic4x_hash_opcode (optable, optable_spec The function returns the length of this instruction in words. */ static int -tic4x_disassemble (pc, instruction, info) - unsigned long pc; - unsigned long instruction; - struct disassemble_info *info; +tic4x_disassemble (unsigned long pc, + unsigned long instruction, + struct disassemble_info *info) { static tic4x_inst_t **optable = NULL; static tic4x_inst_t **optable_special = NULL; tic4x_inst_t *p; int i; unsigned long tic4x_oplevel; - + tic4x_version = info->mach; tic4x_oplevel = (IS_CPU_TIC4X (tic4x_version)) ? OP_C4X : 0; - tic4x_oplevel |= OP_C3X|OP_LPWR|OP_IDLE2|OP_ENH; - + tic4x_oplevel |= OP_C3X | OP_LPWR | OP_IDLE2 | OP_ENH; + if (optable == NULL) { - optable = (tic4x_inst_t **) - xcalloc (sizeof (tic4x_inst_t *), (1 << TIC4X_HASH_SIZE)); + optable = xcalloc (sizeof (tic4x_inst_t *), (1 << TIC4X_HASH_SIZE)); - optable_special = (tic4x_inst_t **) - xcalloc (sizeof (tic4x_inst_t *), TIC4X_SPESOP_SIZE ); + optable_special = xcalloc (sizeof (tic4x_inst_t *), TIC4X_SPESOP_SIZE); /* Install opcodes in reverse order so that preferred forms overwrite synonyms. */ for (i = tic4x_num_insts - 1; i >= 0; i--) - tic4x_hash_opcode (optable, optable_special, &tic4x_insts[i], tic4x_oplevel); + tic4x_hash_opcode (optable, optable_special, &tic4x_insts[i], + tic4x_oplevel); /* We now need to remove the insn that are special from the "normal" optable, to make the disasm search this extra list - for them. - */ - for (i=0; iopcode >> (32 - TIC4X_HASH_SIZE)] = NULL; } - + /* See if we can pick up any loading of the DP register... */ if ((instruction >> 16) == 0x5070 || (instruction >> 16) == 0x1f70) tic4x_dp = EXTRU (instruction, 15, 0); p = optable[instruction >> (32 - TIC4X_HASH_SIZE)]; - if ( p != NULL ) + if (p != NULL) { - if ( ((instruction & p->opmask) == p->opcode) - && tic4x_print_op (NULL, instruction, p, pc) ) + if (((instruction & p->opmask) == p->opcode) + && tic4x_print_op (NULL, instruction, p, pc)) tic4x_print_op (info, instruction, p, pc); else - (*info->fprintf_func) (info->stream, "%08x", instruction); + (*info->fprintf_func) (info->stream, "%08lx", instruction); } else { for (i = 0; iopcode == instruction ) + && optable_special[i]->opcode == instruction) { (*info->fprintf_func)(info->stream, "%s", optable_special[i]->name); break; } - if (i==TIC4X_SPESOP_SIZE) - (*info->fprintf_func) (info->stream, "%08x", instruction); + if (i == TIC4X_SPESOP_SIZE) + (*info->fprintf_func) (info->stream, "%08lx", instruction); } /* Return size of insn in words. */ - return 1; + return 1; } /* The entry point from objdump and gdb. */ int -print_insn_tic4x (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_tic4x (bfd_vma memaddr, struct disassemble_info *info) { int status; unsigned long pc; unsigned long op; bfd_byte buffer[4]; - + status = (*info->read_memory_func) (memaddr, buffer, 4, info); if (status != 0) { (*info->memory_error_func) (status, memaddr, info); return -1; } - + pc = memaddr; op = bfd_getl32 (buffer); info->bytes_per_line = 4; diff -uprN binutils-2.16.91.0.1/opcodes/tic80-dis.c binutils-2.16.91.0.2/opcodes/tic80-dis.c --- binutils-2.16.91.0.1/opcodes/tic80-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/tic80-dis.c 2005-07-20 12:27:29.397845988 -0700 @@ -1,19 +1,20 @@ /* Print TI TMS320C80 (MVP) instructions - Copyright 1996, 1997, 1998, 2000 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 2000, 2005 Free Software Foundation, Inc. -This file is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This file is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include @@ -22,20 +23,6 @@ Foundation, Inc., 51 Franklin Street - F #include "dis-asm.h" static int length; - -static void print_operand_bitnum PARAMS ((struct disassemble_info *, long)); -static void print_operand_condition_code PARAMS ((struct disassemble_info *, long)); -static void print_operand_control_register PARAMS ((struct disassemble_info *, long)); -static void print_operand_float PARAMS ((struct disassemble_info *, long)); -static void print_operand_integer PARAMS ((struct disassemble_info *, long)); -static void print_operand PARAMS ((struct disassemble_info *, long, unsigned long, - const struct tic80_operand *, bfd_vma)); -static int print_one_instruction PARAMS ((struct disassemble_info *, bfd_vma, - unsigned long, const struct tic80_opcode *)); -static int print_instruction PARAMS ((struct disassemble_info *, bfd_vma, unsigned long, - const struct tic80_opcode *)); -static int fill_instruction PARAMS ((struct disassemble_info *, bfd_vma, - unsigned long *)); /* Print an integer operand. Try to be somewhat smart about the format by assuming that small positive or negative integers are @@ -44,18 +31,12 @@ static int fill_instruction PARAMS ((str Larger numbers are probably better printed as hex values. */ static void -print_operand_integer (info, value) - struct disassemble_info *info; - long value; +print_operand_integer (struct disassemble_info *info, long value) { if ((value > 9999 || value < -9999)) - { - (*info->fprintf_func) (info->stream, "%#lx", value); - } + (*info->fprintf_func) (info->stream, "%#lx", value); else - { - (*info->fprintf_func) (info->stream, "%ld", value); - } + (*info->fprintf_func) (info->stream, "%ld", value); } /* FIXME: depends upon sizeof (long) == sizeof (float) and @@ -63,56 +44,40 @@ print_operand_integer (info, value) floating point format. */ static void -print_operand_float (info, value) - struct disassemble_info *info; - long value; +print_operand_float (struct disassemble_info *info, long value) { union { float f; long l; } fval; fval.l = value; (*info->fprintf_func) (info->stream, "%g", fval.f); } - + static void -print_operand_control_register (info, value) - struct disassemble_info *info; - long value; +print_operand_control_register (struct disassemble_info *info, long value) { const char *tmp; tmp = tic80_value_to_symbol (value, TIC80_OPERAND_CR); if (tmp != NULL) - { - (*info->fprintf_func) (info->stream, "%s", tmp); - } + (*info->fprintf_func) (info->stream, "%s", tmp); else - { - (*info->fprintf_func) (info->stream, "%#lx", value); - } + (*info->fprintf_func) (info->stream, "%#lx", value); } - + static void -print_operand_condition_code (info, value) - struct disassemble_info *info; - long value; +print_operand_condition_code (struct disassemble_info *info, long value) { const char *tmp; tmp = tic80_value_to_symbol (value, TIC80_OPERAND_CC); if (tmp != NULL) - { - (*info->fprintf_func) (info->stream, "%s", tmp); - } + (*info->fprintf_func) (info->stream, "%s", tmp); else - { - (*info->fprintf_func) (info->stream, "%ld", value); - } + (*info->fprintf_func) (info->stream, "%ld", value); } - + static void -print_operand_bitnum (info, value) - struct disassemble_info *info; - long value; +print_operand_bitnum (struct disassemble_info *info, long value) { int bitnum; const char *tmp; @@ -120,13 +85,9 @@ print_operand_bitnum (info, value) bitnum = ~value & 0x1F; tmp = tic80_value_to_symbol (bitnum, TIC80_OPERAND_BITNUM); if (tmp != NULL) - { - (*info->fprintf_func) (info->stream, "%s", tmp); - } + (*info->fprintf_func) (info->stream, "%s", tmp); else - { - (*info->fprintf_func) (info->stream, "%ld", bitnum); - } + (*info->fprintf_func) (info->stream, "%d", bitnum); } /* Print the operand as directed by the flags. */ @@ -136,12 +97,11 @@ print_operand_bitnum (info, value) #define R_SCALED(insn,op) ((((op)->flags & TIC80_OPERAND_SCALED) != 0) && ((insn) & (1 << 11))) static void -print_operand (info, value, insn, operand, memaddr) - struct disassemble_info *info; - long value; - unsigned long insn; - const struct tic80_operand *operand; - bfd_vma memaddr; +print_operand (struct disassemble_info *info, + long value, + unsigned long insn, + const struct tic80_operand *operand, + bfd_vma memaddr) { if ((operand->flags & TIC80_OPERAND_GPR) != 0) { @@ -152,58 +112,81 @@ print_operand (info, value, insn, operan } } else if ((operand->flags & TIC80_OPERAND_FPA) != 0) - { - (*info->fprintf_func) (info->stream, "a%ld", value); - } + (*info->fprintf_func) (info->stream, "a%ld", value); + else if ((operand->flags & TIC80_OPERAND_PCREL) != 0) - { - (*info->print_address_func) (memaddr + 4 * value, info); - } + (*info->print_address_func) (memaddr + 4 * value, info); + else if ((operand->flags & TIC80_OPERAND_BASEREL) != 0) - { - (*info->print_address_func) (value, info); - } + (*info->print_address_func) (value, info); + else if ((operand->flags & TIC80_OPERAND_BITNUM) != 0) - { - print_operand_bitnum (info, value); - } + print_operand_bitnum (info, value); + else if ((operand->flags & TIC80_OPERAND_CC) != 0) - { - print_operand_condition_code (info, value); - } + print_operand_condition_code (info, value); + else if ((operand->flags & TIC80_OPERAND_CR) != 0) - { - print_operand_control_register (info, value); - } + print_operand_control_register (info, value); + else if ((operand->flags & TIC80_OPERAND_FLOAT) != 0) - { - print_operand_float (info, value); - } + print_operand_float (info, value); + else if ((operand->flags & TIC80_OPERAND_BITFIELD)) - { - (*info->fprintf_func) (info->stream, "%#lx", value); - } + (*info->fprintf_func) (info->stream, "%#lx", value); + else - { - print_operand_integer (info, value); - } + print_operand_integer (info, value); /* If this is a scaled operand, then print the modifier. */ - if (R_SCALED (insn, operand)) + (*info->fprintf_func) (info->stream, ":s"); +} + +/* Get the next 32 bit word from the instruction stream and convert it + into internal format in the unsigned long INSN, for which we are + passed the address. Return 0 on success, -1 on error. */ + +static int +fill_instruction (struct disassemble_info *info, + bfd_vma memaddr, + unsigned long *insnp) +{ + bfd_byte buffer[4]; + int status; + + /* Get the bits for the next 32 bit word and put in buffer. */ + status = (*info->read_memory_func) (memaddr + length, buffer, 4, info); + if (status != 0) { - (*info->fprintf_func) (info->stream, ":s"); + (*info->memory_error_func) (status, memaddr, info); + return -1; } + + /* Read was successful, so increment count of bytes read and convert + the bits into internal format. */ + + length += 4; + if (info->endian == BFD_ENDIAN_LITTLE) + *insnp = bfd_getl32 (buffer); + + else if (info->endian == BFD_ENDIAN_BIG) + *insnp = bfd_getb32 (buffer); + + else + /* FIXME: Should probably just default to one or the other. */ + abort (); + + return 0; } - + /* We have chosen an opcode table entry. */ static int -print_one_instruction (info, memaddr, insn, opcode) - struct disassemble_info *info; - bfd_vma memaddr; - unsigned long insn; - const struct tic80_opcode *opcode; +print_one_instruction (struct disassemble_info *info, + bfd_vma memaddr, + unsigned long insn, + const struct tic80_opcode *opcode) { const struct tic80_operand *operand; long value; @@ -219,38 +202,31 @@ print_one_instruction (info, memaddr, in /* Extract the value from the instruction. */ if (operand->extract) - { - value = (*operand->extract) (insn, (int *) NULL); - } + value = (*operand->extract) (insn, NULL); + else if (operand->bits == 32) { status = fill_instruction (info, memaddr, (unsigned long *) &value); if (status == -1) - { - return (status); - } + return status; } else { value = (insn >> operand->shift) & ((1 << operand->bits) - 1); + if ((operand->flags & TIC80_OPERAND_SIGNED) != 0 && (value & (1 << (operand->bits - 1))) != 0) - { - value -= 1 << operand->bits; - } + value -= 1 << operand->bits; } /* If this operand is enclosed in parenthesis, then print the open paren, otherwise just print the regular comma separator, except for the first operand. */ - if ((operand->flags & TIC80_OPERAND_PARENS) == 0) { close_paren = 0; if (opindex != opcode->operands) - { - (*info->fprintf_func) (info->stream, ","); - } + (*info->fprintf_func) (info->stream, ","); } else { @@ -262,13 +238,11 @@ print_one_instruction (info, memaddr, in /* If we printed an open paren before printing this operand, close it now. The flag gets reset on each loop. */ - if (close_paren) - { - (*info->fprintf_func) (info->stream, ")"); - } + (*info->fprintf_func) (info->stream, ")"); } - return (length); + + return length; } /* There are no specific bits that tell us for certain whether a vector @@ -280,11 +254,10 @@ print_one_instruction (info, memaddr, in #define TWO_INSN(insn) ((((insn) & (0x1F << 27)) != 0) && (((insn) & (0x1F << 22)) != 0)) static int -print_instruction (info, memaddr, insn, vec_opcode) - struct disassemble_info *info; - bfd_vma memaddr; - unsigned long insn; - const struct tic80_opcode *vec_opcode; +print_instruction (struct disassemble_info *info, + bfd_vma memaddr, + unsigned long insn, + const struct tic80_opcode *vec_opcode) { const struct tic80_opcode *opcode; const struct tic80_opcode *opcode_end; @@ -300,9 +273,7 @@ print_instruction (info, memaddr, insn, { if ((insn & opcode->mask) == opcode->opcode && opcode != vec_opcode) - { - break; - } + break; } if (opcode == opcode_end) @@ -323,55 +294,12 @@ print_instruction (info, memaddr, insn, length = print_instruction (info, memaddr, insn, opcode); } } - return (length); -} -/* Get the next 32 bit word from the instruction stream and convert it - into internal format in the unsigned long INSN, for which we are - passed the address. Return 0 on success, -1 on error. */ - -static int -fill_instruction (info, memaddr, insnp) - struct disassemble_info *info; - bfd_vma memaddr; - unsigned long *insnp; -{ - bfd_byte buffer[4]; - int status; - - /* Get the bits for the next 32 bit word and put in buffer. */ - - status = (*info->read_memory_func) (memaddr + length, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, memaddr, info); - return (-1); - } - - /* Read was successful, so increment count of bytes read and convert - the bits into internal format. */ - - length += 4; - if (info->endian == BFD_ENDIAN_LITTLE) - { - *insnp = bfd_getl32 (buffer); - } - else if (info->endian == BFD_ENDIAN_BIG) - { - *insnp = bfd_getb32 (buffer); - } - else - { - /* FIXME: Should probably just default to one or the other. */ - abort (); - } - return (0); + return length; } int -print_insn_tic80 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_tic80 (bfd_vma memaddr, struct disassemble_info *info) { unsigned long insn; int status; @@ -380,8 +308,7 @@ print_insn_tic80 (memaddr, info) info->bytes_per_line = 8; status = fill_instruction (info, memaddr, &insn); if (status != -1) - { - status = print_instruction (info, memaddr, insn, NULL); - } - return (status); + status = print_instruction (info, memaddr, insn, NULL); + + return status; } diff -uprN binutils-2.16.91.0.1/opcodes/v850-dis.c binutils-2.16.91.0.2/opcodes/v850-dis.c --- binutils-2.16.91.0.1/opcodes/v850-dis.c 2005-05-10 15:46:54.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/v850-dis.c 2005-07-20 12:27:29.398845823 -0700 @@ -1,5 +1,5 @@ /* Disassemble V850 instructions. - Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003 + Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify @@ -14,57 +14,54 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include #include "sysdep.h" -#include "opcode/v850.h" +#include "opcode/v850.h" #include "dis-asm.h" #include "opintl.h" static const char *const v850_reg_names[] = -{ "r0", "r1", "r2", "sp", "gp", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", - "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", +{ "r0", "r1", "r2", "sp", "gp", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "ep", "lp" }; static const char *const v850_sreg_names[] = -{ "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7", +{ "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7", "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15", - "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23", + "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23", "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31", - "sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23", + "sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23", "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31" }; static const char *const v850_cc_names[] = -{ "v", "c/l", "z", "nh", "s/n", "t", "lt", "le", +{ "v", "c/l", "z", "nh", "s/n", "t", "lt", "le", "nv", "nc/nl", "nz", "h", "ns/p", "sa", "ge", "gt" }; -static int disassemble - PARAMS ((bfd_vma, struct disassemble_info *, unsigned long)); - static int -disassemble (memaddr, info, insn) - bfd_vma memaddr; - struct disassemble_info *info; - unsigned long insn; +disassemble (bfd_vma memaddr, + struct disassemble_info * info, + unsigned long insn) { - struct v850_opcode *op = (struct v850_opcode *)v850_opcodes; - const struct v850_operand *operand; + struct v850_opcode * op = (struct v850_opcode *) v850_opcodes; + const struct v850_operand * operand; int match = 0; int short_op = ((insn & 0x0600) != 0x0600); int bytes_read; int target_processor; - - /* Special case: 32 bit MOV */ + + /* Special case: 32 bit MOV. */ if ((insn & 0xffe0) == 0x0620) short_op = 1; - + bytes_read = short_op ? 2 : 4; - - /* If this is a two byte insn, then mask off the high bits. */ + + /* If this is a two byte insn, then mask off the high bits. */ if (short_op) insn &= 0xffff; @@ -83,7 +80,7 @@ disassemble (memaddr, info, insn) target_processor = PROCESSOR_V850E1; break; } - + /* Find the opcode. */ while (op->name) { @@ -96,7 +93,6 @@ disassemble (memaddr, info, insn) match = 1; (*info->fprintf_func) (info->stream, "%s\t", op->name); -/*fprintf (stderr, "match: mask: %x insn: %x, opcode: %x, name: %s\n", op->mask, insn, op->opcode, op->name );*/ memop = op->memop; /* Now print the operands. @@ -111,7 +107,7 @@ disassemble (memaddr, info, insn) insert commas into the output stream as well as when to insert disp[reg] expressions onto the output stream. */ - + for (opindex_ptr = op->operands, opnum = 1; *opindex_ptr != 0; opindex_ptr++, opnum++) @@ -120,9 +116,9 @@ disassemble (memaddr, info, insn) int flag; int status; bfd_byte buffer[4]; - + operand = &v850_operands[*opindex_ptr]; - + if (operand->extract) value = (operand->extract) (insn, 0); else @@ -153,56 +149,70 @@ disassemble (memaddr, info, insn) Else we just need a comma. We may need to output a trailing ']' if the last operand - in an instruction is the register for a memory address. + in an instruction is the register for a memory address. The exception (and there's always an exception) is the "jmp" insn which needs square brackets around it's only register argument. */ - if (memop && opnum == memop + 1) info->fprintf_func (info->stream, "["); - else if (memop && opnum == memop + 2) info->fprintf_func (info->stream, "],"); - else if (memop == 1 && opnum == 1 - && (operand->flags & V850_OPERAND_REG)) - info->fprintf_func (info->stream, "["); - else if (opnum > 1) info->fprintf_func (info->stream, ", "); + if (memop && opnum == memop + 1) + info->fprintf_func (info->stream, "["); + else if (memop && opnum == memop + 2) + info->fprintf_func (info->stream, "],"); + else if (memop == 1 && opnum == 1 + && (operand->flags & V850_OPERAND_REG)) + info->fprintf_func (info->stream, "["); + else if (opnum > 1) + info->fprintf_func (info->stream, ", "); - /* extract the flags, ignorng ones which do not effect disassembly output. */ + /* Extract the flags, ignorng ones which + do not effect disassembly output. */ flag = operand->flags; flag &= ~ V850_OPERAND_SIGNED; flag &= ~ V850_OPERAND_RELAX; flag &= - flag; - + switch (flag) { - case V850_OPERAND_REG: info->fprintf_func (info->stream, "%s", v850_reg_names[value]); break; - case V850_OPERAND_SRG: info->fprintf_func (info->stream, "%s", v850_sreg_names[value]); break; - case V850_OPERAND_CC: info->fprintf_func (info->stream, "%s", v850_cc_names[value]); break; - case V850_OPERAND_EP: info->fprintf_func (info->stream, "ep"); break; - default: info->fprintf_func (info->stream, "%d", value); break; + case V850_OPERAND_REG: + info->fprintf_func (info->stream, "%s", v850_reg_names[value]); + break; + case V850_OPERAND_SRG: + info->fprintf_func (info->stream, "%s", v850_sreg_names[value]); + break; + case V850_OPERAND_CC: + info->fprintf_func (info->stream, "%s", v850_cc_names[value]); + break; + case V850_OPERAND_EP: + info->fprintf_func (info->stream, "ep"); + break; + default: + info->fprintf_func (info->stream, "%ld", value); + break; case V850_OPERAND_DISP: { bfd_vma addr = value + memaddr; - - /* On the v850 the top 8 bits of an address are used by an overlay manager. - Thus it may happen that when we are looking for a symbol to match - against an address with some of its top bits set, the search fails to - turn up an exact match. In this case we try to find an exact match - against a symbol in the lower address space, and if we find one, we - use that address. We only do this for JARL instructions however, as - we do not want to misinterpret branch instructions. */ + + /* On the v850 the top 8 bits of an address are used by an + overlay manager. Thus it may happen that when we are + looking for a symbol to match against an address with + some of its top bits set, the search fails to turn up an + exact match. In this case we try to find an exact match + against a symbol in the lower address space, and if we + find one, we use that address. We only do this for + JARL instructions however, as we do not want to + misinterpret branch instructions. */ if (operand->bits == 22) { if ( ! info->symbol_at_address_func (addr, info) && ((addr & 0xFF000000) != 0) && info->symbol_at_address_func (addr & 0x00FFFFFF, info)) - { - addr &= 0x00FFFFFF; - } + addr &= 0x00FFFFFF; } info->print_address_func (addr, info); break; } - + case V850E_PUSH_POP: { static int list12_regs[32] = { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 }; @@ -213,17 +223,20 @@ disassemble (memaddr, info, insn) unsigned long int mask = 0; int pc = 0; int sr = 0; - - + switch (operand->shift) { case 0xffe00001: regs = list12_regs; break; case 0xfff8000f: regs = list18_h_regs; break; - case 0xfff8001f: regs = list18_l_regs; value &= ~0x10; break; /* Do not include magic bit */ + case 0xfff8001f: + regs = list18_l_regs; + value &= ~0x10; /* Do not include magic bit. */ + break; default: /* xgettext:c-format */ - fprintf (stderr, _("unknown operand shift: %x\n"), operand->shift ); - abort(); + fprintf (stderr, _("unknown operand shift: %x\n"), + operand->shift); + abort (); } for (i = 0; i < 32; i++) @@ -234,7 +247,9 @@ disassemble (memaddr, info, insn) { default: mask |= (1 << regs[ i ]); break; /* xgettext:c-format */ - case 0: fprintf (stderr, _("unknown pop reg: %d\n"), i ); abort(); + case 0: + fprintf (stderr, _("unknown pop reg: %d\n"), i ); + abort (); case -1: pc = 1; break; case -2: sr = 1; break; } @@ -242,14 +257,14 @@ disassemble (memaddr, info, insn) } info->fprintf_func (info->stream, "{"); - + if (mask || pc || sr) { if (mask) { unsigned int bit; int shown_one = 0; - + for (bit = 0; bit < 32; bit++) if (mask & (1 << bit)) { @@ -260,9 +275,10 @@ disassemble (memaddr, info, insn) info->fprintf_func (info->stream, ", "); else shown_one = 1; - - info->fprintf_func (info->stream, v850_reg_names[first]); - + + info->fprintf_func (info->stream, + v850_reg_names[first]); + for (bit++; bit < 32; bit++) if ((mask & (1 << bit)) == 0) break; @@ -270,43 +286,44 @@ disassemble (memaddr, info, insn) last = bit; if (last > first + 1) - { - info->fprintf_func (info->stream, " - %s", v850_reg_names[ last - 1 ]); - } + info->fprintf_func (info->stream, " - %s", + v850_reg_names[last - 1]); } } - + if (pc) info->fprintf_func (info->stream, "%sPC", mask ? ", " : ""); if (sr) info->fprintf_func (info->stream, "%sSR", (mask || pc) ? ", " : ""); } - + info->fprintf_func (info->stream, "}"); } break; - + case V850E_IMMEDIATE16: - status = info->read_memory_func (memaddr + bytes_read, buffer, 2, info); + status = info->read_memory_func (memaddr + bytes_read, + buffer, 2, info); if (status == 0) { bytes_read += 2; value = bfd_getl16 (buffer); - /* If this is a DISPOSE instruction with ff set to 0x10, then shift value up by 16. */ + /* If this is a DISPOSE instruction with ff + set to 0x10, then shift value up by 16. */ if ((insn & 0x001fffc0) == 0x00130780) value <<= 16; - info->fprintf_func (info->stream, "0x%x", value); + info->fprintf_func (info->stream, "0x%lx", value); } else - { - info->memory_error_func (status, memaddr + bytes_read, info); - } + info->memory_error_func (status, memaddr + bytes_read, + info); break; - + case V850E_IMMEDIATE32: - status = info->read_memory_func (memaddr + bytes_read, buffer, 4, info); + status = info->read_memory_func (memaddr + bytes_read, + buffer, 4, info); if (status == 0) { bytes_read += 4; @@ -314,11 +331,10 @@ disassemble (memaddr, info, insn) info->fprintf_func (info->stream, "0x%lx", value); } else - { - info->memory_error_func (status, memaddr + bytes_read, info); - } + info->memory_error_func (status, memaddr + bytes_read, + info); break; - } + } /* Handle jmp correctly. */ if (memop == 1 && opnum == 1 @@ -339,30 +355,27 @@ disassemble (memaddr, info, insn) if (!match) { if (short_op) - info->fprintf_func (info->stream, ".short\t0x%04x", insn); + info->fprintf_func (info->stream, ".short\t0x%04lx", insn); else - info->fprintf_func (info->stream, ".long\t0x%08x", insn); + info->fprintf_func (info->stream, ".long\t0x%08lx", insn); } return bytes_read; } -int -print_insn_v850 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info * info; +int +print_insn_v850 (bfd_vma memaddr, struct disassemble_info * info) { int status; bfd_byte buffer[4]; unsigned long insn = 0; /* First figure out how big the opcode is. */ - status = info->read_memory_func (memaddr, buffer, 2, info); if (status == 0) { insn = bfd_getl16 (buffer); - + if ( (insn & 0x0600) == 0x0600 && (insn & 0xffe0) != 0x0620) { @@ -373,7 +386,7 @@ print_insn_v850 (memaddr, info) insn = bfd_getl32 (buffer); } } - + if (status != 0) { info->memory_error_func (status, memaddr, info); diff -uprN binutils-2.16.91.0.1/opcodes/v850-opc.c binutils-2.16.91.0.2/opcodes/v850-opc.c --- binutils-2.16.91.0.1/opcodes/v850-opc.c 2005-05-10 15:46:55.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/v850-opc.c 2005-07-20 12:27:29.400845493 -0700 @@ -1,5 +1,5 @@ /* Assemble V850 instructions. - Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003 + Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify @@ -14,7 +14,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include "sysdep.h" #include "opcode/v850.h" @@ -34,30 +35,6 @@ /* Two-word opcodes. */ #define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16)) - -static long unsigned insert_d9 PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_d9 PARAMS ((long unsigned, int *)); -static long unsigned insert_d22 PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_d22 PARAMS ((long unsigned, int *)); -static long unsigned insert_d16_15 PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_d16_15 PARAMS ((long unsigned, int *)); -static long unsigned insert_d8_7 PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_d8_7 PARAMS ((long unsigned, int *)); -static long unsigned insert_d8_6 PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_d8_6 PARAMS ((long unsigned, int *)); -static long unsigned insert_d5_4 PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_d5_4 PARAMS ((long unsigned, int *)); -static long unsigned insert_d16_16 PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_d16_16 PARAMS ((long unsigned, int *)); -static long unsigned insert_i9 PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_i9 PARAMS ((long unsigned, int *)); -static long unsigned insert_u9 PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_u9 PARAMS ((long unsigned, int *)); -static long unsigned insert_spe PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_spe PARAMS ((long unsigned, int *)); -static long unsigned insert_i5div PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_i5div PARAMS ((long unsigned, int *)); - /* The functions used to insert and extract complicated operands. */ @@ -73,10 +50,7 @@ static const char * not_aligned = N_ (" static const char * immediate_out_of_range = N_ ("immediate value is out of range"); static unsigned long -insert_d9 (insn, value, errmsg) - unsigned long insn; - long value; - const char ** errmsg; +insert_d9 (unsigned long insn, long value, const char ** errmsg) { if (value > 0xff || value < -0x100) { @@ -88,13 +62,11 @@ insert_d9 (insn, value, errmsg) else if ((value % 2) != 0) * errmsg = _("branch to odd offset"); - return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3)); + return insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3); } static unsigned long -extract_d9 (insn, invalid) - unsigned long insn; - int * invalid ATTRIBUTE_UNUSED; +extract_d9 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED) { unsigned long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3); @@ -105,10 +77,7 @@ extract_d9 (insn, invalid) } static unsigned long -insert_d22 (insn, value, errmsg) - unsigned long insn; - long value; - const char ** errmsg; +insert_d22 (unsigned long insn, long value, const char ** errmsg) { if (value > 0x1fffff || value < -0x200000) { @@ -120,13 +89,11 @@ insert_d22 (insn, value, errmsg) else if ((value % 2) != 0) * errmsg = _("branch to odd offset"); - return (insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16)); + return insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16); } static unsigned long -extract_d22 (insn, invalid) - unsigned long insn; - int * invalid ATTRIBUTE_UNUSED; +extract_d22 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED) { signed long ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16); @@ -134,10 +101,7 @@ extract_d22 (insn, invalid) } static unsigned long -insert_d16_15 (insn, value, errmsg) - unsigned long insn; - long value; - const char ** errmsg; +insert_d16_15 (unsigned long insn, long value, const char ** errmsg) { if (value > 0x7fff || value < -0x8000) { @@ -153,9 +117,7 @@ insert_d16_15 (insn, value, errmsg) } static unsigned long -extract_d16_15 (insn, invalid) - unsigned long insn; - int * invalid ATTRIBUTE_UNUSED; +extract_d16_15 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED) { signed long ret = (insn & 0xfffe0000); @@ -163,10 +125,7 @@ extract_d16_15 (insn, invalid) } static unsigned long -insert_d8_7 (insn, value, errmsg) - unsigned long insn; - long value; - const char ** errmsg; +insert_d8_7 (unsigned long insn, long value, const char ** errmsg) { if (value > 0xff || value < 0) { @@ -180,13 +139,11 @@ insert_d8_7 (insn, value, errmsg) value >>= 1; - return (insn | (value & 0x7f)); + return insn | (value & 0x7f); } static unsigned long -extract_d8_7 (insn, invalid) - unsigned long insn; - int * invalid ATTRIBUTE_UNUSED; +extract_d8_7 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED) { unsigned long ret = (insn & 0x7f); @@ -194,10 +151,7 @@ extract_d8_7 (insn, invalid) } static unsigned long -insert_d8_6 (insn, value, errmsg) - unsigned long insn; - long value; - const char ** errmsg; +insert_d8_6 (unsigned long insn, long value, const char ** errmsg) { if (value > 0xff || value < 0) { @@ -211,13 +165,11 @@ insert_d8_6 (insn, value, errmsg) value >>= 1; - return (insn | (value & 0x7e)); + return insn | (value & 0x7e); } static unsigned long -extract_d8_6 (insn, invalid) - unsigned long insn; - int * invalid ATTRIBUTE_UNUSED; +extract_d8_6 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED) { unsigned long ret = (insn & 0x7e); @@ -225,10 +177,7 @@ extract_d8_6 (insn, invalid) } static unsigned long -insert_d5_4 (insn, value, errmsg) - unsigned long insn; - long value; - const char ** errmsg; +insert_d5_4 (unsigned long insn, long value, const char ** errmsg) { if (value > 0x1f || value < 0) { @@ -242,13 +191,11 @@ insert_d5_4 (insn, value, errmsg) value >>= 1; - return (insn | (value & 0x0f)); + return insn | (value & 0x0f); } static unsigned long -extract_d5_4 (insn, invalid) - unsigned long insn; - int * invalid ATTRIBUTE_UNUSED; +extract_d5_4 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED) { unsigned long ret = (insn & 0x0f); @@ -256,36 +203,28 @@ extract_d5_4 (insn, invalid) } static unsigned long -insert_d16_16 (insn, value, errmsg) - unsigned long insn; - signed long value; - const char ** errmsg; +insert_d16_16 (unsigned long insn, signed long value, const char ** errmsg) { if (value > 0x7fff || value < -0x8000) * errmsg = _(out_of_range); - return (insn | ((value & 0xfffe) << 16) | ((value & 1) << 5)); + return insn | ((value & 0xfffe) << 16) | ((value & 1) << 5); } static unsigned long -extract_d16_16 (insn, invalid) - unsigned long insn; - int * invalid ATTRIBUTE_UNUSED; +extract_d16_16 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED) { signed long ret = insn & 0xfffe0000; ret >>= 16; ret |= ((insn & 0x20) >> 5); - + return ret; } static unsigned long -insert_i9 (insn, value, errmsg) - unsigned long insn; - signed long value; - const char ** errmsg; +insert_i9 (unsigned long insn, signed long value, const char ** errmsg) { if (value > 0xff || value < -0x100) * errmsg = _(immediate_out_of_range); @@ -294,9 +233,7 @@ insert_i9 (insn, value, errmsg) } static unsigned long -extract_i9 (insn, invalid) - unsigned long insn; - int * invalid ATTRIBUTE_UNUSED; +extract_i9 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED) { signed long ret = insn & 0x003c0000; @@ -304,17 +241,15 @@ extract_i9 (insn, invalid) ret >>= 23; ret |= (insn & 0x1f); - + return ret; } static unsigned long -insert_u9 (insn, v, errmsg) - unsigned long insn; - long v; - const char ** errmsg; +insert_u9 (unsigned long insn, long v, const char ** errmsg) { unsigned long value = (unsigned long) v; + if (value > 0x1ff) * errmsg = _(immediate_out_of_range); @@ -322,24 +257,19 @@ insert_u9 (insn, v, errmsg) } static unsigned long -extract_u9 (insn, invalid) - unsigned long insn; - int * invalid ATTRIBUTE_UNUSED; +extract_u9 (unsigned long insn, int * invalid ATTRIBUTE_UNUSED) { unsigned long ret = insn & 0x003c0000; ret >>= 13; ret |= (insn & 0x1f); - + return ret; } static unsigned long -insert_spe (insn, v, errmsg) - unsigned long insn; - long v; - const char ** errmsg; +insert_spe (unsigned long insn, long v, const char ** errmsg) { unsigned long value = (unsigned long) v; @@ -350,18 +280,14 @@ insert_spe (insn, v, errmsg) } static unsigned long -extract_spe (insn, invalid) - unsigned long insn ATTRIBUTE_UNUSED; - int * invalid ATTRIBUTE_UNUSED; +extract_spe (unsigned long insn ATTRIBUTE_UNUSED, + int * invalid ATTRIBUTE_UNUSED) { return 3; } static unsigned long -insert_i5div (insn, v, errmsg) - unsigned long insn; - long v; - const char ** errmsg; +insert_i5div (unsigned long insn, long v, const char ** errmsg) { unsigned long value = (unsigned long) v; @@ -376,21 +302,19 @@ insert_i5div (insn, v, errmsg) * errmsg = _("immediate value must be even"); value = 32 - value; - + return insn | ((value & 0x1e) << 17); } static unsigned long -extract_i5div (insn, invalid) - unsigned long insn; - int * invalid ATTRIBUTE_UNUSED; +extract_i5div (unsigned long insn, int * invalid ATTRIBUTE_UNUSED) { unsigned long ret = insn & 0x3c0000; ret >>= 17; ret = 32 - ret; - + return ret; } @@ -401,11 +325,11 @@ extract_i5div (insn, invalid) const struct v850_operand v850_operands[] = { #define UNUSED 0 - { 0, 0, NULL, NULL, 0 }, + { 0, 0, NULL, NULL, 0 }, /* The R1 field in a format 1, 6, 7, or 9 insn. */ #define R1 (UNUSED + 1) - { 5, 0, NULL, NULL, V850_OPERAND_REG }, + { 5, 0, NULL, NULL, V850_OPERAND_REG }, /* As above, but register 0 is not allowed. */ #define R1_NOTR0 (R1 + 1) @@ -421,7 +345,7 @@ const struct v850_operand v850_operands[ /* The imm5 field in a format 2 insn. */ #define I5 (R2_NOTR0 + 1) - { 5, 0, NULL, NULL, V850_OPERAND_SIGNED }, + { 5, 0, NULL, NULL, V850_OPERAND_SIGNED }, /* The unsigned imm5 field in a format 2 insn. */ #define I5U (I5 + 1) @@ -429,7 +353,7 @@ const struct v850_operand v850_operands[ /* The imm16 field in a format 6 insn. */ #define I16 (I5U + 1) - { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, + { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, /* The signed disp7 field in a format 4 insn. */ #define D7 (I16 + 1) @@ -437,7 +361,7 @@ const struct v850_operand v850_operands[ /* The disp16 field in a format 6 insn. */ #define D16_15 (D7 + 1) - { 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED }, + { 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED }, /* The 3 bit immediate field in format 8 insn. */ #define B3 (D16_15 + 1) @@ -465,7 +389,7 @@ const struct v850_operand v850_operands[ /* The imm16 field (unsigned) in a format 6 insn. */ #define I16U (EP + 1) - { 16, 16, NULL, NULL, 0}, + { 16, 16, NULL, NULL, 0}, /* The R2 field as a system register. */ #define SR2 (I16U + 1) @@ -473,7 +397,7 @@ const struct v850_operand v850_operands[ /* The disp16 field in a format 8 insn. */ #define D16 (SR2 + 1) - { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, + { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, /* The DISP9 field in a format 3 insn, relaxable. */ #define D9_RELAX (D16 + 1) @@ -495,7 +419,7 @@ const struct v850_operand v850_operands[ /* The disp16 field in an format 7 unsigned byte load insn. */ #define D16_16 (D5_4 + 1) - { -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 }, + { -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 }, /* Third register in conditional moves. */ #define R3 (D16_16 + 1) @@ -507,31 +431,31 @@ const struct v850_operand v850_operands[ /* The imm9 field in a multiply word. */ #define I9 (MOVCC + 1) - { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED }, + { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED }, /* The unsigned imm9 field in a multiply word. */ #define U9 (I9 + 1) - { 9, 0, insert_u9, extract_u9, 0 }, + { 9, 0, insert_u9, extract_u9, 0 }, /* A list of registers in a prepare/dispose instruction. */ #define LIST12 (U9 + 1) - { -1, 0xffe00001, NULL, NULL, V850E_PUSH_POP }, + { -1, 0xffe00001, NULL, NULL, V850E_PUSH_POP }, /* The IMM6 field in a call instruction. */ #define I6 (LIST12 + 1) - { 6, 0, NULL, NULL, 0 }, + { 6, 0, NULL, NULL, 0 }, /* The 16 bit immediate following a 32 bit instruction. */ #define IMM16 (I6 + 1) - { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850E_IMMEDIATE16 }, + { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850E_IMMEDIATE16 }, /* The 32 bit immediate following a 32 bit instruction. */ #define IMM32 (IMM16 + 1) - { 0, 0, NULL, NULL, V850E_IMMEDIATE32 }, + { 0, 0, NULL, NULL, V850E_IMMEDIATE32 }, /* The imm5 field in a push/pop instruction. */ #define IMM5 (IMM32 + 1) - { 5, 1, NULL, NULL, 0 }, + { 5, 1, NULL, NULL, 0 }, /* Reg2 in dispose instruction. */ #define R2DISPOSE (IMM5 + 1) @@ -543,17 +467,17 @@ const struct v850_operand v850_operands[ /* The IMM5 field in a divide N step instruction. */ #define I5DIV (SP + 1) - { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED }, + { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED }, /* The list of registers in a PUSHMH/POPMH instruction. */ #define LIST18_H (I5DIV + 1) - { -1, 0xfff8000f, NULL, NULL, V850E_PUSH_POP }, + { -1, 0xfff8000f, NULL, NULL, V850E_PUSH_POP }, /* The list of registers in a PUSHML/POPML instruction. */ #define LIST18_L (LIST18_H + 1) /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c. */ { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP }, -} ; +}; /* Reg - Reg instruction format (Format I). */ @@ -586,7 +510,7 @@ const struct v850_operand v850_operands[ OPERANDS is the list of operands. MEMOP specifies which operand (if any) is a memory operand. PROCESSORS specifies which CPU(s) support the opcode. - + The disassembler reads the table in order and prints the first instruction which matches, so this table is sorted to put more specific instructions before more general instructions. It is also @@ -609,7 +533,7 @@ const struct v850_opcode v850_opcodes[] { "dbtrap", one (0xf840), one (0xffff), {UNUSED}, 0, PROCESSOR_V850E1 }, { "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL }, - + /* Load/store instructions. */ { "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E1 }, { "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, @@ -641,7 +565,7 @@ const struct v850_opcode v850_opcodes[] { "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL }, { "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL }, { "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 }, -{ "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 }, +{ "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 }, { "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 2, PROCESSOR_ALL }, { "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, { "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, @@ -675,7 +599,7 @@ const struct v850_opcode v850_opcodes[] { "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, { "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, { "divh", OP (0x02), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, - + { "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL }, { "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, { "mov", one (0x0620), one (0xffe0), {IMM32, R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, @@ -692,7 +616,7 @@ const struct v850_opcode v850_opcodes[] { "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, { "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL }, { "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL }, - + /* Saturated operation instructions. */ { "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, { "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, @@ -772,9 +696,9 @@ const struct v850_opcode v850_opcodes[] { "jnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "jsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "jbr", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - + { "jr", one (0x0780), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL }, -{ "jarl", one (0x0780), two (0x07c0, 0x0001), {D22, R2}, 0, PROCESSOR_ALL}, +{ "jarl", one (0x0780), two (0x07c0, 0x0001), {D22, R2}, 0, PROCESSOR_ALL }, /* Bit manipulation instructions. */ { "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, diff -uprN binutils-2.16.91.0.1/opcodes/vax-dis.c binutils-2.16.91.0.2/opcodes/vax-dis.c --- binutils-2.16.91.0.1/opcodes/vax-dis.c 2005-05-10 15:46:55.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/vax-dis.c 2005-07-20 12:27:29.401845328 -0700 @@ -15,7 +15,8 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include #include @@ -23,14 +24,6 @@ #include "opcode/vax.h" #include "dis-asm.h" -/* Local function prototypes */ -static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *)); -static int print_insn_arg - PARAMS ((const char *, unsigned char *, bfd_vma, disassemble_info *)); -static int print_insn_mode - PARAMS ((const char *, int, unsigned char *, bfd_vma, disassemble_info *)); - - static char *reg_names[] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", @@ -53,11 +46,7 @@ static char *entry_mask_bit[] = }; /* Sign-extend an (unsigned char). */ -#if __STDC__ == 1 #define COERCE_SIGNED_CHAR(ch) ((signed char)(ch)) -#else -#define COERCE_SIGNED_CHAR(ch) ((int)(((ch) ^ 0x80) & 0xFF) - 128) -#endif /* Get a 1 byte signed integer. */ #define NEXTBYTE(p) \ @@ -96,9 +85,7 @@ struct private ? 1 : fetch_data ((info), (addr))) static int -fetch_data (info, addr) - struct disassemble_info *info; - bfd_byte *addr; +fetch_data (struct disassemble_info *info, bfd_byte *addr) { int status; struct private *priv = (struct private *) info->private_data; @@ -208,13 +195,165 @@ is_function_entry (struct disassemble_in return FALSE; } +static int +print_insn_mode (const char *d, + int size, + unsigned char *p0, + bfd_vma addr, /* PC for this arg to be relative to. */ + disassemble_info *info) +{ + unsigned char *p = p0; + unsigned char mode, reg; + + /* Fetch and interpret mode byte. */ + mode = (unsigned char) NEXTBYTE (p); + reg = mode & 0xF; + switch (mode & 0xF0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: /* Literal mode $number. */ + if (d[1] == 'd' || d[1] == 'f' || d[1] == 'g' || d[1] == 'h') + (*info->fprintf_func) (info->stream, "$0x%x [%c-float]", mode, d[1]); + else + (*info->fprintf_func) (info->stream, "$0x%x", mode); + break; + case 0x40: /* Index: base-addr[Rn] */ + p += print_insn_mode (d, size, p0 + 1, addr + 1, info); + (*info->fprintf_func) (info->stream, "[%s]", reg_names[reg]); + break; + case 0x50: /* Register: Rn */ + (*info->fprintf_func) (info->stream, "%s", reg_names[reg]); + break; + case 0x60: /* Register deferred: (Rn) */ + (*info->fprintf_func) (info->stream, "(%s)", reg_names[reg]); + break; + case 0x70: /* Autodecrement: -(Rn) */ + (*info->fprintf_func) (info->stream, "-(%s)", reg_names[reg]); + break; + case 0x80: /* Autoincrement: (Rn)+ */ + if (reg == 0xF) + { /* Immediate? */ + int i; + + FETCH_DATA (info, p + size); + (*info->fprintf_func) (info->stream, "$0x"); + if (d[1] == 'd' || d[1] == 'f' || d[1] == 'g' || d[1] == 'h') + { + int float_word; + + float_word = p[0] | (p[1] << 8); + if ((d[1] == 'd' || d[1] == 'f') + && (float_word & 0xff80) == 0x8000) + { + (*info->fprintf_func) (info->stream, "[invalid %c-float]", + d[1]); + } + else + { + for (i = 0; i < size; i++) + (*info->fprintf_func) (info->stream, "%02x", + p[size - i - 1]); + (*info->fprintf_func) (info->stream, " [%c-float]", d[1]); + } + } + else + { + for (i = 0; i < size; i++) + (*info->fprintf_func) (info->stream, "%02x", p[size - i - 1]); + } + p += size; + } + else + (*info->fprintf_func) (info->stream, "(%s)+", reg_names[reg]); + break; + case 0x90: /* Autoincrement deferred: @(Rn)+ */ + if (reg == 0xF) + (*info->fprintf_func) (info->stream, "*0x%x", NEXTLONG (p)); + else + (*info->fprintf_func) (info->stream, "@(%s)+", reg_names[reg]); + break; + case 0xB0: /* Displacement byte deferred: *displ(Rn). */ + (*info->fprintf_func) (info->stream, "*"); + case 0xA0: /* Displacement byte: displ(Rn). */ + if (reg == 0xF) + (*info->print_address_func) (addr + 2 + NEXTBYTE (p), info); + else + (*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTBYTE (p), + reg_names[reg]); + break; + case 0xD0: /* Displacement word deferred: *displ(Rn). */ + (*info->fprintf_func) (info->stream, "*"); + case 0xC0: /* Displacement word: displ(Rn). */ + if (reg == 0xF) + (*info->print_address_func) (addr + 3 + NEXTWORD (p), info); + else + (*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTWORD (p), + reg_names[reg]); + break; + case 0xF0: /* Displacement long deferred: *displ(Rn). */ + (*info->fprintf_func) (info->stream, "*"); + case 0xE0: /* Displacement long: displ(Rn). */ + if (reg == 0xF) + (*info->print_address_func) (addr + 5 + NEXTLONG (p), info); + else + (*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTLONG (p), + reg_names[reg]); + break; + } + + return p - p0; +} + +/* Returns number of bytes "eaten" by the operand, or return -1 if an + invalid operand was found, or -2 if an opcode tabel error was + found. */ + +static int +print_insn_arg (const char *d, + unsigned char *p0, + bfd_vma addr, /* PC for this arg to be relative to. */ + disassemble_info *info) +{ + int arg_len; + + /* Check validity of addressing length. */ + switch (d[1]) + { + case 'b' : arg_len = 1; break; + case 'd' : arg_len = 8; break; + case 'f' : arg_len = 4; break; + case 'g' : arg_len = 8; break; + case 'h' : arg_len = 16; break; + case 'l' : arg_len = 4; break; + case 'o' : arg_len = 16; break; + case 'w' : arg_len = 2; break; + case 'q' : arg_len = 8; break; + default : abort (); + } + + /* Branches have no mode byte. */ + if (d[0] == 'b') + { + unsigned char *p = p0; + + if (arg_len == 1) + (*info->print_address_func) (addr + 1 + NEXTBYTE (p), info); + else + (*info->print_address_func) (addr + 2 + NEXTWORD (p), info); + + return p - p0; + } + + return print_insn_mode (d, arg_len, p0, addr, info); +} + /* Print the vax instruction at address MEMADDR in debugged memory, on INFO->STREAM. Returns length of the instruction, in bytes. */ int -print_insn_vax (memaddr, info) - bfd_vma memaddr; - disassemble_info *info; +print_insn_vax (bfd_vma memaddr, disassemble_info *info) { static bfd_boolean parsed_disassembler_options = FALSE; const struct vot *votp; @@ -223,7 +362,7 @@ print_insn_vax (memaddr, info) struct private priv; bfd_byte *buffer = priv.the_buffer; - info->private_data = (PTR) &priv; + info->private_data = & priv; priv.max_fetched = priv.the_buffer; priv.insn_start = memaddr; @@ -237,10 +376,8 @@ print_insn_vax (memaddr, info) } if (setjmp (priv.bailout) != 0) - { - /* Error return. */ - return -1; - } + /* Error return. */ + return -1; argp = NULL; /* Check if the info buffer has more than one byte left since @@ -275,7 +412,7 @@ print_insn_vax (memaddr, info) for (votp = &votstrs[0]; votp->name[0]; votp++) { - register vax_opcodeT opcode = votp->detail.code; + vax_opcodeT opcode = votp->detail.code; /* 2 byte codes match 2 buffer pos. */ if ((bfd_byte) opcode == buffer[0] @@ -315,158 +452,3 @@ print_insn_vax (memaddr, info) return arg - buffer; } -/* Returns number of bytes "eaten" by the operand, or return -1 if an - invalid operand was found, or -2 if an opcode tabel error was - found. */ - -static int -print_insn_arg (d, p0, addr, info) - const char *d; - unsigned char *p0; - bfd_vma addr; /* PC for this arg to be relative to */ - disassemble_info *info; -{ - int arg_len; - - /* check validity of addressing length */ - switch (d[1]) - { - case 'b' : arg_len = 1; break; - case 'd' : arg_len = 8; break; - case 'f' : arg_len = 4; break; - case 'g' : arg_len = 8; break; - case 'h' : arg_len = 16; break; - case 'l' : arg_len = 4; break; - case 'o' : arg_len = 16; break; - case 'w' : arg_len = 2; break; - case 'q' : arg_len = 8; break; - default : abort(); - } - - /* branches have no mode byte */ - if (d[0] == 'b') - { - unsigned char *p = p0; - - if (arg_len == 1) - (*info->print_address_func) (addr + 1 + NEXTBYTE (p), info); - else - (*info->print_address_func) (addr + 2 + NEXTWORD (p), info); - - return p - p0; - } - - return print_insn_mode (d, arg_len, p0, addr, info); -} - -static int -print_insn_mode (d, size, p0, addr, info) - const char *d; - int size; - unsigned char *p0; - bfd_vma addr; /* PC for this arg to be relative to */ - disassemble_info *info; -{ - unsigned char *p = p0; - unsigned char mode, reg; - - /* fetch and interpret mode byte */ - mode = (unsigned char) NEXTBYTE (p); - reg = mode & 0xF; - switch (mode & 0xF0) - { - case 0x00: - case 0x10: - case 0x20: - case 0x30: /* literal mode $number */ - if (d[1] == 'd' || d[1] == 'f' || d[1] == 'g' || d[1] == 'h') - (*info->fprintf_func) (info->stream, "$0x%x [%c-float]", mode, d[1]); - else - (*info->fprintf_func) (info->stream, "$0x%x", mode); - break; - case 0x40: /* index: base-addr[Rn] */ - p += print_insn_mode (d, size, p0 + 1, addr + 1, info); - (*info->fprintf_func) (info->stream, "[%s]", reg_names[reg]); - break; - case 0x50: /* register: Rn */ - (*info->fprintf_func) (info->stream, "%s", reg_names[reg]); - break; - case 0x60: /* register deferred: (Rn) */ - (*info->fprintf_func) (info->stream, "(%s)", reg_names[reg]); - break; - case 0x70: /* autodecrement: -(Rn) */ - (*info->fprintf_func) (info->stream, "-(%s)", reg_names[reg]); - break; - case 0x80: /* autoincrement: (Rn)+ */ - if (reg == 0xF) - { /* immediate? */ - int i; - - FETCH_DATA (info, p + size); - (*info->fprintf_func) (info->stream, "$0x"); - if (d[1] == 'd' || d[1] == 'f' || d[1] == 'g' || d[1] == 'h') - { - int float_word; - - float_word = p[0] | (p[1] << 8); - if ((d[1] == 'd' || d[1] == 'f') - && (float_word & 0xff80) == 0x8000) - { - (*info->fprintf_func) (info->stream, "[invalid %c-float]", - d[1]); - } - else - { - for (i = 0; i < size; i++) - (*info->fprintf_func) (info->stream, "%02x", - p[size - i - 1]); - (*info->fprintf_func) (info->stream, " [%c-float]", d[1]); - } - } - else - { - for (i = 0; i < size; i++) - (*info->fprintf_func) (info->stream, "%02x", p[size - i - 1]); - } - p += size; - } - else - (*info->fprintf_func) (info->stream, "(%s)+", reg_names[reg]); - break; - case 0x90: /* autoincrement deferred: @(Rn)+ */ - if (reg == 0xF) - (*info->fprintf_func) (info->stream, "*0x%x", NEXTLONG (p)); - else - (*info->fprintf_func) (info->stream, "@(%s)+", reg_names[reg]); - break; - case 0xB0: /* displacement byte deferred: *displ(Rn) */ - (*info->fprintf_func) (info->stream, "*"); - case 0xA0: /* displacement byte: displ(Rn) */ - if (reg == 0xF) - (*info->print_address_func) (addr + 2 + NEXTBYTE (p), info); - else - (*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTBYTE (p), - reg_names[reg]); - break; - case 0xD0: /* displacement word deferred: *displ(Rn) */ - (*info->fprintf_func) (info->stream, "*"); - case 0xC0: /* displacement word: displ(Rn) */ - if (reg == 0xF) - (*info->print_address_func) (addr + 3 + NEXTWORD (p), info); - else - (*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTWORD (p), - reg_names[reg]); - break; - case 0xF0: /* displacement long deferred: *displ(Rn) */ - (*info->fprintf_func) (info->stream, "*"); - case 0xE0: /* displacement long: displ(Rn) */ - if (reg == 0xF) - (*info->print_address_func) (addr + 5 + NEXTLONG (p), info); - else - (*info->fprintf_func) (info->stream, "0x%x(%s)", NEXTLONG (p), - reg_names[reg]); - break; - } - - return p - p0; -} diff -uprN binutils-2.16.91.0.1/opcodes/w65-dis.c binutils-2.16.91.0.2/opcodes/w65-dis.c --- binutils-2.16.91.0.1/opcodes/w65-dis.c 2005-05-10 15:46:55.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/w65-dis.c 2005-07-20 12:27:29.402845163 -0700 @@ -2,19 +2,20 @@ Copyright 1995, 1998, 2000, 2001, 2002, 2005 Free Software Foundation, Inc. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include #include "sysdep.h" @@ -28,25 +29,8 @@ static fprintf_ftype fpr; static void *stream; static struct disassemble_info *local_info; -static void print_operand PARAMS ((int, char *, int *)); - -#if 0 -static char *lname[] = { "r0","r1","r2","r3","r4","r5","r6","r7","s0" }; - -static char * -findname (val) - unsigned int val; -{ - if (val >= 0x10 && val <= 0x20) - return lname[(val - 0x10) / 2]; - return 0; -} -#endif static void -print_operand (lookup, format, args) - int lookup; - char *format; - int *args; +print_operand (int lookup, char *format, int *args) { int val; int c; @@ -58,15 +42,7 @@ print_operand (lookup, format, args) case '$': val = args[(*format++) - '0']; if (lookup) - { -#if 0 - name = findname (val); - if (name) - fpr (stream, "%s", name); - else -#endif - local_info->print_address_func (val, local_info); - } + local_info->print_address_func (val, local_info); else fpr (stream, "0x%x", val); @@ -79,9 +55,7 @@ print_operand (lookup, format, args) } int -print_insn_w65 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_w65 (bfd_vma memaddr, struct disassemble_info *info) { int status = 0; unsigned char insn[4]; @@ -90,13 +64,13 @@ print_insn_w65 (memaddr, info) int X = 0; int M = 0; int args[2]; + stream = info->stream; fpr = info->fprintf_func; local_info = info; + for (i = 0; i < 4 && status == 0; i++) - { - status = info->read_memory_func (memaddr + i, insn + i, 1, info); - } + status = info->read_memory_func (memaddr + i, insn + i, 1, info); for (op = optable; op->val != insn[0]; op++) ; diff -uprN binutils-2.16.91.0.1/opcodes/xstormy16-asm.c binutils-2.16.91.0.2/opcodes/xstormy16-asm.c --- binutils-2.16.91.0.1/opcodes/xstormy16-asm.c 2005-05-10 15:46:55.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/xstormy16-asm.c 2005-07-20 12:27:29.403844999 -0700 @@ -1,26 +1,27 @@ /* Assembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-asm.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -48,12 +49,6 @@ static const char * parse_insn_normal /* -- assembler routines inserted here. */ /* -- asm.c */ -static const char * parse_mem8 - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_small_immediate - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_immediate16 - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); /* The machine-independent code doesn't know how to disambiguate mov (foo),r3 @@ -62,11 +57,10 @@ static const char * parse_immediate16 where 'foo' is a label. This helps it out. */ static const char * -parse_mem8 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_mem8 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { if (**strp == '(') { @@ -101,11 +95,10 @@ parse_mem8 (cd, strp, opindex, valuep) of the small size. This is somewhat tricky. */ static const char * -parse_small_immediate (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_small_immediate (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { bfd_vma value; enum cgen_parse_operand_result result; @@ -116,7 +109,7 @@ parse_small_immediate (cd, strp, opindex errmsg = (* cd->parse_operand_fn) (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE, - &result, &value); + & result, & value); if (errmsg) return errmsg; @@ -128,14 +121,13 @@ parse_small_immediate (cd, strp, opindex return NULL; } -/* Literal scan be either a normal literal, a @hi() or @lo relocation. */ +/* Literal scan be either a normal literal, a @hi() or @lo relocation. */ static const char * -parse_immediate16 (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +parse_immediate16 (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { const char *errmsg; enum cgen_parse_operand_result result; @@ -178,7 +170,7 @@ parse_immediate16 (cd, strp, opindex, va /* -- */ const char * xstormy16_cgen_parse_operand - PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); /* Main entry point for operand parsing. @@ -194,11 +186,10 @@ const char * xstormy16_cgen_parse_operan the handlers. */ const char * -xstormy16_cgen_parse_operand (cd, opindex, strp, fields) - CGEN_CPU_DESC cd; - int opindex; - const char ** strp; - CGEN_FIELDS * fields; +xstormy16_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) { const char * errmsg = NULL; /* Used by scalar operands that still need to be parsed. */ @@ -294,8 +285,7 @@ cgen_parse_fn * const xstormy16_cgen_par }; void -xstormy16_cgen_init_asm (cd) - CGEN_CPU_DESC cd; +xstormy16_cgen_init_asm (CGEN_CPU_DESC cd) { xstormy16_cgen_init_opcode_table (cd); xstormy16_cgen_init_ibld_table (cd); @@ -678,30 +668,3 @@ xstormy16_cgen_assemble_insn (CGEN_CPU_D return NULL; } } - -#if 0 /* This calls back to GAS which we can't do without care. */ - -/* Record each member of OPVALS in the assembler's symbol table. - This lets GAS parse registers for us. - ??? Interesting idea but not currently used. */ - -/* Record each member of OPVALS in the assembler's symbol table. - FIXME: Not currently used. */ - -void -xstormy16_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) -{ - CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); - const CGEN_KEYWORD_ENTRY * ke; - - while ((ke = cgen_keyword_search_next (& search)) != NULL) - { -#if 0 /* Unnecessary, should be done in the search routine. */ - if (! xstormy16_cgen_opval_supported (ke)) - continue; -#endif - cgen_asm_record_register (cd, ke->name, ke->value); - } -} - -#endif /* 0 */ diff -uprN binutils-2.16.91.0.1/opcodes/xstormy16-desc.c binutils-2.16.91.0.2/opcodes/xstormy16-desc.c --- binutils-2.16.91.0.1/opcodes/xstormy16-desc.c 2005-05-10 15:46:55.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/xstormy16-desc.c 2005-07-20 12:27:29.405844669 -0700 @@ -1160,27 +1160,23 @@ static const CGEN_IBASE xstormy16_cgen_i #undef A /* Initialize anything needed to be done once, before any cpu_open call. */ -static void init_tables PARAMS ((void)); static void -init_tables () +init_tables (void) { } -static const CGEN_MACH * lookup_mach_via_bfd_name - PARAMS ((const CGEN_MACH *, const char *)); -static void build_hw_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_operand_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_insn_table PARAMS ((CGEN_CPU_TABLE *)); -static void xstormy16_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *)); +static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); +static void build_hw_table (CGEN_CPU_TABLE *); +static void build_ifield_table (CGEN_CPU_TABLE *); +static void build_operand_table (CGEN_CPU_TABLE *); +static void build_insn_table (CGEN_CPU_TABLE *); +static void xstormy16_cgen_rebuild_tables (CGEN_CPU_TABLE *); /* Subroutine of xstormy16_cgen_cpu_open to look up a mach via its bfd name. */ static const CGEN_MACH * -lookup_mach_via_bfd_name (table, name) - const CGEN_MACH *table; - const char *name; +lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) { while (table->name) { @@ -1194,8 +1190,7 @@ lookup_mach_via_bfd_name (table, name) /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */ static void -build_hw_table (cd) - CGEN_CPU_TABLE *cd; +build_hw_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; @@ -1221,8 +1216,7 @@ build_hw_table (cd) /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */ static void -build_ifield_table (cd) - CGEN_CPU_TABLE *cd; +build_ifield_table (CGEN_CPU_TABLE *cd) { cd->ifld_table = & xstormy16_cgen_ifld_table[0]; } @@ -1230,8 +1224,7 @@ build_ifield_table (cd) /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table. */ static void -build_operand_table (cd) - CGEN_CPU_TABLE *cd; +build_operand_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; @@ -1239,8 +1232,7 @@ build_operand_table (cd) /* MAX_OPERANDS is only an upper bound on the number of selected entries. However each entry is indexed by it's enum so there can be holes in the table. */ - const CGEN_OPERAND **selected = - (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); cd->operand_table.init_entries = init; cd->operand_table.entry_size = sizeof (CGEN_OPERAND); @@ -1263,12 +1255,11 @@ build_operand_table (cd) operand elements to be in the table [which they mightn't be]. */ static void -build_insn_table (cd) - CGEN_CPU_TABLE *cd; +build_insn_table (CGEN_CPU_TABLE *cd) { int i; const CGEN_IBASE *ib = & xstormy16_cgen_insn_table[0]; - CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); for (i = 0; i < MAX_INSNS; ++i) @@ -1281,8 +1272,7 @@ build_insn_table (cd) /* Subroutine of xstormy16_cgen_cpu_open to rebuild the tables. */ static void -xstormy16_cgen_rebuild_tables (cd) - CGEN_CPU_TABLE *cd; +xstormy16_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) { int i; unsigned int isas = cd->isas; @@ -1294,7 +1284,7 @@ xstormy16_cgen_rebuild_tables (cd) #define UNSET (CGEN_SIZE_UNKNOWN + 1) cd->default_insn_bitsize = UNSET; cd->base_insn_bitsize = UNSET; - cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) if (((1 << i) & isas) != 0) @@ -1306,7 +1296,7 @@ xstormy16_cgen_rebuild_tables (cd) if (cd->default_insn_bitsize == UNSET) cd->default_insn_bitsize = isa->default_insn_bitsize; else if (isa->default_insn_bitsize == cd->default_insn_bitsize) - ; /* this is ok */ + ; /* This is ok. */ else cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; @@ -1315,7 +1305,7 @@ xstormy16_cgen_rebuild_tables (cd) if (cd->base_insn_bitsize == UNSET) cd->base_insn_bitsize = isa->base_insn_bitsize; else if (isa->base_insn_bitsize == cd->base_insn_bitsize) - ; /* this is ok */ + ; /* This is ok. */ else cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; @@ -1427,12 +1417,12 @@ xstormy16_cgen_cpu_open (enum cgen_cpu_o } va_end (ap); - /* mach unspecified means "all" */ + /* Mach unspecified means "all". */ if (machs == 0) machs = (1 << MAX_MACHS) - 1; - /* base mach is always selected */ + /* Base mach is always selected. */ machs |= 1; - /* isa unspecified means "all" */ + /* ISA unspecified means "all". */ if (isas == 0) isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) @@ -1465,9 +1455,7 @@ xstormy16_cgen_cpu_open (enum cgen_cpu_o MACH_NAME is the bfd name of the mach. */ CGEN_CPU_DESC -xstormy16_cgen_cpu_open_1 (mach_name, endian) - const char *mach_name; - enum cgen_endian endian; +xstormy16_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) { return xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, CGEN_CPU_OPEN_ENDIAN, endian, @@ -1480,8 +1468,7 @@ xstormy16_cgen_cpu_open_1 (mach_name, en place as some simulator ports use this but they don't use libopcodes. */ void -xstormy16_cgen_cpu_close (cd) - CGEN_CPU_DESC cd; +xstormy16_cgen_cpu_close (CGEN_CPU_DESC cd) { unsigned int i; const CGEN_INSN *insns; @@ -1490,23 +1477,17 @@ xstormy16_cgen_cpu_close (cd) { insns = cd->macro_insn_table.init_entries; for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) - { - if (CGEN_INSN_RX ((insns))) - regfree (CGEN_INSN_RX (insns)); - } + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); } if (cd->insn_table.init_entries) { insns = cd->insn_table.init_entries; for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) - { - if (CGEN_INSN_RX (insns)) - regfree (CGEN_INSN_RX (insns)); - } - } - - + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } if (cd->macro_insn_table.init_entries) free ((CGEN_INSN *) cd->macro_insn_table.init_entries); diff -uprN binutils-2.16.91.0.1/opcodes/xstormy16-dis.c binutils-2.16.91.0.2/opcodes/xstormy16-dis.c --- binutils-2.16.91.0.1/opcodes/xstormy16-dis.c 2005-05-10 15:46:55.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/xstormy16-dis.c 2005-07-20 12:27:29.413843350 -0700 @@ -1,27 +1,27 @@ /* Disassembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-dis.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 -Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -56,12 +56,11 @@ static int read_insn (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, unsigned long *); -/* -- disassembler routines inserted here */ +/* -- disassembler routines inserted here. */ void xstormy16_cgen_print_operand - PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, - void const *, bfd_vma, int)); + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); /* Main entry point for printing operands. XINFO is a `void *' and not a `disassemble_info *' to not put a requirement @@ -79,16 +78,15 @@ void xstormy16_cgen_print_operand the handlers. */ void -xstormy16_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) - CGEN_CPU_DESC cd; - int opindex; - PTR xinfo; - CGEN_FIELDS *fields; - void const *attrs ATTRIBUTE_UNUSED; - bfd_vma pc; - int length; +xstormy16_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) { - disassemble_info *info = (disassemble_info *) xinfo; + disassemble_info *info = (disassemble_info *) xinfo; switch (opindex) { @@ -180,8 +178,7 @@ cgen_print_fn * const xstormy16_cgen_pri void -xstormy16_cgen_init_dis (cd) - CGEN_CPU_DESC cd; +xstormy16_cgen_init_dis (CGEN_CPU_DESC cd) { xstormy16_cgen_init_opcode_table (cd); xstormy16_cgen_init_ibld_table (cd); @@ -233,7 +230,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUT /* Print the operand as directed by the attributes. */ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) - ; /* nothing to do */ + ; /* Nothing to do. */ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) (*info->print_address_func) (value, info); else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) @@ -315,6 +312,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UN unsigned long *insn_value) { int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) { (*info->memory_error_func) (status, pc, info); @@ -419,13 +417,13 @@ print_insn (CGEN_CPU_DESC cd, length = CGEN_EXTRACT_FN (cd, insn) (cd, insn, &ex_info, insn_value_cropped, &fields, pc); - /* length < 0 -> error */ + /* Length < 0 -> error. */ if (length < 0) return length; if (length > 0) { CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); - /* length is in bits, result is in bytes */ + /* Length is in bits, result is in bytes. */ return length / 8; } } @@ -475,7 +473,8 @@ default_print_insn (CGEN_CPU_DESC cd, bf Print one instruction from PC on INFO->STREAM. Return the size of the instruction (in bytes). */ -typedef struct cpu_desc_list { +typedef struct cpu_desc_list +{ struct cpu_desc_list *next; int isa; int mach; @@ -560,7 +559,7 @@ print_insn_xstormy16 (bfd_vma pc, disass if (!cd) abort (); - /* save this away for future reference */ + /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; cl->isa = isa; diff -uprN binutils-2.16.91.0.1/opcodes/xstormy16-ibld.c binutils-2.16.91.0.2/opcodes/xstormy16-ibld.c --- binutils-2.16.91.0.1/opcodes/xstormy16-ibld.c 2005-05-10 15:46:55.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/xstormy16-ibld.c 2005-07-20 12:27:29.415843020 -0700 @@ -1,25 +1,26 @@ /* Instruction building/extraction support for xstormy16. -*- C -*- -THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. -- the resultant file is machine generated, cgen-ibld.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -35,9 +36,9 @@ along with this program; if not, write t #include "opintl.h" #include "safe-ctype.h" -#undef min +#undef min #define min(a,b) ((a) < (b) ? (a) : (b)) -#undef max +#undef max #define max(a,b) ((a) > (b) ? (a) : (b)) /* Used by the ifield rtx function. */ @@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd, if (length == 0) return NULL; -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - if (word_length > 32) abort (); @@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd, #if CGEN_INT_INSN_P /* Cover function to store an insn value into an integral insn. Must go here - because it needs -desc.h for CGEN_INT_INSN_P. */ + because it needs -desc.h for CGEN_INT_INSN_P. */ static void put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, @@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATT int shift = insn_length - length; /* Written this way to avoid undefined behaviour. */ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); } } @@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd, { unsigned long x; int shift; -#if 0 - int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; -#endif + x = cgen_get_insn_value (cd, bufp, word_length); if (CGEN_INSN_LSB0_P) @@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd, return 1; } -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - if (word_length > 32) abort (); @@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd, return CGEN_INSN_BITSIZE (insn); } -/* machine generated code added here */ +/* Machine generated code added here. */ const char * xstormy16_cgen_insert_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); /* Main entry point for operand insertion. @@ -559,12 +547,11 @@ const char * xstormy16_cgen_insert_opera resolved during parsing. */ const char * -xstormy16_cgen_insert_operand (cd, opindex, fields, buffer, pc) - CGEN_CPU_DESC cd; - int opindex; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc ATTRIBUTE_UNUSED; +xstormy16_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) { const char * errmsg = NULL; unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); @@ -686,8 +673,7 @@ xstormy16_cgen_insert_operand (cd, opind } int xstormy16_cgen_extract_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - CGEN_FIELDS *, bfd_vma)); + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); /* Main entry point for operand extraction. The result is <= 0 for error, >0 for success. @@ -705,13 +691,12 @@ int xstormy16_cgen_extract_operand the handlers. */ int -xstormy16_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) - CGEN_CPU_DESC cd; - int opindex; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS * fields; - bfd_vma pc; +xstormy16_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) { /* Assume success (for those operands that are nops). */ int length = 1; @@ -843,10 +828,8 @@ cgen_extract_fn * const xstormy16_cgen_e extract_insn_normal, }; -int xstormy16_cgen_get_int_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); -bfd_vma xstormy16_cgen_get_vma_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +int xstormy16_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma xstormy16_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); /* Getting values from cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they return. @@ -854,10 +837,9 @@ bfd_vma xstormy16_cgen_get_vma_operand not appropriate. */ int -xstormy16_cgen_get_int_operand (cd, opindex, fields) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - const CGEN_FIELDS * fields; +xstormy16_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) { int value; @@ -947,10 +929,9 @@ xstormy16_cgen_get_int_operand (cd, opin } bfd_vma -xstormy16_cgen_get_vma_operand (cd, opindex, fields) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - const CGEN_FIELDS * fields; +xstormy16_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) { bfd_vma value; @@ -1039,10 +1020,8 @@ xstormy16_cgen_get_vma_operand (cd, opin return value; } -void xstormy16_cgen_set_int_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); -void xstormy16_cgen_set_vma_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); +void xstormy16_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void xstormy16_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); /* Stuffing values in cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they accept. @@ -1050,11 +1029,10 @@ void xstormy16_cgen_set_vma_operand not appropriate. */ void -xstormy16_cgen_set_int_operand (cd, opindex, fields, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - CGEN_FIELDS * fields; - int value; +xstormy16_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) { switch (opindex) { @@ -1140,11 +1118,10 @@ xstormy16_cgen_set_int_operand (cd, opin } void -xstormy16_cgen_set_vma_operand (cd, opindex, fields, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - CGEN_FIELDS * fields; - bfd_vma value; +xstormy16_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) { switch (opindex) { @@ -1232,8 +1209,7 @@ xstormy16_cgen_set_vma_operand (cd, opin /* Function to call before using the instruction builder tables. */ void -xstormy16_cgen_init_ibld_table (cd) - CGEN_CPU_DESC cd; +xstormy16_cgen_init_ibld_table (CGEN_CPU_DESC cd) { cd->insert_handlers = & xstormy16_cgen_insert_handlers[0]; cd->extract_handlers = & xstormy16_cgen_extract_handlers[0]; diff -uprN binutils-2.16.91.0.1/opcodes/xstormy16-opc.c binutils-2.16.91.0.2/opcodes/xstormy16-opc.c --- binutils-2.16.91.0.1/opcodes/xstormy16-opc.c 2005-05-10 15:46:55.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/xstormy16-opc.c 2005-07-20 12:27:29.416842855 -0700 @@ -33,10 +33,10 @@ with this program; if not, write to the /* The hash functions are recorded here to help keep assembler code out of the disassembler and vice versa. */ -static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int asm_hash_insn PARAMS ((const char *)); -static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); /* Instruction formats. */ @@ -1144,14 +1144,10 @@ dis_hash_insn (buf, value) return CGEN_DIS_HASH (buf, value); } -static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int)); - /* Set the recorded length of the insn in the CGEN_FIELDS struct. */ static void -set_fields_bitsize (fields, size) - CGEN_FIELDS *fields; - int size; +set_fields_bitsize (CGEN_FIELDS *fields, int size) { CGEN_FIELDS_BITSIZE (fields) = size; } @@ -1160,15 +1156,15 @@ set_fields_bitsize (fields, size) This plugs the opcode entries and macro instructions into the cpu table. */ void -xstormy16_cgen_init_opcode_table (cd) - CGEN_CPU_DESC cd; +xstormy16_cgen_init_opcode_table (CGEN_CPU_DESC cd) { int i; int num_macros = (sizeof (xstormy16_cgen_macro_insn_table) / sizeof (xstormy16_cgen_macro_insn_table[0])); const CGEN_IBASE *ib = & xstormy16_cgen_macro_insn_table[0]; const CGEN_OPCODE *oc = & xstormy16_cgen_macro_insn_opcode_table[0]; - CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN)); + CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); for (i = 0; i < num_macros; ++i) { diff -uprN binutils-2.16.91.0.1/opcodes/z8kgen.c binutils-2.16.91.0.2/opcodes/z8kgen.c --- binutils-2.16.91.0.1/opcodes/z8kgen.c 2005-05-10 15:46:55.000000000 -0700 +++ binutils-2.16.91.0.2/opcodes/z8kgen.c 2005-07-20 12:27:29.418842526 -0700 @@ -1,4 +1,4 @@ -/* Copyright 2001, 2002, 2003 Free Software Foundation, Inc. +/* Copyright 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of GNU Binutils. @@ -904,7 +904,7 @@ static void internal (void) { int c = count (); - struct op *new = (struct op *) xmalloc (sizeof (struct op) * c); + struct op *new = xmalloc (sizeof (struct op) * c); struct op *p = opt; memcpy (new, p, c * sizeof (struct op)); @@ -960,12 +960,12 @@ gas (void) struct op *p = opt; int idx = -1; char *oldname = ""; - struct op *new = (struct op *) xmalloc (sizeof (struct op) * c); + struct op *new = xmalloc (sizeof (struct op) * c); memcpy (new, p, c * sizeof (struct op)); /* Sort all names in table alphabetically. */ - qsort (new, c, sizeof (struct op), (int (*)(const void *, const void *))func); + qsort (new, c, sizeof (struct op), (int (*)(const void *, const void *)) func); printf ("/* DO NOT EDIT! -*- buffer-read-only: t -*-\n"); printf (" This file is automatically generated by z8kgen. */\n\n"); @@ -1251,7 +1251,7 @@ gas (void) printf ("#endif\n"); printf (" const char *name;\n"); printf (" unsigned char opcode;\n"); - printf (" void (*func) PARAMS ((void));\n"); + printf (" void (*func) (void);\n"); printf (" unsigned int arg_info[4];\n"); printf (" unsigned int byte_info[%d];\n", BYTE_INFO_LEN); printf (" int noperands;\n"); diff -uprN binutils-2.16.91.0.1/patches/bfd-dwarf-addr-3.patch binutils-2.16.91.0.2/patches/bfd-dwarf-addr-3.patch --- binutils-2.16.91.0.1/patches/bfd-dwarf-addr-3.patch 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/patches/bfd-dwarf-addr-3.patch 1969-12-31 16:00:00.000000000 -0800 @@ -1,81 +0,0 @@ -2005-06-06 H.J. Lu - - * dwarf2.c (varinfo): Add addr. - (lookup_symbol_in_variable_table): Also check addr. - (scan_unit_for_symbols): Set addr for variable. - (comp_unit_find_line): Updated. - ---- bfd/dwarf2.c.addr 2005-06-06 08:45:04.000000000 -0700 -+++ bfd/dwarf2.c 2005-06-06 18:13:02.000000000 -0700 -@@ -719,6 +719,7 @@ struct varinfo - int line; - int tag; - char *name; -+ bfd_vma addr; - /* Where the symbol is defined */ - asection *sec; - /* Is this a stack variable? */ -@@ -1500,6 +1501,7 @@ lookup_symbol_in_function_table (struct - static bfd_boolean - lookup_symbol_in_variable_table (struct comp_unit *unit, - asymbol *sym, -+ bfd_vma addr, - const char **filename_ptr, - unsigned int *linenumber_ptr) - { -@@ -1509,6 +1511,9 @@ lookup_symbol_in_variable_table (struct - - for (each = unit->variable_table; each; each = each->prev_var) - if (each->stack == 0 -+ && each->file != NULL -+ && each->name != NULL -+ && each->addr == addr - && (!each->sec || each->sec == sec) - && strcmp (name, each->name) == 0) - break; -@@ -1754,21 +1759,23 @@ scan_unit_for_symbols (struct comp_unit - break; - - case DW_AT_location: -- if (var->stack) -+ switch (attr.form) - { -- switch (attr.form) -+ case DW_FORM_block: -+ case DW_FORM_block1: -+ case DW_FORM_block2: -+ case DW_FORM_block4: -+ if (*attr.u.blk->data == DW_OP_addr) - { -- case DW_FORM_block: -- case DW_FORM_block1: -- case DW_FORM_block2: -- case DW_FORM_block4: -- if (*attr.u.blk->data == DW_OP_addr) -- var->stack = 0; -- break; -- -- default: -- break; -+ var->stack = 0; -+ var->addr = bfd_get ((attr.u.blk->size - 1) * 8, -+ unit->abfd, -+ attr.u.blk->data + 1); - } -+ break; -+ -+ default: -+ break; - } - break; - -@@ -2078,7 +2085,8 @@ comp_unit_find_line (struct comp_unit *u - filename_ptr, - linenumber_ptr); - else -- return lookup_symbol_in_variable_table (unit, sym, filename_ptr, -+ return lookup_symbol_in_variable_table (unit, sym, addr, -+ filename_ptr, - linenumber_ptr); - } - diff -uprN binutils-2.16.91.0.1/patches/bfd-elf-vsb-1.patch binutils-2.16.91.0.2/patches/bfd-elf-vsb-1.patch --- binutils-2.16.91.0.1/patches/bfd-elf-vsb-1.patch 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/patches/bfd-elf-vsb-1.patch 1969-12-31 16:00:00.000000000 -0800 @@ -1,21 +0,0 @@ -2005-05-27 H.J. Lu - - PR 975 - * elflink.c (_bfd_elf_symbol_refs_local_p): Only undefined - symbol with default visibility is local. - ---- bfd/elflink.c.vsb 2005-05-19 10:38:30.000000000 -0700 -+++ bfd/elflink.c 2005-05-27 17:03:01.000000000 -0700 -@@ -2572,8 +2572,10 @@ _bfd_elf_symbol_refs_local_p (struct elf - if (ELF_COMMON_DEF_P (h)) - /* Do nothing. */; - /* If we don't have a definition in a regular file, then we can't -- resolve locally. The sym is either undefined or dynamic. */ -- else if (!h->def_regular) -+ resolve locally unless it has non-default visibility . The sym -+ is either undefined or dynamic. */ -+ else if (!h->def_regular -+ && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT) - return FALSE; - - /* Forced local symbols resolve locally. */ diff -uprN binutils-2.16.91.0.1/patches/binutils-provide-3.patch binutils-2.16.91.0.2/patches/binutils-provide-3.patch --- binutils-2.16.91.0.1/patches/binutils-provide-3.patch 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/patches/binutils-provide-3.patch 1969-12-31 16:00:00.000000000 -0800 @@ -1,322 +0,0 @@ -bfd/ - -2005-05-31 H.J. Lu - - * elf-bfd.h (elf_link_hash_entry): Add the provide field. - - * elflink.c (bfd_elf_set_symbol): Set the provide field to 1. - (_bfd_elf_provide_section_bound_symbols): Also provide the - symbol if the provide field is non-zero. - -ld/ - -2005-05-31 H.J. Lu - - * emultempl/aix.em (ld_${EMULATION_NAME}_emulation): Set to the - provide_symbols field to NULL. - * emultempl/armcoff.em: Likewise. - * emultempl/beos.em: Likewise. - * emultempl/generic.em: Likewise. - * emultempl/gld960.em: Likewise. - * emultempl/gld960c.em: Likewise. - * emultempl/linux.em: Likewise. - * emultempl/lnk960.em: Likewise. - * emultempl/m68kcoff.em: Likewise. - * emultempl/pe.em: Likewise. - * emultempl/sunos.em: Likewise. - * emultempl/ticoff.em: Likewise. - * emultempl/vanilla.em: Likewise. - - * emultempl/elf32.em (gld${EMULATION_NAME}_provide_init_fini_syms): - Renamd to ... - (gld${EMULATION_NAME}_provide_symbols): This. - - * emultempl/elf32.em (gld${EMULATION_NAME}_finish): Remove call - to gld${EMULATION_NAME}_provide_init_fini_syms. - * emultempl/hppaelf.em: Likewise. - * emultempl/ppc64elf.em: Likewise. - - * ldemul.c (ldemul_provide_symbols): New. - - * ldemul.h (ldemul_provide_symbols): New. - (ld_emulation_xfer_struct): Add the provide_symbols field. - - * ldlang.c (lang_do_assignments): Call ldemul_provide_symbols. - ---- binutils/bfd/elf-bfd.h.provide 2005-06-09 09:06:41.000000000 -0700 -+++ binutils/bfd/elf-bfd.h 2005-06-09 09:06:41.000000000 -0700 -@@ -172,6 +172,10 @@ struct elf_link_hash_entry - matters. */ - unsigned int pointer_equality_needed : 1; - -+ /* Symbol is provided by linker emulation. */ -+ unsigned int provide: 1; -+ -+ /* Symbol is referenced by a shared object. */ - /* String table index in .dynstr if this is a dynamic symbol. */ - unsigned long dynstr_index; - ---- binutils/bfd/elflink.c.provide 2005-06-09 09:06:41.000000000 -0700 -+++ binutils/bfd/elflink.c 2005-06-09 09:06:41.000000000 -0700 -@@ -9828,6 +9828,7 @@ bfd_elf_set_symbol (struct elf_link_hash - h->root.u.def.section = bfd_abs_section_ptr; - h->root.u.def.value = val; - h->def_regular = 1; -+ h->provide = 1; - h->type = STT_OBJECT; - h->other = STV_HIDDEN | (h->other & ~ ELF_ST_VISIBILITY (-1)); - h->forced_local = 1; -@@ -9865,13 +9866,15 @@ _bfd_elf_provide_section_bound_symbols ( - hs = elf_link_hash_lookup (elf_hash_table (info), start, FALSE, - FALSE, FALSE); - do_start = (hs != NULL -- && (hs->root.type == bfd_link_hash_undefined -+ && (hs->provide -+ || hs->root.type == bfd_link_hash_undefined - || hs->root.type == bfd_link_hash_undefweak)); - - he = elf_link_hash_lookup (elf_hash_table (info), end, FALSE, - FALSE, FALSE); - do_end = (he != NULL -- && (he->root.type == bfd_link_hash_undefined -+ && (he->provide -+ || he->root.type == bfd_link_hash_undefined - || he->root.type == bfd_link_hash_undefweak)); - - if (!do_start && !do_end) ---- binutils/ld/emultempl/aix.em.provide 2005-05-12 09:59:24.000000000 -0700 -+++ binutils/ld/emultempl/aix.em 2005-06-09 09:06:41.000000000 -0700 -@@ -1348,6 +1348,7 @@ struct ld_emulation_xfer_struct ld_${EMU - 0, /* open_dynamic_archive */ - 0, /* place_orphan */ - 0, /* set_symbols */ -+ 0, /* provide_symbols */ - gld${EMULATION_NAME}_parse_args, - gld${EMULATION_NAME}_add_options, - gld${EMULATION_NAME}_handle_option, ---- binutils/ld/emultempl/armcoff.em.provide 2005-05-12 09:59:24.000000000 -0700 -+++ binutils/ld/emultempl/armcoff.em 2005-06-09 09:06:41.000000000 -0700 -@@ -268,6 +268,7 @@ struct ld_emulation_xfer_struct ld_${EMU - NULL, /* open dynamic archive */ - NULL, /* place orphan */ - NULL, /* set symbols */ -+ NULL, /* provide symbols */ - NULL, /* parse_args */ - gld${EMULATION_NAME}_add_options, - gld${EMULATION_NAME}_handle_option, ---- binutils/ld/emultempl/beos.em.provide 2005-06-01 08:51:13.000000000 -0700 -+++ binutils/ld/emultempl/beos.em 2005-06-09 09:06:41.000000000 -0700 -@@ -775,6 +775,7 @@ struct ld_emulation_xfer_struct ld_${EMU - NULL, /* open dynamic archive */ - gld${EMULATION_NAME}_place_orphan, - gld_${EMULATION_NAME}_set_symbols, -+ NULL, /* provide_symbols */ - NULL, /* parse_args */ - gld${EMULATION_NAME}_add_options, - gld${EMULATION_NAME}_handle_option, ---- binutils/ld/emultempl/elf32.em.provide 2005-06-09 09:00:48.000000000 -0700 -+++ binutils/ld/emultempl/elf32.em 2005-06-09 09:06:41.000000000 -0700 -@@ -62,7 +62,7 @@ static bfd_boolean gld${EMULATION_NAME}_ - (lang_input_statement_type *file, asection *s); - static void gld${EMULATION_NAME}_layout_sections_again (void); - static void gld${EMULATION_NAME}_strip_empty_sections (void); --static void gld${EMULATION_NAME}_provide_init_fini_syms (void); -+static void gld${EMULATION_NAME}_provide_symbols (void); - static void gld${EMULATION_NAME}_finish (void) ATTRIBUTE_UNUSED; - - EOF -@@ -1475,7 +1475,7 @@ gld${EMULATION_NAME}_provide_bound_symbo - section alignment affecting where the section starts. */ - - static void --gld${EMULATION_NAME}_provide_init_fini_syms (void) -+gld${EMULATION_NAME}_provide_symbols (void) - { - if (!link_info.relocatable && link_info.executable) - { -@@ -1541,7 +1541,6 @@ gld${EMULATION_NAME}_finish (void) - gld${EMULATION_NAME}_layout_sections_again (); - - gld${EMULATION_NAME}_strip_empty_sections (); -- gld${EMULATION_NAME}_provide_init_fini_syms (); - } - EOF - fi -@@ -1920,6 +1919,7 @@ struct ld_emulation_xfer_struct ld_${EMU - ${LDEMUL_OPEN_DYNAMIC_ARCHIVE-gld${EMULATION_NAME}_open_dynamic_archive}, - ${LDEMUL_PLACE_ORPHAN-gld${EMULATION_NAME}_place_orphan}, - ${LDEMUL_SET_SYMBOLS-NULL}, -+ ${LDEMUL_PROVIDE_SYMBOLS-gld${EMULATION_NAME}_provide_symbols}, - ${LDEMUL_PARSE_ARGS-NULL}, - gld${EMULATION_NAME}_add_options, - gld${EMULATION_NAME}_handle_option, ---- binutils/ld/emultempl/generic.em.provide 2005-05-12 09:59:24.000000000 -0700 -+++ binutils/ld/emultempl/generic.em 2005-06-09 09:06:41.000000000 -0700 -@@ -136,6 +136,7 @@ struct ld_emulation_xfer_struct ld_${EMU - ${LDEMUL_OPEN_DYNAMIC_ARCHIVE-NULL}, - ${LDEMUL_PLACE_ORPHAN-NULL}, - ${LDEMUL_SET_SYMBOLS-NULL}, -+ ${LDEMUL_PROVIDE_SYMBOLS-NULL}, - ${LDEMUL_PARSE_ARGS-NULL}, - NULL, /* add_options */ - NULL, /* handle_option */ ---- binutils/ld/emultempl/gld960.em.provide 2005-05-12 09:59:24.000000000 -0700 -+++ binutils/ld/emultempl/gld960.em 2005-06-09 09:06:41.000000000 -0700 -@@ -142,6 +142,7 @@ struct ld_emulation_xfer_struct ld_gld96 - NULL, /* open dynamic archive */ - NULL, /* place orphan */ - NULL, /* set symbols */ -+ NULL, /* provide symbols */ - NULL, /* parse args */ - NULL, /* add_options */ - NULL, /* handle_option */ ---- binutils/ld/emultempl/gld960c.em.provide 2005-05-12 09:59:24.000000000 -0700 -+++ binutils/ld/emultempl/gld960c.em 2005-06-09 09:06:41.000000000 -0700 -@@ -157,6 +157,7 @@ struct ld_emulation_xfer_struct ld_gld96 - NULL, /* open dynamic archive */ - NULL, /* place orphan */ - NULL, /* set symbols */ -+ NULL, /* provide symbols */ - NULL, /* parse args */ - NULL, /* add_options */ - NULL, /* handle_option */ ---- binutils/ld/emultempl/hppaelf.em.provide 2005-05-12 09:59:24.000000000 -0700 -+++ binutils/ld/emultempl/hppaelf.em 2005-06-09 09:06:41.000000000 -0700 -@@ -306,7 +306,6 @@ hppaelf_finish (void) - } - - gld${EMULATION_NAME}_strip_empty_sections (); -- gld${EMULATION_NAME}_provide_init_fini_syms (); - } - - ---- binutils/ld/emultempl/linux.em.provide 2005-05-12 09:59:24.000000000 -0700 -+++ binutils/ld/emultempl/linux.em 2005-06-09 09:06:41.000000000 -0700 -@@ -197,6 +197,7 @@ struct ld_emulation_xfer_struct ld_${EMU - gld${EMULATION_NAME}_open_dynamic_archive, - NULL, /* place orphan */ - NULL, /* set symbols */ -+ NULL, /* provide symbols */ - NULL, /* parse args */ - NULL, /* add_options */ - NULL, /* handle_option */ ---- binutils/ld/emultempl/lnk960.em.provide 2005-05-12 09:59:24.000000000 -0700 -+++ binutils/ld/emultempl/lnk960.em 2005-06-09 09:06:41.000000000 -0700 -@@ -277,6 +277,7 @@ struct ld_emulation_xfer_struct ld_lnk96 - NULL, /* open dynamic archive */ - NULL, /* place orphan */ - NULL, /* set symbols */ -+ NULL, /* provide symbols */ - NULL, /* parse args */ - NULL, /* add_options */ - NULL, /* handle_option */ ---- binutils/ld/emultempl/m68kcoff.em.provide 2005-05-12 09:59:24.000000000 -0700 -+++ binutils/ld/emultempl/m68kcoff.em 2005-06-09 09:06:41.000000000 -0700 -@@ -230,6 +230,7 @@ struct ld_emulation_xfer_struct ld_${EMU - NULL, /* open dynamic archive */ - NULL, /* place orphan */ - NULL, /* set symbols */ -+ NULL, /* provide symbols */ - NULL, /* parse args */ - NULL, /* add_options */ - NULL, /* handle_option */ ---- binutils/ld/emultempl/pe.em.provide 2005-06-01 08:51:13.000000000 -0700 -+++ binutils/ld/emultempl/pe.em 2005-06-09 09:06:41.000000000 -0700 -@@ -1830,6 +1830,7 @@ struct ld_emulation_xfer_struct ld_${EMU - gld_${EMULATION_NAME}_open_dynamic_archive, - gld_${EMULATION_NAME}_place_orphan, - gld_${EMULATION_NAME}_set_symbols, -+ NULL, /* provide_symbols */ - NULL, /* parse_args */ - gld${EMULATION_NAME}_add_options, - gld${EMULATION_NAME}_handle_option, ---- binutils/ld/emultempl/ppc64elf.em.provide 2005-06-09 09:00:48.000000000 -0700 -+++ binutils/ld/emultempl/ppc64elf.em 2005-06-09 09:06:41.000000000 -0700 -@@ -380,7 +380,6 @@ ppc_finish (void) - - ppc64_elf_restore_symbols (&link_info); - gld${EMULATION_NAME}_strip_empty_sections (); -- gld${EMULATION_NAME}_provide_init_fini_syms (); - } - - ---- binutils/ld/emultempl/sunos.em.provide 2005-05-12 09:59:24.000000000 -0700 -+++ binutils/ld/emultempl/sunos.em 2005-06-09 09:06:41.000000000 -0700 -@@ -1021,6 +1021,7 @@ struct ld_emulation_xfer_struct ld_${EMU - NULL, /* open dynamic archive */ - NULL, /* place orphan */ - gld${EMULATION_NAME}_set_symbols, -+ NULL, /* provide_symbols */ - NULL, /* parse args */ - NULL, /* add_options */ - NULL, /* handle_option */ ---- binutils/ld/emultempl/ticoff.em.provide 2005-05-12 09:59:24.000000000 -0700 -+++ binutils/ld/emultempl/ticoff.em 2005-06-09 09:06:41.000000000 -0700 -@@ -170,6 +170,7 @@ struct ld_emulation_xfer_struct ld_${EMU - NULL, /* open dynamic archive */ - NULL, /* place orphan */ - NULL, /* set_symbols */ -+ NULL, /* provide_symbols */ - NULL, /* parse_args */ - gld${EMULATION_NAME}_add_options, - gld${EMULATION_NAME}_handle_option, ---- binutils/ld/emultempl/vanilla.em.provide 2005-05-12 09:59:24.000000000 -0700 -+++ binutils/ld/emultempl/vanilla.em 2005-06-09 09:06:41.000000000 -0700 -@@ -73,6 +73,7 @@ struct ld_emulation_xfer_struct ld_vanil - NULL, /* open dynamic archive */ - NULL, /* place orphan */ - NULL, /* set symbols */ -+ NULL, /* provide symbols */ - NULL, /* parse args */ - NULL, /* add_options */ - NULL, /* handle_option */ ---- binutils/ld/ldemul.c.provide 2005-05-12 09:59:24.000000000 -0700 -+++ binutils/ld/ldemul.c 2005-06-09 09:06:41.000000000 -0700 -@@ -100,6 +100,13 @@ ldemul_set_symbols (void) - } - - void -+ldemul_provide_symbols (void) -+{ -+ if (ld_emulation->provide_symbols) -+ ld_emulation->provide_symbols (); -+} -+ -+void - ldemul_create_output_section_statements (void) - { - if (ld_emulation->create_output_section_statements) ---- binutils/ld/ldemul.h.provide 2005-03-03 09:24:14.000000000 -0800 -+++ binutils/ld/ldemul.h 2005-06-09 09:06:41.000000000 -0700 -@@ -51,6 +51,8 @@ extern void ldemul_finish - (void); - extern void ldemul_set_symbols - (void); -+extern void ldemul_provide_symbols -+ (void); - extern void ldemul_create_output_section_statements - (void); - extern bfd_boolean ldemul_place_orphan -@@ -149,6 +151,10 @@ typedef struct ld_emulation_xfer_struct - reading the script. Used to initialize symbols used in the script. */ - void (*set_symbols) (void); - -+ /* Called in lang_do_assignments. Used to provide symbols by linker -+ emulation. */ -+ void (*provide_symbols) (void); -+ - /* Parse args which the base linker doesn't understand. - Return TRUE if the arg needs no further processing. */ - bfd_boolean (*parse_args) (int, char **); ---- binutils/ld/ldlang.c.provide 2005-06-09 09:06:41.000000000 -0700 -+++ binutils/ld/ldlang.c 2005-06-09 09:07:53.000000000 -0700 -@@ -4665,6 +4665,9 @@ lang_do_assignments (void) - { - lang_statement_iteration++; - lang_do_assignments_1 (statement_list.head, abs_output_section, NULL, 0); -+ -+ /* Assign values for symbols provided by emulation. */ -+ ldemul_provide_symbols (); - } - - /* Fix any .startof. or .sizeof. symbols. When the assemblers see the diff -uprN binutils-2.16.91.0.1/patches/ChangeLog binutils-2.16.91.0.2/patches/ChangeLog --- binutils-2.16.91.0.1/patches/ChangeLog 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/patches/ChangeLog 2005-07-20 12:27:29.435839723 -0700 @@ -1,3 +1,33 @@ +2004-07-11 H.J. Lu + + * binutils-provide-5.patchh: Removed. + + * README: Don't apply binutils-provide-5.patch. + +2004-07-08 H.J. Lu + + * binutils-provide-5.patch: New file. Replace ... + * binutils-provide-4.patch: This. Removed. + * README: Likewise. + +2004-07-07 H.J. Lu + + * bfd-elf-vsb-1.patch: Removed. + + * README: Don't apply bfd-elf-vsb-1.patch. + +2004-07-06 H.J. Lu + + * bfd-dwarf-addr-3.patch: Removed. + + * README: Don't apply bfd-dwarf-addr-3.patch. + +2004-06-30 H.J. Lu + + * binutils-provide-4.patch: New file. Replace ... + * binutils-provide-3.patch: This. Removed. + * README: Likewise. + 2004-06-22 H.J. Lu * bfd-dwarf-addr-3.patch: New file. Fix DWARF 2 address. diff -uprN binutils-2.16.91.0.1/patches/README binutils-2.16.91.0.2/patches/README --- binutils-2.16.91.0.1/patches/README 2005-06-22 13:53:36.000000000 -0700 +++ binutils-2.16.91.0.2/patches/README 2005-07-20 12:27:29.435839723 -0700 @@ -14,10 +14,7 @@ dir=`dirname $0` -patch -p0 -b --suffix .addr < $dir/bfd-dwarf-addr-3.patch && patch -p1 -b --suffix .exec < $dir/binutils-version-exec-2.patch && -patch -p0 -b --suffix .vsb < $dir/bfd-elf-vsb-1.patch && -patch -p1 -b --suffix .provide < $dir/binutils-provide-3.patch && true [ $? = 0 ] || exit 1 find -name "*.rej" | grep rej && exit 1 diff -uprN binutils-2.16.91.0.1/setup.com binutils-2.16.91.0.2/setup.com --- binutils-2.16.91.0.1/setup.com 1999-06-03 11:01:52.000000000 -0700 +++ binutils-2.16.91.0.2/setup.com 2005-07-20 12:27:26.884260476 -0700 @@ -3,6 +3,5 @@ $! $ define aout [-.INCLUDE.AOUT] $ define coff [-.INCLUDE.COFF] $ define elf [-.INCLUDE.ELF] -$ define mpw [-.INCLUDE.MPW] $ define nlm [-.INCLUDE.NLM] $ define opcode [-.INCLUDE.OPCODE] diff -uprN binutils-2.16.91.0.1/src-release binutils-2.16.91.0.2/src-release --- binutils-2.16.91.0.1/src-release 2004-12-20 11:16:48.000000000 -0800 +++ binutils-2.16.91.0.2/src-release 2005-07-20 12:27:26.893258992 -0700 @@ -13,7 +13,7 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. # # This Makefile contains release scripts for gdb, binutils, and other @@ -159,14 +159,6 @@ do-proto-toplev: $(DEVO_SUPPORT) $(SUPPO done cd etc && $(MAKE) info $(MAKE) distclean - # Kludge for pr gdb/708. 'configure' configures in - # dejagnu/example/calc, but 'make distclean' does not clean in - # dejagnu/example. Someday somebody might fix this in dejagnu, - # and then import a new dejagnu into sourceware. Right now, a - # couple of 'rm' commands will get the gdb snapshots working - # again. -- chastain 2003-08-15 - rm -f dejagnu/example/calc/config.status - rm -f dejagnu/example/calc/config.log # Kludge for pr gdb/857. intl/Makefile.in lacks a couple # of files in the distclean rule. Zack W is planning to make # the gcc version of intl/ the master version and then push @@ -284,30 +276,6 @@ gdb.tar: $(DIST_SUPPORT) $(GDB_SUPPORT_D MD5PROG="$(MD5PROG)" \ SUPPORT_FILES="$(GDB_SUPPORT_DIRS)" -DEJAGNU_SUPPORT_DIRS= tcl expect libiberty -.PHONY: dejagnu.tar.bz2 -dejagnu.tar.bz2: $(DIST_SUPPORT) $(DEJAGNU_SUPPORT_DIRS) dejagnu - $(MAKE) -f $(SELF) gdb-taz TOOL=dejagnu \ - MD5PROG="$(MD5PROG)" \ - SUPPORT_FILES="$(DEJAGNU_SUPPORT_DIRS)" -.PHONY: dejagnu.tar -dejagnu.tar: $(DIST_SUPPORT) $(DEJAGNU_SUPPORT_DIRS) dejagnu - $(MAKE) -f $(SELF) gdb-tar TOOL=dejagnu \ - MD5PROG="$(MD5PROG)" \ - SUPPORT_FILES="$(DEJAGNU_SUPPORT_DIRS)" - -.PHONY: gdb+dejagnu.tar.bz2 -GDBD_SUPPORT_DIRS= $(GDB_SUPPORT_DIRS) tcl expect dejagnu -gdb+dejagnu.tar.bz2: $(DIST_SUPPORT) $(GDBD_SUPPORT_DIRS) gdb - $(MAKE) -f $(SELF) gdb-taz TOOL=gdb PACKAGE=gdb+dejagnu \ - MD5PROG="$(MD5PROG)" \ - SUPPORT_FILES="$(GDBD_SUPPORT_DIRS)" -.PHONY: gdb+dejagnu.tar -gdb+dejagnu.tar: $(DIST_SUPPORT) $(GDBD_SUPPORT_DIRS) gdb - $(MAKE) -f $(SELF) gdb-tar TOOL=gdb PACKAGE=gdb+dejagnu \ - MD5PROG="$(MD5PROG)" \ - SUPPORT_FILES="$(GDBD_SUPPORT_DIRS)" - .PHONY: insight.tar.bz2 INSIGHT_SUPPORT_DIRS= $(GDB_SUPPORT_DIRS) tcl tk itcl libgui insight.tar.bz2: $(DIST_SUPPORT) $(GDB_SUPPORT_DIRS) gdb @@ -320,17 +288,5 @@ insight.tar: $(DIST_SUPPORT) $(GDB_SUPPO MD5PROG="$(MD5PROG)" \ SUPPORT_FILES="$(INSIGHT_SUPPORT_DIRS)" -.PHONY: insight+dejagnu.tar.bz2 -INSIGHTD_SUPPORT_DIRS= $(INSIGHT_SUPPORT_DIRS) expect dejagnu -insight+dejagnu.tar.bz2: $(DIST_SUPPORT) $(INSIGHTD_SUPPORT_DIRS) gdb - $(MAKE) -f $(SELF) gdb-taz TOOL=gdb PACKAGE="insight+dejagnu" \ - MD5PROG="$(MD5PROG)" \ - SUPPORT_FILES="$(INSIGHTD_SUPPORT_DIRS)" -.PHONY: insight+dejagnu.tar -insight+dejagnu.tar: $(DIST_SUPPORT) $(INSIGHTD_SUPPORT_DIRS) gdb - $(MAKE) -f $(SELF) gdb-tar TOOL=gdb PACKAGE="insight+dejagnu" \ - MD5PROG="$(MD5PROG)" \ - SUPPORT_FILES="$(INSIGHTD_SUPPORT_DIRS)" - .NOEXPORT: MAKEOVERRIDES= diff -uprN binutils-2.16.91.0.1/symlink-tree binutils-2.16.91.0.2/symlink-tree --- binutils-2.16.91.0.1/symlink-tree 2004-01-14 13:07:42.000000000 -0800 +++ binutils-2.16.91.0.2/symlink-tree 2005-07-20 12:27:26.894258827 -0700 @@ -15,8 +15,8 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, -# Boston, MA 02111-1307, USA. +# Foundation, Inc., 51 Franklin Street, Fifth Floor, +# Boston, MA 02110-1301, USA. # # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a diff -uprN binutils-2.16.91.0.1/ylwrap binutils-2.16.91.0.2/ylwrap --- binutils-2.16.91.0.1/ylwrap 2005-06-22 13:53:34.000000000 -0700 +++ binutils-2.16.91.0.2/ylwrap 2005-07-20 12:27:26.904257178 -0700 @@ -1,7 +1,7 @@ #! /bin/sh # ylwrap - wrapper for lex/yacc invocations. -scriptversion=2005-02-02.22 +scriptversion=2005-05-14.22 # Copyright (C) 1996, 1997, 1998, 1999, 2001, 2002, 2003, 2004, 2005 # Free Software Foundation, Inc. @@ -20,7 +20,8 @@ scriptversion=2005-02-02.22 # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA +# 02110-1301, USA. # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a