--- linux-2.2.17pre10/Documentation/Configure.help Thu Jul 6 02:05:15 2000 +++ linux/Documentation/Configure.help Thu Jul 6 02:28:54 2000 @@ -5783,6 +5783,16 @@ If unsure, say N here. +Cyclades PC300TOO driver +CONFIG_PC300TOO + This driver is an alternative driver for PC300 PCI cards made by + Cyclades Corp. + If you have such a card, say Y here. This driver requires + Generic HDLC driver and its supporting utility available from + ftp://ftp.pm.waw.pl/pub/Linux/hdlc/ + + If unsure, say N here. + Ethernet (10 or 100Mbit) CONFIG_NET_ETHERNET Ethernet (also called IEEE 802.3 or ISO 8802-2) is the most common --- linux-2.2.17pre10/MAINTAINERS Thu Jul 6 02:05:15 2000 +++ linux/MAINTAINERS Thu Jul 6 02:28:54 2000 @@ -378,7 +378,7 @@ W: http://www.icp-vortex.com/ S: Supported -GENERIC HDLC DRIVER AND N2, C101 AND WANXL DRIVERS +GENERIC HDLC DRIVER AND N2, C101, PC300TOO AND WANXL DRIVERS P: Krzysztof Halasa M: khc@pm.waw.pl W: http://hq.pm.waw.pl/hdlc/ --- linux-2.2.17pre10/net/core/dev.c Thu Jul 6 02:05:31 2000 +++ linux/net/core/dev.c Thu Jul 6 02:28:54 2000 @@ -99,6 +99,7 @@ extern void c101_init(void); extern int wanxl_init(void); extern int cpc_init(void); +extern int pc300too_init(void); extern void sync_ppp_init(void); NET_PROFILE_DEFINE(dev_queue_xmit) @@ -2040,6 +2041,9 @@ #endif #ifdef CONFIG_WANXL wanxl_init(); +#endif +#ifdef CONFIG_PC300TOO + pc300too_init(); #endif #ifdef CONFIG_PC300 cpc_init(); --- linux-2.2.17pre10/drivers/net/Config.in Thu Jul 6 02:05:17 2000 +++ linux/drivers/net/Config.in Thu Jul 6 02:28:54 2000 @@ -327,6 +327,7 @@ if [ "$CONFIG_PC300" != "n" ]; then bool ' Cyclades-PC300 X.25 support (please read help)' CONFIG_PC300_X25 fi + dep_tristate ' Cyclades PC300 support (alternative)' CONFIG_PC300TOO $CONFIG_HDLC fi fi fi --- linux-2.2.17pre10/drivers/net/Makefile Thu Jul 6 02:05:17 2000 +++ linux/drivers/net/Makefile Thu Jul 6 02:28:54 2000 @@ -1011,6 +1011,14 @@ endif endif +ifeq ($(CONFIG_PC300TOO),y) +L_OBJS += pc300too.o +else + ifeq ($(CONFIG_PC300TOO),m) + M_OBJS += pc300too.o + endif +endif + # If anything built-in uses syncppp, then build it into the kernel also. # If not, but a module uses it, build as a module. --- linux-2.2.17pre10/drivers/net/hd64572.h Tue Jul 4 22:50:25 2000 +++ linux/drivers/net/hd64572.h Thu Jul 6 02:28:54 2000 @@ -0,0 +1,233 @@ +#ifndef __HD64572_H +#define __HD64572_H + +/* SCA-II HD64572 register definitions - all addresses for mode 0 + and 2 (Intel MPU). For modes 2 and 3, XOR the address with 0x03. + + Source: HD64572 SCA User's Manual +*/ + +#define ILAR 0x00 /* Illegal Access */ + +/* Wait Controller Registers */ +#define PABR0L 0x20 /* Physical Address Boundary 0 L */ +#define PABR0H 0x21 /* Physical Address Boundary 0 H */ +#define PABR1L 0x22 /* Physical Address Boundary 1 L */ +#define PABR1H 0x23 /* Physical Address Boundary 1 H */ +#define WCRL 0x24 /* Wait Control L */ +#define WCRM 0x25 /* Wait Control M */ +#define WCRH 0x26 /* Wait Control H */ + +/* Interrupt Registers */ +#define IVR 0x60 /* Interrupt Vector */ +#define IMVR 0x64 /* Interrupt Modified Vector */ +#define ITCR 0x68 /* Interrupt Control */ +#define ISR0 0x6c /* Interrupt Status 0 */ +#define ISR1 0x70 /* Interrupt Status 1 */ +#define IER0 0x74 /* Interrupt Enable 0 */ +#define IER1 0x78 /* Interrupt Enable 1 */ + +/* MSCI Channel Registers */ +#define MSCI0_OFFSET 0x00 +#define MSCI1_OFFSET 0x80 + +#define MD0 0x138 /* Mode reg 0 */ +#define MD1 0x139 /* Mode reg 1 */ +#define MD2 0x13A /* Mode reg 2 */ +#define MD3 0x13B /* Mode reg 3 */ +#define CTL 0x130 /* Control reg */ +#define RXS 0x13C /* RX clock source */ +#define TXS 0x13D /* TX clock source */ +#define EXS 0x13E /* External clock input selection */ +#define TMCT 0x144 /* Time constant (Tx) */ +#define TMCR 0x145 /* Time constant (Rx) */ +#define CMD 0x128 /* Command reg */ +#define ST0 0x118 /* Status reg 0 */ +#define ST1 0x119 /* Status reg 1 */ +#define ST2 0x11A /* Status reg 2 */ +#define ST3 0x11B /* Status reg 3 */ +#define ST4 0x11C /* Status reg 4 */ +#define FST 0x11D /* frame Status reg */ +#define IE0 0x120 /* Interrupt enable reg 0 */ +#define IE1 0x121 /* Interrupt enable reg 1 */ +#define IE2 0x122 /* Interrupt enable reg 2 */ +#define IE4 0x124 /* Interrupt enable reg 4 */ +#define FIE 0x125 /* Frame Interrupt enable reg */ +#define SA0 0x140 /* Syn Address reg 0 */ +#define SA1 0x141 /* Syn Address reg 1 */ +#define IDL 0x142 /* Idle register */ +#define TRBL 0x100 /* TX/RX buffer reg L */ +#define TRBK 0x101 /* TX/RX buffer reg K */ +#define TRBJ 0x102 /* TX/RX buffer reg J */ +#define TRBH 0x103 /* TX/RX buffer reg H */ +#define TRC0 0x148 /* TX Ready control reg 0 */ +#define TRC1 0x149 /* TX Ready control reg 1 */ +#define RRC 0x14a /* RX Ready control reg */ +#define CST0 0x108 /* Current Status 0 */ +#define CST1 0x109 /* Current Status 1 */ +#define CST2 0x10A /* Current Status 2 */ +#define CST3 0x10B /* Current Status 3 */ +#define GPO 0x131 /* General Purpose Output Pin Ctl Reg */ +#define TFS 0x14B /* Tx Start Threshold Ctl Reg */ +#define TFN 0x143 /* Inter-transmit-frame Time Fill Ctl Reg */ +#define TBN 0x110 /* Tx Buffer Number Reg */ +#define RBN 0x111 /* Rx Buffer Number Reg */ +#define TNR0 0x150 /* Tx DMA Request Ctl Reg 0 */ +#define TNR1 0x151 /* Tx DMA Request Ctl Reg 1 */ +#define TCR 0x152 /* Tx DMA Critical Request Reg */ +#define RNR 0x154 /* Rx DMA Request Ctl Reg */ +#define RCR 0x156 /* Rx DMA Critical Request Reg */ + +/* Timer Registers */ +#define TIMER0RX_OFFSET 0x00 +#define TIMER0TX_OFFSET 0x10 +#define TIMER1RX_OFFSET 0x20 +#define TIMER1TX_OFFSET 0x30 + +#define TCNTL 0x200 /* Timer Upcounter L */ +#define TCNTH 0x201 /* Timer Upcounter H */ +#define TCONRL 0x204 /* Timer Constant L */ +#define TCONRH 0x205 /* Timer Constant H */ +#define TCSR 0x206 /* Timer Control/Status */ +#define TEPR 0x207 /* Timer Expand Prescale */ + +/* DMA registers */ +#define PCR 0x40 /* DMA priority control reg */ +#define DRR 0x44 /* DMA reset reg */ +#define DMER 0x07 /* DMA Master Enable reg */ +#define BTCR 0x08 /* Burst Tx Ctl Reg */ +#define BOLR 0x0c /* Back-off Length Reg */ +#define DSR_RX(node) (0x48 + node*2) /* DMA Status Reg (Rx) */ +#define DSR_TX(node) (0x49 + node*2) /* DMA Status Reg (Tx) */ +#define DIR_RX(node) (0x4c + node*2) /* DMA IRQ Enable Reg (Rx) */ +#define DIR_TX(node) (0x4d + node*2) /* DMA IRQ Enable Reg (Tx) */ +#define FCT_RX(node) (0x50 + node*2) /* Frame End IRQ Counter (Rx) */ +#define FCT_TX(node) (0x51 + node*2) /* Frame End IRQ Counter (Tx) */ +#define DMR_RX(node) (0x54 + node*2) /* DMA Mode Reg (Rx) */ +#define DMR_TX(node) (0x55 + node*2) /* DMA Mode Reg (Tx) */ +#define DCR_RX(node) (0x58 + node*2) /* DMA Command Reg (Rx) */ +#define DCR_TX(node) (0x59 + node*2) /* DMA Command Reg (Tx) */ + +/* DMA Channel Registers */ +#define DMAC0RX_OFFSET 0x00 +#define DMAC0TX_OFFSET 0x20 +#define DMAC1RX_OFFSET 0x40 +#define DMAC1TX_OFFSET 0x60 + +#define DARL 0x80 /* Dest Addr L (single-block, RX only) */ +#define DARH 0x81 /* Dest Addr H (single-block, RX only) */ +#define DARB 0x82 /* Dest Addr B (single-block, RX only) */ +#define DARBH 0x83 /* Dest Addr BH (single-block, RX only) */ +#define SARL 0x80 /* Source Addr L (single-block, TX only) */ +#define SARH 0x81 /* Source Addr H (single-block, TX only) */ +#define SARB 0x82 /* Source Addr B (single-block, TX only) */ +#define DARBH 0x83 /* Source Addr BH (single-block, TX only) */ +#define BARL 0x80 /* Buffer Addr L (chained-block) */ +#define BARH 0x81 /* Buffer Addr H (chained-block) */ +#define BARB 0x82 /* Buffer Addr B (chained-block) */ +#define BARBH 0x83 /* Buffer Addr BH (chained-block) */ +#define CDAL 0x84 /* Current Descriptor Addr L */ +#define CDAH 0x85 /* Current Descriptor Addr H */ +#define CDAB 0x86 /* Current Descriptor Addr B */ +#define CDABH 0x87 /* Current Descriptor Addr BH */ +#define EDAL 0x88 /* Error Descriptor Addr L */ +#define EDAH 0x89 /* Error Descriptor Addr H */ +#define EDAB 0x8a /* Error Descriptor Addr B */ +#define EDABH 0x8b /* Error Descriptor Addr BH */ +#define BFLL 0x90 /* RX Buffer Length L (only RX) */ +#define BFLH 0x91 /* RX Buffer Length H (only RX) */ +#define BCRL 0x8c /* Byte Count L */ +#define BCRH 0x8d /* Byte Count H */ + +/* Block Descriptor Structure */ +typedef struct { + u32 cp; /* pointer to next block descriptor */ + u32 bp; /* buffer pointer */ + u16 len; /* data length */ + u8 stat; /* status */ + u8 unused; /* 4-byte pad */ +}pkt_desc; + + +/* Packet Descriptor Status bits */ + +#define ST_TX_EOM 0x80 /* End of frame */ +#define ST_TX_UNDRRUN 0x08 +#define ST_TX_OWNRSHP 0x02 +#define ST_TX_EOT 0x01 /* End of transmition */ + +#define ST_RX_EOM 0x80 /* End of frame */ +#define ST_RX_SHORT 0x40 /* Short frame */ +#define ST_RX_ABORT 0x20 /* Abort */ +#define ST_RX_RESBIT 0x10 /* Residual bit */ +#define ST_RX_OVERRUN 0x08 /* Overrun */ +#define ST_RX_CRC 0x04 /* CRC */ +#define ST_RX_OWNRSHP 0x02 + + +#define MD0_HDLC 0x80 /* Bit-sync HDLC mode */ + +#define MD0_NOCRC 0x00 +#define MD0_CRC_16_0 0x04 +#define MD0_CRC_16 0x05 +#define MD0_CRC_ITU32 0x06 +#define MD0_CRC_ITU 0x07 + +#define MD2_NRZI 0x20 /* NRZI mode */ +#define MD2_LOOPBACK 0x03 /* Local data Loopback */ + +#define CTL_RTS 0x01 +#define CTL_DTR 0x02 +#define CTL_IDLE 0x10 +#define CTL_UDRNC 0x20 +#define CTL_URSKP 0x40 +#define CTL_URCT 0x80 + +#define ST1_UDRN 0x80 /* MSCI TX underrun */ + +#define IE0_TXINT 0x00000080 /* TX INT MSCI interrupt enable */ +#define IE0_UDRN 0x00008000 /* TX underrun MSCI interrupt enable */ + +#define CLK_LINE_RX 0x00 /* TX/RX clock line input */ +#define CLK_LINE_TX 0x80 +#define CLK_BRG_RX 0x40 /* internal baud rate generator */ +#define CLK_BRG_TX 0xC0 /* internal baud rate generator */ + +#define EXS_TES1 0x20 +#define EXS_RES1 0x02 + +#define CMD_RESET 0x21 +#define CMD_TX_ENABLE 0x02 +#define CMD_RX_ENABLE 0x12 + +#define DSR_DWE 0x01 +#define DSR_DE 0x02 +#define DSR_REF 0x04 +#define DSR_UDRF 0x04 +#define DSR_COA 0x08 +#define DSR_COF 0x10 +#define DSR_BOF 0x20 +#define DSR_EOM 0x40 +#define DSR_EOT 0x80 + +#define DIR_REFE 0x04 +#define DIR_UDRFE 0x04 +#define DIR_COAE 0x08 +#define DIR_COFE 0x10 +#define DIR_BOFE 0x20 +#define DIR_EOME 0x40 +#define DIR_EOTE 0x80 + +#define DMR_CNTE 0x02 +#define DMR_NF 0x04 +#define DMR_SEOME 0x08 +#define DMR_TMOD 0x10 + +#define DMER_DME 0x80 /* DMA Master Enable */ + +#define DCR_ABORT 0x01 +#define DCR_CLEAR_EOF 0x02 + +#define PCR_COTE 0x80 + +#endif /* (__HD64572_H) */ --- linux-2.2.17pre10/drivers/net/pc300too.c Thu Jul 6 02:18:50 2000 +++ linux/drivers/net/pc300too.c Thu Jul 6 02:31:01 2000 @@ -0,0 +1,450 @@ +/* + * Cyclades PC300 synchronous serial card driver for Linux + * + * Copyright (C) 2000 Krzysztof Halasa + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Requires hdlc.c, a generic HDLC support module + * Available from ftp://ftp.pm.waw.pl/pub/Linux/hdlc/ + * + * Current status: + * - this is work in progress + * + * Sources of information: + * Hitachi HD64572 SCA-II User's Manual + * Cyclades PC300 Linux driver + */ + + +/* 24 Jun 2000 Leszek Urbanski found a problem with RxCLK signal connection */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hd64572.h" +#include "syncppp.h" +#include + +#define USE_PCI_CLOCK +#define DEBUG_RINGS +#undef DEBUG_PKT + +static const char* version = "Cyclades PC300 driver revision: 1.0"; +static const char* devname = "PC300"; + +#define PC300_PLX_WIN 0x80 /* PLX control window size (128b) */ +#define PC300_RAMSIZE 0x80000 /* RAM window size (512Kb) */ +#define PC300_SCASIZE 0x400 /* SCA window size (1Kb) */ +#define ALL_PAGES_ALWAYS_MAPPED + +#define PC300_OSC_CLOCK 24576000 +#define PC300_PCI_CLOCK 33000000 + + +#ifdef USE_PCI_CLOCK +#define CLOCK_BASE PC300_PCI_CLOCK +#else +#define CLOCK_BASE PC300_OSC_CLOCK +#endif + + +/* Masks to access the init_ctrl PLX register */ +#define PC300_CLKSEL_MASK (0x00000004UL) +#define PC300_CHMEDIA_MASK(port) (0x00000020UL<<(port*3)) +#define PC300_CTYPE_MASK (0x00000800UL) + + +/* Control Constant Definitions */ +#define PC300_RSV 0x01 +#define PC300_X21 0x02 +#define PC300_TE 0x03 + + +static u16 cpc_pci_dev_id[] = { + PCI_DEVICE_ID_PC300_RX_1, /* PC300/RSV or PC300/X21, 1 chan */ + PCI_DEVICE_ID_PC300_RX_2, /* PC300/RSV or PC300/X21, 2 chan */ + 0 +}; + + +/* + * PLX PCI9050-1 local configuration and shared runtime registers. + * This structure can be used to access 9050 registers (memory mapped). + */ +typedef struct { + u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */ + u32 loc_rom_range; /* 10h : Local ROM Range */ + u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */ + u32 loc_rom_base; /* 24h : Local ROM Base */ + u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */ + u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */ + u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */ + u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */ + u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */ +}plx9050; + + + +typedef struct port_s { + hdlc_device hdlc; /* HDLC device struct - must be first */ + struct card_s *card; + int clkmode; /* bps or 0 (LINE_EXT_CLOCK) */ + int loopback; + int iface; /* LINE_V35 etc */ + int mode; /* CISCO, PPP etc */ + u8 valid; /* port enabled */ + u8 phy_node; /* physical port # - 0 or 1 */ + u8 rxin; /* rx ring buffer 'in' pointer */ + u8 txin; /* tx ring buffer 'in' and 'last' pointers */ + u8 txlast; +}port_t; + + + +typedef struct card_s { + int type; /* RSV, X21, etc. */ + u32 ramphys; /* dual-port memory base (physical) */ + u8* rambase; /* dual-port memory base (virtual) */ + u32 ramsize; /* dual-port memory size */ + u32 scaphys; /* dual-port memory base (physical) */ + u8* scabase; /* dual-port memory base (virtual) */ + u32 plxphys; /* PLX registers memory base (physical) */ + plx9050* plxbase; /* PLX registers memory base (virtual) */ + u16 buff_offset; /* offset of first buffer of first channel */ + u8 irq; /* interrupt request level */ + u8 ring_buffers; /* number of buffers in a ring */ + int clock; /* Board clock */ + + port_t ports[2]; + + struct card_s *next_card; +}card_t; + + +#define sca_in(reg, card) readb(card->scabase+reg) +#define sca_out(value, reg, card) writeb(value, card->scabase+reg) +#define sca_inw(reg, card) readw(card->scabase+reg) +#define sca_outw(value, reg, card) writew(value, card->scabase+reg) +#define sca_inl(reg, card) readl(card->scabase+reg) +#define sca_outl(value, reg, card) writel(value, card->scabase+reg) + +#define port_to_card(port) (port->card) +#define log_node(port) (port->phy_node) +#define phy_node(port) (port->phy_node) +#define winsize(card) (PC300_RAMSIZE) +#define win0base(card) (card->rambase) +#define winbase(card) (card->rambase) +#define get_port(card, port) (card->ports[port].valid ? \ + &card->ports[port] : NULL) + + +static __inline__ int set_clock(port_t *port, int clock) +{ + port->clkmode=clock; + sca_out(EXS_TES1, (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS, + port_to_card(port)); + return 0; +} + + + +static __inline__ int select_phys_iface(port_t *port, int iface) +{ + u32* init_ctrl=&port->card->plxbase->init_ctrl; + + switch(port->card->type) { + case PC300_X21: + if (iface != LINE_X21) + return -EINVAL; + break; + + case PC300_RSV: + switch(iface) { + case LINE_V35: + writel(readl(init_ctrl) | + PC300_CHMEDIA_MASK(port->phy_node), + init_ctrl); + break; + + case LINE_RS232: + writel(readl(init_ctrl) & + ~PC300_CHMEDIA_MASK(port->phy_node), + init_ctrl); + break; + + default: + return -EINVAL; + } + break; + } + + port->iface=iface; + return 0; +} + + + +static __inline__ void open_port(port_t *port) +{ + /* Assert RTS and DTR */ + sca_out(sca_in(CTL, port->card) & ~(CTL_RTS | CTL_DTR), + CTL, port->card); +} + + + +static __inline__ void close_port(port_t *port) +{ +} + + + +#include "hd6457x.c" + + +static u32 detect_ram(card_t *card) +{ + u32 i; + u8* rambase = card->rambase; + + /* Let's find out how much RAM is present on this board */ + for (i = 0; i < PC300_RAMSIZE ; i++) { + writeb((u8)i, rambase + i); + if (readb(rambase + i) != (u8)i) + break; + } + + return i; +} + + + +static void plx_init(card_t *card) +{ + plx9050 *plx_ctl = (plx9050 *)card->plxbase; + + /* Reset PLX */ + writel(readl(&plx_ctl->init_ctrl)|0x40000000, &plx_ctl->init_ctrl); + udelay(100L); + writel(readl(&plx_ctl->init_ctrl)&~0x40000000, &plx_ctl->init_ctrl); + + /* Reload Config. Registers from EEPROM */ + writel(readl(&plx_ctl->init_ctrl)|0x20000000, &plx_ctl->init_ctrl); + udelay(100L); + writel(readl(&plx_ctl->init_ctrl)&~0x20000000, &plx_ctl->init_ctrl); +} + + + +static void pc300_destroy_card(card_t *card) +{ + int i; + for(i = 0; i < 2; i++) + if (card->ports[i].card) + unregister_hdlc_device(&card->ports[i].hdlc); + + if (card->irq) + free_irq(card->irq, card); + + iounmap(card->rambase); + iounmap(card->scabase); + iounmap(card->plxbase); + + kfree(card); +} + + + +static int pc300_pci_init(struct pci_dev *pdev, int ports) +{ + card_t *card; + u8 cpc_rev_id; + int i; + + card = kmalloc(sizeof(card_t), GFP_KERNEL); + if (card==NULL) + return -ENOBUFS; + memset(card, 0, sizeof(card_t)); + + card->plxphys = pdev->base_address[0]; + card->scaphys = pdev->base_address[2]; + card->ramphys = pdev->base_address[3]; + pci_read_config_byte(pdev, PCI_REVISION_ID, &cpc_rev_id); + +#ifdef PC300_DEBUG_PCI + printk(KERN_DEBUG "pc300: bus=0x0%x, pci_id=0x%x, rev_id=%d IRQ%d " + "ramaddr=0x%lx plxaddr=0x%lx ctladdr=0x%lx\n", + pdev->bus->number, pdev->devfn, cpc_rev_id, pdev->irq, + card->ramphys, card->plxphys, card->scaphys); +#endif + card->plxphys &= PCI_BASE_ADDRESS_MEM_MASK; + card->ramphys &= PCI_BASE_ADDRESS_MEM_MASK; + card->scaphys &= PCI_BASE_ADDRESS_MEM_MASK; + + card->plxbase = ioremap(card->plxphys, PC300_PLX_WIN); + card->rambase = ioremap(card->ramphys, PC300_RAMSIZE); + card->scabase = ioremap(card->scaphys, PC300_SCASIZE); + +#ifdef PC300_DEBUG_PCI + printk(KERN_DEBUG "pc300: relocated ramaddr=0x%lx plxaddr=0x%lx " + "ctladdr=0x%lx\n", card->rambase, card->plxbase, card->scabase); +#endif + card->ramsize = detect_ram(card); + + /* Enable interrupts on the PCI bridge */ + plx_init(card); + writew(readw(&card->plxbase->intr_ctrl_stat) | 0x0040, + &card->plxbase->intr_ctrl_stat); + +#ifdef USE_PCI_CLOCK + /* Set board clock to PCI clock */ + writel(readl(&card->plxbase->init_ctrl) | 0x00000004UL, + &card->plxbase->init_ctrl); + card->clock = PC300_PCI_CLOCK; +#else + /* Set board clock to internal oscillator clock */ + writel(readl(&card->plxbase->init_ctrl) &~0x00000004UL, + &card->plxbase->init_ctrl); + card->clock = PC300_OSC_CLOCK; +#endif + + /* Set Global SCA-II registers */ + if(readl(&card->plxbase->init_ctrl) & PC300_CTYPE_MASK) + card->type = PC300_X21; + else + card->type = PC300_RSV; + + if (ports == 2) + card->ports[1].valid=1; + + /* Allocate IRQ */ + if(request_irq(pdev->irq, sca_intr, SA_SHIRQ, devname, card)) { + printk(KERN_WARNING "pc300: could not allocate IRQ%d.\n", + pdev->irq); + pc300_destroy_card(card); + return -EBUSY; + } + card->irq = pdev->irq; + + /* 4 rings required for 2 ports, 2 rings for one port */ + card->ring_buffers = card->ramsize / + (ports * 2 * (sizeof(pkt_desc)+HDLC_MAX_MTU)); + + card->buff_offset = ports*2 * (sizeof(pkt_desc)) * card->ring_buffers; + + printk(KERN_INFO "pc300: PC300/%s %u KB RAM at 0x%x, IRQ%u, " + "using %u packets rings\n", + card->type==PC300_X21 ? "X21" : "RSV", card->ramsize/1024, + card->ramphys, card->irq, card->ring_buffers); + + sca_init(card, 0); + + sca_out(sca_in(PCR, card) | PCR_COTE, PCR, card); + sca_out(0x10, BTCR, card); + + for(i = 0; i < 2; i++) { + port_t *port = &card->ports[i]; + + if (i == 1 && ports != 2) + break; + + port->phy_node = i; + port->valid = 1; + port->iface = card->type == PC300_X21 ? LINE_X21 : LINE_RS232; + + hdlc_to_dev(&port->hdlc)->irq = card->irq; + hdlc_to_dev(&port->hdlc)->mem_start = card->ramphys; + hdlc_to_dev(&port->hdlc)->mem_end = card->ramphys + + card->ramsize - 1; + hdlc_to_dev(&port->hdlc)->tx_queue_len = 50; + port->hdlc.ioctl=sca_ioctl; + port->hdlc.open=sca_open; + port->hdlc.close=sca_close; + hdlc_to_dev(&port->hdlc)->hard_start_xmit=sca_xmit; + + if(register_hdlc_device(&port->hdlc)) { + printk("pc300: unable to register hdlc device\n"); + pc300_destroy_card(card); + return -ENOBUFS; + } + port->card = card; + sca_init_sync_port(port); /* Set up SCA memory */ + + printk(KERN_INFO "%s: PC300 node %d\n", port->hdlc.name, + port->phy_node); + } + *new_card=card; + new_card=&card->next_card; + + return 0; +} + + + +__initfunc(int pc300too_init(void)) +{ + int device_id, dev_index = 0, devs = 0, rep = 0; + + if(pci_present() == 0) /* PCI bus not present */ + return 0; + + /* look for a Cyclades card by vendor and device id */ + while((device_id = cpc_pci_dev_id[dev_index]) != 0) { + struct pci_dev *pdev = NULL; + do { + pdev = pci_find_device(PCI_VENDOR_ID_CYCLADES, + device_id, pdev); + if(pdev) { /* Found a board */ + if (!rep) { + printk(KERN_INFO "%s\n", version); + rep=1; + } + + if (!pc300_pci_init(pdev, device_id==PCI_DEVICE_ID_PC300_RX_1 ? 1 : 2)) + devs++; /* Initialized one card successfully */ + } + }while (pdev!=NULL); + dev_index++; + } + + if(devs==0) + return -ENODEV; /* No cards found */ + + return 0; +} + + +#ifdef MODULE + +int init_module(void) +{ + return pc300too_init(); +} + + + +void cleanup_module(void) +{ + card_t *card=first_card; + + while (card) { + card_t *ptr=card; + card=card->next_card; + pc300_destroy_card(ptr); + } +} + +#endif