--- linux-2.4.20/drivers/net/wan/Makefile 2003-04-07 18:27:30.000000000 +0200 +++ linux-2.4.20.new/drivers/net/wan/Makefile 2003-04-07 18:25:18.000000000 +0200 @@ -77,6 +77,8 @@ endif obj-$(CONFIG_N2) += n2.o obj-$(CONFIG_C101) += c101.o +obj-$(CONFIG_PC300TOO) += pc300too.o +obj-$(CONFIG_PCI200SYN) += pci200syn.o include $(TOPDIR)/Rules.make --- linux-2.4.20/drivers/net/wan/hd64572.h 2003-04-07 18:30:00.000000000 +0200 +++ linux-2.4.20.new/drivers/net/wan/hd64572.h 2003-04-07 18:25:18.000000000 +0200 @@ -0,0 +1,240 @@ +#ifndef __HD64572_H +#define __HD64572_H + +/* SCA-II HD64572 register definitions - all addresses for mode 0 + and 2 (Intel MPU). For modes 2 and 3, XOR the address with 0x03. + + Source: HD64572 SCA User's Manual +*/ + +#define ILAR 0x00 /* Illegal Access */ + +/* Wait Controller Registers */ +#define PABR0L 0x20 /* Physical Address Boundary 0 L */ +#define PABR0H 0x21 /* Physical Address Boundary 0 H */ +#define PABR1L 0x22 /* Physical Address Boundary 1 L */ +#define PABR1H 0x23 /* Physical Address Boundary 1 H */ +#define WCRL 0x24 /* Wait Control L */ +#define WCRM 0x25 /* Wait Control M */ +#define WCRH 0x26 /* Wait Control H */ + +/* Interrupt Registers */ +#define IVR 0x60 /* Interrupt Vector */ +#define IMVR 0x64 /* Interrupt Modified Vector */ +#define ITCR 0x68 /* Interrupt Control */ +#define ISR0 0x6c /* Interrupt Status 0 */ +#define ISR1 0x70 /* Interrupt Status 1 */ +#define IER0 0x74 /* Interrupt Enable 0 */ +#define IER1 0x78 /* Interrupt Enable 1 */ + +/* MSCI Channel Registers */ +#define MSCI0_OFFSET 0x00 +#define MSCI1_OFFSET 0x80 + +#define MD0 0x138 /* Mode reg 0 */ +#define MD1 0x139 /* Mode reg 1 */ +#define MD2 0x13A /* Mode reg 2 */ +#define MD3 0x13B /* Mode reg 3 */ +#define CTL 0x130 /* Control reg */ +#define RXS 0x13C /* RX clock source */ +#define TXS 0x13D /* TX clock source */ +#define EXS 0x13E /* External clock input selection */ +#define TMCT 0x144 /* Time constant (Tx) */ +#define TMCR 0x145 /* Time constant (Rx) */ +#define CMD 0x128 /* Command reg */ +#define ST0 0x118 /* Status reg 0 */ +#define ST1 0x119 /* Status reg 1 */ +#define ST2 0x11A /* Status reg 2 */ +#define ST3 0x11B /* Status reg 3 */ +#define ST4 0x11C /* Status reg 4 */ +#define FST 0x11D /* frame Status reg */ +#define IE0 0x120 /* Interrupt enable reg 0 */ +#define IE1 0x121 /* Interrupt enable reg 1 */ +#define IE2 0x122 /* Interrupt enable reg 2 */ +#define IE4 0x124 /* Interrupt enable reg 4 */ +#define FIE 0x125 /* Frame Interrupt enable reg */ +#define SA0 0x140 /* Syn Address reg 0 */ +#define SA1 0x141 /* Syn Address reg 1 */ +#define IDL 0x142 /* Idle register */ +#define TRBL 0x100 /* TX/RX buffer reg L */ +#define TRBK 0x101 /* TX/RX buffer reg K */ +#define TRBJ 0x102 /* TX/RX buffer reg J */ +#define TRBH 0x103 /* TX/RX buffer reg H */ +#define TRC0 0x148 /* TX Ready control reg 0 */ +#define TRC1 0x149 /* TX Ready control reg 1 */ +#define RRC 0x14a /* RX Ready control reg */ +#define CST0 0x108 /* Current Status 0 */ +#define CST1 0x109 /* Current Status 1 */ +#define CST2 0x10A /* Current Status 2 */ +#define CST3 0x10B /* Current Status 3 */ +#define GPO 0x131 /* General Purpose Output Pin Ctl Reg */ +#define TFS 0x14B /* Tx Start Threshold Ctl Reg */ +#define TFN 0x143 /* Inter-transmit-frame Time Fill Ctl Reg */ +#define TBN 0x110 /* Tx Buffer Number Reg */ +#define RBN 0x111 /* Rx Buffer Number Reg */ +#define TNR0 0x150 /* Tx DMA Request Ctl Reg 0 */ +#define TNR1 0x151 /* Tx DMA Request Ctl Reg 1 */ +#define TCR 0x152 /* Tx DMA Critical Request Reg */ +#define RNR 0x154 /* Rx DMA Request Ctl Reg */ +#define RCR 0x156 /* Rx DMA Critical Request Reg */ + +/* Timer Registers */ +#define TIMER0RX_OFFSET 0x00 +#define TIMER0TX_OFFSET 0x10 +#define TIMER1RX_OFFSET 0x20 +#define TIMER1TX_OFFSET 0x30 + +#define TCNTL 0x200 /* Timer Upcounter L */ +#define TCNTH 0x201 /* Timer Upcounter H */ +#define TCONRL 0x204 /* Timer Constant L */ +#define TCONRH 0x205 /* Timer Constant H */ +#define TCSR 0x206 /* Timer Control/Status */ +#define TEPR 0x207 /* Timer Expand Prescale */ + +/* DMA registers */ +#define PCR 0x40 /* DMA priority control reg */ +#define DRR 0x44 /* DMA reset reg */ +#define DMER 0x07 /* DMA Master Enable reg */ +#define BTCR 0x08 /* Burst Tx Ctl Reg */ +#define BOLR 0x0c /* Back-off Length Reg */ +#define DSR_RX(node) (0x48 + node*2) /* DMA Status Reg (Rx) */ +#define DSR_TX(node) (0x49 + node*2) /* DMA Status Reg (Tx) */ +#define DIR_RX(node) (0x4c + node*2) /* DMA IRQ Enable Reg (Rx) */ +#define DIR_TX(node) (0x4d + node*2) /* DMA IRQ Enable Reg (Tx) */ +#define FCT_RX(node) (0x50 + node*2) /* Frame End IRQ Counter (Rx) */ +#define FCT_TX(node) (0x51 + node*2) /* Frame End IRQ Counter (Tx) */ +#define DMR_RX(node) (0x54 + node*2) /* DMA Mode Reg (Rx) */ +#define DMR_TX(node) (0x55 + node*2) /* DMA Mode Reg (Tx) */ +#define DCR_RX(node) (0x58 + node*2) /* DMA Command Reg (Rx) */ +#define DCR_TX(node) (0x59 + node*2) /* DMA Command Reg (Tx) */ + +/* DMA Channel Registers */ +#define DMAC0RX_OFFSET 0x00 +#define DMAC0TX_OFFSET 0x20 +#define DMAC1RX_OFFSET 0x40 +#define DMAC1TX_OFFSET 0x60 + +#define DARL 0x80 /* Dest Addr L (single-block, RX only) */ +#define DARH 0x81 /* Dest Addr H (single-block, RX only) */ +#define DARB 0x82 /* Dest Addr B (single-block, RX only) */ +#define DARBH 0x83 /* Dest Addr BH (single-block, RX only) */ +#define SARL 0x80 /* Source Addr L (single-block, TX only) */ +#define SARH 0x81 /* Source Addr H (single-block, TX only) */ +#define SARB 0x82 /* Source Addr B (single-block, TX only) */ +#define SARBH 0x83 /* Source Addr BH (single-block, TX only) */ +#define BARL 0x80 /* Buffer Addr L (chained-block) */ +#define BARH 0x81 /* Buffer Addr H (chained-block) */ +#define BARB 0x82 /* Buffer Addr B (chained-block) */ +#define BARBH 0x83 /* Buffer Addr BH (chained-block) */ +#define CDAL 0x84 /* Current Descriptor Addr L */ +#define CDAH 0x85 /* Current Descriptor Addr H */ +#define CDAB 0x86 /* Current Descriptor Addr B */ +#define CDABH 0x87 /* Current Descriptor Addr BH */ +#define EDAL 0x88 /* Error Descriptor Addr L */ +#define EDAH 0x89 /* Error Descriptor Addr H */ +#define EDAB 0x8a /* Error Descriptor Addr B */ +#define EDABH 0x8b /* Error Descriptor Addr BH */ +#define BFLL 0x90 /* RX Buffer Length L (only RX) */ +#define BFLH 0x91 /* RX Buffer Length H (only RX) */ +#define BCRL 0x8c /* Byte Count L */ +#define BCRH 0x8d /* Byte Count H */ + +/* Block Descriptor Structure */ +typedef struct { + u32 cp; /* pointer to next block descriptor */ + u32 bp; /* buffer pointer */ + u16 len; /* data length */ + u8 stat; /* status */ + u8 unused; /* pads to 4-byte boundary */ +}pkt_desc; + + +/* Packet Descriptor Status bits */ + +#define ST_TX_EOM 0x80 /* End of frame */ +#define ST_TX_UNDRRUN 0x08 +#define ST_TX_OWNRSHP 0x02 +#define ST_TX_EOT 0x01 /* End of transmition */ + +#define ST_RX_EOM 0x80 /* End of frame */ +#define ST_RX_SHORT 0x40 /* Short frame */ +#define ST_RX_ABORT 0x20 /* Abort */ +#define ST_RX_RESBIT 0x10 /* Residual bit */ +#define ST_RX_OVERRUN 0x08 /* Overrun */ +#define ST_RX_CRC 0x04 /* CRC */ +#define ST_RX_OWNRSHP 0x02 + +#define ST_ERROR_MASK 0x7C + +#define MD0_HDLC 0x80 /* Bit-sync HDLC mode */ + +#define MD0_CRC_NONE 0x00 +#define MD0_CRC_16_0 0x04 +#define MD0_CRC_16 0x05 +#define MD0_CRC_ITU32 0x06 +#define MD0_CRC_ITU 0x07 + +#define MD2_NRZ 0x00 +#define MD2_NRZI 0x20 +#define MD2_NRZI_IEEE 0x40 +#define MD2_MANCHESTER 0x80 +#define MD2_FM_MARK 0xA0 +#define MD2_FM_SPACE 0xC0 +#define MD2_LOOPBACK 0x03 /* Local data Loopback */ + +#define CTL_NORTS 0x01 +#define CTL_NODTR 0x02 +#define CTL_IDLE 0x10 +#define CTL_UDRNC 0x20 +#define CTL_URSKP 0x40 +#define CTL_URCT 0x80 + +#define ST1_UDRN 0x80 /* MSCI TX underrun */ + +#define IE0_TXINT 0x00000080 /* TX INT MSCI interrupt enable */ +#define IE0_UDRN 0x00008000 /* TX underrun MSCI interrupt enable */ + +#define CLK_BRG_MASK 0x0F +#define CLK_PIN_OUT 0x80 +#define CLK_LINE 0x00 /* clock line input */ +#define CLK_BRG 0x40 /* internal baud rate generator */ +#define CLK_TX_RXCLK 0x60 /* TX clock from RX clock */ + +#define EXS_TES1 0x20 +#define EXS_RES1 0x02 + +#define CMD_RESET 0x21 +#define CMD_TX_ENABLE 0x02 +#define CMD_RX_ENABLE 0x12 + +#define DSR_DWE 0x01 +#define DSR_DE 0x02 +#define DSR_REF 0x04 +#define DSR_UDRF 0x04 +#define DSR_COA 0x08 +#define DSR_COF 0x10 +#define DSR_BOF 0x20 +#define DSR_EOM 0x40 +#define DSR_EOT 0x80 + +#define DIR_REFE 0x04 +#define DIR_UDRFE 0x04 +#define DIR_COAE 0x08 +#define DIR_COFE 0x10 +#define DIR_BOFE 0x20 +#define DIR_EOME 0x40 +#define DIR_EOTE 0x80 + +#define DMR_CNTE 0x02 +#define DMR_NF 0x04 +#define DMR_SEOME 0x08 +#define DMR_TMOD 0x10 + +#define DMER_DME 0x80 /* DMA Master Enable */ + +#define DCR_ABORT 0x01 +#define DCR_CLEAR_EOF 0x02 + +#define PCR_COTE 0x80 + +#endif /* (__HD64572_H) */ --- linux-2.4.20/drivers/net/wan/pci200syn.c 2003-04-07 18:30:00.000000000 +0200 +++ linux-2.4.20.new/drivers/net/wan/pci200syn.c 2003-04-07 18:25:18.000000000 +0200 @@ -0,0 +1,456 @@ +/* + * Goramo PCI200SYN synchronous serial card driver for Linux + * + * Copyright (C) 2002-2003 Krzysztof Halasa + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * For information see http://hq.pm.waw.pl/hdlc/ + * + * Sources of information: + * Hitachi HD64572 SCA-II User's Manual + * PLX Technology Inc. PCI9052 Data Book + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hd64572.h" + +static const char* version = "Goramo PCI200SYN driver version: 1.14"; +static const char* devname = "PCI200SYN"; + +#define PCI200SYN_PLX_SIZE 0x80 /* PLX control window size (128b) */ +#define PCI200SYN_SCA_SIZE 0x400 /* SCA window size (1Kb) */ +#define ALL_PAGES_ALWAYS_MAPPED +#define NEED_DETECT_RAM +#define MAX_TX_BUFFERS 10 + +static int pci_clock_freq = 33000000; +#define CLOCK_BASE pci_clock_freq + +#define PCI_VENDOR_ID_GORAMO 0x10B5 /* uses PLX:9050 ID - this card */ +#define PCI_DEVICE_ID_PCI200SYN 0x9050 /* doesn't have its own ID */ + + +/* + * PLX PCI9052 local configuration and shared runtime registers. + * This structure can be used to access 9052 registers (memory mapped). + */ +typedef struct { + u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */ + u32 loc_rom_range; /* 10h : Local ROM Range */ + u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */ + u32 loc_rom_base; /* 24h : Local ROM Base */ + u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */ + u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */ + u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */ + u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */ + u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */ +}plx9052; + + + +typedef struct port_s { + hdlc_device hdlc; /* HDLC device struct - must be first */ + struct card_s *card; + spinlock_t lock; /* TX lock */ + sync_serial_settings settings; + int rxpart; /* partial frame received, next frame invalid*/ + unsigned short encoding; + unsigned short parity; + u16 rxin; /* rx ring buffer 'in' pointer */ + u16 txin; /* tx ring buffer 'in' and 'last' pointers */ + u16 txlast; + u8 rxs, txs, tmc; /* SCA registers */ + u8 phy_node; /* physical port # - 0 or 1 */ +}port_t; + + + +typedef struct card_s { + u32 ramphys; /* buffer memory base (physical) */ + u8* rambase; /* buffer memory base (virtual) */ + u32 ramsize; /* buffer memory size */ + u32 scaphys; /* SCA memory base (physical) */ + u8* scabase; /* SCA memory base (virtual) */ + u32 plxphys; /* PLX registers memory base (physical) */ + plx9052* plxbase; /* PLX registers memory base (virtual) */ + u16 rx_ring_buffers; /* number of buffers in a ring */ + u16 tx_ring_buffers; + u16 buff_offset; /* offset of first buffer of first channel */ + u8 irq; /* interrupt request level */ + + port_t ports[2]; +}card_t; + + +#define sca_in(reg, card) readb(card->scabase + (reg)) +#define sca_out(value, reg, card) writeb(value, card->scabase + (reg)) +#define sca_inw(reg, card) readw(card->scabase + (reg)) +#define sca_outw(value, reg, card) writew(value, card->scabase + (reg)) +#define sca_inl(reg, card) readl(card->scabase + (reg)) +#define sca_outl(value, reg, card) writel(value, card->scabase + (reg)) + +#define port_to_card(port) (port->card) +#define log_node(port) (port->phy_node) +#define phy_node(port) (port->phy_node) +#define winbase(card) (card->rambase) +#define get_port(card, port) (&card->ports[port]) +#define sca_flush(card) (sca_in(IER0, card)); + +static inline void new_memcpy_toio(char *dest, char *src, int length) +{ + int len; + do { + len = length > 256 ? 256 : length; + memcpy_toio(dest, src, len); + dest += len; + src += len; + length -= len; + readb(dest); + } while (len); +} + +#undef memcpy_toio +#define memcpy_toio new_memcpy_toio + +#include "hd6457x.c" + + +static void pci200_set_iface(port_t *port) +{ + card_t *card = port->card; + u16 msci = get_msci(port); + u8 rxs = port->rxs & CLK_BRG_MASK; + u8 txs = port->txs & CLK_BRG_MASK; + + sca_out(EXS_TES1, (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS, + port_to_card(port)); + switch(port->settings.clock_type) { + case CLOCK_INT: + rxs |= CLK_BRG; /* BRG output */ + txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */ + break; + + case CLOCK_TXINT: + rxs |= CLK_LINE; /* RXC input */ + txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */ + break; + + case CLOCK_TXFROMRX: + rxs |= CLK_LINE; /* RXC input */ + txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */ + break; + + default: /* EXTernal clock */ + rxs |= CLK_LINE; /* RXC input */ + txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */ + break; + } + + port->rxs = rxs; + port->txs = txs; + sca_out(rxs, msci + RXS, card); + sca_out(txs, msci + TXS, card); + sca_set_port(port); +} + + + +static int pci200_open(struct net_device *dev) +{ + hdlc_device *hdlc = dev_to_hdlc(dev); + port_t *port = hdlc_to_port(hdlc); + + int result = hdlc_open(hdlc); + if (result) + return result; + + MOD_INC_USE_COUNT; + sca_open(hdlc); + pci200_set_iface(port); + sca_flush(port_to_card(port)); + return 0; +} + + + +static int pci200_close(struct net_device *dev) +{ + hdlc_device *hdlc = dev_to_hdlc(dev); + sca_close(hdlc); + sca_flush(port_to_card(dev_to_port(dev))); + hdlc_close(hdlc); + MOD_DEC_USE_COUNT; + return 0; +} + + + +static int pci200_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) +{ + const size_t size = sizeof(sync_serial_settings); + sync_serial_settings new_line, *line = ifr->ifr_settings.ifs_ifsu.sync; + hdlc_device *hdlc = dev_to_hdlc(dev); + port_t *port = hdlc_to_port(hdlc); + +#ifdef CONFIG_HDLC_DEBUG_RINGS + if (cmd == SIOCDEVPRIVATE) { + sca_dump_rings(hdlc); + return 0; + } +#endif + if (cmd != SIOCWANDEV) + return hdlc_ioctl(dev, ifr, cmd); + + switch(ifr->ifr_settings.type) { + case IF_GET_IFACE: + ifr->ifr_settings.type = IF_IFACE_V35; + if (ifr->ifr_settings.size < size) { + ifr->ifr_settings.size = size; /* data size wanted */ + return -ENOBUFS; + } + if (copy_to_user(line, &port->settings, size)) + return -EFAULT; + return 0; + + case IF_IFACE_V35: + case IF_IFACE_SYNC_SERIAL: + if (!capable(CAP_NET_ADMIN)) + return -EPERM; + + if (copy_from_user(&new_line, line, size)) + return -EFAULT; + + if (new_line.clock_type != CLOCK_EXT && + new_line.clock_type != CLOCK_TXFROMRX && + new_line.clock_type != CLOCK_INT && + new_line.clock_type != CLOCK_TXINT) + return -EINVAL; /* No such clock setting */ + + if (new_line.loopback != 0 && new_line.loopback != 1) + return -EINVAL; + + memcpy(&port->settings, &new_line, size); /* Update settings */ + pci200_set_iface(port); + sca_flush(port_to_card(port)); + return 0; + + default: + return hdlc_ioctl(dev, ifr, cmd); + } +} + + + +static void pci200_pci_remove_one(struct pci_dev *pdev) +{ + int i; + card_t *card = pci_get_drvdata(pdev); + + for(i = 0; i < 2; i++) + if (card->ports[i].card) + unregister_hdlc_device(&card->ports[i].hdlc); + + if (card->irq) + free_irq(card->irq, card); + iounmap(card->rambase); + iounmap(card->scabase); + iounmap(card->plxbase); + pci_release_regions(pdev); + kfree(card); +} + + + +static int __devinit pci200_pci_init_one(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + card_t *card; + u8 rev_id; + u32 *p; + int i; + +#ifndef MODULE + static int printed_version; + if (!printed_version++) + printk(KERN_INFO "%s\n", version); +#endif + + i = pci_enable_device(pdev); + if (i) + return i; + + i = pci_request_regions(pdev, "PCI200SYN"); + if (i) + return i; + + card = kmalloc(sizeof(card_t), GFP_KERNEL); + if (card == NULL) { + printk(KERN_ERR "pci200syn: unable to allocate memory\n"); + return -ENOBUFS; + } + memset(card, 0, sizeof(card_t)); + pci_set_drvdata(pdev, card); + + pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); + if (pci_resource_len(pdev, 0) != PCI200SYN_PLX_SIZE || + pci_resource_len(pdev, 2) != PCI200SYN_SCA_SIZE || + pci_resource_len(pdev, 3) < 16384) { + printk(KERN_ERR "pci200syn: invalid card EEPROM parameters\n"); + kfree(card); + return -EFAULT; + } + + card->plxphys = pci_resource_start(pdev,0) & PCI_BASE_ADDRESS_MEM_MASK; + card->plxbase = ioremap(card->plxphys, PCI200SYN_PLX_SIZE); + + card->scaphys = pci_resource_start(pdev,2) & PCI_BASE_ADDRESS_MEM_MASK; + card->scabase = ioremap(card->scaphys, PCI200SYN_SCA_SIZE); + + card->ramphys = pci_resource_start(pdev,3) & PCI_BASE_ADDRESS_MEM_MASK; + card->rambase = ioremap(card->ramphys, pci_resource_len(pdev,3)); + + /* Reset PLX */ + p = &card->plxbase->init_ctrl; + writel(readl(p) | 0x40000000, p); + readl(p); /* Flush the write - do not use sca_flush */ + udelay(1); + + writel(readl(p) & ~0x40000000, p); + readl(p); /* Flush the write - do not use sca_flush */ + udelay(1); + + card->ramsize = sca_detect_ram(card, card->rambase, + pci_resource_len(pdev,3)); + + /* number of TX + RX buffers for one port - this is dual port card */ + i = card->ramsize / (2 * (sizeof(pkt_desc) + HDLC_MAX_MRU)); + card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS); + card->rx_ring_buffers = i - card->tx_ring_buffers; + + card->buff_offset = 2 * sizeof(pkt_desc) * (card->tx_ring_buffers + + card->rx_ring_buffers); + + printk(KERN_INFO "pci200syn: %u KB RAM at 0x%x, IRQ%u, using %u TX +" + " %u RX packets rings\n", card->ramsize / 1024, + card->ramphys, pdev->irq, + card->tx_ring_buffers, card->rx_ring_buffers); + + if (card->tx_ring_buffers < 1) { + printk(KERN_ERR "pci200syn: RAM test failed\n"); + pci200_pci_remove_one(pdev); + return -EFAULT; + } + + /* Enable interrupts on the PCI bridge */ + p = &card->plxbase->intr_ctrl_stat; + writew(readw(p) | 0x0040, p); + + /* Allocate IRQ */ + if(request_irq(pdev->irq, sca_intr, SA_SHIRQ, devname, card)) { + printk(KERN_WARNING "pci200syn: could not allocate IRQ%d.\n", + pdev->irq); + pci200_pci_remove_one(pdev); + return -EBUSY; + } + card->irq = pdev->irq; + + sca_init(card, 0); + + for(i = 0; i < 2; i++) { + port_t *port = &card->ports[i]; + struct net_device *dev = hdlc_to_dev(&port->hdlc); + port->phy_node = i; + + spin_lock_init(&port->lock); + dev->irq = card->irq; + dev->mem_start = card->ramphys; + dev->mem_end = card->ramphys + card->ramsize - 1; + dev->tx_queue_len = 50; + dev->do_ioctl = pci200_ioctl; + dev->open = pci200_open; + dev->stop = pci200_close; + port->hdlc.attach = sca_attach; + port->hdlc.xmit = sca_xmit; + port->settings.clock_type = CLOCK_EXT; + if(register_hdlc_device(&port->hdlc)) { + printk(KERN_ERR "pci200syn: unable to register hdlc " + "device\n"); + pci200_pci_remove_one(pdev); + return -ENOBUFS; + } + port->card = card; + sca_init_sync_port(port); /* Set up SCA memory */ + + printk(KERN_INFO "%s: PCI200SYN node %d\n", + hdlc_to_name(&port->hdlc), port->phy_node); + } + + sca_flush(card); + return 0; +} + + + +static struct pci_device_id pci200_pci_tbl[] __devinitdata = { + { PCI_VENDOR_ID_GORAMO, PCI_DEVICE_ID_PCI200SYN, PCI_ANY_ID, + PCI_ANY_ID, 0, 0, 0 }, + { 0, } +}; + + +static struct pci_driver pci200_pci_driver = { + name: "PCI200SYN", + id_table: pci200_pci_tbl, + probe: pci200_pci_init_one, + remove: pci200_pci_remove_one, +}; + + +static int __init pci200_init_module(void) +{ +#ifdef MODULE + printk(KERN_INFO "%s\n", version); +#endif + if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) { + printk(KERN_ERR "pci200syn: Invalid PCI clock frequency\n"); + return -EINVAL; + } + return pci_module_init(&pci200_pci_driver); +} + + + +static void __exit pci200_cleanup_module(void) +{ + pci_unregister_driver(&pci200_pci_driver); +} + +MODULE_AUTHOR("Krzysztof Halasa "); +MODULE_DESCRIPTION("Goramo PCI200SYN serial port driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(pci, pci200_pci_tbl); +MODULE_PARM(pci_clock_freq, "i"); +MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz"); +EXPORT_NO_SYMBOLS; +module_init(pci200_init_module); +module_exit(pci200_cleanup_module); --- linux-2.4.20/drivers/net/wan/pc300too.c 2003-04-07 18:30:00.000000000 +0200 +++ linux-2.4.20.new/drivers/net/wan/pc300too.c 2003-04-07 18:25:18.000000000 +0200 @@ -0,0 +1,524 @@ +/* + * Cyclades PC300 synchronous serial card driver for Linux + * + * Copyright (C) 2000-2003 Krzysztof Halasa + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * For information see http://hq.pm.waw.pl/hdlc/ + * + * Sources of information: + * Hitachi HD64572 SCA-II User's Manual + * Cyclades PC300 Linux driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hd64572.h" + + +static const char* version = "Cyclades PC300 driver version: 1.14"; +static const char* devname = "PC300"; + +#define PC300_PLX_WIN 0x80 /* PLX control window size (128b) */ +#define PC300_RAMSIZE 0x80000 /* RAM window size (512Kb) */ +#define PC300_SCASIZE 0x400 /* SCA window size (1Kb) */ +#define ALL_PAGES_ALWAYS_MAPPED +#define NEED_DETECT_RAM +#define MAX_TX_BUFFERS 10 + +#ifdef CONFIG_PC300TOO_CRYSTAL_CLOCK +#define CLOCK_BASE 24576000 +#else +static int pci_clock_freq = 33000000; +#define CLOCK_BASE pci_clock_freq +#endif + + +/* Masks to access the init_ctrl PLX register */ +#define PC300_CLKSEL_MASK (0x00000004UL) +#define PC300_CHMEDIA_MASK(port) (0x00000020UL << (port * 3)) +#define PC300_CTYPE_MASK (0x00000800UL) + + +/* Control Constant Definitions */ +#define PC300_RSV 0x01 +#define PC300_X21 0x02 +#define PC300_TE 0x03 + + +/* + * PLX PCI9050-1 local configuration and shared runtime registers. + * This structure can be used to access 9050 registers (memory mapped). + */ +typedef struct { + u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */ + u32 loc_rom_range; /* 10h : Local ROM Range */ + u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */ + u32 loc_rom_base; /* 24h : Local ROM Base */ + u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */ + u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */ + u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */ + u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */ + u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */ +}plx9050; + + + +typedef struct port_s { + hdlc_device hdlc; /* HDLC device struct - must be first */ + struct card_s *card; + spinlock_t lock; /* TX lock */ + sync_serial_settings settings; + int rxpart; /* partial frame received, next frame invalid*/ + unsigned short encoding; + unsigned short parity; + unsigned int iface; + u16 rxin; /* rx ring buffer 'in' pointer */ + u16 txin; /* tx ring buffer 'in' and 'last' pointers */ + u16 txlast; + u8 rxs, txs, tmc; /* SCA registers */ + u8 phy_node; /* physical port # - 0 or 1 */ +}port_t; + + + +typedef struct card_s { + int type; /* RSV, X21, etc. */ + int n_ports; /* 1 or 2 ports */ + u32 ramphys; /* dual-port memory base (physical) */ + u8* rambase; /* dual-port memory base (virtual) */ + u32 ramsize; /* dual-port memory size */ + u32 scaphys; /* dual-port memory base (physical) */ + u8* scabase; /* dual-port memory base (virtual) */ + u32 plxphys; /* PLX registers memory base (physical) */ + plx9050* plxbase; /* PLX registers memory base (virtual) */ + u16 rx_ring_buffers; /* number of buffers in a ring */ + u16 tx_ring_buffers; + u16 buff_offset; /* offset of first buffer of first channel */ + u8 irq; /* interrupt request level */ + + port_t ports[2]; +}card_t; + + +#define sca_in(reg, card) readb(card->scabase + (reg)) +#define sca_out(value, reg, card) writeb(value, card->scabase + (reg)) +#define sca_inw(reg, card) readw(card->scabase + (reg)) +#define sca_outw(value, reg, card) writew(value, card->scabase + (reg)) +#define sca_inl(reg, card) readl(card->scabase + (reg)) +#define sca_outl(value, reg, card) writel(value, card->scabase + (reg)) + +#define port_to_card(port) (port->card) +#define log_node(port) (port->phy_node) +#define phy_node(port) (port->phy_node) +#define winsize(card) (PC300_RAMSIZE) +#define win0base(card) (card->rambase) +#define winbase(card) (card->rambase) +#define get_port(card, port) ((port) < (card)->n_ports ? \ + (&(card)->ports[port]) : (NULL)) + +#include "hd6457x.c" + + + +static void pc300_set_iface(port_t *port) +{ + card_t *card = port->card; + u32* init_ctrl = &card->plxbase->init_ctrl; + u16 msci = get_msci(port); + u8 rxs = port->rxs & CLK_BRG_MASK; + u8 txs = port->txs & CLK_BRG_MASK; + + sca_out(EXS_TES1, (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS, + port_to_card(port)); + switch(port->settings.clock_type) { + case CLOCK_INT: + rxs |= CLK_BRG; /* BRG output */ + txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */ + break; + + case CLOCK_TXINT: + rxs |= CLK_LINE; /* RXC input */ + txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */ + break; + + case CLOCK_TXFROMRX: + rxs |= CLK_LINE; /* RXC input */ + txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */ + break; + + default: /* EXTernal clock */ + rxs |= CLK_LINE; /* RXC input */ + txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */ + break; + } + + port->rxs = rxs; + port->txs = txs; + sca_out(rxs, msci + RXS, card); + sca_out(txs, msci + TXS, card); + sca_set_port(port); + + if (port->card->type == PC300_RSV) { + if (port->iface == IF_IFACE_V35) + writel(readl(init_ctrl) | + PC300_CHMEDIA_MASK(port->phy_node), init_ctrl); + else + + writel(readl(init_ctrl) & + ~PC300_CHMEDIA_MASK(port->phy_node), init_ctrl); + } +} + + + +static int pc300_open(struct net_device *dev) +{ + hdlc_device *hdlc = dev_to_hdlc(dev); + port_t *port = hdlc_to_port(hdlc); + + int result = hdlc_open(hdlc); + if (result) + return result; + + MOD_INC_USE_COUNT; + sca_open(hdlc); + pc300_set_iface(port); + return 0; +} + + + +static int pc300_close(struct net_device *dev) +{ + hdlc_device *hdlc = dev_to_hdlc(dev); + sca_close(hdlc); + hdlc_close(hdlc); + MOD_DEC_USE_COUNT; + return 0; +} + + + +static int pc300_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) +{ + const size_t size = sizeof(sync_serial_settings); + sync_serial_settings new_line, *line = ifr->ifr_settings.ifs_ifsu.sync; + int new_type; + hdlc_device *hdlc = dev_to_hdlc(dev); + port_t *port = hdlc_to_port(hdlc); + +#ifdef CONFIG_HDLC_DEBUG_RINGS + if (cmd == SIOCDEVPRIVATE) { + sca_dump_rings(hdlc); + return 0; + } +#endif + if (cmd != SIOCWANDEV) + return hdlc_ioctl(dev, ifr, cmd); + + if (ifr->ifr_settings.type == IF_GET_IFACE) { + ifr->ifr_settings.type = port->iface; + if (ifr->ifr_settings.size < size) { + ifr->ifr_settings.size = size; /* data size wanted */ + return -ENOBUFS; + } + if (copy_to_user(line, &port->settings, size)) + return -EFAULT; + return 0; + + } + + if (port->card->type == PC300_X21 && + (ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL || + ifr->ifr_settings.type == IF_IFACE_X21)) + new_type = IF_IFACE_X21; + + else if (port->card->type == PC300_RSV && + (ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL || + ifr->ifr_settings.type == IF_IFACE_V35)) + new_type = IF_IFACE_V35; + + else if (port->card->type == PC300_RSV && + ifr->ifr_settings.type == IF_IFACE_V24) + new_type = IF_IFACE_V24; + + else + return hdlc_ioctl(dev, ifr, cmd); + + if (!capable(CAP_NET_ADMIN)) + return -EPERM; + + if (copy_from_user(&new_line, line, size)) + return -EFAULT; + + if (new_line.clock_type != CLOCK_EXT && + new_line.clock_type != CLOCK_TXFROMRX && + new_line.clock_type != CLOCK_INT && + new_line.clock_type != CLOCK_TXINT) + return -EINVAL; /* No such clock setting */ + + if (new_line.loopback != 0 && new_line.loopback != 1) + return -EINVAL; + + memcpy(&port->settings, &new_line, size); /* Update settings */ + port->iface = new_type; + pc300_set_iface(port); + return 0; +} + + + +static void pc300_pci_remove_one(struct pci_dev *pdev) +{ + int i; + card_t *card = pci_get_drvdata(pdev); + + if (!card) + BUG(); + + for(i = 0; i < 2; i++) + if (card->ports[i].card) + unregister_hdlc_device(&card->ports[i].hdlc); + + if (card->irq) + free_irq(card->irq, card); + iounmap(card->rambase); + iounmap(card->scabase); + iounmap(card->plxbase); + pci_release_regions(pdev); + kfree(card); + pci_set_drvdata(pdev, NULL); +} + + + +static void __devinit plx_init(card_t *card) +{ + plx9050 *plx_ctl = (plx9050 *)card->plxbase; + + /* Reset PLX */ + writel(readl(&plx_ctl->init_ctrl) | 0x40000000, &plx_ctl->init_ctrl); + udelay(100L); + writel(readl(&plx_ctl->init_ctrl) & ~0x40000000, &plx_ctl->init_ctrl); + + /* Reload Config. Registers from EEPROM */ + writel(readl(&plx_ctl->init_ctrl) | 0x20000000, &plx_ctl->init_ctrl); + udelay(100L); + writel(readl(&plx_ctl->init_ctrl) & ~0x20000000, &plx_ctl->init_ctrl); +} + + + +static int __devinit pc300_pci_init_one(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + card_t *card; + u8 rev_id; + int i; + +#ifndef MODULE + static int printed_version; + if (!printed_version++) + printk(KERN_INFO "%s\n", version); +#endif + + i = pci_enable_device(pdev); + if (i) + return i; + + i = pci_request_regions(pdev, "PC300"); + if (i) + return i; + + card = kmalloc(sizeof(card_t), GFP_KERNEL); + if (card == NULL) { + printk(KERN_ERR "pc300: unable to allocate memory\n"); + return -ENOBUFS; + } + memset(card, 0, sizeof(card_t)); + + pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); + + card->plxphys = pci_resource_start(pdev,0) & PCI_BASE_ADDRESS_MEM_MASK; + card->plxbase = ioremap(card->plxphys, PC300_PLX_WIN); + + card->scaphys = pci_resource_start(pdev,2) & PCI_BASE_ADDRESS_MEM_MASK; + card->scabase = ioremap(card->scaphys, PC300_SCASIZE); + + card->ramphys = pci_resource_start(pdev,3) & PCI_BASE_ADDRESS_MEM_MASK; + card->rambase = ioremap(card->ramphys, PC300_RAMSIZE); + + card->ramsize = sca_detect_ram(card, card->rambase, PC300_RAMSIZE); + + /* Enable interrupts on the PCI bridge */ + plx_init(card); + writew(readw(&card->plxbase->intr_ctrl_stat) | 0x0040, + &card->plxbase->intr_ctrl_stat); + +#ifdef CONFIG_PC300_PCI_CLOCK + /* Set board clock to PCI clock */ + writel(readl(&card->plxbase->init_ctrl) | 0x00000004UL, + &card->plxbase->init_ctrl); +#else + /* Set board clock to internal oscillator clock */ + writel(readl(&card->plxbase->init_ctrl) &~0x00000004UL, + &card->plxbase->init_ctrl); +#endif + + if (readl(&card->plxbase->init_ctrl) & PC300_CTYPE_MASK) + card->type = PC300_X21; + else + card->type = PC300_RSV; + + if (pdev->device == PCI_DEVICE_ID_PC300_RX_1 || + pdev->device == PCI_DEVICE_ID_PC300_TE_1) + card->n_ports = 1; + else + card->n_ports = 2; + + pci_set_drvdata(pdev, card); + + /* Allocate IRQ */ + if(request_irq(pdev->irq, sca_intr, SA_SHIRQ, devname, card)) { + printk(KERN_WARNING "pc300: could not allocate IRQ%d.\n", + pdev->irq); + pc300_pci_remove_one(pdev); + return -EBUSY; + } + card->irq = pdev->irq; + + /* number of TX + RX buffers for one port */ + i = card->ramsize / (card->n_ports * (sizeof(pkt_desc) +HDLC_MAX_MRU)); + card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS); + card->rx_ring_buffers = i - card->tx_ring_buffers; + + card->buff_offset = card->n_ports * sizeof(pkt_desc) * + (card->tx_ring_buffers + card->rx_ring_buffers); + + printk(KERN_INFO "pc300: PC300/%s %u KB RAM at 0x%x, IRQ%u, " + "using %u TX + %u RX packets rings\n", + card->type == PC300_X21 ? "X21" : "RSV", card->ramsize / 1024, + card->ramphys, card->irq, + card->tx_ring_buffers, card->rx_ring_buffers); + + if (card->tx_ring_buffers < 1) { + printk(KERN_ERR "pc300: RAM test failed\n"); + pc300_pci_remove_one(pdev); + return -EIO; + } + + sca_init(card, 0); + + // COTE not set - allows better TX DMA settings + // sca_out(sca_in(PCR, card) | PCR_COTE, PCR, card); + + sca_out(0x10, BTCR, card); + + for(i = 0; i < card->n_ports; i++) { + port_t *port = &card->ports[i]; + struct net_device *dev = hdlc_to_dev(&port->hdlc); + port->phy_node = i; + + spin_lock_init(&port->lock); + dev->irq = card->irq; + dev->mem_start = card->ramphys; + dev->mem_end = card->ramphys + card->ramsize - 1; + dev->tx_queue_len = 50; + dev->do_ioctl = pc300_ioctl; + dev->open = pc300_open; + dev->stop = pc300_close; + port->hdlc.attach = sca_attach; + port->hdlc.xmit = sca_xmit; + port->settings.clock_type = CLOCK_EXT; + if (card->type == PC300_X21) + port->iface = IF_IFACE_X21; + else + port->iface = IF_IFACE_V35; + + if(register_hdlc_device(&port->hdlc)) { + printk("pc300: unable to register hdlc device\n"); + pc300_pci_remove_one(pdev); + return -ENOBUFS; + } + port->card = card; + sca_init_sync_port(port); /* Set up SCA memory */ + + printk(KERN_INFO "%s: PC300 node %d\n", + hdlc_to_name(&port->hdlc), port->phy_node); + } + return 0; +} + + + +static struct pci_device_id pc300_pci_tbl[] __devinitdata = { + { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_1, PCI_ANY_ID, + PCI_ANY_ID, 0, 0, 0 }, + { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_2, PCI_ANY_ID, + PCI_ANY_ID, 0, 0, 0 }, + { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_1, PCI_ANY_ID, + PCI_ANY_ID, 0, 0, 0 }, + { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_2, PCI_ANY_ID, + PCI_ANY_ID, 0, 0, 0 }, + { 0, } +}; + + +static struct pci_driver pc300_pci_driver = { + name: "PC300", + id_table: pc300_pci_tbl, + probe: pc300_pci_init_one, + remove: pc300_pci_remove_one, +}; + + +static int __init pc300_init_module(void) +{ +#ifdef MODULE + printk(KERN_INFO "%s\n", version); +#endif + if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) { + printk(KERN_ERR "pc300: Invalid PCI clock frequency\n"); + return -EINVAL; + } + return pci_module_init(&pc300_pci_driver); +} + + + +static void __exit pc300_cleanup_module(void) +{ + pci_unregister_driver(&pc300_pci_driver); +} + +MODULE_AUTHOR("Krzysztof Halasa "); +MODULE_DESCRIPTION("Cyclades PC300 serial port driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(pci, pc300_pci_tbl); +#ifndef CONFIG_PC300TOO_CRYSTAL_CLOCK +MODULE_PARM(pci_clock_freq, "i"); +MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz"); +#endif +EXPORT_NO_SYMBOLS; +module_init(pc300_init_module); +module_exit(pc300_cleanup_module); --- linux-2.4.20/Documentation/Configure.help 2003-04-07 18:27:30.000000000 +0200 +++ linux-2.4.20.new/Documentation/Configure.help 2003-04-07 18:25:18.000000000 +0200 @@ -10577,6 +10577,36 @@ If unsure, say Y here. +CONFIG_PC300TOO + This is alternative driver for PC300 RSV/X21 PCI cards made by + Cyclades, Inc. If you have such a card, say Y or M here and see + + + If you want to compile the driver as a module ( = code which can be + inserted in and removed from the running kernel whenever you want), + say M here and read . The module + will be called pc300too.o. + + If unsure, say N here. + +CONFIG_PC300TOO_CRYSTAL_CLOCK + This option changes the clock source used by the card circuitry. + Lower clock frequency means lower maximum transmission rate. + + If unsure, say N here. + +CONFIG_PCI200SYN + This driver is for PCI200SYN cards made by Goramo sp. j. + If you have such a card, say Y or M here and see + + + If you want to compile the driver as a module ( = code which can be + inserted in and removed from the running kernel whenever you want), + say M here and read . The module + will be called pci200syn.o. + + If unsure, say N here. + Ethernet (10 or 100Mbit) CONFIG_NET_ETHERNET Ethernet (also called IEEE 802.3 or ISO 8802-2) is the most common --- linux-2.4.20/drivers/net/wan/Config.in 2003-04-07 18:27:30.000000000 +0200 +++ linux-2.4.20.new/drivers/net/wan/Config.in 2003-04-07 18:28:56.000000000 +0200 @@ -82,6 +82,11 @@ fi dep_tristate ' SDL RISCom/N2 support' CONFIG_N2 $CONFIG_HDLC dep_tristate ' Moxa C101 support' CONFIG_C101 $CONFIG_HDLC + dep_tristate ' Cyclades PC300 RSV/X21 alternative support' CONFIG_PC300TOO $CONFIG_HDLC + if [ "$CONFIG_PC300TOO" != "n" ]; then + bool ' Use 24.576 MHz crystal clock instead of 33 MHz PCI clock' CONFIG_PC300TOO_CRYSTAL_CLOCK + fi + dep_tristate ' Goramo PCI200SYN support' CONFIG_PCI200SYN $CONFIG_HDLC bool ' Debug received/transmitted packets' CONFIG_HDLC_DEBUG_PKT bool ' Debug hard_header routines' CONFIG_HDLC_DEBUG_HARD_HEADER bool ' Debug FECN/BECN conditions' CONFIG_HDLC_DEBUG_ECN