diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/Documentation/DocBook/kernel-api.tmpl linux-2.5/Documentation/DocBook/kernel-api.tmpl
--- linux-2.5.60/Documentation/DocBook/kernel-api.tmpl 2003-02-10 17:37:54.000000000 -0100
+++ linux-2.5/Documentation/DocBook/kernel-api.tmpl 2003-01-06 14:40:09.000000000 -0100
@@ -46,13 +46,19 @@
!Iinclude/asm-i386/unaligned.h
+ Delaying, scheduling, and timer routines
+!Ekernel/context.c
+!Ekernel/timer.c
+
+
+ Misc functions
+!Ekernel/exit.c
+
@@ -388,7 +394,7 @@ X!Edrivers/usb/core/config.c
drivers/video/fbgen.c has no docs, which stuffs up the sgml. Comment
out until somebody adds docs. KAO
Frame Buffer Generic Functions
-X!Idrivers/video/fbgen.c
+!Edrivers/video/fbgen.c
KAO -->
Frame Buffer Video Mode Database
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/Documentation/kernel-doc-nano-HOWTO.txt linux-2.5/Documentation/kernel-doc-nano-HOWTO.txt
--- linux-2.5.60/Documentation/kernel-doc-nano-HOWTO.txt 2003-02-10 17:38:30.000000000 -0100
+++ linux-2.5/Documentation/kernel-doc-nano-HOWTO.txt 2003-01-17 00:57:19.000000000 -0100
@@ -69,10 +69,10 @@ if ($#ARGV < 0) {
mkdir $ARGV[0],0777;
$state = 0;
while () {
- if (/^\.TH \"[^\"]*\" 4 \"([^\"]*)\"/) {
+ if (/^\.TH \"[^\"]*\" (\d) \"([^\"]*)\"/) {
if ($state == 1) { close OUT }
$state = 1;
- $fn = "$ARGV[0]/$1.4";
+ $fn = "$ARGV[0]/$2.$1";
print STDERR "Creating $fn\n";
open OUT, ">$fn" or die "can't open $fn: $!\n";
print OUT $_;
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/Documentation/sound/rme96xx linux-2.5/Documentation/sound/rme96xx
--- linux-2.5.60/Documentation/sound/rme96xx 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/Documentation/sound/rme96xx 2003-01-17 00:57:20.000000000 -0100
@@ -0,0 +1,767 @@
+Beta release of the rme96xx (driver for RME 96XX cards like the
+"Hammerfall" and the "Hammerfall light")
+
+Important: The driver module has to be installed on a freshly rebooted system,
+otherwise the driver might not be able to acquire its buffers.
+
+features:
+
+ - OSS programming interface (i.e. runs with standard OSS soundsoftware)
+ - OSS/Multichannel interface (OSS multichannel is done by just aquiring
+ more than 2 channels). The driver does not use more than one device
+ ( yet .. this feature may be implemented later )
+ - more than one RME card supported
+
+The driver uses a specific multichannel interface, which I will document
+when the driver gets stable. (take a look at the defines in rme96xx.h,
+which adds blocked multichannel formats i.e instead of
+lrlrlrlr --> llllrrrr etc.
+
+Use the "rmectrl" programm to look at the status of the card ..
+or use xrmectrl, a GUI interface for the ctrl program.
+
+What you can do with the rmectrl program is to set the stereo device for
+OSS emulation (e.g. if you use SPDIF out).
+
+You do:
+
+./ctrl offset 24 24
+
+which makes the stereo device use channels 25 and 26.
+
+Guenter Geiger
+
+copy the first part of the attached source code into rmectrl.c
+and the second part into xrmectrl (or get the program from
+http://gige.xdv.org/pages/soft/pages/rme)
+
+to compile: gcc -o rmectrl rmectrl.c
+------------------------------ snip ------------------------------------
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "rme96xx.h"
+
+/*
+ remctrl.c
+ (C) 2000 Guenter Geiger
+ HP20020201 - Heiko Purnhagen
+*/
+
+/* # define DEVICE_NAME "/dev/mixer" */
+# define DEVICE_NAME "/dev/mixer1"
+
+
+void usage(void)
+{
+ fprintf(stderr,"usage: rmectrl [/dev/mixer] [command [options]]\n\n");
+ fprintf(stderr,"where command is one of:\n");
+ fprintf(stderr," help show this help\n");
+ fprintf(stderr," status show status bits\n");
+ fprintf(stderr," control show control bits\n");
+ fprintf(stderr," mix show mixer/offset status\n");
+ fprintf(stderr," master set sync master\n");
+ fprintf(stderr," pro set spdif out pro\n");
+ fprintf(stderr," emphasis set spdif out emphasis\n");
+ fprintf(stderr," dolby set spdif out no audio\n");
+ fprintf(stderr," optout set spdif out optical\n");
+ fprintf(stderr," wordclock set sync wordclock\n");
+ fprintf(stderr," spdifin set spdif in (0=optical,1=coax,2=intern)\n");
+ fprintf(stderr," syncref set sync source (0=ADAT1,1=ADAT2,2=ADAT3,3=SPDIF)\n");
+ fprintf(stderr," adat1cd set ADAT1 on internal CD\n");
+ fprintf(stderr," offset set dev (0..3) offset (0..25)\n");
+ exit(-1);
+}
+
+
+int main(int argc, char* argv[])
+{
+ int cards;
+ int ret;
+ int i;
+ double ft;
+ int fd, fdwr;
+ int param,orig;
+ rme_status_t stat;
+ rme_ctrl_t ctrl;
+ char *device;
+ int argidx;
+
+ if (argc < 2)
+ usage();
+
+ if (*argv[1]=='/') {
+ device = argv[1];
+ argidx = 2;
+ }
+ else {
+ device = DEVICE_NAME;
+ argidx = 1;
+ }
+
+ fprintf(stdout,"mixer device %s\n",device);
+ if ((fd = open(device,O_RDONLY)) < 0) {
+ fprintf(stdout,"opening device failed\n");
+ exit(-1);
+ }
+
+ if ((fdwr = open(device,O_WRONLY)) < 0) {
+ fprintf(stdout,"opening device failed\n");
+ exit(-1);
+ }
+
+ if (argc < argidx+1)
+ usage();
+
+ if (!strcmp(argv[argidx],"help"))
+ usage();
+ if (!strcmp(argv[argidx],"-h"))
+ usage();
+ if (!strcmp(argv[argidx],"--help"))
+ usage();
+
+ if (!strcmp(argv[argidx],"status")) {
+ ioctl(fd,SOUND_MIXER_PRIVATE2,&stat);
+ fprintf(stdout,"stat.irq %d\n",stat.irq);
+ fprintf(stdout,"stat.lockmask %d\n",stat.lockmask);
+ fprintf(stdout,"stat.sr48 %d\n",stat.sr48);
+ fprintf(stdout,"stat.wclock %d\n",stat.wclock);
+ fprintf(stdout,"stat.bufpoint %d\n",stat.bufpoint);
+ fprintf(stdout,"stat.syncmask %d\n",stat.syncmask);
+ fprintf(stdout,"stat.doublespeed %d\n",stat.doublespeed);
+ fprintf(stdout,"stat.tc_busy %d\n",stat.tc_busy);
+ fprintf(stdout,"stat.tc_out %d\n",stat.tc_out);
+ fprintf(stdout,"stat.crystalrate %d (0=64k 3=96k 4=88.2k 5=48k 6=44.1k 7=32k)\n",stat.crystalrate);
+ fprintf(stdout,"stat.spdif_error %d\n",stat.spdif_error);
+ fprintf(stdout,"stat.bufid %d\n",stat.bufid);
+ fprintf(stdout,"stat.tc_valid %d\n",stat.tc_valid);
+ exit (0);
+ }
+
+ if (!strcmp(argv[argidx],"control")) {
+ ioctl(fd,SOUND_MIXER_PRIVATE3,&ctrl);
+ fprintf(stdout,"ctrl.start %d\n",ctrl.start);
+ fprintf(stdout,"ctrl.latency %d (0=64 .. 7=8192)\n",ctrl.latency);
+ fprintf(stdout,"ctrl.master %d\n",ctrl.master);
+ fprintf(stdout,"ctrl.ie %d\n",ctrl.ie);
+ fprintf(stdout,"ctrl.sr48 %d\n",ctrl.sr48);
+ fprintf(stdout,"ctrl.spare %d\n",ctrl.spare);
+ fprintf(stdout,"ctrl.doublespeed %d\n",ctrl.doublespeed);
+ fprintf(stdout,"ctrl.pro %d\n",ctrl.pro);
+ fprintf(stdout,"ctrl.emphasis %d\n",ctrl.emphasis);
+ fprintf(stdout,"ctrl.dolby %d\n",ctrl.dolby);
+ fprintf(stdout,"ctrl.opt_out %d\n",ctrl.opt_out);
+ fprintf(stdout,"ctrl.wordclock %d\n",ctrl.wordclock);
+ fprintf(stdout,"ctrl.spdif_in %d (0=optical,1=coax,2=intern)\n",ctrl.spdif_in);
+ fprintf(stdout,"ctrl.sync_ref %d (0=ADAT1,1=ADAT2,2=ADAT3,3=SPDIF)\n",ctrl.sync_ref);
+ fprintf(stdout,"ctrl.spdif_reset %d\n",ctrl.spdif_reset);
+ fprintf(stdout,"ctrl.spdif_select %d\n",ctrl.spdif_select);
+ fprintf(stdout,"ctrl.spdif_clock %d\n",ctrl.spdif_clock);
+ fprintf(stdout,"ctrl.spdif_write %d\n",ctrl.spdif_write);
+ fprintf(stdout,"ctrl.adat1_cd %d\n",ctrl.adat1_cd);
+ exit (0);
+ }
+
+ if (!strcmp(argv[argidx],"mix")) {
+ rme_mixer mix;
+ int i;
+
+ for (i=0; i<4; i++) {
+ mix.devnr = i;
+ ioctl(fd,SOUND_MIXER_PRIVATE1,&mix);
+ if (mix.devnr == i) {
+ fprintf(stdout,"devnr %d\n",mix.devnr);
+ fprintf(stdout,"mix.i_offset %2d (0-25)\n",mix.i_offset);
+ fprintf(stdout,"mix.o_offset %2d (0-25)\n",mix.o_offset);
+ }
+ }
+ exit (0);
+ }
+
+/* the control flags */
+
+ if (argc < argidx+2)
+ usage();
+
+ if (!strcmp(argv[argidx],"master")) {
+ int val = atoi(argv[argidx+1]);
+ ioctl(fd,SOUND_MIXER_PRIVATE3,&ctrl);
+ printf("master = %d\n",val);
+ ctrl.master = val;
+ ioctl(fdwr,SOUND_MIXER_PRIVATE3,&ctrl);
+ exit (0);
+ }
+
+ if (!strcmp(argv[argidx],"pro")) {
+ int val = atoi(argv[argidx+1]);
+ ioctl(fd,SOUND_MIXER_PRIVATE3,&ctrl);
+ printf("pro = %d\n",val);
+ ctrl.pro = val;
+ ioctl(fdwr,SOUND_MIXER_PRIVATE3,&ctrl);
+ exit (0);
+ }
+
+ if (!strcmp(argv[argidx],"emphasis")) {
+ int val = atoi(argv[argidx+1]);
+ ioctl(fd,SOUND_MIXER_PRIVATE3,&ctrl);
+ printf("emphasis = %d\n",val);
+ ctrl.emphasis = val;
+ ioctl(fdwr,SOUND_MIXER_PRIVATE3,&ctrl);
+ exit (0);
+ }
+
+ if (!strcmp(argv[argidx],"dolby")) {
+ int val = atoi(argv[argidx+1]);
+ ioctl(fd,SOUND_MIXER_PRIVATE3,&ctrl);
+ printf("dolby = %d\n",val);
+ ctrl.dolby = val;
+ ioctl(fdwr,SOUND_MIXER_PRIVATE3,&ctrl);
+ exit (0);
+ }
+
+ if (!strcmp(argv[argidx],"optout")) {
+ int val = atoi(argv[argidx+1]);
+ ioctl(fd,SOUND_MIXER_PRIVATE3,&ctrl);
+ printf("optout = %d\n",val);
+ ctrl.opt_out = val;
+ ioctl(fdwr,SOUND_MIXER_PRIVATE3,&ctrl);
+ exit (0);
+ }
+
+ if (!strcmp(argv[argidx],"wordclock")) {
+ int val = atoi(argv[argidx+1]);
+ ioctl(fd,SOUND_MIXER_PRIVATE3,&ctrl);
+ printf("wordclock = %d\n",val);
+ ctrl.wordclock = val;
+ ioctl(fdwr,SOUND_MIXER_PRIVATE3,&ctrl);
+ exit (0);
+ }
+
+ if (!strcmp(argv[argidx],"spdifin")) {
+ int val = atoi(argv[argidx+1]);
+ ioctl(fd,SOUND_MIXER_PRIVATE3,&ctrl);
+ printf("spdifin = %d\n",val);
+ ctrl.spdif_in = val;
+ ioctl(fdwr,SOUND_MIXER_PRIVATE3,&ctrl);
+ exit (0);
+ }
+
+ if (!strcmp(argv[argidx],"syncref")) {
+ int val = atoi(argv[argidx+1]);
+ ioctl(fd,SOUND_MIXER_PRIVATE3,&ctrl);
+ printf("syncref = %d\n",val);
+ ctrl.sync_ref = val;
+ ioctl(fdwr,SOUND_MIXER_PRIVATE3,&ctrl);
+ exit (0);
+ }
+
+ if (!strcmp(argv[argidx],"adat1cd")) {
+ int val = atoi(argv[argidx+1]);
+ ioctl(fd,SOUND_MIXER_PRIVATE3,&ctrl);
+ printf("adat1cd = %d\n",val);
+ ctrl.adat1_cd = val;
+ ioctl(fdwr,SOUND_MIXER_PRIVATE3,&ctrl);
+ exit (0);
+ }
+
+/* setting offset */
+
+ if (argc < argidx+4)
+ usage();
+
+ if (!strcmp(argv[argidx],"offset")) {
+ rme_mixer mix;
+
+ mix.devnr = atoi(argv[argidx+1]);
+
+ mix.i_offset = atoi(argv[argidx+2]);
+ mix.o_offset = atoi(argv[argidx+3]);
+ ioctl(fdwr,SOUND_MIXER_PRIVATE1,&mix);
+ fprintf(stdout,"devnr %d\n",mix.devnr);
+ fprintf(stdout,"mix.i_offset to %d\n",mix.i_offset);
+ fprintf(stdout,"mix.o_offset to %d\n",mix.o_offset);
+ exit (0);
+ }
+
+ usage();
+ exit (0); /* to avoid warning */
+}
+
+
+---------------------------- --------------------------------
+#!/usr/bin/wish
+
+# xrmectrl
+# (C) 2000 Guenter Geiger
+# HP20020201 - Heiko Purnhagen
+
+#set defaults "-relief ridged"
+set CTRLPROG "./rmectrl"
+if {$argc} {
+ set CTRLPROG "$CTRLPROG $argv"
+}
+puts "CTRLPROG $CTRLPROG"
+
+frame .butts
+button .butts.exit -text "Exit" -command "exit" -relief ridge
+#button .butts.state -text "State" -command "get_all"
+
+pack .butts.exit -side left
+pack .butts -side bottom
+
+
+#
+# STATUS
+#
+
+frame .status
+
+# Sampling Rate
+
+frame .status.sr
+label .status.sr.text -text "Sampling Rate" -justify left
+radiobutton .status.sr.441 -selectcolor red -text "44.1 kHz" -width 10 -anchor nw -variable srate -value 44100 -font times
+radiobutton .status.sr.480 -selectcolor red -text "48 kHz" -width 10 -anchor nw -variable srate -value 48000 -font times
+radiobutton .status.sr.882 -selectcolor red -text "88.2 kHz" -width 10 -anchor nw -variable srate -value 88200 -font times
+radiobutton .status.sr.960 -selectcolor red -text "96 kHz" -width 10 -anchor nw -variable srate -value 96000 -font times
+
+pack .status.sr.text .status.sr.441 .status.sr.480 .status.sr.882 .status.sr.960 -side top -padx 3
+
+# Lock
+
+frame .status.lock
+label .status.lock.text -text "Lock" -justify left
+checkbutton .status.lock.adat1 -selectcolor red -text "ADAT1" -anchor nw -width 10 -variable adatlock1 -font times
+checkbutton .status.lock.adat2 -selectcolor red -text "ADAT2" -anchor nw -width 10 -variable adatlock2 -font times
+checkbutton .status.lock.adat3 -selectcolor red -text "ADAT3" -anchor nw -width 10 -variable adatlock3 -font times
+
+pack .status.lock.text .status.lock.adat1 .status.lock.adat2 .status.lock.adat3 -side top -padx 3
+
+# Sync
+
+frame .status.sync
+label .status.sync.text -text "Sync" -justify left
+checkbutton .status.sync.adat1 -selectcolor red -text "ADAT1" -anchor nw -width 10 -variable adatsync1 -font times
+checkbutton .status.sync.adat2 -selectcolor red -text "ADAT2" -anchor nw -width 10 -variable adatsync2 -font times
+checkbutton .status.sync.adat3 -selectcolor red -text "ADAT3" -anchor nw -width 10 -variable adatsync3 -font times
+
+pack .status.sync.text .status.sync.adat1 .status.sync.adat2 .status.sync.adat3 -side top -padx 3
+
+# Timecode
+
+frame .status.tc
+label .status.tc.text -text "Timecode" -justify left
+checkbutton .status.tc.busy -selectcolor red -text "busy" -anchor nw -width 10 -variable tcbusy -font times
+checkbutton .status.tc.out -selectcolor red -text "out" -anchor nw -width 10 -variable tcout -font times
+checkbutton .status.tc.valid -selectcolor red -text "valid" -anchor nw -width 10 -variable tcvalid -font times
+
+pack .status.tc.text .status.tc.busy .status.tc.out .status.tc.valid -side top -padx 3
+
+# SPDIF In
+
+frame .status.spdif
+label .status.spdif.text -text "SPDIF In" -justify left
+label .status.spdif.sr -text "--.- kHz" -anchor n -width 10 -font times
+checkbutton .status.spdif.error -selectcolor red -text "Input Lock" -anchor nw -width 10 -variable spdiferr -font times
+
+pack .status.spdif.text .status.spdif.sr .status.spdif.error -side top -padx 3
+
+pack .status.sr .status.lock .status.sync .status.tc .status.spdif -side left -fill x -anchor n -expand 1
+
+
+#
+# CONTROL
+#
+
+proc setprof {} {
+ global CTRLPROG
+ global spprof
+ exec $CTRLPROG pro $spprof
+}
+
+proc setemph {} {
+ global CTRLPROG
+ global spemph
+ exec $CTRLPROG emphasis $spemph
+}
+
+proc setnoaud {} {
+ global CTRLPROG
+ global spnoaud
+ exec $CTRLPROG dolby $spnoaud
+}
+
+proc setoptical {} {
+ global CTRLPROG
+ global spoptical
+ exec $CTRLPROG optout $spoptical
+}
+
+proc setspdifin {} {
+ global CTRLPROG
+ global spdifin
+ exec $CTRLPROG spdifin [expr $spdifin - 1]
+}
+
+proc setsyncsource {} {
+ global CTRLPROG
+ global syncsource
+ exec $CTRLPROG syncref [expr $syncsource -1]
+}
+
+
+proc setmaster {} {
+ global CTRLPROG
+ global master
+ exec $CTRLPROG master $master
+}
+
+proc setwordclock {} {
+ global CTRLPROG
+ global wordclock
+ exec $CTRLPROG wordclock $wordclock
+}
+
+proc setadat1cd {} {
+ global CTRLPROG
+ global adat1cd
+ exec $CTRLPROG adat1cd $adat1cd
+}
+
+
+frame .control
+
+# SPDIF In & SPDIF Out
+
+
+frame .control.spdif
+
+frame .control.spdif.in
+label .control.spdif.in.text -text "SPDIF In" -justify left
+radiobutton .control.spdif.in.input1 -text "Optical" -anchor nw -width 13 -variable spdifin -value 1 -command setspdifin -selectcolor blue -font times
+radiobutton .control.spdif.in.input2 -text "Coaxial" -anchor nw -width 13 -variable spdifin -value 2 -command setspdifin -selectcolor blue -font times
+radiobutton .control.spdif.in.input3 -text "Intern " -anchor nw -width 13 -variable spdifin -command setspdifin -value 3 -selectcolor blue -font times
+
+checkbutton .control.spdif.in.adat1cd -text "ADAT1 Intern" -anchor nw -width 13 -variable adat1cd -command setadat1cd -selectcolor blue -font times
+
+pack .control.spdif.in.text .control.spdif.in.input1 .control.spdif.in.input2 .control.spdif.in.input3 .control.spdif.in.adat1cd
+
+label .control.spdif.space
+
+frame .control.spdif.out
+label .control.spdif.out.text -text "SPDIF Out" -justify left
+checkbutton .control.spdif.out.pro -text "Professional" -anchor nw -width 13 -variable spprof -command setprof -selectcolor blue -font times
+checkbutton .control.spdif.out.emphasis -text "Emphasis" -anchor nw -width 13 -variable spemph -command setemph -selectcolor blue -font times
+checkbutton .control.spdif.out.dolby -text "NoAudio" -anchor nw -width 13 -variable spnoaud -command setnoaud -selectcolor blue -font times
+checkbutton .control.spdif.out.optout -text "Optical Out" -anchor nw -width 13 -variable spoptical -command setoptical -selectcolor blue -font times
+
+pack .control.spdif.out.optout .control.spdif.out.dolby .control.spdif.out.emphasis .control.spdif.out.pro .control.spdif.out.text -side bottom
+
+pack .control.spdif.in .control.spdif.space .control.spdif.out -side top -fill y -padx 3 -expand 1
+
+# Sync Mode & Sync Source
+
+frame .control.sync
+frame .control.sync.mode
+label .control.sync.mode.text -text "Sync Mode" -justify left
+checkbutton .control.sync.mode.master -text "Master" -anchor nw -width 13 -variable master -command setmaster -selectcolor blue -font times
+checkbutton .control.sync.mode.wc -text "Wordclock" -anchor nw -width 13 -variable wordclock -command setwordclock -selectcolor blue -font times
+
+pack .control.sync.mode.text .control.sync.mode.master .control.sync.mode.wc
+
+label .control.sync.space
+
+frame .control.sync.src
+label .control.sync.src.text -text "Sync Source" -justify left
+radiobutton .control.sync.src.input1 -text "ADAT1" -anchor nw -width 13 -variable syncsource -value 1 -command setsyncsource -selectcolor blue -font times
+radiobutton .control.sync.src.input2 -text "ADAT2" -anchor nw -width 13 -variable syncsource -value 2 -command setsyncsource -selectcolor blue -font times
+radiobutton .control.sync.src.input3 -text "ADAT3" -anchor nw -width 13 -variable syncsource -command setsyncsource -value 3 -selectcolor blue -font times
+radiobutton .control.sync.src.input4 -text "SPDIF" -anchor nw -width 13 -variable syncsource -command setsyncsource -value 4 -selectcolor blue -font times
+
+pack .control.sync.src.input4 .control.sync.src.input3 .control.sync.src.input2 .control.sync.src.input1 .control.sync.src.text -side bottom
+
+pack .control.sync.mode .control.sync.space .control.sync.src -side top -fill y -padx 3 -expand 1
+
+label .control.space -text "" -width 10
+
+# Buffer Size
+
+frame .control.buf
+label .control.buf.text -text "Buffer Size (Latency)" -justify left
+radiobutton .control.buf.b1 -selectcolor red -text "64 (1.5 ms)" -width 13 -anchor nw -variable ssrate -value 1 -font times
+radiobutton .control.buf.b2 -selectcolor red -text "128 (3 ms)" -width 13 -anchor nw -variable ssrate -value 2 -font times
+radiobutton .control.buf.b3 -selectcolor red -text "256 (6 ms)" -width 13 -anchor nw -variable ssrate -value 3 -font times
+radiobutton .control.buf.b4 -selectcolor red -text "512 (12 ms)" -width 13 -anchor nw -variable ssrate -value 4 -font times
+radiobutton .control.buf.b5 -selectcolor red -text "1024 (23 ms)" -width 13 -anchor nw -variable ssrate -value 5 -font times
+radiobutton .control.buf.b6 -selectcolor red -text "2048 (46 ms)" -width 13 -anchor nw -variable ssrate -value 6 -font times
+radiobutton .control.buf.b7 -selectcolor red -text "4096 (93 ms)" -width 13 -anchor nw -variable ssrate -value 7 -font times
+radiobutton .control.buf.b8 -selectcolor red -text "8192 (186 ms)" -width 13 -anchor nw -variable ssrate -value 8 -font times
+
+pack .control.buf.text .control.buf.b1 .control.buf.b2 .control.buf.b3 .control.buf.b4 .control.buf.b5 .control.buf.b6 .control.buf.b7 .control.buf.b8 -side top -padx 3
+
+# Offset
+
+frame .control.offset
+
+frame .control.offset.in
+label .control.offset.in.text -text "Offset In" -justify left
+label .control.offset.in.off0 -text "dev\#0: -" -anchor nw -width 10 -font times
+label .control.offset.in.off1 -text "dev\#1: -" -anchor nw -width 10 -font times
+label .control.offset.in.off2 -text "dev\#2: -" -anchor nw -width 10 -font times
+label .control.offset.in.off3 -text "dev\#3: -" -anchor nw -width 10 -font times
+
+pack .control.offset.in.text .control.offset.in.off0 .control.offset.in.off1 .control.offset.in.off2 .control.offset.in.off3
+
+label .control.offset.space
+
+frame .control.offset.out
+label .control.offset.out.text -text "Offset Out" -justify left
+label .control.offset.out.off0 -text "dev\#0: -" -anchor nw -width 10 -font times
+label .control.offset.out.off1 -text "dev\#1: -" -anchor nw -width 10 -font times
+label .control.offset.out.off2 -text "dev\#2: -" -anchor nw -width 10 -font times
+label .control.offset.out.off3 -text "dev\#3: -" -anchor nw -width 10 -font times
+
+pack .control.offset.out.off3 .control.offset.out.off2 .control.offset.out.off1 .control.offset.out.off0 .control.offset.out.text -side bottom
+
+pack .control.offset.in .control.offset.space .control.offset.out -side top -fill y -padx 3 -expand 1
+
+
+pack .control.spdif .control.sync .control.space .control.buf .control.offset -side left -fill both -anchor n -expand 1
+
+
+label .statustext -text Status -justify center -relief ridge
+label .controltext -text Control -justify center -relief ridge
+
+label .statusspace
+label .controlspace
+
+pack .statustext .status .statusspace .controltext .control .controlspace -side top -anchor nw -fill both -expand 1
+
+
+proc get_bit {output sstr} {
+ set idx1 [string last [concat $sstr 1] $output]
+ set idx1 [expr $idx1 != -1]
+ return $idx1
+}
+
+proc get_val {output sstr} {
+ set val [string wordend $output [string last $sstr $output]]
+ set val [string range $output $val [expr $val+1]]
+ return $val
+}
+
+proc get_val2 {output sstr} {
+ set val [string wordend $output [string first $sstr $output]]
+ set val [string range $output $val [expr $val+2]]
+ return $val
+}
+
+proc get_control {} {
+ global spprof
+ global spemph
+ global spnoaud
+ global spoptical
+ global spdifin
+ global ssrate
+ global master
+ global wordclock
+ global syncsource
+ global CTRLPROG
+
+ set f [open "| $CTRLPROG control" r+]
+ set ooo [read $f 1000]
+ close $f
+# puts $ooo
+
+ set spprof [ get_bit $ooo "pro"]
+ set spemph [ get_bit $ooo "emphasis"]
+ set spnoaud [ get_bit $ooo "dolby"]
+ set spoptical [ get_bit $ooo "opt_out"]
+ set spdifin [ expr [ get_val $ooo "spdif_in"] + 1]
+ set ssrate [ expr [ get_val $ooo "latency"] + 1]
+ set master [ expr [ get_val $ooo "master"]]
+ set wordclock [ expr [ get_val $ooo "wordclock"]]
+ set syncsource [ expr [ get_val $ooo "sync_ref"] + 1]
+}
+
+proc get_status {} {
+ global srate
+ global ctrlcom
+
+ global adatlock1
+ global adatlock2
+ global adatlock3
+
+ global adatsync1
+ global adatsync2
+ global adatsync3
+
+ global tcbusy
+ global tcout
+ global tcvalid
+
+ global spdiferr
+ global crystal
+ global .status.spdif.text
+ global CTRLPROG
+
+
+ set f [open "| $CTRLPROG status" r+]
+ set ooo [read $f 1000]
+ close $f
+# puts $ooo
+
+# samplerate
+
+ set idx1 [string last "sr48 1" $ooo]
+ set idx2 [string last "doublespeed 1" $ooo]
+ if {$idx1 >= 0} {
+ set fact1 48000
+ } else {
+ set fact1 44100
+ }
+
+ if {$idx2 >= 0} {
+ set fact2 2
+ } else {
+ set fact2 1
+ }
+ set srate [expr $fact1 * $fact2]
+# ADAT lock
+
+ set val [get_val $ooo lockmask]
+ set adatlock1 0
+ set adatlock2 0
+ set adatlock3 0
+ if {[expr $val & 1]} {
+ set adatlock3 1
+ }
+ if {[expr $val & 2]} {
+ set adatlock2 1
+ }
+ if {[expr $val & 4]} {
+ set adatlock1 1
+ }
+
+# ADAT sync
+ set val [get_val $ooo syncmask]
+ set adatsync1 0
+ set adatsync2 0
+ set adatsync3 0
+
+ if {[expr $val & 1]} {
+ set adatsync3 1
+ }
+ if {[expr $val & 2]} {
+ set adatsync2 1
+ }
+ if {[expr $val & 4]} {
+ set adatsync1 1
+ }
+
+# TC busy
+
+ set tcbusy [get_bit $ooo "busy"]
+ set tcout [get_bit $ooo "out"]
+ set tcvalid [get_bit $ooo "valid"]
+ set spdiferr [expr [get_bit $ooo "spdif_error"] == 0]
+
+# 000=64kHz, 100=88.2kHz, 011=96kHz
+# 111=32kHz, 110=44.1kHz, 101=48kHz
+
+ set val [get_val $ooo crystalrate]
+
+ set crystal "--.- kHz"
+ if {$val == 0} {
+ set crystal "64 kHz"
+ }
+ if {$val == 4} {
+ set crystal "88.2 kHz"
+ }
+ if {$val == 3} {
+ set crystal "96 kHz"
+ }
+ if {$val == 7} {
+ set crystal "32 kHz"
+ }
+ if {$val == 6} {
+ set crystal "44.1 kHz"
+ }
+ if {$val == 5} {
+ set crystal "48 kHz"
+ }
+ .status.spdif.sr configure -text $crystal
+}
+
+proc get_offset {} {
+ global inoffset
+ global outoffset
+ global CTRLPROG
+
+ set f [open "| $CTRLPROG mix" r+]
+ set ooo [read $f 1000]
+ close $f
+# puts $ooo
+
+ if { [string match "*devnr*" $ooo] } {
+ set ooo [string range $ooo [string wordend $ooo [string first devnr $ooo]] end]
+ set val [get_val2 $ooo i_offset]
+ .control.offset.in.off0 configure -text "dev\#0: $val"
+ set val [get_val2 $ooo o_offset]
+ .control.offset.out.off0 configure -text "dev\#0: $val"
+ } else {
+ .control.offset.in.off0 configure -text "dev\#0: -"
+ .control.offset.out.off0 configure -text "dev\#0: -"
+ }
+ if { [string match "*devnr*" $ooo] } {
+ set ooo [string range $ooo [string wordend $ooo [string first devnr $ooo]] end]
+ set val [get_val2 $ooo i_offset]
+ .control.offset.in.off1 configure -text "dev\#1: $val"
+ set val [get_val2 $ooo o_offset]
+ .control.offset.out.off1 configure -text "dev\#1: $val"
+ } else {
+ .control.offset.in.off1 configure -text "dev\#1: -"
+ .control.offset.out.off1 configure -text "dev\#1: -"
+ }
+ if { [string match "*devnr*" $ooo] } {
+ set ooo [string range $ooo [string wordend $ooo [string first devnr $ooo]] end]
+ set val [get_val2 $ooo i_offset]
+ .control.offset.in.off2 configure -text "dev\#2: $val"
+ set val [get_val2 $ooo o_offset]
+ .control.offset.out.off2 configure -text "dev\#2: $val"
+ } else {
+ .control.offset.in.off2 configure -text "dev\#2: -"
+ .control.offset.out.off2 configure -text "dev\#2: -"
+ }
+ if { [string match "*devnr*" $ooo] } {
+ set ooo [string range $ooo [string wordend $ooo [string first devnr $ooo]] end]
+ set val [get_val2 $ooo i_offset]
+ .control.offset.in.off3 configure -text "dev\#3: $val"
+ set val [get_val2 $ooo o_offset]
+ .control.offset.out.off3 configure -text "dev\#3: $val"
+ } else {
+ .control.offset.in.off3 configure -text "dev\#3: -"
+ .control.offset.out.off3 configure -text "dev\#3: -"
+ }
+}
+
+
+proc get_all {} {
+get_status
+get_control
+get_offset
+}
+
+# main
+while {1} {
+ after 200
+ get_all
+ update
+}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/MAINTAINERS linux-2.5/MAINTAINERS
--- linux-2.5.60/MAINTAINERS 2003-02-10 17:38:43.000000000 -0100
+++ linux-2.5/MAINTAINERS 2003-02-11 10:27:23.000000000 -0100
@@ -460,6 +460,13 @@ M: henrique@cyclades.com
W: http://www.cyclades.com/
S: Supported
+DAC960 RAID CONTROLLER DRIVER
+P: Dave Olien
+M dmo@osdl.org
+W: http://www.osdl.org/archive/dmo/DAC960
+L: linux-kernel@vger.kernel.org
+S: Maintained
+
DAMA SLAVE for AX.25
P: Joerg Reuter
M: jreuter@yaina.de
@@ -1500,6 +1507,11 @@ M: emoenke@gwdg.de
L: linux-kernel@vger.kernel.org
S: Maintained
+SC1200 WDT DRIVER
+P: Zwane Mwaikambo
+M: zwane@commfireservices.com
+S: Maintained
+
SCHEDULER
P: Ingo Molnar
M: mingo@elte.hu
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/Makefile linux-2.5/Makefile
--- linux-2.5.60/Makefile 2003-02-10 17:37:58.000000000 -0100
+++ linux-2.5/Makefile 2003-02-10 19:46:28.000000000 -0100
@@ -1,7 +1,7 @@
VERSION = 2
PATCHLEVEL = 5
SUBLEVEL = 60
-EXTRAVERSION =
+EXTRAVERSION =-dj1
# *DOCUMENTATION*
# To see a list of typical targets execute "make help"
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/Kconfig linux-2.5/arch/i386/Kconfig
--- linux-2.5.60/arch/i386/Kconfig 2003-02-10 17:38:00.000000000 -0100
+++ linux-2.5/arch/i386/Kconfig 2003-02-10 22:48:41.000000000 -0100
@@ -136,6 +136,7 @@ config M386
- "Winchip-2" for IDT Winchip 2.
- "Winchip-2A" for IDT Winchips with 3dNow! capabilities.
- "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
+ - "VIA C3-2 for VIA C3-2 "Nehemiah" (model 9 and above).
If you don't know what to do, choose "386".
@@ -174,7 +175,7 @@ config M686
against the f00f bug found in earlier Pentiums.
config MPENTIUMII
- bool "Pentium-II/Celeron(pre-Coppermine)"
+ bool "Pentium-II/Celeron(pre-Coppermine)"
help
Select this for Intel chips based on the Pentium-II and
pre-Coppermine Celeron core. This option enables an unaligned
@@ -260,6 +261,16 @@ config MCYRIXIII
treat this chip as a generic 586. Whilst the CPU is 686 class,
it lacks the cmov extension which gcc assumes is present when
generating 686 code.
+ Note, that Nehemiah (Model 9) and above will not boot with this
+ kernel due to them lacking the 3dnow instructions used in earlier
+ incarnations of the CPU.
+
+config MVIAC3_2
+ bool "VIA C3-2 (Nehemiah)"
+ help
+ Select this for a VIA C3 "Nehemiah". Selecting this enables usage of SSE
+ and tells gcc to treat the CPU as a 686.
+ Note, this kernel will not boot on older (pre model 9) C3s.
endchoice
@@ -278,8 +289,8 @@ config X86_XADD
config X86_L1_CACHE_SHIFT
int
- default "5" if MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCRUSOE || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586
default "4" if MELAN || M486 || M386
+ default "5" if MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCRUSOE || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2
default "6" if MK7 || MK8
default "7" if MPENTIUM4
@@ -325,12 +336,12 @@ config X86_POPAD_OK
config X86_ALIGNMENT_16
bool
- depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || MELAN || MK6 || M586MMX || M586TSC || M586 || M486
+ depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || MELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2
default y
config X86_TSC
bool
- depends on MWINCHIP3D || MWINCHIP2 || MCRUSOE || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8
+ depends on MWINCHIP3D || MWINCHIP2 || MCRUSOE || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2
default y
config X86_GOOD_APIC
@@ -345,7 +356,7 @@ config X86_INTEL_USERCOPY
config X86_USE_PPRO_CHECKSUM
bool
- depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMIII || MPENTIUMII || M686 || MK8
+ depends on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2
default y
config X86_USE_3DNOW
@@ -360,7 +371,7 @@ config X86_OOSTORE
config X86_PREFETCH
bool
- depends on MPENTIUMIII || MPENTIUM4
+ depends on MPENTIUMIII || MPENTIUM4 || MVIAC3_2
default y
config X86_SSE2
@@ -1005,6 +1016,16 @@ config X86_POWERNOW_K6
If in doubt, say N.
+config X86_POWERNOW_K7
+ tristate "AMD Mobile K7 PowerNow!"
+ depends on CPU_FREQ
+ help
+ This adds the CPUFreq driver for AMD mobile K7 processors.
+
+ For details, take a look at linux/Documentation/cpufreq.
+
+ If in doubt, say N.
+
config ELAN_CPUFREQ
tristate "AMD Elan"
depends on CPU_FREQ && MELAN
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/Makefile linux-2.5/arch/i386/Makefile
--- linux-2.5.60/arch/i386/Makefile 2003-02-10 17:38:19.000000000 -0100
+++ linux-2.5/arch/i386/Makefile 2003-02-07 17:59:54.000000000 -0100
@@ -46,6 +46,7 @@ cflags-$(CONFIG_MWINCHIP3D) += -march=i5
cflags-$(CONFIG_MCYRIXIII) += $(call check_gcc,-march=c3,-march=i486)
# The alignment flags change with gcc 3.2
cflags-$(CONFIG_MCYRIXIII) += $(call check_gcc,-falign-functions=0 -falign-jumps=0 -falign-loops=0,-malign-functions=0 -malign-jumps=0 -malign-loops=0)
+cflags-$(CONFIG_MVIAC3_2) += $(call check_gcc,-march=c3-2,-march=i686)
CFLAGS += $(cflags-y)
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/boot/bootsect.S linux-2.5/arch/i386/boot/bootsect.S
--- linux-2.5.60/arch/i386/boot/bootsect.S 2003-02-10 17:38:38.000000000 -0100
+++ linux-2.5/arch/i386/boot/bootsect.S 2003-01-21 18:18:35.000000000 -0100
@@ -405,7 +405,7 @@ kill_motor:
ret
sectors: .word 0
-disksizes: .byte 36, 18, 15, 9
+disksizes: .byte 36, 21, 18, 15, 9
msg1: .byte 13, 10
.ascii "Loading"
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/kernel/apic.c linux-2.5/arch/i386/kernel/apic.c
--- linux-2.5.60/arch/i386/kernel/apic.c 2003-02-10 17:39:16.000000000 -0100
+++ linux-2.5/arch/i386/kernel/apic.c 2003-02-11 10:27:23.000000000 -0100
@@ -52,7 +52,7 @@ int using_apic_timer = 0;
int prof_multiplier[NR_CPUS] = { 1, };
int prof_old_multiplier[NR_CPUS] = { 1, };
-int prof_counter[NR_CPUS] = { 1, };
+DEFINE_PER_CPU(int, prof_counter) = 1;
int get_maxlvt(void)
{
@@ -997,7 +997,7 @@ inline void smp_local_timer_interrupt(st
x86_do_profile(regs);
- if (--prof_counter[cpu] <= 0) {
+ if (--per_cpu(prof_counter, cpu) <= 0) {
/*
* The multiplier may have changed since the last time we got
* to this point as a result of the user writing to
@@ -1006,10 +1006,12 @@ inline void smp_local_timer_interrupt(st
*
* Interrupts are already masked off at this point.
*/
- prof_counter[cpu] = prof_multiplier[cpu];
- if (prof_counter[cpu] != prof_old_multiplier[cpu]) {
- __setup_APIC_LVTT(calibration_result/prof_counter[cpu]);
- prof_old_multiplier[cpu] = prof_counter[cpu];
+ per_cpu(prof_counter, cpu) = prof_multiplier[cpu];
+ if (per_cpu(prof_counter, cpu) != prof_old_multiplier[cpu]) {
+ __setup_APIC_LVTT(
+ calibration_result/
+ per_cpu(prof_counter, cpu));
+ prof_old_multiplier[cpu] = per_cpu(prof_counter, cpu);
}
#ifdef CONFIG_SMP
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/kernel/apm.c linux-2.5/arch/i386/kernel/apm.c
--- linux-2.5.60/arch/i386/kernel/apm.c 2003-02-10 17:37:57.000000000 -0100
+++ linux-2.5/arch/i386/kernel/apm.c 2003-02-06 03:15:33.000000000 -0100
@@ -1233,16 +1233,18 @@ static void get_time_diff(void)
#endif
}
-static inline void reinit_timer(void)
+static void reinit_timer(void)
{
#ifdef INIT_TIMER_AFTER_SUSPEND
+ unsigned long flags;
+ extern spinlock_t i8253_lock;
+
+ spin_lock_irqsave(&i8253_lock, flags);
/* set the clock to 100 Hz */
outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */
- udelay(10);
outb_p(LATCH & 0xff , 0x40); /* LSB */
- udelay(10);
- outb(LATCH >> 8 , 0x40); /* MSB */
- udelay(10);
+ outb_p(LATCH >> 8, 0x40); /* MSB */
+ spin_unlock_irqrestore(&i8253_lock, flags);
#endif
}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/kernel/cpu/centaur.c linux-2.5/arch/i386/kernel/cpu/centaur.c
--- linux-2.5.60/arch/i386/kernel/cpu/centaur.c 2003-02-10 17:38:44.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/centaur.c 2003-02-11 10:49:12.000000000 -0100
@@ -395,6 +395,8 @@ static void __init init_centaur(struct c
set_bit(X86_FEATURE_CX8, c->x86_capability);
set_bit(X86_FEATURE_3DNOW, c->x86_capability);
+ case 9: /* Nehemiah */
+ default:
get_model_name(c);
display_cacheinfo(c);
break;
@@ -408,6 +410,13 @@ static unsigned int centaur_size_cache(s
/* VIA C3 CPUs (670-68F) need further shifting. */
if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
size >>= 8;
+
+ /* VIA also screwed up Nehemiah stepping 1, and made
+ it return '65KB' instead of '64KB'
+ - Note, it seems this may only be in engineering samples. */
+ if ((c->x86==6) && (c->x86_model==9) && (c->x86_mask==1) && (size==65))
+ size -=1;
+
return size;
}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/kernel/cpu/cpufreq/Makefile linux-2.5/arch/i386/kernel/cpu/cpufreq/Makefile
--- linux-2.5.60/arch/i386/kernel/cpu/cpufreq/Makefile 2003-02-10 17:38:29.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/cpufreq/Makefile 2003-02-10 22:48:41.000000000 -0100
@@ -1,14 +1,9 @@
obj-$(CONFIG_X86_POWERNOW_K6) += powernow-k6.o
+obj-$(CONFIG_X86_POWERNOW_K7) += powernow-k7.o
obj-$(CONFIG_X86_LONGHAUL) += longhaul.o
obj-$(CONFIG_X86_SPEEDSTEP) += speedstep.o
obj-$(CONFIG_X86_P4_CLOCKMOD) += p4-clockmod.o
obj-$(CONFIG_ELAN_CPUFREQ) += elanfreq.o
obj-$(CONFIG_X86_LONGRUN) += longrun.o
obj-$(CONFIG_X86_GX_SUSPMOD) += gx-suspmod.o
-obj-$(CONFIG_X86_ACPI_CPUFREQ) += acpi.o
-ifdef CONFIG_X86_ACPI_CPUFREQ
- ifdef CONFIG_ACPI_DEBUG
- EXTRA_CFLAGS += -DACPI_DEBUG_OUTPUT
- endif
-endif
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/kernel/cpu/cpufreq/elanfreq.c linux-2.5/arch/i386/kernel/cpu/cpufreq/elanfreq.c
--- linux-2.5.60/arch/i386/kernel/cpu/cpufreq/elanfreq.c 2003-02-10 17:38:27.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/cpufreq/elanfreq.c 2003-02-10 22:48:41.000000000 -0100
@@ -31,15 +31,11 @@
#define REG_CSCIR 0x22 /* Chip Setup and Control Index Register */
#define REG_CSCDR 0x23 /* Chip Setup and Control Data Register */
-static struct cpufreq_driver *elanfreq_driver;
+static struct cpufreq_driver elanfreq_driver;
/* Module parameter */
static int max_freq;
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Robert Schwebel , Sven Geggus ");
-MODULE_DESCRIPTION("cpufreq driver for AMD's Elan CPUs");
-
struct s_elan_multiplier {
int clock; /* frequency in kHz */
int val40h; /* PMU Force Mode register */
@@ -127,11 +123,6 @@ static void elanfreq_set_cpu_state (unsi
struct cpufreq_freqs freqs;
- if (!elanfreq_driver) {
- printk(KERN_ERR "cpufreq: initialization problem or invalid target frequency\n");
- return;
- }
-
freqs.old = elanfreq_get_cpu_frequency();
freqs.new = elan_multiplier[state].clock;
freqs.cpu = 0; /* elanfreq.c is UP only driver */
@@ -187,11 +178,13 @@ static int elanfreq_verify (struct cpufr
return cpufreq_frequency_table_verify(policy, &elanfreq_table[0]);
}
-static int elanfreq_setpolicy (struct cpufreq_policy *policy)
+static int elanfreq_target (struct cpufreq_policy *policy,
+ unsigned int target_freq,
+ unsigned int relation)
{
unsigned int newstate = 0;
- if (cpufreq_frequency_table_setpolicy(policy, &elanfreq_table[0], &newstate))
+ if (cpufreq_frequency_table_target(policy, &elanfreq_table[0], target_freq, relation, &newstate))
return -EINVAL;
elanfreq_set_cpu_state(newstate);
@@ -204,6 +197,37 @@ static int elanfreq_setpolicy (struct cp
* Module init and exit code
*/
+static int elanfreq_cpu_init(struct cpufreq_policy *policy)
+{
+ struct cpuinfo_x86 *c = cpu_data;
+ unsigned int i;
+
+ /* capability check */
+ if ((c->x86_vendor != X86_VENDOR_AMD) ||
+ (c->x86 != 4) || (c->x86_model!=10))
+ return -ENODEV;
+
+ /* max freq */
+ if (!max_freq)
+ max_freq = elanfreq_get_cpu_frequency();
+
+ /* table init */
+ for (i=0; (elanfreq_table[i].frequency != CPUFREQ_TABLE_END); i++) {
+ if (elanfreq_table[i].frequency > max_freq)
+ elanfreq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
+ }
+
+ /* cpuinfo and default policy values */
+ policy->policy = CPUFREQ_POLICY_PERFORMANCE;
+ policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
+#ifdef CONFIG_CPU_FREQ_24_API
+ elanfreq_driver.cpu_cur_freq[policy->cpu] = elanfreq_get_cpu_frequency();
+#endif
+
+ return cpufreq_frequency_table_cpuinfo(policy, &elanfreq_table[0]);;
+}
+
+
#ifndef MODULE
/**
* elanfreq_setup - elanfreq command line parameter parsing
@@ -227,8 +251,6 @@ __setup("elanfreq=", elanfreq_setup);
static int __init elanfreq_init(void)
{
struct cpuinfo_x86 *c = cpu_data;
- struct cpufreq_driver *driver;
- int ret, i;
/* Test if we have the right hardware */
if ((c->x86_vendor != X86_VENDOR_AMD) ||
@@ -238,63 +260,32 @@ static int __init elanfreq_init(void)
return -ENODEV;
}
- driver = kmalloc(sizeof(struct cpufreq_driver) +
- NR_CPUS * sizeof(struct cpufreq_policy), GFP_KERNEL);
- if (!driver)
- return -ENOMEM;
-
- driver->policy = (struct cpufreq_policy *) (driver + 1);
-
- if (!max_freq)
- max_freq = elanfreq_get_cpu_frequency();
-
- /* table init */
- for (i=0; (elanfreq_table[i].frequency != CPUFREQ_TABLE_END); i++) {
- if (elanfreq_table[i].frequency > max_freq)
- elanfreq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
- }
+ return cpufreq_register_driver(&elanfreq_driver);
+}
-#ifdef CONFIG_CPU_FREQ_24_API
- driver->cpu_cur_freq[0] = elanfreq_get_cpu_frequency();
-#endif
- driver->verify = &elanfreq_verify;
- driver->setpolicy = &elanfreq_setpolicy;
- driver->init = NULL;
- driver->exit = NULL;
- strncpy(driver->name, "elanfreq", CPUFREQ_NAME_LEN);
-
- driver->policy[0].cpu = 0;
- ret = cpufreq_frequency_table_cpuinfo(&driver->policy[0], &elanfreq_table[0]);
- if (ret) {
- kfree(driver);
- return ret;
- }
- driver->policy[0].policy = CPUFREQ_POLICY_PERFORMANCE;
- driver->policy[0].cpuinfo.transition_latency = CPUFREQ_ETERNAL;
+static void __exit elanfreq_exit(void)
+{
+ cpufreq_unregister_driver(&elanfreq_driver);
+}
- elanfreq_driver = driver;
- ret = cpufreq_register(driver);
- if (ret) {
- elanfreq_driver = NULL;
- kfree(driver);
- }
+static struct cpufreq_driver elanfreq_driver = {
+ .verify = elanfreq_verify,
+ .target = elanfreq_target,
+ .init = elanfreq_cpu_init,
+ .exit = NULL,
+ .policy = NULL,
+ .name = "elanfreq",
+};
- return ret;
-}
+MODULE_PARM (max_freq, "i");
-static void __exit elanfreq_exit(void)
-{
- if (elanfreq_driver) {
- cpufreq_unregister();
- kfree(elanfreq_driver);
- }
-}
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Robert Schwebel , Sven Geggus ");
+MODULE_DESCRIPTION("cpufreq driver for AMD's Elan CPUs");
module_init(elanfreq_init);
module_exit(elanfreq_exit);
-MODULE_PARM (max_freq, "i");
-
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/kernel/cpu/cpufreq/longhaul.c linux-2.5/arch/i386/kernel/cpu/cpufreq/longhaul.c
--- linux-2.5.60/arch/i386/kernel/cpu/cpufreq/longhaul.c 2003-02-10 17:37:57.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/cpufreq/longhaul.c 2003-02-10 22:48:41.000000000 -0100
@@ -1,5 +1,5 @@
/*
- * $Id: longhaul.c,v 1.77 2002/10/31 21:17:40 db Exp $
+ * $Id: longhaul.c,v 1.85 2003/02/10 17:31:50 db Exp $
*
* (C) 2001 Dave Jones.
* (C) 2002 Padraig Brady.
@@ -48,6 +48,7 @@ static int vrmrev;
/* Module parameters */
+static int prefer_slow_fsb;
static int dont_scale_voltage;
static int dont_scale_fsb;
static int current_fsb;
@@ -237,7 +238,6 @@ static unsigned int power_fsb_table[] =
/* fsb values to favour high fsb speed (for e.g. if lowering CPU
freq because of heat, but want to maintain highest performance possible) */
static unsigned int perf_fsb_table[] = { 133, 100, 66, -1 };
-static unsigned int *fsb_search_table;
/* Voltage scales. Div by 1000 to get actual voltage. */
static int __initdata vrm85scales[32] = {
@@ -260,7 +260,7 @@ static int eblcr_table[32];
static int voltage_table[32];
static int highest_speed, lowest_speed; /* kHz */
static int longhaul; /* version. */
-static struct cpufreq_driver *longhaul_driver;
+static struct cpufreq_frequency_table *longhaul_table;
static int longhaul_get_cpu_fsb (void)
@@ -428,7 +428,7 @@ bad_voltage:
}
-static void __init longhaul_get_ranges (void)
+static int __init longhaul_get_ranges (void)
{
unsigned long lo, hi, invalue;
unsigned int minmult=0, maxmult=0, minfsb=0, maxfsb=0;
@@ -436,6 +436,9 @@ static void __init longhaul_get_ranges (
50,30,40,100,55,35,45,95,90,70,80,60,120,75,85,65,
-1,110,120,-1,135,115,125,105,130,150,160,140,-1,155,-1,145 };
unsigned int fsb_table[4] = { 133, 100, -1, 66 };
+ unsigned int fsbcount = 1;
+ unsigned int i, j, k = 0;
+ static unsigned int *fsb_search_table;
switch (longhaul) {
case 1:
@@ -472,6 +475,11 @@ static void __init longhaul_get_ranges (
dprintk (KERN_INFO "longhaul: Min FSB=%d Max FSB=%d\n",
minfsb, maxfsb);
+ fsbcount = 0;
+ for (i=0;i<4;i++) {
+ if((fsb_table[i] >= minfsb) && (fsb_table[i] <= maxfsb))
+ fsbcount++;
+ }
} else {
minfsb = maxfsb = current_fsb;
}
@@ -480,11 +488,37 @@ static void __init longhaul_get_ranges (
highest_speed = maxmult * maxfsb * 100;
lowest_speed = minmult * minfsb * 100;
-
dprintk (KERN_INFO "longhaul: MinMult(x10)=%d MaxMult(x10)=%d\n",
- minmult, maxmult);
+ minmult, maxmult);
dprintk (KERN_INFO "longhaul: Lowestspeed=%d Highestspeed=%d\n",
- lowest_speed, highest_speed);
+ lowest_speed, highest_speed);
+
+ longhaul_table = kmalloc((numscales * fsbcount + 1) * sizeof(struct cpufreq_frequency_table), GFP_KERNEL);
+ if(!longhaul_table)
+ return -ENOMEM;
+
+ if (prefer_slow_fsb)
+ fsb_search_table = perf_fsb_table; // yep, this is right: the last entry is preferred by cpufreq_frequency_table_* ...
+ else
+ fsb_search_table = power_fsb_table;
+
+ for (i=0; (i<4); i++) {
+ if ((fsb_search_table[i] > maxfsb) || (fsb_search_table[i] < minfsb) || (fsb_search_table[i] == -1))
+ continue;
+ for (j=0; (j maxmult) || (clock_ratio[j] < minmult) || (clock_ratio[j] == -1))
+ continue;
+ longhaul_table[k].frequency= clock_ratio[j] * fsb_search_table[i] * 100;
+ longhaul_table[k].index = (j << 8) | (i);
+ k++;
+ }
+ }
+
+ longhaul_table[k].frequency = CPUFREQ_TABLE_END;
+ if (!k)
+ return -EINVAL;
+
+ return 0;
}
@@ -523,182 +557,35 @@ static void __init longhaul_setup_voltag
}
-static inline unsigned int longhaul_statecount_fsb(struct cpufreq_policy *policy, unsigned int fsb) {
- unsigned int i, count = 0;
-
- for(i=0; imax) &&
- ((clock_ratio[i] * fsb * 100) >= policy->min))
- count++;
- }
-
- return count;
-}
-
-
static int longhaul_verify(struct cpufreq_policy *policy)
{
- unsigned int number_states = 0;
- unsigned int i;
- unsigned int fsb_index = 0;
- unsigned int tmpfreq = 0;
- unsigned int newmax = -1;
-
- if (!policy || !longhaul_driver)
- return -EINVAL;
-
- policy->cpu = 0;
- cpufreq_verify_within_limits(policy, lowest_speed, highest_speed);
-
- if (can_scale_fsb==1) {
- for (fsb_index=0; fsb_search_table[fsb_index]!=-1; fsb_index++)
- number_states += longhaul_statecount_fsb(policy, fsb_search_table[fsb_index]);
- } else
- number_states = longhaul_statecount_fsb(policy, current_fsb);
-
- if (number_states)
- return 0;
-
- /* get frequency closest above current policy->max */
- if (can_scale_fsb==1) {
- for (fsb_index=0; fsb_search_table[fsb_index] != -1; fsb_index++)
- for(i=0; i policy->max) &&
- (tmpfreq < newmax))
- newmax = tmpfreq;
- }
- } else {
- for(i=0; i policy->max) &&
- (tmpfreq < newmax))
- newmax = tmpfreq;
- }
- }
-
- policy->max = newmax;
-
- cpufreq_verify_within_limits(policy, lowest_speed, highest_speed);
-
- return 0;
-}
-
-
-static int longhaul_get_best_freq_for_fsb(struct cpufreq_policy *policy,
- unsigned int min_mult,
- unsigned int max_mult,
- unsigned int fsb,
- unsigned int *new_mult)
-{
- unsigned int optimal = 0;
- unsigned int found_optimal = 0;
- unsigned int i;
-
- switch(policy->policy) {
- case CPUFREQ_POLICY_POWERSAVE:
- optimal = max_mult;
- break;
- case CPUFREQ_POLICY_PERFORMANCE:
- optimal = min_mult;
- }
-
- for(i=0; i policy->max) ||
- (freq < policy->min))
- continue;
- switch(policy->policy) {
- case CPUFREQ_POLICY_POWERSAVE:
- if (clock_ratio[i] < clock_ratio[optimal]) {
- found_optimal = 1;
- optimal = i;
- }
- break;
- case CPUFREQ_POLICY_PERFORMANCE:
- if (clock_ratio[i] > clock_ratio[optimal]) {
- found_optimal = 1;
- optimal = i;
- }
- break;
- }
- }
-
- if (found_optimal) {
- *new_mult = optimal;
- return 1;
- }
- return 0;
+ return cpufreq_frequency_table_verify(policy, longhaul_table);
}
-static int longhaul_setpolicy (struct cpufreq_policy *policy)
+static int longhaul_target (struct cpufreq_policy *policy,
+ unsigned int target_freq,
+ unsigned int relation)
{
- unsigned int i;
- unsigned int fsb_index = 0;
- unsigned int new_fsb = 0;
- unsigned int new_clock_ratio = 0;
- unsigned int min_mult = 0;
- unsigned int max_mult = 0;
-
+ unsigned int table_index = 0;
+ unsigned int new_fsb = 0;
+ unsigned int new_clock_ratio = 0;
- if (!longhaul_driver)
+ if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq, relation, &table_index))
return -EINVAL;
- if (policy->policy==CPUFREQ_POLICY_PERFORMANCE)
- fsb_search_table = perf_fsb_table;
- else
- fsb_search_table = power_fsb_table;
-
- for(i=0;i clock_ratio[i])
- min_mult = i;
- }
-
- if (can_scale_fsb==1) {
- unsigned int found = 0;
- for (fsb_index=0; fsb_search_table[fsb_index]!=-1; fsb_index++)
- {
- if (longhaul_get_best_freq_for_fsb(policy,
- min_mult, max_mult,
- fsb_search_table[fsb_index],
- &new_clock_ratio)) {
- new_fsb = fsb_search_table[fsb_index];
- break;
- }
- }
- if (!found)
- return -EINVAL;
- } else {
- new_fsb = current_fsb;
- if (!longhaul_get_best_freq_for_fsb(policy, min_mult,
- max_mult, new_fsb, &new_clock_ratio))
- return -EINVAL;
- }
-
+ new_clock_ratio = longhaul_table[table_index].index & 0xFF;
+ new_fsb = power_fsb_table[(longhaul_table[table_index].index & 0xFF00) >> 8];
+
longhaul_setstate(new_clock_ratio, new_fsb);
return 0;
}
-static int __init longhaul_init (void)
+static int longhaul_cpu_init (struct cpufreq_policy *policy)
{
struct cpuinfo_x86 *c = cpu_data;
- unsigned int currentspeed;
- static int currentmult;
- unsigned long lo, hi;
- int ret;
- struct cpufreq_driver *driver;
if ((c->x86_vendor != X86_VENDOR_CENTAUR) || (c->x86 !=6) )
return -ENODEV;
@@ -733,21 +620,12 @@ static int __init longhaul_init (void)
memcpy (eblcr_table, c5m_eblcr, sizeof(c5m_eblcr));
break;
- default:
- printk (KERN_INFO "longhaul: Unknown VIA CPU. Contact davej@suse.de\n");
- return -ENODEV;
}
printk (KERN_INFO "longhaul: VIA CPU detected. Longhaul version %d supported\n", longhaul);
- current_fsb = longhaul_get_cpu_fsb();
- currentmult = longhaul_get_cpu_mult();
- currentspeed = currentmult * current_fsb * 100;
-
- dprintk (KERN_INFO "longhaul: CPU currently at %dMHz (%d x %d.%d)\n",
- (currentspeed/1000), current_fsb, currentmult/10, currentmult%10);
-
if (longhaul==2 || longhaul==3) {
+ unsigned long lo, hi;
rdmsr (MSR_VIA_LONGHAUL, lo, hi);
if ((lo & (1<<0)) && (dont_scale_voltage==0))
longhaul_setup_voltagescaling (lo, hi);
@@ -756,56 +634,55 @@ static int __init longhaul_init (void)
can_scale_fsb = 1;
}
- longhaul_get_ranges();
-
- driver = kmalloc(sizeof(struct cpufreq_driver) +
- NR_CPUS * sizeof(struct cpufreq_policy), GFP_KERNEL);
- if (!driver)
+ if (longhaul_get_ranges())
return -ENOMEM;
- driver->policy = (struct cpufreq_policy *) (driver + 1);
+ policy->policy = CPUFREQ_POLICY_PERFORMANCE;
+ policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
#ifdef CONFIG_CPU_FREQ_24_API
- driver->cpu_cur_freq[0] = currentspeed;
+ longhaul_driver.cpu_cur_freq[0] = (unsigned int) (longhaul_get_cpu_fsb() * longhaul_get_cpu_mult() * 100);
#endif
- driver->verify = &longhaul_verify;
- driver->setpolicy = &longhaul_setpolicy;
- driver->init = NULL;
- driver->exit = NULL;
- strncpy(driver->name, "longhaul", CPUFREQ_NAME_LEN);
-
- driver->policy[0].cpu = 0;
- driver->policy[0].min = (unsigned int) lowest_speed;
- driver->policy[0].max = (unsigned int) highest_speed;
- driver->policy[0].policy = CPUFREQ_POLICY_PERFORMANCE;
- driver->policy[0].cpuinfo.min_freq = (unsigned int) lowest_speed;
- driver->policy[0].cpuinfo.max_freq = (unsigned int) highest_speed;
- driver->policy[0].cpuinfo.transition_latency = CPUFREQ_ETERNAL;
-
- longhaul_driver = driver;
-
- ret = cpufreq_register(driver);
- if (ret) {
- longhaul_driver = NULL;
- kfree(driver);
+ return cpufreq_frequency_table_cpuinfo(policy, longhaul_table);
+}
+
+static struct cpufreq_driver longhaul_driver = {
+ .verify = longhaul_verify,
+ .target = longhaul_target,
+ .init = longhaul_cpu_init,
+ .name = "longhaul",
+};
+
+static int __init longhaul_init (void)
+{
+ struct cpuinfo_x86 *c = cpu_data;
+
+ if ((c->x86_vendor != X86_VENDOR_CENTAUR) || (c->x86 !=6) )
+ return -ENODEV;
+
+ switch (c->x86_model) {
+ case 6 ... 7:
+ return cpufreq_register_driver(&longhaul_driver);
+ case 8:
+ return -ENODEV;
+ default:
+ printk (KERN_INFO "longhaul: Unknown VIA CPU. Contact davej@suse.de\n");
}
- return ret;
+ return -ENODEV;
}
-
static void __exit longhaul_exit (void)
{
- if (longhaul_driver) {
- cpufreq_unregister();
- kfree(longhaul_driver);
- }
+ cpufreq_unregister_driver(&longhaul_driver);
+ kfree(longhaul_table);
}
MODULE_PARM (dont_scale_fsb, "i");
MODULE_PARM (dont_scale_voltage, "i");
MODULE_PARM (current_fsb, "i");
+MODULE_PARM (prefer_slow_fsb, "i");
MODULE_AUTHOR ("Dave Jones ");
MODULE_DESCRIPTION ("Longhaul driver for VIA Cyrix processors.");
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/kernel/cpu/cpufreq/longrun.c linux-2.5/arch/i386/kernel/cpu/cpufreq/longrun.c
--- linux-2.5.60/arch/i386/kernel/cpu/cpufreq/longrun.c 2003-02-10 17:38:47.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/cpufreq/longrun.c 2003-02-10 22:48:41.000000000 -0100
@@ -1,7 +1,7 @@
/*
- * $Id: longrun.c,v 1.14 2002/10/31 21:17:40 db Exp $
+ * $Id: longrun.c,v 1.22 2003/02/10 17:31:50 db Exp $
*
- * (C) 2002 Dominik Brodowski
+ * (C) 2002 - 2003 Dominik Brodowski
*
* Licensed under the terms of the GNU GPL License version 2.
*
@@ -18,7 +18,7 @@
#include
#include
-static struct cpufreq_driver *longrun_driver;
+static struct cpufreq_driver longrun_driver;
/**
* longrun_{low,high}_freq is needed for the conversion of cpufreq kHz
@@ -39,9 +39,6 @@ static void longrun_get_policy(struct cp
{
u32 msr_lo, msr_hi;
- if (!longrun_driver)
- return;
-
rdmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi);
if (msr_lo & 0x01)
policy->policy = CPUFREQ_POLICY_PERFORMANCE;
@@ -54,7 +51,7 @@ static void longrun_get_policy(struct cp
policy->min = longrun_low_freq + msr_lo *
((longrun_high_freq - longrun_low_freq) / 100);
- policy->min = longrun_low_freq + msr_hi *
+ policy->max = longrun_low_freq + msr_hi *
((longrun_high_freq - longrun_low_freq) / 100);
policy->cpu = 0;
}
@@ -72,7 +69,7 @@ static int longrun_set_policy(struct cpu
u32 msr_lo, msr_hi;
u32 pctg_lo, pctg_hi;
- if (!longrun_driver || !policy)
+ if (!policy)
return -EINVAL;
pctg_lo = (policy->min - longrun_low_freq) /
@@ -117,13 +114,16 @@ static int longrun_set_policy(struct cpu
*/
static int longrun_verify_policy(struct cpufreq_policy *policy)
{
- if (!policy || !longrun_driver)
+ if (!policy)
return -EINVAL;
policy->cpu = 0;
cpufreq_verify_within_limits(policy,
- longrun_driver->policy[0].cpuinfo.min_freq,
- longrun_driver->policy[0].cpuinfo.max_freq);
+ policy->cpuinfo.min_freq,
+ policy->cpuinfo.max_freq);
+
+ if (policy->policy == CPUFREQ_POLICY_GOVERNOR)
+ policy->policy = longrun_driver.policy[0].policy;
return 0;
}
@@ -221,58 +221,51 @@ static unsigned int __init longrun_deter
}
-/**
- * longrun_init - initializes the Transmeta Crusoe LongRun CPUFreq driver
- *
- * Initializes the LongRun support.
- */
-static int __init longrun_init(void)
+static int longrun_cpu_init(struct cpufreq_policy *policy)
{
- int result;
- struct cpufreq_driver *driver;
+ int result = 0;
struct cpuinfo_x86 *c = cpu_data;
+ /* capability check */
+ if (policy->cpu != 0)
+ return -ENODEV;
if (c->x86_vendor != X86_VENDOR_TRANSMETA ||
!cpu_has(c, X86_FEATURE_LONGRUN))
- return 0;
-
- /* initialization of main "cpufreq" code*/
- driver = kmalloc(sizeof(struct cpufreq_driver) +
- NR_CPUS * sizeof(struct cpufreq_policy), GFP_KERNEL);
- if (!driver)
- return -ENOMEM;
-
- driver->policy = (struct cpufreq_policy *) (driver + 1);
-
- if (longrun_determine_freqs(&longrun_low_freq, &longrun_high_freq)) {
- kfree(driver);
- return -EIO;
- }
- driver->policy[0].cpuinfo.min_freq = longrun_low_freq;
- driver->policy[0].cpuinfo.max_freq = longrun_high_freq;
- driver->policy[0].cpuinfo.transition_latency = CPUFREQ_ETERNAL;
- driver->init = NULL;
- driver->exit = NULL;
- strncpy(driver->name, "longrun", CPUFREQ_NAME_LEN);
-
- longrun_get_policy(&driver->policy[0]);
+ return -ENODEV;
+ /* detect low and high frequency */
+ result = longrun_determine_freqs(&longrun_low_freq, &longrun_high_freq);
+ if (result)
+ return result;
+
+ /* cpuinfo and default policy values */
+ policy->cpuinfo.min_freq = longrun_low_freq;
+ policy->cpuinfo.max_freq = longrun_high_freq;
+ policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
+ longrun_get_policy(policy);
+
#ifdef CONFIG_CPU_FREQ_24_API
- driver->cpu_cur_freq[0] = longrun_high_freq; /* dummy value */
+ longrun_driver.cpu_cur_freq[policy->cpu] = longrun_low_freq; /* dummy value */
#endif
- driver->verify = &longrun_verify_policy;
- driver->setpolicy = &longrun_set_policy;
+ return 0;
+}
+
- longrun_driver = driver;
+/**
+ * longrun_init - initializes the Transmeta Crusoe LongRun CPUFreq driver
+ *
+ * Initializes the LongRun support.
+ */
+static int __init longrun_init(void)
+{
+ struct cpuinfo_x86 *c = cpu_data;
- result = cpufreq_register(driver);
- if (result) {
- longrun_driver = NULL;
- kfree(driver);
- }
+ if (c->x86_vendor != X86_VENDOR_TRANSMETA ||
+ !cpu_has(c, X86_FEATURE_LONGRUN))
+ return -ENODEV;
- return result;
+ return cpufreq_register_driver(&longrun_driver);
}
@@ -281,15 +274,23 @@ static int __init longrun_init(void)
*/
static void __exit longrun_exit(void)
{
- if (longrun_driver) {
- cpufreq_unregister();
- kfree(longrun_driver);
- }
+ cpufreq_unregister_driver(&longrun_driver);
}
+static struct cpufreq_driver longrun_driver = {
+ .verify = longrun_verify_policy,
+ .setpolicy = longrun_set_policy,
+ .init = longrun_cpu_init,
+ .exit = NULL,
+ .policy = NULL,
+ .name = "longrun",
+};
+
+
MODULE_AUTHOR ("Dominik Brodowski ");
MODULE_DESCRIPTION ("LongRun driver for Transmeta Crusoe processors.");
MODULE_LICENSE ("GPL");
+
module_init(longrun_init);
module_exit(longrun_exit);
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/kernel/cpu/cpufreq/p4-clockmod.c linux-2.5/arch/i386/kernel/cpu/cpufreq/p4-clockmod.c
--- linux-2.5.60/arch/i386/kernel/cpu/cpufreq/p4-clockmod.c 2003-02-10 17:38:53.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/cpufreq/p4-clockmod.c 2003-02-10 22:48:41.000000000 -0100
@@ -1,5 +1,6 @@
/*
* Pentium 4/Xeon CPU on demand clock modulation/speed scaling
+ * (C) 2002 - 2003 Dominik Brodowski
* (C) 2002 Zwane Mwaikambo
* (C) 2002 Arjan van de Ven
* (C) 2002 Tora T. Engstad
@@ -45,11 +46,10 @@ enum {
#define DC_ENTRIES 8
-static int has_N44_O17_errata;
+static int has_N44_O17_errata[NR_CPUS];
static int stock_freq;
-MODULE_PARM(stock_freq, "i");
-static struct cpufreq_driver *cpufreq_p4_driver;
+static struct cpufreq_driver p4clockmod_driver;
static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate)
@@ -107,17 +107,17 @@ static int cpufreq_p4_setdc(unsigned int
rdmsr(MSR_IA32_THERM_STATUS, l, h);
if (l & 0x01)
- printk(KERN_DEBUG PFX "CPU#%d currently thermal throttled\n", cpu);
+// printk(KERN_DEBUG PFX "CPU#%d currently thermal throttled\n", cpu);
- if (has_N44_O17_errata && (newstate == DC_25PT || newstate == DC_DFLT))
+ if (has_N44_O17_errata[cpu] && (newstate == DC_25PT || newstate == DC_DFLT))
newstate = DC_38PT;
rdmsr(MSR_IA32_THERM_CONTROL, l, h);
if (newstate == DC_DISABLE) {
- printk(KERN_INFO PFX "CPU#%d disabling modulation\n", cpu);
+// printk(KERN_INFO PFX "CPU#%d disabling modulation\n", cpu);
wrmsr(MSR_IA32_THERM_CONTROL, l & ~(1<<4), h);
} else {
- printk(KERN_INFO PFX "CPU#%d setting duty cycle to %d%%\n", cpu, ((125 * newstate) / 10));
+// printk(KERN_INFO PFX "CPU#%d setting duty cycle to %d%%\n", cpu, ((125 * newstate) / 10));
/* bits 63 - 5 : reserved
* bit 4 : enable/disable
* bits 3-1 : duty cycle
@@ -155,14 +155,16 @@ static struct cpufreq_frequency_table p4
};
-static int cpufreq_p4_setpolicy(struct cpufreq_policy *policy)
+static int cpufreq_p4_target(struct cpufreq_policy *policy,
+ unsigned int target_freq,
+ unsigned int relation)
{
unsigned int newstate = DC_RESV;
- if (cpufreq_frequency_table_setpolicy(policy, &p4clockmod_table[0], &newstate))
+ if (cpufreq_frequency_table_target(policy, &p4clockmod_table[0], target_freq, relation, &newstate))
return -EINVAL;
- cpufreq_p4_setdc(policy->cpu, newstate);
+ cpufreq_p4_setdc(policy->cpu, p4clockmod_table[newstate].index);
return 0;
}
@@ -174,39 +176,30 @@ static int cpufreq_p4_verify(struct cpuf
}
-static int __init cpufreq_p4_init(void)
-{
- struct cpuinfo_x86 *c = cpu_data;
- int cpuid;
- int ret;
- struct cpufreq_driver *driver;
+static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy)
+{
+ struct cpuinfo_x86 *c = &cpu_data[policy->cpu];
+ int cpuid = 0;
unsigned int i;
- /*
- * THERM_CONTROL is architectural for IA32 now, so
- * we can rely on the capability checks
- */
+ /* capability check */
if (c->x86_vendor != X86_VENDOR_INTEL)
return -ENODEV;
-
if (!test_bit(X86_FEATURE_ACPI, c->x86_capability) ||
- !test_bit(X86_FEATURE_ACC, c->x86_capability))
+ !test_bit(X86_FEATURE_ACC, c->x86_capability))
return -ENODEV;
-
- /* Errata workarounds */
+
+ /* Errata workaround */
cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_mask;
switch (cpuid) {
- case 0x0f07:
- case 0x0f0a:
- case 0x0f11:
- case 0x0f12:
- has_N44_O17_errata = 1;
- default:
- break;
+ case 0x0f07:
+ case 0x0f0a:
+ case 0x0f11:
+ case 0x0f12:
+ has_N44_O17_errata[policy->cpu] = 1;
}
-
- printk(KERN_INFO PFX "P4/Xeon(TM) CPU On-Demand Clock Modulation available\n");
-
+
+ /* get frequency */
if (!stock_freq) {
if (cpu_khz)
stock_freq = cpu_khz;
@@ -216,71 +209,71 @@ static int __init cpufreq_p4_init(void)
}
}
- driver = kmalloc(sizeof(struct cpufreq_driver) +
- NR_CPUS * sizeof(struct cpufreq_policy), GFP_KERNEL);
- if (!driver)
- return -ENOMEM;
-
- driver->policy = (struct cpufreq_policy *) (driver + 1);
-
/* table init */
for (i=1; (p4clockmod_table[i].frequency != CPUFREQ_TABLE_END); i++) {
- if ((i<2) && (has_N44_O17_errata))
+ if ((i<2) && (has_N44_O17_errata[policy->cpu]))
p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID;
else
p4clockmod_table[i].frequency = (stock_freq * i)/8;
}
-
+ /* cpuinfo and default policy values */
+ policy->policy = CPUFREQ_POLICY_PERFORMANCE;
+ policy->cpuinfo.transition_latency = 1000;
#ifdef CONFIG_CPU_FREQ_24_API
- for (i=0;icpu_cur_freq[i] = stock_freq;
- }
+ p4clockmod_driver.cpu_cur_freq[policy->cpu] = stock_freq;
#endif
- driver->verify = &cpufreq_p4_verify;
- driver->setpolicy = &cpufreq_p4_setpolicy;
- driver->init = NULL;
- driver->exit = NULL;
- strncpy(driver->name, "p4-clockmod", CPUFREQ_NAME_LEN);
-
- for (i=0;ipolicy[i].cpu = i;
- ret = cpufreq_frequency_table_cpuinfo(&driver->policy[i], &p4clockmod_table[0]);
- if (ret) {
- kfree(driver);
- return ret;
- }
- driver->policy[i].policy = CPUFREQ_POLICY_PERFORMANCE;
- driver->policy[i].cpuinfo.transition_latency = CPUFREQ_ETERNAL;
- }
+ return cpufreq_frequency_table_cpuinfo(policy, &p4clockmod_table[0]);
+}
- cpufreq_p4_driver = driver;
-
- ret = cpufreq_register(driver);
- if (ret) {
- cpufreq_p4_driver = NULL;
- kfree(driver);
- }
- return ret;
+static int cpufreq_p4_cpu_exit(struct cpufreq_policy *policy)
+{
+ return cpufreq_p4_setdc(policy->cpu, DC_DISABLE);
+}
+
+
+static int __init cpufreq_p4_init(void)
+{
+ struct cpuinfo_x86 *c = cpu_data;
+
+ /*
+ * THERM_CONTROL is architectural for IA32 now, so
+ * we can rely on the capability checks
+ */
+ if (c->x86_vendor != X86_VENDOR_INTEL)
+ return -ENODEV;
+
+ if (!test_bit(X86_FEATURE_ACPI, c->x86_capability) ||
+ !test_bit(X86_FEATURE_ACC, c->x86_capability))
+ return -ENODEV;
+
+ printk(KERN_INFO PFX "P4/Xeon(TM) CPU On-Demand Clock Modulation available\n");
+
+ return cpufreq_register_driver(&p4clockmod_driver);
}
static void __exit cpufreq_p4_exit(void)
{
- unsigned int i;
-
- if (cpufreq_p4_driver) {
- for (i=0; i");
MODULE_DESCRIPTION ("cpufreq driver for Pentium(TM) 4/Xeon(TM)");
MODULE_LICENSE ("GPL");
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/kernel/cpu/cpufreq/powernow-k6.c linux-2.5/arch/i386/kernel/cpu/cpufreq/powernow-k6.c
--- linux-2.5.60/arch/i386/kernel/cpu/cpufreq/powernow-k6.c 2003-02-10 17:37:59.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/cpufreq/powernow-k6.c 2003-02-10 22:48:41.000000000 -0100
@@ -1,9 +1,9 @@
/*
- * $Id: powernow-k6.c,v 1.36 2002/10/31 21:17:40 db Exp $
+ * $Id: powernow-k6.c,v 1.46 2003/01/20 17:31:47 db Exp $
* This file was part of Powertweak Linux (http://powertweak.sf.net)
* and is shared with the Linux Kernel module.
*
- * (C) 2000-2002 Dave Jones, Arjan van de Ven, Janne Pänkälä, Dominik Brodowski.
+ * (C) 2000-2003 Dave Jones, Arjan van de Ven, Janne Pänkälä, Dominik Brodowski.
*
* Licensed under the terms of the GNU GPL License version 2.
*
@@ -25,7 +25,7 @@
#define POWERNOW_IOPORT 0xfff0 /* it doesn't matter where, as long
as it is unused */
-static struct cpufreq_driver *powernow_driver;
+static struct cpufreq_driver powernow_k6_driver;
static unsigned int busfreq; /* FSB, in 10 kHz */
static unsigned int max_multiplier;
@@ -77,8 +77,8 @@ static void powernow_k6_set_state (unsig
unsigned long msrval;
struct cpufreq_freqs freqs;
- if (!powernow_driver) {
- printk(KERN_ERR "cpufreq: initialization problem or invalid target frequency\n");
+ if (clock_ratio[best_i].index > max_multiplier) {
+ printk(KERN_ERR "cpufreq: invalid target frequency\n");
return;
}
@@ -126,11 +126,13 @@ static int powernow_k6_verify(struct cpu
*
* sets a new CPUFreq policy
*/
-static int powernow_k6_setpolicy (struct cpufreq_policy *policy)
+static int powernow_k6_target (struct cpufreq_policy *policy,
+ unsigned int target_freq,
+ unsigned int relation)
{
unsigned int newstate = 0;
- if (cpufreq_frequency_table_setpolicy(policy, &clock_ratio[0], &newstate))
+ if (cpufreq_frequency_table_target(policy, &clock_ratio[0], target_freq, relation, &newstate))
return -EINVAL;
powernow_k6_set_state(newstate);
@@ -139,41 +141,22 @@ static int powernow_k6_setpolicy (struct
}
-/**
- * powernow_k6_init - initializes the k6 PowerNow! CPUFreq driver
- *
- * Initializes the K6 PowerNow! support. Returns -ENODEV on unsupported
- * devices, -EINVAL or -ENOMEM on problems during initiatization, and zero
- * on success.
- */
-static int __init powernow_k6_init(void)
-{
- struct cpuinfo_x86 *c = cpu_data;
- struct cpufreq_driver *driver;
- unsigned int result;
- unsigned int i;
+static int powernow_k6_cpu_init(struct cpufreq_policy *policy)
+{
+ struct cpuinfo_x86 *c = cpu_data;
+ unsigned int i;
+ /* capability check */
if ((c->x86_vendor != X86_VENDOR_AMD) || (c->x86 != 5) ||
- ((c->x86_model != 12) && (c->x86_model != 13)))
+ ((c->x86_model != 12) && (c->x86_model != 13)))
+ return -ENODEV;
+ if (policy->cpu != 0)
return -ENODEV;
+ /* get frequencies */
max_multiplier = powernow_k6_get_cpu_multiplier();
busfreq = cpu_khz / max_multiplier;
- if (!request_region(POWERNOW_IOPORT, 16, "PowerNow!")) {
- printk("cpufreq: PowerNow IOPORT region already used.\n");
- return -EIO;
- }
-
- /* initialization of main "cpufreq" code*/
- driver = kmalloc(sizeof(struct cpufreq_driver) +
- NR_CPUS * sizeof(struct cpufreq_policy), GFP_KERNEL);
- if (!driver) {
- release_region (POWERNOW_IOPORT, 16);
- return -ENOMEM;
- }
- driver->policy = (struct cpufreq_policy *) (driver + 1);
-
/* table init */
for (i=0; (clock_ratio[i].frequency != CPUFREQ_TABLE_END); i++) {
if (clock_ratio[i].index > max_multiplier)
@@ -182,35 +165,52 @@ static int __init powernow_k6_init(void)
clock_ratio[i].frequency = busfreq * clock_ratio[i].index;
}
- driver->verify = &powernow_k6_verify;
- driver->setpolicy = &powernow_k6_setpolicy;
- driver->init = NULL;
- driver->exit = NULL;
- strncpy(driver->name, "powernow-k6", CPUFREQ_NAME_LEN);
-
/* cpuinfo and default policy values */
- driver->policy[0].cpu = 0;
- driver->policy[0].cpuinfo.transition_latency = CPUFREQ_ETERNAL;
- driver->policy[0].policy = CPUFREQ_POLICY_PERFORMANCE;
+ policy->policy = CPUFREQ_POLICY_PERFORMANCE;
+ policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
#ifdef CONFIG_CPU_FREQ_24_API
- driver->cpu_cur_freq[0] = busfreq * max_multiplier;
+ powernow_k6_driver.cpu_cur_freq[policy->cpu] = busfreq * max_multiplier;
#endif
- result = cpufreq_frequency_table_cpuinfo(&driver->policy[0], &clock_ratio[0]);
- if (result) {
- kfree(driver);
- return result;
+
+ return cpufreq_frequency_table_cpuinfo(policy, &clock_ratio[0]);
+}
+
+static int powernow_k6_cpu_exit(struct cpufreq_policy *policy)
+{
+ unsigned int i;
+ for (i=0; i<8; i++) {
+ if (i==max_multiplier)
+ powernow_k6_set_state(i);
}
+ return 0;
+}
- powernow_driver = driver;
+/**
+ * powernow_k6_init - initializes the k6 PowerNow! CPUFreq driver
+ *
+ * Initializes the K6 PowerNow! support. Returns -ENODEV on unsupported
+ * devices, -EINVAL or -ENOMEM on problems during initiatization, and zero
+ * on success.
+ */
+static int __init powernow_k6_init(void)
+{
+ struct cpuinfo_x86 *c = cpu_data;
+
+ if ((c->x86_vendor != X86_VENDOR_AMD) || (c->x86 != 5) ||
+ ((c->x86_model != 12) && (c->x86_model != 13)))
+ return -ENODEV;
- result = cpufreq_register(driver);
- if (result) {
+ if (!request_region(POWERNOW_IOPORT, 16, "PowerNow!")) {
+ printk("cpufreq: PowerNow IOPORT region already used.\n");
+ return -EIO;
+ }
+
+ if (cpufreq_register_driver(&powernow_k6_driver)) {
release_region (POWERNOW_IOPORT, 16);
- powernow_driver = NULL;
- kfree(driver);
+ return -EINVAL;
}
- return result;
+ return 0;
}
@@ -221,20 +221,24 @@ static int __init powernow_k6_init(void)
*/
static void __exit powernow_k6_exit(void)
{
- unsigned int i;
-
- if (powernow_driver) {
- for (i=0;i<8;i++)
- if (clock_ratio[i].index == max_multiplier)
- powernow_k6_set_state(i);
- cpufreq_unregister();
- kfree(powernow_driver);
- }
+ cpufreq_unregister_driver(&powernow_k6_driver);
+ release_region (POWERNOW_IOPORT, 16);
}
+static struct cpufreq_driver powernow_k6_driver = {
+ .verify = powernow_k6_verify,
+ .target = powernow_k6_target,
+ .init = powernow_k6_cpu_init,
+ .exit = powernow_k6_cpu_exit,
+ .policy = NULL,
+ .name = "powernow-k6",
+};
+
+
MODULE_AUTHOR ("Arjan van de Ven , Dave Jones , Dominik Brodowski ");
MODULE_DESCRIPTION ("PowerNow! driver for AMD K6-2+ / K6-3+ processors.");
MODULE_LICENSE ("GPL");
+
module_init(powernow_k6_init);
module_exit(powernow_k6_exit);
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/kernel/cpu/cpufreq/powernow-k7.c linux-2.5/arch/i386/kernel/cpu/cpufreq/powernow-k7.c
--- linux-2.5.60/arch/i386/kernel/cpu/cpufreq/powernow-k7.c 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/cpufreq/powernow-k7.c 2003-02-11 10:34:32.000000000 -0100
@@ -0,0 +1,390 @@
+/*
+ * $Id: powernow-k7.c,v 1.25 2003/02/10 22:38:28 davej Exp $
+ *
+ * (C) 2003 Dave Jones
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ * Based upon datasheets & sample CPUs kindly provided by AMD.
+ *
+ * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include "powernow-k7.h"
+
+#define DEBUG
+
+#ifdef DEBUG
+#define dprintk(msg...) printk(msg)
+#else
+#define dprintk(msg...) do { } while(0);
+#endif
+
+struct psb_s {
+ u8 signature[10];
+ u8 tableversion;
+ u8 flags;
+ u16 settlingtime;
+ u8 reserved1;
+ u8 numpst;
+};
+
+struct pst_s {
+ u32 cpuid;
+ u8 fsbspeed;
+ u8 maxfid;
+ u8 startvid;
+ u8 numpstates;
+};
+
+
+/* divide by 1000 to get VID. */
+static int mobile_vid_table[32] = {
+ 2000, 1950, 1900, 1850, 1800, 1750, 1700, 1650,
+ 1600, 1550, 1500, 1450, 1400, 1350, 1300, 0,
+ 1275, 1250, 1225, 1200, 1175, 1150, 1125, 1100,
+ 1075, 1050, 1024, 1000, 975, 950, 925, 0,
+};
+
+/* divide by 10 to get FID. */
+static int fid_codes[32] = {
+ 110, 115, 120, 125, 50, 55, 60, 65,
+ 70, 75, 80, 85, 90, 95, 10, 105,
+ 30, 190, 40, 200, 130, 135, 140, 210,
+ 150, 225, 160, 165, 170, 180, -1, -1,
+};
+
+static struct cpufreq_driver powernow_driver;
+
+static struct cpufreq_frequency_table *powernow_table;
+
+static unsigned int can_scale_bus;
+static unsigned int can_scale_vid;
+static unsigned int minimum_speed=-1;
+static unsigned int maximum_speed;
+static unsigned int number_scales;
+static unsigned int fsb;
+static unsigned int latency;
+
+
+#ifndef rdmsrl
+#define rdmsrl(msr,val) do {unsigned long l__,h__; \
+ rdmsr (msr, l__, h__); \
+ val = l__; \
+ val |= ((u64)h__<<32); \
+} while(0);
+#endif
+
+#ifndef wrmsrl
+static void wrmsrl (u32 msr, u64 val)
+{
+ u32 lo, hi;
+
+ lo = (u32) val;
+ hi = val >> 32;
+ wrmsr (msr, lo, hi);
+}
+#endif
+
+
+
+static int check_powernow(void)
+{
+ struct cpuinfo_x86 *c = cpu_data;
+ unsigned int maxei, eax, ebx, ecx, edx;
+
+ if (c->x86_vendor != X86_VENDOR_AMD) {
+ printk (KERN_INFO "powernow: AMD processor not detected.\n");
+ return 0;
+ }
+
+ if (c->x86 !=6) {
+ printk (KERN_INFO "powernow: This module only works with AMD K7 CPUs\n");
+ return 0;
+ }
+
+ printk (KERN_INFO "powernow: AMD K7 CPU detected.\n");
+
+ /* Get maximum capabilities */
+ maxei = cpuid_eax (0x80000000);
+ if (maxei < 0x80000007) { /* Any powernow info ? */
+ printk (KERN_INFO "powernow: No powernow capabilities detected\n");
+ return 0;
+ }
+
+ cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
+ printk (KERN_INFO "powernow: PowerNOW! Technology present. Can scale: ");
+
+ if (edx & 1 << 1) {
+ printk ("frequency");
+ can_scale_bus=1;
+ }
+
+ if ((edx & (1 << 1 | 1 << 2)) == 0x6)
+ printk (" and ");
+
+ if (edx & 1 << 2) {
+ printk ("voltage");
+ can_scale_vid=1;
+ }
+
+ if (!(edx & (1 << 1 | 1 << 2))) {
+ printk (" nothing.\n");
+ return 0;
+ }
+
+ printk (".\n");
+ return 1;
+}
+
+
+static int get_ranges (unsigned char *pst)
+{
+ int j;
+ u8 fid, vid;
+ unsigned int speed;
+
+ powernow_table = kmalloc((sizeof(struct cpufreq_frequency_table) * (number_scales + 1)), GFP_KERNEL);
+ if (!powernow_table)
+ return -ENOMEM;
+ memset(powernow_table, 0, (sizeof(struct cpufreq_frequency_table) * (number_scales + 1)));
+
+ for (j=0 ; j < number_scales; j++) {
+ fid = *pst++;
+
+ powernow_table[j].frequency = fsb * fid_codes[fid] * 100;
+ powernow_table[j].index = fid; /* lower 8 bits */
+
+ speed = fsb * (fid_codes[fid]/10);
+ if ((fid_codes[fid] % 10)==5) {
+ speed += fsb/2;
+#if defined(CONFIG_ACPI_PROCESSOR) || defined(CONFIG_ACPI_PROCESSOR_MODULE)
+ /* TBD: might be fixed in new revisions of the processors */
+ powernow_table[j].frequency = CPUFREQ_ENTRY_INVALID;
+#endif
+ }
+
+ dprintk (KERN_INFO "powernow: FID: 0x%x (%d.%dx [%dMHz])\t", fid,
+ fid_codes[fid] / 10, fid_codes[fid] % 10, speed);
+
+ if (speed < minimum_speed)
+ minimum_speed = speed;
+ if (speed > maximum_speed)
+ maximum_speed = speed;
+
+ vid = *pst++;
+ powernow_table[j].index |= (vid << 8); /* upper 8 bits */
+ dprintk ("VID: 0x%x (%d.%dV)\n", vid, mobile_vid_table[vid]/1000,
+ mobile_vid_table[vid]%1000);
+ }
+ dprintk ("\n");
+
+ powernow_table[number_scales].frequency = CPUFREQ_TABLE_END;
+ powernow_table[number_scales].index = 0;
+
+ return 0;
+}
+
+
+static void change_speed (unsigned int index)
+{
+ u8 fid, vid;
+ struct cpufreq_freqs freqs;
+ union msr_fidvidstatus fidvidstatus;
+ union msr_fidvidctl fidvidctl;
+
+
+ /* fid are the lower 8 bits of the index we stored into
+ * the cpufreq frequency table in powernow_decode_bios,
+ * vid are the upper 8 bits.
+ */
+
+ fid = powernow_table[index].index & 0xFF;
+ vid = (powernow_table[index].index & 0xFF00) >> 8;
+
+ freqs.cpu = 0;
+
+ rdmsrl (MSR_K7_FID_VID_STATUS, fidvidstatus.val);
+ freqs.old = fsb * fid_codes[fidvidstatus.bits.CFID] * 100;
+
+ freqs.new = powernow_table[index].frequency;
+
+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+ /* Now do the magic poking into the MSRs. */
+
+ rdmsrl (MSR_K7_FID_VID_CTL, fidvidctl.val);
+ fidvidctl.bits.SGTC = latency; /* Stop grant timeout counter */
+ fidvidctl.bits.FID = fid;
+ fidvidctl.bits.VID = vid;
+ /* Note, we could set these lazily. Ie, only do voltage transition
+ if its changed since last time (Some speeds have the same voltage) */
+ fidvidctl.bits.FIDC = 1;
+ fidvidctl.bits.VIDC = 1;
+ wrmsrl (MSR_K7_FID_VID_CTL, fidvidctl.val);
+
+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+}
+
+
+int powernow_decode_bios (int maxfid, int startvid)
+{
+ struct psb_s *psb;
+ struct pst_s *pst;
+ struct cpuinfo_x86 *c = cpu_data;
+ unsigned int i, j;
+ unsigned char *p;
+ unsigned int etuple;
+ unsigned int ret;
+
+ etuple = cpuid_eax(0x80000001);
+ etuple &= 0xf00;
+ etuple |= (c->x86_model<<4)|(c->x86_mask);
+
+ for (i=0xC0000; i < 0xffff0 ; i+=16) {
+
+ p = phys_to_virt(i);
+
+ if (memcmp(p, "AMDK7PNOW!", 10) == 0){
+ dprintk (KERN_INFO "powernow: Found PSB header at %p\n", p);
+ psb = (struct psb_s *) p;
+ dprintk (KERN_INFO "powernow: Table version: 0x%x\n", psb->tableversion);
+ if (psb->tableversion != 0x12) {
+ printk (KERN_INFO "powernow: Sorry, only v1.2 tables supported right now\n");
+ return -ENODEV;
+ }
+
+ dprintk (KERN_INFO "powernow: Flags: 0x%x (", psb->flags);
+ if ((psb->flags & 1)==0) {
+ dprintk ("Mobile");
+ } else {
+ dprintk ("Desktop");
+ }
+ dprintk (" voltage regulator)\n");
+
+ latency = psb->settlingtime;
+ dprintk (KERN_INFO "powernow: Settling Time: %d microseconds.\n", psb->settlingtime);
+ dprintk (KERN_INFO "powernow: Has %d PST tables. (Only dumping ones relevant to this CPU).\n", psb->numpst);
+
+ p += sizeof (struct psb_s);
+
+ pst = (struct pst_s *) p;
+
+ for (i = 0 ; i numpst; i++) {
+ pst = (struct pst_s *) p;
+ number_scales = pst->numpstates;
+
+ if ((etuple == pst->cpuid) && (maxfid==pst->maxfid) && (startvid==pst->startvid))
+ {
+ dprintk (KERN_INFO "powernow: PST:%d (@%p)\n", i, pst);
+ dprintk (KERN_INFO "powernow: cpuid: 0x%x\t", pst->cpuid);
+ dprintk ("fsb: %d\t", pst->fsbspeed);
+ dprintk ("maxFID: 0x%x\t", pst->maxfid);
+ dprintk ("startvid: 0x%x\n", pst->startvid);
+
+ fsb = pst->fsbspeed;
+ ret = get_ranges ((char *) pst + sizeof (struct pst_s));
+ return ret;
+
+ } else {
+ p = (char *) pst + sizeof (struct pst_s);
+ for (j=0 ; j < number_scales; j++)
+ p+=2;
+ }
+ }
+ return -EINVAL;
+ }
+ p++;
+ }
+
+ return -ENODEV;
+}
+
+
+static int powernow_target (struct cpufreq_policy *policy,
+ unsigned int target_freq,
+ unsigned int relation)
+{
+ unsigned int newstate;
+
+ if (cpufreq_frequency_table_target(policy, powernow_table, target_freq, relation, &newstate))
+ return -EINVAL;
+
+ change_speed(newstate);
+
+ return 0;
+}
+
+
+static int powernow_verify (struct cpufreq_policy *policy)
+{
+ return cpufreq_frequency_table_verify(policy, powernow_table);
+}
+
+
+static int __init powernow_cpu_init (struct cpufreq_policy *policy)
+{
+ union msr_fidvidstatus fidvidstatus;
+ int result;
+
+ if (policy->cpu != 0)
+ return -ENODEV;
+
+ rdmsrl (MSR_K7_FID_VID_STATUS, fidvidstatus.val);
+
+ result = powernow_decode_bios(fidvidstatus.bits.MFID, fidvidstatus.bits.SVID);
+ if (result)
+ return result;
+
+ printk (KERN_INFO "powernow: Minimum speed %d MHz. Maximum speed %d MHz.\n",
+ minimum_speed, maximum_speed);
+
+ policy->policy = CPUFREQ_POLICY_PERFORMANCE;
+ policy->cpuinfo.transition_latency = latency;
+#ifdef CONFIG_CPU_FREQ_24_API
+ powernow_driver.cpu_cur_freq[policy->cpu] = maximum_speed;
+#endif
+
+ return cpufreq_frequency_table_cpuinfo(policy, powernow_table);
+}
+
+static int __init powernow_init (void)
+{
+ if (check_powernow()==0)
+ return -ENODEV;
+ return cpufreq_register_driver(&powernow_driver);
+}
+
+
+static void __exit powernow_exit (void)
+{
+ cpufreq_unregister_driver(&powernow_driver);
+ if (powernow_table)
+ kfree(powernow_table);
+}
+
+static struct cpufreq_driver powernow_driver = {
+ .verify = powernow_verify,
+ .target = powernow_target,
+ .init = powernow_cpu_init,
+ .name = "powernow-k7",
+};
+
+
+MODULE_AUTHOR ("Dave Jones ");
+MODULE_DESCRIPTION ("Powernow driver for AMD K7 processors.");
+MODULE_LICENSE ("GPL");
+
+module_init(powernow_init);
+module_exit(powernow_exit);
+
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/kernel/cpu/cpufreq/powernow-k7.h linux-2.5/arch/i386/kernel/cpu/cpufreq/powernow-k7.h
--- linux-2.5.60/arch/i386/kernel/cpu/cpufreq/powernow-k7.h 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/cpufreq/powernow-k7.h 2003-02-11 00:44:30.000000000 -0100
@@ -0,0 +1,52 @@
+/*
+ * $Id: powernow-k7.h,v 1.2 2003/02/10 18:26:01 davej Exp $
+ * (C) 2003 Dave Jones.
+ *
+ * Licensed under the terms of the GNU GPL License version 2.
+ *
+ * AMD-specific information
+ *
+ */
+
+#ifndef MSR_K7_FID_VID_CTL
+#define MSR_K7_FID_VID_CTL 0xc0010041
+#endif
+#ifndef MSR_K7_FID_VID_STATUS
+#define MSR_K7_FID_VID_STATUS 0xc0010042
+#endif
+
+
+union msr_fidvidctl {
+ struct {
+ unsigned FID:5, // 4:0
+ reserved1:3, // 7:5
+ VID:5, // 12:8
+ reserved2:3, // 15:13
+ FIDC:1, // 16
+ VIDC:1, // 17
+ reserved3:2, // 19:18
+ FIDCHGRATIO:1, // 20
+ reserved4:11, // 31-21
+ SGTC:20, // 32:51
+ reserved5:12; // 63:52
+ } bits;
+ unsigned long long val;
+};
+
+union msr_fidvidstatus {
+ struct {
+ unsigned CFID:5, // 4:0
+ reserved1:3, // 7:5
+ SFID:5, // 12:8
+ reserved2:3, // 15:13
+ MFID:5, // 20:16
+ reserved3:11, // 31:21
+ CVID:5, // 36:32
+ reserved4:3, // 39:37
+ SVID:5, // 44:40
+ reserved5:3, // 47:45
+ MVID:5, // 52:48
+ reserved6:11; // 63:53
+ } bits;
+ unsigned long long val;
+};
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/kernel/cpu/cpufreq/speedstep.c linux-2.5/arch/i386/kernel/cpu/cpufreq/speedstep.c
--- linux-2.5.60/arch/i386/kernel/cpu/cpufreq/speedstep.c 2003-02-10 17:37:54.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/cpufreq/speedstep.c 2003-02-10 22:48:41.000000000 -0100
@@ -1,8 +1,8 @@
/*
- * $Id: speedstep.c,v 1.58 2002/11/11 15:35:46 db Exp $
+ * $Id: speedstep.c,v 1.68 2003/01/20 17:31:47 db Exp $
*
* (C) 2001 Dave Jones, Arjan van de ven.
- * (C) 2002 Dominik Brodowski
+ * (C) 2002 - 2003 Dominik Brodowski
*
* Licensed under the terms of the GNU GPL License version 2.
* Based upon reverse engineered information, and on Intel documentation
@@ -30,7 +30,7 @@
#include
-static struct cpufreq_driver *speedstep_driver;
+static struct cpufreq_driver speedstep_driver;
/* speedstep_chipset:
* It is necessary to know which chipset is used. As accesses to
@@ -573,11 +573,13 @@ static int speedstep_detect_speeds (void
*
* Sets a new CPUFreq policy.
*/
-static int speedstep_setpolicy (struct cpufreq_policy *policy)
+static int speedstep_target (struct cpufreq_policy *policy,
+ unsigned int target_freq,
+ unsigned int relation)
{
unsigned int newstate = 0;
- if (cpufreq_frequency_table_setpolicy(policy, &speedstep_freqs[0], &newstate))
+ if (cpufreq_frequency_table_target(policy, &speedstep_freqs[0], target_freq, relation, &newstate))
return -EINVAL;
speedstep_set_state(newstate, 1);
@@ -599,6 +601,42 @@ static int speedstep_verify (struct cpuf
}
+static int speedstep_cpu_init(struct cpufreq_policy *policy)
+{
+ int result = 0;
+ unsigned int speed;
+
+ /* capability check */
+ if (policy->cpu != 0)
+ return -ENODEV;
+
+ /* detect low and high frequency */
+ result = speedstep_detect_speeds();
+ if (result)
+ return result;
+
+ /* get current speed setting */
+ result = speedstep_get_state(&speed);
+ if (result)
+ return result;
+
+ speed = (speed == SPEEDSTEP_LOW) ? speedstep_low_freq : speedstep_high_freq;
+ dprintk(KERN_INFO "cpufreq: currently at %s speed setting - %i MHz\n",
+ (speed == speedstep_low_freq) ? "low" : "high",
+ (speed / 1000));
+
+ /* cpuinfo and default policy values */
+ policy->policy = (speed == speedstep_low_freq) ?
+ CPUFREQ_POLICY_POWERSAVE : CPUFREQ_POLICY_PERFORMANCE;
+ policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
+#ifdef CONFIG_CPU_FREQ_24_API
+ speedstep_driver.cpu_cur_freq[policy->cpu] = speed;
+#endif
+
+ return cpufreq_frequency_table_cpuinfo(policy, &speedstep_freqs[0]);
+}
+
+
#ifndef MODULE
/**
* speedstep_setup speedstep command line parameter parsing
@@ -627,11 +665,6 @@ __setup("speedstep_coppermine=", speedst
*/
static int __init speedstep_init(void)
{
- int result;
- unsigned int speed;
- struct cpufreq_driver *driver;
-
-
/* detect chipset */
speedstep_chipset = speedstep_detect_chipset();
@@ -644,70 +677,13 @@ static int __init speedstep_init(void)
return -ENODEV;
}
- dprintk(KERN_INFO "cpufreq: Intel(R) SpeedStep(TM) support $Revision: 1.58 $\n");
- dprintk(KERN_DEBUG "cpufreq: chipset 0x%x - processor 0x%x\n",
- speedstep_chipset, speedstep_processor);
+ dprintk(KERN_INFO "cpufreq: Intel(R) SpeedStep(TM) support $Revision: 1.68 $\n");
/* activate speedstep support */
- result = speedstep_activate();
- if (result)
- return result;
-
- /* detect low and high frequency */
- result = speedstep_detect_speeds();
- if (result)
- return result;
-
- /* get current speed setting */
- result = speedstep_get_state(&speed);
- if (result)
- return result;
-
- speed = (speed == SPEEDSTEP_LOW) ? speedstep_low_freq : speedstep_high_freq;
-
- dprintk(KERN_INFO "cpufreq: currently at %s speed setting - %i MHz\n",
- (speed == speedstep_low_freq) ? "low" : "high",
- (speed / 1000));
-
- /* initialization of main "cpufreq" code*/
- driver = kmalloc(sizeof(struct cpufreq_driver) +
- NR_CPUS * sizeof(struct cpufreq_policy), GFP_KERNEL);
- if (!driver)
- return -ENOMEM;
-
- driver->policy = (struct cpufreq_policy *) (driver + 1);
-
- driver->policy[0].cpu = 0;
- result = cpufreq_frequency_table_cpuinfo(&driver->policy[0], &speedstep_freqs[0]);
- if (result) {
- kfree(driver);
- return result;
- }
-
-#ifdef CONFIG_CPU_FREQ_24_API
- driver->cpu_cur_freq[0] = speed;
-#endif
-
- driver->verify = &speedstep_verify;
- driver->setpolicy = &speedstep_setpolicy;
- driver->init = NULL;
- driver->exit = NULL;
- strncpy(driver->name, "speedstep", CPUFREQ_NAME_LEN);
-
- driver->policy[0].cpuinfo.transition_latency = CPUFREQ_ETERNAL;
-
- driver->policy[0].policy = (speed == speedstep_low_freq) ?
- CPUFREQ_POLICY_POWERSAVE : CPUFREQ_POLICY_PERFORMANCE;
-
- speedstep_driver = driver;
-
- result = cpufreq_register(driver);
- if (result) {
- speedstep_driver = NULL;
- kfree(driver);
- }
+ if (speedstep_activate())
+ return -EINVAL;
- return result;
+ return cpufreq_register_driver(&speedstep_driver);
}
@@ -718,17 +694,25 @@ static int __init speedstep_init(void)
*/
static void __exit speedstep_exit(void)
{
- if (speedstep_driver) {
- cpufreq_unregister();
- kfree(speedstep_driver);
- }
+ cpufreq_unregister_driver(&speedstep_driver);
}
+static struct cpufreq_driver speedstep_driver = {
+ .verify = speedstep_verify,
+ .target = speedstep_target,
+ .init = speedstep_cpu_init,
+ .exit = NULL,
+ .policy = NULL,
+ .name = "speedstep",
+};
+
+
+MODULE_PARM (speedstep_coppermine, "i");
+
MODULE_AUTHOR ("Dave Jones , Dominik Brodowski ");
MODULE_DESCRIPTION ("Speedstep driver for Intel mobile processors.");
MODULE_LICENSE ("GPL");
+
module_init(speedstep_init);
module_exit(speedstep_exit);
-
-MODULE_PARM (speedstep_coppermine, "i");
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/kernel/cpu/intel.c linux-2.5/arch/i386/kernel/cpu/intel.c
--- linux-2.5.60/arch/i386/kernel/cpu/intel.c 2003-02-10 17:38:11.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/intel.c 2003-02-10 19:54:46.000000000 -0100
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include "cpu.h"
@@ -75,6 +76,36 @@ static int __init P4_disable_ht(char *s)
}
__setup("noht", P4_disable_ht);
+/*
+ * Some 'overdrive' boards, such as those from Powerleap don't have
+ * the L2 cache enabled, and the BIOS doesn't know about it, so we
+ * have this option to 'force' it on.
+ */
+static int __init P2_enable_L2(char *s)
+{
+ unsigned long cr0, lo, hi;
+
+ printk ("CPU: Enabling L2 cache.\n");
+
+ __asm__ ("cli");
+
+ cr0 = read_cr0();
+ cr0 |= 1<<30;
+ write_cr0 (cr0);
+
+ rdmsr (0x11e, lo, hi);
+ lo |= 0x40101;
+ wrmsr (0x11e, lo, hi);
+
+ cr0 &= ~(1<<30);
+ write_cr0 (cr0);
+
+ wbinvd();
+ __asm__("sti");
+ return 0;
+}
+__setup("enable-l2", P2_enable_L2);
+
#define LVL_1_INST 1
#define LVL_1_DATA 2
#define LVL_2 3
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/kernel/cpu/mtrr/main.c linux-2.5/arch/i386/kernel/cpu/mtrr/main.c
--- linux-2.5.60/arch/i386/kernel/cpu/mtrr/main.c 2003-02-10 17:37:57.000000000 -0100
+++ linux-2.5/arch/i386/kernel/cpu/mtrr/main.c 2003-02-10 19:54:47.000000000 -0100
@@ -71,21 +71,27 @@ void set_mtrr_ops(struct mtrr_ops * ops)
mtrr_ops[ops->vendor] = ops;
}
+static int __initdata mtrr_forced;
+static int __init force_mtrr(char *s)
+{
+ mtrr_forced = 1;
+ return 0;
+}
+__setup("force-mtrr", force_mtrr);
+
/* Returns non-zero if we have the write-combining memory type */
static int have_wrcomb(void)
{
struct pci_dev *dev = NULL;
- /* WTF is this?
- * Someone, please shoot me.
- */
-
/* ServerWorks LE chipsets have problems with write-combining
- Don't allow it and leave room for other chipsets to be tagged */
+ Don't allow it and leave room for other chipsets to be tagged.
+ Rumour has it that rev6 and above are ok. Until we get confirmation
+ of this, we use the force-mtrr bootflag. */
if ((dev = pci_find_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) {
- if ((dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
- (dev->device == PCI_DEVICE_ID_SERVERWORKS_LE)) {
+ if (((dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
+ (dev->device == PCI_DEVICE_ID_SERVERWORKS_LE)) && mtrr_forced == 0) {
printk(KERN_INFO
"mtrr: Serverworks LE detected. Write-combining disabled.\n");
return 0;
@@ -574,7 +580,7 @@ static int __init mtrr_init(void)
query the width (in bits) of the physical
addressable memory on the Hammer family.
*/
- if (boot_cpu_data.x86 == 15
+ if (boot_cpu_data.x86 >= 7
&& (cpuid_eax(0x80000000) >= 0x80000008)) {
u32 phys_addr;
phys_addr = cpuid_eax(0x80000008) & 0xff;
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/kernel/i8259.c linux-2.5/arch/i386/kernel/i8259.c
--- linux-2.5.60/arch/i386/kernel/i8259.c 2003-02-10 17:38:53.000000000 -0100
+++ linux-2.5/arch/i386/kernel/i8259.c 2003-01-17 00:57:27.000000000 -0100
@@ -369,11 +369,16 @@ void __init init_ISA_irqs (void)
static void setup_timer(void)
{
+ extern spinlock_t i8253_lock;
+ unsigned long flags;
+
+ spin_lock_irqsave(&i8253_lock, flags);
outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */
udelay(10);
outb_p(LATCH & 0xff , 0x40); /* LSB */
udelay(10);
outb(LATCH >> 8 , 0x40); /* MSB */
+ spin_unlock_irqrestore(&i8253_lock, flags);
}
static int timer_resume(struct device *dev, u32 level)
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/kernel/io_apic.c linux-2.5/arch/i386/kernel/io_apic.c
--- linux-2.5.60/arch/i386/kernel/io_apic.c 2003-02-10 17:38:17.000000000 -0100
+++ linux-2.5/arch/i386/kernel/io_apic.c 2003-02-11 10:27:23.000000000 -0100
@@ -604,13 +604,21 @@ int pirq_entries [MAX_PIRQS];
int pirqs_enabled;
int skip_ioapic_setup;
-static int __init ioapic_setup(char *str)
+static int __init noioapic_setup(char *str)
{
skip_ioapic_setup = 1;
return 1;
}
-__setup("noapic", ioapic_setup);
+__setup("noapic", noioapic_setup);
+
+static int __init ioapic_setup(char *str)
+{
+ skip_ioapic_setup = 0;
+ return 1;
+}
+
+__setup("apic", ioapic_setup);
static int __init ioapic_pirq_setup(char *str)
{
@@ -1440,7 +1448,8 @@ void disable_IO_APIC(void)
* by Matt Domsch Tue Dec 21 12:25:05 CST 1999
*/
-static void __init setup_ioapic_ids_from_mpc (void)
+#ifndef CONFIG_X86_NUMAQ
+static void __init setup_ioapic_ids_from_mpc(void)
{
struct IO_APIC_reg_00 reg_00;
unsigned long phys_id_present_map;
@@ -1533,6 +1542,9 @@ static void __init setup_ioapic_ids_from
printk(" ok.\n");
}
}
+#else
+static void __init setup_ioapic_ids_from_mpc(void) { }
+#endif
/*
* There is a nasty bug in some older SMP boards, their mptable lies
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/kernel/smpboot.c linux-2.5/arch/i386/kernel/smpboot.c
--- linux-2.5.60/arch/i386/kernel/smpboot.c 2003-02-10 17:38:31.000000000 -0100
+++ linux-2.5/arch/i386/kernel/smpboot.c 2003-02-11 10:27:23.000000000 -0100
@@ -160,7 +160,6 @@ static void __init smp_store_cpu_info(in
goto valid_k7;
/* If we get here, it's not a certified SMP capable AMD system. */
- printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
tainted |= TAINT_UNSAFE_SMP;
}
@@ -935,10 +934,6 @@ static void smp_tune_scheduling (void)
* Cycle through the processors sending APIC IPIs to boot each.
*/
-extern int prof_multiplier[NR_CPUS];
-extern int prof_old_multiplier[NR_CPUS];
-extern int prof_counter[NR_CPUS];
-
static int boot_cpu_logical_apicid;
/* Where the IO area was mapped on multiquad, always 0 otherwise */
void *xquad_portio;
@@ -950,17 +945,6 @@ static void __init smp_boot_cpus(unsigne
int apicid, cpu, bit;
/*
- * Initialize the logical to physical CPU number mapping
- * and the per-CPU profiling counter/multiplier
- */
-
- for (cpu = 0; cpu < NR_CPUS; cpu++) {
- prof_counter[cpu] = 1;
- prof_old_multiplier[cpu] = 1;
- prof_multiplier[cpu] = 1;
- }
-
- /*
* Setup boot CPU information
*/
smp_store_cpu_info(0); /* Final full version of the data */
@@ -1084,6 +1068,15 @@ static void __init smp_boot_cpus(unsigne
if (smp_b_stepping)
printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
+
+ /* Don't taint if we are running SMP kernel on a single non-MP approved Athlon */
+ if (tainted & TAINT_UNSAFE_SMP) {
+ if (cpucount)
+ printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
+ else
+ tainted &= ~TAINT_UNSAFE_SMP;
+ }
+
Dprintk("Boot done.\n");
/*
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/kernel/traps.c linux-2.5/arch/i386/kernel/traps.c
--- linux-2.5.60/arch/i386/kernel/traps.c 2003-02-10 17:38:01.000000000 -0100
+++ linux-2.5/arch/i386/kernel/traps.c 2003-02-10 03:23:01.000000000 -0100
@@ -620,9 +620,10 @@ void math_error(void *eip)
default:
break;
case 0x001: /* Invalid Op */
- case 0x040: /* Stack Fault */
- case 0x240: /* Stack Fault | Direction */
+ case 0x041: /* Stack Fault */
+ case 0x241: /* Stack Fault | Direction */
info.si_code = FPE_FLTINV;
+ /* Should we clear the SF or let user space do it ???? */
break;
case 0x002: /* Denormalize */
case 0x010: /* Underflow */
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/i386/mach-voyager/voyager_smp.c linux-2.5/arch/i386/mach-voyager/voyager_smp.c
--- linux-2.5.60/arch/i386/mach-voyager/voyager_smp.c 2003-02-10 17:38:20.000000000 -0100
+++ linux-2.5/arch/i386/mach-voyager/voyager_smp.c 2003-02-11 10:27:23.000000000 -0100
@@ -236,7 +236,7 @@ static __u32 trampoline_base;
/* The per cpu profile stuff - used in smp_local_timer_interrupt */
static unsigned int prof_multiplier[NR_CPUS] __cacheline_aligned = { 1, };
static unsigned int prof_old_multiplier[NR_CPUS] __cacheline_aligned = { 1, };
-static unsigned int prof_counter[NR_CPUS] __cacheline_aligned = { 1, };
+static DEFINE_PER_CPU(unsigned int, prof_counter) = 1;
/* the map used to check if a CPU has booted */
static __u32 cpu_booted_map;
@@ -393,9 +393,6 @@ find_smp_config(void)
/* initialize the CPU structures (moved from smp_boot_cpus) */
for(i=0; ix86_model_id[0])
- printk("AMD %s", c->x86_model_id);
+ printk("%s", c->x86_model_id);
if (c->x86_mask || c->cpuid_level >= 0)
printk(" stepping %02x\n", c->x86_mask);
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/arch/x86_64/mm/hugetlbpage.c linux-2.5/arch/x86_64/mm/hugetlbpage.c
--- linux-2.5.60/arch/x86_64/mm/hugetlbpage.c 2003-02-10 17:38:39.000000000 -0100
+++ linux-2.5/arch/x86_64/mm/hugetlbpage.c 2003-02-11 10:27:23.000000000 -0100
@@ -86,6 +86,18 @@ static void set_huge_pte(struct mm_struc
set_pte(page_table, entry);
}
+/*
+ * This function checks for proper alignment of input addr and len parameters.
+ */
+int is_aligned_hugepage_range(unsigned long addr, unsigned long len)
+{
+ if (len & ~HPAGE_MASK)
+ return -EINVAL;
+ if (addr & ~HPAGE_MASK)
+ return -EINVAL;
+ return 0;
+}
+
int
copy_hugetlb_page_range(struct mm_struct *dst, struct mm_struct *src,
struct vm_area_struct *vma)
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/acorn/char/Makefile linux-2.5/drivers/acorn/char/Makefile
--- linux-2.5.60/drivers/acorn/char/Makefile 2003-02-10 17:37:58.000000000 -0100
+++ linux-2.5/drivers/acorn/char/Makefile 2003-01-17 00:57:49.000000000 -0100
@@ -18,6 +18,8 @@ $(obj)/defkeymap-acorn.o: $(obj)/defkeym
ifdef GENERATE_KEYMAP
$(obj)/defkeymap-acorn.c: $(obj)/%.c: $(src)/%.map
- loadkeys --mktable $< > $@
+ loadkeys --mktable $< > $@.tmp
+ sed -e 's/^static *//' $@.tmp > $@
+ rm $@.tmp
endif
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/block/DAC960.c linux-2.5/drivers/block/DAC960.c
--- linux-2.5.60/drivers/block/DAC960.c 2003-02-10 17:38:49.000000000 -0100
+++ linux-2.5/drivers/block/DAC960.c 2003-02-11 10:27:23.000000000 -0100
@@ -1731,12 +1731,17 @@ static boolean DAC960_V2_ReadControllerC
if (!DAC960_V2_NewLogicalDeviceInfo(Controller, LogicalDeviceNumber))
break;
LogicalDeviceNumber = NewLogicalDeviceInfo->LogicalDeviceNumber;
- if (LogicalDeviceNumber > DAC960_MaxLogicalDrives)
- panic("DAC960: Logical Drive Number %d not supported\n",
- LogicalDeviceNumber);
- if (NewLogicalDeviceInfo->DeviceBlockSizeInBytes != DAC960_BlockSize)
- panic("DAC960: Logical Drive Block Size %d not supported\n",
- NewLogicalDeviceInfo->DeviceBlockSizeInBytes);
+ if (LogicalDeviceNumber >= DAC960_MaxLogicalDrives) {
+ DAC960_Error("DAC960: Logical Drive Number %d not supported\n",
+ Controller, LogicalDeviceNumber);
+ break;
+ }
+ if (NewLogicalDeviceInfo->DeviceBlockSizeInBytes != DAC960_BlockSize) {
+ DAC960_Error("DAC960: Logical Drive Block Size %d not supported\n",
+ Controller, NewLogicalDeviceInfo->DeviceBlockSizeInBytes);
+ LogicalDeviceNumber++;
+ continue;
+ }
PhysicalDevice.Controller = 0;
PhysicalDevice.Channel = NewLogicalDeviceInfo->Channel;
PhysicalDevice.TargetID = NewLogicalDeviceInfo->TargetID;
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/block/cciss.c linux-2.5/drivers/block/cciss.c
--- linux-2.5.60/drivers/block/cciss.c 2003-02-10 17:38:54.000000000 -0100
+++ linux-2.5/drivers/block/cciss.c 2003-01-17 00:57:51.000000000 -0100
@@ -353,7 +353,7 @@ static int cciss_open(struct inode *inod
* but I'm already using way to many device nodes to claim another one
* for "raw controller".
*/
- if (inode->i_bdev->bd_inode->i_size == 0) {
+ if (hba[ctlr]->drv[dsk].nr_blocks == 0) {
if (minor(inode->i_rdev) != 0)
return -ENXIO;
if (!capable(CAP_SYS_ADMIN))
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/Kconfig linux-2.5/drivers/char/Kconfig
--- linux-2.5.60/drivers/char/Kconfig 2003-02-10 17:37:57.000000000 -0100
+++ linux-2.5/drivers/char/Kconfig 2003-02-10 15:26:58.000000000 -0100
@@ -745,6 +745,12 @@ config AMD_RNG
If unsure, say N.
+config CONFIG_AMD_PM768
+ depends on X86 && PCI
+ ---help---
+ If you say Y here, the kernel will use direct hardware access
+ to control power management features of the AMD 768 chipset.
+
config NVRAM
tristate "/dev/nvram support"
---help---
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/Makefile linux-2.5/drivers/char/Makefile
--- linux-2.5.60/drivers/char/Makefile 2003-02-10 17:38:54.000000000 -0100
+++ linux-2.5/drivers/char/Makefile 2003-02-04 19:12:27.000000000 -0100
@@ -61,6 +61,7 @@ obj-$(CONFIG_I8K) += i8k.o
obj-$(CONFIG_DS1620) += ds1620.o
obj-$(CONFIG_INTEL_RNG) += i810_rng.o
obj-$(CONFIG_AMD_RNG) += amd768_rng.o
+obj-$(CONFIG_AMD_PM768) += amd76x_pm.o
obj-$(CONFIG_QIC02_TAPE) += tpqic02.o
obj-$(CONFIG_FTAPE) += ftape/
obj-$(CONFIG_H8) += h8.o
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/agp/Kconfig linux-2.5/drivers/char/agp/Kconfig
--- linux-2.5.60/drivers/char/agp/Kconfig 2003-02-10 17:38:43.000000000 -0100
+++ linux-2.5/drivers/char/agp/Kconfig 2003-02-10 19:30:03.000000000 -0100
@@ -61,16 +61,6 @@ config AGP_VIA
You should say Y here if you use XFree86 3.3.6 or 4.x and want to
use GLX or DRI. If unsure, say N.
-config AGP_VIA_KT400
- tristate "VIA KT400 chipset support"
- depends on AGP3
- help
- This option gives you AGP support for the GLX component of the
- XFree86 4.x on VIA KT400 AGP 3.0 chipsets.
-
- You should say Y here if you use XFree86 3.3.6 or 4.x and want to
- use GLX or DRI. If unsure, say N.
-
config AGP_AMD
tristate "AMD Irongate, 761, and 762 support"
depends on AGP
@@ -141,6 +131,11 @@ config AGP_HP_ZX1
This option gives you AGP GART support for the HP ZX1 chipset
for IA64 processors.
+config AGP_ALPHA_CORE
+ tristate
+ depends on AGP && (ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL)
+ default AGP
+
# Put AGP 3.0 entries below here.
config AGP_I7505
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/agp/Makefile linux-2.5/drivers/char/agp/Makefile
--- linux-2.5.60/drivers/char/agp/Makefile 2003-02-10 17:38:17.000000000 -0100
+++ linux-2.5/drivers/char/agp/Makefile 2003-02-10 19:30:03.000000000 -0100
@@ -4,13 +4,14 @@
# that other drivers could use to manipulate agp memory.
agpgart-y := backend.o frontend.o generic.o
+
+
agpgart-$(CONFIG_AGP3) += generic-3.0.o
agpgart-objs := $(agpgart-y)
obj-$(CONFIG_AGP) += agpgart.o
obj-$(CONFIG_AGP_INTEL) += intel-agp.o
obj-$(CONFIG_AGP_VIA) += via-agp.o
-obj-$(CONFIG_AGP_VIA_KT400) += via-kt400.o
obj-$(CONFIG_AGP_AMD) += amd-k7-agp.o
obj-$(CONFIG_AGP_SIS) += sis-agp.o
obj-$(CONFIG_AGP_ALI) += ali-agp.o
@@ -18,6 +19,7 @@ obj-$(CONFIG_AGP_SWORKS) += sworks-agp.o
obj-$(CONFIG_AGP_I460) += i460-agp.o
obj-$(CONFIG_AGP_HP_ZX1) += hp-agp.o
obj-$(CONFIG_AGP_AMD_8151) += amd-k8-agp.o
+obj-$(CONFIG_AGP_ALPHA_CORE) += alpha-agp.o
obj-$(CONFIG_AGP_I7x05) += i7x05-agp.o
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/agp/agp.h linux-2.5/drivers/char/agp/agp.h
--- linux-2.5.60/drivers/char/agp/agp.h 2003-02-10 17:38:29.000000000 -0100
+++ linux-2.5/drivers/char/agp/agp.h 2003-02-10 19:30:03.000000000 -0100
@@ -30,7 +30,7 @@
#include /* for flush_agp_cache() */
-extern struct agp_bridge_data agp_bridge;
+extern struct agp_bridge_data *agp_bridge;
#define PFX "agpgart: "
@@ -128,6 +128,7 @@ struct agp_bridge_data {
int num_aperture_sizes;
int capndx;
int cant_use_aperture;
+ struct vm_operations_struct *vm_ops;
/* Links to driver specific functions */
@@ -165,20 +166,20 @@ struct agp_bridge_data {
#define MB(x) (KB (KB (x)))
#define GB(x) (MB (KB (x)))
-#define CACHE_FLUSH agp_bridge.cache_flush
+#define CACHE_FLUSH agp_bridge->cache_flush
#define A_SIZE_8(x) ((struct aper_size_info_8 *) x)
#define A_SIZE_16(x) ((struct aper_size_info_16 *) x)
#define A_SIZE_32(x) ((struct aper_size_info_32 *) x)
#define A_SIZE_LVL2(x) ((struct aper_size_info_lvl2 *) x)
#define A_SIZE_FIX(x) ((struct aper_size_info_fixed *) x)
-#define A_IDX8() (A_SIZE_8(agp_bridge.aperture_sizes) + i)
-#define A_IDX16() (A_SIZE_16(agp_bridge.aperture_sizes) + i)
-#define A_IDX32() (A_SIZE_32(agp_bridge.aperture_sizes) + i)
-#define A_IDXLVL2() (A_SIZE_LVL2(agp_bridge.aperture_sizes) + i)
-#define A_IDXFIX() (A_SIZE_FIX(agp_bridge.aperture_sizes) + i)
+#define A_IDX8() (A_SIZE_8(agp_bridge->aperture_sizes) + i)
+#define A_IDX16() (A_SIZE_16(agp_bridge->aperture_sizes) + i)
+#define A_IDX32() (A_SIZE_32(agp_bridge->aperture_sizes) + i)
+#define A_IDXLVL2() (A_SIZE_LVL2(agp_bridge->aperture_sizes) + i)
+#define A_IDXFIX() (A_SIZE_FIX(agp_bridge->aperture_sizes) + i)
#define MAXKEY (4096 * 32)
-#define PGE_EMPTY(p) (!(p) || (p) == (unsigned long) agp_bridge.scratch_page)
+#define PGE_EMPTY(p) (!(p) || (p) == (unsigned long) agp_bridge->scratch_page)
/* intel register */
#define INTEL_APBASE 0x10
@@ -366,7 +367,7 @@ struct agp_driver {
/* Generic routines. */
void agp_generic_agp_enable(u32 mode);
-int agp_generic_agp_3_0_enable(u32 mode);
+void agp_generic_agp_3_0_enable(u32 mode);
int agp_generic_create_gatt_table(void);
int agp_generic_free_gatt_table(void);
agp_memory *agp_create_memory(int scratch_pages);
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/agp/ali-agp.c linux-2.5/drivers/char/agp/ali-agp.c
--- linux-2.5.60/drivers/char/agp/ali-agp.c 2003-02-10 17:38:44.000000000 -0100
+++ linux-2.5/drivers/char/agp/ali-agp.c 2003-02-10 19:30:03.000000000 -0100
@@ -17,15 +17,15 @@ static int ali_fetch_size(void)
u32 temp;
struct aper_size_info_32 *values;
- pci_read_config_dword(agp_bridge.dev, ALI_ATTBASE, &temp);
+ pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp);
temp &= ~(0xfffffff0);
- values = A_SIZE_32(agp_bridge.aperture_sizes);
+ values = A_SIZE_32(agp_bridge->aperture_sizes);
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
- agp_bridge.previous_size =
- agp_bridge.current_size = (void *) (values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->previous_size =
+ agp_bridge->current_size = (void *) (values + i);
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
@@ -37,9 +37,9 @@ static void ali_tlbflush(agp_memory * me
{
u32 temp;
- pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
+ pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
// clear tag
- pci_write_config_dword(agp_bridge.dev, ALI_TAGCTRL,
+ pci_write_config_dword(agp_bridge->dev, ALI_TAGCTRL,
((temp & 0xfffffff0) | 0x00000001|0x00000002));
}
@@ -48,15 +48,15 @@ static void ali_cleanup(void)
struct aper_size_info_32 *previous_size;
u32 temp;
- previous_size = A_SIZE_32(agp_bridge.previous_size);
+ previous_size = A_SIZE_32(agp_bridge->previous_size);
- pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
+ pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
// clear tag
- pci_write_config_dword(agp_bridge.dev, ALI_TAGCTRL,
+ pci_write_config_dword(agp_bridge->dev, ALI_TAGCTRL,
((temp & 0xffffff00) | 0x00000001|0x00000002));
- pci_read_config_dword(agp_bridge.dev, ALI_ATTBASE, &temp);
- pci_write_config_dword(agp_bridge.dev, ALI_ATTBASE,
+ pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp);
+ pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE,
((temp & 0x00000ff0) | previous_size->size_value));
}
@@ -65,24 +65,24 @@ static int ali_configure(void)
u32 temp;
struct aper_size_info_32 *current_size;
- current_size = A_SIZE_32(agp_bridge.current_size);
+ current_size = A_SIZE_32(agp_bridge->current_size);
/* aperture size and gatt addr */
- pci_read_config_dword(agp_bridge.dev, ALI_ATTBASE, &temp);
- temp = (((temp & 0x00000ff0) | (agp_bridge.gatt_bus_addr & 0xfffff000))
+ pci_read_config_dword(agp_bridge->dev, ALI_ATTBASE, &temp);
+ temp = (((temp & 0x00000ff0) | (agp_bridge->gatt_bus_addr & 0xfffff000))
| (current_size->size_value & 0xf));
- pci_write_config_dword(agp_bridge.dev, ALI_ATTBASE, temp);
+ pci_write_config_dword(agp_bridge->dev, ALI_ATTBASE, temp);
/* tlb control */
- pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
- pci_write_config_dword(agp_bridge.dev, ALI_TLBCTRL, ((temp & 0xffffff00) | 0x00000010));
+ pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
+ pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, ((temp & 0xffffff00) | 0x00000010));
/* address to map to */
- pci_read_config_dword(agp_bridge.dev, ALI_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, ALI_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
#if 0
- if (agp_bridge.type == ALI_M1541) {
+ if (agp_bridge->type == ALI_M1541) {
u32 nlvm_addr = 0;
switch (current_size->size_value) {
@@ -101,15 +101,15 @@ static int ali_configure(void)
nlvm_addr--;
nlvm_addr&=0xfff00000;
- nlvm_addr+= agp_bridge.gart_bus_addr;
- nlvm_addr|=(agp_bridge.gart_bus_addr>>12);
+ nlvm_addr+= agp_bridge->gart_bus_addr;
+ nlvm_addr|=(agp_bridge->gart_bus_addr>>12);
printk(KERN_INFO PFX "nlvm top &base = %8x\n",nlvm_addr);
}
#endif
- pci_read_config_dword(agp_bridge.dev, ALI_TLBCTRL, &temp);
+ pci_read_config_dword(agp_bridge->dev, ALI_TLBCTRL, &temp);
temp &= 0xffffff7f; //enable TLB
- pci_write_config_dword(agp_bridge.dev, ALI_TLBCTRL, temp);
+ pci_write_config_dword(agp_bridge->dev, ALI_TLBCTRL, temp);
return 0;
}
@@ -118,23 +118,23 @@ static unsigned long ali_mask_memory(uns
{
/* Memory type is ignored */
- return addr | agp_bridge.masks[0].mask;
+ return addr | agp_bridge->masks[0].mask;
}
static void ali_cache_flush(void)
{
global_cache_flush();
- if (agp_bridge.type == ALI_M1541) {
+ if (agp_bridge->type == ALI_M1541) {
int i, page_count;
u32 temp;
- page_count = 1 << A_SIZE_32(agp_bridge.current_size)->page_order;
+ page_count = 1 << A_SIZE_32(agp_bridge->current_size)->page_order;
for (i = 0; i < PAGE_SIZE * page_count; i += PAGE_SIZE) {
- pci_read_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, &temp);
- pci_write_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL,
+ pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp);
+ pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
(((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
- (agp_bridge.gatt_bus_addr + i)) |
+ (agp_bridge->gatt_bus_addr + i)) |
ALI_CACHE_FLUSH_EN));
}
}
@@ -148,9 +148,9 @@ static void *ali_alloc_page(void)
if (adr == 0)
return 0;
- if (agp_bridge.type == ALI_M1541) {
- pci_read_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, &temp);
- pci_write_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL,
+ if (agp_bridge->type == ALI_M1541) {
+ pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp);
+ pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
(((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
virt_to_phys(adr)) |
ALI_CACHE_FLUSH_EN ));
@@ -167,9 +167,9 @@ static void ali_destroy_page(void * addr
global_cache_flush();
- if (agp_bridge.type == ALI_M1541) {
- pci_read_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL, &temp);
- pci_write_config_dword(agp_bridge.dev, ALI_CACHE_FLUSH_CTRL,
+ if (agp_bridge->type == ALI_M1541) {
+ pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp);
+ pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
(((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
virt_to_phys(addr)) |
ALI_CACHE_FLUSH_EN));
@@ -197,30 +197,30 @@ static struct aper_size_info_32 ali_gene
static int __init ali_generic_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = ali_generic_masks;
- agp_bridge.aperture_sizes = (void *) ali_generic_sizes;
- agp_bridge.size_type = U32_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = ali_configure;
- agp_bridge.fetch_size = ali_fetch_size;
- agp_bridge.cleanup = ali_cleanup;
- agp_bridge.tlb_flush = ali_tlbflush;
- agp_bridge.mask_memory = ali_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = ali_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = ali_alloc_page;
- agp_bridge.agp_destroy_page = ali_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = ali_generic_masks;
+ agp_bridge->aperture_sizes = (void *) ali_generic_sizes;
+ agp_bridge->size_type = U32_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = ali_configure;
+ agp_bridge->fetch_size = ali_fetch_size;
+ agp_bridge->cleanup = ali_cleanup;
+ agp_bridge->tlb_flush = ali_tlbflush;
+ agp_bridge->mask_memory = ali_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = ali_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = ali_alloc_page;
+ agp_bridge->agp_destroy_page = ali_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
@@ -313,7 +313,7 @@ static int __init agp_lookup_host_bridge
printk (KERN_INFO PFX "Detected ALi %s chipset\n",
devs[j].chipset_name);
- agp_bridge.type = devs[j].chipset;
+ agp_bridge->type = devs[j].chipset;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
@@ -327,7 +327,7 @@ static int __init agp_lookup_host_bridge
if (agp_try_unsupported) {
printk(KERN_WARNING PFX "Trying generic ALi routines"
" for device id: %04x\n", pdev->device);
- agp_bridge.type = ALI_GENERIC;
+ agp_bridge->type = ALI_GENERIC;
return ali_generic_setup(pdev);
}
@@ -350,10 +350,10 @@ static int __init agp_ali_probe (struct
/* probe for known chipsets */
if (agp_lookup_host_bridge(dev) != -ENODEV) {
- agp_bridge.dev = dev;
- agp_bridge.capndx = cap_ptr;
+ agp_bridge->dev = dev;
+ agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
ali_agp_driver.dev = dev;
agp_register_driver(&ali_agp_driver);
return 0;
@@ -387,7 +387,7 @@ static int __init agp_ali_init(void)
ret_val = pci_module_init(&agp_ali_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/agp/alpha-agp.c linux-2.5/drivers/char/agp/alpha-agp.c
--- linux-2.5.60/drivers/char/agp/alpha-agp.c 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/drivers/char/agp/alpha-agp.c 2003-02-10 19:55:56.000000000 -0100
@@ -0,0 +1,217 @@
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include "../../../arch/alpha/kernel/pci_impl.h"
+
+#include "agp.h"
+
+static struct page *alpha_core_agp_vm_nopage(struct vm_area_struct *vma,
+ unsigned long address,
+ int write_access)
+{
+ alpha_agp_info *agp = agp_bridge->dev_private_data;
+ dma_addr_t dma_addr;
+ unsigned long pa;
+ struct page *page;
+
+ dma_addr = address - vma->vm_start + agp->aperture.bus_base;
+ pa = agp->ops->translate(agp, dma_addr);
+
+ if (pa == (unsigned long)-EINVAL) return NULL; /* no translation */
+
+ /*
+ * Get the page, inc the use count, and return it
+ */
+ page = virt_to_page(__va(pa));
+ get_page(page);
+ return page;
+}
+
+static struct aper_size_info_fixed alpha_core_agp_sizes[] =
+{
+ { 0, 0, 0 }, /* filled in by alpha_core_agp_setup */
+};
+
+static struct gatt_mask alpha_core_agp_masks[] = {
+ { .mask = 0, .type = 0 },
+};
+
+struct vm_operations_struct alpha_core_agp_vm_ops = {
+ .nopage = alpha_core_agp_vm_nopage,
+};
+
+
+static int alpha_core_agp_nop(void)
+{
+ /* just return success */
+ return 0;
+}
+
+static int alpha_core_agp_fetch_size(void)
+{
+ return alpha_core_agp_sizes[0].size;
+}
+
+static int alpha_core_agp_configure(void)
+{
+ alpha_agp_info *agp = agp_bridge->dev_private_data;
+ agp_bridge->gart_bus_addr = agp->aperture.bus_base;
+ return 0;
+}
+
+static void alpha_core_agp_cleanup(void)
+{
+ alpha_agp_info *agp = agp_bridge->dev_private_data;
+
+ agp->ops->cleanup(agp);
+}
+
+static void alpha_core_agp_tlbflush(agp_memory *mem)
+{
+ alpha_agp_info *agp = agp_bridge->dev_private_data;
+ alpha_mv.mv_pci_tbi(agp->hose, 0, -1);
+}
+
+static unsigned long alpha_core_agp_mask_memory(unsigned long addr, int type)
+{
+ /* Memory type is ignored */
+ return addr | agp_bridge->masks[0].mask;
+}
+
+static void alpha_core_agp_enable(u32 mode)
+{
+ alpha_agp_info *agp = agp_bridge->dev_private_data;
+
+ agp->mode.lw = agp_collect_device_status(mode, agp->capability.lw);
+
+ agp->mode.bits.enable = 1;
+ agp->ops->configure(agp);
+
+ agp_device_command(agp->mode.lw, 0);
+}
+
+static int alpha_core_agp_insert_memory(agp_memory *mem, off_t pg_start,
+ int type)
+{
+ alpha_agp_info *agp = agp_bridge->dev_private_data;
+ int num_entries, status;
+ void *temp;
+
+ temp = agp_bridge->current_size;
+ num_entries = A_SIZE_FIX(temp)->num_entries;
+ if ((pg_start + mem->page_count) > num_entries) return -EINVAL;
+
+ status = agp->ops->bind(agp, pg_start, mem);
+ mb();
+ agp_bridge->tlb_flush(mem);
+
+ return status;
+}
+
+static int alpha_core_agp_remove_memory(agp_memory *mem, off_t pg_start,
+ int type)
+{
+ alpha_agp_info *agp = agp_bridge->dev_private_data;
+ int status;
+
+ status = agp->ops->unbind(agp, pg_start, mem);
+ agp_bridge->tlb_flush(mem);
+ return status;
+}
+
+
+static struct agp_driver alpha_core_agp_driver = {
+ .owner = THIS_MODULE,
+};
+
+int __init
+alpha_core_agp_setup(void)
+{
+ alpha_agp_info *agp = alpha_mv.agp_info();
+ struct aper_size_info_fixed *aper_size;
+
+ if (!agp) return -ENODEV;
+ if (agp->ops->setup(agp)) return -ENODEV;
+
+ /*
+ * Build the aperture size descriptor
+ */
+ aper_size = alpha_core_agp_sizes;
+ if (!aper_size) return -ENOMEM;
+ aper_size->size = agp->aperture.size / (1024 * 1024);
+ aper_size->num_entries = agp->aperture.size / PAGE_SIZE;
+ aper_size->page_order = ffs(aper_size->num_entries / 1024) - 1;
+
+ /*
+ * Build a fake pci_dev struct
+ */
+ if (!(agp_bridge->dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL))) {
+ return -ENOMEM;
+ }
+ agp_bridge->dev->vendor = 0xffff;
+ agp_bridge->dev->device = 0xffff;
+ agp_bridge->dev->sysdata = agp->hose;
+
+ /*
+ * Fill in the rest of the agp_bridge struct
+ */
+ agp_bridge->masks = alpha_core_agp_masks;
+ agp_bridge->aperture_sizes = aper_size;
+ agp_bridge->current_size = aper_size; /* only one entry */
+ agp_bridge->size_type = FIXED_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 1;
+ agp_bridge->dev_private_data = agp;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = alpha_core_agp_configure;
+ agp_bridge->fetch_size = alpha_core_agp_fetch_size;
+ agp_bridge->cleanup = alpha_core_agp_cleanup;
+ agp_bridge->tlb_flush = alpha_core_agp_tlbflush;
+ agp_bridge->mask_memory = alpha_core_agp_mask_memory;
+ agp_bridge->agp_enable = alpha_core_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = alpha_core_agp_nop;
+ agp_bridge->free_gatt_table = alpha_core_agp_nop;
+ agp_bridge->insert_memory = alpha_core_agp_insert_memory;
+ agp_bridge->remove_memory = alpha_core_agp_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->mode = agp->capability.lw;
+ agp_bridge->cant_use_aperture = 1;
+ agp_bridgevm_ops = &alpha_core_agp_vm_ops;
+
+ alpha_core_agp_driver.dev = agp_bridge->dev;
+ agp_register_driver(&alpha_core_agp_driver);
+ printk(KERN_INFO "Detected AGP on hose %d\n", agp->hose->index);
+ return 0;
+}
+
+static int __init agp_alpha_core_init(void)
+{
+ int ret_val = -ENODEV;
+ if (alpha_mv.agp_info) {
+ agp_bridge->type = ALPHA_CORE_AGP;
+ ret_val = alpha_core_agp_setup();
+ }
+
+ return ret_val;
+}
+
+static void __exit agp_alpha_core_cleanup(void)
+{
+ agp_unregister_driver(&alpha_core_agp_driver);
+ /* no pci driver for core */
+}
+
+module_init(agp_alpha_core_init);
+module_exit(agp_alpha_core_cleanup);
+
+MODULE_AUTHOR("Jeff Wiedemeier ");
+MODULE_LICENSE("GPL and additional rights");
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/agp/amd-k7-agp.c linux-2.5/drivers/char/agp/amd-k7-agp.c
--- linux-2.5.60/drivers/char/agp/amd-k7-agp.c 2003-02-10 17:39:17.000000000 -0100
+++ linux-2.5/drivers/char/agp/amd-k7-agp.c 2003-02-10 19:30:03.000000000 -0100
@@ -45,7 +45,7 @@ static int amd_create_page_map(struct am
CACHE_FLUSH();
for(i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
- page_map->remapped[i] = agp_bridge.scratch_page;
+ page_map->remapped[i] = agp_bridge->scratch_page;
}
return 0;
@@ -115,7 +115,7 @@ static int amd_create_gatt_pages(int nr_
#define GET_PAGE_DIR_OFF(addr) (addr >> 22)
#define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
- GET_PAGE_DIR_OFF(agp_bridge.gart_bus_addr))
+ GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
#define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
#define GET_GATT(addr) (amd_irongate_private.gatt_pages[\
GET_PAGE_DIR_IDX(addr)]->remapped)
@@ -129,7 +129,7 @@ static int amd_create_gatt_table(void)
u32 temp;
int i;
- value = A_SIZE_LVL2(agp_bridge.current_size);
+ value = A_SIZE_LVL2(agp_bridge->current_size);
retval = amd_create_page_map(&page_dir);
if (retval != 0) {
return retval;
@@ -141,18 +141,18 @@ static int amd_create_gatt_table(void)
return retval;
}
- agp_bridge.gatt_table_real = (u32 *)page_dir.real;
- agp_bridge.gatt_table = (u32 *)page_dir.remapped;
- agp_bridge.gatt_bus_addr = virt_to_phys(page_dir.real);
+ agp_bridge->gatt_table_real = (u32 *)page_dir.real;
+ agp_bridge->gatt_table = (u32 *)page_dir.remapped;
+ agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
/* Get the address for the gart region.
* This is a bus address even on the alpha, b/c its
* used to program the agp master not the cpu
*/
- pci_read_config_dword(agp_bridge.dev, AMD_APBASE, &temp);
+ pci_read_config_dword(agp_bridge->dev, AMD_APBASE, &temp);
addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
- agp_bridge.gart_bus_addr = addr;
+ agp_bridge->gart_bus_addr = addr;
/* Calculate the agp offset */
for(i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {
@@ -168,8 +168,8 @@ static int amd_free_gatt_table(void)
{
struct amd_page_map page_dir;
- page_dir.real = (unsigned long *)agp_bridge.gatt_table_real;
- page_dir.remapped = (unsigned long *)agp_bridge.gatt_table;
+ page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
+ page_dir.remapped = (unsigned long *)agp_bridge->gatt_table;
amd_free_gatt_pages();
amd_free_page_map(&page_dir);
@@ -182,15 +182,15 @@ static int amd_irongate_fetch_size(void)
u32 temp;
struct aper_size_info_lvl2 *values;
- pci_read_config_dword(agp_bridge.dev, AMD_APSIZE, &temp);
+ pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
temp = (temp & 0x0000000e);
- values = A_SIZE_LVL2(agp_bridge.aperture_sizes);
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ values = A_SIZE_LVL2(agp_bridge->aperture_sizes);
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
- agp_bridge.previous_size =
- agp_bridge.current_size = (void *) (values + i);
+ agp_bridge->previous_size =
+ agp_bridge->current_size = (void *) (values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
@@ -204,22 +204,22 @@ static int amd_irongate_configure(void)
u32 temp;
u16 enable_reg;
- current_size = A_SIZE_LVL2(agp_bridge.current_size);
+ current_size = A_SIZE_LVL2(agp_bridge->current_size);
/* Get the memory mapped registers */
- pci_read_config_dword(agp_bridge.dev, AMD_MMBASE, &temp);
+ pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp);
temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
amd_irongate_private.registers = (volatile u8 *) ioremap(temp, 4096);
/* Write out the address of the gatt table */
OUTREG32(amd_irongate_private.registers, AMD_ATTBASE,
- agp_bridge.gatt_bus_addr);
+ agp_bridge->gatt_bus_addr);
/* Write the Sync register */
- pci_write_config_byte(agp_bridge.dev, AMD_MODECNTL, 0x80);
+ pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80);
/* Set indexing mode */
- pci_write_config_byte(agp_bridge.dev, AMD_MODECNTL2, 0x00);
+ pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00);
/* Write the enable register */
enable_reg = INREG16(amd_irongate_private.registers, AMD_GARTENABLE);
@@ -227,10 +227,10 @@ static int amd_irongate_configure(void)
OUTREG16(amd_irongate_private.registers, AMD_GARTENABLE, enable_reg);
/* Write out the size register */
- pci_read_config_dword(agp_bridge.dev, AMD_APSIZE, &temp);
+ pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
temp = (((temp & ~(0x0000000e)) | current_size->size_value)
| 0x00000001);
- pci_write_config_dword(agp_bridge.dev, AMD_APSIZE, temp);
+ pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
/* Flush the tlb */
OUTREG32(amd_irongate_private.registers, AMD_TLBFLUSH, 0x00000001);
@@ -244,16 +244,16 @@ static void amd_irongate_cleanup(void)
u32 temp;
u16 enable_reg;
- previous_size = A_SIZE_LVL2(agp_bridge.previous_size);
+ previous_size = A_SIZE_LVL2(agp_bridge->previous_size);
enable_reg = INREG16(amd_irongate_private.registers, AMD_GARTENABLE);
enable_reg = (enable_reg & ~(0x0004));
OUTREG16(amd_irongate_private.registers, AMD_GARTENABLE, enable_reg);
/* Write back the previous size and disable gart translation */
- pci_read_config_dword(agp_bridge.dev, AMD_APSIZE, &temp);
+ pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
temp = ((temp & ~(0x0000000f)) | previous_size->size_value);
- pci_write_config_dword(agp_bridge.dev, AMD_APSIZE, temp);
+ pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
iounmap((void *) amd_irongate_private.registers);
}
@@ -274,7 +274,7 @@ static unsigned long amd_irongate_mask_m
{
/* Only type 0 is supported by the irongate */
- return addr | agp_bridge.masks[0].mask;
+ return addr | agp_bridge->masks[0].mask;
}
static int amd_insert_memory(agp_memory * mem,
@@ -284,7 +284,7 @@ static int amd_insert_memory(agp_memory
unsigned long *cur_gatt;
unsigned long addr;
- num_entries = A_SIZE_LVL2(agp_bridge.current_size)->num_entries;
+ num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
if (type != 0 || mem->type != 0) {
return -EINVAL;
@@ -295,7 +295,7 @@ static int amd_insert_memory(agp_memory
j = pg_start;
while (j < (pg_start + mem->page_count)) {
- addr = (j * PAGE_SIZE) + agp_bridge.gart_bus_addr;
+ addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = GET_GATT(addr);
if (!PGE_EMPTY(cur_gatt[GET_GATT_OFF(addr)])) {
return -EBUSY;
@@ -309,12 +309,12 @@ static int amd_insert_memory(agp_memory
}
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
- addr = (j * PAGE_SIZE) + agp_bridge.gart_bus_addr;
+ addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = GET_GATT(addr);
cur_gatt[GET_GATT_OFF(addr)] =
- agp_bridge.mask_memory(mem->memory[i], mem->type);
+ agp_bridge->mask_memory(mem->memory[i], mem->type);
}
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
@@ -329,13 +329,13 @@ static int amd_remove_memory(agp_memory
return -EINVAL;
}
for (i = pg_start; i < (mem->page_count + pg_start); i++) {
- addr = (i * PAGE_SIZE) + agp_bridge.gart_bus_addr;
+ addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = GET_GATT(addr);
cur_gatt[GET_GATT_OFF(addr)] =
- (unsigned long) agp_bridge.scratch_page;
+ (unsigned long) agp_bridge->scratch_page;
}
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
@@ -357,30 +357,30 @@ static struct gatt_mask amd_irongate_mas
static int __init amd_irongate_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = amd_irongate_masks;
- agp_bridge.aperture_sizes = (void *) amd_irongate_sizes;
- agp_bridge.size_type = LVL2_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = (void *) &amd_irongate_private;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = amd_irongate_configure;
- agp_bridge.fetch_size = amd_irongate_fetch_size;
- agp_bridge.cleanup = amd_irongate_cleanup;
- agp_bridge.tlb_flush = amd_irongate_tlbflush;
- agp_bridge.mask_memory = amd_irongate_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = amd_create_gatt_table;
- agp_bridge.free_gatt_table = amd_free_gatt_table;
- agp_bridge.insert_memory = amd_insert_memory;
- agp_bridge.remove_memory = amd_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = amd_irongate_masks;
+ agp_bridge->aperture_sizes = (void *) amd_irongate_sizes;
+ agp_bridge->size_type = LVL2_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = (void *) &amd_irongate_private;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = amd_irongate_configure;
+ agp_bridge->fetch_size = amd_irongate_fetch_size;
+ agp_bridge->cleanup = amd_irongate_cleanup;
+ agp_bridge->tlb_flush = amd_irongate_tlbflush;
+ agp_bridge->mask_memory = amd_irongate_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = amd_create_gatt_table;
+ agp_bridge->free_gatt_table = amd_free_gatt_table;
+ agp_bridge->insert_memory = amd_insert_memory;
+ agp_bridge->remove_memory = amd_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
@@ -416,7 +416,7 @@ static int __init agp_lookup_host_bridge
while (devs[j].chipset_name != NULL) {
if (pdev->device == devs[j].device_id) {
printk (KERN_INFO PFX "Detected AMD %s chipset\n", devs[j].chipset_name);
- agp_bridge.type = devs[j].chipset;
+ agp_bridge->type = devs[j].chipset;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
@@ -430,7 +430,7 @@ static int __init agp_lookup_host_bridge
if (agp_try_unsupported) {
printk(KERN_WARNING PFX "Trying generic AMD routines"
" for device id: %04x\n", pdev->device);
- agp_bridge.type = AMD_GENERIC;
+ agp_bridge->type = AMD_GENERIC;
return amd_irongate_setup(pdev);
}
@@ -455,10 +455,10 @@ static int __init agp_amdk7_probe (struc
return -ENODEV;
if (agp_lookup_host_bridge(dev) != -ENODEV) {
- agp_bridge.dev = dev;
- agp_bridge.capndx = cap_ptr;
+ agp_bridge->dev = dev;
+ agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
amd_k7_agp_driver.dev = dev;
agp_register_driver(&amd_k7_agp_driver);
return 0;
@@ -492,7 +492,7 @@ static int __init agp_amdk7_init(void)
ret_val = pci_module_init(&agp_amdk7_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/agp/amd-k8-agp.c linux-2.5/drivers/char/agp/amd-k8-agp.c
--- linux-2.5.60/drivers/char/agp/amd-k8-agp.c 2003-02-10 17:38:44.000000000 -0100
+++ linux-2.5/drivers/char/agp/amd-k8-agp.c 2003-02-10 19:30:03.000000000 -0100
@@ -70,7 +70,7 @@ static int x86_64_insert_memory(agp_memo
/* gatt table should be empty. */
while (j < (pg_start + mem->page_count)) {
- if (!PGE_EMPTY(agp_bridge.gatt_table[j]))
+ if (!PGE_EMPTY(agp_bridge->gatt_table[j]))
return -EBUSY;
j++;
}
@@ -81,7 +81,7 @@ static int x86_64_insert_memory(agp_memo
}
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
- addr = agp_bridge.mask_memory(mem->memory[i], mem->type);
+ addr = agp_bridge->mask_memory(mem->memory[i], mem->type);
tmp = addr;
BUG_ON(tmp & 0xffffff0000000ffc);
@@ -89,9 +89,9 @@ static int x86_64_insert_memory(agp_memo
pte |=(tmp & 0x00000000fffff000);
pte |= 1<<1|1<<0;
- agp_bridge.gatt_table[j] = pte;
+ agp_bridge->gatt_table[j] = pte;
}
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
@@ -134,12 +134,12 @@ static int amd_x86_64_fetch_size(void)
temp = (temp & 0xe);
values = A_SIZE_32(x86_64_aperture_sizes);
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
- agp_bridge.previous_size =
- agp_bridge.current_size = (void *) (values + i);
+ agp_bridge->previous_size =
+ agp_bridge->current_size = (void *) (values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
@@ -225,14 +225,14 @@ static int amd_8151_configure(void)
int current_size;
int tmp, tmp2, i;
u64 aperbar;
- unsigned long gatt_bus = virt_to_phys(agp_bridge.gatt_table_real);
+ unsigned long gatt_bus = virt_to_phys(agp_bridge->gatt_table_real);
/* Configure AGP regs in each x86-64 host bridge. */
pci_for_each_dev(dev) {
if (dev->bus->number==0 &&
PCI_FUNC(dev->devfn)==3 &&
PCI_SLOT(dev->devfn)>=24 && PCI_SLOT(dev->devfn)<=31) {
- agp_bridge.gart_bus_addr = amd_x86_64_configure(dev,gatt_bus);
+ agp_bridge->gart_bus_addr = amd_x86_64_configure(dev,gatt_bus);
hammer = dev;
/*
@@ -248,7 +248,7 @@ static int amd_8151_configure(void)
/* Shadow x86-64 registers into 8151 registers. */
- dev = agp_bridge.dev;
+ dev = agp_bridge->dev;
if (!dev)
return -ENODEV;
@@ -315,7 +315,7 @@ static void amd_8151_cleanup(void)
static unsigned long amd_8151_mask_memory(unsigned long addr, int type)
{
- return addr | agp_bridge.masks[0].mask;
+ return addr | agp_bridge->masks[0].mask;
}
@@ -368,12 +368,12 @@ static void agp_x86_64_agp_enable(u32 mo
}
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &command);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &command);
command = agp_collect_device_status(mode, command);
command |= 0x100;
- pci_write_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_COMMAND, command);
+ pci_write_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_COMMAND, command);
agp_device_command(command, 1);
}
@@ -381,30 +381,30 @@ static void agp_x86_64_agp_enable(u32 mo
static int __init amd_8151_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = amd_8151_masks;
- agp_bridge.aperture_sizes = (void *) amd_8151_sizes;
- agp_bridge.size_type = U32_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = amd_8151_configure;
- agp_bridge.fetch_size = amd_x86_64_fetch_size;
- agp_bridge.cleanup = amd_8151_cleanup;
- agp_bridge.tlb_flush = amd_x86_64_tlbflush;
- agp_bridge.mask_memory = amd_8151_mask_memory;
- agp_bridge.agp_enable = agp_x86_64_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = x86_64_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = amd_8151_masks;
+ agp_bridge->aperture_sizes = (void *) amd_8151_sizes;
+ agp_bridge->size_type = U32_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = amd_8151_configure;
+ agp_bridge->fetch_size = amd_x86_64_fetch_size;
+ agp_bridge->cleanup = amd_8151_cleanup;
+ agp_bridge->tlb_flush = amd_x86_64_tlbflush;
+ agp_bridge->mask_memory = amd_8151_mask_memory;
+ agp_bridge->agp_enable = agp_x86_64_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = x86_64_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
@@ -420,11 +420,11 @@ static int __init agp_amdk8_probe (struc
if (cap_ptr == 0)
return -ENODEV;
- agp_bridge.dev = dev;
- agp_bridge.capndx = cap_ptr;
+ agp_bridge->dev = dev;
+ agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
amd_8151_setup(dev);
amd_k8_agp_driver.dev = dev;
agp_register_driver(&amd_k8_agp_driver);
@@ -458,9 +458,9 @@ int __init agp_amdk8_init(void)
ret_val = pci_module_init(&agp_amdk8_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
- agp_bridge.type = AMD_8151;
+ agp_bridge->type = AMD_8151;
return ret_val;
}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/agp/backend.c linux-2.5/drivers/char/agp/backend.c
--- linux-2.5.60/drivers/char/agp/backend.c 2003-02-10 17:38:46.000000000 -0100
+++ linux-2.5/drivers/char/agp/backend.c 2003-02-10 19:30:03.000000000 -0100
@@ -44,26 +44,27 @@
#define AGPGART_VERSION_MAJOR 0
#define AGPGART_VERSION_MINOR 100
-struct agp_bridge_data agp_bridge = { .type = NOT_SUPPORTED };
+struct agp_bridge_data agp_bridge_dummy = { .type = NOT_SUPPORTED };
+struct agp_bridge_data *agp_bridge = &agp_bridge_dummy;
int agp_backend_acquire(void)
{
- if (agp_bridge.type == NOT_SUPPORTED)
+ if (agp_bridge->type == NOT_SUPPORTED)
return -EINVAL;
- if (atomic_read(&agp_bridge.agp_in_use) != 0)
+ if (atomic_read(&agp_bridge->agp_in_use) != 0)
return -EBUSY;
- atomic_inc(&agp_bridge.agp_in_use);
+ atomic_inc(&agp_bridge->agp_in_use);
return 0;
}
void agp_backend_release(void)
{
- if (agp_bridge.type == NOT_SUPPORTED)
+ if (agp_bridge->type == NOT_SUPPORTED)
return;
- atomic_dec(&agp_bridge.agp_in_use);
+ atomic_dec(&agp_bridge->agp_in_use);
}
struct agp_max_table {
@@ -114,38 +115,38 @@ static int agp_backend_initialize(struct
{
int size_value, rc, got_gatt=0, got_keylist=0;
- agp_bridge.max_memory_agp = agp_find_max();
- agp_bridge.version = &agp_current_version;
+ agp_bridge->max_memory_agp = agp_find_max();
+ agp_bridge->version = &agp_current_version;
- if (agp_bridge.needs_scratch_page == TRUE) {
+ if (agp_bridge->needs_scratch_page == TRUE) {
void *addr;
- addr = agp_bridge.agp_alloc_page();
+ addr = agp_bridge->agp_alloc_page();
if (addr == NULL) {
printk(KERN_ERR PFX "unable to get memory for scratch page.\n");
return -ENOMEM;
}
- agp_bridge.scratch_page_real = virt_to_phys(addr);
- agp_bridge.scratch_page =
- agp_bridge.mask_memory(agp_bridge.scratch_page_real, 0);
+ agp_bridge->scratch_page_real = virt_to_phys(addr);
+ agp_bridge->scratch_page =
+ agp_bridge->mask_memory(agp_bridge->scratch_page_real, 0);
}
- size_value = agp_bridge.fetch_size();
+ size_value = agp_bridge->fetch_size();
if (size_value == 0) {
printk(KERN_ERR PFX "unable to determine aperture size.\n");
rc = -EINVAL;
goto err_out;
}
- if (agp_bridge.create_gatt_table()) {
+ if (agp_bridge->create_gatt_table()) {
printk(KERN_ERR PFX "unable to get memory for graphics translation table.\n");
rc = -ENOMEM;
goto err_out;
}
got_gatt = 1;
- agp_bridge.key_list = vmalloc(PAGE_SIZE * 4);
- if (agp_bridge.key_list == NULL) {
+ agp_bridge->key_list = vmalloc(PAGE_SIZE * 4);
+ if (agp_bridge->key_list == NULL) {
printk(KERN_ERR PFX "error allocating memory for key lists.\n");
rc = -ENOMEM;
goto err_out;
@@ -153,27 +154,27 @@ static int agp_backend_initialize(struct
got_keylist = 1;
/* FIXME vmalloc'd memory not guaranteed contiguous */
- memset(agp_bridge.key_list, 0, PAGE_SIZE * 4);
+ memset(agp_bridge->key_list, 0, PAGE_SIZE * 4);
- if (agp_bridge.configure()) {
+ if (agp_bridge->configure()) {
printk(KERN_ERR PFX "error configuring host chipset.\n");
rc = -EINVAL;
goto err_out;
}
printk(KERN_INFO PFX "AGP aperture is %dM @ 0x%lx\n",
- size_value, agp_bridge.gart_bus_addr);
+ size_value, agp_bridge->gart_bus_addr);
return 0;
err_out:
- if (agp_bridge.needs_scratch_page == TRUE) {
- agp_bridge.agp_destroy_page(phys_to_virt(agp_bridge.scratch_page_real));
+ if (agp_bridge->needs_scratch_page == TRUE) {
+ agp_bridge->agp_destroy_page(phys_to_virt(agp_bridge->scratch_page_real));
}
if (got_gatt)
- agp_bridge.free_gatt_table();
+ agp_bridge->free_gatt_table();
if (got_keylist)
- vfree(agp_bridge.key_list);
+ vfree(agp_bridge->key_list);
return rc;
}
@@ -181,13 +182,16 @@ err_out:
/* cannot be __exit b/c as it could be called from __init code */
static void agp_backend_cleanup(void)
{
- agp_bridge.cleanup();
- agp_bridge.free_gatt_table();
- vfree(agp_bridge.key_list);
-
- if (agp_bridge.needs_scratch_page == TRUE) {
- agp_bridge.agp_destroy_page(phys_to_virt(agp_bridge.scratch_page_real));
- }
+ if (agp_bridge->cleanup != NULL)
+ agp_bridge->cleanup();
+ if (agp_bridge->free_gatt_table != NULL)
+ agp_bridge->free_gatt_table();
+ if (agp_bridge->key_list)
+ vfree(agp_bridge->key_list);
+
+ if ((agp_bridge->agp_destroy_page!=NULL) &&
+ (agp_bridge->needs_scratch_page == TRUE))
+ agp_bridge->agp_destroy_page(phys_to_virt(agp_bridge->scratch_page_real));
}
static int agp_power(struct pm_dev *dev, pm_request_t rq, void *data)
@@ -195,9 +199,9 @@ static int agp_power(struct pm_dev *dev,
switch(rq)
{
case PM_SUSPEND:
- return agp_bridge.suspend();
+ return agp_bridge->suspend();
case PM_RESUME:
- agp_bridge.resume();
+ agp_bridge->resume();
return 0;
}
return 0;
@@ -248,21 +252,25 @@ int agp_register_driver (struct agp_driv
/* FIXME: What to do with this? */
inter_module_register("drm_agp", THIS_MODULE, &drm_agp);
- pm_register(PM_PCI_DEV, PM_PCI_ID(agp_bridge.dev), agp_power);
+ pm_register(PM_PCI_DEV, PM_PCI_ID(agp_bridge->dev), agp_power);
agp_count++;
return 0;
frontend_err:
agp_backend_cleanup();
err_out:
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
module_put(drv->owner);
+ drv->dev = NULL;
return ret_val;
}
int agp_unregister_driver(struct agp_driver *drv)
{
- agp_bridge.type = NOT_SUPPORTED;
+ if (drv->dev==NULL)
+ return -ENODEV;
+
+ agp_bridge->type = NOT_SUPPORTED;
pm_unregister_all(agp_power);
agp_frontend_cleanup();
agp_backend_cleanup();
@@ -282,8 +290,8 @@ int __init agp_init(void)
already_initialised = 1;
- memset(&agp_bridge, 0, sizeof(struct agp_bridge_data));
- agp_bridge.type = NOT_SUPPORTED;
+ memset(agp_bridge, 0, sizeof(struct agp_bridge_data));
+ agp_bridge->type = NOT_SUPPORTED;
printk(KERN_INFO "Linux agpgart interface v%d.%d (c) Dave Jones\n",
AGPGART_VERSION_MAJOR, AGPGART_VERSION_MINOR);
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/agp/frontend.c linux-2.5/drivers/char/agp/frontend.c
--- linux-2.5.60/drivers/char/agp/frontend.c 2003-02-10 17:37:59.000000000 -0100
+++ linux-2.5/drivers/char/agp/frontend.c 2003-02-10 19:30:03.000000000 -0100
@@ -97,7 +97,9 @@ static agp_segment_priv *agp_find_seg_in
int size, pgprot_t page_prot)
{
agp_segment_priv *seg;
- int num_segments, pg_start, pg_count, i;
+ int num_segments, i;
+ off_t pg_start;
+ size_t pg_count;
pg_start = offset / 4096;
pg_count = size / 4096;
@@ -174,7 +176,7 @@ static int agp_create_segment(agp_client
agp_segment_priv **ret_seg;
agp_segment_priv *seg;
agp_segment *user_seg;
- int i;
+ size_t i;
seg = kmalloc((sizeof(agp_segment_priv) * region->seg_count), GFP_KERNEL);
if (seg == NULL) {
@@ -578,8 +580,7 @@ static int agp_remove_client(pid_t id)
static int agp_mmap(struct file *file, struct vm_area_struct *vma)
{
- int size;
- int current_size;
+ unsigned int size, current_size;
unsigned long offset;
agp_client *client;
agp_file_private *priv = (agp_file_private *) file->private_data;
@@ -611,8 +612,11 @@ static int agp_mmap(struct file *file, s
if (!agp_find_seg_in_client(client, offset, size, vma->vm_page_prot))
goto out_inval;
- if (remap_page_range(vma, vma->vm_start, (kerninfo.aper_base + offset),
- size, vma->vm_page_prot)) {
+ if (kerninfo.vm_ops) {
+ vma->vm_ops = kerninfo.vm_ops;
+ } else if (remap_page_range(vma, vma->vm_start,
+ (kerninfo.aper_base + offset),
+ size, vma->vm_page_prot)) {
goto out_again;
}
AGP_UNLOCK();
@@ -623,8 +627,11 @@ static int agp_mmap(struct file *file, s
if (size != current_size)
goto out_inval;
- if (remap_page_range(vma, vma->vm_start, kerninfo.aper_base,
- size, vma->vm_page_prot)) {
+ if (kerninfo.vm_ops) {
+ vma->vm_ops = kerninfo.vm_ops;
+ } else if (remap_page_range(vma, vma->vm_start,
+ kerninfo.aper_base,
+ size, vma->vm_page_prot)) {
goto out_again;
}
AGP_UNLOCK();
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/agp/generic-3.0.c linux-2.5/drivers/char/agp/generic-3.0.c
--- linux-2.5.60/drivers/char/agp/generic-3.0.c 2003-02-10 17:38:00.000000000 -0100
+++ linux-2.5/drivers/char/agp/generic-3.0.c 2003-02-10 19:30:03.000000000 -0100
@@ -77,7 +77,7 @@ static int agp_3_0_isochronous_node_enab
struct agp_3_0_dev *dev;
};
- struct pci_dev *td = agp_bridge.dev, *dev;
+ struct pci_dev *td = agp_bridge->dev, *dev;
struct list_head *head = &dev_list->list, *pos;
struct agp_3_0_dev *cur;
struct isoch_data *master, target;
@@ -117,8 +117,8 @@ static int agp_3_0_isochronous_node_enab
if((ret = agp_3_0_dev_list_sort(dev_list, ndevs)) != 0)
goto free_and_exit;
- pci_read_config_dword(td, agp_bridge.capndx + 0x0c, &tnistat);
- pci_read_config_dword(td, agp_bridge.capndx + 0x04, &tstatus);
+ pci_read_config_dword(td, agp_bridge->capndx + 0x0c, &tnistat);
+ pci_read_config_dword(td, agp_bridge->capndx + 0x04, &tstatus);
/* Extract power-on defaults from the target */
target.maxbw = (tnistat >> 16) & 0xff;
@@ -170,13 +170,13 @@ static int agp_3_0_isochronous_node_enab
* in the target's NISTAT register, so we need to do this now
* to get an accurate value for ISOCH_N later.
*/
- pci_read_config_word(td, agp_bridge.capndx + 0x20, &tnicmd);
+ pci_read_config_word(td, agp_bridge->capndx + 0x20, &tnicmd);
tnicmd &= ~(0x3 << 6);
tnicmd |= target.y << 6;
- pci_write_config_word(td, agp_bridge.capndx + 0x20, tnicmd);
+ pci_write_config_word(td, agp_bridge->capndx + 0x20, tnicmd);
/* Reread the target's ISOCH_N */
- pci_read_config_dword(td, agp_bridge.capndx + 0x0c, &tnistat);
+ pci_read_config_dword(td, agp_bridge->capndx + 0x0c, &tnistat);
target.n = (tnistat >> 8) & 0xff;
/* Calculate the minimum ISOCH_N needed by each master */
@@ -296,7 +296,7 @@ static int agp_3_0_nonisochronous_node_e
u32 trq, mrq, rem;
unsigned int cdev = 0;
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx + 0x04, &tstatus);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + 0x04, &tstatus);
trq = (tstatus >> 24) & 0xff;
mrq = trq / ndevs;
@@ -321,7 +321,7 @@ static int agp_3_0_nonisochronous_node_e
*/
static int agp_3_0_node_enable(u32 mode, u32 minor)
{
- struct pci_dev *td = agp_bridge.dev, *dev;
+ struct pci_dev *td = agp_bridge->dev, *dev;
u8 bus_num, mcapndx;
u32 isoch, arqsz, cal_cycle, tmp, rate;
u32 tstatus, tcmd, mcmd, mstatus, ncapid;
@@ -364,7 +364,7 @@ static int agp_3_0_node_enable(u32 mode,
}
/* Extract some power-on defaults from the target */
- pci_read_config_dword(td, agp_bridge.capndx + 0x04, &tstatus);
+ pci_read_config_dword(td, agp_bridge->capndx + 0x04, &tstatus);
isoch = (tstatus >> 17) & 0x1;
arqsz = (tstatus >> 13) & 0x7;
cal_cycle = (tstatus >> 10) & 0x7;
@@ -470,7 +470,7 @@ static int agp_3_0_node_enable(u32 mode,
* Also set the AGP_ENABLE bit, effectively 'turning on' the
* target (this has to be done _before_ turning on the masters).
*/
- pci_read_config_dword(td, agp_bridge.capndx + 0x08, &tcmd);
+ pci_read_config_dword(td, agp_bridge->capndx + 0x08, &tcmd);
tcmd &= ~(0x7 << 10);
tcmd &= ~0x7;
@@ -479,7 +479,7 @@ static int agp_3_0_node_enable(u32 mode,
tcmd |= 0x1 << 8;
tcmd |= rate;
- pci_write_config_dword(td, agp_bridge.capndx + 0x08, tcmd);
+ pci_write_config_dword(td, agp_bridge->capndx + 0x08, tcmd);
/*
* Set the target's advertised arqsz value, the minimum supported
@@ -525,11 +525,11 @@ get_out:
* (AGP 3.0 devices are required to operate as AGP 2.0 devices
* when not using 3.0 electricals.
*/
-int agp_generic_agp_3_0_enable(u32 mode)
+void agp_generic_agp_3_0_enable(u32 mode)
{
u32 ncapid, major, minor, agp_3_0;
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx, &ncapid);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx, &ncapid);
major = (ncapid >> 20) & 0xf;
minor = (ncapid >> 16) & 0xf;
@@ -537,16 +537,13 @@ int agp_generic_agp_3_0_enable(u32 mode)
printk(KERN_INFO PFX "Found an AGP %d.%d compliant device.\n",major, minor);
if(major >= 3) {
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx + 0x4, &agp_3_0);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + 0x4, &agp_3_0);
/*
* Check to see if we are operating in 3.0 mode
*/
- if((agp_3_0 >> 3) & 0x1) {
+ if((agp_3_0 >> 3) & 0x1)
agp_3_0_node_enable(mode, minor);
- return TRUE;
- }
}
- return FALSE;
}
EXPORT_SYMBOL(agp_generic_agp_3_0_enable);
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/agp/generic.c linux-2.5/drivers/char/agp/generic.c
--- linux-2.5.60/drivers/char/agp/generic.c 2003-02-10 17:38:18.000000000 -0100
+++ linux-2.5/drivers/char/agp/generic.c 2003-02-10 19:30:03.000000000 -0100
@@ -52,16 +52,16 @@ void agp_free_key(int key)
return;
if (key < MAXKEY)
- clear_bit(key, agp_bridge.key_list);
+ clear_bit(key, agp_bridge->key_list);
}
static int agp_get_key(void)
{
int bit;
- bit = find_first_zero_bit(agp_bridge.key_list, MAXKEY);
+ bit = find_first_zero_bit(agp_bridge->key_list, MAXKEY);
if (bit < MAXKEY) {
- set_bit(bit, agp_bridge.key_list);
+ set_bit(bit, agp_bridge->key_list);
return bit;
}
return -1;
@@ -96,21 +96,21 @@ agp_memory *agp_create_memory(int scratc
void agp_free_memory(agp_memory * curr)
{
- int i;
+ size_t i;
- if ((agp_bridge.type == NOT_SUPPORTED) || (curr == NULL))
+ if ((agp_bridge->type == NOT_SUPPORTED) || (curr == NULL))
return;
if (curr->is_bound == TRUE)
agp_unbind_memory(curr);
if (curr->type != 0) {
- agp_bridge.free_by_type(curr);
+ agp_bridge->free_by_type(curr);
return;
}
if (curr->page_count != 0) {
for (i = 0; i < curr->page_count; i++) {
- agp_bridge.agp_destroy_page(phys_to_virt(curr->memory[i]));
+ agp_bridge->agp_destroy_page(phys_to_virt(curr->memory[i]));
}
}
agp_free_key(curr->key);
@@ -124,16 +124,16 @@ agp_memory *agp_allocate_memory(size_t p
{
int scratch_pages;
agp_memory *new;
- int i;
+ size_t i;
- if (agp_bridge.type == NOT_SUPPORTED)
+ if (agp_bridge->type == NOT_SUPPORTED)
return NULL;
- if ((atomic_read(&agp_bridge.current_memory_agp) + page_count) > agp_bridge.max_memory_agp)
+ if ((atomic_read(&agp_bridge->current_memory_agp) + page_count) > agp_bridge->max_memory_agp)
return NULL;
if (type != 0) {
- new = agp_bridge.alloc_by_type(page_count, type);
+ new = agp_bridge->alloc_by_type(page_count, type);
return new;
}
@@ -145,7 +145,7 @@ agp_memory *agp_allocate_memory(size_t p
return NULL;
for (i = 0; i < page_count; i++) {
- void *addr = agp_bridge.agp_alloc_page();
+ void *addr = agp_bridge->agp_alloc_page();
if (addr == NULL) {
agp_free_memory(new);
@@ -167,9 +167,9 @@ static int agp_return_size(void)
int current_size;
void *temp;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
- switch (agp_bridge.size_type) {
+ switch (agp_bridge->size_type) {
case U8_APER_SIZE:
current_size = A_SIZE_8(temp)->size;
break;
@@ -201,9 +201,9 @@ int agp_num_entries(void)
int num_entries;
void *temp;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
- switch (agp_bridge.size_type) {
+ switch (agp_bridge->size_type) {
case U8_APER_SIZE:
num_entries = A_SIZE_8(temp)->num_entries;
break;
@@ -235,20 +235,21 @@ int agp_num_entries(void)
int agp_copy_info(agp_kern_info * info)
{
memset(info, 0, sizeof(agp_kern_info));
- if (agp_bridge.type == NOT_SUPPORTED) {
- info->chipset = agp_bridge.type;
+ if (agp_bridge->type == NOT_SUPPORTED) {
+ info->chipset = agp_bridge->type;
return -EIO;
}
- info->version.major = agp_bridge.version->major;
- info->version.minor = agp_bridge.version->minor;
- info->device = agp_bridge.dev;
- info->chipset = agp_bridge.type;
- info->mode = agp_bridge.mode;
- info->aper_base = agp_bridge.gart_bus_addr;
+ info->version.major = agp_bridge->version->major;
+ info->version.minor = agp_bridge->version->minor;
+ info->device = agp_bridge->dev;
+ info->chipset = agp_bridge->type;
+ info->mode = agp_bridge->mode;
+ info->aper_base = agp_bridge->gart_bus_addr;
info->aper_size = agp_return_size();
- info->max_memory = agp_bridge.max_memory_agp;
- info->current_memory = atomic_read(&agp_bridge.current_memory_agp);
- info->cant_use_aperture = agp_bridge.cant_use_aperture;
+ info->max_memory = agp_bridge->max_memory_agp;
+ info->current_memory = atomic_read(&agp_bridge->current_memory_agp);
+ info->cant_use_aperture = agp_bridge->cant_use_aperture;
+ info->vm_ops = agp_bridge->vm_ops;
info->page_mask = ~0UL;
return 0;
}
@@ -265,7 +266,7 @@ int agp_bind_memory(agp_memory * curr, o
{
int ret_val;
- if ((agp_bridge.type == NOT_SUPPORTED) ||
+ if ((agp_bridge->type == NOT_SUPPORTED) ||
(curr == NULL) || (curr->is_bound == TRUE)) {
return -EINVAL;
}
@@ -273,7 +274,7 @@ int agp_bind_memory(agp_memory * curr, o
CACHE_FLUSH();
curr->is_flushed = TRUE;
}
- ret_val = agp_bridge.insert_memory(curr, pg_start, curr->type);
+ ret_val = agp_bridge->insert_memory(curr, pg_start, curr->type);
if (ret_val != 0)
return ret_val;
@@ -287,13 +288,13 @@ int agp_unbind_memory(agp_memory * curr)
{
int ret_val;
- if ((agp_bridge.type == NOT_SUPPORTED) || (curr == NULL))
+ if ((agp_bridge->type == NOT_SUPPORTED) || (curr == NULL))
return -EINVAL;
if (curr->is_bound != TRUE)
return -EINVAL;
- ret_val = agp_bridge.remove_memory(curr, curr->pg_start, curr->type);
+ ret_val = agp_bridge->remove_memory(curr, curr->pg_start, curr->type);
if (ret_val != 0)
return ret_val;
@@ -395,15 +396,15 @@ void agp_generic_agp_enable(u32 mode)
{
u32 command;
- pci_read_config_dword(agp_bridge.dev,
- agp_bridge.capndx + PCI_AGP_STATUS,
+ pci_read_config_dword(agp_bridge->dev,
+ agp_bridge->capndx + PCI_AGP_STATUS,
&command);
command = agp_collect_device_status(mode, command);
command |= 0x100;
- pci_write_config_dword(agp_bridge.dev,
- agp_bridge.capndx + PCI_AGP_COMMAND,
+ pci_write_config_dword(agp_bridge->dev,
+ agp_bridge->capndx + PCI_AGP_COMMAND,
command);
agp_device_command(command, 0);
@@ -421,17 +422,17 @@ int agp_generic_create_gatt_table(void)
struct page *page;
/* The generic routines can't handle 2 level gatt's */
- if (agp_bridge.size_type == LVL2_APER_SIZE)
+ if (agp_bridge->size_type == LVL2_APER_SIZE)
return -EINVAL;
table = NULL;
- i = agp_bridge.aperture_size_idx;
- temp = agp_bridge.current_size;
+ i = agp_bridge->aperture_size_idx;
+ temp = agp_bridge->current_size;
size = page_order = num_entries = 0;
- if (agp_bridge.size_type != FIXED_APER_SIZE) {
+ if (agp_bridge->size_type != FIXED_APER_SIZE) {
do {
- switch (agp_bridge.size_type) {
+ switch (agp_bridge->size_type) {
case U8_APER_SIZE:
size = A_SIZE_8(temp)->size;
page_order =
@@ -462,15 +463,15 @@ int agp_generic_create_gatt_table(void)
if (table == NULL) {
i++;
- switch (agp_bridge.size_type) {
+ switch (agp_bridge->size_type) {
case U8_APER_SIZE:
- agp_bridge.current_size = A_IDX8();
+ agp_bridge->current_size = A_IDX8();
break;
case U16_APER_SIZE:
- agp_bridge.current_size = A_IDX16();
+ agp_bridge->current_size = A_IDX16();
break;
case U32_APER_SIZE:
- agp_bridge.current_size = A_IDX32();
+ agp_bridge->current_size = A_IDX32();
break;
/* This case will never really
* happen.
@@ -478,15 +479,15 @@ int agp_generic_create_gatt_table(void)
case FIXED_APER_SIZE:
case LVL2_APER_SIZE:
default:
- agp_bridge.current_size =
- agp_bridge.current_size;
+ agp_bridge->current_size =
+ agp_bridge->current_size;
break;
}
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
} else {
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->aperture_size_idx = i;
}
- } while ((table == NULL) && (i < agp_bridge.num_aperture_sizes));
+ } while ((table == NULL) && (i < agp_bridge->num_aperture_sizes));
} else {
size = ((struct aper_size_info_fixed *) temp)->size;
page_order = ((struct aper_size_info_fixed *) temp)->page_order;
@@ -502,14 +503,14 @@ int agp_generic_create_gatt_table(void)
for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
SetPageReserved(page);
- agp_bridge.gatt_table_real = (u32 *) table;
+ agp_bridge->gatt_table_real = (u32 *) table;
agp_gatt_table = (void *)table;
CACHE_FLUSH();
- agp_bridge.gatt_table = ioremap_nocache(virt_to_phys(table),
+ agp_bridge->gatt_table = ioremap_nocache(virt_to_phys(table),
(PAGE_SIZE * (1 << page_order)));
CACHE_FLUSH();
- if (agp_bridge.gatt_table == NULL) {
+ if (agp_bridge->gatt_table == NULL) {
for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
ClearPageReserved(page);
@@ -517,11 +518,11 @@ int agp_generic_create_gatt_table(void)
return -ENOMEM;
}
- agp_bridge.gatt_bus_addr = virt_to_phys(agp_bridge.gatt_table_real);
+ agp_bridge->gatt_bus_addr = virt_to_phys(agp_bridge->gatt_table_real);
/* AK: bogus, should encode addresses > 4GB */
for (i = 0; i < num_entries; i++)
- agp_bridge.gatt_table[i] = (unsigned long) agp_bridge.scratch_page;
+ agp_bridge->gatt_table[i] = (unsigned long) agp_bridge->scratch_page;
return 0;
}
@@ -543,9 +544,9 @@ int agp_generic_free_gatt_table(void)
void *temp;
struct page *page;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
- switch (agp_bridge.size_type) {
+ switch (agp_bridge->size_type) {
case U8_APER_SIZE:
page_order = A_SIZE_8(temp)->page_order;
break;
@@ -572,25 +573,27 @@ int agp_generic_free_gatt_table(void)
* from the table.
*/
- iounmap(agp_bridge.gatt_table);
- table = (char *) agp_bridge.gatt_table_real;
+ iounmap(agp_bridge->gatt_table);
+ table = (char *) agp_bridge->gatt_table_real;
table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1);
for (page = virt_to_page(table); page <= virt_to_page(table_end); page++)
ClearPageReserved(page);
- free_pages((unsigned long) agp_bridge.gatt_table_real, page_order);
+ free_pages((unsigned long) agp_bridge->gatt_table_real, page_order);
return 0;
}
int agp_generic_insert_memory(agp_memory * mem, off_t pg_start, int type)
{
- int i, j, num_entries;
+ int num_entries;
+ size_t i;
+ off_t j;
void *temp;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
- switch (agp_bridge.size_type) {
+ switch (agp_bridge->size_type) {
case U8_APER_SIZE:
num_entries = A_SIZE_8(temp)->num_entries;
break;
@@ -627,7 +630,7 @@ int agp_generic_insert_memory(agp_memory
j = pg_start;
while (j < (pg_start + mem->page_count)) {
- if (!PGE_EMPTY(agp_bridge.gatt_table[j])) {
+ if (!PGE_EMPTY(agp_bridge->gatt_table[j])) {
return -EBUSY;
}
j++;
@@ -639,16 +642,16 @@ int agp_generic_insert_memory(agp_memory
}
for (i = 0, j = pg_start; i < mem->page_count; i++, j++)
- agp_bridge.gatt_table[j] =
- agp_bridge.mask_memory(mem->memory[i], mem->type);
+ agp_bridge->gatt_table[j] =
+ agp_bridge->mask_memory(mem->memory[i], mem->type);
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
int agp_generic_remove_memory(agp_memory * mem, off_t pg_start, int type)
{
- int i;
+ size_t i;
if (type != 0 || mem->type != 0) {
/* The generic routines know nothing of memory types */
@@ -657,11 +660,11 @@ int agp_generic_remove_memory(agp_memory
/* AK: bogus, should encode addresses > 4GB */
for (i = pg_start; i < (mem->page_count + pg_start); i++) {
- agp_bridge.gatt_table[i] =
- (unsigned long) agp_bridge.scratch_page;
+ agp_bridge->gatt_table[i] =
+ (unsigned long) agp_bridge->scratch_page;
}
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
@@ -700,7 +703,7 @@ void *agp_generic_alloc_page(void)
get_page(page);
SetPageLocked(page);
- atomic_inc(&agp_bridge.current_memory_agp);
+ atomic_inc(&agp_bridge->current_memory_agp);
return page_address(page);
}
@@ -716,16 +719,16 @@ void agp_generic_destroy_page(void *addr
put_page(page);
unlock_page(page);
free_page((unsigned long)addr);
- atomic_dec(&agp_bridge.current_memory_agp);
+ atomic_dec(&agp_bridge->current_memory_agp);
}
/* End Basic Page Allocation Routines */
void agp_enable(u32 mode)
{
- if (agp_bridge.type == NOT_SUPPORTED)
+ if (agp_bridge->type == NOT_SUPPORTED)
return;
- agp_bridge.agp_enable(mode);
+ agp_bridge->agp_enable(mode);
}
EXPORT_SYMBOL(agp_free_memory);
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/agp/hp-agp.c linux-2.5/drivers/char/agp/hp-agp.c
--- linux-2.5.60/drivers/char/agp/hp-agp.c 2003-02-10 17:38:49.000000000 -0100
+++ linux-2.5/drivers/char/agp/hp-agp.c 2003-02-10 19:30:03.000000000 -0100
@@ -176,7 +176,7 @@ static int hp_zx1_fetch_size(void)
size = hp_private.gart_size / MB(1);
hp_zx1_sizes[0].size = size;
- agp_bridge.current_size = (void *) &hp_zx1_sizes[0];
+ agp_bridge->current_size = (void *) &hp_zx1_sizes[0];
return size;
}
@@ -184,10 +184,10 @@ static int hp_zx1_configure(void)
{
struct _hp_private *hp = &hp_private;
- agp_bridge.gart_bus_addr = hp->gart_base;
- agp_bridge.capndx = pci_find_capability(agp_bridge.dev, PCI_CAP_ID_AGP);
- pci_read_config_dword(agp_bridge.dev,
- agp_bridge.capndx + PCI_AGP_STATUS, &agp_bridge.mode);
+ agp_bridge->gart_bus_addr = hp->gart_base;
+ agp_bridge->capndx = pci_find_capability(agp_bridge->dev, PCI_CAP_ID_AGP);
+ pci_read_config_dword(agp_bridge->dev,
+ agp_bridge->capndx + PCI_AGP_STATUS, &agp_bridge->mode);
if (hp->io_pdir_owner) {
OUTREG64(hp->registers, HP_ZX1_PDIR_BASE,
@@ -241,7 +241,7 @@ static int hp_zx1_create_gatt_table(void
}
for (i = 0; i < hp->gatt_entries; i++) {
- hp->gatt[i] = (unsigned long) agp_bridge.scratch_page;
+ hp->gatt[i] = (unsigned long) agp_bridge->scratch_page;
}
return 0;
@@ -296,11 +296,11 @@ static int hp_zx1_insert_memory(agp_memo
for (k = 0;
k < hp->io_pages_per_kpage;
k++, j++, paddr += hp->io_page_size) {
- hp->gatt[j] = agp_bridge.mask_memory(paddr, type);
+ hp->gatt[j] = agp_bridge->mask_memory(paddr, type);
}
}
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
@@ -316,10 +316,10 @@ static int hp_zx1_remove_memory(agp_memo
io_pg_start = hp->io_pages_per_kpage * pg_start;
io_pg_count = hp->io_pages_per_kpage * mem->page_count;
for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) {
- hp->gatt[i] = agp_bridge.scratch_page;
+ hp->gatt[i] = agp_bridge->scratch_page;
}
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
@@ -330,39 +330,39 @@ static unsigned long hp_zx1_mask_memory(
static int __init hp_zx1_setup (struct pci_dev *pdev __attribute__((unused)))
{
- agp_bridge.masks = hp_zx1_masks;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.size_type = FIXED_APER_SIZE;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = hp_zx1_configure;
- agp_bridge.fetch_size = hp_zx1_fetch_size;
- agp_bridge.cleanup = hp_zx1_cleanup;
- agp_bridge.tlb_flush = hp_zx1_tlbflush;
- agp_bridge.mask_memory = hp_zx1_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = hp_zx1_create_gatt_table;
- agp_bridge.free_gatt_table = hp_zx1_free_gatt_table;
- agp_bridge.insert_memory = hp_zx1_insert_memory;
- agp_bridge.remove_memory = hp_zx1_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.cant_use_aperture = 1;
+ agp_bridge->masks = hp_zx1_masks;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->size_type = FIXED_APER_SIZE;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = hp_zx1_configure;
+ agp_bridge->fetch_size = hp_zx1_fetch_size;
+ agp_bridge->cleanup = hp_zx1_cleanup;
+ agp_bridge->tlb_flush = hp_zx1_tlbflush;
+ agp_bridge->mask_memory = hp_zx1_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = hp_zx1_create_gatt_table;
+ agp_bridge->free_gatt_table = hp_zx1_free_gatt_table;
+ agp_bridge->insert_memory = hp_zx1_insert_memory;
+ agp_bridge->remove_memory = hp_zx1_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->cant_use_aperture = 1;
return hp_zx1_ioc_init();
}
static int __init agp_find_supported_device(struct pci_dev *dev)
{
- agp_bridge.dev = dev;
+ agp_bridge->dev = dev;
/* ZX1 LBAs can be either PCI or AGP bridges */
if (pci_find_capability(dev, PCI_CAP_ID_AGP)) {
printk(KERN_INFO PFX "Detected HP ZX1 AGP chipset at %s\n",
dev->slot_name);
- agp_bridge.type = HP_ZX1;
- agp_bridge.dev = dev;
+ agp_bridge->type = HP_ZX1;
+ agp_bridge->dev = dev;
return hp_zx1_setup(dev);
}
return -ENODEV;
@@ -408,7 +408,7 @@ static int __init agp_hp_init(void)
ret_val = pci_module_init(&agp_hp_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/agp/i460-agp.c linux-2.5/drivers/char/agp/i460-agp.c
--- linux-2.5.60/drivers/char/agp/i460-agp.c 2003-02-10 17:38:43.000000000 -0100
+++ linux-2.5/drivers/char/agp/i460-agp.c 2003-02-10 19:30:03.000000000 -0100
@@ -96,7 +96,7 @@ static int i460_fetch_size (void)
struct aper_size_info_8 *values;
/* Determine the GART page size */
- pci_read_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL, &temp);
+ pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &temp);
i460.io_page_shift = (temp & I460_4M_PS) ? 22 : 12;
pr_debug("i460_fetch_size: io_page_shift=%d\n", i460.io_page_shift);
@@ -107,9 +107,9 @@ static int i460_fetch_size (void)
return 0;
}
- values = A_SIZE_8(agp_bridge.aperture_sizes);
+ values = A_SIZE_8(agp_bridge->aperture_sizes);
- pci_read_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ, &temp);
+ pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp);
/* Exit now if the IO drivers for the GART SRAMS are turned off */
if (temp & I460_SRAM_IO_DISABLE) {
@@ -130,7 +130,7 @@ static int i460_fetch_size (void)
else
i460.dynamic_apbase = INTEL_I460_APBASE;
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
/*
* Dynamically calculate the proper num_entries and page_order values for
* the define aperture sizes. Take care not to shift off the end of
@@ -140,11 +140,11 @@ static int i460_fetch_size (void)
values[i].page_order = log2((sizeof(u32)*values[i].num_entries) >> PAGE_SHIFT);
}
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
/* Neglect control bits when matching up size_value */
if ((temp & I460_AGPSIZ_MASK) == values[i].size_value) {
- agp_bridge.previous_size = agp_bridge.current_size = (void *) (values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
@@ -166,8 +166,8 @@ static void i460_write_agpsiz (u8 size_v
{
u8 temp;
- pci_read_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ, &temp);
- pci_write_config_byte(agp_bridge.dev, INTEL_I460_AGPSIZ,
+ pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp);
+ pci_write_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ,
((temp & ~I460_AGPSIZ_MASK) | size_value));
}
@@ -175,7 +175,7 @@ static void i460_cleanup (void)
{
struct aper_size_info_8 *previous_size;
- previous_size = A_SIZE_8(agp_bridge.previous_size);
+ previous_size = A_SIZE_8(agp_bridge->previous_size);
i460_write_agpsiz(previous_size->size_value);
if (I460_IO_PAGE_SHIFT > PAGE_SHIFT)
@@ -194,7 +194,7 @@ static int i460_configure (void)
temp.large = 0;
- current_size = A_SIZE_8(agp_bridge.current_size);
+ current_size = A_SIZE_8(agp_bridge->current_size);
i460_write_agpsiz(current_size->size_value);
/*
@@ -202,14 +202,14 @@ static int i460_configure (void)
* This has to be done since the AGP aperture can be above 4GB on
* 460 based systems.
*/
- pci_read_config_dword(agp_bridge.dev, i460.dynamic_apbase, &(temp.small[0]));
- pci_read_config_dword(agp_bridge.dev, i460.dynamic_apbase + 4, &(temp.small[1]));
+ pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase, &(temp.small[0]));
+ pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase + 4, &(temp.small[1]));
/* Clear BAR control bits */
- agp_bridge.gart_bus_addr = temp.large & ~((1UL << 3) - 1);
+ agp_bridge->gart_bus_addr = temp.large & ~((1UL << 3) - 1);
- pci_read_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL, &scratch);
- pci_write_config_byte(agp_bridge.dev, INTEL_I460_GXBCTL,
+ pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &scratch);
+ pci_write_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL,
(scratch & 0x02) | I460_GXBCTL_OOG | I460_GXBCTL_BWC);
/*
@@ -234,16 +234,16 @@ static int i460_create_gatt_table (void)
/*
* Load up the fixed address of the GART SRAMS which hold our GATT table.
*/
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
page_order = A_SIZE_8(temp)->page_order;
num_entries = A_SIZE_8(temp)->num_entries;
i460.gatt = ioremap(INTEL_I460_ATTBASE, PAGE_SIZE << page_order);
/* These are no good, the should be removed from the agp_bridge strucure... */
- agp_bridge.gatt_table_real = NULL;
- agp_bridge.gatt_table = NULL;
- agp_bridge.gatt_bus_addr = 0;
+ agp_bridge->gatt_table_real = NULL;
+ agp_bridge->gatt_table = NULL;
+ agp_bridge->gatt_bus_addr = 0;
for (i = 0; i < num_entries; ++i)
WR_GATT(i, 0);
@@ -256,7 +256,7 @@ static int i460_free_gatt_table (void)
int num_entries, i;
void *temp;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
num_entries = A_SIZE_8(temp)->num_entries;
@@ -284,7 +284,7 @@ static int i460_insert_memory_small_io_p
io_pg_start = I460_IOPAGES_PER_KPAGE * pg_start;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
num_entries = A_SIZE_8(temp)->num_entries;
if ((io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count) > num_entries) {
@@ -306,7 +306,7 @@ static int i460_insert_memory_small_io_p
for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
paddr = mem->memory[i];
for (k = 0; k < I460_IOPAGES_PER_KPAGE; k++, j++, paddr += io_page_size)
- WR_GATT(j, agp_bridge.mask_memory(paddr, mem->type));
+ WR_GATT(j, agp_bridge->mask_memory(paddr, mem->type));
}
WR_FLUSH_GATT(j - 1);
return 0;
@@ -364,7 +364,7 @@ static int i460_alloc_large_page (struct
lp->paddr = virt_to_phys(lpage);
lp->refcount = 0;
- atomic_add(I460_KPAGES_PER_IOPAGE, &agp_bridge.current_memory_agp);
+ atomic_add(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp);
return 0;
}
@@ -374,7 +374,7 @@ static void i460_free_large_page (struct
lp->alloced_map = NULL;
free_pages((unsigned long) phys_to_virt(lp->paddr), I460_IO_PAGE_SHIFT - PAGE_SHIFT);
- atomic_sub(I460_KPAGES_PER_IOPAGE, &agp_bridge.current_memory_agp);
+ atomic_sub(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp);
}
static int i460_insert_memory_large_io_page (agp_memory * mem, off_t pg_start, int type)
@@ -383,7 +383,7 @@ static int i460_insert_memory_large_io_p
struct lp_desc *start, *end, *lp;
void *temp;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
num_entries = A_SIZE_8(temp)->num_entries;
/* Figure out what pg_start means in terms of our large GART pages */
@@ -417,7 +417,7 @@ static int i460_insert_memory_large_io_p
if (i460_alloc_large_page(lp) < 0)
return -ENOMEM;
pg = lp - i460.lp_desc;
- WR_GATT(pg, agp_bridge.mask_memory(lp->paddr, 0));
+ WR_GATT(pg, agp_bridge->mask_memory(lp->paddr, 0));
WR_FLUSH_GATT(pg);
}
@@ -439,7 +439,7 @@ static int i460_remove_memory_large_io_p
struct lp_desc *start, *end, *lp;
void *temp;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
num_entries = A_SIZE_8(temp)->num_entries;
/* Figure out what pg_start means in terms of our large GART pages */
@@ -519,43 +519,43 @@ static void i460_destroy_page (void *pag
static unsigned long i460_mask_memory (unsigned long addr, int type)
{
/* Make sure the returned address is a valid GATT entry */
- return (agp_bridge.masks[0].mask
+ return (agp_bridge->masks[0].mask
| (((addr & ~((1 << I460_IO_PAGE_SHIFT) - 1)) & 0xffffff000) >> 12));
}
static int __init intel_i460_setup (struct pci_dev *pdev __attribute__((unused)))
{
- agp_bridge.masks = i460_masks;
- agp_bridge.aperture_sizes = (void *) i460_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 3;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = i460_configure;
- agp_bridge.fetch_size = i460_fetch_size;
- agp_bridge.cleanup = i460_cleanup;
- agp_bridge.tlb_flush = i460_tlb_flush;
- agp_bridge.mask_memory = i460_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = i460_create_gatt_table;
- agp_bridge.free_gatt_table = i460_free_gatt_table;
+ agp_bridge->masks = i460_masks;
+ agp_bridge->aperture_sizes = (void *) i460_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 3;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = i460_configure;
+ agp_bridge->fetch_size = i460_fetch_size;
+ agp_bridge->cleanup = i460_cleanup;
+ agp_bridge->tlb_flush = i460_tlb_flush;
+ agp_bridge->mask_memory = i460_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = i460_create_gatt_table;
+ agp_bridge->free_gatt_table = i460_free_gatt_table;
#if I460_LARGE_IO_PAGES
- agp_bridge.insert_memory = i460_insert_memory;
- agp_bridge.remove_memory = i460_remove_memory;
- agp_bridge.agp_alloc_page = i460_alloc_page;
- agp_bridge.agp_destroy_page = i460_destroy_page;
+ agp_bridge->insert_memory = i460_insert_memory;
+ agp_bridge->remove_memory = i460_remove_memory;
+ agp_bridge->agp_alloc_page = i460_alloc_page;
+ agp_bridge->agp_destroy_page = i460_destroy_page;
#else
- agp_bridge.insert_memory = i460_insert_memory_small_io_page;
- agp_bridge.remove_memory = i460_remove_memory_small_io_page;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->insert_memory = i460_insert_memory_small_io_page;
+ agp_bridge->remove_memory = i460_remove_memory_small_io_page;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
#endif
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 1;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 1;
return 0;
}
@@ -571,8 +571,8 @@ static int __init agp_intel_i460_probe (
if (cap_ptr == 0)
return -ENODEV;
- agp_bridge.dev = dev;
- agp_bridge.capndx = cap_ptr;
+ agp_bridge->dev = dev;
+ agp_bridge->capndx = cap_ptr;
intel_i460_setup(dev);
i460_agp_driver.dev = dev;
agp_register_driver(&i460_agp_driver);
@@ -605,7 +605,7 @@ static int __init agp_intel_i460_init(vo
ret_val = pci_module_init(&agp_intel_i460_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/agp/i7x05-agp.c linux-2.5/drivers/char/agp/i7x05-agp.c
--- linux-2.5.60/drivers/char/agp/i7x05-agp.c 2003-02-10 17:37:58.000000000 -0100
+++ linux-2.5/drivers/char/agp/i7x05-agp.c 2003-02-10 19:30:03.000000000 -0100
@@ -13,16 +13,16 @@ static int intel_7505_fetch_size(void)
/*
* For AGP 3.0 APSIZE is now 16 bits
*/
- pci_read_config_word (agp_bridge.dev, INTEL_I7505_APSIZE, &tmp);
+ pci_read_config_word (agp_bridge->dev, INTEL_I7505_APSIZE, &tmp);
tmp = (tmp & 0xfff);
- values = A_SIZE_16(agp_bridge.aperture_sizes);
+ values = A_SIZE_16(agp_bridge->aperture_sizes);
- for (i=0; i < agp_bridge.num_aperture_sizes; i++) {
+ for (i=0; i < agp_bridge->num_aperture_sizes; i++) {
if (tmp == values[i].size_value) {
- agp_bridge.previous_size = agp_bridge.current_size =
+ agp_bridge->previous_size = agp_bridge->current_size =
(void *)(values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
@@ -33,18 +33,18 @@ static int intel_7505_fetch_size(void)
static void intel_7505_tlbflush(agp_memory *mem)
{
u32 temp;
- pci_read_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, &temp);
- pci_write_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, temp & ~(1 << 7));
- pci_read_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, &temp);
- pci_write_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, temp | (1 << 7));
+ pci_read_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, &temp);
+ pci_write_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, temp & ~(1 << 7));
+ pci_read_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, &temp);
+ pci_write_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, temp | (1 << 7));
}
static void intel_7505_cleanup(void)
{
aper_size_info_16 *previous_size;
- previous_size = A_SIZE_16(agp_bridge.previous_size);
- pci_write_config_byte(agp_bridge.dev, INTEL_I7505_APSIZE,
+ previous_size = A_SIZE_16(agp_bridge->previous_size);
+ pci_write_config_byte(agp_bridge->dev, INTEL_I7505_APSIZE,
previous_size->size_value);
}
@@ -54,25 +54,25 @@ static int intel_7505_configure(void)
u32 temp;
aper_size_info_16 *current_size;
- current_size = A_SIZE_16(agp_bridge.current_size);
+ current_size = A_SIZE_16(agp_bridge->current_size);
/* aperture size */
- pci_write_config_word(agp_bridge.dev, INTEL_I7505_APSIZE,
+ pci_write_config_word(agp_bridge->dev, INTEL_I7505_APSIZE,
current_size->size_value);
/* address to map to */
- pci_read_config_dword(agp_bridge.dev, INTEL_I7505_NAPBASELO, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, INTEL_I7505_NAPBASELO, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase */
- pci_write_config_dword(agp_bridge.dev, INTEL_I7505_ATTBASE,
- agp_bridge.gatt_bus_addr);
+ pci_write_config_dword(agp_bridge->dev, INTEL_I7505_ATTBASE,
+ agp_bridge->gatt_bus_addr);
/* agpctrl */
- pci_write_config_dword(agp_bridge.dev, INTEL_I7505_AGPCTRL, 0x0000);
+ pci_write_config_dword(agp_bridge->dev, INTEL_I7505_AGPCTRL, 0x0000);
/* clear error registers */
- pci_write_config_byte(agp_bridge.dev, INTEL_I7505_ERRSTS, 0xff);
+ pci_write_config_byte(agp_bridge->dev, INTEL_I7505_ERRSTS, 0xff);
return 0;
}
@@ -95,30 +95,30 @@ static void i7505_setup (u32 mode)
static int __init intel_7505_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = intel_generic_masks;
- agp_bridge.aperture_sizes = (void *) intel_7505_sizes;
- agp_bridge.size_type = U16_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = intel_7505_configure;
- agp_bridge.fetch_size = intel_7505_fetch_size;
- agp_bridge.cleanup = intel_7505_cleanup;
- agp_bridge.tlb_flush = intel_7505_tlbflush;
- agp_bridge.mask_memory = intel_mask_memory;
- agp_bridge.agp_enable = i7505_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_generic_masks;
+ agp_bridge->aperture_sizes = (void *) intel_7505_sizes;
+ agp_bridge->size_type = U16_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = intel_7505_configure;
+ agp_bridge->fetch_size = intel_7505_fetch_size;
+ agp_bridge->cleanup = intel_7505_cleanup;
+ agp_bridge->tlb_flush = intel_7505_tlbflush;
+ agp_bridge->mask_memory = intel_mask_memory;
+ agp_bridge->agp_enable = i7505_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
@@ -149,7 +149,7 @@ static int __init agp_lookup_host_bridge
if (pdev->device == devs[j].device_id) {
printk (KERN_INFO PFX "Detected Intel %s chipset\n",
devs[j].chipset_name);
- agp_bridge.type = devs[j].chipset;
+ agp_bridge->type = devs[j].chipset;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
@@ -177,10 +177,10 @@ static int __init agp_i7x05_probe (struc
return -ENODEV;
if (agp_lookup_host_bridge(dev) != -ENODEV) {
- agp_bridge.dev = dev;
- agp_bridge.capndx = cap_ptr;
+ agp_bridge->dev = dev;
+ agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode)
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode)
i7x05_agp_driver.dev = dev;
agp_register_driver(&i7x05_agp_driver);
return 0;
@@ -215,7 +215,7 @@ int __init agp_i7x05_init(void)
ret_val = pci_module_init(&agp_i7x05_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/agp/intel-agp.c linux-2.5/drivers/char/agp/intel-agp.c
--- linux-2.5.60/drivers/char/agp/intel-agp.c 2003-02-10 17:38:36.000000000 -0100
+++ linux-2.5/drivers/char/agp/intel-agp.c 2003-02-10 19:30:03.000000000 -0100
@@ -39,22 +39,22 @@ static int intel_i810_fetch_size(void)
u32 smram_miscc;
struct aper_size_info_fixed *values;
- pci_read_config_dword(agp_bridge.dev, I810_SMRAM_MISCC, &smram_miscc);
- values = A_SIZE_FIX(agp_bridge.aperture_sizes);
+ pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
+ values = A_SIZE_FIX(agp_bridge->aperture_sizes);
if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
printk(KERN_WARNING PFX "i810 is disabled\n");
return 0;
}
if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
- agp_bridge.previous_size =
- agp_bridge.current_size = (void *) (values + 1);
- agp_bridge.aperture_size_idx = 1;
+ agp_bridge->previous_size =
+ agp_bridge->current_size = (void *) (values + 1);
+ agp_bridge->aperture_size_idx = 1;
return values[1].size;
} else {
- agp_bridge.previous_size =
- agp_bridge.current_size = (void *) (values);
- agp_bridge.aperture_size_idx = 0;
+ agp_bridge->previous_size =
+ agp_bridge->current_size = (void *) (values);
+ agp_bridge->aperture_size_idx = 0;
return values[0].size;
}
@@ -67,7 +67,7 @@ static int intel_i810_configure(void)
u32 temp;
int i;
- current_size = A_SIZE_FIX(agp_bridge.current_size);
+ current_size = A_SIZE_FIX(agp_bridge->current_size);
pci_read_config_dword(intel_i810_private.i810_dev, I810_MMADDR, &temp);
temp &= 0xfff80000;
@@ -81,16 +81,16 @@ static int intel_i810_configure(void)
intel_i810_private.num_dcache_entries = 1024;
}
pci_read_config_dword(intel_i810_private.i810_dev, I810_GMADDR, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
OUTREG32(intel_i810_private.registers, I810_PGETBL_CTL,
- agp_bridge.gatt_bus_addr | I810_PGETBL_ENABLED);
+ agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED);
CACHE_FLUSH();
- if (agp_bridge.needs_scratch_page == TRUE) {
+ if (agp_bridge->needs_scratch_page == TRUE) {
for (i = 0; i < current_size->num_entries; i++) {
OUTREG32(intel_i810_private.registers,
I810_PTE_BASE + (i * 4),
- agp_bridge.scratch_page);
+ agp_bridge->scratch_page);
}
}
return 0;
@@ -118,14 +118,14 @@ static int intel_i810_insert_entries(agp
int i, j, num_entries;
void *temp;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
num_entries = A_SIZE_FIX(temp)->num_entries;
if ((pg_start + mem->page_count) > num_entries) {
return -EINVAL;
}
for (j = pg_start; j < (pg_start + mem->page_count); j++) {
- if (!PGE_EMPTY(agp_bridge.gatt_table[j])) {
+ if (!PGE_EMPTY(agp_bridge->gatt_table[j])) {
return -EBUSY;
}
}
@@ -141,7 +141,7 @@ static int intel_i810_insert_entries(agp
I810_PTE_VALID);
}
CACHE_FLUSH();
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
if((type == AGP_PHYS_MEMORY) && (mem->type == AGP_PHYS_MEMORY))
@@ -154,11 +154,11 @@ insert:
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
OUTREG32(intel_i810_private.registers,
I810_PTE_BASE + (j * 4),
- agp_bridge.mask_memory(mem->memory[i], mem->type));
+ agp_bridge->mask_memory(mem->memory[i], mem->type));
}
CACHE_FLUSH();
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
@@ -170,11 +170,11 @@ static int intel_i810_remove_entries(agp
for (i = pg_start; i < (mem->page_count + pg_start); i++) {
OUTREG32(intel_i810_private.registers,
I810_PTE_BASE + (i * 4),
- agp_bridge.scratch_page);
+ agp_bridge->scratch_page);
}
CACHE_FLUSH();
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
@@ -211,7 +211,7 @@ static agp_memory *intel_i810_alloc_by_t
if (new == NULL)
return NULL;
- addr = agp_bridge.agp_alloc_page();
+ addr = agp_bridge->agp_alloc_page();
if (addr == NULL) {
/* Free this structure */
@@ -232,7 +232,7 @@ static void intel_i810_free_by_type(agp_
{
agp_free_key(curr->key);
if(curr->type == AGP_PHYS_MEMORY) {
- agp_bridge.agp_destroy_page(phys_to_virt(curr->memory[0]));
+ agp_bridge->agp_destroy_page(phys_to_virt(curr->memory[0]));
vfree(curr->memory);
}
kfree(curr);
@@ -241,37 +241,37 @@ static void intel_i810_free_by_type(agp_
static unsigned long intel_i810_mask_memory(unsigned long addr, int type)
{
/* Type checking must be done elsewhere */
- return addr | agp_bridge.masks[type].mask;
+ return addr | agp_bridge->masks[type].mask;
}
static int __init intel_i810_setup(struct pci_dev *i810_dev)
{
intel_i810_private.i810_dev = i810_dev;
- agp_bridge.masks = intel_i810_masks;
- agp_bridge.aperture_sizes = (void *) intel_i810_sizes;
- agp_bridge.size_type = FIXED_APER_SIZE;
- agp_bridge.num_aperture_sizes = 2;
- agp_bridge.dev_private_data = (void *) &intel_i810_private;
- agp_bridge.needs_scratch_page = TRUE;
- agp_bridge.configure = intel_i810_configure;
- agp_bridge.fetch_size = intel_i810_fetch_size;
- agp_bridge.cleanup = intel_i810_cleanup;
- agp_bridge.tlb_flush = intel_i810_tlbflush;
- agp_bridge.mask_memory = intel_i810_mask_memory;
- agp_bridge.agp_enable = intel_i810_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = intel_i810_insert_entries;
- agp_bridge.remove_memory = intel_i810_remove_entries;
- agp_bridge.alloc_by_type = intel_i810_alloc_by_type;
- agp_bridge.free_by_type = intel_i810_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_i810_masks;
+ agp_bridge->aperture_sizes = (void *) intel_i810_sizes;
+ agp_bridge->size_type = FIXED_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 2;
+ agp_bridge->dev_private_data = (void *) &intel_i810_private;
+ agp_bridge->needs_scratch_page = TRUE;
+ agp_bridge->configure = intel_i810_configure;
+ agp_bridge->fetch_size = intel_i810_fetch_size;
+ agp_bridge->cleanup = intel_i810_cleanup;
+ agp_bridge->tlb_flush = intel_i810_tlbflush;
+ agp_bridge->mask_memory = intel_i810_mask_memory;
+ agp_bridge->agp_enable = intel_i810_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = intel_i810_insert_entries;
+ agp_bridge->remove_memory = intel_i810_remove_entries;
+ agp_bridge->alloc_by_type = intel_i810_alloc_by_type;
+ agp_bridge->free_by_type = intel_i810_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
@@ -296,7 +296,7 @@ static void intel_i830_init_gtt_entries(
u8 rdct;
static const int ddt[4] = { 0, 16, 32, 64 };
- pci_read_config_word(agp_bridge.dev,I830_GMCH_CTRL,&gmch_ctrl);
+ pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
case I830_GMCH_GMS_STOLEN_512:
@@ -337,10 +337,10 @@ static int intel_i830_create_gatt_table(
int num_entries;
u32 temp;
- size = agp_bridge.current_size;
+ size = agp_bridge->current_size;
page_order = size->page_order;
num_entries = size->num_entries;
- agp_bridge.gatt_table_real = 0;
+ agp_bridge->gatt_table_real = 0;
pci_read_config_dword(intel_i830_private.i830_dev,I810_MMADDR,&temp);
temp &= 0xfff80000;
@@ -354,9 +354,9 @@ static int intel_i830_create_gatt_table(
/* we have to call this as early as possible after the MMIO base address is known */
intel_i830_init_gtt_entries();
- agp_bridge.gatt_table = NULL;
+ agp_bridge->gatt_table = NULL;
- agp_bridge.gatt_bus_addr = temp;
+ agp_bridge->gatt_bus_addr = temp;
return(0);
}
@@ -374,16 +374,16 @@ static int intel_i830_fetch_size(void)
u16 gmch_ctrl;
struct aper_size_info_fixed *values;
- pci_read_config_word(agp_bridge.dev,I830_GMCH_CTRL,&gmch_ctrl);
- values = A_SIZE_FIX(agp_bridge.aperture_sizes);
+ pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
+ values = A_SIZE_FIX(agp_bridge->aperture_sizes);
if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
- agp_bridge.previous_size = agp_bridge.current_size = (void *) values;
- agp_bridge.aperture_size_idx = 0;
+ agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
+ agp_bridge->aperture_size_idx = 0;
return(values[0].size);
} else {
- agp_bridge.previous_size = agp_bridge.current_size = (void *) values;
- agp_bridge.aperture_size_idx = 1;
+ agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
+ agp_bridge->aperture_size_idx = 1;
return(values[1].size);
}
@@ -397,21 +397,21 @@ static int intel_i830_configure(void)
u16 gmch_ctrl;
int i;
- current_size = A_SIZE_FIX(agp_bridge.current_size);
+ current_size = A_SIZE_FIX(agp_bridge->current_size);
pci_read_config_dword(intel_i830_private.i830_dev,I810_GMADDR,&temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
- pci_read_config_word(agp_bridge.dev,I830_GMCH_CTRL,&gmch_ctrl);
+ pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
gmch_ctrl |= I830_GMCH_ENABLED;
- pci_write_config_word(agp_bridge.dev,I830_GMCH_CTRL,gmch_ctrl);
+ pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
- OUTREG32(intel_i830_private.registers,I810_PGETBL_CTL,agp_bridge.gatt_bus_addr | I810_PGETBL_ENABLED);
+ OUTREG32(intel_i830_private.registers,I810_PGETBL_CTL,agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED);
CACHE_FLUSH();
- if (agp_bridge.needs_scratch_page == TRUE)
+ if (agp_bridge->needs_scratch_page == TRUE)
for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++)
- OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (i * 4),agp_bridge.scratch_page);
+ OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (i * 4),agp_bridge->scratch_page);
return (0);
}
@@ -426,7 +426,7 @@ static int intel_i830_insert_entries(agp
int i,j,num_entries;
void *temp;
- temp = agp_bridge.current_size;
+ temp = agp_bridge->current_size;
num_entries = A_SIZE_FIX(temp)->num_entries;
if (pg_start < intel_i830_private.gtt_entries) {
@@ -452,11 +452,11 @@ static int intel_i830_insert_entries(agp
for (i = 0, j = pg_start; i < mem->page_count; i++, j++)
OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (j * 4),
- agp_bridge.mask_memory(mem->memory[i], mem->type));
+ agp_bridge->mask_memory(mem->memory[i], mem->type));
CACHE_FLUSH();
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return(0);
}
@@ -473,11 +473,11 @@ static int intel_i830_remove_entries(agp
}
for (i = pg_start; i < (mem->page_count + pg_start); i++)
- OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (i * 4),agp_bridge.scratch_page);
+ OUTREG32(intel_i830_private.registers,I810_PTE_BASE + (i * 4),agp_bridge->scratch_page);
CACHE_FLUSH();
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return (0);
}
@@ -504,7 +504,7 @@ static agp_memory *intel_i830_alloc_by_t
if (nw == NULL) return(NULL);
- addr = agp_bridge.agp_alloc_page();
+ addr = agp_bridge->agp_alloc_page();
if (addr == NULL) {
/* free this structure */
agp_free_memory(nw);
@@ -526,35 +526,35 @@ static int __init intel_i830_setup(struc
{
intel_i830_private.i830_dev = i830_dev;
- agp_bridge.masks = intel_i810_masks;
- agp_bridge.aperture_sizes = (void *) intel_i830_sizes;
- agp_bridge.size_type = FIXED_APER_SIZE;
- agp_bridge.num_aperture_sizes = 2;
-
- agp_bridge.dev_private_data = (void *) &intel_i830_private;
- agp_bridge.needs_scratch_page = TRUE;
-
- agp_bridge.configure = intel_i830_configure;
- agp_bridge.fetch_size = intel_i830_fetch_size;
- agp_bridge.cleanup = intel_i830_cleanup;
- agp_bridge.tlb_flush = intel_i810_tlbflush;
- agp_bridge.mask_memory = intel_i810_mask_memory;
- agp_bridge.agp_enable = intel_i810_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
-
- agp_bridge.create_gatt_table = intel_i830_create_gatt_table;
- agp_bridge.free_gatt_table = intel_i830_free_gatt_table;
-
- agp_bridge.insert_memory = intel_i830_insert_entries;
- agp_bridge.remove_memory = intel_i830_remove_entries;
- agp_bridge.alloc_by_type = intel_i830_alloc_by_type;
- agp_bridge.free_by_type = intel_i810_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
-
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_i810_masks;
+ agp_bridge->aperture_sizes = (void *) intel_i830_sizes;
+ agp_bridge->size_type = FIXED_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 2;
+
+ agp_bridge->dev_private_data = (void *) &intel_i830_private;
+ agp_bridge->needs_scratch_page = TRUE;
+
+ agp_bridge->configure = intel_i830_configure;
+ agp_bridge->fetch_size = intel_i830_fetch_size;
+ agp_bridge->cleanup = intel_i830_cleanup;
+ agp_bridge->tlb_flush = intel_i810_tlbflush;
+ agp_bridge->mask_memory = intel_i810_mask_memory;
+ agp_bridge->agp_enable = intel_i810_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+
+ agp_bridge->create_gatt_table = intel_i830_create_gatt_table;
+ agp_bridge->free_gatt_table = intel_i830_free_gatt_table;
+
+ agp_bridge->insert_memory = intel_i830_insert_entries;
+ agp_bridge->remove_memory = intel_i830_remove_entries;
+ agp_bridge->alloc_by_type = intel_i830_alloc_by_type;
+ agp_bridge->free_by_type = intel_i810_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return(0);
}
@@ -564,13 +564,13 @@ static int intel_fetch_size(void)
u16 temp;
struct aper_size_info_16 *values;
- pci_read_config_word(agp_bridge.dev, INTEL_APSIZE, &temp);
- values = A_SIZE_16(agp_bridge.aperture_sizes);
+ pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
+ values = A_SIZE_16(agp_bridge->aperture_sizes);
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
- agp_bridge.previous_size = agp_bridge.current_size = (void *) (values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
@@ -584,20 +584,20 @@ static int intel_8xx_fetch_size(void)
u8 temp;
struct aper_size_info_8 *values;
- pci_read_config_byte(agp_bridge.dev, INTEL_APSIZE, &temp);
+ pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
/* Intel 815 chipsets have a _weird_ APSIZE register with only
* one non-reserved bit, so mask the others out ... */
- if (agp_bridge.type == INTEL_I815)
+ if (agp_bridge->type == INTEL_I815)
temp &= (1 << 3);
- values = A_SIZE_8(agp_bridge.aperture_sizes);
+ values = A_SIZE_8(agp_bridge->aperture_sizes);
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
- agp_bridge.previous_size =
- agp_bridge.current_size = (void *) (values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->previous_size =
+ agp_bridge->current_size = (void *) (values + i);
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
@@ -607,18 +607,18 @@ static int intel_8xx_fetch_size(void)
static void intel_tlbflush(agp_memory * mem)
{
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x2200);
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x2280);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
}
static void intel_8xx_tlbflush(agp_memory * mem)
{
u32 temp;
- pci_read_config_dword(agp_bridge.dev, INTEL_AGPCTRL, &temp);
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, temp & ~(1 << 7));
- pci_read_config_dword(agp_bridge.dev, INTEL_AGPCTRL, &temp);
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, temp | (1 << 7));
+ pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
+ pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
}
@@ -627,10 +627,10 @@ static void intel_cleanup(void)
u16 temp;
struct aper_size_info_16 *previous_size;
- previous_size = A_SIZE_16(agp_bridge.previous_size);
- pci_read_config_word(agp_bridge.dev, INTEL_NBXCFG, &temp);
- pci_write_config_word(agp_bridge.dev, INTEL_NBXCFG, temp & ~(1 << 9));
- pci_write_config_word(agp_bridge.dev, INTEL_APSIZE, previous_size->size_value);
+ previous_size = A_SIZE_16(agp_bridge->previous_size);
+ pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
+ pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
+ pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
}
@@ -639,10 +639,10 @@ static void intel_8xx_cleanup(void)
u16 temp;
struct aper_size_info_8 *previous_size;
- previous_size = A_SIZE_8(agp_bridge.previous_size);
- pci_read_config_word(agp_bridge.dev, INTEL_NBXCFG, &temp);
- pci_write_config_word(agp_bridge.dev, INTEL_NBXCFG, temp & ~(1 << 9));
- pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, previous_size->size_value);
+ previous_size = A_SIZE_8(agp_bridge->previous_size);
+ pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
+ pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
+ pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
}
@@ -652,27 +652,27 @@ static int intel_configure(void)
u16 temp2;
struct aper_size_info_16 *current_size;
- current_size = A_SIZE_16(agp_bridge.current_size);
+ current_size = A_SIZE_16(agp_bridge->current_size);
/* aperture size */
- pci_write_config_word(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
+ pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
- pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
- pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
+ pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x2280);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
/* paccfg/nbxcfg */
- pci_read_config_word(agp_bridge.dev, INTEL_NBXCFG, &temp2);
- pci_write_config_word(agp_bridge.dev, INTEL_NBXCFG,
+ pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
+ pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
(temp2 & ~(1 << 10)) | (1 << 9));
/* clear any possible error conditions */
- pci_write_config_byte(agp_bridge.dev, INTEL_ERRSTS + 1, 7);
+ pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
return 0;
}
@@ -682,32 +682,32 @@ static int intel_815_configure(void)
u8 temp2;
struct aper_size_info_8 *current_size;
- current_size = A_SIZE_8(agp_bridge.current_size);
+ current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
- pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE,
+ pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
current_size->size_value);
/* address to map to */
- pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
/* the Intel 815 chipset spec. says that bits 29-31 in the
* ATTBASE register are reserved -> try not to write them */
- if (agp_bridge.gatt_bus_addr & INTEL_815_ATTBASE_MASK)
+ if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK)
panic("gatt bus addr too high");
- pci_read_config_dword(agp_bridge.dev, INTEL_ATTBASE, &addr);
+ pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
addr &= INTEL_815_ATTBASE_MASK;
- addr |= agp_bridge.gatt_bus_addr;
- pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, addr);
+ addr |= agp_bridge->gatt_bus_addr;
+ pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
/* agpctrl */
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* apcont */
- pci_read_config_byte(agp_bridge.dev, INTEL_815_APCONT, &temp2);
- pci_write_config_byte(agp_bridge.dev, INTEL_815_APCONT, temp2 | (1 << 1));
+ pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
+ pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
/* clear any possible error conditions */
/* Oddness : this chipset seems to have no ERRSTS register ! */
@@ -724,11 +724,11 @@ static void intel_820_cleanup(void)
u8 temp;
struct aper_size_info_8 *previous_size;
- previous_size = A_SIZE_8(agp_bridge.previous_size);
- pci_read_config_byte(agp_bridge.dev, INTEL_I820_RDCR, &temp);
- pci_write_config_byte(agp_bridge.dev, INTEL_I820_RDCR,
+ previous_size = A_SIZE_8(agp_bridge->previous_size);
+ pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
+ pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
temp & ~(1 << 1));
- pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE,
+ pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
previous_size->size_value);
}
@@ -739,28 +739,28 @@ static int intel_820_configure(void)
u8 temp2;
struct aper_size_info_8 *current_size;
- current_size = A_SIZE_8(agp_bridge.current_size);
+ current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
- pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
+ pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
- pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
- pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
+ pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* global enable aperture access */
/* This flag is not accessed through MCHCFG register as in */
/* i850 chipset. */
- pci_read_config_byte(agp_bridge.dev, INTEL_I820_RDCR, &temp2);
- pci_write_config_byte(agp_bridge.dev, INTEL_I820_RDCR, temp2 | (1 << 1));
+ pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
+ pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
/* clear any possible AGP-related error conditions */
- pci_write_config_word(agp_bridge.dev, INTEL_I820_ERRSTS, 0x001c);
+ pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
return 0;
}
@@ -770,26 +770,26 @@ static int intel_840_configure(void)
u16 temp2;
struct aper_size_info_8 *current_size;
- current_size = A_SIZE_8(agp_bridge.current_size);
+ current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
- pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
+ pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
- pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
- pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
+ pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* mcgcfg */
- pci_read_config_word(agp_bridge.dev, INTEL_I840_MCHCFG, &temp2);
- pci_write_config_word(agp_bridge.dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
+ pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
+ pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
/* clear any possible error conditions */
- pci_write_config_word(agp_bridge.dev, INTEL_I840_ERRSTS, 0xc000);
+ pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
return 0;
}
@@ -799,26 +799,26 @@ static int intel_845_configure(void)
u8 temp2;
struct aper_size_info_8 *current_size;
- current_size = A_SIZE_8(agp_bridge.current_size);
+ current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
- pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
+ pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
- pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
- pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
+ pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* agpm */
- pci_read_config_byte(agp_bridge.dev, INTEL_I845_AGPM, &temp2);
- pci_write_config_byte(agp_bridge.dev, INTEL_I845_AGPM, temp2 | (1 << 1));
+ pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
+ pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
/* clear any possible error conditions */
- pci_write_config_word(agp_bridge.dev, INTEL_I845_ERRSTS, 0x001c);
+ pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
return 0;
}
@@ -833,26 +833,26 @@ static int intel_850_configure(void)
u16 temp2;
struct aper_size_info_8 *current_size;
- current_size = A_SIZE_8(agp_bridge.current_size);
+ current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
- pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
+ pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
- pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
- pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
+ pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* mcgcfg */
- pci_read_config_word(agp_bridge.dev, INTEL_I850_MCHCFG, &temp2);
- pci_write_config_word(agp_bridge.dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
+ pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
+ pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
/* clear any possible AGP-related error conditions */
- pci_write_config_word(agp_bridge.dev, INTEL_I850_ERRSTS, 0x001c);
+ pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
return 0;
}
@@ -862,26 +862,26 @@ static int intel_860_configure(void)
u16 temp2;
struct aper_size_info_8 *current_size;
- current_size = A_SIZE_8(agp_bridge.current_size);
+ current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
- pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
+ pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
- pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
- pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
+ pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* mcgcfg */
- pci_read_config_word(agp_bridge.dev, INTEL_I860_MCHCFG, &temp2);
- pci_write_config_word(agp_bridge.dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
+ pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
+ pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
/* clear any possible AGP-related error conditions */
- pci_write_config_word(agp_bridge.dev, INTEL_I860_ERRSTS, 0xf700);
+ pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
return 0;
}
@@ -891,33 +891,33 @@ static int intel_830mp_configure(void)
u16 temp2;
struct aper_size_info_8 *current_size;
- current_size = A_SIZE_8(agp_bridge.current_size);
+ current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
- pci_write_config_byte(agp_bridge.dev, INTEL_APSIZE, current_size->size_value);
+ pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
/* address to map to */
- pci_read_config_dword(agp_bridge.dev, INTEL_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, INTEL_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* attbase - aperture base */
- pci_write_config_dword(agp_bridge.dev, INTEL_ATTBASE, agp_bridge.gatt_bus_addr);
+ pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
/* agpctrl */
- pci_write_config_dword(agp_bridge.dev, INTEL_AGPCTRL, 0x0000);
+ pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
/* gmch */
- pci_read_config_word(agp_bridge.dev, INTEL_NBXCFG, &temp2);
- pci_write_config_word(agp_bridge.dev, INTEL_NBXCFG, temp2 | (1 << 9));
+ pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
+ pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
/* clear any possible AGP-related error conditions */
- pci_write_config_word(agp_bridge.dev, INTEL_I830_ERRSTS, 0x1c);
+ pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
return 0;
}
static unsigned long intel_mask_memory(unsigned long addr, int type)
{
/* Memory type is ignored */
- return addr | agp_bridge.masks[0].mask;
+ return addr | agp_bridge->masks[0].mask;
}
static void intel_resume(void)
@@ -969,234 +969,234 @@ static struct aper_size_info_8 intel_830
static int __init intel_generic_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = intel_generic_masks;
- agp_bridge.aperture_sizes = (void *) intel_generic_sizes;
- agp_bridge.size_type = U16_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = intel_configure;
- agp_bridge.fetch_size = intel_fetch_size;
- agp_bridge.cleanup = intel_cleanup;
- agp_bridge.tlb_flush = intel_tlbflush;
- agp_bridge.mask_memory = intel_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = intel_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_generic_masks;
+ agp_bridge->aperture_sizes = (void *) intel_generic_sizes;
+ agp_bridge->size_type = U16_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = intel_configure;
+ agp_bridge->fetch_size = intel_fetch_size;
+ agp_bridge->cleanup = intel_cleanup;
+ agp_bridge->tlb_flush = intel_tlbflush;
+ agp_bridge->mask_memory = intel_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = intel_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_815_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = intel_generic_masks;
- agp_bridge.aperture_sizes = (void *) intel_815_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 2;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = intel_815_configure;
- agp_bridge.fetch_size = intel_8xx_fetch_size;
- agp_bridge.cleanup = intel_8xx_cleanup;
- agp_bridge.tlb_flush = intel_8xx_tlbflush;
- agp_bridge.mask_memory = intel_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_generic_masks;
+ agp_bridge->aperture_sizes = (void *) intel_815_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 2;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = intel_815_configure;
+ agp_bridge->fetch_size = intel_8xx_fetch_size;
+ agp_bridge->cleanup = intel_8xx_cleanup;
+ agp_bridge->tlb_flush = intel_8xx_tlbflush;
+ agp_bridge->mask_memory = intel_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_820_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = intel_generic_masks;
- agp_bridge.aperture_sizes = (void *) intel_8xx_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = intel_820_configure;
- agp_bridge.fetch_size = intel_8xx_fetch_size;
- agp_bridge.cleanup = intel_820_cleanup;
- agp_bridge.tlb_flush = intel_820_tlbflush;
- agp_bridge.mask_memory = intel_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_generic_masks;
+ agp_bridge->aperture_sizes = (void *) intel_8xx_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = intel_820_configure;
+ agp_bridge->fetch_size = intel_8xx_fetch_size;
+ agp_bridge->cleanup = intel_820_cleanup;
+ agp_bridge->tlb_flush = intel_820_tlbflush;
+ agp_bridge->mask_memory = intel_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_830mp_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = intel_generic_masks;
- agp_bridge.aperture_sizes = (void *) intel_830mp_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 4;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = intel_830mp_configure;
- agp_bridge.fetch_size = intel_8xx_fetch_size;
- agp_bridge.cleanup = intel_8xx_cleanup;
- agp_bridge.tlb_flush = intel_8xx_tlbflush;
- agp_bridge.mask_memory = intel_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_generic_masks;
+ agp_bridge->aperture_sizes = (void *) intel_830mp_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 4;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = intel_830mp_configure;
+ agp_bridge->fetch_size = intel_8xx_fetch_size;
+ agp_bridge->cleanup = intel_8xx_cleanup;
+ agp_bridge->tlb_flush = intel_8xx_tlbflush;
+ agp_bridge->mask_memory = intel_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_840_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = intel_generic_masks;
- agp_bridge.aperture_sizes = (void *) intel_8xx_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = intel_840_configure;
- agp_bridge.fetch_size = intel_8xx_fetch_size;
- agp_bridge.cleanup = intel_8xx_cleanup;
- agp_bridge.tlb_flush = intel_8xx_tlbflush;
- agp_bridge.mask_memory = intel_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_generic_masks;
+ agp_bridge->aperture_sizes = (void *) intel_8xx_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = intel_840_configure;
+ agp_bridge->fetch_size = intel_8xx_fetch_size;
+ agp_bridge->cleanup = intel_8xx_cleanup;
+ agp_bridge->tlb_flush = intel_8xx_tlbflush;
+ agp_bridge->mask_memory = intel_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_845_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = intel_generic_masks;
- agp_bridge.aperture_sizes = (void *) intel_8xx_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = intel_845_configure;
- agp_bridge.fetch_size = intel_8xx_fetch_size;
- agp_bridge.cleanup = intel_8xx_cleanup;
- agp_bridge.tlb_flush = intel_8xx_tlbflush;
- agp_bridge.mask_memory = intel_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = intel_845_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_generic_masks;
+ agp_bridge->aperture_sizes = (void *) intel_8xx_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = intel_845_configure;
+ agp_bridge->fetch_size = intel_8xx_fetch_size;
+ agp_bridge->cleanup = intel_8xx_cleanup;
+ agp_bridge->tlb_flush = intel_8xx_tlbflush;
+ agp_bridge->mask_memory = intel_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = intel_845_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_850_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = intel_generic_masks;
- agp_bridge.aperture_sizes = (void *) intel_8xx_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = intel_850_configure;
- agp_bridge.fetch_size = intel_8xx_fetch_size;
- agp_bridge.cleanup = intel_8xx_cleanup;
- agp_bridge.tlb_flush = intel_8xx_tlbflush;
- agp_bridge.mask_memory = intel_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_generic_masks;
+ agp_bridge->aperture_sizes = (void *) intel_8xx_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = intel_850_configure;
+ agp_bridge->fetch_size = intel_8xx_fetch_size;
+ agp_bridge->cleanup = intel_8xx_cleanup;
+ agp_bridge->tlb_flush = intel_8xx_tlbflush;
+ agp_bridge->mask_memory = intel_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
static int __init intel_860_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = intel_generic_masks;
- agp_bridge.aperture_sizes = (void *) intel_8xx_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = intel_860_configure;
- agp_bridge.fetch_size = intel_8xx_fetch_size;
- agp_bridge.cleanup = intel_8xx_cleanup;
- agp_bridge.tlb_flush = intel_8xx_tlbflush;
- agp_bridge.mask_memory = intel_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = intel_generic_masks;
+ agp_bridge->aperture_sizes = (void *) intel_8xx_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = intel_860_configure;
+ agp_bridge->fetch_size = intel_8xx_fetch_size;
+ agp_bridge->cleanup = intel_8xx_cleanup;
+ agp_bridge->tlb_flush = intel_8xx_tlbflush;
+ agp_bridge->mask_memory = intel_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
@@ -1287,7 +1287,7 @@ static int __init agp_lookup_host_bridge
if (pdev->device == devs[j].device_id) {
printk (KERN_INFO PFX "Detected Intel %s chipset\n",
devs[j].chipset_name);
- agp_bridge.type = devs[j].chipset;
+ agp_bridge->type = devs[j].chipset;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
@@ -1302,7 +1302,7 @@ static int __init agp_lookup_host_bridge
if (agp_try_unsupported) {
printk(KERN_WARNING PFX "Trying generic Intel routines"
" for device id: %04x\n", pdev->device);
- agp_bridge.type = INTEL_GENERIC;
+ agp_bridge->type = INTEL_GENERIC;
return intel_generic_setup(pdev);
}
@@ -1319,7 +1319,7 @@ static int __init agp_find_supported_dev
struct pci_dev *i810_dev;
u8 cap_ptr = 0;
- agp_bridge.dev = dev;
+ agp_bridge->dev = dev;
/* This shit needs moving into tables/init-routines. */
switch (dev->device) {
@@ -1331,7 +1331,7 @@ static int __init agp_find_supported_dev
return -ENODEV;
}
printk(KERN_INFO PFX "Detected an Intel i810 Chipset.\n");
- agp_bridge.type = INTEL_I810;
+ agp_bridge->type = INTEL_I810;
return intel_i810_setup (i810_dev);
case PCI_DEVICE_ID_INTEL_82810_MC3:
@@ -1342,7 +1342,7 @@ static int __init agp_find_supported_dev
return -ENODEV;
}
printk(KERN_INFO PFX "Detected an Intel i810 DC100 Chipset.\n");
- agp_bridge.type = INTEL_I810;
+ agp_bridge->type = INTEL_I810;
return intel_i810_setup(i810_dev);
case PCI_DEVICE_ID_INTEL_82810E_MC:
@@ -1353,7 +1353,7 @@ static int __init agp_find_supported_dev
return -ENODEV;
}
printk(KERN_INFO PFX "Detected an Intel i810 E Chipset.\n");
- agp_bridge.type = INTEL_I810;
+ agp_bridge->type = INTEL_I810;
return intel_i810_setup(i810_dev);
case PCI_DEVICE_ID_INTEL_82815_MC:
@@ -1371,7 +1371,7 @@ static int __init agp_find_supported_dev
break;
}
printk(KERN_INFO PFX "agpgart: Detected an Intel i815 Chipset.\n");
- agp_bridge.type = INTEL_I810;
+ agp_bridge->type = INTEL_I810;
return intel_i810_setup(i810_dev);
case PCI_DEVICE_ID_INTEL_82845G_HB:
@@ -1387,11 +1387,11 @@ static int __init agp_find_supported_dev
* We probably have a I845MP chipset with an external graphics
* card. It will be initialized later
*/
- agp_bridge.type = INTEL_I845_G;
+ agp_bridge->type = INTEL_I845_G;
break;
}
printk(KERN_INFO PFX "Detected an Intel 845G Chipset.\n");
- agp_bridge.type = INTEL_I810;
+ agp_bridge->type = INTEL_I810;
return intel_i830_setup(i810_dev);
case PCI_DEVICE_ID_INTEL_82830_HB:
@@ -1402,11 +1402,11 @@ static int __init agp_find_supported_dev
if (i810_dev == NULL) {
/* Intel 830MP with external graphic card */
/* It will be initialized later */
- agp_bridge.type = INTEL_I830_M;
+ agp_bridge->type = INTEL_I830_M;
break;
}
printk(KERN_INFO PFX "Detected an Intel 830M Chipset.\n");
- agp_bridge.type = INTEL_I810;
+ agp_bridge->type = INTEL_I810;
return intel_i830_setup(i810_dev);
default:
@@ -1416,10 +1416,10 @@ static int __init agp_find_supported_dev
cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP);
if (cap_ptr == 0)
return -ENODEV;
- agp_bridge.capndx = cap_ptr;
+ agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
/* probe for known chipsets */
return agp_lookup_host_bridge(dev);
@@ -1472,7 +1472,7 @@ int __init agp_intel_init(void)
ret_val = pci_module_init(&agp_intel_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/agp/sis-agp.c linux-2.5/drivers/char/agp/sis-agp.c
--- linux-2.5.60/drivers/char/agp/sis-agp.c 2003-02-10 17:37:57.000000000 -0100
+++ linux-2.5/drivers/char/agp/sis-agp.c 2003-02-10 19:30:03.000000000 -0100
@@ -16,16 +16,16 @@ static int sis_fetch_size(void)
int i;
struct aper_size_info_8 *values;
- pci_read_config_byte(agp_bridge.dev, SIS_APSIZE, &temp_size);
- values = A_SIZE_8(agp_bridge.aperture_sizes);
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ pci_read_config_byte(agp_bridge->dev, SIS_APSIZE, &temp_size);
+ values = A_SIZE_8(agp_bridge->aperture_sizes);
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if ((temp_size == values[i].size_value) ||
((temp_size & ~(0x03)) ==
(values[i].size_value & ~(0x03)))) {
- agp_bridge.previous_size =
- agp_bridge.current_size = (void *) (values + i);
+ agp_bridge->previous_size =
+ agp_bridge->current_size = (void *) (values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
@@ -35,7 +35,7 @@ static int sis_fetch_size(void)
static void sis_tlbflush(agp_memory * mem)
{
- pci_write_config_byte(agp_bridge.dev, SIS_TLBFLUSH, 0x02);
+ pci_write_config_byte(agp_bridge->dev, SIS_TLBFLUSH, 0x02);
}
static int sis_configure(void)
@@ -43,13 +43,13 @@ static int sis_configure(void)
u32 temp;
struct aper_size_info_8 *current_size;
- current_size = A_SIZE_8(agp_bridge.current_size);
- pci_write_config_byte(agp_bridge.dev, SIS_TLBCNTRL, 0x05);
- pci_read_config_dword(agp_bridge.dev, SIS_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
- pci_write_config_dword(agp_bridge.dev, SIS_ATTBASE,
- agp_bridge.gatt_bus_addr);
- pci_write_config_byte(agp_bridge.dev, SIS_APSIZE,
+ current_size = A_SIZE_8(agp_bridge->current_size);
+ pci_write_config_byte(agp_bridge->dev, SIS_TLBCNTRL, 0x05);
+ pci_read_config_dword(agp_bridge->dev, SIS_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_write_config_dword(agp_bridge->dev, SIS_ATTBASE,
+ agp_bridge->gatt_bus_addr);
+ pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
current_size->size_value);
return 0;
}
@@ -58,8 +58,8 @@ static void sis_cleanup(void)
{
struct aper_size_info_8 *previous_size;
- previous_size = A_SIZE_8(agp_bridge.previous_size);
- pci_write_config_byte(agp_bridge.dev, SIS_APSIZE,
+ previous_size = A_SIZE_8(agp_bridge->previous_size);
+ pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
(previous_size->size_value & ~(0x03)));
}
@@ -67,7 +67,7 @@ static unsigned long sis_mask_memory(uns
{
/* Memory type is ignored */
- return addr | agp_bridge.masks[0].mask;
+ return addr | agp_bridge->masks[0].mask;
}
static struct aper_size_info_8 sis_generic_sizes[7] =
@@ -88,30 +88,30 @@ static struct gatt_mask sis_generic_mask
static int __init sis_generic_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = sis_generic_masks;
- agp_bridge.aperture_sizes = (void *) sis_generic_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = sis_configure;
- agp_bridge.fetch_size = sis_fetch_size;
- agp_bridge.cleanup = sis_cleanup;
- agp_bridge.tlb_flush = sis_tlbflush;
- agp_bridge.mask_memory = sis_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = sis_generic_masks;
+ agp_bridge->aperture_sizes = (void *) sis_generic_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = sis_configure;
+ agp_bridge->fetch_size = sis_fetch_size;
+ agp_bridge->cleanup = sis_cleanup;
+ agp_bridge->tlb_flush = sis_tlbflush;
+ agp_bridge->mask_memory = sis_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
@@ -198,7 +198,7 @@ static int __init agp_lookup_host_bridge
if (pdev->device == devs[j].device_id) {
printk (KERN_INFO PFX "Detected SiS %s chipset\n",
devs[j].chipset_name);
- agp_bridge.type = devs[j].chipset;
+ agp_bridge->type = devs[j].chipset;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
@@ -212,7 +212,7 @@ static int __init agp_lookup_host_bridge
if (agp_try_unsupported) {
printk(KERN_WARNING PFX "Trying generic SiS routines"
" for device id: %04x\n", pdev->device);
- agp_bridge.type = SIS_GENERIC;
+ agp_bridge->type = SIS_GENERIC;
return sis_generic_setup(pdev);
}
@@ -235,10 +235,10 @@ static int __init agp_sis_probe (struct
/* probe for known chipsets */
if (agp_lookup_host_bridge(dev) != -ENODEV) {
- agp_bridge.dev = dev;
- agp_bridge.capndx = cap_ptr;
+ agp_bridge->dev = dev;
+ agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
sis_agp_driver.dev = dev;
agp_register_driver(&sis_agp_driver);
return 0;
@@ -272,7 +272,7 @@ static int __init agp_sis_init(void)
ret_val = pci_module_init(&agp_sis_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/agp/sworks-agp.c linux-2.5/drivers/char/agp/sworks-agp.c
--- linux-2.5.60/drivers/char/agp/sworks-agp.c 2003-02-10 17:38:19.000000000 -0100
+++ linux-2.5/drivers/char/agp/sworks-agp.c 2003-02-10 19:30:03.000000000 -0100
@@ -47,7 +47,7 @@ static int serverworks_create_page_map(s
CACHE_FLUSH();
for(i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
- page_map->remapped[i] = agp_bridge.scratch_page;
+ page_map->remapped[i] = agp_bridge->scratch_page;
}
return 0;
@@ -120,7 +120,7 @@ static int serverworks_create_gatt_pages
#ifndef GET_PAGE_DIR_IDX
#define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
- GET_PAGE_DIR_OFF(agp_bridge.gart_bus_addr))
+ GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
#endif
#ifndef GET_GATT_OFF
@@ -135,7 +135,7 @@ static int serverworks_create_gatt_table
u32 temp;
int i;
- value = A_SIZE_LVL2(agp_bridge.current_size);
+ value = A_SIZE_LVL2(agp_bridge->current_size);
retval = serverworks_create_page_map(&page_dir);
if (retval != 0) {
return retval;
@@ -147,7 +147,7 @@ static int serverworks_create_gatt_table
}
/* Create a fake scratch directory */
for(i = 0; i < 1024; i++) {
- serverworks_private.scratch_dir.remapped[i] = (unsigned long) agp_bridge.scratch_page;
+ serverworks_private.scratch_dir.remapped[i] = (unsigned long) agp_bridge->scratch_page;
page_dir.remapped[i] =
virt_to_phys(serverworks_private.scratch_dir.real);
page_dir.remapped[i] |= 0x00000001;
@@ -160,17 +160,17 @@ static int serverworks_create_gatt_table
return retval;
}
- agp_bridge.gatt_table_real = (u32 *)page_dir.real;
- agp_bridge.gatt_table = (u32 *)page_dir.remapped;
- agp_bridge.gatt_bus_addr = virt_to_phys(page_dir.real);
+ agp_bridge->gatt_table_real = (u32 *)page_dir.real;
+ agp_bridge->gatt_table = (u32 *)page_dir.remapped;
+ agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
/* Get the address for the gart region.
* This is a bus address even on the alpha, b/c its
* used to program the agp master not the cpu
*/
- pci_read_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,&temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* Calculate the agp offset */
@@ -187,8 +187,8 @@ static int serverworks_free_gatt_table(v
{
struct serverworks_page_map page_dir;
- page_dir.real = (unsigned long *)agp_bridge.gatt_table_real;
- page_dir.remapped = (unsigned long *)agp_bridge.gatt_table;
+ page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
+ page_dir.remapped = (unsigned long *)agp_bridge->gatt_table;
serverworks_free_gatt_pages();
serverworks_free_page_map(&page_dir);
@@ -203,20 +203,20 @@ static int serverworks_fetch_size(void)
u32 temp2;
struct aper_size_info_lvl2 *values;
- values = A_SIZE_LVL2(agp_bridge.aperture_sizes);
- pci_read_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,&temp);
- pci_write_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,
+ values = A_SIZE_LVL2(agp_bridge->aperture_sizes);
+ pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
+ pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,
SVWRKS_SIZE_MASK);
- pci_read_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,&temp2);
- pci_write_config_dword(agp_bridge.dev,serverworks_private.gart_addr_ofs,temp);
+ pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2);
+ pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp);
temp2 &= SVWRKS_SIZE_MASK;
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp2 == values[i].size_value) {
- agp_bridge.previous_size =
- agp_bridge.current_size = (void *) (values + i);
+ agp_bridge->previous_size =
+ agp_bridge->current_size = (void *) (values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
@@ -231,17 +231,17 @@ static int serverworks_configure(void)
u8 enable_reg;
u16 cap_reg;
- current_size = A_SIZE_LVL2(agp_bridge.current_size);
+ current_size = A_SIZE_LVL2(agp_bridge->current_size);
/* Get the memory mapped registers */
- pci_read_config_dword(agp_bridge.dev, serverworks_private.mm_addr_ofs, &temp);
+ pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp);
temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
serverworks_private.registers = (volatile u8 *) ioremap(temp, 4096);
OUTREG8(serverworks_private.registers, SVWRKS_GART_CACHE, 0x0a);
OUTREG32(serverworks_private.registers, SVWRKS_GATTBASE,
- agp_bridge.gatt_bus_addr);
+ agp_bridge->gatt_bus_addr);
cap_reg = INREG16(serverworks_private.registers, SVWRKS_COMMAND);
cap_reg &= ~0x0007;
@@ -253,21 +253,21 @@ static int serverworks_configure(void)
enable_reg |= 0x1; /* Agp Enable bit */
pci_write_config_byte(serverworks_private.svrwrks_dev,
SVWRKS_AGP_ENABLE, enable_reg);
- agp_bridge.tlb_flush(NULL);
+ agp_bridge->tlb_flush(NULL);
- agp_bridge.capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);
+ agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);
/* Fill in the mode register */
pci_read_config_dword(serverworks_private.svrwrks_dev,
- agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
+ agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
- pci_read_config_byte(agp_bridge.dev, SVWRKS_CACHING, &enable_reg);
+ pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg);
enable_reg &= ~0x3;
- pci_write_config_byte(agp_bridge.dev, SVWRKS_CACHING, enable_reg);
+ pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg);
- pci_read_config_byte(agp_bridge.dev, SVWRKS_FEATURE, &enable_reg);
+ pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg);
enable_reg |= (1<<6);
- pci_write_config_byte(agp_bridge.dev,SVWRKS_FEATURE, enable_reg);
+ pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg);
return 0;
}
@@ -313,7 +313,7 @@ static unsigned long serverworks_mask_me
{
/* Only type 0 is supported by the serverworks chipsets */
- return addr | agp_bridge.masks[0].mask;
+ return addr | agp_bridge->masks[0].mask;
}
static int serverworks_insert_memory(agp_memory * mem,
@@ -323,7 +323,7 @@ static int serverworks_insert_memory(agp
unsigned long *cur_gatt;
unsigned long addr;
- num_entries = A_SIZE_LVL2(agp_bridge.current_size)->num_entries;
+ num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
if (type != 0 || mem->type != 0) {
return -EINVAL;
@@ -334,7 +334,7 @@ static int serverworks_insert_memory(agp
j = pg_start;
while (j < (pg_start + mem->page_count)) {
- addr = (j * PAGE_SIZE) + agp_bridge.gart_bus_addr;
+ addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = SVRWRKS_GET_GATT(addr);
if (!PGE_EMPTY(cur_gatt[GET_GATT_OFF(addr)])) {
return -EBUSY;
@@ -348,12 +348,12 @@ static int serverworks_insert_memory(agp
}
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
- addr = (j * PAGE_SIZE) + agp_bridge.gart_bus_addr;
+ addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = SVRWRKS_GET_GATT(addr);
cur_gatt[GET_GATT_OFF(addr)] =
- agp_bridge.mask_memory(mem->memory[i], mem->type);
+ agp_bridge->mask_memory(mem->memory[i], mem->type);
}
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
@@ -369,16 +369,16 @@ static int serverworks_remove_memory(agp
}
CACHE_FLUSH();
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
for (i = pg_start; i < (mem->page_count + pg_start); i++) {
- addr = (i * PAGE_SIZE) + agp_bridge.gart_bus_addr;
+ addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = SVRWRKS_GET_GATT(addr);
cur_gatt[GET_GATT_OFF(addr)] =
- (unsigned long) agp_bridge.scratch_page;
+ (unsigned long) agp_bridge->scratch_page;
}
- agp_bridge.tlb_flush(mem);
+ agp_bridge->tlb_flush(mem);
return 0;
}
@@ -403,7 +403,7 @@ static void serverworks_agp_enable(u32 m
u32 command;
pci_read_config_dword(serverworks_private.svrwrks_dev,
- agp_bridge.capndx + PCI_AGP_STATUS,
+ agp_bridge->capndx + PCI_AGP_STATUS,
&command);
command = agp_collect_device_status(mode, command);
@@ -414,7 +414,7 @@ static void serverworks_agp_enable(u32 m
command |= 0x100;
pci_write_config_dword(serverworks_private.svrwrks_dev,
- agp_bridge.capndx + PCI_AGP_COMMAND,
+ agp_bridge->capndx + PCI_AGP_COMMAND,
command);
agp_device_command(command, 0);
@@ -427,39 +427,39 @@ static int __init serverworks_setup (str
serverworks_private.svrwrks_dev = pdev;
- agp_bridge.masks = serverworks_masks;
- agp_bridge.aperture_sizes = (void *) serverworks_sizes;
- agp_bridge.size_type = LVL2_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = (void *) &serverworks_private;
- agp_bridge.needs_scratch_page = TRUE;
- agp_bridge.configure = serverworks_configure;
- agp_bridge.fetch_size = serverworks_fetch_size;
- agp_bridge.cleanup = serverworks_cleanup;
- agp_bridge.tlb_flush = serverworks_tlbflush;
- agp_bridge.mask_memory = serverworks_mask_memory;
- agp_bridge.agp_enable = serverworks_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = serverworks_create_gatt_table;
- agp_bridge.free_gatt_table = serverworks_free_gatt_table;
- agp_bridge.insert_memory = serverworks_insert_memory;
- agp_bridge.remove_memory = serverworks_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+ agp_bridge->masks = serverworks_masks;
+ agp_bridge->aperture_sizes = (void *) serverworks_sizes;
+ agp_bridge->size_type = LVL2_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = (void *) &serverworks_private;
+ agp_bridge->needs_scratch_page = TRUE;
+ agp_bridge->configure = serverworks_configure;
+ agp_bridge->fetch_size = serverworks_fetch_size;
+ agp_bridge->cleanup = serverworks_cleanup;
+ agp_bridge->tlb_flush = serverworks_tlbflush;
+ agp_bridge->mask_memory = serverworks_mask_memory;
+ agp_bridge->agp_enable = serverworks_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = serverworks_create_gatt_table;
+ agp_bridge->free_gatt_table = serverworks_free_gatt_table;
+ agp_bridge->insert_memory = serverworks_insert_memory;
+ agp_bridge->remove_memory = serverworks_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
- pci_read_config_dword(agp_bridge.dev,
+ pci_read_config_dword(agp_bridge->dev,
SVWRKS_APSIZE,
&temp);
serverworks_private.gart_addr_ofs = 0x10;
if(temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
- pci_read_config_dword(agp_bridge.dev,
+ pci_read_config_dword(agp_bridge->dev,
SVWRKS_APSIZE + 4,
&temp2);
if(temp2 != 0) {
@@ -472,11 +472,11 @@ static int __init serverworks_setup (str
serverworks_private.mm_addr_ofs = 0x14;
}
- pci_read_config_dword(agp_bridge.dev,
+ pci_read_config_dword(agp_bridge->dev,
serverworks_private.mm_addr_ofs,
&temp);
if(temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
- pci_read_config_dword(agp_bridge.dev,
+ pci_read_config_dword(agp_bridge->dev,
serverworks_private.mm_addr_ofs + 4,
&temp2);
if(temp2 != 0) {
@@ -503,21 +503,21 @@ static int __init agp_find_supported_dev
return -ENODEV;
}
- agp_bridge.dev = dev;
+ agp_bridge->dev = dev;
switch (dev->device) {
case PCI_DEVICE_ID_SERVERWORKS_HE:
- agp_bridge.type = SVWRKS_HE;
+ agp_bridge->type = SVWRKS_HE;
return serverworks_setup(bridge_dev);
case PCI_DEVICE_ID_SERVERWORKS_LE:
case 0x0007:
- agp_bridge.type = SVWRKS_LE;
+ agp_bridge->type = SVWRKS_LE;
return serverworks_setup(bridge_dev);
default:
if(agp_try_unsupported) {
- agp_bridge.type = SVWRKS_GENERIC;
+ agp_bridge->type = SVWRKS_GENERIC;
return serverworks_setup(bridge_dev);
}
break;
@@ -565,7 +565,7 @@ static int __init agp_serverworks_init(v
ret_val = pci_module_init(&agp_serverworks_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/agp/via-agp.c linux-2.5/drivers/char/agp/via-agp.c
--- linux-2.5.60/drivers/char/agp/via-agp.c 2003-02-10 17:38:51.000000000 -0100
+++ linux-2.5/drivers/char/agp/via-agp.c 2003-02-10 19:30:03.000000000 -0100
@@ -11,73 +11,78 @@
static int agp_try_unsupported __initdata = 0;
+
static int via_fetch_size(void)
{
int i;
u8 temp;
struct aper_size_info_8 *values;
- values = A_SIZE_8(agp_bridge.aperture_sizes);
- pci_read_config_byte(agp_bridge.dev, VIA_APSIZE, &temp);
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
+ values = A_SIZE_8(agp_bridge->aperture_sizes);
+ pci_read_config_byte(agp_bridge->dev, VIA_APSIZE, &temp);
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
if (temp == values[i].size_value) {
- agp_bridge.previous_size =
- agp_bridge.current_size = (void *) (values + i);
- agp_bridge.aperture_size_idx = i;
+ agp_bridge->previous_size =
+ agp_bridge->current_size = (void *) (values + i);
+ agp_bridge->aperture_size_idx = i;
return values[i].size;
}
}
-
return 0;
}
+
static int via_configure(void)
{
u32 temp;
struct aper_size_info_8 *current_size;
- current_size = A_SIZE_8(agp_bridge.current_size);
+ current_size = A_SIZE_8(agp_bridge->current_size);
/* aperture size */
- pci_write_config_byte(agp_bridge.dev, VIA_APSIZE,
+ pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
current_size->size_value);
/* address to map too */
- pci_read_config_dword(agp_bridge.dev, VIA_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+ pci_read_config_dword(agp_bridge->dev, VIA_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
/* GART control register */
- pci_write_config_dword(agp_bridge.dev, VIA_GARTCTRL, 0x0000000f);
+ pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f);
/* attbase - aperture GATT base */
- pci_write_config_dword(agp_bridge.dev, VIA_ATTBASE,
- (agp_bridge.gatt_bus_addr & 0xfffff000) | 3);
+ pci_write_config_dword(agp_bridge->dev, VIA_ATTBASE,
+ (agp_bridge->gatt_bus_addr & 0xfffff000) | 3);
return 0;
}
+
static void via_cleanup(void)
{
struct aper_size_info_8 *previous_size;
- previous_size = A_SIZE_8(agp_bridge.previous_size);
- pci_write_config_byte(agp_bridge.dev, VIA_APSIZE,
+ previous_size = A_SIZE_8(agp_bridge->previous_size);
+ pci_write_config_byte(agp_bridge->dev, VIA_APSIZE,
previous_size->size_value);
/* Do not disable by writing 0 to VIA_ATTBASE, it screws things up
* during reinitialization.
*/
}
+
static void via_tlbflush(agp_memory * mem)
{
- pci_write_config_dword(agp_bridge.dev, VIA_GARTCTRL, 0x0000008f);
- pci_write_config_dword(agp_bridge.dev, VIA_GARTCTRL, 0x0000000f);
+ pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000008f);
+ pci_write_config_dword(agp_bridge->dev, VIA_GARTCTRL, 0x0000000f);
}
+
static unsigned long via_mask_memory(unsigned long addr, int type)
{
/* Memory type is ignored */
- return addr | agp_bridge.masks[0].mask;
+ return addr | agp_bridge->masks[0].mask;
}
+
static struct aper_size_info_8 via_generic_sizes[7] =
{
{256, 65536, 6, 0},
@@ -89,123 +94,327 @@ static struct aper_size_info_8 via_gener
{4, 1024, 0, 252}
};
+
static struct gatt_mask via_generic_masks[] =
{
{.mask = 0x00000000, .type = 0}
};
+
+#ifdef CONFIG_AGP3
+static int via_fetch_size_agp3(void)
+{
+ int i;
+ u16 temp;
+ struct aper_size_info_16 *values;
+
+ values = A_SIZE_16(agp_bridge->aperture_sizes);
+ pci_read_config_word(agp_bridge->dev, VIA_AGP3_APSIZE, &temp);
+ temp &= 0xfff;
+
+ for (i = 0; i < agp_bridge->num_aperture_sizes; i++) {
+ if (temp == values[i].size_value) {
+ agp_bridge->previous_size =
+ agp_bridge->current_size = (void *) (values + i);
+ agp_bridge->aperture_size_idx = i;
+ return values[i].size;
+ }
+ }
+ return 0;
+}
+
+
+static int via_configure_agp3(void)
+{
+ u32 temp;
+ struct aper_size_info_16 *current_size;
+
+ current_size = A_SIZE_16(agp_bridge->current_size);
+
+ /* address to map too */
+ pci_read_config_dword(agp_bridge->dev, VIA_APBASE, &temp);
+ agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
+
+ /* attbase - aperture GATT base */
+ pci_write_config_dword(agp_bridge->dev, VIA_AGP3_ATTBASE,
+ agp_bridge->gatt_bus_addr & 0xfffff000);
+ return 0;
+}
+
+
+static void via_cleanup_agp3(void)
+{
+ struct aper_size_info_16 *previous_size;
+
+ previous_size = A_SIZE_16(agp_bridge->previous_size);
+ pci_write_config_byte(agp_bridge->dev, VIA_APSIZE, previous_size->size_value);
+}
+
+
+static void via_tlbflush_agp3(agp_memory * mem)
+{
+ u32 temp;
+
+ pci_read_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, &temp);
+ pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7));
+ pci_write_config_dword(agp_bridge->dev, VIA_AGP3_GARTCTRL, temp);
+}
+
+
+static struct aper_size_info_16 via_generic_agp3_sizes[11] =
+{
+ { 4, 1024, 0, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2|1<<1|1<<0 },
+ { 8, 2048, 1, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2|1<<1},
+ { 16, 4096, 2, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2},
+ { 32, 8192, 3, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3},
+ { 64, 16384, 4, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4},
+ { 128, 32768, 5, 1<<11|1<<10|1<<9|1<<8|1<<5},
+ { 256, 65536, 6, 1<<11|1<<10|1<<9|1<<8},
+ { 512, 131072, 7, 1<<11|1<<10|1<<9},
+ { 1024, 262144, 8, 1<<11|1<<10},
+ { 2048, 524288, 9, 1<<11} /* 2GB <- Max supported */
+};
+
+
+static int __init via_generic_agp3_setup (struct pci_dev *pdev)
+{
+ agp_bridge->dev = pdev;
+ agp_bridge->type = VIA_GENERIC;
+ agp_bridge->masks = via_generic_masks;
+ agp_bridge->aperture_sizes = (void *) via_generic_agp3_sizes;
+ agp_bridge->size_type = U16_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 10;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->agp_enable = agp_generic_agp_3_0_enable;
+ agp_bridge->configure = via_configure_agp3;
+ agp_bridge->fetch_size = via_fetch_size_agp3;
+ agp_bridge->cleanup = via_cleanup_agp3;
+ agp_bridge->tlb_flush = via_tlbflush_agp3;
+ agp_bridge->mask_memory = via_mask_memory;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
+ return 0;
+}
+#else
+static int __init via_generic_agp3_setup (struct pci_dev *pdev)
+{
+ printk (KERN_INFO PFX "Bridge in AGP3 mode, but CONFIG_AGP3=n\n");
+ return -ENODEV;
+}
+#endif /* CONFIG_AGP3 */
+
+
static int __init via_generic_setup (struct pci_dev *pdev)
{
- agp_bridge.masks = via_generic_masks;
- agp_bridge.aperture_sizes = (void *) via_generic_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.configure = via_configure;
- agp_bridge.fetch_size = via_fetch_size;
- agp_bridge.cleanup = via_cleanup;
- agp_bridge.tlb_flush = via_tlbflush;
- agp_bridge.mask_memory = via_mask_memory;
- agp_bridge.agp_enable = agp_generic_agp_enable;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
+#ifdef CONFIG_AGP3
+ /* Garg, there are KT400s with KT266 IDs. */
+ if (pdev->device == PCI_DEVICE_ID_VIA_8367_0) {
+
+ /* Is there a KT400 subsystem ? */
+ if (pdev->subsystem_device==PCI_DEVICE_ID_VIA_8377_0) {
+ u8 reg;
+
+ printk (KERN_INFO PFX "Found KT400 in disguise as a KT266.\n");
+
+ /* Check AGP compatability mode. */
+ pci_read_config_byte(pdev, VIA_AGPSEL, ®);
+ if ((reg & (1<<1))==0)
+ return via_generic_agp3_setup(pdev);
+
+ /* Its in 2.0 mode, drop through. */
+ }
+ }
+#endif
+
+ agp_bridge->masks = via_generic_masks;
+ agp_bridge->aperture_sizes = (void *) via_generic_sizes;
+ agp_bridge->size_type = U8_APER_SIZE;
+ agp_bridge->num_aperture_sizes = 7;
+ agp_bridge->dev_private_data = NULL;
+ agp_bridge->needs_scratch_page = FALSE;
+ agp_bridge->configure = via_configure;
+ agp_bridge->fetch_size = via_fetch_size;
+ agp_bridge->cleanup = via_cleanup;
+ agp_bridge->tlb_flush = via_tlbflush;
+ agp_bridge->mask_memory = via_mask_memory;
+ agp_bridge->agp_enable = agp_generic_agp_enable;
+ agp_bridge->cache_flush = global_cache_flush;
+ agp_bridge->create_gatt_table = agp_generic_create_gatt_table;
+ agp_bridge->free_gatt_table = agp_generic_free_gatt_table;
+ agp_bridge->insert_memory = agp_generic_insert_memory;
+ agp_bridge->remove_memory = agp_generic_remove_memory;
+ agp_bridge->alloc_by_type = agp_generic_alloc_by_type;
+ agp_bridge->free_by_type = agp_generic_free_by_type;
+ agp_bridge->agp_alloc_page = agp_generic_alloc_page;
+ agp_bridge->agp_destroy_page = agp_generic_destroy_page;
+ agp_bridge->suspend = agp_generic_suspend;
+ agp_bridge->resume = agp_generic_resume;
+ agp_bridge->cant_use_aperture = 0;
return 0;
}
-/*
- * The KT400 does magick to put the AGP bridge compliant with the same
- * standards version as the graphics card. If we haven't fallen into
- * 2.0 compatability mode, we abort, as this gets picked up by
- * via-agp3.o
- */
+/* The KT400 does magick to put the AGP bridge compliant with the same
+ * standards version as the graphics card. */
static int __init via_kt400_setup(struct pci_dev *pdev)
{
u8 reg;
pci_read_config_byte(pdev, VIA_AGPSEL, ®);
/* Check AGP 2.0 compatability mode. */
- if ((reg & (1<<1))==1) {
- via_generic_setup(pdev);
- return 0;
- }
- return -ENODEV;
+ if ((reg & (1<<1))==0)
+ return via_generic_agp3_setup(pdev);
+ return via_generic_setup(pdev);
}
+
static struct agp_device_ids via_agp_device_ids[] __initdata =
{
{
.device_id = PCI_DEVICE_ID_VIA_82C597_0,
- .chipset = VIA_VP3,
.chipset_name = "VP3",
},
+
{
.device_id = PCI_DEVICE_ID_VIA_82C598_0,
- .chipset = VIA_MVP3,
.chipset_name = "MVP3",
},
+
{
.device_id = PCI_DEVICE_ID_VIA_8501_0,
- .chipset = VIA_MVP4,
.chipset_name = "MVP4",
},
+
+ /* VT8601 */
+ {
+ .device_id = PCI_DEVICE_ID_VIA_8601_0,
+ .chipset_name = "PLE133 ProMedia",
+ },
+
+ /* VT82C693A / VT28C694T */
{
.device_id = PCI_DEVICE_ID_VIA_82C691,
- .chipset = VIA_APOLLO_PRO,
- .chipset_name = "Apollo Pro",
+ .chipset_name = "Apollo Pro 133",
},
+
{
.device_id = PCI_DEVICE_ID_VIA_8371_0,
- .chipset = VIA_APOLLO_KX133,
.chipset_name = "Apollo Pro KX133",
},
+
+ /* VT8633 */
{
.device_id = PCI_DEVICE_ID_VIA_8633_0,
- .chipset = VIA_APOLLO_PRO_266,
.chipset_name = "Apollo Pro 266",
},
+
+ /* VT8361 */
+/* {
+ .device_id = PCI_DEVICE_ID_VIA_8361, // 0x3112
+ .chipset_name = "Apollo KLE133",
+ }, */
+
+ /* VT8365 / VT8362 */
{
.device_id = PCI_DEVICE_ID_VIA_8363_0,
- .chipset = VIA_APOLLO_KT133,
- .chipset_name = "Apollo Pro KT133",
+ .chipset_name = "Apollo Pro KT133/KM133/TwisterK",
},
+
+ /* VT8753A */
+/* {
+ .device_id = PCI_DEVICE_ID_VIA_8753_0, // 0x3128
+ .chipset_name = "P4X266",
+ }, */
+
+ /* VT8366 */
{
.device_id = PCI_DEVICE_ID_VIA_8367_0,
- .chipset = VIA_APOLLO_KT133,
- .chipset_name = "Apollo Pro KT266",
+ .chipset_name = "Apollo Pro KT266/KT333",
},
+
+ /* VT8633 (for CuMine/ Celeron) */
{
.device_id = PCI_DEVICE_ID_VIA_8653_0,
- .chipset = VIA_APOLLO_PRO,
.chipset_name = "Apollo Pro 266T",
},
+
+ /* KM266 / PM266 */
+/* {
+ .device_id = PCI_DEVICE_ID_VIA_KM266, // 0x3116
+ .chipset_name = "KM266/PM266",
+ }, */
+
+ /* CLE266 */
+/* {
+ .device_id = PCI_DEVICE_ID_VIA_CLE266, // 0x3123
+ .chipset_name = "CLE266",
+ }, */
+
{
.device_id = PCI_DEVICE_ID_VIA_8377_0,
- .chipset = VIA_APOLLO_KT400,
.chipset_name = "Apollo Pro KT400",
.chipset_setup = via_kt400_setup,
},
+
+ /* VT8604 / VT8605 / VT8603 / TwisterT
+ * (Apollo Pro133A chipset with S3 Savage4) */
{
- /* VIA ProSavage PM133 (Apollo Pro133A chipset with S3 Savage4) */
.device_id = PCI_DEVICE_ID_VIA_82C694X_0,
- .chipset = VIA_VT8605,
- .chipset_name = "Apollo ProSavage PM133"
+ .chipset_name = "Apollo ProSavage PM133/PL133/PN133/Twister"
},
+
+ /* VT8752*/
+/* {
+ .device_id = PCI_DEVICE_ID_VIA_8752, // 0x3148
+ .chipset_name = "ProSavage DDR P4M266",
+ }, */
+
+ /* KN266/PN266 */
+/* {
+ .device_id = PCI_DEVICE_ID_KN266, // 0x3156
+ .chipset_name = "KN266/PN266",
+ }, */
+
+ /* VT8754 */
{
.device_id = PCI_DEVICE_ID_VIA_8754,
- .chipset = VIA_P4X,
.chipset_name = "Apollo P4X333/P4X400"
},
+
+ /* P4N333 */
+/* {
+ .device_id = PCI_DEVICE_ID_VIA_P4N333, // 0x3178
+ .chipset_name = "P4N333",
+ }, */
+
+ /* P4X600 */
+/* {
+ .device_id = PCI_DEVICE_ID_VIA_P4X600, // 0x0198
+ .chipset_name = "P4X600",
+ }, */
+
+ /* KM400 */
+/* {
+ .device_id = PCI_DEVICE_ID_VIA_KM400, // 0x3205
+ .chipset_name = "KM400",
+ }, */
+
+ /* P4M400 */
+/* {
+ .device_id = PCI_DEVICE_ID_VIA_P4M400, // 0x3209
+ .chipset_name = "PM400",
+ }, */
+
{ }, /* dummy final entry, always present */
};
@@ -221,7 +430,7 @@ static int __init agp_lookup_host_bridge
while (devs[j].chipset_name != NULL) {
if (pdev->device == devs[j].device_id) {
printk (KERN_INFO PFX "Detected VIA %s chipset\n", devs[j].chipset_name);
- agp_bridge.type = devs[j].chipset;
+ agp_bridge->type = VIA_GENERIC;
if (devs[j].chipset_setup != NULL)
return devs[j].chipset_setup(pdev);
@@ -235,7 +444,7 @@ static int __init agp_lookup_host_bridge
if (agp_try_unsupported) {
printk(KERN_WARNING PFX "Trying generic VIA routines"
" for device id: %04x\n", pdev->device);
- agp_bridge.type = VIA_GENERIC;
+ agp_bridge->type = VIA_GENERIC;
return via_generic_setup(pdev);
}
@@ -244,10 +453,12 @@ static int __init agp_lookup_host_bridge
return -ENODEV;
}
+
static struct agp_driver via_agp_driver = {
.owner = THIS_MODULE,
};
+
static int __init agp_via_probe (struct pci_dev *dev, const struct pci_device_id *ent)
{
u8 cap_ptr = 0;
@@ -258,10 +469,10 @@ static int __init agp_via_probe (struct
/* probe for known chipsets */
if (agp_lookup_host_bridge (dev) != -ENODEV) {
- agp_bridge.dev = dev;
- agp_bridge.capndx = cap_ptr;
+ agp_bridge->dev = dev;
+ agp_bridge->capndx = cap_ptr;
/* Fill in the mode register */
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
+ pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
via_agp_driver.dev = dev;
agp_register_driver(&via_agp_driver);
return 0;
@@ -269,6 +480,7 @@ static int __init agp_via_probe (struct
return -ENODEV;
}
+
static struct pci_device_id agp_via_pci_table[] __initdata = {
{
.class = (PCI_CLASS_BRIDGE_HOST << 8),
@@ -283,31 +495,36 @@ static struct pci_device_id agp_via_pci_
MODULE_DEVICE_TABLE(pci, agp_via_pci_table);
+
static struct __initdata pci_driver agp_via_pci_driver = {
.name = "agpgart-via",
.id_table = agp_via_pci_table,
.probe = agp_via_probe,
};
+
static int __init agp_via_init(void)
{
int ret_val;
ret_val = pci_module_init(&agp_via_pci_driver);
if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
+ agp_bridge->type = NOT_SUPPORTED;
return ret_val;
}
+
static void __exit agp_via_cleanup(void)
{
agp_unregister_driver(&via_agp_driver);
pci_unregister_driver(&agp_via_pci_driver);
}
+
module_init(agp_via_init);
module_exit(agp_via_cleanup);
MODULE_PARM(agp_try_unsupported, "1i");
MODULE_LICENSE("GPL and additional rights");
+MODULE_AUTHOR("Dave Jones ");
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/agp/via-kt400.c linux-2.5/drivers/char/agp/via-kt400.c
--- linux-2.5.60/drivers/char/agp/via-kt400.c 2003-02-10 17:38:49.000000000 -0100
+++ linux-2.5/drivers/char/agp/via-kt400.c 1969-12-31 23:00:00.000000000 -0100
@@ -1,202 +0,0 @@
-/*
- * VIA KT400 AGPGART routines.
- *
- * The KT400 does magick to put the AGP bridge compliant with the same
- * standards version as the graphics card. If we haven't fallen into
- * 2.0 compatability mode, we run this code. Otherwise, we run the
- * code in via-agp.c
- */
-
-#include
-#include
-#include
-#include
-#include
-#include "agp.h"
-
-static int via_fetch_size(void)
-{
- int i;
- u8 temp;
- struct aper_size_info_16 *values;
-
- values = A_SIZE_16(agp_bridge.aperture_sizes);
- pci_read_config_byte(agp_bridge.dev, VIA_AGP3_APSIZE, &temp);
- for (i = 0; i < agp_bridge.num_aperture_sizes; i++) {
- if (temp == values[i].size_value) {
- agp_bridge.previous_size =
- agp_bridge.current_size = (void *) (values + i);
- agp_bridge.aperture_size_idx = i;
- return values[i].size;
- }
- }
- return 0;
-}
-
-static int via_configure(void)
-{
- u32 temp;
- struct aper_size_info_16 *current_size;
-
- current_size = A_SIZE_16(agp_bridge.current_size);
-
- /* address to map too */
- pci_read_config_dword(agp_bridge.dev, VIA_APBASE, &temp);
- agp_bridge.gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
-
- /* attbase - aperture GATT base */
- pci_write_config_dword(agp_bridge.dev, VIA_AGP3_ATTBASE,
- agp_bridge.gatt_bus_addr & 0xfffff000);
- return 0;
-}
-
-static void via_cleanup(void)
-{
- struct aper_size_info_16 *previous_size;
-
- previous_size = A_SIZE_16(agp_bridge.previous_size);
- pci_write_config_byte(agp_bridge.dev, VIA_APSIZE, previous_size->size_value);
-}
-
-static void via_tlbflush(agp_memory * mem)
-{
- u32 temp;
-
- pci_read_config_dword(agp_bridge.dev, VIA_AGP3_GARTCTRL, &temp);
- pci_write_config_dword(agp_bridge.dev, VIA_AGP3_GARTCTRL, temp & ~(1<<7));
- pci_write_config_dword(agp_bridge.dev, VIA_AGP3_GARTCTRL, temp);
-}
-
-static unsigned long via_mask_memory(unsigned long addr, int type)
-{
- /* Memory type is ignored */
-
- return addr | agp_bridge.masks[0].mask;
-}
-
-static struct aper_size_info_16 via_generic_sizes[11] =
-{
- { 4, 1024, 0, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2|1<<1|1<<0 },
- { 8, 2048, 1, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2|1<<1},
- { 16, 4096, 2, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3|1<<2},
- { 32, 8192, 3, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4|1<<3},
- { 64, 16384, 4, 1<<11|1<<10|1<<9|1<<8|1<<5|1<<4},
- { 128, 32768, 5, 1<<11|1<<10|1<<9|1<<8|1<<5},
- { 256, 65536, 6, 1<<11|1<<10|1<<9|1<<8},
- { 512, 131072, 7, 1<<11|1<<10|1<<9},
- { 1024, 262144, 8, 1<<11|1<<10},
- { 2048, 524288, 9, 1<<11} /* 2GB <- Max supported */
-};
-
-static struct gatt_mask via_generic_masks[] =
-{
- {.mask = 0x00000000, .type = 0}
-};
-
-
-static void __init via_kt400_enable(u32 mode)
-{
- if ((agp_generic_agp_3_0_enable(mode))==FALSE)
- printk (KERN_INFO PFX "agp_generic_agp_3_0_enable() failed\n");
-}
-
-static struct agp_driver via_kt400_agp_driver = {
- .owner = THIS_MODULE,
-};
-
-static int __init agp_via_probe (struct pci_dev *dev, const struct pci_device_id *ent)
-{
- u8 reg;
- u8 cap_ptr = 0;
-
- cap_ptr = pci_find_capability(dev, PCI_CAP_ID_AGP);
- if (cap_ptr == 0)
- return -ENODEV;
-
- pci_read_config_byte(dev, VIA_AGPSEL, ®);
- /* Check if we are in AGP 2.0 compatability mode, if so it
- * will be picked up by via-agp.o */
- if ((reg & (1<<1))==1)
- return -ENODEV;
-
- printk (KERN_INFO PFX "Detected VIA KT400 AGP3 chipset\n");
-
- agp_bridge.dev = dev;
- agp_bridge.type = VIA_APOLLO_KT400_3;
- agp_bridge.capndx = cap_ptr;
- agp_bridge.masks = via_generic_masks;
- agp_bridge.aperture_sizes = (void *) via_generic_sizes;
- agp_bridge.size_type = U8_APER_SIZE;
- agp_bridge.num_aperture_sizes = 7;
- agp_bridge.dev_private_data = NULL;
- agp_bridge.needs_scratch_page = FALSE;
- agp_bridge.agp_enable = via_kt400_enable;
- agp_bridge.configure = via_configure;
- agp_bridge.fetch_size = via_fetch_size;
- agp_bridge.cleanup = via_cleanup;
- agp_bridge.tlb_flush = via_tlbflush;
- agp_bridge.mask_memory = via_mask_memory;
- agp_bridge.cache_flush = global_cache_flush;
- agp_bridge.create_gatt_table = agp_generic_create_gatt_table;
- agp_bridge.free_gatt_table = agp_generic_free_gatt_table;
- agp_bridge.insert_memory = agp_generic_insert_memory;
- agp_bridge.remove_memory = agp_generic_remove_memory;
- agp_bridge.alloc_by_type = agp_generic_alloc_by_type;
- agp_bridge.free_by_type = agp_generic_free_by_type;
- agp_bridge.agp_alloc_page = agp_generic_alloc_page;
- agp_bridge.agp_destroy_page = agp_generic_destroy_page;
- agp_bridge.suspend = agp_generic_suspend;
- agp_bridge.resume = agp_generic_resume;
- agp_bridge.cant_use_aperture = 0;
-
- /* Fill in the mode register */
- pci_read_config_dword(agp_bridge.dev, agp_bridge.capndx+PCI_AGP_STATUS, &agp_bridge.mode);
-
- via_kt400_agp_driver.dev = dev;
- agp_register_driver(&via_kt400_agp_driver);
- return 0;
-}
-
-static struct pci_device_id agp_via_pci_table[] __initdata = {
- {
- .class = (PCI_CLASS_BRIDGE_HOST << 8),
- .class_mask = ~0,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_8377_0,
- .subvendor = PCI_ANY_ID,
- .subdevice = PCI_ANY_ID,
- },
- { }
-};
-
-MODULE_DEVICE_TABLE(pci, agp_via_pci_table);
-
-static struct __initdata pci_driver agp_via_pci_driver = {
- .name = "agpgart-via",
- .id_table = agp_via_pci_table,
- .probe = agp_via_probe,
-};
-
-static int __init agp_via_init(void)
-{
- int ret_val;
-
- ret_val = pci_module_init(&agp_via_pci_driver);
- if (ret_val)
- agp_bridge.type = NOT_SUPPORTED;
-
- return ret_val;
-}
-
-static void __exit agp_via_cleanup(void)
-{
- agp_unregister_driver(&via_kt400_agp_driver);
- pci_unregister_driver(&agp_via_pci_driver);
-}
-
-module_init(agp_via_init);
-module_exit(agp_via_cleanup);
-
-MODULE_AUTHOR("Dave Jones ");
-MODULE_LICENSE("GPL and additional rights");
-
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/amd76x_pm.c linux-2.5/drivers/char/amd76x_pm.c
--- linux-2.5.60/drivers/char/amd76x_pm.c 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/drivers/char/amd76x_pm.c 2003-01-17 00:57:52.000000000 -0100
@@ -0,0 +1,688 @@
+/*
+ * ACPI sytle PM for SMP AMD-760MP(X) based systems.
+ * For use until the ACPI project catches up. :-)
+ *
+ * Copyright (C) 2002 Johnathan Hicks
+ *
+ * History:
+ *
+ * 20020702 - amd-smp-idle: Tony Lindgren
+ * Influenced by Vcool, and LVCool. Rewrote everything from scratch to
+ * use the PCI features in Linux, and to support SMP systems. Provides
+ * C2 idling on SMP AMD-760MP systems.
+ *
+ * 20020722: JH
+ * I adapted Tony's code for the AMD-765/766 southbridge and adapted it
+ * according to the AMD-768 data sheet to provide the same capability for
+ * SMP AMD-760MPX systems. Posted to acpi-devel list.
+ *
+ * 20020722: Alan Cox
+ * Replaces non-functional amd76x_pm code in -ac tree.
+ *
+ * 20020730: JH
+ * Added ability to do normal throttling (the non-thermal kind), C3 idling
+ * and Power On Suspend (S1 sleep). It would be very easy to tie swsusp
+ * into activate_amd76x_SLP(). C3 idling doesn't happen yet; see my note
+ * in amd76x_smp_idle(). I've noticed that when NTH and idling are both
+ * enabled, my hardware locks and requires a hard reset, so I have
+ * #ifndefed around the idle loop setting to prevent this. POS locks it up
+ * too, both ought to be fixable. I've also noticed that idling and NTH
+ * make some interference that is picked up by the onboard sound chip on
+ * my ASUS A7M266-D motherboard.
+ *
+ *
+ * TODO: Thermal throttling (TTH).
+ * /proc interface for normal throttling level.
+ * /proc interface for POS.
+ *
+ *
+ *
+ *
+ * Processor idle mode module for AMD SMP 760MP(X) based systems
+ *
+ * Copyright (C) 2002 Tony Lindgren
+ * Johnathan Hicks (768 support)
+ *
+ * Using this module saves about 70 - 90W of energy in the idle mode compared
+ * to the default idle mode. Waking up from the idle mode is fast to keep the
+ * system response time good. Currently no CPU load calculation is done, the
+ * system exits the idle mode if the idle function runs twice on the same
+ * processor in a row. This only works on SMP systems, but maybe the idle mode
+ * enabling can be integrated to ACPI to provide C2 mode at some point.
+ *
+ * NOTE: Currently there's a bug somewhere where the reading the
+ * P_LVL2 for the first time causes the system to sleep instead of
+ * idling. This means that you need to hit the power button once to
+ * wake the system after loading the module for the first time after
+ * reboot. After that the system idles as supposed.
+ *
+ *
+ * Influenced by Vcool, and LVCool. Rewrote everything from scratch to
+ * use the PCI features in Linux, and to support SMP systems.
+ *
+ * Currently only tested on a TYAN S2460 (760MP) system (Tony) and an
+ * ASUS A7M266-D (760MPX) system (Johnathan). Adding support for other Athlon
+ * SMP or single processor systems should be easy if desired.
+ *
+ * This software is licensed under GNU General Public License Version 2
+ * as specified in file COPYING in the Linux kernel source tree main
+ * directory.
+ *
+ *
+ */
+
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "amd76x_pm.h"
+
+#define VERSION "20020730"
+
+// #define AMD76X_C3 1
+// #define AMD76X_NTH 1
+// #define AMD76X_POS 1
+
+
+extern void default_idle(void);
+static void amd76x_smp_idle(void);
+static int amd76x_pm_main(void);
+static int __devinit amd_nb_init(struct pci_dev *pdev,
+ const struct pci_device_id *ent);
+static void amd_nb_remove(struct pci_dev *pdev);
+static int __devinit amd_sb_init(struct pci_dev *pdev,
+ const struct pci_device_id *ent);
+static void amd_sb_remove(struct pci_dev *pdev);
+
+
+static struct pci_dev *pdev_nb;
+static struct pci_dev *pdev_sb;
+
+struct PM_cfg {
+ unsigned int status_reg;
+ unsigned int C2_reg;
+ unsigned int C3_reg;
+ unsigned int NTH_reg;
+ unsigned int slp_reg;
+ unsigned int resume_reg;
+ void (*orig_idle) (void);
+ void (*curr_idle) (void);
+ unsigned long C2_cnt, C3_cnt;
+ int last_pr;
+};
+static struct PM_cfg amd76x_pm_cfg;
+
+struct cpu_idle_state {
+ int idle;
+ int count;
+};
+static struct cpu_idle_state prs[2];
+
+static struct pci_device_id amd_nb_tbl[] __devinitdata = {
+ {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, PCI_ANY_ID, PCI_ANY_ID,},
+ {0,}
+};
+
+static struct pci_device_id amd_sb_tbl[] __devinitdata = {
+ {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7413, PCI_ANY_ID, PCI_ANY_ID,},
+ {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7443, PCI_ANY_ID, PCI_ANY_ID,},
+ {0,}
+};
+
+static struct pci_driver amd_nb_driver = {
+ name:"amd76x_pm-nb",
+ id_table:amd_nb_tbl,
+ probe:amd_nb_init,
+ remove:__devexit_p(amd_nb_remove),
+};
+
+static struct pci_driver amd_sb_driver = {
+ name:"amd76x_pm-sb",
+ id_table:amd_sb_tbl,
+ probe:amd_sb_init,
+ remove:__devexit_p(amd_sb_remove),
+};
+
+
+static int __devinit
+amd_nb_init(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+ pdev_nb = pdev;
+ printk(KERN_INFO "amd76x_pm: Initializing northbridge %s\n",
+ pdev_nb->name);
+
+ return 0;
+}
+
+
+static void __devexit
+amd_nb_remove(struct pci_dev *pdev)
+{
+}
+
+
+static int __devinit
+amd_sb_init(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+ pdev_sb = pdev;
+ printk(KERN_INFO "amd76x_pm: Initializing southbridge %s\n",
+ pdev_sb->name);
+
+ return 0;
+}
+
+
+static void __devexit
+amd_sb_remove(struct pci_dev *pdev)
+{
+}
+
+
+/*
+ * Configures the AMD-762 northbridge to support PM calls
+ */
+static int
+config_amd762(int enable)
+{
+ unsigned int regdword;
+
+ /* Enable STPGNT in BIU Status/Control for cpu0 */
+ pci_read_config_dword(pdev_nb, 0x60, ®dword);
+ regdword |= (1 << 17);
+ pci_write_config_dword(pdev_nb, 0x60, regdword);
+
+ /* Enable STPGNT in BIU Status/Control for cpu1 */
+ pci_read_config_dword(pdev_nb, 0x68, ®dword);
+ regdword |= (1 << 17);
+ pci_write_config_dword(pdev_nb, 0x68, regdword);
+
+ /* DRAM refresh enable */
+ pci_read_config_dword(pdev_nb, 0x58, ®dword);
+ regdword &= ~(1 << 19);
+ pci_write_config_dword(pdev_nb, 0x58, regdword);
+
+ /* Self refresh enable */
+ pci_read_config_dword(pdev_nb, 0x70, ®dword);
+ regdword |= (1 << 18);
+ pci_write_config_dword(pdev_nb, 0x70, regdword);
+
+ return 0;
+}
+
+
+/*
+ * Get the base PMIO address and set the pm registers in amd76x_pm_cfg.
+ */
+static void
+amd76x_get_PM(void)
+{
+ unsigned int regdword;
+
+ /* Get the address for pm status, P_LVL2, etc */
+ pci_read_config_dword(pdev_sb, 0x58, ®dword);
+ regdword &= 0xff80;
+ amd76x_pm_cfg.status_reg = (regdword + 0x00);
+ amd76x_pm_cfg.slp_reg = (regdword + 0x04);
+ amd76x_pm_cfg.NTH_reg = (regdword + 0x10);
+ amd76x_pm_cfg.C2_reg = (regdword + 0x14);
+ amd76x_pm_cfg.C3_reg = (regdword + 0x15);
+ amd76x_pm_cfg.resume_reg = (regdword + 0x16); /* N/A for 768 */
+}
+
+
+/*
+ * En/Disable PMIO and configure W4SG & STPGNT.
+ */
+static int
+config_PMIO_amd76x(int is_766, int enable)
+{
+ unsigned char regbyte;
+
+ /* Clear W4SG, and set PMIOEN, if using a 765/766 set STPGNT as well.
+ * AMD-766: C3A41; page 59 in AMD-766 doc
+ * AMD-768: DevB:3x41C; page 94 in AMD-768 doc */
+ pci_read_config_byte(pdev_sb, 0x41, ®byte);
+ if(enable) {
+ regbyte |= ((0 << 0) | (is_766?1:0 << 1) | (1 << 7));
+ }
+ else {
+ regbyte |= (0 << 7);
+ }
+ pci_write_config_byte(pdev_sb, 0x41, regbyte);
+
+ return 0;
+}
+
+/*
+ * C2 idle support for AMD-766.
+ */
+static void
+config_amd766_C2(int enable)
+{
+ unsigned int regdword;
+
+ /* Set C2 options in C3A50, page 63 in AMD-766 doc */
+ pci_read_config_dword(pdev_sb, 0x50, ®dword);
+ if(enable) {
+ regdword &= ~((DCSTOP_EN | CPUSTP_EN | PCISTP_EN | SUSPND_EN |
+ CPURST_EN) << C2_REGS);
+ regdword |= (STPCLK_EN /* ~ 20 Watt savings max */
+ | CPUSLP_EN) /* Additional ~ 70 Watts max! */
+ << C2_REGS;
+ }
+ else
+ regdword &= ~((STPCLK_EN | CPUSLP_EN) << C2_REGS);
+ pci_write_config_dword(pdev_sb, 0x50, regdword);
+}
+
+
+#ifdef AMD76X_C3
+/*
+ * Untested C3 idle support for AMD-766.
+ */
+static void
+config_amd766_C3(int enable)
+{
+ unsigned int regdword;
+
+ /* Set C3 options in C3A50, page 63 in AMD-766 doc */
+ pci_read_config_dword(pdev_sb, 0x50, ®dword);
+ if(enable) {
+ regdword &= ~((DCSTOP_EN | PCISTP_EN | SUSPND_EN | CPURST_EN)
+ << C3_REGS);
+ regdword |= (STPCLK_EN /* ~ 20 Watt savings max */
+ | CPUSLP_EN /* Additional ~ 70 Watts max! */
+ | CPUSTP_EN) /* yet more savings! */
+ << C3_REGS;
+ }
+ else
+ regdword &= ~((STPCLK_EN | CPUSLP_EN | CPUSTP_EN) << C3_REGS);
+ pci_write_config_dword(pdev_sb, 0x50, regdword);
+}
+#endif
+
+
+#ifdef AMD76X_POS
+static void
+config_amd766_POS(int enable)
+{
+ unsigned int regdword;
+
+ /* Set C3 options in C3A50, page 63 in AMD-766 doc */
+ pci_read_config_dword(pdev_sb, 0x50, ®dword);
+ if(enable) {
+ regdword &= ~((ZZ_CACHE_EN | CPURST_EN) << POS_REGS);
+ regdword |= ((DCSTOP_EN | STPCLK_EN | CPUSTP_EN | PCISTP_EN |
+ CPUSLP_EN | SUSPND_EN) << POS_REGS);
+ }
+ else
+ regdword ^= (0xff << POS_REGS);
+ pci_write_config_dword(pdev_sb, 0x50, regdword);
+}
+#endif
+
+
+/*
+ * Configures the 765 & 766 southbridges.
+ */
+static int
+config_amd766(int enable)
+{
+ amd76x_get_PM();
+ config_PMIO_amd76x(1, 1);
+
+ config_amd766_C2(enable);
+#ifdef AMD76X_C3
+ config_amd766_C3(enable);
+#endif
+#ifdef AMD76X_POS
+ config_amd766_POS(enable);
+#endif
+
+ return 0;
+}
+
+
+/*
+ * C2 idling support for AMD-768.
+ */
+static void
+config_amd768_C2(int enable)
+{
+ unsigned char regbyte;
+
+ /* Set C2 options in DevB:3x4F, page 100 in AMD-768 doc */
+ pci_read_config_byte(pdev_sb, 0x4F, ®byte);
+ if(enable)
+ regbyte |= C2EN;
+ else
+ regbyte ^= C2EN;
+ pci_write_config_byte(pdev_sb, 0x4F, regbyte);
+}
+
+
+#ifdef AMD76X_C3
+/*
+ * C3 idle support for AMD-768. The idle loop would need some extra
+ * handling for C3, but it would make more sense for ACPI to handle CX level
+ * transitions like it is supposed to. Unfortunately ACPI doesn't do CX
+ * levels on SMP systems yet.
+ */
+static void
+config_amd768_C3(int enable)
+{
+ unsigned char regbyte;
+
+ /* Set C3 options in DevB:3x4F, page 100 in AMD-768 doc */
+ pci_read_config_byte(pdev_sb, 0x4F, ®byte);
+ if(enable)
+ regbyte |= (C3EN /* | ZZ_C3EN | CSLP_C3EN | CSTP_C3EN */);
+ else
+ regbyte ^= C3EN;
+ pci_write_config_byte(pdev_sb, 0x4F, regbyte);
+}
+#endif
+
+
+#ifdef AMD76X_POS
+/*
+ * Untested Power On Suspend support for AMD-768. This should also be handled
+ * by ACPI.
+ */
+static void
+config_amd768_POS(int enable)
+{
+ unsigned int regdword;
+
+ /* Set POS options in DevB:3x50, page 101 in AMD-768 doc */
+ pci_read_config_dword(pdev_sb, 0x50, ®dword);
+ if(enable)
+ regdword |= (POSEN | CSTP | PSTP | ASTP | DCSTP | CSLP | SUSP);
+ else
+ regdword ^= POSEN;
+ pci_write_config_dword(pdev_sb, 0x50, regdword);
+}
+#endif
+
+
+#ifdef AMD76X_NTH
+/*
+ * Normal Throttling support for AMD-768. There are several settings
+ * that can be set depending on how long you want some of the delays to be.
+ * I'm not sure if this is even neccessary at all as the 766 doesn't need this.
+ */
+static void
+config_amd768_NTH(int enable, int ntper, int thminen)
+{
+ unsigned char regbyte;
+
+ /* DevB:3x40, pg 93 of 768 doc */
+ pci_read_config_byte(pdev_sb, 0x40, ®byte);
+ /* Is it neccessary to use THMINEN at ANY time? */
+ regbyte |= (NTPER(ntper) | THMINEN(thminen));
+ pci_write_config_byte(pdev_sb, 0x40, regbyte);
+}
+#endif
+
+
+/*
+ * Configures the 768 southbridge to support idle calls, and gets
+ * the processor idle call register location.
+ */
+static int
+config_amd768(int enable)
+{
+ amd76x_get_PM();
+ config_PMIO_amd76x(0, 1);
+
+ config_amd768_C2(enable);
+#ifdef AMD76X_C3
+ config_amd768_C3(enable);
+#endif
+#ifdef AMD76X_POS
+ config_amd768_POS(enable);
+#endif
+#ifdef AMD76X_NTH
+ config_amd768_NTH(enable, 1, 2);
+#endif
+
+ return 0;
+}
+
+
+#ifdef AMD76X_NTH
+/*
+ * Activate normal throttling via its ACPI register (P_CNT).
+ */
+static void
+activate_amd76x_NTH(int enable, int ratio)
+{
+ unsigned int regdword;
+
+ /* PM10, pg 110 of 768 doc, pg 70 of 766 doc */
+ regdword=inl(amd76x_pm_cfg.NTH_reg);
+ if(enable)
+ regdword |= (NTH_EN | NTH_RATIO(ratio));
+ else
+ regdword ^= NTH_EN;
+ outl(regdword, amd76x_pm_cfg.NTH_reg);
+}
+#endif
+
+
+/*
+ * Activate sleep state via its ACPI register (PM1_CNT).
+ */
+static void
+activate_amd76x_SLP(int type)
+{
+ unsigned short regshort;
+
+ /* PM04, pg 109 of 768 doc, pg 69 of 766 doc */
+ regshort=inw(amd76x_pm_cfg.slp_reg);
+ regshort |= (SLP_EN | SLP_TYP(type)) ;
+ outw(regshort, amd76x_pm_cfg.slp_reg);
+}
+
+
+#ifdef AMD76X_POS
+/*
+ * Wrapper function to activate POS sleep state.
+ */
+static void
+activate_amd76x_POS(void)
+{
+ activate_amd76x_SLP(1);
+}
+#endif
+
+
+#if 0
+/*
+ * Idle loop for single processor systems
+ */
+void
+amd76x_up_idle(void)
+{
+ // FIXME: Optionally add non-smp idle loop here
+}
+#endif
+
+
+/*
+ * Idle loop for SMP systems, supports currently only 2 processors.
+ *
+ * Note; for 2.5 folks - not pre-empt safe
+ */
+static void
+amd76x_smp_idle(void)
+{
+
+ /*
+ * Exit idle mode immediately if the CPU does not change.
+ * Usually that means that we have some load on another CPU.
+ */
+ if (prs[0].idle && prs[1].idle && amd76x_pm_cfg.last_pr == smp_processor_id()) {
+ prs[0].idle = 0;
+ prs[1].idle = 0;
+ /* This looks redundent as it was just checked in the if() */
+ /* amd76x_pm_cfg.last_pr = smp_processor_id(); */
+ return;
+ }
+
+ prs[smp_processor_id()].count++;
+
+ /* Don't start the idle mode immediately */
+ if (prs[smp_processor_id()].count >= LAZY_IDLE_DELAY) {
+
+ /* Put the current processor into idle mode */
+ prs[smp_processor_id()].idle =
+ (prs[smp_processor_id()].idle ? 2 : 1);
+
+ /* Only idle if both processors are idle */
+ if ((prs[0].idle==1) && (prs[1].idle==1)) {
+ amd76x_pm_cfg.C2_cnt++;
+ inb(amd76x_pm_cfg.C2_reg);
+ }
+ #ifdef AMD76X_C3
+ /*
+ * JH: I've not been able to get into here. Could this have
+ * something to do with the way the kernel handles the idle
+ * loop, or and error that I've made?
+ */
+ else if ((prs[0].idle==2) && (prs[1].idle==2)) {
+ amd76x_pm_cfg.C3_cnt++;
+ inb(amd76x_pm_cfg.C3_reg);
+ }
+ #endif
+
+ prs[smp_processor_id()].count = 0;
+
+ }
+ amd76x_pm_cfg.last_pr = smp_processor_id();
+}
+
+
+/*
+ * Finds and initializes the bridges, and then sets the idle function
+ */
+static int
+amd76x_pm_main(void)
+{
+ int found;
+
+ /* Find northbridge */
+ found = pci_module_init(&amd_nb_driver);
+ if (found < 0) {
+ printk(KERN_ERR "amd76x_pm: Could not find northbridge\n");
+ return 1;
+ }
+
+ /* Find southbridge */
+ found = pci_module_init(&amd_sb_driver);
+ if (found < 0) {
+ printk(KERN_ERR "amd76x_pm: Could not find southbridge\n");
+ pci_unregister_driver(&amd_nb_driver);
+ return 1;
+ }
+
+ /* Init southbridge */
+ switch (pdev_sb->device) {
+ case PCI_DEVICE_ID_AMD_VIPER_7413: /* AMD-765 or 766 */
+ config_amd766(1);
+ break;
+ case PCI_DEVICE_ID_AMD_VIPER_7443: /* AMD-768 */
+ config_amd768(1);
+ break;
+ default:
+ printk(KERN_ERR "amd76x_pm: No southbridge to initialize\n");
+ break;
+ }
+
+ /* Init northbridge and queue the new idle function */
+ switch (pdev_nb->device) {
+ case PCI_DEVICE_ID_AMD_FE_GATE_700C: /* AMD-762 */
+ config_amd762(1);
+#ifndef AMD76X_NTH
+ amd76x_pm_cfg.curr_idle = amd76x_smp_idle;
+#endif
+ break;
+ default:
+ printk(KERN_ERR "amd76x_pm: No northbridge to initialize\n");
+ break;
+ }
+
+#ifndef AMD76X_NTH
+ if (!amd76x_pm_cfg.curr_idle) {
+ printk(KERN_ERR "amd76x_pm: Idle function not changed\n");
+ return 1;
+ }
+
+ amd76x_pm_cfg.orig_idle = pm_idle;
+ pm_idle = amd76x_pm_cfg.curr_idle;
+#endif
+
+#ifdef AMD76X_NTH
+ /* Turn NTH on with maxium throttling for testing. */
+ activate_amd76x_NTH(1, 1);
+#endif
+
+#ifdef AMD76X_POS
+ /* Testing here only. */
+ activate_amd76x_POS();
+#endif
+
+ return 0;
+}
+
+
+static int __init
+amd76x_pm_init(void)
+{
+ printk(KERN_INFO "amd76x_pm: Version %s\n", VERSION);
+ return amd76x_pm_main();
+}
+
+
+static void __exit
+amd76x_pm_cleanup(void)
+{
+#ifndef AMD76X_NTH
+ pm_idle = amd76x_pm_cfg.orig_idle;
+
+ /* This isn't really needed. */
+ printk(KERN_INFO "amd76x_pm: %lu C2 calls\n", amd76x_pm_cfg.C2_cnt);
+#ifdef AMD76X_C3
+ printk(KERN_INFO "amd76x_pm: %lu C3 calls\n", amd76x_pm_cfg.C3_cnt);
+#endif
+
+ /*
+ * FIXME: We want to wait until all CPUs have set the new
+ * idle function, otherwise we will oops. This may not be
+ * the right way to do it, but seems to work.
+ *
+ * - Best answer is going to be to ban unload, but when its debugged
+ * --- Alan
+ */
+ schedule();
+ mdelay(1000);
+#endif
+
+#ifdef AMD76X_NTH
+ /* Turn NTH off*/
+ activate_amd76x_NTH(0, 0);
+#endif
+
+ pci_unregister_driver(&amd_nb_driver);
+ pci_unregister_driver(&amd_sb_driver);
+
+}
+
+
+MODULE_LICENSE("GPL");
+module_init(amd76x_pm_init);
+module_exit(amd76x_pm_cleanup);
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/amd76x_pm.h linux-2.5/drivers/char/amd76x_pm.h
--- linux-2.5.60/drivers/char/amd76x_pm.h 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/drivers/char/amd76x_pm.h 2003-01-17 00:57:52.000000000 -0100
@@ -0,0 +1,59 @@
+/*
+ * Begin 765/766
+ */
+/* C2/C3/POS options in C3A50, page 63 in AMD-766 doc */
+#define ZZ_CACHE_EN 1
+#define DCSTOP_EN (1 << 1)
+#define STPCLK_EN (1 << 2)
+#define CPUSTP_EN (1 << 3)
+#define PCISTP_EN (1 << 4)
+#define CPUSLP_EN (1 << 5)
+#define SUSPND_EN (1 << 6)
+#define CPURST_EN (1 << 7)
+
+#define C2_REGS 0
+#define C3_REGS 8
+#define POS_REGS 16
+/*
+ * End 765/766
+ */
+
+
+/*
+ * Begin 768
+ */
+/* C2/C3 options in DevB:3x4F, page 100 in AMD-768 doc */
+#define C2EN 1
+#define C3EN (1 << 1)
+#define ZZ_C3EN (1 << 2)
+#define CSLP_C3EN (1 << 3)
+#define CSTP_C3EN (1 << 4)
+
+/* POS options in DevB:3x50, page 101 in AMD-768 doc */
+#define POSEN 1
+#define CSTP (1 << 2)
+#define PSTP (1 << 3)
+#define ASTP (1 << 4)
+#define DCSTP (1 << 5)
+#define CSLP (1 << 6)
+#define SUSP (1 << 8)
+#define MSRSM (1 << 14)
+#define PITRSM (1 << 15)
+
+/* NTH options DevB:3x40, pg 93 of 768 doc */
+#define NTPER(x) (x << 3)
+#define THMINEN(x) (x << 4)
+
+/*
+ * End 768
+ */
+
+/* NTH activate. PM10, pg 110 of 768 doc, pg 70 of 766 doc */
+#define NTH_RATIO(x) (x << 1)
+#define NTH_EN (1 << 4)
+
+/* Sleep state. PM04, pg 109 of 768 doc, pg 69 of 766 doc */
+#define SLP_EN (1 << 13)
+#define SLP_TYP(x) (x << 10)
+
+#define LAZY_IDLE_DELAY 800 /* 0: Best savings, 3000: More responsive */
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/dummy_keyb.c linux-2.5/drivers/char/dummy_keyb.c
--- linux-2.5.60/drivers/char/dummy_keyb.c 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/drivers/char/dummy_keyb.c 2003-01-17 00:57:52.000000000 -0100
@@ -0,0 +1,60 @@
+/*
+ * linux/drivers/char/dummy_keyb.c
+ *
+ * Allows CONFIG_VT on hardware without keyboards.
+ *
+ * Copyright (C) 1999, 2001 Bradley D. LaRonde
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * What is this for?
+ *
+ * Not all systems have keyboards. Some don't even have a keyboard
+ * port. However, some of those systems have video support and can
+ * use the virtual terminal support for display. However, the virtual
+ * terminal code expects a keyboard of some kind. This driver keeps
+ * the virtual terminal code happy by providing it a "keyboard", albeit
+ * a very quiet one.
+ *
+ * If you want to use the virtual terminal support but your system
+ * does not support a keyboard, define CONFIG_DUMMY_KEYB along with
+ * CONFIG_VT.
+ *
+ */
+#include
+#include
+#include
+
+void kbd_leds(unsigned char leds)
+{
+}
+
+int kbd_setkeycode(unsigned int scancode, unsigned int keycode)
+{
+ return (scancode == keycode) ? 0 : -EINVAL;
+}
+
+int kbd_getkeycode(unsigned int scancode)
+{
+ return scancode;
+}
+
+int kbd_translate(unsigned char scancode, unsigned char *keycode,
+ char raw_mode)
+{
+ *keycode = scancode;
+
+ return 1;
+}
+
+char kbd_unexpected_up(unsigned char keycode)
+{
+ return 0x80;
+}
+
+void __init kbd_init_hw(void)
+{
+ printk("Dummy keyboard driver installed.\n");
+}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/ftape/lowlevel/ftape-calibr.c linux-2.5/drivers/char/ftape/lowlevel/ftape-calibr.c
--- linux-2.5.60/drivers/char/ftape/lowlevel/ftape-calibr.c 2003-02-10 17:38:15.000000000 -0100
+++ linux-2.5/drivers/char/ftape/lowlevel/ftape-calibr.c 2003-01-17 00:57:57.000000000 -0100
@@ -31,7 +31,10 @@
#include
#if defined(__alpha__)
# include
-#elif defined(__i386__) || defined(__x86_64__)
+#elif defined(__x86_64__)
+# include
+# include
+#elif defined(__i386__)
# include
#endif
#include
@@ -45,10 +48,14 @@
# error Ftape is not implemented for this architecture!
#endif
-#if defined(__alpha__)
+#if defined(__alpha__) || defined(__x86_64__)
static unsigned long ps_per_cycle = 0;
#endif
+#if defined(__i386__)
+extern spinlock_t i8253_lock;
+#endif
+
/*
* Note: On Intel PCs, the clock ticks at 100 Hz (HZ==100) which is
* too slow for certain timeouts (and that clock doesn't even tick
@@ -67,48 +74,58 @@ unsigned int ftape_timestamp(void)
{
#if defined(__alpha__)
unsigned long r;
-
asm volatile ("rpcc %0" : "=r" (r));
return r;
-#elif defined(__i386__) || defined(__x86_64__)
+#elif defined(__x86_64__)
+ unsigned long r;
+ rdtscl(r);
+ return r;
+#elif defined(__i386__)
+
+/*
+ * Note that there is some time between counter underflowing and jiffies
+ * increasing, so the code below won't always give correct output.
+ * -Vojtech
+ */
+
unsigned long flags;
__u16 lo;
__u16 hi;
- save_flags(flags);
- cli();
+ spin_lock_irqsave(&i8253_lock, flags);
outb_p(0x00, 0x43); /* latch the count ASAP */
lo = inb_p(0x40); /* read the latched count */
lo |= inb(0x40) << 8;
hi = jiffies;
- restore_flags(flags);
+ spin_unlock_irqrestore(&i8253_lock, flags);
+
return ((hi + 1) * (unsigned int) LATCH) - lo; /* downcounter ! */
#endif
}
static unsigned int short_ftape_timestamp(void)
{
-#if defined(__alpha__)
+#if defined(__alpha__) || defined(__x86_64__)
return ftape_timestamp();
-#elif defined(__i386__) || defined(__x86_64__)
+#elif defined(__i386__)
unsigned int count;
unsigned long flags;
- save_flags(flags);
- cli();
+ spin_lock_irqsave(&i8253_lock, flags);
outb_p(0x00, 0x43); /* latch the count ASAP */
count = inb_p(0x40); /* read the latched count */
count |= inb(0x40) << 8;
- restore_flags(flags);
+ spin_unlock_irqrestore(&i8253_lock, flags);
+
return (LATCH - count); /* normal: downcounter */
#endif
}
static unsigned int diff(unsigned int t0, unsigned int t1)
{
-#if defined(__alpha__)
- return (t1 <= t0) ? t1 + (1UL << 32) - t0 : t1 - t0;
-#elif defined(__i386__) || defined(__x86_64__)
+#if defined(__alpha__) || defined(__x86_64__)
+ return (t1 - t0);
+#elif defined(__i386__)
/*
* This is tricky: to work for both short and full ftape_timestamps
* we'll have to discriminate between these.
@@ -122,9 +139,9 @@ static unsigned int diff(unsigned int t0
static unsigned int usecs(unsigned int count)
{
-#if defined(__alpha__)
+#if defined(__alpha__) || defined(__x86_64__)
return (ps_per_cycle * count) / 1000000UL;
-#elif defined(__i386__) || defined(__x86_64__)
+#elif defined(__i386__)
return (10000 * count) / ((CLOCK_TICK_RATE + 50) / 100);
#endif
}
@@ -153,49 +170,24 @@ static void time_inb(void)
save_flags(flags);
cli();
t0 = short_ftape_timestamp();
- for (i = 0; i < 1000; ++i) {
+ for (i = 0; i < 1000; ++i)
status = inb(fdc.msr);
- }
t1 = short_ftape_timestamp();
restore_flags(flags);
+
TRACE(ft_t_info, "inb() duration: %d nsec", ftape_timediff(t0, t1));
TRACE_EXIT;
}
static void init_clock(void)
{
-#if defined(__i386__) || defined(__x86_64__)
- unsigned int t;
- int i;
TRACE_FUN(ft_t_any);
- /* Haven't studied on why, but there sometimes is a problem
- * with the tick timer readout. The two bytes get swapped.
- * This hack solves that problem by doing one extra input.
- */
- for (i = 0; i < 1000; ++i) {
- t = short_ftape_timestamp();
- if (t > LATCH) {
- inb_p(0x40); /* get in sync again */
- TRACE(ft_t_warn, "clock counter fixed");
- break;
- }
- }
+#if defined(__x86_64__)
+ ps_per_cycle = 1000000000UL / cpu_khz;
#elif defined(__alpha__)
-#if CONFIG_FT_ALPHA_CLOCK == 0
-#error You must define and set CONFIG_FT_ALPHA_CLOCK in 'make config' !
-#endif
extern struct hwrpb_struct *hwrpb;
- TRACE_FUN(ft_t_any);
-
- if (hwrpb->cycle_freq != 0) {
- ps_per_cycle = (1000*1000*1000*1000UL) / hwrpb->cycle_freq;
- } else {
- /*
- * HELP: Linux 2.0.x doesn't set cycle_freq on my noname !
- */
- ps_per_cycle = (1000*1000*1000*1000UL) / CONFIG_FT_ALPHA_CLOCK;
- }
+ ps_per_cycle = (1000*1000*1000*1000UL) / hwrpb->cycle_freq;
#endif
TRACE_EXIT;
}
@@ -214,7 +206,7 @@ void ftape_calibrate(char *name,
unsigned int tc = 0;
unsigned int count;
unsigned int time;
-#if defined(__i386__) || defined(__x86_64__)
+#if defined(__i386__)
unsigned int old_tc = 0;
unsigned int old_count = 1;
unsigned int old_time = 1;
@@ -257,15 +249,14 @@ void ftape_calibrate(char *name,
tc = (1000 * time) / (count - 1);
TRACE(ft_t_any, "once:%3d us,%6d times:%6d us, TC:%5d ns",
usecs(once), count - 1, usecs(multiple), tc);
-#if defined(__alpha__)
+#if defined(__alpha__) || defined(__x86_64__)
/*
* Increase the calibration count exponentially until the
* calibration time exceeds 100 ms.
*/
- if (time >= 100*1000) {
+ if (time >= 100*1000)
break;
- }
-#elif defined(__i386__) || defined(__x86_64__)
+#elif defined(__i386__)
/*
* increase the count until the resulting time nears 2/HZ,
* then the tc will drop sharply because we lose LATCH counts.
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/ftape/zftape/zftape-init.c linux-2.5/drivers/char/ftape/zftape/zftape-init.c
--- linux-2.5.60/drivers/char/ftape/zftape/zftape-init.c 2003-02-10 17:38:20.000000000 -0100
+++ linux-2.5/drivers/char/ftape/zftape/zftape-init.c 2003-02-04 15:43:50.000000000 -0100
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#include
#ifdef CONFIG_KMOD
#include
@@ -202,6 +203,7 @@ static int zft_mmap(struct file *filep,
static struct vm_operations_struct dummy = { NULL, };
vma->vm_ops = &dummy;
#endif
+ vma->vm_flags &= ~VM_IO;
}
current->blocked = old_sigmask; /* restore mask */
TRACE_EXIT result;
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/mem.c linux-2.5/drivers/char/mem.c
--- linux-2.5.60/drivers/char/mem.c 2003-02-10 17:38:38.000000000 -0100
+++ linux-2.5/drivers/char/mem.c 2003-01-06 15:44:09.000000000 -0100
@@ -190,10 +190,10 @@ static int mmap_mem(struct file * file,
vma->vm_flags |= VM_RESERVED;
/*
- * Don't dump addresses that are not real memory to a core file.
+ * Dump addresses that are real memory to a core file.
*/
- if (offset >= __pa(high_memory) || (file->f_flags & O_SYNC))
- vma->vm_flags |= VM_IO;
+ if (offset < __pa(high_memory) && !(file->f_flags & O_SYNC))
+ vma->vm_flags &= ~VM_IO;
if (remap_page_range(vma, vma->vm_start, offset, vma->vm_end-vma->vm_start,
vma->vm_page_prot))
@@ -466,6 +466,7 @@ static int mmap_zero(struct file * file,
return shmem_zero_setup(vma);
if (zeromap_page_range(vma, vma->vm_start, vma->vm_end - vma->vm_start, vma->vm_page_prot))
return -EAGAIN;
+ vma->vm_flags &= ~VM_IO;
return 0;
}
#else /* CONFIG_MMU */
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/n_tty.c linux-2.5/drivers/char/n_tty.c
--- linux-2.5.60/drivers/char/n_tty.c 2003-02-10 17:37:56.000000000 -0100
+++ linux-2.5/drivers/char/n_tty.c 2003-02-09 04:00:30.000000000 -0100
@@ -23,6 +23,11 @@
* 2000/01/20 Fixed SMP locking on put_tty_queue using bits of
* the patch by Andrew J. Kroll
* who actually finally proved there really was a race.
+ *
+ * 2002/03/18 Implemented n_tty_wakeup to send SIGIO POLL_OUTs to
+ * waiting writing processes-Sapan Bhatia .
+ * Also fixed a bug in BLOCKING mode where write_chan returns
+ * EAGAIN
*/
#include
@@ -707,6 +712,22 @@ static int n_tty_receive_room(struct tty
return 0;
}
+/*
+ * Required for the ptys, serial driver etc. since processes
+ * that attach themselves to the master and rely on ASYNC
+ * IO must be woken up
+ */
+
+static void n_tty_write_wakeup(struct tty_struct *tty)
+{
+ if (tty->fasync)
+ {
+ set_bit(TTY_DO_WRITE_WAKEUP, &tty->flags);
+ kill_fasync(&tty->fasync, SIGIO, POLL_OUT);
+ }
+ return;
+}
+
static void n_tty_receive_buf(struct tty_struct *tty, const unsigned char *cp,
char *fp, int count)
{
@@ -1156,6 +1177,8 @@ static ssize_t write_chan(struct tty_str
while (nr > 0) {
ssize_t num = opost_block(tty, b, nr);
if (num < 0) {
+ if (num == -EAGAIN)
+ break;
retval = num;
goto break_out;
}
@@ -1235,6 +1258,6 @@ struct tty_ldisc tty_ldisc_N_TTY = {
normal_poll, /* poll */
n_tty_receive_buf, /* receive_buf */
n_tty_receive_room, /* receive_room */
- 0 /* write_wakeup */
+ n_tty_write_wakeup /* write_wakeup */
};
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/nvram.c linux-2.5/drivers/char/nvram.c
--- linux-2.5.60/drivers/char/nvram.c 2003-02-10 17:38:21.000000000 -0100
+++ linux-2.5/drivers/char/nvram.c 2003-02-09 04:00:30.000000000 -0100
@@ -231,8 +231,7 @@ nvram_set_checksum(void)
* The are the file operation function for user access to /dev/nvram
*/
-static long long
-nvram_llseek(struct file *file, loff_t offset, int origin)
+static loff_t nvram_llseek(struct file *file,loff_t offset, int origin )
{
lock_kernel();
switch (origin) {
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/nwflash.c linux-2.5/drivers/char/nwflash.c
--- linux-2.5.60/drivers/char/nwflash.c 2003-02-10 17:39:16.000000000 -0100
+++ linux-2.5/drivers/char/nwflash.c 2003-01-06 14:40:10.000000000 -0100
@@ -47,7 +47,7 @@ static int write_block(unsigned long p,
static int flash_ioctl(struct inode *inodep, struct file *filep, unsigned int cmd, unsigned long arg);
static ssize_t flash_read(struct file *file, char *buf, size_t count, loff_t * ppos);
static ssize_t flash_write(struct file *file, const char *buf, size_t count, loff_t * ppos);
-static long long flash_llseek(struct file *file, long long offset, int orig);
+static loff_t flash_llseek(struct file *file, loff_t offset, int orig);
#define KFLASH_SIZE 1024*1024 //1 Meg
#define KFLASH_SIZE4 4*1024*1024 //4 Meg
@@ -301,9 +301,9 @@ static ssize_t flash_write(struct file *
* also note that seeking relative to the "end of file" isn't supported:
* it has no meaning, so it returns -EINVAL.
*/
-static long long flash_llseek(struct file *file, long long offset, int orig)
+static loff_t flash_llseek(struct file *file, loff_t offset, int orig)
{
- long long ret;
+ loff_t ret;
lock_kernel();
if (flashdebug)
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/rio/rioroute.c linux-2.5/drivers/char/rio/rioroute.c
--- linux-2.5.60/drivers/char/rio/rioroute.c 2003-02-10 17:38:42.000000000 -0100
+++ linux-2.5/drivers/char/rio/rioroute.c 2003-02-11 03:10:50.000000000 -0100
@@ -763,7 +763,7 @@ uint UnitId;
#endif
UnitId--; /* this trick relies on the Unit Id being UNSIGNED! */
- if ( UnitId > MAX_RUP ) /* dontcha just lurv unsigned maths! */
+ if ( UnitId >= MAX_RUP ) /* dontcha just lurv unsigned maths! */
return(0);
if ( HostP->Mapping[UnitId].Flags & BEEN_HERE )
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/rtc.c linux-2.5/drivers/char/rtc.c
--- linux-2.5.60/drivers/char/rtc.c 2003-02-10 17:38:27.000000000 -0100
+++ linux-2.5/drivers/char/rtc.c 2003-02-11 10:49:29.000000000 -0100
@@ -47,7 +47,7 @@
#define RTC_VERSION "1.11"
-#define RTC_IO_EXTENT 0x10 /* Only really two ports, but... */
+#define RTC_IO_EXTENT 0x2
/*
* Note that *all* calls to CMOS_READ and CMOS_WRITE are done with
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/specialix.c linux-2.5/drivers/char/specialix.c
--- linux-2.5.60/drivers/char/specialix.c 2003-02-10 17:38:53.000000000 -0100
+++ linux-2.5/drivers/char/specialix.c 2003-02-11 03:10:50.000000000 -0100
@@ -1456,7 +1456,7 @@ static int sx_open(struct tty_struct * t
board = SX_BOARD(minor(tty->device));
- if (board > SX_NBOARD || !(sx_board[board].flags & SX_BOARD_PRESENT))
+ if (board >= SX_NBOARD || !(sx_board[board].flags & SX_BOARD_PRESENT))
return -ENODEV;
bp = &sx_board[board];
@@ -2363,7 +2363,7 @@ int specialix_init(void)
struct pci_dev *pdev = NULL;
i=0;
- while (i <= SX_NBOARD) {
+ while (i < SX_NBOARD) {
if (sx_board[i].flags & SX_BOARD_PRESENT) {
i++;
continue;
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/stallion.c linux-2.5/drivers/char/stallion.c
--- linux-2.5.60/drivers/char/stallion.c 2003-02-10 17:38:48.000000000 -0100
+++ linux-2.5/drivers/char/stallion.c 2003-01-17 00:57:53.000000000 -0100
@@ -188,14 +188,6 @@ static stlport_t stl_dummyport;
*/
static char stl_unwanted[SC26198_RXFIFOSIZE];
-/*
- * Keep track of what interrupts we have requested for us.
- * We don't need to request an interrupt twice if it is being
- * shared with another Stallion board.
- */
-static int stl_gotintrs[STL_MAXBRDS];
-static int stl_numintrs;
-
/*****************************************************************************/
static stlbrd_t *stl_brds[STL_MAXBRDS];
@@ -520,7 +512,6 @@ static int stl_readproc(char *page, char
static int stl_brdinit(stlbrd_t *brdp);
static int stl_initports(stlbrd_t *brdp, stlpanel_t *panelp);
-static int stl_mapirq(int irq, char *name);
static int stl_getserial(stlport_t *portp, struct serial_struct *sp);
static int stl_setserial(stlport_t *portp, struct serial_struct *sp);
static int stl_getbrdstats(combrd_t *bp);
@@ -836,6 +827,7 @@ static void __exit stallion_module_exit(
}
kfree(panelp);
}
+ free_irq(brdp->irq, brdp);
release_region(brdp->ioaddr1, brdp->iosize1);
if (brdp->iosize2 > 0)
@@ -844,10 +836,6 @@ static void __exit stallion_module_exit(
kfree(brdp);
stl_brds[i] = (stlbrd_t *) NULL;
}
-
- for (i = 0; (i < stl_numintrs); i++)
- free_irq(stl_gotintrs[i], NULL);
-
restore_flags(flags);
}
@@ -2088,19 +2076,12 @@ stl_readdone:
static void stl_intr(int irq, void *dev_id, struct pt_regs *regs)
{
stlbrd_t *brdp;
- int i;
#if DEBUG
printk("stl_intr(irq=%d,regs=%x)\n", irq, (int) regs);
#endif
-
- for (i = 0; (i < stl_nrbrds); i++) {
- if ((brdp = stl_brds[i]) == (stlbrd_t *) NULL)
- continue;
- if (brdp->state == 0)
- continue;
- (* brdp->isr)(brdp);
- }
+ brdp = (stlbrd_t *) dev_id;
+ (* brdp->isr)(brdp);
}
/*****************************************************************************/
@@ -2275,39 +2256,6 @@ out:
/*****************************************************************************/
/*
- * Map in interrupt vector to this driver. Check that we don't
- * already have this vector mapped, we might be sharing this
- * interrupt across multiple boards.
- */
-
-static int __init stl_mapirq(int irq, char *name)
-{
- int rc, i;
-
-#if DEBUG
- printk("stl_mapirq(irq=%d,name=%s)\n", irq, name);
-#endif
-
- rc = 0;
- for (i = 0; (i < stl_numintrs); i++) {
- if (stl_gotintrs[i] == irq)
- break;
- }
- if (i >= stl_numintrs) {
- if (request_irq(irq, stl_intr, SA_SHIRQ, name, NULL) != 0) {
- printk("STALLION: failed to register interrupt "
- "routine for %s irq=%d\n", name, irq);
- rc = -ENODEV;
- } else {
- stl_gotintrs[stl_numintrs++] = irq;
- }
- }
- return(rc);
-}
-
-/*****************************************************************************/
-
-/*
* Initialize all the ports on a panel.
*/
@@ -2370,7 +2318,6 @@ static inline int stl_initeio(stlbrd_t *
stlpanel_t *panelp;
unsigned int status;
char *name;
- int rc;
#if DEBUG
printk("stl_initeio(brdp=%x)\n", (int) brdp);
@@ -2492,8 +2439,13 @@ static inline int stl_initeio(stlbrd_t *
brdp->nrpanels = 1;
brdp->state |= BRD_FOUND;
brdp->hwid = status;
- rc = stl_mapirq(brdp->irq, name);
- return(rc);
+ if (request_irq(brdp->irq, stl_intr, SA_SHIRQ, name, brdp) != 0) {
+ printk("STALLION: failed to register interrupt "
+ "routine for %s irq=%d\n", name, brdp->irq);
+ return -ENODEV;
+ }
+
+ return 0;
}
/*****************************************************************************/
@@ -2697,7 +2649,12 @@ static inline int stl_initech(stlbrd_t *
outb((brdp->ioctrlval | ECH_BRDDISABLE), brdp->ioctrl);
brdp->state |= BRD_FOUND;
- i = stl_mapirq(brdp->irq, name);
+ if (request_irq(brdp->irq, stl_intr, SA_SHIRQ, name, brdp) != 0) {
+ printk("STALLION: failed to register interrupt "
+ "routine for %s irq=%d\n", name, brdp->irq);
+ i = -ENODEV;
+ }
+
return(i);
}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/tty_io.c linux-2.5/drivers/char/tty_io.c
--- linux-2.5.60/drivers/char/tty_io.c 2003-02-10 17:38:43.000000000 -0100
+++ linux-2.5/drivers/char/tty_io.c 2003-02-06 03:15:33.000000000 -0100
@@ -1681,6 +1681,21 @@ static int send_break(struct tty_struct
return 0;
}
+static int tty_generic_brk(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg)
+{
+ if (cmd == TCSBRK && arg)
+ {
+ /* tcdrain case */
+ int retval = tty_check_change(tty);
+ if (retval)
+ return retval;
+ tty_wait_until_sent(tty, 0);
+ if (signal_pending(current))
+ return -EINTR;
+ }
+ return 0;
+}
+
/*
* Split this up, as gcc can choke on it otherwise..
*/
@@ -1714,11 +1729,12 @@ int tty_ioctl(struct inode * inode, stru
/* the driver doesn't support them. */
case TCSBRK:
case TCSBRKP:
- if (!tty->driver.ioctl)
- return 0;
- retval = tty->driver.ioctl(tty, file, cmd, arg);
+ retval = -ENOIOCTLCMD;
+ if (tty->driver.ioctl)
+ retval = tty->driver.ioctl(tty, file, cmd, arg);
+ /* Not driver handled */
if (retval == -ENOIOCTLCMD)
- retval = 0;
+ retval = tty_generic_brk(tty, file, cmd, arg);
return retval;
}
}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/tty_ioctl.c linux-2.5/drivers/char/tty_ioctl.c
--- linux-2.5.60/drivers/char/tty_ioctl.c 2003-02-10 17:39:16.000000000 -0100
+++ linux-2.5/drivers/char/tty_ioctl.c 2003-01-17 00:57:55.000000000 -0100
@@ -394,7 +394,7 @@ int n_tty_ioctl(struct tty_struct * tty,
return -EFAULT;
return 0;
case TCSETSF:
- return set_termios(real_tty, arg, TERMIOS_FLUSH);
+ return set_termios(real_tty, arg, TERMIOS_FLUSH | TERMIOS_WAIT);
case TCSETSW:
return set_termios(real_tty, arg, TERMIOS_WAIT);
case TCSETS:
@@ -402,7 +402,7 @@ int n_tty_ioctl(struct tty_struct * tty,
case TCGETA:
return get_termio(real_tty,(struct termio *) arg);
case TCSETAF:
- return set_termios(real_tty, arg, TERMIOS_FLUSH | TERMIOS_TERMIO);
+ return set_termios(real_tty, arg, TERMIOS_FLUSH | TERMIOS_WAIT | TERMIOS_TERMIO);
case TCSETAW:
return set_termios(real_tty, arg, TERMIOS_WAIT | TERMIOS_TERMIO);
case TCSETA:
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/watchdog/Makefile linux-2.5/drivers/char/watchdog/Makefile
--- linux-2.5.60/drivers/char/watchdog/Makefile 2003-02-10 17:38:47.000000000 -0100
+++ linux-2.5/drivers/char/watchdog/Makefile 2003-01-13 14:01:25.000000000 -0100
@@ -29,3 +29,5 @@ obj-$(CONFIG_SC520_WDT) += sc520_wdt.o
obj-$(CONFIG_ALIM7101_WDT) += alim7101_wdt.o
obj-$(CONFIG_SC1200_WDT) += sc1200wdt.o
obj-$(CONFIG_WAFER_WDT) += wafer5823wdt.o
+obj-$(CONFIG_AMD7XX_TCO) += amd7xx_tco.o
+
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/watchdog/amd7xx_tco.c linux-2.5/drivers/char/watchdog/amd7xx_tco.c
--- linux-2.5.60/drivers/char/watchdog/amd7xx_tco.c 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/drivers/char/watchdog/amd7xx_tco.c 2003-02-10 19:56:01.000000000 -0100
@@ -0,0 +1,377 @@
+/*
+ * AMD 766/768 TCO Timer Driver
+ * (c) Copyright 2002 Zwane Mwaikambo
+ * All Rights Reserved.
+ *
+ * Parts from;
+ * Hardware driver for the AMD 768 Random Number Generator (RNG)
+ * (c) Copyright 2001 Red Hat Inc
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * The author(s) of this software shall not be held liable for damages
+ * of any nature resulting due to the use of this software. This
+ * software is provided AS-IS with no warranties.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define AMDTCO_MODULE_VER "build 20020601"
+#define AMDTCO_MODULE_NAME "amd7xx_tco"
+#define PFX AMDTCO_MODULE_NAME ": "
+
+#define MAX_TIMEOUT 38 /* max of 38 seconds */
+
+/* pmbase registers */
+#define GLOBAL_SMI_REG 0x2a
+#define TCO_EN (1 << 1) /* bit 1 in global SMI register */
+#define TCO_RELOAD_REG 0x40 /* bits 0-5 are current count, 6-7 are reserved */
+#define TCO_INITVAL_REG 0x41 /* bits 0-5 are value to load, 6-7 are reserved */
+#define TCO_TIMEOUT_MASK 0x3f
+#define TCO_STATUS2_REG 0x46
+#define NDTO_STS2 (1 << 1) /* we're interested in the second timeout */
+#define BOOT_STS (1 << 2) /* will be set if NDTO_STS2 was set before reboot */
+#define TCO_CTRL1_REG 0x48
+#define TCO_HALT (1 << 11)
+
+static char banner[] __initdata = KERN_INFO PFX AMDTCO_MODULE_VER;
+static int timeout = 38;
+static u32 pmbase; /* PMxx I/O base */
+static struct pci_dev *dev;
+static struct semaphore open_sem;
+spinlock_t amdtco_lock; /* only for device access */
+static int expect_close = 0;
+
+MODULE_PARM(timeout, "i");
+MODULE_PARM_DESC(timeout, "range is 0-38 seconds, default is 38");
+
+static inline int amdtco_status(void)
+{
+ u16 reg;
+ int status = 0;
+
+ reg = inb(pmbase+TCO_CTRL1_REG);
+ if ((reg & TCO_HALT) == 0)
+ status |= WDIOF_KEEPALIVEPING;
+
+ reg = inb(pmbase+TCO_STATUS2_REG);
+ if (reg & BOOT_STS)
+ status |= WDIOF_CARDRESET;
+
+ return status;
+}
+
+static inline void amdtco_ping(void)
+{
+ u8 reg;
+
+ spin_lock(&amdtco_lock);
+ reg = inb(pmbase+TCO_RELOAD_REG);
+ outb(1 | reg, pmbase+TCO_RELOAD_REG);
+ spin_unlock(&amdtco_lock);
+}
+
+static inline int amdtco_gettimeout(void)
+{
+ return inb(TCO_RELOAD_REG) & TCO_TIMEOUT_MASK;
+}
+
+static inline void amdtco_settimeout(unsigned int timeout)
+{
+ u8 reg;
+
+ spin_lock(&amdtco_lock);
+ reg = inb(pmbase+TCO_INITVAL_REG);
+ reg |= timeout & TCO_TIMEOUT_MASK;
+ outb(reg, pmbase+TCO_INITVAL_REG);
+ spin_unlock(&amdtco_lock);
+}
+
+static inline void amdtco_global_enable(void)
+{
+ u16 reg;
+
+ spin_lock(&amdtco_lock);
+ reg = inw(pmbase+GLOBAL_SMI_REG);
+ reg |= TCO_EN;
+ outw(reg, pmbase+GLOBAL_SMI_REG);
+ spin_unlock(&amdtco_lock);
+}
+
+static inline void amdtco_enable(void)
+{
+ u16 reg;
+
+ spin_lock(&amdtco_lock);
+ reg = inw(pmbase+TCO_CTRL1_REG);
+ reg &= ~TCO_HALT;
+ outw(reg, pmbase+TCO_CTRL1_REG);
+ spin_unlock(&amdtco_lock);
+}
+
+static inline void amdtco_disable(void)
+{
+ u16 reg;
+
+ spin_lock(&amdtco_lock);
+ reg = inw(pmbase+TCO_CTRL1_REG);
+ reg |= TCO_HALT;
+ outw(reg, pmbase+TCO_CTRL1_REG);
+ spin_unlock(&amdtco_lock);
+}
+
+static int amdtco_fop_open(struct inode *inode, struct file *file)
+{
+ if (down_trylock(&open_sem))
+ return -EBUSY;
+
+#ifdef CONFIG_WATCHDOG_NOWAYOUT
+ MOD_INC_USE_COUNT;
+#endif
+
+ if (timeout > MAX_TIMEOUT)
+ timeout = MAX_TIMEOUT;
+
+ amdtco_settimeout(timeout);
+ amdtco_global_enable();
+ amdtco_ping();
+ printk(KERN_INFO PFX "Watchdog enabled, timeout = %d/%d seconds",
+ amdtco_gettimeout(), timeout);
+
+ return 0;
+}
+
+
+static int amdtco_fop_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
+{
+ int new_timeout;
+ int tmp;
+
+ static struct watchdog_info ident = {
+ .options = WDIOF_SETTIMEOUT | WDIOF_CARDRESET,
+ .identity = "AMD 766/768"
+ };
+
+ switch (cmd) {
+ default:
+ return -ENOTTY;
+
+ case WDIOC_GETSUPPORT:
+ if (copy_to_user((struct watchdog_info *)arg, &ident, sizeof ident))
+ return -EFAULT;
+ return 0;
+
+ case WDIOC_GETSTATUS:
+ return put_user(amdtco_status(), (int *)arg);
+
+ case WDIOC_KEEPALIVE:
+ amdtco_ping();
+ return 0;
+
+ case WDIOC_SETTIMEOUT:
+ if (get_user(new_timeout, (int *)arg))
+ return -EFAULT;
+
+ if (new_timeout < 0)
+ return -EINVAL;
+
+ if (new_timeout > MAX_TIMEOUT)
+ new_timeout = MAX_TIMEOUT;
+
+ timeout = new_timeout;
+ amdtco_settimeout(timeout);
+ /* fall through and return the new timeout */
+
+ case WDIOC_GETTIMEOUT:
+ return put_user(amdtco_gettimeout(), (int *)arg);
+
+ case WDIOC_SETOPTIONS:
+ if (copy_from_user(&tmp, (int *)arg, sizeof tmp))
+ return -EFAULT;
+
+ if (tmp & WDIOS_DISABLECARD)
+ amdtco_disable();
+
+ if (tmp & WDIOS_ENABLECARD)
+ amdtco_enable();
+
+ return 0;
+ }
+}
+
+
+static int amdtco_fop_release(struct inode *inode, struct file *file)
+{
+ if (expect_close) {
+ amdtco_disable();
+ printk(KERN_INFO PFX "Watchdog disabled\n");
+ } else {
+ amdtco_ping();
+ printk(KERN_CRIT PFX "Unexpected close!, timeout in %d seconds)\n", timeout);
+ }
+
+ up(&open_sem);
+ return 0;
+}
+
+
+static ssize_t amdtco_fop_write(struct file *file, const char *data, size_t len, loff_t *ppos)
+{
+ if (ppos != &file->f_pos)
+ return -ESPIPE;
+
+ if (len) {
+#ifndef CONFIG_WATCHDOG_NOWAYOUT
+ size_t i;
+ char c;
+ expect_close = 0;
+
+ for (i = 0; i != len; i++) {
+ if (get_user(c, data + i))
+ return -EFAULT;
+
+ if (c == 'V')
+ expect_close = 1;
+ }
+#endif
+ amdtco_ping();
+ return len;
+ }
+
+ return 0;
+}
+
+
+static int amdtco_notify_sys(struct notifier_block *this, unsigned long code, void *unused)
+{
+ if (code == SYS_DOWN || code == SYS_HALT)
+ amdtco_disable();
+
+ return NOTIFY_DONE;
+}
+
+
+static struct notifier_block amdtco_notifier =
+{
+ notifier_call: amdtco_notify_sys
+};
+
+static struct file_operations amdtco_fops =
+{
+ .owner = THIS_MODULE,
+ .write = amdtco_fop_write,
+ .ioctl = amdtco_fop_ioctl,
+ .open = amdtco_fop_open,
+ .release = amdtco_fop_release
+};
+
+static struct miscdevice amdtco_miscdev =
+{
+ .minor = WATCHDOG_MINOR,
+ .name = "watchdog",
+ .fops = &amdtco_fops
+};
+
+static struct pci_device_id amdtco_pci_tbl[] __initdata = {
+ /* AMD 766 PCI_IDs here */
+ { 0x1022, 0x7443, PCI_ANY_ID, PCI_ANY_ID, },
+ { 0, }
+};
+
+MODULE_DEVICE_TABLE (pci, amdtco_pci_tbl);
+
+static int __init amdtco_init(void)
+{
+ int ret;
+
+ sema_init(&open_sem, 1);
+ spin_lock_init(&amdtco_lock);
+
+ pci_for_each_dev(dev) {
+ if (pci_match_device (amdtco_pci_tbl, dev) != NULL)
+ goto found_one;
+ }
+
+ return -ENODEV;
+
+found_one:
+
+ if ((ret = register_reboot_notifier(&amdtco_notifier))) {
+ printk(KERN_ERR PFX "Unable to register reboot notifier err = %d\n", ret);
+ goto out_clean;
+ }
+
+ if ((ret = misc_register(&amdtco_miscdev))) {
+ printk(KERN_ERR PFX "Unable to register miscdev on minor %d\n", WATCHDOG_MINOR);
+ goto out_unreg_reboot;
+ }
+
+ pci_read_config_dword(dev, 0x58, &pmbase);
+ pmbase &= 0x0000FF00;
+
+ if (pmbase == 0) {
+ printk (KERN_ERR PFX "power management base not set\n");
+ ret = -EIO;
+ goto out_unreg_misc;
+ }
+
+ /* ret = 0; */
+ printk(banner);
+ goto out_clean;
+
+out_unreg_misc:
+ misc_deregister(&amdtco_miscdev);
+out_unreg_reboot:
+ unregister_reboot_notifier(&amdtco_notifier);
+out_clean:
+ return ret;
+}
+
+static void __exit amdtco_exit(void)
+{
+ misc_deregister(&amdtco_miscdev);
+ unregister_reboot_notifier(&amdtco_notifier);
+}
+
+
+#ifndef MODULE
+static int __init amdtco_setup(char *str)
+{
+ int ints[4];
+
+ str = get_options (str, ARRAY_SIZE(ints), ints);
+ if (ints[0] > 0)
+ timeout = ints[1];
+
+ return 1;
+}
+
+__setup("amd7xx_tco=", amdtco_setup);
+#endif
+
+module_init(amdtco_init);
+module_exit(amdtco_exit);
+
+MODULE_AUTHOR("Zwane Mwaikambo ");
+MODULE_DESCRIPTION("AMD 766/768 TCO Timer Driver");
+MODULE_LICENSE("GPL");
+EXPORT_NO_SYMBOLS;
+
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/char/watchdog/sc1200wdt.c linux-2.5/drivers/char/watchdog/sc1200wdt.c
--- linux-2.5.60/drivers/char/watchdog/sc1200wdt.c 2003-02-10 17:38:01.000000000 -0100
+++ linux-2.5/drivers/char/watchdog/sc1200wdt.c 2003-02-11 04:41:17.000000000 -0100
@@ -23,6 +23,7 @@
* Add WDIOC_GETBOOTSTATUS and WDIOC_SETOPTIONS ioctls
* Fix CONFIG_WATCHDOG_NOWAYOUT
* 20020530 Joel Becker Add Matt Domsch's nowayout module option
+ * 20030116 Adam Belay Updated to the latest pnp code
*
*/
@@ -35,7 +36,7 @@
#include
#include
#include
-#include
+#include
#include
#include
@@ -75,9 +76,9 @@ struct semaphore open_sem;
static char expect_close;
spinlock_t sc1200wdt_lock; /* io port access serialisation */
-#if defined CONFIG_ISAPNP || defined CONFIG_ISAPNP_MODULE
+#if defined CONFIG_PNP
static int isapnp = 1;
-static struct pci_dev *wdt_dev;
+static struct pnp_dev *wdt_dev;
MODULE_PARM(isapnp, "i");
MODULE_PARM_DESC(isapnp, "When set to 0 driver ISA PnP support will be disabled");
@@ -328,40 +329,49 @@ static int __init sc1200wdt_probe(void)
}
-#if defined CONFIG_ISAPNP || defined CONFIG_ISAPNP_MODULE
+#if defined CONFIG_PNP
-static int __init sc1200wdt_isapnp_probe(void)
+struct pnp_device_id scl200wdt_pnp_devices[] = {
+ /* National Semiconductor PC87307/PC97307 watchdog component */
+ {.id = "NSC0800", .driver_data = 0},
+ {.id = ""}
+};
+
+static int scl200wdt_pnp_probe(struct pnp_dev * dev, const struct pnp_device_id *dev_id)
{
- int ret;
+ /* this driver only supports one card at a time */
+ if (wdt_dev || !isapnp)
+ return -EBUSY;
- /* The WDT is logical device 8 on the main device */
- wdt_dev = isapnp_find_dev(NULL, ISAPNP_VENDOR('N','S','C'), ISAPNP_FUNCTION(0x08), NULL);
- if (!wdt_dev)
- return -ENODEV;
-
- if (wdt_dev->prepare(wdt_dev) < 0) {
- printk(KERN_ERR PFX "ISA PnP found device that could not be autoconfigured\n");
- return -EAGAIN;
- }
+ wdt_dev = dev;
+ io = pnp_port_start(wdt_dev, 0);
+ io_len = pnp_port_len(wdt_dev, 0);
- if (!(pci_resource_flags(wdt_dev, 0) & IORESOURCE_IO)) {
- printk(KERN_ERR PFX "ISA PnP could not find io ports\n");
- return -ENODEV;
+ if (!request_region(io, io_len, SC1200_MODULE_NAME)) {
+ printk(KERN_ERR PFX "Unable to register IO port %#x\n", io);
+ return -EBUSY;
}
- ret = wdt_dev->activate(wdt_dev);
- if (ret && (ret != -EBUSY))
- return -ENOMEM;
-
- /* io port resource overriding support? */
- io = pci_resource_start(wdt_dev, 0);
- io_len = pci_resource_len(wdt_dev, 0);
-
- printk(KERN_DEBUG PFX "ISA PnP found device at io port %#x/%d\n", io, io_len);
+ printk(KERN_INFO "scl200wdt: PnP device found at io port %#x/%d\n", io, io_len);
return 0;
}
-#endif /* CONFIG_ISAPNP */
+static void scl200wdt_pnp_remove(struct pnp_dev * dev)
+{
+ if (wdt_dev){
+ release_region(io, io_len);
+ wdt_dev = NULL;
+ }
+}
+
+static struct pnp_driver scl200wdt_pnp_driver = {
+ .name = "scl200wdt",
+ .id_table = scl200wdt_pnp_devices,
+ .probe = scl200wdt_pnp_probe,
+ .remove = scl200wdt_pnp_remove,
+};
+
+#endif /* CONFIG_PNP */
static int __init sc1200wdt_init(void)
@@ -373,9 +383,9 @@ static int __init sc1200wdt_init(void)
spin_lock_init(&sc1200wdt_lock);
sema_init(&open_sem, 1);
-#if defined CONFIG_ISAPNP || defined CONFIG_ISAPNP_MODULE
+#if defined CONFIG_PNP
if (isapnp) {
- ret = sc1200wdt_isapnp_probe();
+ ret = pnp_register_driver(&scl200wdt_pnp_driver);
if (ret)
goto out_clean;
}
@@ -387,12 +397,17 @@ static int __init sc1200wdt_init(void)
goto out_clean;
}
+ /* now that the user has specified an IO port and we haven't detected
+ * any devices, disable pnp support */
+ isapnp = 0;
+ pnp_unregister_driver(&scl200wdt_pnp_driver);
+
if (!request_region(io, io_len, SC1200_MODULE_NAME)) {
printk(KERN_ERR PFX "Unable to register IO port %#x\n", io);
ret = -EBUSY;
- goto out_pnp;
+ goto out_clean;
}
-
+
ret = sc1200wdt_probe();
if (ret)
goto out_io;
@@ -420,11 +435,6 @@ out_rbt:
out_io:
release_region(io, io_len);
-out_pnp:
-#if defined CONFIG_ISAPNP || defined CONFIG_ISAPNP_MODULE
- if (isapnp && wdt_dev)
- wdt_dev->deactivate(wdt_dev);
-#endif
goto out_clean;
}
@@ -434,11 +444,11 @@ static void __exit sc1200wdt_exit(void)
misc_deregister(&sc1200wdt_miscdev);
unregister_reboot_notifier(&sc1200wdt_notifier);
-#if defined CONFIG_ISAPNP || defined CONFIG_ISAPNP_MODULE
- if(isapnp && wdt_dev)
- wdt_dev->deactivate(wdt_dev);
+#if defined CONFIG_PNP
+ if(isapnp)
+ pnp_unregister_driver(&scl200wdt_pnp_driver);
+ else
#endif
-
release_region(io, io_len);
}
@@ -455,7 +465,7 @@ static int __init sc1200wdt_setup(char *
if (ints[0] > 1)
timeout = ints[2];
-#if defined CONFIG_ISAPNP || defined CONFIG_ISAPNP_MODULE
+#if defined CONFIG_PNP
if (ints[0] > 2)
isapnp = ints[3];
#endif
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/i2c/i2c-core.c linux-2.5/drivers/i2c/i2c-core.c
--- linux-2.5.60/drivers/i2c/i2c-core.c 2003-02-10 17:37:59.000000000 -0100
+++ linux-2.5/drivers/i2c/i2c-core.c 2003-02-10 15:26:58.000000000 -0100
@@ -56,7 +56,7 @@
/* ----- global variables -------------------------------------------------- */
/**** lock for writing to global variables: the adapter & driver list */
-DECLARE_MUTEX(adap_lock);
+static DECLARE_MUTEX(adap_lock);
static DECLARE_MUTEX(driver_lock);
/**** adapter list */
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/ide/pci/amd74xx.c linux-2.5/drivers/ide/pci/amd74xx.c
--- linux-2.5.60/drivers/ide/pci/amd74xx.c 2003-02-10 17:39:14.000000000 -0100
+++ linux-2.5/drivers/ide/pci/amd74xx.c 2003-02-11 10:27:23.000000000 -0100
@@ -60,7 +60,7 @@ static struct amd_ide_chip {
{ PCI_DEVICE_ID_AMD_OPUS_7441, 0x00, 0x40, AMD_UDMA_100 }, /* AMD-768 Opus */
{ PCI_DEVICE_ID_AMD_8111_IDE, 0x00, 0x40, AMD_UDMA_100 }, /* AMD-8111 */
{ PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, 0x00, 0x50, AMD_UDMA_100 }, /* nVidia nForce */
-
+ { PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, 0x00, 0x50, AMD_UDMA_100 }, /* nVidia nForce 2 */
{ 0 }
};
@@ -446,6 +446,7 @@ static struct pci_device_id amd74xx_pci_
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
+ { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
{ 0, },
};
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/ide/pci/amd74xx.h linux-2.5/drivers/ide/pci/amd74xx.h
--- linux-2.5.60/drivers/ide/pci/amd74xx.h 2003-02-10 17:37:57.000000000 -0100
+++ linux-2.5/drivers/ide/pci/amd74xx.h 2003-02-11 10:27:23.000000000 -0100
@@ -110,6 +110,20 @@ static ide_pci_device_t amd74xx_chipsets
.bootable = ON_BOARD,
.extra = 0,
},
+ { /* 6 */
+ .vendor = PCI_VENDOR_ID_NVIDIA,
+ .device = PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE,
+ .name = "NFORCE2",
+ .init_chipset = init_chipset_amd74xx,
+ .init_iops = NULL,
+ .init_hwif = init_hwif_amd74xx,
+ .init_dma = init_dma_amd74xx,
+ .channels = 2,
+ .autodma = AUTODMA,
+ .enablebits = {{0x50,0x01,0x01}, {0x50,0x02,0x02}},
+ .bootable = ON_BOARD,
+ .extra = 0,
+ },
{
.vendor = 0,
.device = 0,
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/ieee1394/ieee1394_syms.c linux-2.5/drivers/ieee1394/ieee1394_syms.c
--- linux-2.5.60/drivers/ieee1394/ieee1394_syms.c 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/drivers/ieee1394/ieee1394_syms.c 2003-02-04 17:55:59.000000000 -0100
@@ -0,0 +1,88 @@
+/*
+ * IEEE 1394 for Linux
+ *
+ * Exported symbols for module usage.
+ *
+ * Copyright (C) 1999 Andreas E. Bombe
+ *
+ * This code is licensed under the GPL. See the file COPYING in the root
+ * directory of the kernel sources for details.
+ */
+
+#include
+#include
+#include
+#include
+
+#include "ieee1394_types.h"
+#include "hosts.h"
+#include "ieee1394_core.h"
+#include "ieee1394_transactions.h"
+#include "ieee1394_hotplug.h"
+#include "highlevel.h"
+#include "nodemgr.h"
+
+EXPORT_SYMBOL(hpsb_register_lowlevel);
+EXPORT_SYMBOL(hpsb_unregister_lowlevel);
+EXPORT_SYMBOL(hpsb_get_host);
+EXPORT_SYMBOL(hpsb_inc_host_usage);
+EXPORT_SYMBOL(hpsb_dec_host_usage);
+
+EXPORT_SYMBOL(alloc_hpsb_packet);
+EXPORT_SYMBOL(free_hpsb_packet);
+EXPORT_SYMBOL(hpsb_send_packet);
+EXPORT_SYMBOL(hpsb_reset_bus);
+EXPORT_SYMBOL(hpsb_bus_reset);
+EXPORT_SYMBOL(hpsb_selfid_received);
+EXPORT_SYMBOL(hpsb_selfid_complete);
+EXPORT_SYMBOL(hpsb_packet_sent);
+EXPORT_SYMBOL(hpsb_packet_received);
+
+EXPORT_SYMBOL(get_tlabel);
+EXPORT_SYMBOL(free_tlabel);
+EXPORT_SYMBOL(fill_async_readquad);
+EXPORT_SYMBOL(fill_async_readquad_resp);
+EXPORT_SYMBOL(fill_async_readblock);
+EXPORT_SYMBOL(fill_async_readblock_resp);
+EXPORT_SYMBOL(fill_async_writequad);
+EXPORT_SYMBOL(fill_async_writeblock);
+EXPORT_SYMBOL(fill_async_write_resp);
+EXPORT_SYMBOL(fill_async_lock);
+EXPORT_SYMBOL(fill_async_lock_resp);
+EXPORT_SYMBOL(fill_iso_packet);
+EXPORT_SYMBOL(fill_phy_packet);
+EXPORT_SYMBOL(hpsb_make_readqpacket);
+EXPORT_SYMBOL(hpsb_make_readbpacket);
+EXPORT_SYMBOL(hpsb_make_writeqpacket);
+EXPORT_SYMBOL(hpsb_make_writebpacket);
+EXPORT_SYMBOL(hpsb_make_lockpacket);
+EXPORT_SYMBOL(hpsb_make_phypacket);
+EXPORT_SYMBOL(hpsb_packet_success);
+EXPORT_SYMBOL(hpsb_make_packet);
+EXPORT_SYMBOL(hpsb_read);
+EXPORT_SYMBOL(hpsb_write);
+EXPORT_SYMBOL(hpsb_lock);
+
+EXPORT_SYMBOL(hpsb_register_highlevel);
+EXPORT_SYMBOL(hpsb_unregister_highlevel);
+EXPORT_SYMBOL(hpsb_register_addrspace);
+EXPORT_SYMBOL(hpsb_listen_channel);
+EXPORT_SYMBOL(hpsb_unlisten_channel);
+EXPORT_SYMBOL(highlevel_read);
+EXPORT_SYMBOL(highlevel_write);
+EXPORT_SYMBOL(highlevel_lock);
+EXPORT_SYMBOL(highlevel_lock64);
+EXPORT_SYMBOL(highlevel_add_host);
+EXPORT_SYMBOL(highlevel_remove_host);
+EXPORT_SYMBOL(highlevel_host_reset);
+EXPORT_SYMBOL(highlevel_add_one_host);
+
+EXPORT_SYMBOL(hpsb_guid_get_entry);
+EXPORT_SYMBOL(hpsb_nodeid_get_entry);
+EXPORT_SYMBOL(hpsb_get_host_by_ne);
+EXPORT_SYMBOL(hpsb_guid_fill_packet);
+EXPORT_SYMBOL(hpsb_register_protocol);
+EXPORT_SYMBOL(hpsb_unregister_protocol);
+EXPORT_SYMBOL(hpsb_release_unit_directory);
+
+MODULE_LICENSE("GPL");
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/mtd/devices/ms02-nv.c linux-2.5/drivers/mtd/devices/ms02-nv.c
--- linux-2.5.60/drivers/mtd/devices/ms02-nv.c 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/drivers/mtd/devices/ms02-nv.c 2003-02-11 10:49:37.000000000 -0100
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2001 Maciej W. Rozycki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "ms02-nv.h"
+
+
+static char version[] __initdata =
+ "ms02-nv.c: v.1.0.0 13 Aug 2001 Maciej W. Rozycki.\n";
+
+MODULE_AUTHOR("Maciej W. Rozycki ");
+MODULE_DESCRIPTION("DEC MS02-NV NVRAM module driver");
+MODULE_LICENSE("GPL");
+
+
+/*
+ * Addresses we probe for an MS02-NV at. Modules may be located
+ * at any 8MB boundary within a 0MB up to 112MB range or at any 32MB
+ * boundary within a 0MB up to 448MB range. We don't support a module
+ * at 0MB, though.
+ */
+static ulong ms02nv_addrs[] __initdata = {
+ 0x07000000, 0x06800000, 0x06000000, 0x05800000, 0x05000000,
+ 0x04800000, 0x04000000, 0x03800000, 0x03000000, 0x02800000,
+ 0x02000000, 0x01800000, 0x01000000, 0x00800000
+};
+
+static const char ms02nv_name[] = "DEC MS02-NV NVRAM";
+static const char ms02nv_res_diag_ram[] = "Diagnostic RAM";
+static const char ms02nv_res_user_ram[] = "General-purpose RAM";
+static const char ms02nv_res_csr[] = "Control and status register";
+
+static struct mtd_info *root_ms02nv_mtd;
+
+
+static int ms02nv_read(struct mtd_info *mtd, loff_t from,
+ size_t len, size_t *retlen, u_char *buf)
+{
+ struct ms02nv_private *mp = (struct ms02nv_private *)mtd->priv;
+
+ if (from + len > mtd->size)
+ return -EINVAL;
+
+ memcpy(buf, mp->uaddr + from, len);
+ *retlen = len;
+
+ return 0;
+}
+
+static int ms02nv_write(struct mtd_info *mtd, loff_t to,
+ size_t len, size_t *retlen, const u_char *buf)
+{
+ struct ms02nv_private *mp = (struct ms02nv_private *)mtd->priv;
+
+ if (to + len > mtd->size)
+ return -EINVAL;
+
+ memcpy(mp->uaddr + to, buf, len);
+ *retlen = len;
+
+ return 0;
+}
+
+
+static inline uint ms02nv_probe_one(ulong addr)
+{
+ ms02nv_uint *ms02nv_diagp;
+ ms02nv_uint *ms02nv_magicp;
+ uint ms02nv_diag;
+ uint ms02nv_magic;
+ size_t size;
+
+ int err;
+
+ /*
+ * The firmware writes MS02NV_ID at MS02NV_MAGIC and also
+ * a diagnostic status at MS02NV_DIAG.
+ */
+ ms02nv_diagp = (ms02nv_uint *)(KSEG1ADDR(addr + MS02NV_DIAG));
+ ms02nv_magicp = (ms02nv_uint *)(KSEG1ADDR(addr + MS02NV_MAGIC));
+ err = get_dbe(ms02nv_magic, ms02nv_magicp);
+ if (err)
+ return 0;
+ if (ms02nv_magic != MS02NV_ID)
+ return 0;
+
+ ms02nv_diag = *ms02nv_diagp;
+ size = (ms02nv_diag & MS02NV_DIAG_SIZE_MASK) << MS02NV_DIAG_SIZE_SHIFT;
+ if (size > MS02NV_CSR)
+ size = MS02NV_CSR;
+
+ return size;
+}
+
+static int __init ms02nv_init_one(ulong addr)
+{
+ struct mtd_info *mtd;
+ struct ms02nv_private *mp;
+ struct resource *mod_res;
+ struct resource *diag_res;
+ struct resource *user_res;
+ struct resource *csr_res;
+ ulong fixaddr;
+ size_t size, fixsize;
+
+ static int version_printed;
+
+ int ret = -ENODEV;
+
+ /* The module decodes 8MB of address space. */
+ mod_res = kmalloc(sizeof(*mod_res), GFP_KERNEL);
+ if (!mod_res)
+ return -ENOMEM;
+
+ memset(mod_res, 0, sizeof(*mod_res));
+ mod_res->name = ms02nv_name;
+ mod_res->start = addr;
+ mod_res->end = addr + MS02NV_SLOT_SIZE - 1;
+ mod_res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
+ if (request_resource(&iomem_resource, mod_res) < 0)
+ goto err_out_mod_res;
+
+ size = ms02nv_probe_one(addr);
+ if (!size)
+ goto err_out_mod_res_rel;
+
+ if (!version_printed) {
+ printk(KERN_INFO "%s", version);
+ version_printed = 1;
+ }
+
+ ret = -ENOMEM;
+ mtd = kmalloc(sizeof(*mtd), GFP_KERNEL);
+ if (!mtd)
+ goto err_out_mod_res_rel;
+ memset(mtd, 0, sizeof(*mtd));
+ mp = kmalloc(sizeof(*mp), GFP_KERNEL);
+ if (!mp)
+ goto err_out_mtd;
+ memset(mp, 0, sizeof(*mp));
+
+ mtd->priv = mp;
+ mp->resource.module = mod_res;
+
+ /* Firmware's diagnostic NVRAM area. */
+ diag_res = kmalloc(sizeof(*diag_res), GFP_KERNEL);
+ if (!diag_res)
+ goto err_out_mp;
+
+ memset(diag_res, 0, sizeof(*diag_res));
+ diag_res->name = ms02nv_res_diag_ram;
+ diag_res->start = addr;
+ diag_res->end = addr + MS02NV_RAM - 1;
+ diag_res->flags = IORESOURCE_BUSY;
+ request_resource(mod_res, diag_res);
+
+ mp->resource.diag_ram = diag_res;
+
+ /* User-available general-purpose NVRAM area. */
+ user_res = kmalloc(sizeof(*user_res), GFP_KERNEL);
+ if (!user_res)
+ goto err_out_diag_res;
+
+ memset(user_res, 0, sizeof(*user_res));
+ user_res->name = ms02nv_res_user_ram;
+ user_res->start = addr + MS02NV_RAM;
+ user_res->end = addr + size - 1;
+ user_res->flags = IORESOURCE_BUSY;
+ request_resource(mod_res, user_res);
+
+ mp->resource.user_ram = user_res;
+
+ /* Control and status register. */
+ csr_res = kmalloc(sizeof(*csr_res), GFP_KERNEL);
+ if (!csr_res)
+ goto err_out_user_res;
+
+ memset(csr_res, 0, sizeof(*csr_res));
+ csr_res->name = ms02nv_res_csr;
+ csr_res->start = addr + MS02NV_CSR;
+ csr_res->end = addr + MS02NV_CSR + 3;
+ csr_res->flags = IORESOURCE_BUSY;
+ request_resource(mod_res, csr_res);
+
+ mp->resource.csr = csr_res;
+
+ mp->addr = phys_to_virt(addr);
+ mp->size = size;
+
+ /*
+ * Hide the firmware's diagnostic area. It may get destroyed
+ * upon a reboot. Take paging into account for mapping support.
+ */
+ fixaddr = (addr + MS02NV_RAM + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
+ fixsize = (size - (fixaddr - addr)) & ~(PAGE_SIZE - 1);
+ mp->uaddr = phys_to_virt(fixaddr);
+
+ mtd->type = MTD_RAM;
+ mtd->flags = MTD_CAP_RAM | MTD_XIP;
+ mtd->size = fixsize;
+ mtd->name = (char *)ms02nv_name;
+ mtd->module = THIS_MODULE;
+ mtd->read = ms02nv_read;
+ mtd->write = ms02nv_write;
+
+ ret = -EIO;
+ if (add_mtd_device(mtd)) {
+ printk(KERN_ERR
+ "ms02-nv: Unable to register MTD device, aborting!\n");
+ goto err_out_csr_res;
+ }
+
+ printk(KERN_INFO "mtd%d: %s at 0x%08lx, size %uMB.\n",
+ mtd->index, ms02nv_name, addr, size >> 20);
+
+ mp->next = root_ms02nv_mtd;
+ root_ms02nv_mtd = mtd;
+
+ return 0;
+
+
+err_out_csr_res:
+ release_resource(csr_res);
+ kfree(csr_res);
+err_out_user_res:
+ release_resource(user_res);
+ kfree(user_res);
+err_out_diag_res:
+ release_resource(diag_res);
+ kfree(diag_res);
+err_out_mp:
+ kfree(mp);
+err_out_mtd:
+ kfree(mtd);
+err_out_mod_res_rel:
+ release_resource(mod_res);
+err_out_mod_res:
+ kfree(mod_res);
+ return ret;
+}
+
+static void __exit ms02nv_remove_one(void)
+{
+ struct mtd_info *mtd = root_ms02nv_mtd;
+ struct ms02nv_private *mp = (struct ms02nv_private *)mtd->priv;
+
+ root_ms02nv_mtd = mp->next;
+
+ del_mtd_device(mtd);
+
+ release_resource(mp->resource.csr);
+ kfree(mp->resource.csr);
+ release_resource(mp->resource.user_ram);
+ kfree(mp->resource.user_ram);
+ release_resource(mp->resource.diag_ram);
+ kfree(mp->resource.diag_ram);
+ release_resource(mp->resource.module);
+ kfree(mp->resource.module);
+ kfree(mp);
+ kfree(mtd);
+}
+
+
+static int __init ms02nv_init(void)
+{
+ volatile u32 *csr;
+ uint stride = 0;
+ int count = 0;
+ int i;
+
+ switch (mips_machtype) {
+ case MACH_DS5000_200:
+ csr = (volatile u32 *)KN02_CSR_ADDR;
+ if (*csr & KN02_CSR_BNK32M)
+ stride = 2;
+ break;
+ case MACH_DS5000_2X0:
+ csr = (volatile u32 *)KN03_MCR_BASE;
+ if (*csr & KN03_MCR_BNK32M)
+ stride = 2;
+ break;
+ default:
+ return -ENODEV;
+ break;
+ }
+
+ for (i = 0; i < (sizeof(ms02nv_addrs) / sizeof(*ms02nv_addrs)); i++)
+ if (!ms02nv_init_one(ms02nv_addrs[i] << stride))
+ count++;
+
+ return (count > 0) ? 0 : -ENODEV;
+}
+
+static void __exit ms02nv_cleanup(void)
+{
+ while (root_ms02nv_mtd)
+ ms02nv_remove_one();
+}
+
+
+module_init(ms02nv_init);
+module_exit(ms02nv_cleanup);
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/mtd/devices/ms02-nv.h linux-2.5/drivers/mtd/devices/ms02-nv.h
--- linux-2.5.60/drivers/mtd/devices/ms02-nv.h 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/drivers/mtd/devices/ms02-nv.h 2003-02-11 10:49:37.000000000 -0100
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2001 Maciej W. Rozycki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include
+#include
+
+/* MS02-NV iomem register offsets. */
+#define MS02NV_CSR 0x400000 /* control & status register */
+
+/* MS02-NV memory offsets. */
+#define MS02NV_DIAG 0x0003f8 /* diagnostic status */
+#define MS02NV_MAGIC 0x0003fc /* MS02-NV magic ID */
+#define MS02NV_RAM 0x000400 /* general-purpose RAM start */
+
+/* MS02-NV diagnostic status constants. */
+#define MS02NV_DIAG_SIZE_MASK 0xf0 /* RAM size mask */
+#define MS02NV_DIAG_SIZE_SHIFT 0x10 /* RAM size shift (left) */
+
+/* MS02-NV general constants. */
+#define MS02NV_ID 0x03021966 /* MS02-NV magic ID value */
+#define MS02NV_SLOT_SIZE 0x800000 /* size of the address space
+ decoded by the module */
+
+typedef volatile u32 ms02nv_uint;
+
+struct ms02nv_private {
+ struct mtd_info *next;
+ struct {
+ struct resource *module;
+ struct resource *diag_ram;
+ struct resource *user_ram;
+ struct resource *csr;
+ } resource;
+ u_char *addr;
+ size_t size;
+ u_char *uaddr;
+};
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/mtd/maps/amd766rom.c linux-2.5/drivers/mtd/maps/amd766rom.c
--- linux-2.5.60/drivers/mtd/maps/amd766rom.c 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/drivers/mtd/maps/amd766rom.c 2003-02-11 10:49:37.000000000 -0100
@@ -0,0 +1,245 @@
+/*
+ * amd766rom.c
+ *
+ * Normal mappings of chips in physical memory
+ * $Id: amd766rom.c,v 1.1 2002/01/10 22:59:13 eric Exp $
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+
+struct amd766rom_map_info {
+ struct map_info map;
+ struct mtd_info *mtd;
+ unsigned long window_addr;
+ u32 window_start, window_size;
+ struct pci_dev *pdev;
+};
+
+static __u8 amd766rom_read8(struct map_info *map, unsigned long ofs)
+{
+ return __raw_readb(map->map_priv_1 + ofs);
+}
+
+static __u16 amd766rom_read16(struct map_info *map, unsigned long ofs)
+{
+ return __raw_readw(map->map_priv_1 + ofs);
+}
+
+static __u32 amd766rom_read32(struct map_info *map, unsigned long ofs)
+{
+ return __raw_readl(map->map_priv_1 + ofs);
+}
+
+static void amd766rom_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
+{
+ memcpy_fromio(to, map->map_priv_1 + from, len);
+}
+
+static void amd766rom_write8(struct map_info *map, __u8 d, unsigned long adr)
+{
+ __raw_writeb(d, map->map_priv_1 + adr);
+ mb();
+}
+
+static void amd766rom_write16(struct map_info *map, __u16 d, unsigned long adr)
+{
+ __raw_writew(d, map->map_priv_1 + adr);
+ mb();
+}
+
+static void amd766rom_write32(struct map_info *map, __u32 d, unsigned long adr)
+{
+ __raw_writel(d, map->map_priv_1 + adr);
+ mb();
+}
+
+static void amd766rom_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
+{
+ memcpy_toio(map->map_priv_1 + to, from, len);
+}
+
+static struct amd766rom_map_info amd766rom_map = {
+ map: {
+ name: "AMD766 rom",
+ size: 0,
+ buswidth: 1,
+ read8: amd766rom_read8,
+ read16: amd766rom_read16,
+ read32: amd766rom_read32,
+ copy_from: amd766rom_copy_from,
+ write8: amd766rom_write8,
+ write16: amd766rom_write16,
+ write32: amd766rom_write32,
+ copy_to: amd766rom_copy_to,
+ /* The standard rom socket is for single power supply chips
+ * that don't have an extra vpp.
+ */
+ },
+ mtd: 0,
+ window_addr: 0,
+};
+
+static int __devinit amd766rom_init_one (struct pci_dev *pdev,
+ const struct pci_device_id *ent)
+{
+ struct rom_window {
+ u32 start;
+ u32 size;
+ u8 segen_bits;
+ };
+ static struct rom_window rom_window[] = {
+ { 0xffb00000, 5*1024*1024, (1<<7) | (1<<6), },
+ { 0xffc00000, 4*1024*1024, (1<<7), },
+ { 0xffff0000, 64*1024, 0 },
+ { 0 , 0, 0 },
+ };
+ static const u32 rom_probe_sizes[] = {
+ 5*1024*1024, 4*1024*1024, 2*1024*1024, 1024*1024, 512*1024,
+ 256*1024, 128*1024, 64*1024, 0};
+ static char *rom_probe_types[] = { "cfi_probe", "jedec_probe", 0 };
+ u8 byte;
+ struct amd766rom_map_info *info = &amd766rom_map;
+ struct rom_window *window;
+ int i;
+ u32 rom_size;
+
+ window = &rom_window[0];
+ while(window->size) {
+ if (request_mem_region(window->start, window->size, "amd766rom")) {
+ break;
+ }
+ window++;
+ }
+ if (!window->size) {
+ printk(KERN_ERR "amd766rom: cannot reserve rom window");
+ goto err_out_none;
+ }
+
+ /* Enable the selected rom window */
+ pci_read_config_byte(pdev, 0x43, &byte);
+ pci_write_config_byte(pdev, 0x43, byte | window->segen_bits);
+
+ /* Enable writes through the rom window */
+ pci_read_config_byte(pdev, 0x40, &byte);
+ pci_write_config_byte(pdev, 0x40, byte | 1);
+
+ /* FIXME handle registers 0x80 - 0x8C the bios region locks */
+
+ printk(KERN_NOTICE "amd766rom window : %x at %x\n",
+ window->size, window->start);
+ /* For write accesses caches are useless */
+ info->window_addr = (unsigned long)ioremap_nocache(window->start, window->size);
+
+ if (!info->window_addr) {
+ printk(KERN_ERR "Failed to ioremap\n");
+ goto err_out_free_mmio_region;
+ }
+ info->mtd = 0;
+ for(i = 0; (rom_size = rom_probe_sizes[i]); i++) {
+ char **chip_type;
+ if (rom_size > window->size) {
+ continue;
+ }
+ info->map.map_priv_1 =
+ info->window_addr + window->size - rom_size;
+ info->map.size = rom_size;
+ chip_type = rom_probe_types;
+ for(; !info->mtd && *chip_type; chip_type++) {
+ info->mtd = do_map_probe(*chip_type, &amd766rom_map.map);
+ }
+ if (info->mtd) {
+ break;
+ }
+ }
+ if (!info->mtd) {
+ goto err_out_iounmap;
+ }
+ printk(KERN_NOTICE "amd766rom chip at offset: %x\n",
+ window->size - rom_size);
+
+ info->mtd->module = THIS_MODULE;
+ add_mtd_device(info->mtd);
+ info->window_start = window->start;
+ info->window_size = window->size;
+ return 0;
+
+err_out_iounmap:
+ iounmap((void *)(info->window_addr));
+err_out_free_mmio_region:
+ release_mem_region(window->start, window->size);
+err_out_none:
+ return -ENODEV;
+}
+
+
+static void __devexit amd766rom_remove_one (struct pci_dev *pdev)
+{
+ struct amd766rom_map_info *info = &amd766rom_map;
+ u8 byte;
+
+ del_mtd_device(info->mtd);
+ map_destroy(info->mtd);
+ info->mtd = 0;
+ info->map.map_priv_1 = 0;
+
+ iounmap((void *)(info->window_addr));
+ info->window_addr = 0;
+
+ /* Disable writes through the rom window */
+ pci_read_config_byte(pdev, 0x40, &byte);
+ pci_write_config_byte(pdev, 0x40, byte & ~1);
+
+ release_mem_region(info->window_start, info->window_size);
+}
+
+static struct pci_device_id amd766rom_pci_tbl[] __devinitdata = {
+ { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410,
+ PCI_ANY_ID, PCI_ANY_ID, },
+};
+
+MODULE_DEVICE_TABLE(pci, amd766rom_pci_tbl);
+
+#if 0
+static struct pci_driver amd766rom_driver = {
+ name: "amd766rom",
+ id_table: amd766rom_pci_tbl,
+ probe: amd766rom_init_one,
+ remove: amd766rom_remove_one,
+};
+#endif
+
+int __init init_amd766rom(void)
+{
+ struct pci_dev *pdev;
+ pdev = pci_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, 0);
+ if (pdev) {
+ amd766rom_map.pdev = pdev;
+ return amd766rom_init_one(pdev, &amd766rom_pci_tbl[0]);
+ }
+ return -ENXIO;
+#if 0
+ return pci_module_init(&amd766rom_driver);
+#endif
+}
+
+static void __exit cleanup_amd766rom(void)
+{
+ amd766rom_remove_one(amd766rom_map.pdev);
+}
+
+module_init(init_amd766rom);
+module_exit(cleanup_amd766rom);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Eric Biederman ");
+MODULE_DESCRIPTION("MTD map driver for BIOS chips on the AMD766 southbridge");
+
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/mtd/maps/dilnetpc.c linux-2.5/drivers/mtd/maps/dilnetpc.c
--- linux-2.5.60/drivers/mtd/maps/dilnetpc.c 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/drivers/mtd/maps/dilnetpc.c 2003-02-11 10:49:37.000000000 -0100
@@ -0,0 +1,540 @@
+/* dilnetpc.c -- MTD map driver for SSV DIL/Net PC Boards "DNP" and "ADNP"
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ *
+ * $Id: dilnetpc.c,v 1.8 2002/03/12 13:07:26 rkaiser Exp $
+ *
+ * The DIL/Net PC is a tiny embedded PC board made by SSV Embedded Systems
+ * featuring the AMD Elan SC410 processor. There are two variants of this
+ * board: DNP/1486 and ADNP/1486. The DNP version has 2 megs of flash
+ * ROM (Intel 28F016S3) and 8 megs of DRAM, the ADNP version has 4 megs
+ * flash and 16 megs of RAM.
+ * For details, see http://www.ssv-embedded.de/ssv/pc104/p169.htm
+ * and http://www.ssv-embedded.de/ssv/pc104/p170.htm
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+** The DIL/NetPC keeps it's BIOS in two distinct flash blocks.
+** Destroying any of these blocks transforms the DNPC into
+** a paperweight (albeit not a very useful one, considering
+** it only weighs a few grams).
+**
+** Therefore, the BIOS blocks must never be erased or written to
+** except by people who know exactly what they are doing (e.g.
+** to install a BIOS update). These partitions are marked read-only
+** by default, but can be made read/write by undefining
+** DNPC_BIOS_BLOCKS_WRITEPROTECTED:
+*/
+#define DNPC_BIOS_BLOCKS_WRITEPROTECTED
+
+/*
+** The ID string (in ROM) is checked to determine whether we
+** are running on a DNP/1486 or ADNP/1486
+*/
+#define BIOSID_BASE 0x000fe100
+
+#define ID_DNPC "DNP1486"
+#define ID_ADNP "ADNP1486"
+
+/*
+** Address where the flash should appear in CPU space
+*/
+#define FLASH_BASE 0x2000000
+
+/*
+** Chip Setup and Control (CSC) indexed register space
+*/
+#define CSC_INDEX 0x22
+#define CSC_DATA 0x23
+
+#define CSC_MMSWAR 0x30 /* MMS window C-F attributes register */
+#define CSC_MMSWDSR 0x31 /* MMS window C-F device select register */
+
+#define CSC_RBWR 0xa7 /* GPIO Read-Back/Write Register B */
+
+#define CSC_CR 0xd0 /* internal I/O device disable/Echo */
+ /* Z-bus/configuration register */
+
+#define CSC_PCCMDCR 0xf1 /* PC card mode and DMA control register */
+
+
+/*
+** PC Card indexed register space:
+*/
+
+#define PCC_INDEX 0x3e0
+#define PCC_DATA 0x3e1
+
+#define PCC_AWER_B 0x46 /* Socket B Address Window enable register */
+#define PCC_MWSAR_1_Lo 0x58 /* memory window 1 start address low register */
+#define PCC_MWSAR_1_Hi 0x59 /* memory window 1 start address high register */
+#define PCC_MWEAR_1_Lo 0x5A /* memory window 1 stop address low register */
+#define PCC_MWEAR_1_Hi 0x5B /* memory window 1 stop address high register */
+#define PCC_MWAOR_1_Lo 0x5C /* memory window 1 address offset low register */
+#define PCC_MWAOR_1_Hi 0x5D /* memory window 1 address offset high register */
+
+
+/*
+** Access to SC4x0's Chip Setup and Control (CSC)
+** and PC Card (PCC) indexed registers:
+*/
+static inline void setcsc(int reg, unsigned char data)
+{
+ outb(reg, CSC_INDEX);
+ outb(data, CSC_DATA);
+}
+
+static inline unsigned char getcsc(int reg)
+{
+ outb(reg, CSC_INDEX);
+ return(inb(CSC_DATA));
+}
+
+static inline void setpcc(int reg, unsigned char data)
+{
+ outb(reg, PCC_INDEX);
+ outb(data, PCC_DATA);
+}
+
+static inline unsigned char getpcc(int reg)
+{
+ outb(reg, PCC_INDEX);
+ return(inb(PCC_DATA));
+}
+
+
+/*
+************************************************************
+** Enable access to DIL/NetPC's flash by mapping it into
+** the SC4x0's MMS Window C.
+************************************************************
+*/
+static void dnpc_map_flash(unsigned long flash_base, unsigned long flash_size)
+{
+ unsigned long flash_end = flash_base + flash_size - 1;
+
+ /*
+ ** enable setup of MMS windows C-F:
+ */
+ /* - enable PC Card indexed register space */
+ setcsc(CSC_CR, getcsc(CSC_CR) | 0x2);
+ /* - set PC Card controller to operate in standard mode */
+ setcsc(CSC_PCCMDCR, getcsc(CSC_PCCMDCR) & ~1);
+
+ /*
+ ** Program base address and end address of window
+ ** where the flash ROM should appear in CPU address space
+ */
+ setpcc(PCC_MWSAR_1_Lo, (flash_base >> 12) & 0xff);
+ setpcc(PCC_MWSAR_1_Hi, (flash_base >> 20) & 0x3f);
+ setpcc(PCC_MWEAR_1_Lo, (flash_end >> 12) & 0xff);
+ setpcc(PCC_MWEAR_1_Hi, (flash_end >> 20) & 0x3f);
+
+ /* program offset of first flash location to appear in this window (0) */
+ setpcc(PCC_MWAOR_1_Lo, ((0 - flash_base) >> 12) & 0xff);
+ setpcc(PCC_MWAOR_1_Hi, ((0 - flash_base)>> 20) & 0x3f);
+
+ /* set attributes for MMS window C: non-cacheable, write-enabled */
+ setcsc(CSC_MMSWAR, getcsc(CSC_MMSWAR) & ~0x11);
+
+ /* select physical device ROMCS0 (i.e. flash) for MMS Window C */
+ setcsc(CSC_MMSWDSR, getcsc(CSC_MMSWDSR) & ~0x03);
+
+ /* enable memory window 1 */
+ setpcc(PCC_AWER_B, getpcc(PCC_AWER_B) | 0x02);
+
+ /* now disable PC Card indexed register space again */
+ setcsc(CSC_CR, getcsc(CSC_CR) & ~0x2);
+}
+
+
+/*
+************************************************************
+** Disable access to DIL/NetPC's flash by mapping it into
+** the SC4x0's MMS Window C.
+************************************************************
+*/
+static void dnpc_unmap_flash(void)
+{
+ /* - enable PC Card indexed register space */
+ setcsc(CSC_CR, getcsc(CSC_CR) | 0x2);
+
+ /* disable memory window 1 */
+ setpcc(PCC_AWER_B, getpcc(PCC_AWER_B) & ~0x02);
+
+ /* now disable PC Card indexed register space again */
+ setcsc(CSC_CR, getcsc(CSC_CR) & ~0x2);
+}
+
+
+static __u8 dnpc_read8(struct map_info *map, unsigned long ofs)
+{
+ return readb(map->map_priv_1 + ofs);
+}
+
+static __u16 dnpc_read16(struct map_info *map, unsigned long ofs)
+{
+ return readw(map->map_priv_1 + ofs);
+}
+
+static __u32 dnpc_read32(struct map_info *map, unsigned long ofs)
+{
+ return readl(map->map_priv_1 + ofs);
+}
+
+static void dnpc_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
+{
+ memcpy_fromio(to, (void *)(map->map_priv_1 + from), len);
+}
+
+static void dnpc_write8(struct map_info *map, __u8 d, unsigned long adr)
+{
+ writeb(d, map->map_priv_1 + adr);
+}
+
+static void dnpc_write16(struct map_info *map, __u16 d, unsigned long adr)
+{
+ writew(d, map->map_priv_1 + adr);
+}
+
+static void dnpc_write32(struct map_info *map, __u32 d, unsigned long adr)
+{
+ writel(d, map->map_priv_1 + adr);
+}
+
+static void dnpc_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
+{
+ memcpy_toio((void *)(map->map_priv_1 + to), from, len);
+}
+
+/*
+************************************************************
+** Enable/Disable VPP to write to flash
+************************************************************
+*/
+
+static spinlock_t dnpc_spin = SPIN_LOCK_UNLOCKED;
+static int vpp_counter = 0;
+/*
+** This is what has to be done for the DNP board ..
+*/
+static void dnp_set_vpp(struct map_info *not_used, int on)
+{
+ spin_lock_irq(&dnpc_spin);
+
+ if (on)
+ {
+ if(++vpp_counter == 1)
+ setcsc(CSC_RBWR, getcsc(CSC_RBWR) & ~0x4);
+ }
+ else
+ {
+ if(--vpp_counter == 0)
+ setcsc(CSC_RBWR, getcsc(CSC_RBWR) | 0x4);
+ else if(vpp_counter < 0)
+ BUG();
+ }
+ spin_unlock_irq(&dnpc_spin);
+}
+
+/*
+** .. and this the ADNP version:
+*/
+static void adnp_set_vpp(struct map_info *not_used, int on)
+{
+ spin_lock_irq(&dnpc_spin);
+
+ if (on)
+ {
+ if(++vpp_counter == 1)
+ setcsc(CSC_RBWR, getcsc(CSC_RBWR) & ~0x8);
+ }
+ else
+ {
+ if(--vpp_counter == 0)
+ setcsc(CSC_RBWR, getcsc(CSC_RBWR) | 0x8);
+ else if(vpp_counter < 0)
+ BUG();
+ }
+ spin_unlock_irq(&dnpc_spin);
+}
+
+
+
+#define DNP_WINDOW_SIZE 0x00200000 /* DNP flash size is 2MiB */
+#define ADNP_WINDOW_SIZE 0x00400000 /* ADNP flash size is 4MiB */
+#define WINDOW_ADDR FLASH_BASE
+
+static struct map_info dnpc_map = {
+ name: "ADNP Flash Bank",
+ size: ADNP_WINDOW_SIZE,
+ buswidth: 1,
+ read8: dnpc_read8,
+ read16: dnpc_read16,
+ read32: dnpc_read32,
+ copy_from: dnpc_copy_from,
+ write8: dnpc_write8,
+ write16: dnpc_write16,
+ write32: dnpc_write32,
+ copy_to: dnpc_copy_to,
+ set_vpp: adnp_set_vpp,
+ map_priv_2: WINDOW_ADDR
+};
+
+/*
+** The layout of the flash is somewhat "strange":
+**
+** 1. 960 KiB (15 blocks) : Space for ROM Bootloader and user data
+** 2. 64 KiB (1 block) : System BIOS
+** 3. 960 KiB (15 blocks) : User Data (DNP model) or
+** 3. 3008 KiB (47 blocks) : User Data (ADNP model)
+** 4. 64 KiB (1 block) : System BIOS Entry
+*/
+
+static struct mtd_partition partition_info[]=
+{
+ {
+ name: "ADNP boot",
+ offset: 0,
+ size: 0xf0000,
+ },
+ {
+ name: "ADNP system BIOS",
+ offset: MTDPART_OFS_NXTBLK,
+ size: 0x10000,
+#ifdef DNPC_BIOS_BLOCKS_WRITEPROTECTED
+ mask_flags: MTD_WRITEABLE,
+#endif
+ },
+ {
+ name: "ADNP file system",
+ offset: MTDPART_OFS_NXTBLK,
+ size: 0x2f0000,
+ },
+ {
+ name: "ADNP system BIOS entry",
+ offset: MTDPART_OFS_NXTBLK,
+ size: MTDPART_SIZ_FULL,
+#ifdef DNPC_BIOS_BLOCKS_WRITEPROTECTED
+ mask_flags: MTD_WRITEABLE,
+#endif
+ },
+};
+
+#define NUM_PARTITIONS (sizeof(partition_info)/sizeof(partition_info[0]))
+
+static struct mtd_info *mymtd;
+static struct mtd_info *lowlvl_parts[NUM_PARTITIONS];
+static struct mtd_info *merged_mtd;
+
+/*
+** "Highlevel" partition info:
+**
+** Using the MTD concat layer, we can re-arrange partitions to our
+** liking: we construct a virtual MTD device by concatenating the
+** partitions, specifying the sequence such that the boot block
+** is immediately followed by the filesystem block (i.e. the stupid
+** system BIOS block is mapped to a different place). When re-partitioning
+** this concatenated MTD device, we can set the boot block size to
+** an arbitrary (though erase block aligned) value i.e. not one that
+** is dictated by the flash's physical layout. We can thus set the
+** boot block to be e.g. 64 KB (which is fully sufficient if we want
+** to boot an etherboot image) or to -say- 1.5 MB if we want to boot
+** a large kernel image. In all cases, the remainder of the flash
+** is available as file system space.
+*/
+
+static struct mtd_partition higlvl_partition_info[]=
+{
+ {
+ name: "ADNP boot block",
+ offset: 0,
+ size: CONFIG_MTD_DILNETPC_BOOTSIZE,
+ },
+ {
+ name: "ADNP file system space",
+ offset: MTDPART_OFS_NXTBLK,
+ size: ADNP_WINDOW_SIZE-CONFIG_MTD_DILNETPC_BOOTSIZE-0x20000,
+ },
+ {
+ name: "ADNP system BIOS + BIOS Entry",
+ offset: MTDPART_OFS_NXTBLK,
+ size: MTDPART_SIZ_FULL,
+#ifdef DNPC_BIOS_BLOCKS_WRITEPROTECTED
+ mask_flags: MTD_WRITEABLE,
+#endif
+ },
+};
+
+#define NUM_HIGHLVL_PARTITIONS (sizeof(higlvl_partition_info)/sizeof(partition_info[0]))
+
+
+static int dnp_adnp_probe(void)
+{
+ char *biosid, rc = -1;
+
+ biosid = (char*)ioremap(BIOSID_BASE, 16);
+ if(biosid)
+ {
+ if(!strcmp(biosid, ID_DNPC))
+ rc = 1; /* this is a DNPC */
+ else if(!strcmp(biosid, ID_ADNP))
+ rc = 0; /* this is a ADNPC */
+ }
+ iounmap((void *)biosid);
+ return(rc);
+}
+
+
+static int __init init_dnpc(void)
+{
+ int is_dnp;
+
+ /*
+ ** determine hardware (DNP/ADNP/invalid)
+ */
+ if((is_dnp = dnp_adnp_probe()) < 0)
+ return -ENXIO;
+
+ /*
+ ** Things are set up for ADNP by default
+ ** -> modify all that needs to be different for DNP
+ */
+ if(is_dnp)
+ { /*
+ ** Adjust window size, select correct set_vpp function.
+ ** The partitioning scheme is identical on both DNP
+ ** and ADNP except for the size of the third partition.
+ */
+ int i;
+ dnpc_map.size = DNP_WINDOW_SIZE;
+ dnpc_map.set_vpp = dnp_set_vpp;
+ partition_info[2].size = 0xf0000;
+
+ /*
+ ** increment all string pointers so the leading 'A' gets skipped,
+ ** thus turning all occurrences of "ADNP ..." into "DNP ..."
+ */
+ ++dnpc_map.name;
+ for(i = 0; i < NUM_PARTITIONS; i++)
+ ++partition_info[i].name;
+ higlvl_partition_info[1].size = DNP_WINDOW_SIZE -
+ CONFIG_MTD_DILNETPC_BOOTSIZE - 0x20000;
+ for(i = 0; i < NUM_HIGHLVL_PARTITIONS; i++)
+ ++higlvl_partition_info[i].name;
+ }
+
+ printk(KERN_NOTICE "DIL/Net %s flash: 0x%lx at 0x%lx\n",
+ is_dnp ? "DNPC" : "ADNP", dnpc_map.size, dnpc_map.map_priv_2);
+
+ dnpc_map.map_priv_1 = (unsigned long)ioremap_nocache(dnpc_map.map_priv_2, dnpc_map.size);
+
+ dnpc_map_flash(dnpc_map.map_priv_2, dnpc_map.size);
+
+ if (!dnpc_map.map_priv_1) {
+ printk("Failed to ioremap_nocache\n");
+ return -EIO;
+ }
+
+ printk("FLASH virtual address: 0x%lx\n", dnpc_map.map_priv_1);
+
+ mymtd = do_map_probe("jedec_probe", &dnpc_map);
+
+ if (!mymtd)
+ mymtd = do_map_probe("cfi_probe", &dnpc_map);
+
+ /*
+ ** If flash probes fail, try to make flashes accessible
+ ** at least as ROM. Ajust erasesize in this case since
+ ** the default one (128M) will break our partitioning
+ */
+ if (!mymtd)
+ if((mymtd = do_map_probe("map_rom", &dnpc_map)))
+ mymtd->erasesize = 0x10000;
+
+ if (!mymtd) {
+ iounmap((void *)dnpc_map.map_priv_1);
+ return -ENXIO;
+ }
+
+ mymtd->module = THIS_MODULE;
+
+ /*
+ ** Supply pointers to lowlvl_parts[] array to add_mtd_partitions()
+ ** -> add_mtd_partitions() will _not_ register MTD devices for
+ ** the partitions, but will instead store pointers to the MTD
+ ** objects it creates into our lowlvl_parts[] array.
+ ** NOTE: we arrange the pointers such that the sequence of the
+ ** partitions gets re-arranged: partition #2 follows
+ ** partition #0.
+ */
+ partition_info[0].mtdp = &lowlvl_parts[0];
+ partition_info[1].mtdp = &lowlvl_parts[2];
+ partition_info[2].mtdp = &lowlvl_parts[1];
+ partition_info[3].mtdp = &lowlvl_parts[3];
+
+ add_mtd_partitions(mymtd, partition_info, NUM_PARTITIONS);
+
+ /*
+ ** now create a virtual MTD device by concatenating the for partitions
+ ** (in the sequence given by the lowlvl_parts[] array.
+ */
+ merged_mtd = mtd_concat_create(lowlvl_parts, NUM_PARTITIONS, "(A)DNP Flash Concatenated");
+ if(merged_mtd)
+ { /*
+ ** now partition the new device the way we want it. This time,
+ ** we do not supply mtd pointers in higlvl_partition_info, so
+ ** add_mtd_partitions() will register the devices.
+ */
+ add_mtd_partitions(merged_mtd, higlvl_partition_info, NUM_HIGHLVL_PARTITIONS);
+ }
+
+ return 0;
+}
+
+static void __exit cleanup_dnpc(void)
+{
+ if(merged_mtd) {
+ del_mtd_partitions(merged_mtd);
+ mtd_concat_destroy(merged_mtd);
+ }
+
+ if (mymtd) {
+ del_mtd_partitions(mymtd);
+ map_destroy(mymtd);
+ }
+ if (dnpc_map.map_priv_1) {
+ iounmap((void *)dnpc_map.map_priv_1);
+ dnpc_unmap_flash();
+ dnpc_map.map_priv_1 = 0;
+ }
+}
+
+module_init(init_dnpc);
+module_exit(cleanup_dnpc);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Sysgo Real-Time Solutions GmbH");
+MODULE_DESCRIPTION("MTD map driver for SSV DIL/NetPC DNP & ADNP");
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/mtd/maps/ich2rom.c linux-2.5/drivers/mtd/maps/ich2rom.c
--- linux-2.5.60/drivers/mtd/maps/ich2rom.c 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/drivers/mtd/maps/ich2rom.c 2003-02-11 10:49:37.000000000 -0100
@@ -0,0 +1,302 @@
+/*
+ * ich2rom.c
+ *
+ * Normal mappings of chips in physical memory
+ * $Id: ich2rom.c,v 1.1 2002/01/10 22:59:13 eric Exp $
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define RESERVE_MEM_REGION 0
+
+#define ICH2_FWH_REGION_START 0xFF000000UL
+#define ICH2_FWH_REGION_SIZE 0x01000000UL
+#define BIOS_CNTL 0x4e
+#define FWH_DEC_EN1 0xE3
+#define FWH_DEC_EN2 0xF0
+#define FWH_SEL1 0xE8
+#define FWH_SEL2 0xEE
+
+struct ich2rom_map_info {
+ struct map_info map;
+ struct mtd_info *mtd;
+ unsigned long window_addr;
+};
+
+static inline unsigned long addr(struct map_info *map, unsigned long ofs)
+{
+ unsigned long offset;
+ offset = ((8*1024*1024) - map->size) + ofs;
+ if (offset >= (4*1024*1024)) {
+ offset += 0x400000;
+ }
+ return map->map_priv_1 + 0x400000 + offset;
+}
+
+static inline unsigned long dbg_addr(struct map_info *map, unsigned long addr)
+{
+ return addr - map->map_priv_1 + ICH2_FWH_REGION_START;
+}
+
+static __u8 ich2rom_read8(struct map_info *map, unsigned long ofs)
+{
+ return __raw_readb(addr(map, ofs));
+}
+
+static __u16 ich2rom_read16(struct map_info *map, unsigned long ofs)
+{
+ return __raw_readw(addr(map, ofs));
+}
+
+static __u32 ich2rom_read32(struct map_info *map, unsigned long ofs)
+{
+ return __raw_readl(addr(map, ofs));
+}
+
+static void ich2rom_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
+{
+ memcpy_fromio(to, addr(map, from), len);
+}
+
+static void ich2rom_write8(struct map_info *map, __u8 d, unsigned long ofs)
+{
+ __raw_writeb(d, addr(map,ofs));
+ mb();
+}
+
+static void ich2rom_write16(struct map_info *map, __u16 d, unsigned long ofs)
+{
+ __raw_writew(d, addr(map, ofs));
+ mb();
+}
+
+static void ich2rom_write32(struct map_info *map, __u32 d, unsigned long ofs)
+{
+ __raw_writel(d, addr(map, ofs));
+ mb();
+}
+
+static void ich2rom_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
+{
+ memcpy_toio(addr(map, to), from, len);
+}
+
+static struct ich2rom_map_info ich2rom_map = {
+ map: {
+ name: "ICH2 rom",
+ size: 0,
+ buswidth: 1,
+ read8: ich2rom_read8,
+ read16: ich2rom_read16,
+ read32: ich2rom_read32,
+ copy_from: ich2rom_copy_from,
+ write8: ich2rom_write8,
+ write16: ich2rom_write16,
+ write32: ich2rom_write32,
+ copy_to: ich2rom_copy_to,
+ /* Firmware hubs only use vpp when being programmed
+ * in a factory setting. So in place programming
+ * needs to use a different method.
+ */
+ },
+ mtd: 0,
+ window_addr: 0,
+};
+
+enum fwh_lock_state {
+ FWH_DENY_WRITE = 1,
+ FWH_IMMUTABLE = 2,
+ FWH_DENY_READ = 4,
+};
+
+static int ich2rom_set_lock_state(struct mtd_info *mtd, loff_t ofs, size_t len,
+ enum fwh_lock_state state)
+{
+ struct map_info *map = mtd->priv;
+ unsigned long start = ofs;
+ unsigned long end = start + len -1;
+
+ /* FIXME do I need to guard against concurrency here? */
+ /* round down to 64K boundaries */
+ start = start & ~0xFFFF;
+ end = end & ~0xFFFF;
+ while (start <= end) {
+ unsigned long ctrl_addr;
+ ctrl_addr = addr(map, start) - 0x400000 + 2;
+ writeb(state, ctrl_addr);
+ start = start + 0x10000;
+ }
+ return 0;
+}
+
+static int ich2rom_lock(struct mtd_info *mtd, loff_t ofs, size_t len)
+{
+ return ich2rom_set_lock_state(mtd, ofs, len, FWH_DENY_WRITE);
+}
+
+static int ich2rom_unlock(struct mtd_info *mtd, loff_t ofs, size_t len)
+{
+ return ich2rom_set_lock_state(mtd, ofs, len, 0);
+}
+
+static int __devinit ich2rom_init_one (struct pci_dev *pdev,
+ const struct pci_device_id *ent)
+{
+ u16 word;
+ struct ich2rom_map_info *info = &ich2rom_map;
+ unsigned long map_size;
+
+ /* For now I just handle the ich2 and I assume there
+ * are not a lot of resources up at the top of the address
+ * space. It is possible to handle other devices in the
+ * top 16MB but it is very painful. Also since
+ * you can only really attach a FWH to an ICH2 there
+ * a number of simplifications you can make.
+ *
+ * Also you can page firmware hubs if an 8MB window isn't enough
+ * but don't currently handle that case either.
+ */
+
+#if RESERVE_MEM_REGION
+ /* Some boards have this reserved and I haven't found a good work
+ * around to say I know what I'm doing!
+ */
+ if (!request_mem_region(ICH2_FWH_REGION_START, ICH2_FWH_REGION_SIZE, "ich2rom")) {
+ printk(KERN_ERR "ich2rom: cannot reserve rom window\n");
+ goto err_out_none;
+ }
+#endif /* RESERVE_MEM_REGION */
+
+ /* Enable writes through the rom window */
+ pci_read_config_word(pdev, BIOS_CNTL, &word);
+ if (!(word & 1) && (word & (1<<1))) {
+ /* The BIOS will generate an error if I enable
+ * this device, so don't even try.
+ */
+ printk(KERN_ERR "ich2rom: firmware access control, I can't enable writes\n");
+ goto err_out_none;
+ }
+ pci_write_config_word(pdev, BIOS_CNTL, word | 1);
+
+
+ /* Map the firmware hub into my address space. */
+ /* Does this use to much virtual address space? */
+ info->window_addr = (unsigned long)ioremap(
+ ICH2_FWH_REGION_START, ICH2_FWH_REGION_SIZE);
+ if (!info->window_addr) {
+ printk(KERN_ERR "Failed to ioremap\n");
+ goto err_out_free_mmio_region;
+ }
+
+ /* For now assume the firmware has setup all relavent firmware
+ * windows. We don't have enough information to handle this case
+ * intelligently.
+ */
+
+ /* FIXME select the firmware hub and enable a window to it. */
+
+ info->mtd = 0;
+ info->map.map_priv_1 = info->window_addr;
+
+ map_size = ICH2_FWH_REGION_SIZE;
+ while(!info->mtd && (map_size > 0)) {
+ info->map.size = map_size;
+ info->mtd = do_map_probe("jedec_probe", &ich2rom_map.map);
+ map_size -= 512*1024;
+ }
+ if (!info->mtd) {
+ goto err_out_iounmap;
+ }
+ /* I know I can only be a firmware hub here so put
+ * in the special lock and unlock routines.
+ */
+ info->mtd->lock = ich2rom_lock;
+ info->mtd->unlock = ich2rom_unlock;
+
+ info->mtd->module = THIS_MODULE;
+ add_mtd_device(info->mtd);
+ return 0;
+
+err_out_iounmap:
+ iounmap((void *)(info->window_addr));
+err_out_free_mmio_region:
+#if RESERVE_MEM_REGION
+ release_mem_region(ICH2_FWH_REGION_START, ICH2_FWH_REGION_SIZE);
+#endif
+err_out_none:
+ return -ENODEV;
+}
+
+
+static void __devexit ich2rom_remove_one (struct pci_dev *pdev)
+{
+ struct ich2rom_map_info *info = &ich2rom_map;
+ u16 word;
+
+ del_mtd_device(info->mtd);
+ map_destroy(info->mtd);
+ info->mtd = 0;
+ info->map.map_priv_1 = 0;
+
+ iounmap((void *)(info->window_addr));
+ info->window_addr = 0;
+
+ /* Disable writes through the rom window */
+ pci_read_config_word(pdev, BIOS_CNTL, &word);
+ pci_write_config_word(pdev, BIOS_CNTL, word & ~1);
+
+#if RESERVE_MEM_REGION
+ release_mem_region(ICH2_FWH_REGION_START, ICH2_FWH_REGION_SIZE);
+#endif
+}
+
+static struct pci_device_id ich2rom_pci_tbl[] __devinitdata = {
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0,
+ PCI_ANY_ID, PCI_ANY_ID, },
+};
+
+MODULE_DEVICE_TABLE(pci, ich2rom_pci_tbl);
+
+#if 0
+static struct pci_driver ich2rom_driver = {
+ name: "ich2rom",
+ id_table: ich2rom_pci_tbl,
+ probe: ich2rom_init_one,
+ remove: ich2rom_remove_one,
+};
+#endif
+
+static struct pci_dev *mydev;
+int __init init_ich2rom(void)
+{
+ struct pci_dev *pdev;
+ pdev = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, 0);
+ if (pdev) {
+ mydev = pdev;
+ return ich2rom_init_one(pdev, &ich2rom_pci_tbl[0]);
+ }
+ return -ENXIO;
+#if 0
+ return pci_module_init(&ich2rom_driver);
+#endif
+}
+
+static void __exit cleanup_ich2rom(void)
+{
+ ich2rom_remove_one(mydev);
+}
+
+module_init(init_ich2rom);
+module_exit(cleanup_ich2rom);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Eric Biederman ");
+MODULE_DESCRIPTION("MTD map driver for BIOS chips on the ICH2 southbridge");
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/mtd/maps/mbx860.c linux-2.5/drivers/mtd/maps/mbx860.c
--- linux-2.5.60/drivers/mtd/maps/mbx860.c 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/drivers/mtd/maps/mbx860.c 2003-02-11 10:49:37.000000000 -0100
@@ -0,0 +1,144 @@
+/*
+ * $Id: mbx860.c,v 1.1 2001/11/18 19:43:09 dwmw2 Exp $
+ *
+ * Handle mapping of the flash on MBX860 boards
+ *
+ * Author: Anton Todorov
+ * Copyright: (C) 2001 Emness Technology
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+
+#define WINDOW_ADDR 0xfe000000
+#define WINDOW_SIZE 0x00200000
+
+/* Flash / Partition sizing */
+#define MAX_SIZE_KiB 8192
+#define BOOT_PARTITION_SIZE_KiB 512
+#define KERNEL_PARTITION_SIZE_KiB 5632
+#define APP_PARTITION_SIZE_KiB 2048
+
+#define NUM_PARTITIONS 3
+
+/* partition_info gives details on the logical partitions that the split the
+ * single flash device into. If the size if zero we use up to the end of the
+ * device. */
+static struct mtd_partition partition_info[]={
+ { name: "MBX flash BOOT partition",
+ offset: 0,
+ size: BOOT_PARTITION_SIZE_KiB*1024 },
+ { name: "MBX flash DATA partition",
+ offset: BOOT_PARTITION_SIZE_KiB*1024,
+ size: (KERNEL_PARTITION_SIZE_KiB)*1024 },
+ { name: "MBX flash APPLICATION partition",
+ offset: (BOOT_PARTITION_SIZE_KiB+KERNEL_PARTITION_SIZE_KiB)*1024 }
+};
+
+
+static struct mtd_info *mymtd;
+
+__u8 mbx_read8(struct map_info *map, unsigned long ofs)
+{
+ return readb(map->map_priv_1 + ofs);
+}
+
+__u16 mbx_read16(struct map_info *map, unsigned long ofs)
+{
+ return readw(map->map_priv_1 + ofs);
+}
+
+__u32 mbx_read32(struct map_info *map, unsigned long ofs)
+{
+ return readl(map->map_priv_1 + ofs);
+}
+
+void mbx_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
+{
+ memcpy_fromio(to, (void *)(map->map_priv_1 + from), len);
+}
+
+void mbx_write8(struct map_info *map, __u8 d, unsigned long adr)
+{
+ writeb(d, map->map_priv_1 + adr);
+}
+
+void mbx_write16(struct map_info *map, __u16 d, unsigned long adr)
+{
+ writew(d, map->map_priv_1 + adr);
+}
+
+void mbx_write32(struct map_info *map, __u32 d, unsigned long adr)
+{
+ writel(d, map->map_priv_1 + adr);
+}
+
+void mbx_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
+{
+ memcpy_toio((void *)(map->map_priv_1 + to), from, len);
+}
+
+struct map_info mbx_map = {
+ name: "MBX flash",
+ size: WINDOW_SIZE,
+ buswidth: 4,
+ read8: mbx_read8,
+ read16: mbx_read16,
+ read32: mbx_read32,
+ copy_from: mbx_copy_from,
+ write8: mbx_write8,
+ write16: mbx_write16,
+ write32: mbx_write32,
+ copy_to: mbx_copy_to
+};
+
+int __init init_mbx(void)
+{
+ printk(KERN_NOTICE "Motorola MBX flash device: %x at %x\n", WINDOW_SIZE*4, WINDOW_ADDR);
+ mbx_map.map_priv_1 = (unsigned long)ioremap(WINDOW_ADDR, WINDOW_SIZE * 4);
+
+ if (!mbx_map.map_priv_1) {
+ printk("Failed to ioremap\n");
+ return -EIO;
+ }
+ mymtd = do_map_probe("jedec_probe", &mbx_map);
+ if (mymtd) {
+ mymtd->module = THIS_MODULE;
+ add_mtd_device(mymtd);
+ add_mtd_partitions(mymtd, partition_info, NUM_PARTITIONS);
+ return 0;
+ }
+
+ iounmap((void *)mbx_map.map_priv_1);
+ return -ENXIO;
+}
+
+static void __exit cleanup_mbx(void)
+{
+ if (mymtd) {
+ del_mtd_device(mymtd);
+ map_destroy(mymtd);
+ }
+ if (mbx_map.map_priv_1) {
+ iounmap((void *)mbx_map.map_priv_1);
+ mbx_map.map_priv_1 = 0;
+ }
+}
+
+module_init(init_mbx);
+module_exit(cleanup_mbx);
+
+MODULE_AUTHOR("Anton Todorov ");
+MODULE_DESCRIPTION("MTD map driver for Motorola MBX860 board");
+MODULE_LICENSE("GPL");
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/mtd/maps/pb1xxx-flash.c linux-2.5/drivers/mtd/maps/pb1xxx-flash.c
--- linux-2.5.60/drivers/mtd/maps/pb1xxx-flash.c 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/drivers/mtd/maps/pb1xxx-flash.c 2003-02-11 10:49:37.000000000 -0100
@@ -0,0 +1,253 @@
+/*
+ * Flash memory access on Alchemy Pb1xxx boards
+ *
+ * (C) 2001 Pete Popov
+ *
+ * $Id: pb1xxx-flash.c,v 1.5 2002/02/01 23:08:50 ppopov Exp $
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+
+#ifdef DEBUG_RW
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+#ifdef CONFIG_MIPS_PB1000
+#define WINDOW_ADDR 0x1F800000
+#define WINDOW_SIZE 0x800000
+#endif
+
+__u8 physmap_read8(struct map_info *map, unsigned long ofs)
+{
+ __u8 ret;
+ ret = __raw_readb(map->map_priv_1 + ofs);
+ DBG("read8 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret);
+ return ret;
+}
+
+__u16 physmap_read16(struct map_info *map, unsigned long ofs)
+{
+ __u16 ret;
+ ret = __raw_readw(map->map_priv_1 + ofs);
+ DBG("read16 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret);
+ return ret;
+}
+
+__u32 physmap_read32(struct map_info *map, unsigned long ofs)
+{
+ __u32 ret;
+ ret = __raw_readl(map->map_priv_1 + ofs);
+ DBG("read32 from %x, %x\n", (unsigned)(map->map_priv_1 + ofs), ret);
+ return ret;
+}
+
+void physmap_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
+{
+ DBG("physmap_copy from %x to %x\n", (unsigned)from, (unsigned)to);
+ memcpy_fromio(to, map->map_priv_1 + from, len);
+}
+
+void physmap_write8(struct map_info *map, __u8 d, unsigned long adr)
+{
+ DBG("write8 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d);
+ __raw_writeb(d, map->map_priv_1 + adr);
+ mb();
+}
+
+void physmap_write16(struct map_info *map, __u16 d, unsigned long adr)
+{
+ DBG("write16 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d);
+ __raw_writew(d, map->map_priv_1 + adr);
+ mb();
+}
+
+void physmap_write32(struct map_info *map, __u32 d, unsigned long adr)
+{
+ DBG("write32 at %x, %x\n", (unsigned)(map->map_priv_1 + adr), d);
+ __raw_writel(d, map->map_priv_1 + adr);
+ mb();
+}
+
+void physmap_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
+{
+ DBG("physmap_copy_to %x from %x\n", (unsigned)to, (unsigned)from);
+ memcpy_toio(map->map_priv_1 + to, from, len);
+}
+
+
+
+static struct map_info pb1xxx_map = {
+ name: "Pb1xxx flash",
+ read8: physmap_read8,
+ read16: physmap_read16,
+ read32: physmap_read32,
+ copy_from: physmap_copy_from,
+ write8: physmap_write8,
+ write16: physmap_write16,
+ write32: physmap_write32,
+ copy_to: physmap_copy_to,
+};
+
+
+#ifdef CONFIG_MIPS_PB1000
+
+static unsigned long flash_size = 0x00800000;
+static unsigned char flash_buswidth = 4;
+static struct mtd_partition pb1xxx_partitions[] = {
+ {
+ name: "yamon env",
+ size: 0x00020000,
+ offset: 0,
+ mask_flags: MTD_WRITEABLE
+ },{
+ name: "User FS",
+ size: 0x003e0000,
+ offset: 0x20000,
+ },{
+ name: "boot code",
+ size: 0x100000,
+ offset: 0x400000,
+ mask_flags: MTD_WRITEABLE
+ },{
+ name: "raw/kernel",
+ size: 0x300000,
+ offset: 0x500000
+ }
+};
+
+#elif defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_PB1100)
+
+static unsigned char flash_buswidth = 4;
+#if defined(CONFIG_MTD_PB1500_BOOT) && defined(CONFIG_MTD_PB1500_USER)
+/* both 32MB banks will be used. Combine the first 32MB bank and the
+ * first 28MB of the second bank together into a single jffs/jffs2
+ * partition.
+ */
+static unsigned long flash_size = 0x04000000;
+#define WINDOW_ADDR 0x1C000000
+#define WINDOW_SIZE 0x4000000
+static struct mtd_partition pb1xxx_partitions[] = {
+ {
+ name: "User FS",
+ size: 0x3c00000,
+ offset: 0x0000000
+ },{
+ name: "yamon",
+ size: 0x0100000,
+ offset: 0x3c00000,
+ mask_flags: MTD_WRITEABLE
+ },{
+ name: "raw kernel",
+ size: 0x02c0000,
+ offset: 0x3d00000
+ }
+};
+#elif defined(CONFIG_MTD_PB1500_BOOT) && !defined(CONFIG_MTD_PB1500_USER)
+static unsigned long flash_size = 0x02000000;
+#define WINDOW_ADDR 0x1E000000
+#define WINDOW_SIZE 0x2000000
+static struct mtd_partition pb1xxx_partitions[] = {
+ {
+ name: "User FS",
+ size: 0x1c00000,
+ offset: 0x0000000
+ },{
+ name: "yamon",
+ size: 0x0100000,
+ offset: 0x1c00000,
+ mask_flags: MTD_WRITEABLE
+ },{
+ name: "raw kernel",
+ size: 0x02c0000,
+ offset: 0x1d00000
+ }
+};
+#elif !defined(CONFIG_MTD_PB1500_BOOT) && defined(CONFIG_MTD_PB1500_USER)
+static unsigned long flash_size = 0x02000000;
+#define WINDOW_ADDR 0x1C000000
+#define WINDOW_SIZE 0x2000000
+static struct mtd_partition pb1xxx_partitions[] = {
+ {
+ name: "User FS",
+ size: 0x1e00000,
+ offset: 0x0000000
+ },{
+ name: "raw kernel",
+ size: 0x0200000,
+ offset: 0x1e00000,
+ }
+};
+#else
+#error MTD_PB1500 define combo error /* should never happen */
+#endif
+#else
+#error Unsupported board
+#endif
+
+
+#define NB_OF(x) (sizeof(x)/sizeof(x[0]))
+
+static struct mtd_partition *parsed_parts;
+static struct mtd_info *mymtd;
+
+int __init pb1xxx_mtd_init(void)
+{
+ struct mtd_partition *parts;
+ int nb_parts = 0;
+ char *part_type;
+
+ /* Default flash buswidth */
+ pb1xxx_map.buswidth = flash_buswidth;
+
+ /*
+ * Static partition definition selection
+ */
+ part_type = "static";
+ parts = pb1xxx_partitions;
+ nb_parts = NB_OF(pb1xxx_partitions);
+ pb1xxx_map.size = flash_size;
+
+ /*
+ * Now let's probe for the actual flash. Do it here since
+ * specific machine settings might have been set above.
+ */
+ printk(KERN_NOTICE "Pb1xxx flash: probing %d-bit flash bus\n",
+ pb1xxx_map.buswidth*8);
+ pb1xxx_map.map_priv_1 =
+ (unsigned long)ioremap(WINDOW_ADDR, WINDOW_SIZE);
+ mymtd = do_map_probe("cfi_probe", &pb1xxx_map);
+ if (!mymtd) return -ENXIO;
+ mymtd->module = THIS_MODULE;
+
+ add_mtd_partitions(mymtd, parts, nb_parts);
+ return 0;
+}
+
+static void __exit pb1xxx_mtd_cleanup(void)
+{
+ if (mymtd) {
+ del_mtd_partitions(mymtd);
+ map_destroy(mymtd);
+ if (parsed_parts)
+ kfree(parsed_parts);
+ }
+}
+
+module_init(pb1xxx_mtd_init);
+module_exit(pb1xxx_mtd_cleanup);
+
+MODULE_AUTHOR("Pete Popov");
+MODULE_DESCRIPTION("Pb1xxx CFI map driver");
+MODULE_LICENSE("GPL");
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/mtd/maps/tsunami_flash.c linux-2.5/drivers/mtd/maps/tsunami_flash.c
--- linux-2.5.60/drivers/mtd/maps/tsunami_flash.c 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/drivers/mtd/maps/tsunami_flash.c 2003-02-11 10:49:37.000000000 -0100
@@ -0,0 +1,110 @@
+/*
+ * tsunami_flash.c
+ *
+ * flash chip on alpha ds10...
+ * $Id: tsunami_flash.c,v 1.1 2002/01/10 22:59:13 eric Exp $
+ */
+#include
+#include
+#include
+
+#define FLASH_ENABLE_PORT 0x00C00001
+#define FLASH_ENABLE_BYTE 0x01
+#define FLASH_DISABLE_BYTE 0x00
+
+#define MAX_TIG_FLASH_SIZE (12*1024*1024)
+static inline __u8 tsunami_flash_read8(struct map_info *map, unsigned long offset)
+{
+ return tsunami_tig_readb(offset);
+}
+
+static void tsunami_flash_write8(struct map_info *map, __u8 value, unsigned long offset)
+{
+ tsunami_tig_writeb(value, offset);
+}
+
+static void tsunami_flash_copy_from(
+ struct map_info *map, void *addr, unsigned long offset, ssize_t len)
+{
+ unsigned char *dest;
+ dest = addr;
+ while(len && (offset < MAX_TIG_FLASH_SIZE)) {
+ *dest = tsunami_tig_readb(offset);
+ offset++;
+ dest++;
+ len--;
+ }
+}
+
+static void tsunami_flash_copy_to(
+ struct map_info *map, unsigned long offset,
+ const void *addr, ssize_t len)
+{
+ const unsigned char *src;
+ src = addr;
+ while(len && (offset < MAX_TIG_FLASH_SIZE)) {
+ tsunami_tig_writeb(*src, offset);
+ offset++;
+ src++;
+ len--;
+ }
+}
+
+/*
+ * Deliberately don't provide operations wider than 8 bits. I don't
+ * have then and it scares me to think how you could mess up if
+ * you tried to use them. Buswidth is correctly so I'm safe.
+ */
+static struct map_info tsunami_flash_map = {
+ .name = "flash chip on the Tsunami TIG bus",
+ .size = MAX_TIG_FLASH_SIZE,
+ .buswidth = 1,
+ .read8 = tsunami_flash_read8,
+ .read16 = 0,
+ .read32 = 0,
+ .copy_from = tsunami_flash_copy_from,
+ .write8 = tsunami_flash_write8,
+ .write16 = 0,
+ .write32 = 0,
+ .copy_to = tsunami_flash_copy_to,
+ .set_vpp = 0,
+ .map_priv_1 = 0,
+
+};
+
+static struct mtd_info *tsunami_flash_mtd;
+
+static void __exit cleanup_tsunami_flash(void)
+{
+ struct mtd_info *mtd;
+ mtd = tsunami_flash_mtd;
+ if (mtd) {
+ del_mtd_device(mtd);
+ map_destroy(mtd);
+ }
+ tsunami_flash_mtd = 0;
+}
+
+
+static int __init init_tsunami_flash(void)
+{
+ static const char *rom_probe_types[] = { "cfi_probe", "jedec_probe", "map_rom", 0 };
+ char **type;
+
+ tsunami_tig_writeb(FLASH_ENABLE_BYTE, FLASH_ENABLE_PORT);
+
+ tsunami_flash_mtd = 0;
+ type = rom_probe_types;
+ for(; !tsunami_flash_mtd && *type; type++) {
+ tsunami_flash_mtd = do_map_probe(*type, &tsunami_flash_map);
+ }
+ if (tsunami_flash_mtd) {
+ tsunami_flash_mtd->module = THIS_MODULE;
+ add_mtd_device(tsunami_flash_mtd);
+ return 0;
+ }
+ return -ENXIO;
+}
+
+module_init(init_tsunami_flash);
+module_exit(cleanup_tsunami_flash);
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/3c509.c linux-2.5/drivers/net/3c509.c
--- linux-2.5.60/drivers/net/3c509.c 2003-02-10 17:37:57.000000000 -0100
+++ linux-2.5/drivers/net/3c509.c 2003-02-11 10:27:23.000000000 -0100
@@ -338,16 +338,6 @@ static int __init el3_common_init (struc
dev->watchdog_timeo = TX_TIMEOUT;
dev->do_ioctl = netdev_ioctl;
-#ifdef CONFIG_PM
- /* register power management */
- lp->pmdev = pm_register(PM_ISA_DEV, card_idx, el3_pm_callback);
- if (lp->pmdev) {
- struct pm_dev *p;
- p = lp->pmdev;
- p->data = (struct net_device *)dev;
- }
-#endif
-
return 0;
}
@@ -417,6 +407,13 @@ static int __init el3_probe(int card_idx
phys_addr[j] =
htons(read_eeprom(ioaddr, j));
if_port = read_eeprom(ioaddr, 8) >> 14;
+ if (!(dev = init_etherdev(NULL, sizeof(struct el3_private)))) {
+ release_region(ioaddr, EL3_IO_EXTENT);
+ pnp_device_detach(idev);
+ return -ENOMEM;
+ }
+
+ SET_MODULE_OWNER(dev);
pnp_cards++;
goto found;
}
@@ -497,24 +494,29 @@ no_pnp:
}
irq = id_read_eeprom(9) >> 12;
-#if 0 /* Huh ?
- Can someone explain what is this for ? */
- if (dev) { /* Set passed-in IRQ or I/O Addr. */
- if (dev->irq > 1 && dev->irq < 16)
+ if (!(dev = init_etherdev(NULL, sizeof(struct el3_private))))
+ return -ENOMEM;
+
+ SET_MODULE_OWNER(dev);
+
+ /* Set passed-in IRQ or I/O Addr. */
+ if (dev->irq > 1 && dev->irq < 16)
irq = dev->irq;
- if (dev->base_addr) {
+ if (dev->base_addr) {
if (dev->mem_end == 0x3c509 /* Magic key */
&& dev->base_addr >= 0x200 && dev->base_addr <= 0x3e0)
- ioaddr = dev->base_addr & 0x3f0;
- else if (dev->base_addr != ioaddr)
- return -ENODEV;
- }
+ ioaddr = dev->base_addr & 0x3f0;
+ else if (dev->base_addr != ioaddr) {
+ unregister_netdev (dev);
+ return -ENODEV;
+ }
}
-#endif
- if (!request_region(ioaddr, EL3_IO_EXTENT, "3c509"))
- return -EBUSY;
+ if (!request_region(ioaddr, EL3_IO_EXTENT, "3c509")) {
+ unregister_netdev (dev);
+ return -EBUSY;
+ }
/* Set the adaptor tag so that the next card can be found. */
outb(0xd0 + ++current_tag, id_port);
@@ -524,6 +526,7 @@ no_pnp:
EL3WINDOW(0);
if (inw(ioaddr) != 0x6d50) {
+ unregister_netdev (dev);
release_region(ioaddr, EL3_IO_EXTENT);
return -ENODEV;
}
@@ -531,12 +534,9 @@ no_pnp:
/* Free the interrupt so that some other card can use it. */
outw(0x0f00, ioaddr + WN0_IRQ);
- dev = init_etherdev(NULL, sizeof(struct el3_private));
- if (dev == NULL) {
- release_region(ioaddr, EL3_IO_EXTENT);
- return -ENOMEM;
- }
- SET_MODULE_OWNER(dev);
+#ifdef __ISAPNP__
+ found: /* PNP jumps here... */
+#endif /* __ISAPNP__ */
memcpy(dev->dev_addr, phys_addr, sizeof(phys_addr));
dev->base_addr = ioaddr;
@@ -547,6 +547,16 @@ no_pnp:
lp->dev = &idev->dev;
#endif
+#ifdef CONFIG_PM
+ /* register power management */
+ lp->pmdev = pm_register(PM_ISA_DEV, card_idx, el3_pm_callback);
+ if (lp->pmdev) {
+ struct pm_dev *p;
+ p = lp->pmdev;
+ p->data = (struct net_device *)dev;
+ }
+#endif
+
return el3_common_init (dev);
}
@@ -667,6 +677,7 @@ static int __init el3_eisa_probe (struct
}
#endif
+#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
/* This remove works for all device types.
*
* The net dev must be stored in the driver_data field */
@@ -679,6 +690,7 @@ static int __devexit el3_device_remove (
el3_common_remove (dev);
return 0;
}
+#endif
/* Read a word from the EEPROM using the regular EEPROM access register.
Assume that we are in register window zero.
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/3c59x.c linux-2.5/drivers/net/3c59x.c
--- linux-2.5.60/drivers/net/3c59x.c 2003-02-10 17:37:54.000000000 -0100
+++ linux-2.5/drivers/net/3c59x.c 2003-02-11 10:27:23.000000000 -0100
@@ -181,7 +181,7 @@
- See http://www.zip.com.au/~akpm/linux/#3c59x-2.3 for more details.
- Also see Documentation/networking/vortex.txt
- LK1.1.19 10Nov09 Marc Zyngier
+ LK1.1.19 10Nov02 Marc Zyngier
- EISA sysfs integration.
*/
@@ -817,7 +817,11 @@ struct vortex_private {
u32 power_state[16];
};
+#ifdef CONFIG_PCI
#define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
+#else
+#define DEVICE_PCI(dev) NULL
+#endif
#define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/Space.c linux-2.5/drivers/net/Space.c
--- linux-2.5.60/drivers/net/Space.c 2003-02-10 17:37:58.000000000 -0100
+++ linux-2.5/drivers/net/Space.c 2003-02-11 10:27:23.000000000 -0100
@@ -224,9 +224,6 @@ static struct devprobe isa_probes[] __in
#ifdef CONFIG_EL2 /* 3c503 */
{el2_probe, 0},
#endif
-#ifdef CONFIG_EL3
- {el3_probe, 0},
-#endif
#ifdef CONFIG_HPLAN
{hp_probe, 0},
#endif
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/aironet4500_core.c linux-2.5/drivers/net/aironet4500_core.c
--- linux-2.5.60/drivers/net/aironet4500_core.c 2003-02-10 17:37:54.000000000 -0100
+++ linux-2.5/drivers/net/aironet4500_core.c 2003-02-11 10:49:38.000000000 -0100
@@ -2210,7 +2210,7 @@ awc_tx_complete_check(struct net_device
void
-awc_bh(struct net_device *dev){
+awc_work(struct net_device *dev){
struct awc_private * priv = (struct awc_private *)dev->priv;
int active_interrupts;
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/au1000_eth.c linux-2.5/drivers/net/au1000_eth.c
--- linux-2.5.60/drivers/net/au1000_eth.c 2003-02-10 17:38:42.000000000 -0100
+++ linux-2.5/drivers/net/au1000_eth.c 2003-01-17 00:58:21.000000000 -0100
@@ -675,37 +675,24 @@ au1000_probe1(struct net_device *dev, lo
char *pmac, *argptr;
char ethaddr[6];
- if (!request_region(ioaddr, MAC_IOSIZE, "Au1000 ENET")) {
+ if (!request_region(ioaddr, MAC_IOSIZE, "Au1000 ENET"))
return -ENODEV;
- }
if (version_printed++ == 0) printk(version);
- if (!dev) {
+ if (!dev)
dev = init_etherdev(0, sizeof(struct au1000_private));
- }
+
if (!dev) {
- printk (KERN_ERR "au1000 eth: init_etherdev failed\n");
- return -ENODEV;
+ printk (KERN_ERR "au1000 eth: init_etherdev failed\n");
+ release_region(ioaddr, MAC_IOSIZE);
+ return -ENODEV;
}
printk("%s: Au1xxx ethernet found at 0x%lx, irq %d\n",
dev->name, ioaddr, irq);
- /* Initialize our private structure */
- if (dev->priv == NULL) {
- aup = (struct au1000_private *)
- kmalloc(sizeof(*aup), GFP_KERNEL);
- if (aup == NULL) {
- retval = -ENOMEM;
- goto free_region;
- }
- dev->priv = aup;
- }
-
aup = dev->priv;
- memset(aup, 0, sizeof(*aup));
-
/* Allocate the data buffers */
aup->vaddr = (u32)dma_alloc(MAX_BUF_SIZE *
@@ -834,8 +821,6 @@ free_region:
if (aup->vaddr)
dma_free((void *)aup->vaddr,
MAX_BUF_SIZE * (NUM_TX_BUFFS+NUM_RX_BUFFS));
- if (dev->priv != NULL)
- kfree(dev->priv);
printk(KERN_ERR "%s: au1000_probe1 failed. Returns %d\n",
dev->name, retval);
kfree(dev);
@@ -1003,15 +988,15 @@ static int au1000_close(struct net_devic
spin_lock_irqsave(&aup->lock, flags);
/* stop the device */
- if (netif_device_present(dev)) {
+ if (netif_device_present(dev))
netif_stop_queue(dev);
- }
/* disable the interrupt */
free_irq(dev->irq, dev);
spin_unlock_irqrestore(&aup->lock, flags);
reset_mac(dev);
+ kfree(dev);
MOD_DEC_USE_COUNT;
return 0;
}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/bmac.c linux-2.5/drivers/net/bmac.c
--- linux-2.5.60/drivers/net/bmac.c 2003-02-10 17:37:57.000000000 -0100
+++ linux-2.5/drivers/net/bmac.c 2003-01-17 00:58:21.000000000 -0100
@@ -1401,10 +1401,7 @@ static void __init bmac_probe1(struct de
bp->queue = (struct sk_buff_head *)(bp->rx_cmds + N_RX_RING + 1);
skb_queue_head_init(bp->queue);
- memset((char *) bp->tx_cmds, 0,
- (N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd));
init_timer(&bp->tx_timeout);
- /* bp->timeout_active = 0; */
ret = request_irq(dev->irq, bmac_misc_intr, 0, "BMAC-misc", dev);
if (ret) {
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/cs89x0.h linux-2.5/drivers/net/cs89x0.h
--- linux-2.5.60/drivers/net/cs89x0.h 2003-02-10 17:38:46.000000000 -0100
+++ linux-2.5/drivers/net/cs89x0.h 2003-01-17 00:58:21.000000000 -0100
@@ -385,11 +385,11 @@
#define A_CNF_10B_T 0x0001
#define A_CNF_AUI 0x0002
#define A_CNF_10B_2 0x0004
-#define A_CNF_MEDIA_TYPE 0x0060
-#define A_CNF_MEDIA_AUTO 0x0000
+#define A_CNF_MEDIA_TYPE 0x0070
+#define A_CNF_MEDIA_AUTO 0x0070
#define A_CNF_MEDIA_10B_T 0x0020
#define A_CNF_MEDIA_AUI 0x0040
-#define A_CNF_MEDIA_10B_2 0x0060
+#define A_CNF_MEDIA_10B_2 0x0010
#define A_CNF_DC_DC_POLARITY 0x0080
#define A_CNF_NO_AUTO_POLARITY 0x2000
#define A_CNF_LOW_RX_SQUELCH 0x4000
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/depca.c linux-2.5/drivers/net/depca.c
--- linux-2.5.60/drivers/net/depca.c 2003-02-10 17:38:39.000000000 -0100
+++ linux-2.5/drivers/net/depca.c 2003-01-13 14:01:26.000000000 -0100
@@ -334,16 +334,6 @@ static enum {
#define MAX_NUM_DEPCAS 2
/*
-** Memory Alignment. Each descriptor is 4 longwords long. To force a
-** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
-** DESC_ALIGN. DEPCA_ALIGN aligns the start address of the private memory area
-** and hence the RX descriptor ring's first entry.
-*/
-#define DEPCA_ALIGN4 ((u_long)4 - 1) /* 1 longword align */
-#define DEPCA_ALIGN8 ((u_long)8 - 1) /* 2 longword (quadword) align */
-#define DEPCA_ALIGN DEPCA_ALIGN8 /* Keep the LANCE happy... */
-
-/*
** The DEPCA Rx and Tx ring descriptors.
*/
struct depca_rx_desc {
@@ -627,7 +617,7 @@ static int __init depca_hw_init(struct n
offset += sizeof(struct depca_init);
/* Tx & Rx descriptors (aligned to a quadword boundary) */
- offset = (offset + DEPCA_ALIGN) & ~DEPCA_ALIGN;
+ offset = ALIGN(offset, 8);
lp->rx_ring = (struct depca_rx_desc *) (lp->sh_mem + offset);
lp->rx_ring_offset = offset;
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/e100/e100_main.c linux-2.5/drivers/net/e100/e100_main.c
--- linux-2.5.60/drivers/net/e100/e100_main.c 2003-02-10 17:38:31.000000000 -0100
+++ linux-2.5/drivers/net/e100/e100_main.c 2003-02-04 15:43:51.000000000 -0100
@@ -3783,7 +3783,7 @@ static int e100_ethtool_gstrings(struct
struct ethtool_gstrings info;
char *strings = NULL;
char *usr_strings;
- int i;
+ int i, rc=0;
memset((void *) &info, 0, sizeof(info));
@@ -3824,14 +3824,17 @@ static int e100_ethtool_gstrings(struct
return -EOPNOTSUPP;
}
- if (copy_to_user(ifr->ifr_data, &info, sizeof (info)))
- return -EFAULT;
+ if (copy_to_user(ifr->ifr_data, &info, sizeof (info))) {
+ rc = -EFAULT;
+ goto out;
+ }
if (copy_to_user(usr_strings, strings, info.len * ETH_GSTRING_LEN))
- return -EFAULT;
+ rc = -EFAULT;
+out:
kfree(strings);
- return 0;
+ return rc;
}
static int
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/fc/iph5526.c linux-2.5/drivers/net/fc/iph5526.c
--- linux-2.5.60/drivers/net/fc/iph5526.c 2003-02-10 17:38:03.000000000 -0100
+++ linux-2.5/drivers/net/fc/iph5526.c 2003-01-17 00:58:23.000000000 -0100
@@ -2984,8 +2984,7 @@ static int iph5526_send_packet(struct sk
*/
if ((type == ETH_P_ARP) || (status == 0))
dev_kfree_skb(skb);
- else
- netif_wake_queue(dev);
+ netif_wake_queue(dev);
LEAVE("iph5526_send_packet");
return 0;
}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/gt96100eth.c linux-2.5/drivers/net/gt96100eth.c
--- linux-2.5.60/drivers/net/gt96100eth.c 2003-02-10 17:38:49.000000000 -0100
+++ linux-2.5/drivers/net/gt96100eth.c 2003-01-06 18:00:54.000000000 -0100
@@ -758,19 +758,6 @@ gt96100_probe1(int port_num)
goto free_region;
}
- /* Initialize our private structure. */
- if (dev->priv == NULL) {
-
- gp = (struct gt96100_private *)kmalloc(sizeof(*gp),
- GFP_KERNEL);
- if (gp == NULL) {
- retval = -ENOMEM;
- goto free_region;
- }
-
- dev->priv = gp;
- }
-
gp = dev->priv;
memset(gp, 0, sizeof(*gp)); // clear it
@@ -854,8 +841,6 @@ gt96100_probe1(int port_num)
free_region:
release_region(gtif->iobase, GT96100_ETH_IO_SIZE);
unregister_netdev(dev);
- if (dev->priv != NULL)
- kfree (dev->priv);
kfree (dev);
err("%s failed. Returns %d\n", __FUNCTION__, retval);
return retval;
@@ -1601,8 +1586,6 @@ static void gt96100_cleanup_module(void)
(struct gt96100_private *)gtif->dev->priv;
release_region(gtif->iobase, gp->io_size);
unregister_netdev(gtif->dev);
- if (gtif->dev->priv != NULL)
- kfree (gtif->dev->priv);
kfree (gtif->dev);
}
}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/hamachi.c linux-2.5/drivers/net/hamachi.c
--- linux-2.5.60/drivers/net/hamachi.c 2003-02-10 17:39:14.000000000 -0100
+++ linux-2.5/drivers/net/hamachi.c 2003-02-07 17:13:31.000000000 -0100
@@ -207,8 +207,10 @@ KERN_INFO " Further modifications by K
/* Condensed bus+endian portability operations. */
#if ADDRLEN == 64
#define cpu_to_leXX(addr) cpu_to_le64(addr)
+#define desc_to_virt(addr) bus_to_virt(le64_to_cpu(addr))
#else
#define cpu_to_leXX(addr) cpu_to_le32(addr)
+#define desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
#endif
@@ -1493,7 +1495,7 @@ static int hamachi_rx(struct net_device
break;
pci_dma_sync_single(hmp->pci_dev, desc->addr, hmp->rx_buf_sz,
PCI_DMA_FROMDEVICE);
- buf_addr = (u8 *)hmp->rx_ring + entry*sizeof(*desc);
+ buf_addr = desc_to_virt(desc->addr);
frame_status = le32_to_cpu(get_unaligned((s32*)&(buf_addr[data_size - 12])));
if (hamachi_debug > 4)
printk(KERN_DEBUG " hamachi_rx() status was %8.8x.\n",
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/hamradio/mkiss.c linux-2.5/drivers/net/hamradio/mkiss.c
--- linux-2.5.60/drivers/net/hamradio/mkiss.c 2003-02-10 17:38:55.000000000 -0100
+++ linux-2.5/drivers/net/hamradio/mkiss.c 2003-01-17 00:58:23.000000000 -0100
@@ -347,6 +347,7 @@ static void ax_bump(struct ax_disp *ax)
netif_rx(skb);
tmp_ax->dev->last_rx = jiffies;
tmp_ax->rx_packets++;
+ tmp_ax->rx_bytes+=count;
}
/* Encapsulate one AX.25 packet and stuff into a TTY queue. */
@@ -386,6 +387,7 @@ static void ax_encaps(struct ax_disp *ax
ax->tty->flags |= (1 << TTY_DO_WRITE_WAKEUP);
actual = ax->tty->driver.write(ax->tty, 0, ax->xbuff, count);
ax->tx_packets++;
+ ax->tx_bytes+=actual;
ax->dev->trans_start = jiffies;
ax->xleft = count - actual;
ax->xhead = ax->xbuff + actual;
@@ -394,6 +396,7 @@ static void ax_encaps(struct ax_disp *ax
ax->mkiss->tty->flags |= (1 << TTY_DO_WRITE_WAKEUP);
actual = ax->mkiss->tty->driver.write(ax->mkiss->tty, 0, ax->mkiss->xbuff, count);
ax->tx_packets++;
+ ax->tx_bytes+=actual;
ax->mkiss->dev->trans_start = jiffies;
ax->mkiss->xleft = count - actual;
ax->mkiss->xhead = ax->mkiss->xbuff + actual;
@@ -709,6 +712,8 @@ static struct net_device_stats *ax_get_s
stats.rx_packets = ax->rx_packets;
stats.tx_packets = ax->tx_packets;
+ stats.rx_bytes = ax->rx_bytes;
+ stats.tx_bytes = ax->tx_bytes;
stats.rx_dropped = ax->rx_dropped;
stats.tx_dropped = ax->tx_dropped;
stats.tx_errors = ax->tx_errors;
@@ -936,7 +941,7 @@ static int ax25_init(struct net_device *
memcpy(dev->dev_addr, ax25_test, AX25_ADDR_LEN);
/* New-style flags. */
- dev->flags = 0;
+ dev->flags = IFF_BROADCAST | IFF_MULTICAST;
return 0;
}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/hamradio/mkiss.h linux-2.5/drivers/net/hamradio/mkiss.h
--- linux-2.5.60/drivers/net/hamradio/mkiss.h 2003-02-10 17:37:59.000000000 -0100
+++ linux-2.5/drivers/net/hamradio/mkiss.h 2003-01-17 00:58:23.000000000 -0100
@@ -31,6 +31,8 @@ struct ax_disp {
/* SLIP interface statistics. */
unsigned long rx_packets; /* inbound frames counter */
unsigned long tx_packets; /* outbound frames counter */
+ unsigned long rx_bytes; /* inbound bytes counter */
+ unsigned long tx_bytes; /* outbound bytes counter */
unsigned long rx_errors; /* Parity, etc. errors */
unsigned long tx_errors; /* Planned stuff */
unsigned long rx_dropped; /* No memory for skb */
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/myri_sbus.c linux-2.5/drivers/net/myri_sbus.c
--- linux-2.5.60/drivers/net/myri_sbus.c 2003-02-10 17:37:57.000000000 -0100
+++ linux-2.5/drivers/net/myri_sbus.c 2003-01-17 00:52:49.000000000 -0100
@@ -1063,9 +1063,6 @@ static int __init myri_ether_init(struct
goto err;
}
- DET(("ether_setup()\n"));
- ether_setup(dev);
-
dev->mtu = MYRINET_MTU;
dev->change_mtu = myri_change_mtu;
dev->hard_header = myri_header;
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/pcmcia/i82593.h linux-2.5/drivers/net/pcmcia/i82593.h
--- linux-2.5.60/drivers/net/pcmcia/i82593.h 1969-12-31 23:00:00.000000000 -0100
+++ linux-2.5/drivers/net/pcmcia/i82593.h 2003-01-17 00:58:23.000000000 -0100
@@ -0,0 +1,224 @@
+/*
+ * Definitions for Intel 82593 CSMA/CD Core LAN Controller
+ * The definitions are taken from the 1992 users manual with Intel
+ * order number 297125-001.
+ *
+ * /usr/src/pc/RCS/i82593.h,v 1.1 1996/07/17 15:23:12 root Exp
+ *
+ * Copyright 1994, Anders Klemets
+ *
+ * This software may be freely distributed for noncommercial purposes
+ * as long as this notice is retained.
+ *
+ * HISTORY
+ * i82593.h,v
+ * Revision 1.1 1996/07/17 15:23:12 root
+ * Initial revision
+ *
+ * Revision 1.3 1995/04/05 15:13:58 adj
+ * Initial alpha release
+ *
+ * Revision 1.2 1994/06/16 23:57:31 klemets
+ * Mirrored all the fields in the configuration block.
+ *
+ * Revision 1.1 1994/06/02 20:25:34 klemets
+ * Initial revision
+ *
+ *
+ */
+#ifndef _I82593_H
+#define _I82593_H
+
+/* Intel 82593 CSMA/CD Core LAN Controller */
+
+/* Port 0 Command Register definitions */
+
+/* Execution operations */
+#define OP0_NOP 0 /* CHNL = 0 */
+#define OP0_SWIT_TO_PORT_1 0 /* CHNL = 1 */
+#define OP0_IA_SETUP 1
+#define OP0_CONFIGURE 2
+#define OP0_MC_SETUP 3
+#define OP0_TRANSMIT 4
+#define OP0_TDR 5
+#define OP0_DUMP 6
+#define OP0_DIAGNOSE 7
+#define OP0_TRANSMIT_NO_CRC 9
+#define OP0_RETRANSMIT 12
+#define OP0_ABORT 13
+/* Reception operations */
+#define OP0_RCV_ENABLE 8
+#define OP0_RCV_DISABLE 10
+#define OP0_STOP_RCV 11
+/* Status pointer control operations */
+#define OP0_FIX_PTR 15 /* CHNL = 1 */
+#define OP0_RLS_PTR 15 /* CHNL = 0 */
+#define OP0_RESET 14
+
+#define CR0_CHNL (1 << 4) /* 0=Channel 0, 1=Channel 1 */
+#define CR0_STATUS_0 0x00
+#define CR0_STATUS_1 0x20
+#define CR0_STATUS_2 0x40
+#define CR0_STATUS_3 0x60
+#define CR0_INT_ACK (1 << 7) /* 0=No ack, 1=acknowledge */
+
+/* Port 0 Status Register definitions */
+
+#define SR0_NO_RESULT 0 /* dummy */
+#define SR0_EVENT_MASK 0x0f
+#define SR0_IA_SETUP_DONE 1
+#define SR0_CONFIGURE_DONE 2
+#define SR0_MC_SETUP_DONE 3
+#define SR0_TRANSMIT_DONE 4
+#define SR0_TDR_DONE 5
+#define SR0_DUMP_DONE 6
+#define SR0_DIAGNOSE_PASSED 7
+#define SR0_TRANSMIT_NO_CRC_DONE 9
+#define SR0_RETRANSMIT_DONE 12
+#define SR0_EXECUTION_ABORTED 13
+#define SR0_END_OF_FRAME 8
+#define SR0_RECEPTION_ABORTED 10
+#define SR0_DIAGNOSE_FAILED 15
+#define SR0_STOP_REG_HIT 11
+
+#define SR0_CHNL (1 << 4)
+#define SR0_EXECUTION (1 << 5)
+#define SR0_RECEPTION (1 << 6)
+#define SR0_INTERRUPT (1 << 7)
+#define SR0_BOTH_RX_TX (SR0_EXECUTION | SR0_RECEPTION)
+
+#define SR3_EXEC_STATE_MASK 0x03
+#define SR3_EXEC_IDLE 0
+#define SR3_TX_ABORT_IN_PROGRESS 1
+#define SR3_EXEC_ACTIVE 2
+#define SR3_ABORT_IN_PROGRESS 3
+#define SR3_EXEC_CHNL (1 << 2)
+#define SR3_STP_ON_NO_RSRC (1 << 3)
+#define SR3_RCVING_NO_RSRC (1 << 4)
+#define SR3_RCV_STATE_MASK 0x60
+#define SR3_RCV_IDLE 0x00
+#define SR3_RCV_READY 0x20
+#define SR3_RCV_ACTIVE 0x40
+#define SR3_RCV_STOP_IN_PROG 0x60
+#define SR3_RCV_CHNL (1 << 7)
+
+/* Port 1 Command Register definitions */
+
+#define OP1_NOP 0
+#define OP1_SWIT_TO_PORT_0 1
+#define OP1_INT_DISABLE 2
+#define OP1_INT_ENABLE 3
+#define OP1_SET_TS 5
+#define OP1_RST_TS 7
+#define OP1_POWER_DOWN 8
+#define OP1_RESET_RING_MNGMT 11
+#define OP1_RESET 14
+#define OP1_SEL_RST 15
+
+#define CR1_STATUS_4 0x00
+#define CR1_STATUS_5 0x20
+#define CR1_STATUS_6 0x40
+#define CR1_STOP_REG_UPDATE (1 << 7)
+
+/* Receive frame status bits */
+
+#define RX_RCLD (1 << 0)
+#define RX_IA_MATCH (1 << 1)
+#define RX_NO_AD_MATCH (1 << 2)
+#define RX_NO_SFD (1 << 3)
+#define RX_SRT_FRM (1 << 7)
+#define RX_OVRRUN (1 << 8)
+#define RX_ALG_ERR (1 << 10)
+#define RX_CRC_ERR (1 << 11)
+#define RX_LEN_ERR (1 << 12)
+#define RX_RCV_OK (1 << 13)
+#define RX_TYP_LEN (1 << 15)
+
+/* Transmit status bits */
+
+#define TX_NCOL_MASK 0x0f
+#define TX_FRTL (1 << 4)
+#define TX_MAX_COL (1 << 5)
+#define TX_HRT_BEAT (1 << 6)
+#define TX_DEFER (1 << 7)
+#define TX_UND_RUN (1 << 8)
+#define TX_LOST_CTS (1 << 9)
+#define TX_LOST_CRS (1 << 10)
+#define TX_LTCOL (1 << 11)
+#define TX_OK (1 << 13)
+#define TX_COLL (1 << 15)
+
+struct i82593_conf_block {
+ u_char fifo_limit : 4,
+ forgnesi : 1,
+ fifo_32 : 1,
+ d6mod : 1,
+ throttle_enb : 1;
+ u_char throttle : 6,
+ cntrxint : 1,
+ contin : 1;
+ u_char addr_len : 3,
+ acloc : 1,
+ preamb_len : 2,
+ loopback : 2;
+ u_char lin_prio : 3,
+ tbofstop : 1,
+ exp_prio : 3,
+ bof_met : 1;
+ u_char : 4,
+ ifrm_spc : 4;
+ u_char : 5,
+ slottim_low : 3;
+ u_char slottim_hi : 3,
+ : 1,
+ max_retr : 4;
+ u_char prmisc : 1,
+ bc_dis : 1,
+ : 1,
+ crs_1 : 1,
+ nocrc_ins : 1,
+ crc_1632 : 1,
+ : 1,
+ crs_cdt : 1;
+ u_char cs_filter : 3,
+ crs_src : 1,
+ cd_filter : 3,
+ : 1;
+ u_char : 2,
+ min_fr_len : 6;
+ u_char lng_typ : 1,
+ lng_fld : 1,
+ rxcrc_xf : 1,
+ artx : 1,
+ sarec : 1,
+ tx_jabber : 1, /* why is this called max_len in the manual? */
+ hash_1 : 1,
+ lbpkpol : 1;
+ u_char : 6,
+ fdx : 1,
+ : 1;
+ u_char dummy_6 : 6, /* supposed to be ones */
+ mult_ia : 1,
+ dis_bof : 1;
+ u_char dummy_1 : 1, /* supposed to be one */
+ tx_ifs_retrig : 2,
+ mc_all : 1,
+ rcv_mon : 2,
+ frag_acpt : 1,
+ tstrttrs : 1;
+ u_char fretx : 1,
+ runt_eop : 1,
+ hw_sw_pin : 1,
+ big_endn : 1,
+ syncrqs : 1,
+ sttlen : 1,
+ tx_eop : 1,
+ rx_eop : 1;
+ u_char rbuf_size : 5,
+ rcvstop : 1,
+ : 2;
+};
+
+#define I82593_MAX_MULTICAST_ADDRESSES 128 /* Hardware hashed filter */
+
+#endif /* _I82593_H */
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/rclanmtl.h linux-2.5/drivers/net/rclanmtl.h
--- linux-2.5.60/drivers/net/rclanmtl.h 2003-02-10 17:38:38.000000000 -0100
+++ linux-2.5/drivers/net/rclanmtl.h 2003-01-17 00:58:22.000000000 -0100
@@ -54,10 +54,10 @@
#include
/* Debug stuff. Define for debug output */
-#define RCDEBUG
+#undef RCDEBUG
#ifdef RCDEBUG
-#define dprintk(args...) printk(KERN_DEBUG "(rcpci45 driver:) " args)
+#define dprintk(args...) printk("rc: " args)
#else
#define dprintk(args...) { }
#endif
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/sb1000.c linux-2.5/drivers/net/sb1000.c
--- linux-2.5.60/drivers/net/sb1000.c 2003-02-10 17:37:57.000000000 -0100
+++ linux-2.5/drivers/net/sb1000.c 2003-01-13 14:01:26.000000000 -0100
@@ -218,7 +218,7 @@ sb1000_probe(struct net_device *dev)
"S/N %#8.8x, IRQ %d.\n", dev->name, dev->base_addr,
dev->mem_start, serial_number, dev->irq);
- dev = init_etherdev(dev, 0);
+ dev = init_etherdev(dev, sizeof(struct sb1000_private));
if (!dev) {
pnp_device_detach(idev);
release_region(ioaddr[1], 16);
@@ -227,12 +227,6 @@ sb1000_probe(struct net_device *dev)
}
SET_MODULE_OWNER(dev);
- /* Make up a SB1000-specific-data structure. */
- dev->priv = kmalloc(sizeof(struct sb1000_private), GFP_KERNEL);
- if (dev->priv == NULL)
- return -ENOMEM;
- memset(dev->priv, 0, sizeof(struct sb1000_private));
-
if (sb1000_debug > 0)
printk(KERN_NOTICE "%s", version);
@@ -1251,8 +1245,7 @@ void cleanup_module(void)
unregister_netdev(&dev_sb1000);
release_region(dev_sb1000.base_addr, 16);
release_region(dev_sb1000.mem_start, 16);
- kfree(dev_sb1000.priv);
- dev_sb1000.priv = NULL;
+ kfree(dev_sb1000);
}
#endif /* MODULE */
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/sb1250-mac.c linux-2.5/drivers/net/sb1250-mac.c
--- linux-2.5.60/drivers/net/sb1250-mac.c 2003-02-10 17:38:53.000000000 -0100
+++ linux-2.5/drivers/net/sb1250-mac.c 2003-01-17 00:58:22.000000000 -0100
@@ -24,6 +24,9 @@
*/
+
+#define CONFIG_SBMAC_COALESCE
+
/* A few user-configurable values.
These may be modified when a driver module is loaded. */
@@ -41,6 +44,8 @@ static int options[MAX_UNITS] = {-1, -1,
static int full_duplex[MAX_UNITS] = {-1, -1, -1};
#endif
+static int int_pktcnt = 0;
+static int int_timeout = 0;
/* Operational parameters that usually are not changed. */
@@ -59,11 +64,11 @@ static int full_duplex[MAX_UNITS] = {-1,
#include
#include
#include
+#include
#include
#include
#include
#include
-#include
#include
#include
#include /* Processor type for cache alignment. */
@@ -74,7 +79,7 @@ static int full_duplex[MAX_UNITS] = {-1,
/* This is only here until the firmware is ready. In that case,
the firmware leaves the ethernet address in the register for us. */
-#ifdef CONFIG_SWARM_STANDALONE
+#ifdef CONFIG_SIBYTE_STANDALONE
#define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
#define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
#define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
@@ -95,12 +100,15 @@ MODULE_PARM(debug, "i");
MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
+MODULE_PARM(int_pktcnt, "i");
+MODULE_PARM(int_timeout, "i");
#include
#include
#include
#include
#include
+#include /* Only to check SOC part number. */
/**********************************************************************
@@ -151,7 +159,8 @@ typedef enum { sbmac_state_uninit, sbmac
#define ETHER_ALIGN 2
#define ETHER_ADDR_LEN 6
-#define ENET_PACKET_SIZE 1518
+#define ENET_PACKET_SIZE 1518
+/*#define ENET_PACKET_SIZE 9216 */
/**********************************************************************
* DMA Descriptor structure
@@ -178,8 +187,13 @@ typedef struct sbmacdma_s {
struct sbmac_softc *sbdma_eth; /* back pointer to associated MAC */
int sbdma_channel; /* channel number */
- int sbdma_txdir; /* direction (1=transmit) */
- int sbdma_maxdescr; /* total # of descriptors in ring */
+ int sbdma_txdir; /* direction (1=transmit) */
+ int sbdma_maxdescr; /* total # of descriptors in ring */
+#ifdef CONFIG_SBMAC_COALESCE
+ int sbdma_int_pktcnt; /* # descriptors rx before interrupt*/
+ int sbdma_int_timeout; /* # usec rx interrupt */
+#endif
+
sbmac_port_t sbdma_config0; /* DMA config register 0 */
sbmac_port_t sbdma_config1; /* DMA config register 1 */
sbmac_port_t sbdma_dscrbase; /* Descriptor base address */
@@ -250,6 +264,8 @@ struct sbmac_softc {
sbmacdma_t sbm_txdma; /* for now, only use channel 0 */
sbmacdma_t sbm_rxdma;
+ int rx_hw_checksum;
+ int sbe_idx;
};
@@ -267,7 +283,7 @@ static void sbdma_initctx(sbmacdma_t *d,
int chan,
int txrx,
int maxdescr);
-static void sbdma_channel_start(sbmacdma_t *d);
+static void sbdma_channel_start(sbmacdma_t *d, int rxtx);
static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *m);
static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *m);
static void sbdma_emptyring(sbmacdma_t *d);
@@ -308,6 +324,9 @@ static void sbmac_mii_write(struct sbmac
* Globals
********************************************************************* */
+static uint64_t sbmac_orig_hwaddr[MAX_UNITS];
+static uint64_t chip_revision;
+
/**********************************************************************
* MDIO constants
@@ -328,7 +347,7 @@ static void sbmac_mii_write(struct sbmac
#define BMCR_DUPLEX 0x0100
#define BMCR_COLTEST 0x0080
#define BMCR_SPEED1 0x0040
-#define BMCR_SPEED1000 (BMCR_SPEED1|BMCR_SPEED0)
+#define BMCR_SPEED1000 (BMCR_SPEED1)
#define BMCR_SPEED100 (BMCR_SPEED0)
#define BMCR_SPEED10 0
@@ -437,6 +456,8 @@ static void sbmac_mii_write(struct sbmac
#define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */
+#define ENABLE 1
+#define DISABLE 0
/**********************************************************************
* SBMAC_MII_SYNC(s)
@@ -651,6 +672,52 @@ static void sbdma_initctx(sbmacdma_t *d,
d->sbdma_channel = chan;
d->sbdma_txdir = txrx;
+ /* RMON clearing */
+ s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
+
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)), 0);
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)), 0);
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)), 0);
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)), 0);
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)), 0);
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)), 0);
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)), 0);
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)), 0);
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)), 0);
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)), 0);
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)), 0);
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)), 0);
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)), 0);
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)), 0);
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)), 0);
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)), 0);
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)), 0);
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)), 0);
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)), 0);
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)), 0);
+ SBMAC_WRITECSR(PKSEG1(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)), 0);
+
/*
* initialize register pointers
*/
@@ -658,7 +725,7 @@ static void sbdma_initctx(sbmacdma_t *d,
d->sbdma_config0 =
PKSEG1(s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0));
d->sbdma_config1 =
- PKSEG1(s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0));
+ PKSEG1(s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1));
d->sbdma_dscrbase =
PKSEG1(s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE));
d->sbdma_dscrcnt =
@@ -690,6 +757,32 @@ static void sbdma_initctx(sbmacdma_t *d,
memset(d->sbdma_ctxtable,0,d->sbdma_maxdescr*sizeof(struct sk_buff *));
+#ifdef CONFIG_SBMAC_COALESCE
+ /*
+ * Setup Rx DMA coalescing defaults
+ */
+
+ if ( txrx == DMA_RX ) {
+ if ( int_pktcnt ) {
+ d->sbdma_int_pktcnt = int_pktcnt;
+ }
+ else {
+ d->sbdma_int_pktcnt = 1;
+ }
+
+ if ( int_timeout ) {
+ d->sbdma_int_timeout = int_timeout;
+ }
+ else {
+ d->sbdma_int_timeout = 0;
+ }
+ }
+ else {
+ d->sbdma_int_pktcnt = 0;
+ d->sbdma_int_timeout = 0;
+ }
+#endif
+
}
/**********************************************************************
@@ -699,34 +792,85 @@ static void sbdma_initctx(sbmacdma_t *d,
*
* Input parameters:
* d - DMA channel to init (context must be previously init'd
+ * rxtx - DMA_RX or DMA_TX depending on what type of channel
*
* Return value:
* nothing
********************************************************************* */
-static void sbdma_channel_start(sbmacdma_t *d)
+static void sbdma_channel_start(sbmacdma_t *d, int rxtx )
+{
+ /*
+ * Turn on the DMA channel
+ */
+
+#ifdef CONFIG_SBMAC_COALESCE
+ if (rxtx == DMA_RX) {
+ SBMAC_WRITECSR(d->sbdma_config1,
+ V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
+ 0);
+ SBMAC_WRITECSR(d->sbdma_config0,
+ M_DMA_EOP_INT_EN |
+ V_DMA_RINGSZ(d->sbdma_maxdescr) |
+ V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
+ 0);
+ }
+ else {
+ SBMAC_WRITECSR(d->sbdma_config1,0);
+ SBMAC_WRITECSR(d->sbdma_config0,
+ V_DMA_RINGSZ(d->sbdma_maxdescr) |
+ 0);
+ }
+#else
+ SBMAC_WRITECSR(d->sbdma_config1,0);
+ SBMAC_WRITECSR(d->sbdma_config0,
+ V_DMA_RINGSZ(d->sbdma_maxdescr) |
+ 0);
+#endif
+
+
+ SBMAC_WRITECSR(d->sbdma_dscrbase,d->sbdma_dscrtable_phys);
+
+ /*
+ * Initialize ring pointers
+ */
+
+ d->sbdma_addptr = d->sbdma_dscrtable;
+ d->sbdma_remptr = d->sbdma_dscrtable;
+}
+
+/**********************************************************************
+ * SBDMA_CHANNEL_STOP(d)
+ *
+ * Initialize the hardware registers for a DMA channel.
+ *
+ * Input parameters:
+ * d - DMA channel to init (context must be previously init'd
+ *
+ * Return value:
+ * nothing
+ ********************************************************************* */
+
+static void sbdma_channel_stop(sbmacdma_t *d)
{
/*
- * Turn on the DMA channel
+ * Turn off the DMA channel
*/
SBMAC_WRITECSR(d->sbdma_config1,0);
- SBMAC_WRITECSR(d->sbdma_dscrbase,d->sbdma_dscrtable_phys);
+ SBMAC_WRITECSR(d->sbdma_dscrbase,0);
- SBMAC_WRITECSR(d->sbdma_config0,
- V_DMA_RINGSZ(d->sbdma_maxdescr) |
- 0);
+ SBMAC_WRITECSR(d->sbdma_config0,0);
/*
- * Initialize ring pointers
+ * Zero ring pointers
*/
- d->sbdma_addptr = d->sbdma_dscrtable;
- d->sbdma_remptr = d->sbdma_dscrtable;
+ d->sbdma_addptr = 0;
+ d->sbdma_remptr = 0;
}
-
static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset)
{
unsigned long addr;
@@ -788,7 +932,7 @@ static int sbdma_add_rcvbuffer(sbmacdma_
*
* 1. the data does not start in the middle of a cache line.
* 2. The data does not end in the middle of a cache line
- * 3. The buffer can be aligned such that the IP addresses are
+ * 3. The buffer can be aligned such that the IP addresses are
* naturally aligned.
*
* Remember, the SB1250's MAC writes whole cache lines at a time,
@@ -822,9 +966,18 @@ static int sbdma_add_rcvbuffer(sbmacdma_
* fill in the descriptor
*/
+#ifdef CONFIG_SBMAC_COALESCE
+ /*
+ * Do not interrupt per DMA transfer.
+ */
+ dsc->dscr_a = KVTOPHYS(sb_new->tail) |
+ V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
+ 0;
+#else
dsc->dscr_a = KVTOPHYS(sb_new->tail) |
V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
M_DMA_DSCRA_INTERRUPT;
+#endif
/* receiving: no options */
dsc->dscr_b = 0;
@@ -1079,6 +1232,20 @@ static void sbdma_rx_process(struct sbma
sc->sbm_stats.rx_bytes += len;
sc->sbm_stats.rx_packets++;
sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
+ if (sc->rx_hw_checksum == ENABLE) {
+ /* if the ip checksum is good indicate in skb.
+ else set CHECKSUM_NONE as device failed to
+ checksum the packet */
+
+ if (((dsc->dscr_b) |M_DMA_ETHRX_BADTCPCS) ||
+ ((dsc->dscr_a)| M_DMA_ETHRX_BADIP4CS)){
+ sb->ip_summed = CHECKSUM_NONE;
+ } else {
+ printk(KERN_DEBUG "hw checksum fail .\n");
+ sb->ip_summed = CHECKSUM_UNNECESSARY;
+ }
+ } /*rx_hw_checksum */
+
netif_rx(sb);
}
}
@@ -1351,8 +1518,14 @@ static void sbmac_channel_start(struct s
M_MAC_SS_EN |
0;
+ /*
+ * Be sure that RD_THRSH+WR_THRSH <= 32
+ * Use a larger RD_THRSH for gigabit
+ */
+
fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */
- V_MAC_TX_RD_THRSH(4) |
+ ((s->sbm_speed == sbmac_speed_1000)
+ ? V_MAC_TX_RD_THRSH(28) : V_MAC_TX_RD_THRSH(4)) |
V_MAC_TX_RL_THRSH(4) |
V_MAC_RX_PL_THRSH(4) |
V_MAC_RX_RD_THRSH(4) | /* Must be '4' */
@@ -1439,8 +1612,8 @@ static void sbmac_channel_start(struct s
* Initialize DMA channels (rings should be ok now)
*/
- sbdma_channel_start(&(s->sbm_rxdma));
- sbdma_channel_start(&(s->sbm_txdma));
+ sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
+ sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
/*
* Configure the speed, duplex, and flow control
@@ -1467,12 +1640,22 @@ static void sbmac_channel_start(struct s
+
+#ifdef CONFIG_SBMAC_COALESCE
+ /*
+ * Accept any TX interrupt and EOP count/timer RX interrupts on ch 0
+ */
+ SBMAC_WRITECSR(s->sbm_imr,
+ (M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
+ ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0));
+#else
/*
* Accept any kind of interrupt on TX and RX DMA channel 0
*/
SBMAC_WRITECSR(s->sbm_imr,
(M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
(M_MAC_INT_CHANNEL << S_MAC_RX_CH0));
+#endif
/*
* Enable receiving unicasts and broadcasts
@@ -1517,8 +1700,6 @@ static void sbmac_channel_start(struct s
static void sbmac_channel_stop(struct sbmac_softc *s)
{
- uint64_t ctl;
-
/* don't do this if already stopped */
if (s->sbm_state == sbmac_state_off) return;
@@ -1534,14 +1715,18 @@ static void sbmac_channel_stop(struct sb
/* turn off receiver and transmitter */
- ctl = SBMAC_READCSR(s->sbm_macenable);
- ctl &= ~(M_MAC_RXDMA_EN0 | M_MAC_TXDMA_EN0);
- SBMAC_WRITECSR(s->sbm_macenable,ctl);
+ SBMAC_WRITECSR(s->sbm_macenable,0);
/* We're stopped now. */
s->sbm_state = sbmac_state_off;
+ /*
+ * Stop DMA channels (rings should be ok now)
+ */
+
+ sbdma_channel_stop(&(s->sbm_rxdma));
+ sbdma_channel_stop(&(s->sbm_txdma));
/* Empty the receive and transmit rings */
@@ -1624,6 +1809,36 @@ static void sbmac_promiscuous_mode(struc
}
}
+/**********************************************************************
+ * SBMAC_SETIPHDR_OFFSET(sc,onoff)
+ *
+ * Set the iphdr offset as 15 assuming ethernet encapsulation
+ *
+ * Input parameters:
+ * sc - softc
+ *
+ * Return value:
+ * nothing
+ ********************************************************************* */
+
+static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
+{
+ uint64_t reg;
+
+ reg = SBMAC_READCSR(sc->sbm_rxfilter);
+ reg &= ~M_MAC_IPHDR_OFFSET;
+ /* Hard code the off set to 15 for now */
+ reg |= 15 << S_MAC_IPHDR_OFFSET;
+ SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
+
+ /* read system identification to determine revision */
+ if (sb1250_pass >= K_SYS_REVISION_PASS2) {
+ printk(KERN_INFO "pass2 - enabling Rx rcv tcp checksum\n");
+ sc->rx_hw_checksum = ENABLE;
+ } else {
+ sc->rx_hw_checksum = DISABLE;
+ }
+}
#if 0
@@ -1895,10 +2110,11 @@ static void sbmac_intr(int irq,void *dev
for (;;) {
/*
- * Read the ISR (this clears the bits in the real register)
+ * Read the ISR (this clears the bits in the real
+ * register, except for counter addr)
*/
- isr = SBMAC_READCSR(sc->sbm_isr);
+ isr = SBMAC_READCSR(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
if (isr == 0) break;
@@ -1913,6 +2129,23 @@ static void sbmac_intr(int irq,void *dev
/*
* Receives on channel 0
*/
+
+ /*
+ * It's important to test all the bits (or at least the
+ * EOP_SEEN bit) when deciding to do the RX process
+ * particularly when coalescing, to make sure we
+ * take care of the following:
+ *
+ * If you have some packets waiting (have been received
+ * but no interrupt) and get a TX interrupt before
+ * the RX timer or counter expires, reading the ISR
+ * above will clear the timer and counter, and you
+ * won't get another interrupt until a packet shows
+ * up to start the timer again. Testing
+ * EOP_SEEN here takes care of this case.
+ * (EOP_SEEN is part of M_MAC_INT_CHANNEL << S_MAC_RX_CH0)
+ */
+
if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
sbdma_rx_process(sc,&(sc->sbm_rxdma));
@@ -1950,6 +2183,9 @@ static int sbmac_start_tx(struct sk_buff
if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
/* XXX save skb that we could not send */
netif_stop_queue(dev);
+ spin_unlock_irq(&sc->sbm_lock);
+
+ return 1;
}
dev->trans_start = jiffies;
@@ -2121,6 +2357,15 @@ static int sbmac_parse_hwaddr(char *str,
}
#endif
+static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
+{
+ if (new_mtu > ENET_PACKET_SIZE)
+ return -EINVAL;
+ _dev->mtu = new_mtu;
+ printk(KERN_INFO "changing the mtu to %d\n", new_mtu);
+ return 0;
+}
+
/**********************************************************************
* SBMAC_INIT(dev)
*
@@ -2206,6 +2451,16 @@ static int sbmac_init(struct net_device
dev->do_ioctl = sbmac_mii_ioctl;
dev->tx_timeout = sbmac_tx_timeout;
dev->watchdog_timeo = TX_TIMEOUT;
+
+ dev->change_mtu = sb1250_change_mtu;
+
+ if (sb1250_pass >= K_SYS_REVISION_PASS3) {
+ /* In pass3 we do dumb checksum in TX */
+ dev->features |= NETIF_F_IP_CSUM;
+ }
+
+ /* This is needed for PASS2 for Rx H/W checksum feature */
+ sbmac_set_iphdr_offset( sc);
return 0;
@@ -2361,6 +2616,9 @@ static int sbmac_mii_poll(struct sbmac_s
p += sprintf(p,"Unknown");
}
+#ifdef CONFIG_NET_SB1250_MAC_QUIET
+ noisy = 0;
+#endif
if (noisy) {
printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer);
}
@@ -2528,36 +2786,33 @@ static int sbmac_close(struct net_device
{
struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
unsigned long flags;
-
+
sbmac_set_channel_state(sc,sbmac_state_off);
-
+
del_timer_sync(&sc->sbm_timer);
-
+
spin_lock_irqsave(&sc->sbm_lock, flags);
-
+
netif_stop_queue(dev);
-
- if (debug > 1) {
+
+ if (debug > 1)
printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name);
- }
-
+
spin_unlock_irqrestore(&sc->sbm_lock, flags);
-
+
/* Make sure there is no irq-handler running on a different CPU. */
synchronize_irq(dev->irq);
-
+
free_irq(dev->irq, dev);
-
+
sbdma_emptyring(&(sc->sbm_txdma));
sbdma_emptyring(&(sc->sbm_rxdma));
-
+
MOD_DEC_USE_COUNT;
-
+
return 0;
}
-
-
#if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR)
static void
sbmac_setup_hwaddr(int chan,char *addr)
@@ -2583,6 +2838,7 @@ sbmac_init_module(void)
int macidx = 0;
struct net_device *dev;
sbmac_port_t port;
+ int chip_max_units;
/*
* For bringup when not using the firmware, we can pre-fill
@@ -2603,8 +2859,25 @@ sbmac_init_module(void)
* Walk through the Ethernet controllers and find
* those who have their MAC addresses set.
*/
-
- for (idx = 0; idx < MAX_UNITS; idx++) {
+ chip_revision = SBMAC_READCSR(PKSEG1(A_SCD_SYSTEM_REVISION));
+ switch ((int)G_SYS_PART(chip_revision)) {
+ case 0x1150:
+ case 0x1250:
+ chip_max_units = 3;
+ break;
+ case 0x1120:
+ case 0x1125:
+ case 0x1126:
+ chip_max_units = 2;
+ break;
+ default:
+ chip_max_units = 0;
+ break;
+ }
+ if (chip_max_units > MAX_UNITS)
+ chip_max_units = MAX_UNITS;
+
+ for (idx = 0; idx < chip_max_units; idx++) {
/*
* This is the base address of the MAC.
@@ -2618,16 +2891,20 @@ sbmac_init_module(void)
* If we find a zero, skip this MAC.
*/
- if (SBMAC_READCSR(PKSEG1(port+R_MAC_ETHERNET_ADDR)) == 0) {
+ sbmac_orig_hwaddr[idx] = SBMAC_READCSR(PKSEG1(port+R_MAC_ETHERNET_ADDR));
+ if (sbmac_orig_hwaddr[idx] == 0) {
+ printk( KERN_DEBUG "sbmac: not configuring MAC at %x\n",(uint32_t)port);
continue;
- }
+ }
/*
* Okay, cool. Initialize this MAC.
*/
dev = init_etherdev(NULL,sizeof(struct sbmac_softc));
- if (!dev) break; /* problems, get out now. */
+ if (!dev)
+ return -ENOMEM; /* return ENOMEM */
+
dev->irq = K_INT_MAC_0 + idx;
dev->base_addr = port;
dev->mem_end = 0;
@@ -2652,6 +2929,7 @@ sbmac_cleanup_module(void)
{
int idx;
struct net_device *dev;
+ sbmac_port_t port;
for (idx = 0; idx < MAX_UNITS; idx++) {
dev = dev_sbmac[idx];
if (dev == NULL) continue;
@@ -2662,8 +2940,10 @@ sbmac_cleanup_module(void)
sbmac_uninitctx(sc);
- KFREE(sc);
}
+
+ port = A_MAC_CHANNEL_BASE(idx);
+ SBMAC_WRITECSR(PKSEG1(port+R_MAC_ETHERNET_ADDR), sbmac_orig_hwaddr[idx] );
KFREE(dev);
dev_sbmac[idx] = NULL;
}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/sk98lin/skge.c linux-2.5/drivers/net/sk98lin/skge.c
--- linux-2.5.60/drivers/net/sk98lin/skge.c 2003-02-10 17:38:00.000000000 -0100
+++ linux-2.5/drivers/net/sk98lin/skge.c 2003-01-17 00:58:23.000000000 -0100
@@ -442,7 +442,7 @@ static int __init skge_probe (void)
pci_set_dma_mask(pdev, (u64) 0xffffffff))
continue;
- if ((dev = init_etherdev(dev, sizeof(DEV_NET))) == 0) {
+ if ((dev = init_etherdev(dev, sizeof(DEV_NET))) == NULL) {
printk(KERN_ERR "Unable to allocate etherdev "
"structure!\n");
break;
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/sunbmac.c linux-2.5/drivers/net/sunbmac.c
--- linux-2.5.60/drivers/net/sunbmac.c 2003-02-10 17:38:42.000000000 -0100
+++ linux-2.5/drivers/net/sunbmac.c 2003-01-17 00:58:22.000000000 -0100
@@ -1033,8 +1033,9 @@ static void bigmac_set_multicast(struct
sbus_writel(tmp, bregs + BMAC_RXCFG);
}
-static int __init bigmac_ether_init(struct net_device *dev, struct sbus_dev *qec_sdev)
+static int __init bigmac_ether_init(struct sbus_dev *qec_sdev)
{
+ struct net_device *dev;
static int version_printed;
struct bigmac *bp;
u8 bsizes, bsizes_more;
@@ -1049,9 +1050,6 @@ static int __init bigmac_ether_init(stru
if (version_printed++ == 0)
printk(KERN_INFO "%s", version);
- if (!dev)
- return -ENOMEM;
-
/* Report what we have found to the user. */
printk(KERN_INFO "%s: BigMAC 100baseT Ethernet ", dev->name);
dev->base_addr = (long) qec_sdev;
@@ -1180,7 +1178,6 @@ static int __init bigmac_ether_init(stru
/* Finish net device registration. */
dev->irq = bp->bigmac_sdev->irqs[0];
dev->dma = 0;
- ether_setup(dev);
/* Put us into the list of instances attached for later driver
* exit.
@@ -1235,7 +1232,6 @@ static int __init bigmac_match(struct sb
static int __init bigmac_probe(void)
{
- struct net_device *dev = NULL;
struct sbus_bus *sbus;
struct sbus_dev *sdev = 0;
static int called;
@@ -1249,12 +1245,9 @@ static int __init bigmac_probe(void)
for_each_sbus(sbus) {
for_each_sbusdev(sdev, sbus) {
- if (cards)
- dev = NULL;
-
if (bigmac_match(sdev)) {
cards++;
- if ((v = bigmac_ether_init(dev, sdev)))
+ if ((v = bigmac_ether_init(sdev)))
return v;
}
}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/sunqe.c linux-2.5/drivers/net/sunqe.c
--- linux-2.5.60/drivers/net/sunqe.c 2003-02-10 17:38:20.000000000 -0100
+++ linux-2.5/drivers/net/sunqe.c 2003-01-17 00:58:22.000000000 -0100
@@ -924,7 +924,6 @@ qec_free_devs:
sizeof(struct sunqe_buffers),
qe->buffers,
qe->buffers_dvma);
- kfree(qe_devs[i]->priv);
}
kfree(qe_devs[i]);
}
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/tulip/ChangeLog linux-2.5/drivers/net/tulip/ChangeLog
--- linux-2.5.60/drivers/net/tulip/ChangeLog 2003-02-10 17:38:01.000000000 -0100
+++ linux-2.5/drivers/net/tulip/ChangeLog 2003-01-17 00:58:24.000000000 -0100
@@ -26,17 +26,22 @@
PCI transaction.
Fix bugs in tulip MWI config also.
+2002-02-07 Uwe Bonnes
+
+ * tulip_core (tulip_pci_tbl[]):
+ Add PCI id for comet tulip clone.
+
2002-01-28 Stefan Rompf ,
Jeff Garzik
- * 21142.c (t21142_timer): Use return value of
- tulip_check_duplex() to indicate to system whether or not
- carrier is present. Use carrier presence/absence to determine
- when next the 21142 media timer should check for link beat.
-
- * timer (tulip_timer): Un-comment-out calls to
- netif_carrier_{on,off}, as there is now value in
- reporting link beta information to userspace.
+ * 21142.c (t21142_timer): Use return value of
+ tulip_check_duplex() to indicate to system whether or not
+ carrier is present. Use carrier presence/absence to determine
+ when next the 21142 media timer should check for link beat.
+
+ * timer (tulip_timer): Un-comment-out calls to
+ netif_carrier_{on,off}, as there is now value in
+ reporting link beta information to userspace.
2002-01-28 Pavel Roskin
@@ -48,10 +53,19 @@
* tulip.h: Likewise. Increase EEPROM_SIZE to 512 bytes to
accomodate EEPROM on Conexant RS7112.
-2002-02-07 Uwe Bonnes
+2001-12-19 John Zielinski
+
+ * tulip_core.c (tulip_up, tulip_init_one):
+ More places to revert PHY autoconfiguration bit removal.
+
+2001-12-18 Jeff Garzik
+
+ * tulip.h: revert PHY autoconfiguration bit removal
+
+2001-12-16 Andrew Lambeth
- * tulip_core (tulip_pci_tbl[]):
- Add PCI id for comet tulip clone.
+ * tulip_core.c (tulip_start_xmit): Use the more-portable
+ spin_lock_irqsave.
2001-12-11 Jeff Garzik
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/tulip/de4x5.c linux-2.5/drivers/net/tulip/de4x5.c
--- linux-2.5.60/drivers/net/tulip/de4x5.c 2003-02-10 17:37:57.000000000 -0100
+++ linux-2.5/drivers/net/tulip/de4x5.c 2003-02-11 03:10:50.000000000 -0100
@@ -440,8 +440,6 @@
=========================================================================
*/
-static char version[] __initdata = "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
-
#include
#include
#include
@@ -477,6 +475,8 @@ static char version[] __initdata = "de4x
#include "de4x5.h"
+static char version[] __initdata = "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
+
#define c_char const char
#define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((u_short *)(a)))
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/tulip/tulip.h linux-2.5/drivers/net/tulip/tulip.h
--- linux-2.5.60/drivers/net/tulip/tulip.h 2003-02-10 17:38:53.000000000 -0100
+++ linux-2.5/drivers/net/tulip/tulip.h 2003-01-17 00:58:24.000000000 -0100
@@ -199,8 +199,8 @@ enum t21041_csr13_bits {
csr13_cac = (1<<2), /* CSR13/14/15 autoconfiguration */
csr13_srl = (1<<0), /* When reset, resets all SIA functions, machines */
- csr13_mask_auibnc = (csr13_eng | csr13_aui | csr13_srl),
- csr13_mask_10bt = (csr13_eng | csr13_srl),
+ csr13_mask_auibnc = (csr13_eng | csr13_aui | csr13_srl | csr13_cac),
+ csr13_mask_10bt = (csr13_eng | csr13_srl | csr13_cac),
};
enum t21143_csr6_bits {
diff -urpN --exclude-from=/home/davej/.exclude linux-2.5.60/drivers/net/tulip/tulip_core.c linux-2.5/drivers/net/tulip/tulip_core.c
--- linux-2.5.60/drivers/net/tulip/tulip_core.c 2003-02-10 17:38:43.000000000 -0100
+++ linux-2.5/drivers/net/tulip/tulip_core.c 2003-01-06 19:06:59.000000000 -0100
@@ -2,7 +2,7 @@
/*
Maintained by Jeff Garzik